SDL API Guide for J721E
sdl_ecc_soc.h
Go to the documentation of this file.
1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2021
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38 #ifndef INCLUDE_SDL_ECC_SOC_H_
39 #define INCLUDE_SDL_ECC_SOC_H_
40 
41 #include <stdint.h>
42 #include <sdl_ecc.h>
43 #include <src/ip/sdl_ip_ecc.h>
44 #include <soc.h>
45 #include <src/sdl/sdl_esm_core.h>
46 #include "ecc/sdl_ecc_priv.h"
47 
48 #define SDL_ECC_WIDTH_UNDEFINED 0x1
49 
50 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
51 #define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
52 #define SDL_MAIN_AC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
53 #define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
54 #define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RAM_IDS_TOTAL_ENTRIES (0U)
55 #define SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES (7U)
56 #define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (32U)
57 #define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
58 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
59 #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES (2U)
60 #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
61 #define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
62 #define SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES (8U)
63 #define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RAM_IDS_TOTAL_ENTRIES (0U)
64 #define SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
65 #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES (8U)
66 #define SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
67 #define SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (68U)
68 #define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (20U)
69 #define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
70 #define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
71 #define SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (7U)
72 #define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
73 #define SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (26U)
74 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
75 #define SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES (7U)
76 #define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
77 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
78 #define SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES (8U)
79 #define SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
80 #define SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (10U)
81 #define SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (34U)
82 #define SDL_MCU_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
83 #define SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES (7U)
84 #define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
85 #define SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
86 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
87 #define SDL_NAVSS0_NBSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
88 #define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
89 #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
90 #define SDL_IDOM1_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
91 #define SDL_IDOM1_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES (0U)
92 #define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
93 #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
94 #define SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES (8U)
95 #define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
96 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
97 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
98 #define SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
99 #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
100 #define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
101 #define SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
102 #define SDL_MCU_I3C1_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
103 #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES (4U)
104 #define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
105 #define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
106 #define SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (14U)
107 #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES (5U)
108 #define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES (0U)
109 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
110 #define SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES (7U)
111 #define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (59U)
112 #define SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
113 #define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
114 #define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
115 #define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
116 #define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
117 #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (24U)
118 #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (24U)
119 #define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
120 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
121 #define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
122 #define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
123 #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
124 #define SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
125 #define SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES (8U)
126 #define SDL_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
127 #define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
128 #define SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
129 #define SDL_MAIN_RC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
130 #define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RAM_IDS_TOTAL_ENTRIES (0U)
131 #define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
132 #define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
133 #define SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U)
134 #define SDL_MAIN_HC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
135 #define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES (0U)
136 #define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES (0U)
137 #define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (2U)
138 #define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
139 #define SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
140 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
141 #define SDL_NAVSS_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (0U)
142 #define SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (28U)
143 #define SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (6U)
144 #define SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (38U)
145 #define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
146 #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
147 #define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
148 #define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
149 #define SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES (3U)
150 #define SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES (15U)
151 #define SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES (1U)
152 #define SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES (1U)
153 #define SDL_WKUP_DMSC0_0_RAM_IDS_TOTAL_ENTRIES (5U)
154 #define SDL_COMPUTE_CLUSTER0_10_RAM_IDS_TOTAL_ENTRIES (4U)
155 #define SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES (20U)
156 
157 
162 static const SDL_MemConfig_t SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
163 {
164  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0xB000000u,
165  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
166  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
167  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0xB002000u,
168  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
169  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
170  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0xB034000u,
171  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
172  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
173  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0xB038000u,
174  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
175  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
176  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0xB010000u,
177  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
178  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
179  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0xB004000u,
180  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
181  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
182  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0xB006000u,
183  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
184  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
185  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0xB00A000u,
186  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
187  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
188  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0xB00C000u,
189  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
190  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
191 };
192 
198 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
199 {
200  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
201  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
202  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
203  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
204  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
205  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
206  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
207  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
208  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
209  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
210  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
211  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
212  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
213  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
214  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
215  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
216  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
217  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
218  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
219  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
220  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
221  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
222  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
223  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
224  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
225  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
226  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
227  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
228  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
229  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
230  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
231  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
232  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
233  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
234  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
235  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
236  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
237  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
238  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
239  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
240  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
241  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
242  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
243  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
244  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
245  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
246  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
247  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
248  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
249  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
250  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
251  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
252  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
253  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
254  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
255  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
256  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
257  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
258  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
259  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
260  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
261  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
262  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
263  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
264  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
265  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
266  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
267  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
268  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
269  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
270  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
271  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
272  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
273  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
274  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
275  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
276  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
277  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
278  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
279  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
280  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
281  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
282 };
283 
289 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
290 {
291  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
292  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
293  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
294  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
295  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
296  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
297  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
298  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
299  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
300  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
301  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
302  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
303  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
304  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
305  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
306  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
307  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
308  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
309  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
310  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
311  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
312  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
313  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
314  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
315  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
316  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
317  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
318  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
319  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
320  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
321  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
322  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
323  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
324  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
325  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
326  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
327  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
328  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
329  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
330  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
331  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
332  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
333  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
334  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
335  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
336  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
337  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
338  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
339  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
340  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
341  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
342  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
343  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
344  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
345  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
346  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
347  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
348  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
349  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
350  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
351  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
352  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
353  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
354  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
355  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
356  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
357  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
358  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
359  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
360  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
361  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
362  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
363  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
364  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
365  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
366  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
367  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
368  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
369  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
370  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
371  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
372  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
373 };
374 
380 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
381 {
382  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
383  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
384  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
385  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
386  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
387  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
388  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
389  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
390  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
391  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
392  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
393  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
394  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
395  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
396  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
397  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
398  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
399  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
400  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
401  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
402  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
403  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
404  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
405  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
406  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
407  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
408  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
409  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
410  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
411  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
412  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
413  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
414  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
415  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
416  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
417  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
418  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
419  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
420  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
421  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
422  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
423  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
424  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
425  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
426  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
427  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
428  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
429  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
430  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
431  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
432  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
433  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
434  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
435  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
436  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
437  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
438  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
439  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
440  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
441  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
442  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
443  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
444  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
445  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
446  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
447  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
448  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
449  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
450  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
451  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
452  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
453  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
454  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
455  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
456  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
457  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
458  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
459  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
460  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
461  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
462  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
463  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
464 };
465 
471 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
472 {
473  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
474  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
475  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
476  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
477  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
478  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
479  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
480  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
481  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
482  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
483  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
484  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
485  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
486  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
487  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
488  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
489  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
490  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
491  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
492  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
493  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
494  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
495  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
496  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
497  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
498  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
499  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
500  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
501  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
502  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
503  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
504  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
505  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
506  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
507  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
508  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
509  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
510  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
511  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
512  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
513  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
514  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
515  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
516  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
517  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
518  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
519  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
520  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
521  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
522  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
523  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
524  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
525  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
526  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
527  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
528  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
529  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
530  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
531  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
532  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
533  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
534  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
535  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
536  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
537  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
538  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
539  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
540  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
541  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
542  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
543  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
544  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
545  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
546  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
547  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
548  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
549  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
550  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
551  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
552  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
553  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
554  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
555 };
556 
562 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
563 {
564  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
565  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
566  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
567  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
568  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
569  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
570  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
571  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
572  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
573  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
574  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
575  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
576  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
577  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
578  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
579  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
580  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
581  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
582  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
583  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
584  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
585  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
586  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
587  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
588  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
589  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
590  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
591  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
592  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
593  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
594  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
595  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
596  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
597  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
598  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
599  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
600  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
601  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
602  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
603  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
604  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
605  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
606  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
607  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
608  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
609  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
610  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
611  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
612  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
613  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
614  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
615  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
616  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
617  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
618  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
619  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
620  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
621  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
622  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
623  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
624  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
625  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
626  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
627  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
628  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
629  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
630  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
631  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
632  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
633  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
634  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
635  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
636  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
637  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
638  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
639  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
640  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
641  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
642  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
643  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
644  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
645  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
646 };
647 
653 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS] =
654 {
655  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_0_CHECKER_TYPE,
656  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_0_WIDTH },
657  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_1_CHECKER_TYPE,
658  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_1_WIDTH },
659  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_2_CHECKER_TYPE,
660  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_2_WIDTH },
661  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_3_CHECKER_TYPE,
662  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_3_WIDTH },
663  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_4_CHECKER_TYPE,
664  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_4_WIDTH },
665  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_5_CHECKER_TYPE,
666  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_5_WIDTH },
667  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_6_CHECKER_TYPE,
668  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_6_WIDTH },
669  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_7_CHECKER_TYPE,
670  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_7_WIDTH },
671  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_8_CHECKER_TYPE,
672  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_8_WIDTH },
673  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_9_CHECKER_TYPE,
674  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_9_WIDTH },
675  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_10_CHECKER_TYPE,
676  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_10_WIDTH },
677  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_11_CHECKER_TYPE,
678  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_11_WIDTH },
679  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_12_CHECKER_TYPE,
680  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_12_WIDTH },
681  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_13_CHECKER_TYPE,
682  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_13_WIDTH },
683  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_14_CHECKER_TYPE,
684  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_14_WIDTH },
685  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_15_CHECKER_TYPE,
686  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_15_WIDTH },
687  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_16_CHECKER_TYPE,
688  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_16_WIDTH },
689  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_17_CHECKER_TYPE,
690  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_17_WIDTH },
691  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_18_CHECKER_TYPE,
692  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_18_WIDTH },
693  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_19_CHECKER_TYPE,
694  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_19_WIDTH },
695  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_20_CHECKER_TYPE,
696  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_20_WIDTH },
697  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_21_CHECKER_TYPE,
698  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_21_WIDTH },
699  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_22_CHECKER_TYPE,
700  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_22_WIDTH },
701  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_23_CHECKER_TYPE,
702  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_23_WIDTH },
703  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_24_CHECKER_TYPE,
704  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_24_WIDTH },
705  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_25_CHECKER_TYPE,
706  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_25_WIDTH },
707  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_26_CHECKER_TYPE,
708  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_26_WIDTH },
709  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_27_CHECKER_TYPE,
710  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_27_WIDTH },
711  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_28_CHECKER_TYPE,
712  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_28_WIDTH },
713  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_29_CHECKER_TYPE,
714  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_29_WIDTH },
715  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_30_CHECKER_TYPE,
716  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_30_WIDTH },
717  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_31_CHECKER_TYPE,
718  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_31_WIDTH },
719  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_32_CHECKER_TYPE,
720  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_32_WIDTH },
721  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_33_CHECKER_TYPE,
722  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_33_WIDTH },
723  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_34_CHECKER_TYPE,
724  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_34_WIDTH },
725  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_35_CHECKER_TYPE,
726  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_35_WIDTH },
727  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_36_CHECKER_TYPE,
728  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_36_WIDTH },
729  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_37_CHECKER_TYPE,
730  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_37_WIDTH },
731  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_38_CHECKER_TYPE,
732  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_38_WIDTH },
733  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_39_CHECKER_TYPE,
734  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_39_WIDTH },
735  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_40_CHECKER_TYPE,
736  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_40_WIDTH },
737  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_41_CHECKER_TYPE,
738  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_41_WIDTH },
739  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_42_CHECKER_TYPE,
740  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_42_WIDTH },
741  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_43_CHECKER_TYPE,
742  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_43_WIDTH },
743  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_44_CHECKER_TYPE,
744  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_44_WIDTH },
745  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_45_CHECKER_TYPE,
746  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_45_WIDTH },
747  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_46_CHECKER_TYPE,
748  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_46_WIDTH },
749  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_47_CHECKER_TYPE,
750  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_47_WIDTH },
751  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_48_CHECKER_TYPE,
752  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_48_WIDTH },
753  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_49_CHECKER_TYPE,
754  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_49_WIDTH },
755  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_50_CHECKER_TYPE,
756  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_50_WIDTH },
757  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_51_CHECKER_TYPE,
758  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_51_WIDTH },
759  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_52_CHECKER_TYPE,
760  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_52_WIDTH },
761  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_53_CHECKER_TYPE,
762  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_53_WIDTH },
763  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_54_CHECKER_TYPE,
764  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_54_WIDTH },
765  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_55_CHECKER_TYPE,
766  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_55_WIDTH },
767  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_56_CHECKER_TYPE,
768  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_56_WIDTH },
769  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_57_CHECKER_TYPE,
770  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_57_WIDTH },
771  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_58_CHECKER_TYPE,
772  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_58_WIDTH },
773  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_59_CHECKER_TYPE,
774  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_59_WIDTH },
775  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_60_CHECKER_TYPE,
776  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_60_WIDTH },
777  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_61_CHECKER_TYPE,
778  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_61_WIDTH },
779  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_62_CHECKER_TYPE,
780  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_62_WIDTH },
781  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_63_CHECKER_TYPE,
782  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_63_WIDTH },
783  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_64_CHECKER_TYPE,
784  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_64_WIDTH },
785  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_65_CHECKER_TYPE,
786  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_65_WIDTH },
787  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_66_CHECKER_TYPE,
788  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_66_WIDTH },
789  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_67_CHECKER_TYPE,
790  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_67_WIDTH },
791  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_68_CHECKER_TYPE,
792  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_68_WIDTH },
793  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_69_CHECKER_TYPE,
794  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_69_WIDTH },
795  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_70_CHECKER_TYPE,
796  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_70_WIDTH },
797  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_71_CHECKER_TYPE,
798  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_71_WIDTH },
799  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_72_CHECKER_TYPE,
800  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_72_WIDTH },
801  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_73_CHECKER_TYPE,
802  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_73_WIDTH },
803  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_74_CHECKER_TYPE,
804  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_74_WIDTH },
805  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_75_CHECKER_TYPE,
806  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_75_WIDTH },
807  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_76_CHECKER_TYPE,
808  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_76_WIDTH },
809  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_77_CHECKER_TYPE,
810  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_77_WIDTH },
811  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_78_CHECKER_TYPE,
812  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_78_WIDTH },
813  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_79_CHECKER_TYPE,
814  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_79_WIDTH },
815  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_80_CHECKER_TYPE,
816  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_80_WIDTH },
817  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_81_CHECKER_TYPE,
818  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_81_WIDTH },
819  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_82_CHECKER_TYPE,
820  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_82_WIDTH },
821  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_83_CHECKER_TYPE,
822  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_83_WIDTH },
823  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_84_CHECKER_TYPE,
824  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_84_WIDTH },
825  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_85_CHECKER_TYPE,
826  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_85_WIDTH },
827  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_86_CHECKER_TYPE,
828  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_86_WIDTH },
829  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_87_CHECKER_TYPE,
830  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_87_WIDTH },
831  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_88_CHECKER_TYPE,
832  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_88_WIDTH },
833  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_89_CHECKER_TYPE,
834  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_89_WIDTH },
835  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_90_CHECKER_TYPE,
836  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_90_WIDTH },
837  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_91_CHECKER_TYPE,
838  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_91_WIDTH },
839  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_92_CHECKER_TYPE,
840  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_92_WIDTH },
841  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_93_CHECKER_TYPE,
842  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_93_WIDTH },
843  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_94_CHECKER_TYPE,
844  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_94_WIDTH },
845  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_95_CHECKER_TYPE,
846  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_95_WIDTH },
847  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_96_CHECKER_TYPE,
848  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_96_WIDTH },
849  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_97_CHECKER_TYPE,
850  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_97_WIDTH },
851  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_98_CHECKER_TYPE,
852  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_98_WIDTH },
853  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_99_CHECKER_TYPE,
854  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_99_WIDTH },
855  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_100_CHECKER_TYPE,
856  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_100_WIDTH },
857  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_101_CHECKER_TYPE,
858  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_101_WIDTH },
859  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_102_CHECKER_TYPE,
860  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_102_WIDTH },
861  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_103_CHECKER_TYPE,
862  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_103_WIDTH },
863  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_104_CHECKER_TYPE,
864  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_104_WIDTH },
865  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_105_CHECKER_TYPE,
866  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_105_WIDTH },
867  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_106_CHECKER_TYPE,
868  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_106_WIDTH },
869  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_107_CHECKER_TYPE,
870  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_107_WIDTH },
871  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_108_CHECKER_TYPE,
872  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_108_WIDTH },
873  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_109_CHECKER_TYPE,
874  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_109_WIDTH },
875  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_110_CHECKER_TYPE,
876  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_110_WIDTH },
877  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_111_CHECKER_TYPE,
878  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_111_WIDTH },
879  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_112_CHECKER_TYPE,
880  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_112_WIDTH },
881  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_113_CHECKER_TYPE,
882  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_113_WIDTH },
883  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_114_CHECKER_TYPE,
884  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_114_WIDTH },
885  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_115_CHECKER_TYPE,
886  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_115_WIDTH },
887  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_116_CHECKER_TYPE,
888  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_116_WIDTH },
889  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_117_CHECKER_TYPE,
890  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_117_WIDTH },
891  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_118_CHECKER_TYPE,
892  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_118_WIDTH },
893  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_119_CHECKER_TYPE,
894  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_119_WIDTH },
895  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_120_CHECKER_TYPE,
896  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_120_WIDTH },
897  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_121_CHECKER_TYPE,
898  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_121_WIDTH },
899  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_122_CHECKER_TYPE,
900  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_122_WIDTH },
901  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_123_CHECKER_TYPE,
902  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_123_WIDTH },
903  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_124_CHECKER_TYPE,
904  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_124_WIDTH },
905  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_125_CHECKER_TYPE,
906  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_125_WIDTH },
907  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_126_CHECKER_TYPE,
908  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_126_WIDTH },
909  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_127_CHECKER_TYPE,
910  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_127_WIDTH },
911  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_128_CHECKER_TYPE,
912  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_128_WIDTH },
913  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_129_CHECKER_TYPE,
914  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_129_WIDTH },
915  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_130_CHECKER_TYPE,
916  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_130_WIDTH },
917  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_131_CHECKER_TYPE,
918  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_131_WIDTH },
919  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_132_CHECKER_TYPE,
920  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_132_WIDTH },
921  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_133_CHECKER_TYPE,
922  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_133_WIDTH },
923  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_134_CHECKER_TYPE,
924  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_134_WIDTH },
925  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_135_CHECKER_TYPE,
926  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_135_WIDTH },
927  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_136_CHECKER_TYPE,
928  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_136_WIDTH },
929  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_137_CHECKER_TYPE,
930  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_137_WIDTH },
931  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_138_CHECKER_TYPE,
932  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_138_WIDTH },
933  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_139_CHECKER_TYPE,
934  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_139_WIDTH },
935  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_140_CHECKER_TYPE,
936  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_140_WIDTH },
937  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_141_CHECKER_TYPE,
938  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_141_WIDTH },
939  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_142_CHECKER_TYPE,
940  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_142_WIDTH },
941  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_143_CHECKER_TYPE,
942  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_143_WIDTH },
943  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_144_CHECKER_TYPE,
944  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_144_WIDTH },
945  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_145_CHECKER_TYPE,
946  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_145_WIDTH },
947  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_146_CHECKER_TYPE,
948  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_146_WIDTH },
949  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_147_CHECKER_TYPE,
950  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_147_WIDTH },
951  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_148_CHECKER_TYPE,
952  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_148_WIDTH },
953  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_149_CHECKER_TYPE,
954  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_149_WIDTH },
955  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_150_CHECKER_TYPE,
956  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_150_WIDTH },
957  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_151_CHECKER_TYPE,
958  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_151_WIDTH },
959  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_152_CHECKER_TYPE,
960  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_152_WIDTH },
961  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_153_CHECKER_TYPE,
962  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_153_WIDTH },
963  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_154_CHECKER_TYPE,
964  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_154_WIDTH },
965  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_155_CHECKER_TYPE,
966  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_155_WIDTH },
967  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_156_CHECKER_TYPE,
968  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_156_WIDTH },
969  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_157_CHECKER_TYPE,
970  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_157_WIDTH },
971  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_158_CHECKER_TYPE,
972  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_158_WIDTH },
973  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_159_CHECKER_TYPE,
974  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_159_WIDTH },
975  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_160_CHECKER_TYPE,
976  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_160_WIDTH },
977  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_161_CHECKER_TYPE,
978  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_161_WIDTH },
979  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_162_CHECKER_TYPE,
980  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_162_WIDTH },
981  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_163_CHECKER_TYPE,
982  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_163_WIDTH },
983  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_164_CHECKER_TYPE,
984  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_164_WIDTH },
985  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_165_CHECKER_TYPE,
986  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_165_WIDTH },
987  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_166_CHECKER_TYPE,
988  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_166_WIDTH },
989  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_167_CHECKER_TYPE,
990  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_167_WIDTH },
991  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_168_CHECKER_TYPE,
992  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_168_WIDTH },
993  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_169_CHECKER_TYPE,
994  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_169_WIDTH },
995  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_170_CHECKER_TYPE,
996  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_170_WIDTH },
997  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_171_CHECKER_TYPE,
998  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_171_WIDTH },
999  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_172_CHECKER_TYPE,
1000  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_172_WIDTH },
1001  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_173_CHECKER_TYPE,
1002  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_173_WIDTH },
1003  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_174_CHECKER_TYPE,
1004  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_174_WIDTH },
1005  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_175_CHECKER_TYPE,
1006  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_GROUP_175_WIDTH },
1007 };
1008 
1014 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
1015 {
1016  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
1017  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
1018  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
1019  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
1020  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
1021  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
1022  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
1023  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
1024  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
1025  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
1026  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
1027  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
1028  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
1029  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
1030  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
1031  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
1032  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
1033  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
1034  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
1035  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
1036  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
1037  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
1038  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
1039  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
1040  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
1041  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
1042  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
1043  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
1044  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
1045  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
1046 };
1047 
1053 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
1054 {
1055  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
1056  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
1057  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
1058  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
1059  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
1060  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
1061  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
1062  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
1063 };
1064 
1070 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
1071 {
1072  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
1073  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
1074  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
1075  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
1076  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
1077  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
1078  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
1079  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
1080  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
1081  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
1082  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
1083  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
1084  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
1085  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
1086  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
1087  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
1088  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
1089  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
1090  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
1091  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
1092  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
1093  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
1094  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
1095  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
1096  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
1097  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
1098  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
1099  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
1100  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
1101  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
1102  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
1103  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
1104  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
1105  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
1106  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
1107  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
1108  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
1109  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
1110  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
1111  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
1112  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
1113  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
1114  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
1115  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
1116 };
1117 
1123 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
1124 {
1125  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
1126  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
1127  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
1128  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
1129  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
1130  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
1131  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
1132  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
1133  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
1134  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
1135  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
1136  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
1137  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
1138  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
1139  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
1140  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
1141  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
1142  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
1143  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
1144  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
1145  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
1146  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
1147  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
1148  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
1149  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
1150  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
1151  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
1152  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
1153  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
1154  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
1155  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
1156  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
1157  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
1158  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
1159  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
1160  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
1161  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
1162  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
1163  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
1164  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
1165  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
1166  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
1167  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
1168  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
1169  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
1170  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
1171  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
1172  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
1173  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
1174  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
1175  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
1176  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
1177  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
1178  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
1179  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
1180  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
1181  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
1182  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
1183  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
1184  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
1185  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
1186  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
1187  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
1188  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
1189  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
1190  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
1191  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
1192  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
1193  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
1194  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
1195  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
1196  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
1197  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
1198  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
1199  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
1200  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
1201  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
1202  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
1203  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
1204  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
1205  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
1206  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
1207  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
1208  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
1209  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
1210  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
1211  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
1212  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
1213  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
1214  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
1215  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
1216  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
1217  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
1218  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
1219  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
1220  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
1221  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
1222  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
1223  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
1224  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
1225  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
1226  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
1227  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
1228  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
1229  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
1230  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
1231  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
1232  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
1233  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
1234  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
1235  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
1236  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
1237  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
1238  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
1239  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
1240  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
1241  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
1242  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
1243  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
1244  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
1245  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
1246  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
1247  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
1248  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
1249  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
1250  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
1251  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
1252  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
1253  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
1254  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
1255  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
1256  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
1257  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
1258  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
1259  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
1260  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
1261  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
1262  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
1263  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
1264  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
1265  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
1266  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
1267  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
1268  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
1269  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
1270  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
1271  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
1272  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
1273  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
1274  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
1275  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
1276  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
1277  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
1278  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
1279  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
1280  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
1281  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
1282  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
1283  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
1284  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
1285  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
1286  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
1287  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
1288  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
1289  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
1290  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
1291  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
1292  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
1293  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
1294  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
1295  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
1296  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
1297  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
1298  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
1299  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
1300  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
1301  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
1302  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
1303  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
1304  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
1305  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
1306  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
1307  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
1308  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
1309  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
1310  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
1311  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
1312  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
1313  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
1314  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
1315  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
1316  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
1317  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
1318  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
1319  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
1320  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
1321  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
1322  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
1323  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
1324  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
1325 };
1326 
1332 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1333 {
1334  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1335  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1336  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1337  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1338  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1339  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1340  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1341  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1342  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1343  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1344  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1345  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1346  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1347  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1348  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1349  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1350  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1351  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1352  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1353  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1354  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1355  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1356  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1357  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1358  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1359  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1360  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1361  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1362  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1363  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1364  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1365  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1366  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1367  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1368  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1369  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1370  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1371  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1372  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1373  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1374  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1375  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1376  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1377  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1378  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1379  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1380  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1381  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1382  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1383  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1384  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1385  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1386  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1387  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1388  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1389  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1390  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1391  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1392  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1393  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1394  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1395  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1396  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1397  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1398  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1399  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1400  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1401  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1402  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1403  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1404  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1405  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1406  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1407  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1408  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1409  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1410  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1411  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1412  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1413  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1414  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1415  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1416  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1417  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1418  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1419  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1420  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1421  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1422  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1423  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1424  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1425  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1426  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1427  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1428  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1429  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1430  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1431  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1432  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1433  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1434  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1435  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1436  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1437  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1438  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1439  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1440  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1441  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1442  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1443  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1444  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1445  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1446  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1447  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1448  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1449  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1450  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1451  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1452  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1453  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1454  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1455  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1456  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1457  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1458  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1459  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1460  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1461  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1462  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1463  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1464  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1465  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1466  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1467  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
1468  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
1469  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
1470  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
1471  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
1472  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
1473  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
1474  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
1475  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
1476  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
1477  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
1478  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
1479  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
1480  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
1481  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
1482  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
1483  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
1484  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
1485  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
1486  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
1487  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
1488  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
1489  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
1490  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
1491  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
1492  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
1493  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
1494  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
1495  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
1496  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
1497  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
1498  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
1499  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
1500  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
1501  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
1502  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
1503  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
1504  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
1505  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
1506  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
1507  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
1508  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
1509  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
1510  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
1511  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
1512  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
1513  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
1514  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
1515  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
1516  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
1517  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
1518  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
1519  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
1520  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
1521  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
1522  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
1523  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
1524  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
1525  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
1526  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
1527  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
1528  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
1529  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
1530  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
1531  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
1532  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
1533  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
1534  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
1535  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
1536  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
1537  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
1538  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
1539  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
1540  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
1541  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
1542  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
1543  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
1544  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
1545  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
1546  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
1547  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
1548  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
1549  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
1550  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
1551  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
1552  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
1553  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
1554  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
1555  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
1556  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
1557  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
1558  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
1559  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
1560  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
1561  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
1562  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
1563  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
1564  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
1565  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
1566  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
1567  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
1568  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
1569  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
1570  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
1571  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
1572  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
1573  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
1574  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
1575  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
1576  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
1577  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
1578  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
1579  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
1580  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
1581  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
1582  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
1583  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
1584  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
1585  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
1586  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
1587  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
1588  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
1589  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
1590  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
1591  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
1592  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
1593  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
1594  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
1595  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
1596 };
1597 
1603 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1604 {
1605  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1606  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1607  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1608  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1609  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1610  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1611  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1612  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1613  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1614  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1615 };
1616 
1622 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
1623 {
1624  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
1625  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
1626  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
1627  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
1628  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
1629  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
1630 };
1631 
1637 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
1638 {
1639  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
1640  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
1641  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
1642  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
1643  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
1644  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
1645  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
1646  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
1647  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
1648  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
1649  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
1650  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
1651  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
1652  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
1653  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
1654  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
1655  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
1656  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
1657  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
1658  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
1659  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
1660  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
1661  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
1662  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
1663  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
1664  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
1665  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
1666  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
1667  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
1668  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
1669 };
1670 
1676 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
1677 {
1678  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
1679  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
1680  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
1681  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
1682  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
1683  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
1684  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
1685  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
1686 };
1687 
1693 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1694 {
1695  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1696  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1697  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1698  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1699  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1700  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1701  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1702  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1703  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1704  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1705  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1706  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1707  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1708  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1709  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1710  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1711  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1712  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1713  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1714  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1715  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1716  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1717  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1718  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1719  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1720  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1721  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1722  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1723  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1724  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1725  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1726  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1727  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1728  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1729  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1730  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1731  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1732  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1733  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1734  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1735  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1736  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1737  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1738  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1739  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1740  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1741  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1742  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1743  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1744  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1745  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1746  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1747  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1748  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1749  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1750  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1751  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1752  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1753  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1754  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1755  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1756  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1757  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1758  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1759  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1760  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1761  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1762  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1763  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1764  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1765  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1766  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1767  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1768  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1769  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1770  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1771  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1772  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1773  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1774  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1775  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1776  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1777  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1778  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1779 };
1780 
1786 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1787 {
1788  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1789  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1790  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1791  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1792  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1793  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1794  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1795  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1796  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1797  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1798  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1799  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1800  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1801  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1802  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1803  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1804  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1805  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1806  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1807  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1808  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1809  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1810  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1811  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1812  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1813  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1814  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1815  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1816  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1817  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1818  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1819  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1820  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1821  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1822  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1823  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1824  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1825  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1826  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1827  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1828  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1829  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1830  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1831  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1832  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1833  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1834  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1835  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1836  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1837  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1838  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1839  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1840  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1841  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1842  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1843  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1844  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1845  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1846  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1847  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1848  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1849  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1850  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1851  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1852  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1853  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1854  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1855  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1856  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1857  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1858  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1859  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1860  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1861  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1862  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1863  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1864  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1865  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1866  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1867  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1868  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1869  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1870  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1871  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1872  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1873  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1874  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1875  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1876  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1877  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1878  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1879  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1880  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1881  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1882  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1883  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1884 };
1885 
1891 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1892 {
1893  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1894  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1895  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1896  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1897  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1898  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1899  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1900  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1901  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1902  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1903  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1904  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1905  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1906  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1907  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1908  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1909  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1910  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1911  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1912  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1913  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1914  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1915  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1916  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1917  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1918  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1919  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1920  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1921  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1922  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1923  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1924  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1925  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1926  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1927  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1928  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1929  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1930  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1931  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1932  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1933  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1934  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1935  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1936  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1937  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1938  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1939  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1940  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1941  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1942  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1943  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1944  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1945  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1946  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1947  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1948  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1949  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1950  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1951  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1952  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1953  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1954  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1955  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1956  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1957  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1958  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1959  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1960  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1961  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1962  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1963  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1964  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1965  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1966  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1967  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1968  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1969  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1970  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1971  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1972  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1973  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1974  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1975  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1976  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1977  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1978  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1979  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1980  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1981  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1982  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1983  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1984  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1985  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1986  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1987  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1988  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1989 };
1990 
1996 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
1997 {
1998  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1999  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2000  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2001  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2002  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2003  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2004  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2005  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2006  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2007  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2008  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2009  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2010  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2011  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2012  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2013  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2014  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2015  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2016  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2017  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2018  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2019  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2020  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2021  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2022  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2023  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2024  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2025  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2026  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2027  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2028  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
2029  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
2030  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
2031  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
2032  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
2033  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
2034  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
2035  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
2036  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
2037  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
2038  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
2039  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
2040  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
2041  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
2042  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
2043  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
2044  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
2045  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
2046  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
2047  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
2048  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
2049  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
2050  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
2051  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
2052  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
2053  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
2054  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
2055  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
2056  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
2057  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
2058  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
2059  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
2060  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
2061  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
2062  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
2063  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
2064  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
2065  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
2066  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
2067  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
2068  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
2069  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
2070  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
2071  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
2072  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
2073  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
2074  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
2075  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
2076  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
2077  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
2078  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
2079  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
2080  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
2081  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
2082  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
2083  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
2084  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
2085  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
2086  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
2087  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
2088  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
2089  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
2090  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
2091  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
2092  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
2093  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
2094 };
2095 
2101 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
2102 {
2103  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
2104  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2105  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2106  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2107  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2108  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2109  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2110  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2111  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2112  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2113  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2114  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2115  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2116  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2117  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2118  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2119  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2120  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2121  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2122  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2123  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2124  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2125  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2126  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2127  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2128  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2129  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2130  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2131  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2132  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2133  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
2134  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
2135  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
2136  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
2137  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
2138  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
2139  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
2140  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
2141  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
2142  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
2143  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
2144  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
2145  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
2146  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
2147  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
2148  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
2149  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
2150  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
2151  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
2152  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
2153  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
2154  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
2155  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
2156  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
2157  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
2158  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
2159  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
2160  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
2161  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
2162  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
2163  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
2164  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
2165  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
2166  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
2167  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
2168  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
2169  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
2170  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
2171  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
2172  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
2173  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
2174  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
2175  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
2176  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
2177  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
2178  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
2179  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
2180  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
2181  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
2182  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
2183  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
2184  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
2185  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
2186  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
2187  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
2188  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
2189  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
2190  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
2191  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
2192  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
2193  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
2194  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
2195  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
2196  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
2197  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
2198  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
2199 };
2200 
2206 static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
2207 {
2208  { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2209  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
2210  { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
2211  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
2212  { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
2213  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
2214  { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
2215  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
2216  { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
2217  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
2218  { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
2219  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
2220 };
2221 
2226 static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
2227 {
2228  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_ID, 0x200000u,
2229  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_SIZE, 4u,
2230  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
2231 };
2232 
2238 static const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
2239 {
2240  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
2241  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
2242  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
2243  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
2244  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
2245  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
2246  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
2247  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
2248  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
2249  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
2250  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
2251  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
2252  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
2253  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
2254  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
2255  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
2256  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
2257  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
2258  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
2259  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
2260  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
2261  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
2262  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
2263  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
2264  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
2265  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
2266  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
2267  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
2268  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
2269  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
2270  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
2271  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
2272  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
2273  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
2274 };
2275 
2281 static const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_MAX_NUM_CHECKERS] =
2282 {
2283  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
2284  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_0_WIDTH },
2285  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
2286  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_1_WIDTH },
2287  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
2288  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_2_WIDTH },
2289  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
2290  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_3_WIDTH },
2291  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
2292  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_4_WIDTH },
2293  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
2294  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_GROUP_5_WIDTH },
2295 };
2296 
2302 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS] =
2303 {
2304  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_0_CHECKER_TYPE,
2305  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_0_WIDTH },
2306  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_1_CHECKER_TYPE,
2307  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_1_WIDTH },
2308  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_2_CHECKER_TYPE,
2309  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_2_WIDTH },
2310  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_3_CHECKER_TYPE,
2311  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_3_WIDTH },
2312  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_4_CHECKER_TYPE,
2313  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_4_WIDTH },
2314  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_5_CHECKER_TYPE,
2315  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_5_WIDTH },
2316  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_6_CHECKER_TYPE,
2317  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_6_WIDTH },
2318  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_7_CHECKER_TYPE,
2319  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_7_WIDTH },
2320  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_8_CHECKER_TYPE,
2321  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_8_WIDTH },
2322  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_9_CHECKER_TYPE,
2323  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_9_WIDTH },
2324  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_10_CHECKER_TYPE,
2325  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_10_WIDTH },
2326  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_11_CHECKER_TYPE,
2327  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_11_WIDTH },
2328  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_12_CHECKER_TYPE,
2329  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_12_WIDTH },
2330  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_13_CHECKER_TYPE,
2331  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_13_WIDTH },
2332  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_14_CHECKER_TYPE,
2333  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_14_WIDTH },
2334  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_15_CHECKER_TYPE,
2335  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_15_WIDTH },
2336  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_16_CHECKER_TYPE,
2337  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_16_WIDTH },
2338  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_17_CHECKER_TYPE,
2339  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_17_WIDTH },
2340  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_18_CHECKER_TYPE,
2341  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_18_WIDTH },
2342  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_19_CHECKER_TYPE,
2343  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_19_WIDTH },
2344  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_20_CHECKER_TYPE,
2345  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_20_WIDTH },
2346  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_21_CHECKER_TYPE,
2347  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_21_WIDTH },
2348  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_22_CHECKER_TYPE,
2349  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_22_WIDTH },
2350  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_23_CHECKER_TYPE,
2351  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_23_WIDTH },
2352  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_24_CHECKER_TYPE,
2353  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_24_WIDTH },
2354  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_25_CHECKER_TYPE,
2355  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_25_WIDTH },
2356  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_26_CHECKER_TYPE,
2357  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_26_WIDTH },
2358  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_27_CHECKER_TYPE,
2359  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_27_WIDTH },
2360  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_28_CHECKER_TYPE,
2361  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_28_WIDTH },
2362  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_29_CHECKER_TYPE,
2363  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_29_WIDTH },
2364  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_30_CHECKER_TYPE,
2365  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_30_WIDTH },
2366  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_31_CHECKER_TYPE,
2367  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_31_WIDTH },
2368  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_32_CHECKER_TYPE,
2369  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_32_WIDTH },
2370  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_33_CHECKER_TYPE,
2371  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_33_WIDTH },
2372  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_34_CHECKER_TYPE,
2373  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_34_WIDTH },
2374  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_35_CHECKER_TYPE,
2375  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_35_WIDTH },
2376  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_36_CHECKER_TYPE,
2377  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_36_WIDTH },
2378  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_37_CHECKER_TYPE,
2379  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_37_WIDTH },
2380  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_38_CHECKER_TYPE,
2381  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_38_WIDTH },
2382  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_39_CHECKER_TYPE,
2383  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_39_WIDTH },
2384  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_40_CHECKER_TYPE,
2385  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_40_WIDTH },
2386  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_41_CHECKER_TYPE,
2387  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_41_WIDTH },
2388  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_42_CHECKER_TYPE,
2389  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_42_WIDTH },
2390  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_43_CHECKER_TYPE,
2391  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_43_WIDTH },
2392  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_44_CHECKER_TYPE,
2393  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_44_WIDTH },
2394  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_45_CHECKER_TYPE,
2395  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_45_WIDTH },
2396  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_46_CHECKER_TYPE,
2397  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_46_WIDTH },
2398  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_47_CHECKER_TYPE,
2399  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_47_WIDTH },
2400  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_48_CHECKER_TYPE,
2401  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_48_WIDTH },
2402  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_49_CHECKER_TYPE,
2403  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_49_WIDTH },
2404  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_50_CHECKER_TYPE,
2405  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_50_WIDTH },
2406  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_51_CHECKER_TYPE,
2407  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_51_WIDTH },
2408  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_52_CHECKER_TYPE,
2409  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_52_WIDTH },
2410  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_53_CHECKER_TYPE,
2411  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_53_WIDTH },
2412  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_54_CHECKER_TYPE,
2413  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_54_WIDTH },
2414  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_55_CHECKER_TYPE,
2415  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_55_WIDTH },
2416  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_56_CHECKER_TYPE,
2417  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_56_WIDTH },
2418  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_57_CHECKER_TYPE,
2419  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_57_WIDTH },
2420  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_58_CHECKER_TYPE,
2421  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_58_WIDTH },
2422  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_59_CHECKER_TYPE,
2423  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_59_WIDTH },
2424  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_60_CHECKER_TYPE,
2425  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_60_WIDTH },
2426  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_61_CHECKER_TYPE,
2427  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_61_WIDTH },
2428  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_62_CHECKER_TYPE,
2429  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_62_WIDTH },
2430  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_63_CHECKER_TYPE,
2431  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_63_WIDTH },
2432  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_64_CHECKER_TYPE,
2433  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_64_WIDTH },
2434  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_65_CHECKER_TYPE,
2435  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_65_WIDTH },
2436  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_66_CHECKER_TYPE,
2437  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_66_WIDTH },
2438  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_67_CHECKER_TYPE,
2439  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_67_WIDTH },
2440  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_68_CHECKER_TYPE,
2441  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_68_WIDTH },
2442  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_69_CHECKER_TYPE,
2443  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_69_WIDTH },
2444  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_70_CHECKER_TYPE,
2445  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_70_WIDTH },
2446  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_71_CHECKER_TYPE,
2447  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_71_WIDTH },
2448  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_72_CHECKER_TYPE,
2449  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_72_WIDTH },
2450  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_73_CHECKER_TYPE,
2451  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_73_WIDTH },
2452  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_74_CHECKER_TYPE,
2453  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_74_WIDTH },
2454  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_75_CHECKER_TYPE,
2455  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_75_WIDTH },
2456  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_76_CHECKER_TYPE,
2457  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_76_WIDTH },
2458  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_77_CHECKER_TYPE,
2459  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_77_WIDTH },
2460  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_78_CHECKER_TYPE,
2461  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_78_WIDTH },
2462  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_79_CHECKER_TYPE,
2463  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_79_WIDTH },
2464  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_80_CHECKER_TYPE,
2465  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_80_WIDTH },
2466  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_81_CHECKER_TYPE,
2467  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_81_WIDTH },
2468  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_82_CHECKER_TYPE,
2469  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_82_WIDTH },
2470  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_83_CHECKER_TYPE,
2471  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_83_WIDTH },
2472  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_84_CHECKER_TYPE,
2473  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_84_WIDTH },
2474  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_85_CHECKER_TYPE,
2475  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_85_WIDTH },
2476  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_86_CHECKER_TYPE,
2477  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_86_WIDTH },
2478  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_87_CHECKER_TYPE,
2479  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_87_WIDTH },
2480  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_88_CHECKER_TYPE,
2481  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_88_WIDTH },
2482  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_89_CHECKER_TYPE,
2483  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_89_WIDTH },
2484  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_90_CHECKER_TYPE,
2485  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_90_WIDTH },
2486  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_91_CHECKER_TYPE,
2487  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_91_WIDTH },
2488  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_92_CHECKER_TYPE,
2489  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_92_WIDTH },
2490  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_93_CHECKER_TYPE,
2491  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_93_WIDTH },
2492  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_94_CHECKER_TYPE,
2493  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_94_WIDTH },
2494  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_95_CHECKER_TYPE,
2495  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_95_WIDTH },
2496  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_96_CHECKER_TYPE,
2497  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_96_WIDTH },
2498  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_97_CHECKER_TYPE,
2499  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_97_WIDTH },
2500  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_98_CHECKER_TYPE,
2501  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_98_WIDTH },
2502  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_99_CHECKER_TYPE,
2503  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_99_WIDTH },
2504  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_100_CHECKER_TYPE,
2505  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_100_WIDTH },
2506  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_101_CHECKER_TYPE,
2507  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_101_WIDTH },
2508  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_102_CHECKER_TYPE,
2509  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_102_WIDTH },
2510  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_103_CHECKER_TYPE,
2511  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_103_WIDTH },
2512  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_104_CHECKER_TYPE,
2513  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_104_WIDTH },
2514  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_105_CHECKER_TYPE,
2515  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_105_WIDTH },
2516  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_106_CHECKER_TYPE,
2517  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_106_WIDTH },
2518  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_107_CHECKER_TYPE,
2519  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_107_WIDTH },
2520  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_108_CHECKER_TYPE,
2521  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_108_WIDTH },
2522  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_109_CHECKER_TYPE,
2523  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_109_WIDTH },
2524  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_110_CHECKER_TYPE,
2525  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_110_WIDTH },
2526  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_111_CHECKER_TYPE,
2527  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_111_WIDTH },
2528  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_112_CHECKER_TYPE,
2529  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_112_WIDTH },
2530  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_113_CHECKER_TYPE,
2531  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_113_WIDTH },
2532  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_114_CHECKER_TYPE,
2533  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_114_WIDTH },
2534  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_115_CHECKER_TYPE,
2535  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_115_WIDTH },
2536  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_116_CHECKER_TYPE,
2537  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_116_WIDTH },
2538  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_117_CHECKER_TYPE,
2539  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_117_WIDTH },
2540  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_118_CHECKER_TYPE,
2541  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_118_WIDTH },
2542  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_119_CHECKER_TYPE,
2543  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_119_WIDTH },
2544  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_120_CHECKER_TYPE,
2545  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_120_WIDTH },
2546  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_121_CHECKER_TYPE,
2547  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_121_WIDTH },
2548  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_122_CHECKER_TYPE,
2549  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_122_WIDTH },
2550  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_123_CHECKER_TYPE,
2551  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_123_WIDTH },
2552  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_124_CHECKER_TYPE,
2553  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_124_WIDTH },
2554  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_125_CHECKER_TYPE,
2555  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_125_WIDTH },
2556  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_126_CHECKER_TYPE,
2557  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_126_WIDTH },
2558  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_127_CHECKER_TYPE,
2559  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_127_WIDTH },
2560  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_128_CHECKER_TYPE,
2561  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_128_WIDTH },
2562  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_129_CHECKER_TYPE,
2563  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_129_WIDTH },
2564  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_130_CHECKER_TYPE,
2565  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_130_WIDTH },
2566  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_131_CHECKER_TYPE,
2567  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_131_WIDTH },
2568  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_132_CHECKER_TYPE,
2569  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_132_WIDTH },
2570  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_133_CHECKER_TYPE,
2571  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_133_WIDTH },
2572  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_134_CHECKER_TYPE,
2573  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_134_WIDTH },
2574  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_135_CHECKER_TYPE,
2575  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_135_WIDTH },
2576  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_136_CHECKER_TYPE,
2577  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_136_WIDTH },
2578  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_137_CHECKER_TYPE,
2579  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_137_WIDTH },
2580  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_138_CHECKER_TYPE,
2581  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_138_WIDTH },
2582  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_139_CHECKER_TYPE,
2583  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_139_WIDTH },
2584  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_140_CHECKER_TYPE,
2585  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_140_WIDTH },
2586  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_141_CHECKER_TYPE,
2587  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_141_WIDTH },
2588  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_142_CHECKER_TYPE,
2589  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_142_WIDTH },
2590  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_143_CHECKER_TYPE,
2591  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_143_WIDTH },
2592  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_144_CHECKER_TYPE,
2593  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_144_WIDTH },
2594  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_145_CHECKER_TYPE,
2595  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_145_WIDTH },
2596  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_146_CHECKER_TYPE,
2597  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_146_WIDTH },
2598  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_147_CHECKER_TYPE,
2599  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_147_WIDTH },
2600  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_148_CHECKER_TYPE,
2601  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_148_WIDTH },
2602  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_149_CHECKER_TYPE,
2603  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_149_WIDTH },
2604  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_150_CHECKER_TYPE,
2605  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_150_WIDTH },
2606  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_151_CHECKER_TYPE,
2607  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_151_WIDTH },
2608  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_152_CHECKER_TYPE,
2609  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_152_WIDTH },
2610  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_153_CHECKER_TYPE,
2611  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_153_WIDTH },
2612  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_154_CHECKER_TYPE,
2613  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_154_WIDTH },
2614  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_155_CHECKER_TYPE,
2615  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_155_WIDTH },
2616  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_156_CHECKER_TYPE,
2617  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_156_WIDTH },
2618  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_157_CHECKER_TYPE,
2619  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_157_WIDTH },
2620  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_158_CHECKER_TYPE,
2621  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_158_WIDTH },
2622  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_159_CHECKER_TYPE,
2623  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_159_WIDTH },
2624  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_160_CHECKER_TYPE,
2625  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_160_WIDTH },
2626  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_161_CHECKER_TYPE,
2627  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_161_WIDTH },
2628  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_162_CHECKER_TYPE,
2629  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_162_WIDTH },
2630  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_163_CHECKER_TYPE,
2631  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_163_WIDTH },
2632  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_164_CHECKER_TYPE,
2633  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_164_WIDTH },
2634  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_165_CHECKER_TYPE,
2635  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_165_WIDTH },
2636  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_166_CHECKER_TYPE,
2637  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_166_WIDTH },
2638  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_167_CHECKER_TYPE,
2639  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_167_WIDTH },
2640  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_168_CHECKER_TYPE,
2641  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_168_WIDTH },
2642  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_169_CHECKER_TYPE,
2643  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_169_WIDTH },
2644  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_170_CHECKER_TYPE,
2645  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_170_WIDTH },
2646  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_171_CHECKER_TYPE,
2647  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_171_WIDTH },
2648  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_172_CHECKER_TYPE,
2649  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_172_WIDTH },
2650  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_173_CHECKER_TYPE,
2651  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_173_WIDTH },
2652  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_174_CHECKER_TYPE,
2653  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_174_WIDTH },
2654  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_175_CHECKER_TYPE,
2655  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_175_WIDTH },
2656  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_176_CHECKER_TYPE,
2657  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_176_WIDTH },
2658  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_177_CHECKER_TYPE,
2659  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_177_WIDTH },
2660  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_178_CHECKER_TYPE,
2661  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_178_WIDTH },
2662  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_179_CHECKER_TYPE,
2663  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_179_WIDTH },
2664  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_180_CHECKER_TYPE,
2665  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_180_WIDTH },
2666  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_181_CHECKER_TYPE,
2667  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_181_WIDTH },
2668  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_182_CHECKER_TYPE,
2669  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_182_WIDTH },
2670  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_183_CHECKER_TYPE,
2671  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_183_WIDTH },
2672  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_184_CHECKER_TYPE,
2673  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_184_WIDTH },
2674  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_185_CHECKER_TYPE,
2675  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_185_WIDTH },
2676  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_186_CHECKER_TYPE,
2677  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_186_WIDTH },
2678  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_187_CHECKER_TYPE,
2679  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_187_WIDTH },
2680  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_188_CHECKER_TYPE,
2681  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_188_WIDTH },
2682  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_189_CHECKER_TYPE,
2683  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_189_WIDTH },
2684  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_190_CHECKER_TYPE,
2685  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_190_WIDTH },
2686  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_191_CHECKER_TYPE,
2687  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_191_WIDTH },
2688  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_192_CHECKER_TYPE,
2689  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_192_WIDTH },
2690  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_193_CHECKER_TYPE,
2691  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_193_WIDTH },
2692  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_194_CHECKER_TYPE,
2693  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_194_WIDTH },
2694  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_195_CHECKER_TYPE,
2695  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_195_WIDTH },
2696  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_196_CHECKER_TYPE,
2697  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_196_WIDTH },
2698  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_197_CHECKER_TYPE,
2699  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_197_WIDTH },
2700  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_198_CHECKER_TYPE,
2701  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_198_WIDTH },
2702  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_199_CHECKER_TYPE,
2703  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_199_WIDTH },
2704  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_200_CHECKER_TYPE,
2705  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_200_WIDTH },
2706  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_201_CHECKER_TYPE,
2707  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_201_WIDTH },
2708  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_202_CHECKER_TYPE,
2709  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_202_WIDTH },
2710  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_203_CHECKER_TYPE,
2711  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_203_WIDTH },
2712  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_204_CHECKER_TYPE,
2713  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_204_WIDTH },
2714  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_205_CHECKER_TYPE,
2715  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_205_WIDTH },
2716  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_206_CHECKER_TYPE,
2717  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_206_WIDTH },
2718  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_207_CHECKER_TYPE,
2719  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_207_WIDTH },
2720  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_208_CHECKER_TYPE,
2721  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_208_WIDTH },
2722  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_209_CHECKER_TYPE,
2723  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_209_WIDTH },
2724  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_210_CHECKER_TYPE,
2725  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_210_WIDTH },
2726  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_211_CHECKER_TYPE,
2727  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_211_WIDTH },
2728  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_212_CHECKER_TYPE,
2729  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_212_WIDTH },
2730  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_213_CHECKER_TYPE,
2731  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_213_WIDTH },
2732  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_214_CHECKER_TYPE,
2733  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_214_WIDTH },
2734  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_215_CHECKER_TYPE,
2735  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_215_WIDTH },
2736  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_216_CHECKER_TYPE,
2737  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_216_WIDTH },
2738  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_217_CHECKER_TYPE,
2739  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_217_WIDTH },
2740  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_218_CHECKER_TYPE,
2741  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_218_WIDTH },
2742  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_219_CHECKER_TYPE,
2743  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_219_WIDTH },
2744  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_220_CHECKER_TYPE,
2745  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_220_WIDTH },
2746  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_221_CHECKER_TYPE,
2747  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_221_WIDTH },
2748  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_222_CHECKER_TYPE,
2749  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_222_WIDTH },
2750  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_223_CHECKER_TYPE,
2751  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_223_WIDTH },
2752  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_224_CHECKER_TYPE,
2753  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_224_WIDTH },
2754  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_225_CHECKER_TYPE,
2755  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_225_WIDTH },
2756  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_226_CHECKER_TYPE,
2757  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_226_WIDTH },
2758  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_227_CHECKER_TYPE,
2759  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_227_WIDTH },
2760  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_228_CHECKER_TYPE,
2761  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_228_WIDTH },
2762  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_229_CHECKER_TYPE,
2763  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_229_WIDTH },
2764  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_230_CHECKER_TYPE,
2765  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_230_WIDTH },
2766  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_231_CHECKER_TYPE,
2767  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_231_WIDTH },
2768  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_232_CHECKER_TYPE,
2769  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_232_WIDTH },
2770  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_233_CHECKER_TYPE,
2771  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_233_WIDTH },
2772  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_234_CHECKER_TYPE,
2773  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_234_WIDTH },
2774  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_235_CHECKER_TYPE,
2775  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_235_WIDTH },
2776  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_236_CHECKER_TYPE,
2777  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_236_WIDTH },
2778  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_237_CHECKER_TYPE,
2779  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_237_WIDTH },
2780  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_238_CHECKER_TYPE,
2781  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_238_WIDTH },
2782  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_239_CHECKER_TYPE,
2783  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_239_WIDTH },
2784  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_240_CHECKER_TYPE,
2785  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_240_WIDTH },
2786  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_241_CHECKER_TYPE,
2787  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_241_WIDTH },
2788  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_242_CHECKER_TYPE,
2789  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_242_WIDTH },
2790  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_243_CHECKER_TYPE,
2791  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_243_WIDTH },
2792  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_244_CHECKER_TYPE,
2793  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_244_WIDTH },
2794  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_245_CHECKER_TYPE,
2795  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_245_WIDTH },
2796  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_246_CHECKER_TYPE,
2797  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_246_WIDTH },
2798  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_247_CHECKER_TYPE,
2799  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_247_WIDTH },
2800  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_248_CHECKER_TYPE,
2801  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_248_WIDTH },
2802  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_249_CHECKER_TYPE,
2803  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_249_WIDTH },
2804  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_250_CHECKER_TYPE,
2805  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_250_WIDTH },
2806  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_251_CHECKER_TYPE,
2807  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_251_WIDTH },
2808  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_252_CHECKER_TYPE,
2809  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_252_WIDTH },
2810  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_253_CHECKER_TYPE,
2811  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_253_WIDTH },
2812  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_254_CHECKER_TYPE,
2813  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_254_WIDTH },
2814  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_255_CHECKER_TYPE,
2815  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_GROUP_255_WIDTH },
2816 };
2817 
2823 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS] =
2824 {
2825  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_0_CHECKER_TYPE,
2826  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_0_WIDTH },
2827  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_1_CHECKER_TYPE,
2828  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_1_WIDTH },
2829  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_2_CHECKER_TYPE,
2830  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_2_WIDTH },
2831  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_3_CHECKER_TYPE,
2832  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_3_WIDTH },
2833  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_4_CHECKER_TYPE,
2834  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_4_WIDTH },
2835  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_5_CHECKER_TYPE,
2836  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_5_WIDTH },
2837  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_6_CHECKER_TYPE,
2838  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_6_WIDTH },
2839  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_7_CHECKER_TYPE,
2840  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_7_WIDTH },
2841  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_8_CHECKER_TYPE,
2842  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_8_WIDTH },
2843  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_9_CHECKER_TYPE,
2844  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_9_WIDTH },
2845  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_10_CHECKER_TYPE,
2846  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_10_WIDTH },
2847  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_11_CHECKER_TYPE,
2848  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_11_WIDTH },
2849  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_12_CHECKER_TYPE,
2850  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_12_WIDTH },
2851  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_13_CHECKER_TYPE,
2852  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_13_WIDTH },
2853  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_14_CHECKER_TYPE,
2854  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_14_WIDTH },
2855  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_15_CHECKER_TYPE,
2856  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_15_WIDTH },
2857  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_16_CHECKER_TYPE,
2858  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_16_WIDTH },
2859  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_17_CHECKER_TYPE,
2860  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_17_WIDTH },
2861  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_18_CHECKER_TYPE,
2862  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_18_WIDTH },
2863  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_19_CHECKER_TYPE,
2864  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_19_WIDTH },
2865  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_20_CHECKER_TYPE,
2866  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_20_WIDTH },
2867  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_21_CHECKER_TYPE,
2868  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_21_WIDTH },
2869  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_22_CHECKER_TYPE,
2870  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_22_WIDTH },
2871  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_23_CHECKER_TYPE,
2872  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_23_WIDTH },
2873  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_24_CHECKER_TYPE,
2874  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_24_WIDTH },
2875  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_25_CHECKER_TYPE,
2876  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_25_WIDTH },
2877  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_26_CHECKER_TYPE,
2878  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_26_WIDTH },
2879  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_27_CHECKER_TYPE,
2880  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_27_WIDTH },
2881  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_28_CHECKER_TYPE,
2882  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_28_WIDTH },
2883  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_29_CHECKER_TYPE,
2884  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_29_WIDTH },
2885  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_30_CHECKER_TYPE,
2886  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_30_WIDTH },
2887  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_31_CHECKER_TYPE,
2888  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_31_WIDTH },
2889  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_32_CHECKER_TYPE,
2890  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_32_WIDTH },
2891  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_33_CHECKER_TYPE,
2892  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_33_WIDTH },
2893  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_34_CHECKER_TYPE,
2894  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_34_WIDTH },
2895  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_35_CHECKER_TYPE,
2896  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_35_WIDTH },
2897  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_36_CHECKER_TYPE,
2898  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_36_WIDTH },
2899  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_37_CHECKER_TYPE,
2900  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_37_WIDTH },
2901  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_38_CHECKER_TYPE,
2902  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_38_WIDTH },
2903  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_39_CHECKER_TYPE,
2904  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_39_WIDTH },
2905  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_40_CHECKER_TYPE,
2906  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_40_WIDTH },
2907  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_41_CHECKER_TYPE,
2908  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_41_WIDTH },
2909  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_42_CHECKER_TYPE,
2910  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_42_WIDTH },
2911  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_43_CHECKER_TYPE,
2912  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_43_WIDTH },
2913  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_44_CHECKER_TYPE,
2914  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_44_WIDTH },
2915  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_45_CHECKER_TYPE,
2916  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_45_WIDTH },
2917  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_46_CHECKER_TYPE,
2918  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_46_WIDTH },
2919  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_47_CHECKER_TYPE,
2920  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_47_WIDTH },
2921  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_48_CHECKER_TYPE,
2922  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_48_WIDTH },
2923  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_49_CHECKER_TYPE,
2924  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_49_WIDTH },
2925  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_50_CHECKER_TYPE,
2926  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_50_WIDTH },
2927  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_51_CHECKER_TYPE,
2928  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_51_WIDTH },
2929  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_52_CHECKER_TYPE,
2930  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_52_WIDTH },
2931  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_53_CHECKER_TYPE,
2932  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_53_WIDTH },
2933  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_54_CHECKER_TYPE,
2934  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_54_WIDTH },
2935  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_55_CHECKER_TYPE,
2936  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_55_WIDTH },
2937  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_56_CHECKER_TYPE,
2938  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_56_WIDTH },
2939  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_57_CHECKER_TYPE,
2940  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_57_WIDTH },
2941  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_58_CHECKER_TYPE,
2942  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_58_WIDTH },
2943  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_59_CHECKER_TYPE,
2944  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_59_WIDTH },
2945  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_60_CHECKER_TYPE,
2946  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_60_WIDTH },
2947  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_61_CHECKER_TYPE,
2948  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_61_WIDTH },
2949  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_62_CHECKER_TYPE,
2950  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_62_WIDTH },
2951  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_63_CHECKER_TYPE,
2952  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_63_WIDTH },
2953  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_64_CHECKER_TYPE,
2954  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_64_WIDTH },
2955  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_65_CHECKER_TYPE,
2956  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_65_WIDTH },
2957  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_66_CHECKER_TYPE,
2958  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_66_WIDTH },
2959  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_67_CHECKER_TYPE,
2960  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_67_WIDTH },
2961  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_68_CHECKER_TYPE,
2962  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_68_WIDTH },
2963  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_69_CHECKER_TYPE,
2964  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_69_WIDTH },
2965  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_70_CHECKER_TYPE,
2966  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_70_WIDTH },
2967  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_71_CHECKER_TYPE,
2968  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_71_WIDTH },
2969  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_72_CHECKER_TYPE,
2970  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_72_WIDTH },
2971  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_73_CHECKER_TYPE,
2972  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_73_WIDTH },
2973  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_74_CHECKER_TYPE,
2974  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_74_WIDTH },
2975  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_75_CHECKER_TYPE,
2976  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_75_WIDTH },
2977  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_76_CHECKER_TYPE,
2978  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_76_WIDTH },
2979  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_77_CHECKER_TYPE,
2980  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_77_WIDTH },
2981  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_78_CHECKER_TYPE,
2982  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_78_WIDTH },
2983  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_79_CHECKER_TYPE,
2984  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_79_WIDTH },
2985  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_80_CHECKER_TYPE,
2986  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_80_WIDTH },
2987  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_81_CHECKER_TYPE,
2988  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_81_WIDTH },
2989  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_82_CHECKER_TYPE,
2990  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_82_WIDTH },
2991  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_83_CHECKER_TYPE,
2992  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_83_WIDTH },
2993  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_84_CHECKER_TYPE,
2994  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_84_WIDTH },
2995  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_85_CHECKER_TYPE,
2996  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_85_WIDTH },
2997  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_86_CHECKER_TYPE,
2998  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_86_WIDTH },
2999  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_87_CHECKER_TYPE,
3000  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_87_WIDTH },
3001  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_88_CHECKER_TYPE,
3002  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_88_WIDTH },
3003  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_89_CHECKER_TYPE,
3004  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_89_WIDTH },
3005  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_90_CHECKER_TYPE,
3006  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_90_WIDTH },
3007  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_91_CHECKER_TYPE,
3008  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_91_WIDTH },
3009  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_92_CHECKER_TYPE,
3010  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_92_WIDTH },
3011  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_93_CHECKER_TYPE,
3012  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_93_WIDTH },
3013  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_94_CHECKER_TYPE,
3014  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_94_WIDTH },
3015  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_95_CHECKER_TYPE,
3016  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_95_WIDTH },
3017  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_96_CHECKER_TYPE,
3018  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_96_WIDTH },
3019  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_97_CHECKER_TYPE,
3020  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_97_WIDTH },
3021  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_98_CHECKER_TYPE,
3022  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_98_WIDTH },
3023  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_99_CHECKER_TYPE,
3024  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_99_WIDTH },
3025  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_100_CHECKER_TYPE,
3026  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_100_WIDTH },
3027  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_101_CHECKER_TYPE,
3028  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_101_WIDTH },
3029  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_102_CHECKER_TYPE,
3030  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_102_WIDTH },
3031  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_103_CHECKER_TYPE,
3032  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_103_WIDTH },
3033  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_104_CHECKER_TYPE,
3034  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_104_WIDTH },
3035  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_105_CHECKER_TYPE,
3036  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_105_WIDTH },
3037  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_106_CHECKER_TYPE,
3038  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_106_WIDTH },
3039  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_107_CHECKER_TYPE,
3040  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_107_WIDTH },
3041  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_108_CHECKER_TYPE,
3042  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_108_WIDTH },
3043  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_109_CHECKER_TYPE,
3044  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_109_WIDTH },
3045  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_110_CHECKER_TYPE,
3046  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_110_WIDTH },
3047  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_111_CHECKER_TYPE,
3048  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_111_WIDTH },
3049  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_112_CHECKER_TYPE,
3050  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_112_WIDTH },
3051  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_113_CHECKER_TYPE,
3052  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_113_WIDTH },
3053  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_114_CHECKER_TYPE,
3054  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_114_WIDTH },
3055  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_115_CHECKER_TYPE,
3056  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_115_WIDTH },
3057  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_116_CHECKER_TYPE,
3058  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_116_WIDTH },
3059  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_117_CHECKER_TYPE,
3060  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_117_WIDTH },
3061  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_118_CHECKER_TYPE,
3062  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_118_WIDTH },
3063  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_119_CHECKER_TYPE,
3064  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_119_WIDTH },
3065  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_120_CHECKER_TYPE,
3066  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_120_WIDTH },
3067  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_121_CHECKER_TYPE,
3068  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_121_WIDTH },
3069  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_122_CHECKER_TYPE,
3070  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_122_WIDTH },
3071  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_123_CHECKER_TYPE,
3072  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_123_WIDTH },
3073  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_124_CHECKER_TYPE,
3074  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_124_WIDTH },
3075  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_125_CHECKER_TYPE,
3076  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_125_WIDTH },
3077  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_126_CHECKER_TYPE,
3078  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_126_WIDTH },
3079  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_127_CHECKER_TYPE,
3080  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_127_WIDTH },
3081  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_128_CHECKER_TYPE,
3082  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_128_WIDTH },
3083  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_129_CHECKER_TYPE,
3084  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_129_WIDTH },
3085  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_130_CHECKER_TYPE,
3086  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_130_WIDTH },
3087  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_131_CHECKER_TYPE,
3088  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_131_WIDTH },
3089  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_132_CHECKER_TYPE,
3090  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_132_WIDTH },
3091  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_133_CHECKER_TYPE,
3092  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_133_WIDTH },
3093  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_134_CHECKER_TYPE,
3094  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_134_WIDTH },
3095  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_135_CHECKER_TYPE,
3096  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_135_WIDTH },
3097  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_136_CHECKER_TYPE,
3098  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_136_WIDTH },
3099  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_137_CHECKER_TYPE,
3100  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_137_WIDTH },
3101  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_138_CHECKER_TYPE,
3102  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_138_WIDTH },
3103  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_139_CHECKER_TYPE,
3104  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_139_WIDTH },
3105  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_140_CHECKER_TYPE,
3106  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_140_WIDTH },
3107  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_141_CHECKER_TYPE,
3108  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_141_WIDTH },
3109  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_142_CHECKER_TYPE,
3110  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_142_WIDTH },
3111  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_143_CHECKER_TYPE,
3112  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_143_WIDTH },
3113  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_144_CHECKER_TYPE,
3114  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_144_WIDTH },
3115  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_145_CHECKER_TYPE,
3116  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_145_WIDTH },
3117  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_146_CHECKER_TYPE,
3118  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_146_WIDTH },
3119  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_147_CHECKER_TYPE,
3120  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_147_WIDTH },
3121  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_148_CHECKER_TYPE,
3122  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_148_WIDTH },
3123  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_149_CHECKER_TYPE,
3124  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_149_WIDTH },
3125  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_150_CHECKER_TYPE,
3126  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_150_WIDTH },
3127  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_151_CHECKER_TYPE,
3128  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_151_WIDTH },
3129  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_152_CHECKER_TYPE,
3130  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_152_WIDTH },
3131  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_153_CHECKER_TYPE,
3132  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_153_WIDTH },
3133  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_154_CHECKER_TYPE,
3134  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_154_WIDTH },
3135  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_155_CHECKER_TYPE,
3136  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_155_WIDTH },
3137  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_156_CHECKER_TYPE,
3138  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_156_WIDTH },
3139  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_157_CHECKER_TYPE,
3140  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_157_WIDTH },
3141  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_158_CHECKER_TYPE,
3142  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_158_WIDTH },
3143  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_159_CHECKER_TYPE,
3144  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_159_WIDTH },
3145  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_160_CHECKER_TYPE,
3146  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_160_WIDTH },
3147  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_161_CHECKER_TYPE,
3148  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_161_WIDTH },
3149  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_162_CHECKER_TYPE,
3150  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_162_WIDTH },
3151  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_163_CHECKER_TYPE,
3152  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_163_WIDTH },
3153  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_164_CHECKER_TYPE,
3154  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_164_WIDTH },
3155  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_165_CHECKER_TYPE,
3156  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_165_WIDTH },
3157  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_166_CHECKER_TYPE,
3158  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_166_WIDTH },
3159  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_167_CHECKER_TYPE,
3160  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_167_WIDTH },
3161  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_168_CHECKER_TYPE,
3162  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_168_WIDTH },
3163  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_169_CHECKER_TYPE,
3164  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_169_WIDTH },
3165  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_170_CHECKER_TYPE,
3166  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_170_WIDTH },
3167  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_171_CHECKER_TYPE,
3168  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_171_WIDTH },
3169  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_172_CHECKER_TYPE,
3170  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_172_WIDTH },
3171  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_173_CHECKER_TYPE,
3172  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_173_WIDTH },
3173  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_174_CHECKER_TYPE,
3174  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_174_WIDTH },
3175  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_175_CHECKER_TYPE,
3176  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_175_WIDTH },
3177  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_176_CHECKER_TYPE,
3178  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_176_WIDTH },
3179  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_177_CHECKER_TYPE,
3180  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_177_WIDTH },
3181  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_178_CHECKER_TYPE,
3182  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_178_WIDTH },
3183  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_179_CHECKER_TYPE,
3184  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_179_WIDTH },
3185  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_180_CHECKER_TYPE,
3186  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_180_WIDTH },
3187  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_181_CHECKER_TYPE,
3188  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_181_WIDTH },
3189  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_182_CHECKER_TYPE,
3190  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_182_WIDTH },
3191  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_183_CHECKER_TYPE,
3192  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_183_WIDTH },
3193  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_184_CHECKER_TYPE,
3194  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_184_WIDTH },
3195  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_185_CHECKER_TYPE,
3196  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_185_WIDTH },
3197  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_186_CHECKER_TYPE,
3198  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_186_WIDTH },
3199  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_187_CHECKER_TYPE,
3200  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_187_WIDTH },
3201  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_188_CHECKER_TYPE,
3202  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_188_WIDTH },
3203  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_189_CHECKER_TYPE,
3204  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_189_WIDTH },
3205  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_190_CHECKER_TYPE,
3206  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_190_WIDTH },
3207  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_191_CHECKER_TYPE,
3208  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_191_WIDTH },
3209  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_192_CHECKER_TYPE,
3210  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_192_WIDTH },
3211  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_193_CHECKER_TYPE,
3212  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_193_WIDTH },
3213  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_194_CHECKER_TYPE,
3214  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_194_WIDTH },
3215  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_195_CHECKER_TYPE,
3216  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_195_WIDTH },
3217  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_196_CHECKER_TYPE,
3218  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_196_WIDTH },
3219  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_197_CHECKER_TYPE,
3220  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_197_WIDTH },
3221  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_198_CHECKER_TYPE,
3222  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_198_WIDTH },
3223  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_199_CHECKER_TYPE,
3224  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_199_WIDTH },
3225  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_200_CHECKER_TYPE,
3226  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_200_WIDTH },
3227  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_201_CHECKER_TYPE,
3228  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_201_WIDTH },
3229  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_202_CHECKER_TYPE,
3230  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_202_WIDTH },
3231  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_203_CHECKER_TYPE,
3232  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_203_WIDTH },
3233  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_204_CHECKER_TYPE,
3234  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_204_WIDTH },
3235  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_205_CHECKER_TYPE,
3236  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_205_WIDTH },
3237  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_206_CHECKER_TYPE,
3238  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_206_WIDTH },
3239  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_207_CHECKER_TYPE,
3240  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_207_WIDTH },
3241  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_208_CHECKER_TYPE,
3242  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_208_WIDTH },
3243  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_209_CHECKER_TYPE,
3244  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_209_WIDTH },
3245  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_210_CHECKER_TYPE,
3246  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_210_WIDTH },
3247  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_211_CHECKER_TYPE,
3248  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_211_WIDTH },
3249  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_212_CHECKER_TYPE,
3250  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_212_WIDTH },
3251  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_213_CHECKER_TYPE,
3252  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_213_WIDTH },
3253  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_214_CHECKER_TYPE,
3254  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_214_WIDTH },
3255  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_215_CHECKER_TYPE,
3256  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_215_WIDTH },
3257  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_216_CHECKER_TYPE,
3258  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_216_WIDTH },
3259  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_217_CHECKER_TYPE,
3260  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_217_WIDTH },
3261  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_218_CHECKER_TYPE,
3262  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_218_WIDTH },
3263  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_219_CHECKER_TYPE,
3264  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_219_WIDTH },
3265  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_220_CHECKER_TYPE,
3266  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_220_WIDTH },
3267  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_221_CHECKER_TYPE,
3268  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_221_WIDTH },
3269  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_222_CHECKER_TYPE,
3270  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_222_WIDTH },
3271  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_223_CHECKER_TYPE,
3272  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_223_WIDTH },
3273  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_224_CHECKER_TYPE,
3274  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_224_WIDTH },
3275  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_225_CHECKER_TYPE,
3276  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_225_WIDTH },
3277  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_226_CHECKER_TYPE,
3278  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_226_WIDTH },
3279  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_227_CHECKER_TYPE,
3280  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_227_WIDTH },
3281  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_228_CHECKER_TYPE,
3282  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_228_WIDTH },
3283  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_229_CHECKER_TYPE,
3284  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_229_WIDTH },
3285  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_230_CHECKER_TYPE,
3286  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_230_WIDTH },
3287  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_231_CHECKER_TYPE,
3288  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_231_WIDTH },
3289  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_232_CHECKER_TYPE,
3290  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_232_WIDTH },
3291  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_233_CHECKER_TYPE,
3292  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_233_WIDTH },
3293  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_234_CHECKER_TYPE,
3294  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_234_WIDTH },
3295  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_235_CHECKER_TYPE,
3296  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_235_WIDTH },
3297  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_236_CHECKER_TYPE,
3298  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_236_WIDTH },
3299  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_237_CHECKER_TYPE,
3300  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_237_WIDTH },
3301  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_238_CHECKER_TYPE,
3302  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_238_WIDTH },
3303  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_239_CHECKER_TYPE,
3304  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_239_WIDTH },
3305  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_240_CHECKER_TYPE,
3306  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_240_WIDTH },
3307  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_241_CHECKER_TYPE,
3308  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_241_WIDTH },
3309  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_242_CHECKER_TYPE,
3310  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_242_WIDTH },
3311  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_243_CHECKER_TYPE,
3312  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_243_WIDTH },
3313  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_244_CHECKER_TYPE,
3314  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_244_WIDTH },
3315  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_245_CHECKER_TYPE,
3316  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_245_WIDTH },
3317  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_246_CHECKER_TYPE,
3318  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_246_WIDTH },
3319  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_247_CHECKER_TYPE,
3320  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_247_WIDTH },
3321  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_248_CHECKER_TYPE,
3322  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_248_WIDTH },
3323  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_249_CHECKER_TYPE,
3324  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_249_WIDTH },
3325  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_250_CHECKER_TYPE,
3326  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_250_WIDTH },
3327  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_251_CHECKER_TYPE,
3328  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_251_WIDTH },
3329  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_252_CHECKER_TYPE,
3330  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_252_WIDTH },
3331  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_253_CHECKER_TYPE,
3332  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_253_WIDTH },
3333  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_254_CHECKER_TYPE,
3334  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_254_WIDTH },
3335  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_255_CHECKER_TYPE,
3336  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_GROUP_255_WIDTH },
3337 };
3338 
3344 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS] =
3345 {
3346  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_0_CHECKER_TYPE,
3347  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_0_WIDTH },
3348  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_1_CHECKER_TYPE,
3349  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_1_WIDTH },
3350  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_2_CHECKER_TYPE,
3351  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_2_WIDTH },
3352  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_3_CHECKER_TYPE,
3353  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_3_WIDTH },
3354  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_4_CHECKER_TYPE,
3355  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_4_WIDTH },
3356  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_5_CHECKER_TYPE,
3357  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_5_WIDTH },
3358  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_6_CHECKER_TYPE,
3359  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_6_WIDTH },
3360  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_7_CHECKER_TYPE,
3361  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_7_WIDTH },
3362  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_8_CHECKER_TYPE,
3363  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_8_WIDTH },
3364  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_9_CHECKER_TYPE,
3365  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_9_WIDTH },
3366  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_10_CHECKER_TYPE,
3367  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_10_WIDTH },
3368  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_11_CHECKER_TYPE,
3369  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_11_WIDTH },
3370  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_12_CHECKER_TYPE,
3371  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_12_WIDTH },
3372  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_13_CHECKER_TYPE,
3373  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_13_WIDTH },
3374  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_14_CHECKER_TYPE,
3375  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_14_WIDTH },
3376  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_15_CHECKER_TYPE,
3377  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_15_WIDTH },
3378  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_16_CHECKER_TYPE,
3379  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_16_WIDTH },
3380  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_17_CHECKER_TYPE,
3381  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_17_WIDTH },
3382  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_18_CHECKER_TYPE,
3383  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_18_WIDTH },
3384  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_19_CHECKER_TYPE,
3385  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_19_WIDTH },
3386  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_20_CHECKER_TYPE,
3387  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_20_WIDTH },
3388  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_21_CHECKER_TYPE,
3389  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_21_WIDTH },
3390  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_22_CHECKER_TYPE,
3391  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_22_WIDTH },
3392  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_23_CHECKER_TYPE,
3393  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_23_WIDTH },
3394  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_24_CHECKER_TYPE,
3395  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_24_WIDTH },
3396  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_25_CHECKER_TYPE,
3397  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_25_WIDTH },
3398  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_26_CHECKER_TYPE,
3399  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_26_WIDTH },
3400  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_27_CHECKER_TYPE,
3401  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_27_WIDTH },
3402  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_28_CHECKER_TYPE,
3403  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_28_WIDTH },
3404  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_29_CHECKER_TYPE,
3405  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_29_WIDTH },
3406  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_30_CHECKER_TYPE,
3407  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_30_WIDTH },
3408  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_31_CHECKER_TYPE,
3409  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_31_WIDTH },
3410  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_32_CHECKER_TYPE,
3411  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_32_WIDTH },
3412  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_33_CHECKER_TYPE,
3413  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_33_WIDTH },
3414  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_34_CHECKER_TYPE,
3415  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_34_WIDTH },
3416  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_35_CHECKER_TYPE,
3417  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_35_WIDTH },
3418  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_36_CHECKER_TYPE,
3419  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_36_WIDTH },
3420  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_37_CHECKER_TYPE,
3421  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_37_WIDTH },
3422  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_38_CHECKER_TYPE,
3423  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_38_WIDTH },
3424  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_39_CHECKER_TYPE,
3425  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_39_WIDTH },
3426  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_40_CHECKER_TYPE,
3427  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_40_WIDTH },
3428  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_41_CHECKER_TYPE,
3429  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_41_WIDTH },
3430  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_42_CHECKER_TYPE,
3431  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_42_WIDTH },
3432  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_43_CHECKER_TYPE,
3433  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_43_WIDTH },
3434  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_44_CHECKER_TYPE,
3435  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_44_WIDTH },
3436  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_45_CHECKER_TYPE,
3437  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_45_WIDTH },
3438  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_46_CHECKER_TYPE,
3439  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_46_WIDTH },
3440  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_47_CHECKER_TYPE,
3441  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_47_WIDTH },
3442  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_48_CHECKER_TYPE,
3443  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_48_WIDTH },
3444  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_49_CHECKER_TYPE,
3445  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_49_WIDTH },
3446  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_50_CHECKER_TYPE,
3447  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_50_WIDTH },
3448  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_51_CHECKER_TYPE,
3449  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_51_WIDTH },
3450  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_52_CHECKER_TYPE,
3451  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_52_WIDTH },
3452  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_53_CHECKER_TYPE,
3453  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_53_WIDTH },
3454  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_54_CHECKER_TYPE,
3455  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_54_WIDTH },
3456  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_55_CHECKER_TYPE,
3457  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_55_WIDTH },
3458  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_56_CHECKER_TYPE,
3459  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_56_WIDTH },
3460  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_57_CHECKER_TYPE,
3461  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_57_WIDTH },
3462  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_58_CHECKER_TYPE,
3463  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_58_WIDTH },
3464  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_59_CHECKER_TYPE,
3465  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_59_WIDTH },
3466  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_60_CHECKER_TYPE,
3467  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_60_WIDTH },
3468  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_61_CHECKER_TYPE,
3469  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_61_WIDTH },
3470  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_62_CHECKER_TYPE,
3471  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_62_WIDTH },
3472  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_63_CHECKER_TYPE,
3473  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_63_WIDTH },
3474  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_64_CHECKER_TYPE,
3475  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_64_WIDTH },
3476  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_65_CHECKER_TYPE,
3477  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_65_WIDTH },
3478  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_66_CHECKER_TYPE,
3479  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_66_WIDTH },
3480  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_67_CHECKER_TYPE,
3481  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_67_WIDTH },
3482  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_68_CHECKER_TYPE,
3483  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_68_WIDTH },
3484  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_69_CHECKER_TYPE,
3485  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_69_WIDTH },
3486  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_70_CHECKER_TYPE,
3487  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_70_WIDTH },
3488  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_71_CHECKER_TYPE,
3489  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_71_WIDTH },
3490  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_72_CHECKER_TYPE,
3491  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_72_WIDTH },
3492  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_73_CHECKER_TYPE,
3493  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_73_WIDTH },
3494  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_74_CHECKER_TYPE,
3495  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_74_WIDTH },
3496  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_75_CHECKER_TYPE,
3497  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_75_WIDTH },
3498  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_76_CHECKER_TYPE,
3499  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_76_WIDTH },
3500  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_77_CHECKER_TYPE,
3501  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_77_WIDTH },
3502  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_78_CHECKER_TYPE,
3503  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_78_WIDTH },
3504  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_79_CHECKER_TYPE,
3505  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_79_WIDTH },
3506  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_80_CHECKER_TYPE,
3507  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_80_WIDTH },
3508  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_81_CHECKER_TYPE,
3509  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_81_WIDTH },
3510  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_82_CHECKER_TYPE,
3511  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_82_WIDTH },
3512  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_83_CHECKER_TYPE,
3513  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_83_WIDTH },
3514  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_84_CHECKER_TYPE,
3515  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_84_WIDTH },
3516  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_85_CHECKER_TYPE,
3517  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_85_WIDTH },
3518  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_86_CHECKER_TYPE,
3519  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_86_WIDTH },
3520  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_87_CHECKER_TYPE,
3521  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_87_WIDTH },
3522  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_88_CHECKER_TYPE,
3523  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_88_WIDTH },
3524  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_89_CHECKER_TYPE,
3525  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_89_WIDTH },
3526  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_90_CHECKER_TYPE,
3527  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_90_WIDTH },
3528  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_91_CHECKER_TYPE,
3529  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_91_WIDTH },
3530  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_92_CHECKER_TYPE,
3531  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_92_WIDTH },
3532  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_93_CHECKER_TYPE,
3533  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_93_WIDTH },
3534  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_94_CHECKER_TYPE,
3535  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_94_WIDTH },
3536  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_95_CHECKER_TYPE,
3537  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_95_WIDTH },
3538  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_96_CHECKER_TYPE,
3539  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_96_WIDTH },
3540  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_97_CHECKER_TYPE,
3541  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_97_WIDTH },
3542  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_98_CHECKER_TYPE,
3543  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_98_WIDTH },
3544  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_99_CHECKER_TYPE,
3545  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_99_WIDTH },
3546  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_100_CHECKER_TYPE,
3547  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_100_WIDTH },
3548  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_101_CHECKER_TYPE,
3549  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_101_WIDTH },
3550  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_102_CHECKER_TYPE,
3551  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_102_WIDTH },
3552  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_103_CHECKER_TYPE,
3553  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_103_WIDTH },
3554  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_104_CHECKER_TYPE,
3555  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_104_WIDTH },
3556  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_105_CHECKER_TYPE,
3557  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_105_WIDTH },
3558  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_106_CHECKER_TYPE,
3559  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_106_WIDTH },
3560  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_107_CHECKER_TYPE,
3561  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_107_WIDTH },
3562  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_108_CHECKER_TYPE,
3563  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_108_WIDTH },
3564  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_109_CHECKER_TYPE,
3565  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_109_WIDTH },
3566  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_110_CHECKER_TYPE,
3567  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_110_WIDTH },
3568  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_111_CHECKER_TYPE,
3569  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_111_WIDTH },
3570  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_112_CHECKER_TYPE,
3571  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_112_WIDTH },
3572  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_113_CHECKER_TYPE,
3573  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_113_WIDTH },
3574  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_114_CHECKER_TYPE,
3575  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_114_WIDTH },
3576  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_115_CHECKER_TYPE,
3577  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_115_WIDTH },
3578  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_116_CHECKER_TYPE,
3579  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_116_WIDTH },
3580  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_117_CHECKER_TYPE,
3581  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_117_WIDTH },
3582  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_118_CHECKER_TYPE,
3583  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_118_WIDTH },
3584  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_119_CHECKER_TYPE,
3585  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_119_WIDTH },
3586  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_120_CHECKER_TYPE,
3587  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_120_WIDTH },
3588  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_121_CHECKER_TYPE,
3589  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_121_WIDTH },
3590  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_122_CHECKER_TYPE,
3591  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_122_WIDTH },
3592  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_123_CHECKER_TYPE,
3593  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_123_WIDTH },
3594  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_124_CHECKER_TYPE,
3595  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_124_WIDTH },
3596  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_125_CHECKER_TYPE,
3597  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_125_WIDTH },
3598  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_126_CHECKER_TYPE,
3599  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_126_WIDTH },
3600  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_127_CHECKER_TYPE,
3601  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_127_WIDTH },
3602  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_128_CHECKER_TYPE,
3603  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_128_WIDTH },
3604  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_129_CHECKER_TYPE,
3605  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_129_WIDTH },
3606  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_130_CHECKER_TYPE,
3607  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_130_WIDTH },
3608  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_131_CHECKER_TYPE,
3609  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_131_WIDTH },
3610  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_132_CHECKER_TYPE,
3611  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_132_WIDTH },
3612  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_133_CHECKER_TYPE,
3613  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_133_WIDTH },
3614  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_134_CHECKER_TYPE,
3615  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_134_WIDTH },
3616  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_135_CHECKER_TYPE,
3617  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_135_WIDTH },
3618  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_136_CHECKER_TYPE,
3619  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_136_WIDTH },
3620  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_137_CHECKER_TYPE,
3621  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_137_WIDTH },
3622  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_138_CHECKER_TYPE,
3623  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_138_WIDTH },
3624  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_139_CHECKER_TYPE,
3625  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_139_WIDTH },
3626  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_140_CHECKER_TYPE,
3627  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_140_WIDTH },
3628  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_141_CHECKER_TYPE,
3629  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_141_WIDTH },
3630  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_142_CHECKER_TYPE,
3631  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_142_WIDTH },
3632  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_143_CHECKER_TYPE,
3633  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_143_WIDTH },
3634  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_144_CHECKER_TYPE,
3635  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_144_WIDTH },
3636  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_145_CHECKER_TYPE,
3637  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_145_WIDTH },
3638  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_146_CHECKER_TYPE,
3639  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_146_WIDTH },
3640  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_147_CHECKER_TYPE,
3641  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_147_WIDTH },
3642  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_148_CHECKER_TYPE,
3643  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_148_WIDTH },
3644  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_149_CHECKER_TYPE,
3645  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_149_WIDTH },
3646  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_150_CHECKER_TYPE,
3647  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_150_WIDTH },
3648  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_151_CHECKER_TYPE,
3649  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_151_WIDTH },
3650  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_152_CHECKER_TYPE,
3651  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_152_WIDTH },
3652  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_153_CHECKER_TYPE,
3653  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_153_WIDTH },
3654  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_154_CHECKER_TYPE,
3655  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_154_WIDTH },
3656  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_155_CHECKER_TYPE,
3657  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_155_WIDTH },
3658  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_156_CHECKER_TYPE,
3659  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_156_WIDTH },
3660  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_157_CHECKER_TYPE,
3661  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_157_WIDTH },
3662  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_158_CHECKER_TYPE,
3663  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_158_WIDTH },
3664  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_159_CHECKER_TYPE,
3665  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_159_WIDTH },
3666  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_160_CHECKER_TYPE,
3667  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_160_WIDTH },
3668  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_161_CHECKER_TYPE,
3669  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_161_WIDTH },
3670  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_162_CHECKER_TYPE,
3671  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_162_WIDTH },
3672  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_163_CHECKER_TYPE,
3673  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_163_WIDTH },
3674  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_164_CHECKER_TYPE,
3675  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_164_WIDTH },
3676  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_165_CHECKER_TYPE,
3677  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_165_WIDTH },
3678  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_166_CHECKER_TYPE,
3679  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_166_WIDTH },
3680  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_167_CHECKER_TYPE,
3681  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_167_WIDTH },
3682  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_168_CHECKER_TYPE,
3683  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_168_WIDTH },
3684  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_169_CHECKER_TYPE,
3685  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_169_WIDTH },
3686  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_170_CHECKER_TYPE,
3687  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_170_WIDTH },
3688  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_171_CHECKER_TYPE,
3689  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_171_WIDTH },
3690  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_172_CHECKER_TYPE,
3691  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_172_WIDTH },
3692  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_173_CHECKER_TYPE,
3693  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_173_WIDTH },
3694  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_174_CHECKER_TYPE,
3695  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_174_WIDTH },
3696  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_175_CHECKER_TYPE,
3697  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_175_WIDTH },
3698  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_176_CHECKER_TYPE,
3699  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_176_WIDTH },
3700  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_177_CHECKER_TYPE,
3701  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_177_WIDTH },
3702  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_178_CHECKER_TYPE,
3703  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_178_WIDTH },
3704  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_179_CHECKER_TYPE,
3705  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_179_WIDTH },
3706  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_180_CHECKER_TYPE,
3707  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_180_WIDTH },
3708  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_181_CHECKER_TYPE,
3709  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_181_WIDTH },
3710  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_182_CHECKER_TYPE,
3711  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_182_WIDTH },
3712  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_183_CHECKER_TYPE,
3713  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_183_WIDTH },
3714  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_184_CHECKER_TYPE,
3715  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_184_WIDTH },
3716  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_185_CHECKER_TYPE,
3717  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_185_WIDTH },
3718  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_186_CHECKER_TYPE,
3719  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_186_WIDTH },
3720  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_187_CHECKER_TYPE,
3721  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_187_WIDTH },
3722  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_188_CHECKER_TYPE,
3723  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_188_WIDTH },
3724  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_189_CHECKER_TYPE,
3725  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_189_WIDTH },
3726  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_190_CHECKER_TYPE,
3727  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_190_WIDTH },
3728  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_191_CHECKER_TYPE,
3729  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_191_WIDTH },
3730  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_192_CHECKER_TYPE,
3731  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_192_WIDTH },
3732  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_193_CHECKER_TYPE,
3733  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_193_WIDTH },
3734  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_194_CHECKER_TYPE,
3735  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_194_WIDTH },
3736  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_195_CHECKER_TYPE,
3737  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_195_WIDTH },
3738  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_196_CHECKER_TYPE,
3739  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_196_WIDTH },
3740  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_197_CHECKER_TYPE,
3741  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_197_WIDTH },
3742  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_198_CHECKER_TYPE,
3743  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_198_WIDTH },
3744  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_199_CHECKER_TYPE,
3745  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_199_WIDTH },
3746  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_200_CHECKER_TYPE,
3747  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_200_WIDTH },
3748  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_201_CHECKER_TYPE,
3749  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_201_WIDTH },
3750  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_202_CHECKER_TYPE,
3751  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_202_WIDTH },
3752  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_203_CHECKER_TYPE,
3753  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_203_WIDTH },
3754  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_204_CHECKER_TYPE,
3755  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_204_WIDTH },
3756  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_205_CHECKER_TYPE,
3757  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_205_WIDTH },
3758  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_206_CHECKER_TYPE,
3759  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_206_WIDTH },
3760  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_207_CHECKER_TYPE,
3761  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_207_WIDTH },
3762  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_208_CHECKER_TYPE,
3763  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_208_WIDTH },
3764  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_209_CHECKER_TYPE,
3765  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_209_WIDTH },
3766  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_210_CHECKER_TYPE,
3767  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_210_WIDTH },
3768  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_211_CHECKER_TYPE,
3769  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_211_WIDTH },
3770  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_212_CHECKER_TYPE,
3771  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_212_WIDTH },
3772  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_213_CHECKER_TYPE,
3773  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_213_WIDTH },
3774  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_214_CHECKER_TYPE,
3775  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_214_WIDTH },
3776  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_215_CHECKER_TYPE,
3777  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_215_WIDTH },
3778  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_216_CHECKER_TYPE,
3779  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_216_WIDTH },
3780  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_217_CHECKER_TYPE,
3781  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_217_WIDTH },
3782  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_218_CHECKER_TYPE,
3783  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_218_WIDTH },
3784  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_219_CHECKER_TYPE,
3785  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_219_WIDTH },
3786  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_220_CHECKER_TYPE,
3787  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_220_WIDTH },
3788  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_221_CHECKER_TYPE,
3789  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_221_WIDTH },
3790  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_222_CHECKER_TYPE,
3791  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_222_WIDTH },
3792  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_223_CHECKER_TYPE,
3793  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_223_WIDTH },
3794  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_224_CHECKER_TYPE,
3795  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_224_WIDTH },
3796  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_225_CHECKER_TYPE,
3797  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_225_WIDTH },
3798  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_226_CHECKER_TYPE,
3799  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_226_WIDTH },
3800  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_227_CHECKER_TYPE,
3801  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_227_WIDTH },
3802  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_228_CHECKER_TYPE,
3803  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_228_WIDTH },
3804  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_229_CHECKER_TYPE,
3805  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_229_WIDTH },
3806  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_230_CHECKER_TYPE,
3807  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_230_WIDTH },
3808  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_231_CHECKER_TYPE,
3809  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_231_WIDTH },
3810  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_232_CHECKER_TYPE,
3811  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_232_WIDTH },
3812  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_233_CHECKER_TYPE,
3813  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_233_WIDTH },
3814  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_234_CHECKER_TYPE,
3815  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_234_WIDTH },
3816  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_235_CHECKER_TYPE,
3817  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_235_WIDTH },
3818  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_236_CHECKER_TYPE,
3819  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_236_WIDTH },
3820  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_237_CHECKER_TYPE,
3821  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_237_WIDTH },
3822  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_238_CHECKER_TYPE,
3823  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_238_WIDTH },
3824  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_239_CHECKER_TYPE,
3825  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_239_WIDTH },
3826  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_240_CHECKER_TYPE,
3827  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_240_WIDTH },
3828  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_241_CHECKER_TYPE,
3829  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_241_WIDTH },
3830  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_242_CHECKER_TYPE,
3831  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_242_WIDTH },
3832  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_243_CHECKER_TYPE,
3833  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_243_WIDTH },
3834  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_244_CHECKER_TYPE,
3835  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_244_WIDTH },
3836  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_245_CHECKER_TYPE,
3837  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_245_WIDTH },
3838  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_246_CHECKER_TYPE,
3839  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_246_WIDTH },
3840  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_247_CHECKER_TYPE,
3841  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_247_WIDTH },
3842  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_248_CHECKER_TYPE,
3843  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_248_WIDTH },
3844  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_249_CHECKER_TYPE,
3845  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_249_WIDTH },
3846  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_250_CHECKER_TYPE,
3847  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_250_WIDTH },
3848  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_251_CHECKER_TYPE,
3849  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_251_WIDTH },
3850  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_252_CHECKER_TYPE,
3851  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_252_WIDTH },
3852  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_253_CHECKER_TYPE,
3853  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_253_WIDTH },
3854  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_254_CHECKER_TYPE,
3855  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_254_WIDTH },
3856  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_255_CHECKER_TYPE,
3857  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_GROUP_255_WIDTH },
3858 };
3859 
3865 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_MAX_NUM_CHECKERS] =
3866 {
3867  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_0_CHECKER_TYPE,
3868  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_0_WIDTH },
3869  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_1_CHECKER_TYPE,
3870  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_1_WIDTH },
3871  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_2_CHECKER_TYPE,
3872  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_2_WIDTH },
3873  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_3_CHECKER_TYPE,
3874  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_3_WIDTH },
3875  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_4_CHECKER_TYPE,
3876  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_4_WIDTH },
3877  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_5_CHECKER_TYPE,
3878  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_5_WIDTH },
3879  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_6_CHECKER_TYPE,
3880  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_6_WIDTH },
3881  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_7_CHECKER_TYPE,
3882  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_7_WIDTH },
3883  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_8_CHECKER_TYPE,
3884  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_8_WIDTH },
3885  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_9_CHECKER_TYPE,
3886  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_9_WIDTH },
3887  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_10_CHECKER_TYPE,
3888  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_10_WIDTH },
3889  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_11_CHECKER_TYPE,
3890  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_11_WIDTH },
3891  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_12_CHECKER_TYPE,
3892  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_12_WIDTH },
3893  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_13_CHECKER_TYPE,
3894  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_13_WIDTH },
3895  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_14_CHECKER_TYPE,
3896  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_14_WIDTH },
3897  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_15_CHECKER_TYPE,
3898  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_15_WIDTH },
3899  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_16_CHECKER_TYPE,
3900  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_16_WIDTH },
3901  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_17_CHECKER_TYPE,
3902  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_17_WIDTH },
3903  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_18_CHECKER_TYPE,
3904  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_18_WIDTH },
3905  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_19_CHECKER_TYPE,
3906  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_19_WIDTH },
3907  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_20_CHECKER_TYPE,
3908  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_20_WIDTH },
3909  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_21_CHECKER_TYPE,
3910  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_21_WIDTH },
3911  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_22_CHECKER_TYPE,
3912  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_22_WIDTH },
3913  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_23_CHECKER_TYPE,
3914  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_23_WIDTH },
3915  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_24_CHECKER_TYPE,
3916  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_24_WIDTH },
3917  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_25_CHECKER_TYPE,
3918  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_25_WIDTH },
3919  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_26_CHECKER_TYPE,
3920  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_26_WIDTH },
3921  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_27_CHECKER_TYPE,
3922  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_27_WIDTH },
3923  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_28_CHECKER_TYPE,
3924  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_28_WIDTH },
3925  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_29_CHECKER_TYPE,
3926  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_29_WIDTH },
3927  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_30_CHECKER_TYPE,
3928  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_30_WIDTH },
3929  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_31_CHECKER_TYPE,
3930  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_31_WIDTH },
3931  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_32_CHECKER_TYPE,
3932  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_32_WIDTH },
3933  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_33_CHECKER_TYPE,
3934  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_33_WIDTH },
3935  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_34_CHECKER_TYPE,
3936  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_34_WIDTH },
3937  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_35_CHECKER_TYPE,
3938  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_35_WIDTH },
3939  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_36_CHECKER_TYPE,
3940  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_36_WIDTH },
3941  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_37_CHECKER_TYPE,
3942  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_37_WIDTH },
3943  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_38_CHECKER_TYPE,
3944  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_38_WIDTH },
3945  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_39_CHECKER_TYPE,
3946  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_39_WIDTH },
3947  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_40_CHECKER_TYPE,
3948  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_40_WIDTH },
3949  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_41_CHECKER_TYPE,
3950  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_41_WIDTH },
3951  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_42_CHECKER_TYPE,
3952  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_42_WIDTH },
3953  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_43_CHECKER_TYPE,
3954  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_43_WIDTH },
3955  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_44_CHECKER_TYPE,
3956  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_44_WIDTH },
3957  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_45_CHECKER_TYPE,
3958  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_45_WIDTH },
3959  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_46_CHECKER_TYPE,
3960  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_46_WIDTH },
3961  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_47_CHECKER_TYPE,
3962  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_47_WIDTH },
3963  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_48_CHECKER_TYPE,
3964  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_48_WIDTH },
3965  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_49_CHECKER_TYPE,
3966  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_49_WIDTH },
3967  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_50_CHECKER_TYPE,
3968  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_50_WIDTH },
3969  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_51_CHECKER_TYPE,
3970  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_51_WIDTH },
3971  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_52_CHECKER_TYPE,
3972  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_52_WIDTH },
3973  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_53_CHECKER_TYPE,
3974  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_53_WIDTH },
3975  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_54_CHECKER_TYPE,
3976  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_54_WIDTH },
3977  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_55_CHECKER_TYPE,
3978  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_55_WIDTH },
3979  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_56_CHECKER_TYPE,
3980  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_56_WIDTH },
3981  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_57_CHECKER_TYPE,
3982  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_57_WIDTH },
3983  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_58_CHECKER_TYPE,
3984  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_58_WIDTH },
3985  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_59_CHECKER_TYPE,
3986  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_59_WIDTH },
3987  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_60_CHECKER_TYPE,
3988  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_60_WIDTH },
3989  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_61_CHECKER_TYPE,
3990  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_61_WIDTH },
3991  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_62_CHECKER_TYPE,
3992  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_62_WIDTH },
3993  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_63_CHECKER_TYPE,
3994  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_63_WIDTH },
3995  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_64_CHECKER_TYPE,
3996  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_64_WIDTH },
3997  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_65_CHECKER_TYPE,
3998  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_65_WIDTH },
3999  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_66_CHECKER_TYPE,
4000  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_66_WIDTH },
4001  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_67_CHECKER_TYPE,
4002  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_67_WIDTH },
4003  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_68_CHECKER_TYPE,
4004  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_68_WIDTH },
4005  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_69_CHECKER_TYPE,
4006  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_69_WIDTH },
4007  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_70_CHECKER_TYPE,
4008  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_70_WIDTH },
4009  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_71_CHECKER_TYPE,
4010  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_71_WIDTH },
4011  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_72_CHECKER_TYPE,
4012  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_72_WIDTH },
4013  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_73_CHECKER_TYPE,
4014  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_73_WIDTH },
4015  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_74_CHECKER_TYPE,
4016  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_74_WIDTH },
4017  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_75_CHECKER_TYPE,
4018  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_75_WIDTH },
4019  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_76_CHECKER_TYPE,
4020  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_76_WIDTH },
4021  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_77_CHECKER_TYPE,
4022  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_77_WIDTH },
4023  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_78_CHECKER_TYPE,
4024  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_78_WIDTH },
4025  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_79_CHECKER_TYPE,
4026  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_79_WIDTH },
4027  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_80_CHECKER_TYPE,
4028  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_80_WIDTH },
4029  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_81_CHECKER_TYPE,
4030  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_81_WIDTH },
4031  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_82_CHECKER_TYPE,
4032  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_82_WIDTH },
4033  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_83_CHECKER_TYPE,
4034  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_83_WIDTH },
4035  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_84_CHECKER_TYPE,
4036  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_84_WIDTH },
4037  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_85_CHECKER_TYPE,
4038  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_85_WIDTH },
4039  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_86_CHECKER_TYPE,
4040  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_86_WIDTH },
4041  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_87_CHECKER_TYPE,
4042  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_87_WIDTH },
4043  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_88_CHECKER_TYPE,
4044  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_88_WIDTH },
4045  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_89_CHECKER_TYPE,
4046  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_89_WIDTH },
4047  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_90_CHECKER_TYPE,
4048  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_90_WIDTH },
4049  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_91_CHECKER_TYPE,
4050  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_91_WIDTH },
4051  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_92_CHECKER_TYPE,
4052  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_92_WIDTH },
4053  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_93_CHECKER_TYPE,
4054  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_93_WIDTH },
4055  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_94_CHECKER_TYPE,
4056  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_94_WIDTH },
4057  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_95_CHECKER_TYPE,
4058  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_95_WIDTH },
4059  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_96_CHECKER_TYPE,
4060  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_96_WIDTH },
4061  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_97_CHECKER_TYPE,
4062  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_97_WIDTH },
4063  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_98_CHECKER_TYPE,
4064  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_98_WIDTH },
4065  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_99_CHECKER_TYPE,
4066  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_99_WIDTH },
4067  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_100_CHECKER_TYPE,
4068  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_100_WIDTH },
4069  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_101_CHECKER_TYPE,
4070  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_101_WIDTH },
4071  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_102_CHECKER_TYPE,
4072  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_102_WIDTH },
4073  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_103_CHECKER_TYPE,
4074  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_103_WIDTH },
4075  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_104_CHECKER_TYPE,
4076  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_104_WIDTH },
4077  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_105_CHECKER_TYPE,
4078  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_105_WIDTH },
4079  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_106_CHECKER_TYPE,
4080  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_106_WIDTH },
4081  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_107_CHECKER_TYPE,
4082  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_107_WIDTH },
4083  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_108_CHECKER_TYPE,
4084  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_108_WIDTH },
4085  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_109_CHECKER_TYPE,
4086  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_109_WIDTH },
4087  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_110_CHECKER_TYPE,
4088  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_110_WIDTH },
4089  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_111_CHECKER_TYPE,
4090  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_111_WIDTH },
4091  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_112_CHECKER_TYPE,
4092  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_112_WIDTH },
4093  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_113_CHECKER_TYPE,
4094  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_113_WIDTH },
4095  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_114_CHECKER_TYPE,
4096  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_114_WIDTH },
4097  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_115_CHECKER_TYPE,
4098  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_115_WIDTH },
4099  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_116_CHECKER_TYPE,
4100  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_116_WIDTH },
4101  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_117_CHECKER_TYPE,
4102  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_117_WIDTH },
4103  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_118_CHECKER_TYPE,
4104  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_118_WIDTH },
4105  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_119_CHECKER_TYPE,
4106  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_119_WIDTH },
4107  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_120_CHECKER_TYPE,
4108  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_120_WIDTH },
4109  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_121_CHECKER_TYPE,
4110  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_121_WIDTH },
4111  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_122_CHECKER_TYPE,
4112  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_122_WIDTH },
4113  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_123_CHECKER_TYPE,
4114  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_123_WIDTH },
4115  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_124_CHECKER_TYPE,
4116  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_124_WIDTH },
4117  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_125_CHECKER_TYPE,
4118  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_125_WIDTH },
4119  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_126_CHECKER_TYPE,
4120  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_126_WIDTH },
4121  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_127_CHECKER_TYPE,
4122  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_127_WIDTH },
4123  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_128_CHECKER_TYPE,
4124  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_128_WIDTH },
4125  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_129_CHECKER_TYPE,
4126  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_129_WIDTH },
4127  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_130_CHECKER_TYPE,
4128  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_130_WIDTH },
4129  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_131_CHECKER_TYPE,
4130  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_131_WIDTH },
4131  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_132_CHECKER_TYPE,
4132  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_132_WIDTH },
4133  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_133_CHECKER_TYPE,
4134  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_133_WIDTH },
4135  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_134_CHECKER_TYPE,
4136  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_134_WIDTH },
4137  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_135_CHECKER_TYPE,
4138  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_135_WIDTH },
4139  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_136_CHECKER_TYPE,
4140  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_136_WIDTH },
4141  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_137_CHECKER_TYPE,
4142  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_137_WIDTH },
4143  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_138_CHECKER_TYPE,
4144  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_138_WIDTH },
4145  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_139_CHECKER_TYPE,
4146  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_139_WIDTH },
4147  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_140_CHECKER_TYPE,
4148  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_140_WIDTH },
4149  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_141_CHECKER_TYPE,
4150  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_141_WIDTH },
4151  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_142_CHECKER_TYPE,
4152  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_142_WIDTH },
4153  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_143_CHECKER_TYPE,
4154  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_143_WIDTH },
4155  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_144_CHECKER_TYPE,
4156  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_144_WIDTH },
4157  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_145_CHECKER_TYPE,
4158  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_145_WIDTH },
4159  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_146_CHECKER_TYPE,
4160  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_146_WIDTH },
4161  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_147_CHECKER_TYPE,
4162  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_147_WIDTH },
4163  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_148_CHECKER_TYPE,
4164  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_148_WIDTH },
4165  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_149_CHECKER_TYPE,
4166  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_149_WIDTH },
4167  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_150_CHECKER_TYPE,
4168  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_150_WIDTH },
4169  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_151_CHECKER_TYPE,
4170  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_151_WIDTH },
4171  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_152_CHECKER_TYPE,
4172  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_152_WIDTH },
4173  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_153_CHECKER_TYPE,
4174  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_153_WIDTH },
4175  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_154_CHECKER_TYPE,
4176  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_154_WIDTH },
4177  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_155_CHECKER_TYPE,
4178  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_155_WIDTH },
4179  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_156_CHECKER_TYPE,
4180  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_156_WIDTH },
4181  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_157_CHECKER_TYPE,
4182  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_157_WIDTH },
4183  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_158_CHECKER_TYPE,
4184  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_158_WIDTH },
4185  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_159_CHECKER_TYPE,
4186  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_159_WIDTH },
4187  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_160_CHECKER_TYPE,
4188  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_160_WIDTH },
4189  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_161_CHECKER_TYPE,
4190  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_161_WIDTH },
4191  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_162_CHECKER_TYPE,
4192  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_162_WIDTH },
4193  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_163_CHECKER_TYPE,
4194  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_163_WIDTH },
4195  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_164_CHECKER_TYPE,
4196  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_164_WIDTH },
4197  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_165_CHECKER_TYPE,
4198  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_165_WIDTH },
4199  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_166_CHECKER_TYPE,
4200  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_166_WIDTH },
4201  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_167_CHECKER_TYPE,
4202  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_167_WIDTH },
4203  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_168_CHECKER_TYPE,
4204  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_168_WIDTH },
4205  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_169_CHECKER_TYPE,
4206  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_169_WIDTH },
4207  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_170_CHECKER_TYPE,
4208  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_170_WIDTH },
4209  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_171_CHECKER_TYPE,
4210  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_171_WIDTH },
4211  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_172_CHECKER_TYPE,
4212  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_172_WIDTH },
4213  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_173_CHECKER_TYPE,
4214  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_173_WIDTH },
4215  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_174_CHECKER_TYPE,
4216  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_174_WIDTH },
4217  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_175_CHECKER_TYPE,
4218  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_175_WIDTH },
4219  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_176_CHECKER_TYPE,
4220  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_176_WIDTH },
4221  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_177_CHECKER_TYPE,
4222  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_177_WIDTH },
4223  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_178_CHECKER_TYPE,
4224  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_178_WIDTH },
4225  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_179_CHECKER_TYPE,
4226  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_179_WIDTH },
4227  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_180_CHECKER_TYPE,
4228  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_180_WIDTH },
4229  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_181_CHECKER_TYPE,
4230  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_181_WIDTH },
4231  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_182_CHECKER_TYPE,
4232  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_182_WIDTH },
4233  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_183_CHECKER_TYPE,
4234  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_183_WIDTH },
4235  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_184_CHECKER_TYPE,
4236  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_184_WIDTH },
4237  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_185_CHECKER_TYPE,
4238  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_185_WIDTH },
4239  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_186_CHECKER_TYPE,
4240  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_186_WIDTH },
4241  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_187_CHECKER_TYPE,
4242  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_187_WIDTH },
4243  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_188_CHECKER_TYPE,
4244  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_188_WIDTH },
4245  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_189_CHECKER_TYPE,
4246  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_189_WIDTH },
4247  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_190_CHECKER_TYPE,
4248  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_190_WIDTH },
4249  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_191_CHECKER_TYPE,
4250  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_191_WIDTH },
4251  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_192_CHECKER_TYPE,
4252  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_192_WIDTH },
4253  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_193_CHECKER_TYPE,
4254  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_193_WIDTH },
4255  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_194_CHECKER_TYPE,
4256  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_194_WIDTH },
4257  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_195_CHECKER_TYPE,
4258  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_195_WIDTH },
4259  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_196_CHECKER_TYPE,
4260  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_196_WIDTH },
4261  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_197_CHECKER_TYPE,
4262  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_197_WIDTH },
4263  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_198_CHECKER_TYPE,
4264  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_198_WIDTH },
4265  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_199_CHECKER_TYPE,
4266  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_199_WIDTH },
4267  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_200_CHECKER_TYPE,
4268  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_200_WIDTH },
4269  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_201_CHECKER_TYPE,
4270  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_201_WIDTH },
4271  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_202_CHECKER_TYPE,
4272  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_202_WIDTH },
4273  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_203_CHECKER_TYPE,
4274  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_203_WIDTH },
4275  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_204_CHECKER_TYPE,
4276  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_204_WIDTH },
4277  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_205_CHECKER_TYPE,
4278  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_205_WIDTH },
4279  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_206_CHECKER_TYPE,
4280  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_206_WIDTH },
4281  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_207_CHECKER_TYPE,
4282  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_207_WIDTH },
4283  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_208_CHECKER_TYPE,
4284  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_208_WIDTH },
4285  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_209_CHECKER_TYPE,
4286  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_209_WIDTH },
4287  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_210_CHECKER_TYPE,
4288  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_210_WIDTH },
4289  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_211_CHECKER_TYPE,
4290  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_211_WIDTH },
4291  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_212_CHECKER_TYPE,
4292  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_212_WIDTH },
4293  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_213_CHECKER_TYPE,
4294  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_213_WIDTH },
4295  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_214_CHECKER_TYPE,
4296  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_214_WIDTH },
4297  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_215_CHECKER_TYPE,
4298  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_215_WIDTH },
4299  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_216_CHECKER_TYPE,
4300  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_216_WIDTH },
4301  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_217_CHECKER_TYPE,
4302  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_217_WIDTH },
4303  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_218_CHECKER_TYPE,
4304  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_218_WIDTH },
4305  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_219_CHECKER_TYPE,
4306  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_219_WIDTH },
4307  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_220_CHECKER_TYPE,
4308  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_220_WIDTH },
4309  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_221_CHECKER_TYPE,
4310  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_221_WIDTH },
4311  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_222_CHECKER_TYPE,
4312  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_222_WIDTH },
4313  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_223_CHECKER_TYPE,
4314  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_223_WIDTH },
4315  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_224_CHECKER_TYPE,
4316  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_224_WIDTH },
4317  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_225_CHECKER_TYPE,
4318  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_225_WIDTH },
4319  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_226_CHECKER_TYPE,
4320  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_226_WIDTH },
4321  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_227_CHECKER_TYPE,
4322  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_227_WIDTH },
4323  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_228_CHECKER_TYPE,
4324  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_228_WIDTH },
4325  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_229_CHECKER_TYPE,
4326  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_229_WIDTH },
4327  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_230_CHECKER_TYPE,
4328  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_230_WIDTH },
4329  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_231_CHECKER_TYPE,
4330  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_231_WIDTH },
4331  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_232_CHECKER_TYPE,
4332  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_232_WIDTH },
4333  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_233_CHECKER_TYPE,
4334  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_233_WIDTH },
4335  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_234_CHECKER_TYPE,
4336  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_234_WIDTH },
4337  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_235_CHECKER_TYPE,
4338  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_235_WIDTH },
4339  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_236_CHECKER_TYPE,
4340  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_236_WIDTH },
4341  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_237_CHECKER_TYPE,
4342  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_237_WIDTH },
4343  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_238_CHECKER_TYPE,
4344  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_238_WIDTH },
4345  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_239_CHECKER_TYPE,
4346  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_239_WIDTH },
4347  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_240_CHECKER_TYPE,
4348  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_240_WIDTH },
4349  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_241_CHECKER_TYPE,
4350  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_241_WIDTH },
4351  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_242_CHECKER_TYPE,
4352  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_242_WIDTH },
4353  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_243_CHECKER_TYPE,
4354  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_243_WIDTH },
4355  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_244_CHECKER_TYPE,
4356  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_244_WIDTH },
4357  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_245_CHECKER_TYPE,
4358  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_245_WIDTH },
4359  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_246_CHECKER_TYPE,
4360  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_246_WIDTH },
4361  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_247_CHECKER_TYPE,
4362  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_247_WIDTH },
4363  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_248_CHECKER_TYPE,
4364  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_248_WIDTH },
4365  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_249_CHECKER_TYPE,
4366  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_249_WIDTH },
4367  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_250_CHECKER_TYPE,
4368  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_250_WIDTH },
4369  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_251_CHECKER_TYPE,
4370  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_251_WIDTH },
4371  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_252_CHECKER_TYPE,
4372  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_252_WIDTH },
4373  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_253_CHECKER_TYPE,
4374  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_253_WIDTH },
4375  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_254_CHECKER_TYPE,
4376  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_254_WIDTH },
4377  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_255_CHECKER_TYPE,
4378  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_GROUP_255_WIDTH },
4379 };
4380 
4386 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS] =
4387 {
4388  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4389  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_0_WIDTH },
4390  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4391  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_1_WIDTH },
4392  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4393  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_2_WIDTH },
4394  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4395  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_3_WIDTH },
4396  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4397  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_4_WIDTH },
4398  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4399  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_5_WIDTH },
4400  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4401  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_6_WIDTH },
4402  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4403  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_7_WIDTH },
4404  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4405  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_8_WIDTH },
4406  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4407  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_9_WIDTH },
4408  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4409  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_10_WIDTH },
4410  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4411  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_11_WIDTH },
4412  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4413  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_12_WIDTH },
4414  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4415  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_13_WIDTH },
4416  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4417  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_14_WIDTH },
4418  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4419  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_15_WIDTH },
4420  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4421  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_16_WIDTH },
4422  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4423  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_17_WIDTH },
4424  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4425  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_18_WIDTH },
4426  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4427  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_19_WIDTH },
4428  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4429  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_20_WIDTH },
4430  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4431  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_GROUP_21_WIDTH },
4432 };
4433 
4439 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
4440 {
4441  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4442  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
4443  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4444  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
4445  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4446  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
4447  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4448  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
4449 };
4450 
4455 static const SDL_MemConfig_t SDL_PCIE2_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES] =
4456 {
4457  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
4458  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
4459  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
4460  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
4461  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
4462  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
4463  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
4464  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
4465  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
4466  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
4467  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
4468  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
4469  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
4470  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
4471  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
4472  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
4473  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
4474  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
4475  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
4476  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
4477  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
4478 };
4479 
4484 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
4485 {
4486  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
4487  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
4488  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4489  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
4490  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
4491  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4492  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
4493  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
4494  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4495  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
4496  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
4497  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4498  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
4499  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
4500  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4501  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
4502  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
4503  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4504  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
4505  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
4506  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4507  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
4508  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
4509  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4510  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
4511  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
4512  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4513  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
4514  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
4515  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4516  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
4517  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
4518  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4519  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
4520  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
4521  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4522  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
4523  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
4524  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4525  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
4526  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
4527  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4528  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
4529  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
4530  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4531  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
4532  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
4533  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4534  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
4535  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
4536  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4537  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
4538  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
4539  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4540  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
4541  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
4542  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4543  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
4544  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
4545  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4546  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK8_ECC_SVBUS_RAM_ID, 0u,
4547  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK8_ECC_SVBUS_RAM_SIZE, 4u,
4548  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK8_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4549  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK9_ECC_SVBUS_RAM_ID, 0u,
4550  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK9_ECC_SVBUS_RAM_SIZE, 4u,
4551  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK9_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4552  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK10_ECC_SVBUS_RAM_ID, 0u,
4553  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK10_ECC_SVBUS_RAM_SIZE, 4u,
4554  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK10_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4555  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK11_ECC_SVBUS_RAM_ID, 0u,
4556  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK11_ECC_SVBUS_RAM_SIZE, 4u,
4557  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK11_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4558  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK12_ECC_SVBUS_RAM_ID, 0u,
4559  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK12_ECC_SVBUS_RAM_SIZE, 4u,
4560  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK12_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4561  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK13_ECC_SVBUS_RAM_ID, 0u,
4562  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK13_ECC_SVBUS_RAM_SIZE, 4u,
4563  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK13_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4564  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK14_ECC_SVBUS_RAM_ID, 0u,
4565  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK14_ECC_SVBUS_RAM_SIZE, 4u,
4566  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK14_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4567  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK15_ECC_SVBUS_RAM_ID, 0u,
4568  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK15_ECC_SVBUS_RAM_SIZE, 4u,
4569  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK15_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4570  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
4571  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
4572  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4573  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
4574  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
4575  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4576  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
4577  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
4578  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4579  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
4580  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
4581  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
4582 };
4583 
4589 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS] =
4590 {
4591  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_CHECKER_TYPE,
4592  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_WIDTH },
4593  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_CHECKER_TYPE,
4594  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_WIDTH },
4595  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_CHECKER_TYPE,
4596  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_WIDTH },
4597  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_CHECKER_TYPE,
4598  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_WIDTH },
4599  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_CHECKER_TYPE,
4600  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_WIDTH },
4601  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_CHECKER_TYPE,
4602  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_WIDTH },
4603 };
4604 
4610 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
4611 {
4612  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
4613  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_0_WIDTH },
4614  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
4615  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_1_WIDTH },
4616  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
4617  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_GROUP_2_WIDTH },
4618 };
4619 
4625 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
4626 {
4627  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
4628  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_0_WIDTH },
4629  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
4630  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_1_WIDTH },
4631  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
4632  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_GROUP_2_WIDTH },
4633 };
4634 
4640 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
4641 {
4642  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
4643  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_0_WIDTH },
4644  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
4645  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_1_WIDTH },
4646  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
4647  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_GROUP_2_WIDTH },
4648 };
4649 
4655 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
4656 {
4657  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
4658  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
4659  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
4660  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
4661  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
4662  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
4663  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
4664  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
4665  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
4666  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
4667  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
4668  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
4669  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
4670  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
4671  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
4672  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
4673  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
4674  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
4675  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
4676  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
4677  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
4678  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
4679  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
4680  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
4681  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
4682  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
4683  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
4684  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
4685  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
4686  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
4687  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
4688  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
4689  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
4690  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
4691  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
4692  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
4693  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
4694  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
4695  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
4696  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
4697  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
4698  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
4699  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
4700  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
4701  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
4702  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
4703  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
4704  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
4705  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
4706  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
4707  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
4708  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
4709  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
4710  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
4711  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
4712  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
4713  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
4714  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
4715  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
4716  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
4717  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
4718  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
4719  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
4720  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
4721  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
4722  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
4723  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
4724  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
4725  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
4726  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
4727  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
4728  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
4729  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
4730  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
4731  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
4732  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
4733  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
4734  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
4735  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
4736  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
4737  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
4738  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
4739  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
4740  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
4741  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
4742  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
4743  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
4744  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
4745  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
4746  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
4747  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
4748  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
4749  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
4750  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
4751  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
4752  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
4753  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
4754  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
4755  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
4756  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
4757  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
4758  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
4759  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
4760  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
4761  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
4762  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
4763  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
4764  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
4765  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
4766  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
4767  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
4768  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
4769  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
4770  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
4771  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
4772  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
4773  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
4774  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
4775  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
4776  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
4777  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
4778  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
4779  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
4780  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
4781  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
4782  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
4783  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
4784  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
4785  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
4786  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
4787  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
4788  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
4789  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
4790  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
4791  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
4792  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
4793  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
4794  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
4795  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
4796  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
4797  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
4798  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
4799  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
4800  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
4801  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
4802  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
4803  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
4804  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
4805  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
4806  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
4807  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
4808  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
4809  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
4810  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
4811  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
4812  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
4813  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
4814  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
4815  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
4816  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
4817  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
4818  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
4819  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
4820  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
4821  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
4822  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
4823  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
4824  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
4825  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
4826  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
4827  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
4828  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
4829  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
4830  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
4831  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
4832  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
4833  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
4834  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
4835  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
4836  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
4837  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
4838  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
4839  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
4840  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
4841  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
4842  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
4843  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
4844  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
4845  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
4846  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
4847  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
4848  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
4849  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
4850  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
4851  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
4852  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
4853  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
4854  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
4855  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
4856  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
4857  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
4858  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
4859  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
4860  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
4861  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
4862  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
4863  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
4864  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
4865  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
4866  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
4867 };
4868 
4874 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_MAX_NUM_CHECKERS] =
4875 {
4876  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_0_CHECKER_TYPE,
4877  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_0_WIDTH },
4878  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_1_CHECKER_TYPE,
4879  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_1_WIDTH },
4880  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_2_CHECKER_TYPE,
4881  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_2_WIDTH },
4882  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_3_CHECKER_TYPE,
4883  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_3_WIDTH },
4884  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_4_CHECKER_TYPE,
4885  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_4_WIDTH },
4886  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_5_CHECKER_TYPE,
4887  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_5_WIDTH },
4888  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_6_CHECKER_TYPE,
4889  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_6_WIDTH },
4890  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_7_CHECKER_TYPE,
4891  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_7_WIDTH },
4892  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_8_CHECKER_TYPE,
4893  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_8_WIDTH },
4894  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_9_CHECKER_TYPE,
4895  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_9_WIDTH },
4896  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_10_CHECKER_TYPE,
4897  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_10_WIDTH },
4898  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_11_CHECKER_TYPE,
4899  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_11_WIDTH },
4900  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_12_CHECKER_TYPE,
4901  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_GROUP_12_WIDTH },
4902 };
4903 
4909 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
4910 {
4911  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
4912  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_0_WIDTH },
4913  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
4914  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_1_WIDTH },
4915  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
4916  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_2_WIDTH },
4917  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
4918  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_3_WIDTH },
4919  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
4920  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_4_WIDTH },
4921  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
4922  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_5_WIDTH },
4923  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
4924  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_6_WIDTH },
4925  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
4926  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_7_WIDTH },
4927  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
4928  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_8_WIDTH },
4929  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
4930  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_9_WIDTH },
4931  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
4932  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_10_WIDTH },
4933  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
4934  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_11_WIDTH },
4935  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
4936  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_12_WIDTH },
4937  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
4938  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_13_WIDTH },
4939  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
4940  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_14_WIDTH },
4941 };
4942 
4948 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS] =
4949 {
4950  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
4951  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_WIDTH },
4952  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
4953  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_WIDTH },
4954  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
4955  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_WIDTH },
4956  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
4957  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_WIDTH },
4958 };
4959 
4965 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS] =
4966 {
4967  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
4968  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_0_WIDTH },
4969  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
4970  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_1_WIDTH },
4971  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
4972  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_2_WIDTH },
4973  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
4974  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_3_WIDTH },
4975  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
4976  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_4_WIDTH },
4977  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
4978  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_5_WIDTH },
4979  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
4980  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_6_WIDTH },
4981  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
4982  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_7_WIDTH },
4983  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
4984  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_8_WIDTH },
4985  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
4986  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_9_WIDTH },
4987  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
4988  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_10_WIDTH },
4989  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
4990  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_11_WIDTH },
4991  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
4992  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_12_WIDTH },
4993  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
4994  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_13_WIDTH },
4995  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
4996  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_14_WIDTH },
4997  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
4998  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_15_WIDTH },
4999  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
5000  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_16_WIDTH },
5001  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
5002  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_17_WIDTH },
5003  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
5004  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_18_WIDTH },
5005  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
5006  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_19_WIDTH },
5007  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
5008  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_20_WIDTH },
5009  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
5010  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_21_WIDTH },
5011  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
5012  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_22_WIDTH },
5013  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
5014  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_23_WIDTH },
5015  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
5016  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_24_WIDTH },
5017  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
5018  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_25_WIDTH },
5019  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
5020  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_26_WIDTH },
5021  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
5022  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_27_WIDTH },
5023  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
5024  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_28_WIDTH },
5025  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
5026  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_29_WIDTH },
5027  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
5028  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_30_WIDTH },
5029  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
5030  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_31_WIDTH },
5031  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
5032  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_32_WIDTH },
5033  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
5034  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_33_WIDTH },
5035  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
5036  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_34_WIDTH },
5037  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
5038  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_35_WIDTH },
5039  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
5040  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_36_WIDTH },
5041  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
5042  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_37_WIDTH },
5043  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
5044  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_38_WIDTH },
5045  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
5046  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_39_WIDTH },
5047  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
5048  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_40_WIDTH },
5049 };
5050 
5056 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS] =
5057 {
5058  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
5059  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_0_WIDTH },
5060  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
5061  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_1_WIDTH },
5062  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
5063  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_2_WIDTH },
5064  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
5065  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_3_WIDTH },
5066  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_4_CHECKER_TYPE,
5067  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_4_WIDTH },
5068  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_5_CHECKER_TYPE,
5069  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_5_WIDTH },
5070  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_6_CHECKER_TYPE,
5071  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_6_WIDTH },
5072  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_7_CHECKER_TYPE,
5073  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_7_WIDTH },
5074  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_8_CHECKER_TYPE,
5075  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_8_WIDTH },
5076  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_9_CHECKER_TYPE,
5077  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_9_WIDTH },
5078  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_10_CHECKER_TYPE,
5079  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_10_WIDTH },
5080  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_11_CHECKER_TYPE,
5081  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_11_WIDTH },
5082  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_12_CHECKER_TYPE,
5083  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_12_WIDTH },
5084  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_13_CHECKER_TYPE,
5085  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_13_WIDTH },
5086 };
5087 
5093 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5094 {
5095  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5096  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
5097  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5098  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
5099  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5100  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
5101  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5102  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
5103  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5104  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
5105  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5106  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
5107 };
5108 
5114 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5115 {
5116  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5117  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
5118  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5119  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
5120  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5121  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
5122  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5123  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
5124  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5125  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
5126  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5127  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
5128  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5129  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
5130  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5131  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
5132  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5133  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
5134  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5135  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
5136  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5137  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
5138  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5139  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
5140  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5141  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
5142  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5143  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
5144  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5145  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
5146  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5147  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
5148  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5149  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
5150  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5151  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
5152  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5153  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
5154  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5155  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
5156  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5157  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
5158  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5159  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
5160  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5161  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
5162  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5163  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
5164  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5165  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
5166  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5167  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
5168  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5169  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
5170  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5171  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
5172  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5173  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
5174  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5175  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
5176  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5177  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
5178  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5179  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
5180  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5181  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
5182  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5183  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
5184  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5185  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
5186  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5187  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
5188  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5189  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
5190  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5191  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
5192  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5193  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
5194  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5195  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
5196  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5197  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
5198  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5199  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
5200  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5201  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
5202  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5203  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
5204  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5205  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
5206  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5207  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
5208  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5209  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
5210  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5211  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
5212  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5213  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
5214  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5215  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
5216  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
5217  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
5218  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
5219  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
5220  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
5221  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
5222  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
5223  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
5224  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
5225  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
5226  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
5227  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
5228  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
5229  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
5230  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
5231  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
5232  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
5233  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
5234  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
5235  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
5236  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
5237  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
5238  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
5239  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
5240  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
5241  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
5242  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
5243  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
5244  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
5245  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
5246  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
5247  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
5248  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
5249  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
5250  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
5251  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
5252  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
5253  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
5254  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
5255  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
5256  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
5257  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
5258  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
5259  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
5260  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
5261  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
5262  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
5263  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
5264  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
5265  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
5266  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
5267  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
5268  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
5269  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
5270  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
5271  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
5272  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
5273  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
5274  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
5275  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
5276  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
5277  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
5278  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
5279  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
5280  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
5281  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
5282  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
5283  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
5284  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
5285  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
5286  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
5287  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
5288  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
5289  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
5290  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
5291  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
5292  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
5293  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
5294  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
5295  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
5296  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
5297  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
5298  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
5299  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
5300  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
5301  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
5302  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
5303  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
5304  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
5305  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
5306  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
5307  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
5308  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
5309  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
5310  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
5311  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
5312  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
5313  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
5314  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
5315  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
5316  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
5317  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
5318  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
5319  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
5320  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
5321  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
5322  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
5323  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
5324  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
5325  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
5326  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
5327  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
5328  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
5329  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
5330  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
5331  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
5332  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
5333  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
5334  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
5335  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
5336  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
5337  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
5338  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
5339  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
5340  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
5341  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
5342  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
5343  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
5344  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
5345  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
5346  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
5347  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
5348  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
5349  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
5350  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
5351  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
5352  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
5353  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
5354  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
5355  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
5356  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
5357  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
5358  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
5359  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
5360  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
5361  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
5362  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
5363  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
5364  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
5365  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
5366  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
5367  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
5368  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
5369  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
5370  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
5371  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
5372  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
5373  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
5374  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
5375  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
5376  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
5377  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
5378  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
5379  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
5380  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
5381  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
5382  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
5383  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
5384  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
5385  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
5386  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
5387  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
5388  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
5389  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
5390  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
5391  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
5392  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
5393  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
5394  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
5395  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
5396  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
5397  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
5398  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
5399  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
5400  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
5401  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
5402  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
5403  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
5404  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
5405  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
5406  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
5407  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
5408  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
5409  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
5410  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
5411  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
5412  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
5413  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
5414  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
5415  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
5416  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
5417  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
5418  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
5419  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
5420  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
5421  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
5422  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
5423  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
5424  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
5425  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
5426  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
5427  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
5428  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
5429  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
5430  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
5431  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
5432  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
5433  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
5434  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
5435  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
5436  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
5437  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
5438  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
5439  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
5440  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
5441  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
5442  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
5443  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
5444  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
5445  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
5446  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
5447  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
5448  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
5449  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
5450  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
5451  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
5452  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
5453  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
5454  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
5455  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
5456  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
5457  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
5458 };
5459 
5465 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5466 {
5467  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5468  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
5469 };
5470 
5476 static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5477 {
5478  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5479  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
5480  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5481  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
5482  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5483  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
5484  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5485  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
5486  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5487  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
5488  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5489  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
5490  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5491  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
5492  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5493  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
5494  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5495  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
5496  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5497  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
5498  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5499  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
5500  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5501  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
5502  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5503  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
5504  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5505  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
5506  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5507  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
5508  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5509  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
5510  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5511  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
5512  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5513  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
5514  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5515  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
5516  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5517  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
5518  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5519  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
5520  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5521  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
5522  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5523  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
5524  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5525  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
5526  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5527  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
5528  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5529  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
5530  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5531  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
5532  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5533  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
5534  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5535  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
5536  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5537  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
5538  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5539  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
5540  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5541  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
5542  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5543  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
5544  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5545  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
5546  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5547  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
5548  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5549  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
5550  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5551  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
5552  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5553  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
5554  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5555  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
5556  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5557  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
5558  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5559  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
5560  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5561  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
5562  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5563  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
5564  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5565  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
5566  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5567  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
5568  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5569  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
5570  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5571  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
5572  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5573  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
5574  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5575  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
5576  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5577  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
5578 };
5579 
5584 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
5585 {
5586  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
5587  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
5588  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
5589 };
5590 
5595 static const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES] =
5596 {
5597  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_RAM_ID, 0u,
5598  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_RAM_SIZE, 4u,
5599  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
5600  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_RAM_ID, 0u,
5601  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_RAM_SIZE, 4u,
5602  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
5603 };
5604 
5610 static const SDL_GrpChkConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5611 {
5612  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5613  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_0_WIDTH },
5614  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5615  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_1_WIDTH },
5616  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5617  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_2_WIDTH },
5618  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5619  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_GROUP_3_WIDTH },
5620 };
5621 
5626 static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
5627 {
5628  { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID, 0u,
5629  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
5630  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
5631 };
5632 
5637 static const SDL_MemConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
5638 {
5639  { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2758000u,
5640  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
5641  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
5642 };
5643 
5649 static const SDL_GrpChkConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
5650 {
5651  { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
5652  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
5653 };
5654 
5659 static const SDL_MemConfig_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES] =
5660 {
5661  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
5662  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
5663  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
5664  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
5665  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
5666  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
5667  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
5668  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
5669  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
5670  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
5671  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
5672  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
5673  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
5674  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
5675  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
5676  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
5677  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
5678  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
5679  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
5680  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
5681  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
5682  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
5683  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
5684  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
5685 };
5686 
5692 static const SDL_GrpChkConfig_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5693 {
5694  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5695  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_WIDTH },
5696  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5697  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_WIDTH },
5698  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5699  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_WIDTH },
5700  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5701  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_WIDTH },
5702  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5703  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_WIDTH },
5704  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5705  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_WIDTH },
5706  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5707  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_WIDTH },
5708  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5709  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_WIDTH },
5710  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5711  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_WIDTH },
5712  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5713  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_WIDTH },
5714  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5715  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_WIDTH },
5716  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5717  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_WIDTH },
5718  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5719  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_WIDTH },
5720  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5721  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_WIDTH },
5722  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5723  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_WIDTH },
5724  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5725  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_WIDTH },
5726 };
5727 
5733 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5734 {
5735  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5736  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_0_WIDTH },
5737  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5738  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_1_WIDTH },
5739  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5740  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_2_WIDTH },
5741  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5742  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_GROUP_3_WIDTH },
5743 };
5744 
5750 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5751 {
5752  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5753  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
5754  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5755  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
5756  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5757  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
5758  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5759  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
5760  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5761  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
5762  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5763  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
5764  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5765  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
5766  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5767  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
5768  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5769  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
5770  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5771  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
5772  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5773  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
5774  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5775  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
5776  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5777  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
5778  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5779  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
5780  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5781  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
5782  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5783  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
5784  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5785  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
5786  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5787  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
5788  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5789  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
5790  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5791  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
5792  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5793  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
5794  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5795  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
5796  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5797  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
5798  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5799  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
5800  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5801  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
5802  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5803  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
5804  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5805  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
5806  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5807  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
5808  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5809  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
5810  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5811  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
5812  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5813  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
5814  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5815  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
5816  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5817  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
5818  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5819  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
5820  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5821  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
5822  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5823  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
5824  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5825  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
5826  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5827  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
5828  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5829  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
5830  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5831  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
5832  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5833  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
5834 };
5835 
5841 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5842 {
5843  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5844  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
5845  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5846  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
5847  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5848  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
5849  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5850  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
5851  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5852  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
5853  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5854  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
5855  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5856  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
5857  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5858  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
5859  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5860  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
5861  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5862  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
5863  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5864  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
5865  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5866  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
5867  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5868  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
5869  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5870  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
5871  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5872  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
5873 };
5874 
5880 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5881 {
5882  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5883  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
5884  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5885  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
5886  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5887  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
5888  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5889  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
5890  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5891  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_4_WIDTH },
5892  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5893  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_5_WIDTH },
5894  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5895  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_6_WIDTH },
5896  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5897  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_7_WIDTH },
5898  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5899  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_8_WIDTH },
5900  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5901  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_9_WIDTH },
5902  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5903  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_10_WIDTH },
5904  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5905  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_11_WIDTH },
5906  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5907  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_12_WIDTH },
5908  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5909  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_GROUP_13_WIDTH },
5910 };
5911 
5917 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5918 {
5919  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5920  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
5921  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5922  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
5923  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5924  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
5925  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5926  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
5927  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5928  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
5929  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5930  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
5931  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5932  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
5933  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5934  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
5935  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5936  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
5937  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5938  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
5939  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5940  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
5941  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5942  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
5943  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5944  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
5945  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5946  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
5947  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5948  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
5949  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5950  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
5951  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5952  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
5953  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5954  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
5955  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5956  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
5957  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5958  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
5959  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5960  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
5961  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5962  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
5963  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5964  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
5965  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5966  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
5967  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5968  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
5969  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5970  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
5971  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5972  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
5973  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5974  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
5975  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5976  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
5977  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5978  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
5979  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5980  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
5981  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5982  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
5983 };
5984 
5990 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
5991 {
5992  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5993  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
5994  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5995  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
5996  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5997  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
5998  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5999  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
6000  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6001  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
6002  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6003  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
6004  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6005  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
6006  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6007  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
6008  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6009  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
6010  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6011  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
6012  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6013  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
6014  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6015  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
6016  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6017  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
6018  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6019  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
6020  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6021  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
6022  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6023  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
6024  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6025  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
6026  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6027  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
6028  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6029  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
6030  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6031  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
6032  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6033  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
6034  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6035  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
6036  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6037  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
6038  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6039  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
6040  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6041  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
6042  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6043  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
6044  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6045  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
6046  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6047  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
6048  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6049  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
6050  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6051  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
6052  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6053  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
6054  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6055  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
6056  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6057  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
6058  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6059  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
6060  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6061  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
6062  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6063  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
6064  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6065  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
6066  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6067  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
6068  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6069  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
6070  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6071  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
6072  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6073  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
6074  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6075  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
6076  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6077  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
6078  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6079  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
6080  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6081  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
6082  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6083  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
6084  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6085  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
6086  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6087  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
6088  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6089  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
6090  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6091  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
6092  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6093  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
6094  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6095  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
6096  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6097  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
6098  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6099  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
6100  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6101  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
6102  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
6103  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
6104  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
6105  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
6106  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
6107  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
6108  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
6109  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
6110  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
6111  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
6112  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
6113  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
6114  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
6115  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
6116  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
6117  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
6118  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
6119  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
6120  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
6121  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
6122  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
6123  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
6124  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
6125  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
6126  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
6127  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
6128  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
6129  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
6130  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
6131  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
6132  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
6133  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
6134  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
6135  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
6136  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
6137  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
6138  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
6139  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
6140  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
6141  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
6142 };
6143 
6149 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6150 {
6151  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6152  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
6153  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6154  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
6155  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6156  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
6157  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6158  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
6159  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6160  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
6161  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6162  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
6163  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6164  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
6165  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6166  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
6167  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6168  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
6169  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6170  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
6171  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6172  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
6173  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6174  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
6175  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6176  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
6177  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6178  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
6179  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6180  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
6181 };
6182 
6188 /* NOTE: For VIM RAM Id, with a 32 bit vector, the 2 LSB bits are not used.
6189 ECC is done only on 30 bits. But need to add a correction of 2 to get the address
6190 calculation to be right */
6191 #define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION (2U)
6192 
6193 static const SDL_MemConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
6194 {
6195  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
6196  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
6197  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
6198  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
6199  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
6200  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
6201  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
6202  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
6203  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
6204  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
6205  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
6206  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
6207  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
6208  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
6209  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
6210  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
6211  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
6212  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
6213  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
6214  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
6215  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
6216  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
6217  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
6218  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
6219  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
6220  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
6221  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
6222  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
6223  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
6224  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
6225  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
6226  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
6227  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
6228  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
6229  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
6230  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
6231  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
6232  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
6233  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
6234  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
6235  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
6236  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
6237  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
6238  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
6239  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
6240  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
6241  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
6242  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
6243  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
6244  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
6245  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
6246  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
6247  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
6248  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
6249  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
6250  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
6251  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
6252  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
6253  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
6254  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
6255  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
6256  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
6257  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
6258  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0u,
6259  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 8u,
6260  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
6261  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x4u,
6262  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 8u,
6263  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
6264  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x41010000u,
6265  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 16u,
6266  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
6267  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x41010004u,
6268  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 16u,
6269  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
6270  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x41010008u,
6271  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 16u,
6272  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
6273  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x4101000cu,
6274  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 16u,
6275  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
6276  /* NOTE: VIM width and size needs correction: see note above */
6277  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x40f82000u,
6278  ((SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE
6279  *(SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH
6280  +SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION))
6281  /SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH), 4u,
6282  (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH+SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION), ((bool)true) },
6283 };
6284 
6290 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS] =
6291 {
6292  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6293  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_WIDTH },
6294  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6295  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_WIDTH },
6296  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6297  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_WIDTH },
6298  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6299  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_WIDTH },
6300  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6301  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_WIDTH },
6302  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6303  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_WIDTH },
6304  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
6305  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_WIDTH },
6306  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
6307  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_WIDTH },
6308  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
6309  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_WIDTH },
6310  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
6311  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_WIDTH },
6312  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
6313  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_WIDTH },
6314  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
6315  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_WIDTH },
6316  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
6317  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_WIDTH },
6318  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_CHECKER_TYPE,
6319  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_WIDTH },
6320  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_CHECKER_TYPE,
6321  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_WIDTH },
6322  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_CHECKER_TYPE,
6323  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_WIDTH },
6324  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_CHECKER_TYPE,
6325  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_WIDTH },
6326  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_CHECKER_TYPE,
6327  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_WIDTH },
6328  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_CHECKER_TYPE,
6329  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_WIDTH },
6330  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_CHECKER_TYPE,
6331  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_WIDTH },
6332  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_CHECKER_TYPE,
6333  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_WIDTH },
6334  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_CHECKER_TYPE,
6335  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_WIDTH },
6336  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_CHECKER_TYPE,
6337  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_WIDTH },
6338  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_CHECKER_TYPE,
6339  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_WIDTH },
6340  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_CHECKER_TYPE,
6341  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_WIDTH },
6342  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_CHECKER_TYPE,
6343  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_WIDTH },
6344  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_CHECKER_TYPE,
6345  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_WIDTH },
6346  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_CHECKER_TYPE,
6347  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_WIDTH },
6348  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_CHECKER_TYPE,
6349  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_WIDTH },
6350  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_CHECKER_TYPE,
6351  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_WIDTH },
6352  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_CHECKER_TYPE,
6353  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_WIDTH },
6354  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_CHECKER_TYPE,
6355  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_WIDTH },
6356  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_CHECKER_TYPE,
6357  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_WIDTH },
6358  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_CHECKER_TYPE,
6359  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_WIDTH },
6360  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_CHECKER_TYPE,
6361  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_WIDTH },
6362  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_CHECKER_TYPE,
6363  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_WIDTH },
6364  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_CHECKER_TYPE,
6365  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_WIDTH },
6366  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_CHECKER_TYPE,
6367  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_WIDTH },
6368  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_CHECKER_TYPE,
6369  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_WIDTH },
6370  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_CHECKER_TYPE,
6371  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_WIDTH },
6372  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_CHECKER_TYPE,
6373  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_WIDTH },
6374  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_CHECKER_TYPE,
6375  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_WIDTH },
6376  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_CHECKER_TYPE,
6377  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_WIDTH },
6378  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_CHECKER_TYPE,
6379  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_WIDTH },
6380  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_CHECKER_TYPE,
6381  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_WIDTH },
6382  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_CHECKER_TYPE,
6383  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_WIDTH },
6384  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_CHECKER_TYPE,
6385  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_WIDTH },
6386  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_CHECKER_TYPE,
6387  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_WIDTH },
6388  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_CHECKER_TYPE,
6389  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_WIDTH },
6390 };
6391 
6397 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
6398 {
6399  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6400  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
6401  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6402  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
6403  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6404  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
6405  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6406  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
6407  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6408  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
6409  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6410  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
6411  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
6412  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
6413  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
6414  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
6415  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
6416  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
6417  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
6418  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
6419  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
6420  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
6421  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
6422  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
6423  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
6424  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
6425  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
6426  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
6427  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
6428  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
6429  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
6430  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
6431  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
6432  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
6433  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
6434  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
6435  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
6436  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
6437  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
6438  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
6439  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
6440  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
6441  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
6442  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
6443  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
6444  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
6445  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
6446  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
6447  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
6448  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
6449  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
6450  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
6451  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
6452  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
6453  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
6454  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
6455  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
6456  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
6457  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
6458  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
6459  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
6460  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
6461 };
6462 
6468 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
6469 {
6470  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6471  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
6472  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6473  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
6474  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6475  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
6476  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6477  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
6478  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6479  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
6480  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6481  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
6482  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
6483  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
6484  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
6485  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
6486  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
6487  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
6488  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
6489  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
6490  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
6491  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
6492  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
6493  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
6494  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
6495  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
6496  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
6497  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
6498  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
6499  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
6500  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_CHECKER_TYPE,
6501  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_WIDTH },
6502 };
6503 
6509 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
6510 {
6511  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6512  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
6513  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6514  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
6515  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6516  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
6517  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6518  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
6519  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6520  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
6521  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6522  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
6523  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
6524  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
6525  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
6526  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
6527  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
6528  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
6529  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
6530  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
6531  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
6532  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
6533  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
6534  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
6535  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
6536  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
6537  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
6538  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
6539  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
6540  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
6541  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
6542  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
6543  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
6544  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
6545  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
6546  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
6547  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
6548  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
6549  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
6550  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
6551  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
6552  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
6553  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
6554  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
6555  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
6556  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
6557  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
6558  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
6559  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
6560  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
6561  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
6562  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
6563  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
6564  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
6565  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
6566  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
6567  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
6568  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
6569  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
6570  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
6571  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
6572  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
6573 };
6574 
6580 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
6581 {
6582  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6583  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
6584  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6585  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
6586  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6587  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
6588  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6589  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
6590  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6591  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
6592  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6593  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
6594  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
6595  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
6596  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
6597  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
6598  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
6599  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
6600  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
6601  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
6602  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
6603  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
6604  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
6605  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
6606  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
6607  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
6608  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
6609  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
6610  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
6611  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
6612 };
6613 
6619 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS] =
6620 {
6621  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6622  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_WIDTH },
6623  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6624  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_WIDTH },
6625  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6626  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_WIDTH },
6627  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6628  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_WIDTH },
6629  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6630  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_WIDTH },
6631  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6632  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_WIDTH },
6633  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
6634  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_WIDTH },
6635  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
6636  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_WIDTH },
6637  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
6638  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_WIDTH },
6639  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
6640  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_WIDTH },
6641  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
6642  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_WIDTH },
6643  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
6644  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_WIDTH },
6645  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
6646  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_WIDTH },
6647 };
6648 
6654 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS] =
6655 {
6656  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6657  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
6658  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6659  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
6660  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6661  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
6662 };
6663 
6669 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
6670 {
6671  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
6672  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
6673  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
6674  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
6675  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
6676  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
6677  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
6678  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
6679  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
6680  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
6681  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
6682  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
6683 };
6684 
6689 static const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES] =
6690 {
6691  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_RAM_ID, 0u,
6692  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_RAM_SIZE, 4u,
6693  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6694  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_RAM_ID, 0u,
6695  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_RAM_SIZE, 4u,
6696  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6697  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_RAM_ID, 0u,
6698  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_RAM_SIZE, 4u,
6699  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6700  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_RAM_ID, 0u,
6701  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_RAM_SIZE, 4u,
6702  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6703  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_RAM_ID, 0u,
6704  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_RAM_SIZE, 4u,
6705  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6706  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_RAM_ID, 0u,
6707  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_RAM_SIZE, 4u,
6708  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6709  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_RAM_ID, 0u,
6710  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_RAM_SIZE, 4u,
6711  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6712  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_RAM_ID, 0u,
6713  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_RAM_SIZE, 4u,
6714  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
6715 };
6716 
6721 static const SDL_MemConfig_t SDL_MCU_I3C0_I3C_S_ECC_AGGR_MemEntries[SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
6722 {
6723  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID, 0u,
6724  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
6725  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
6726  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID, 0u,
6727  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
6728  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
6729  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID, 0u,
6730  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
6731  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
6732  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID, 0u,
6733  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
6734  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
6735  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID, 0u,
6736  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_SIZE, 4u,
6737  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_ROW_WIDTH, ((bool)false) },
6738  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID, 0u,
6739  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_SIZE, 4u,
6740  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
6741  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID, 0u,
6742  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_SIZE, 4u,
6743  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
6744  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID, 0u,
6745  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_SIZE, 4u,
6746  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
6747  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID, 0u,
6748  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_SIZE, 4u,
6749  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
6750 };
6751 
6756 static const SDL_MemConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_MemEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
6757 {
6758  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PSTATE_RAM_ID, 0u,
6759  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PSTATE_RAM_SIZE, 4u,
6760  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PSTATE_ROW_WIDTH, ((bool)false) },
6761  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PCONFIG_RAM_ID, 0u,
6762  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PCONFIG_RAM_SIZE, 4u,
6763  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PCONFIG_ROW_WIDTH, ((bool)false) },
6764  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_CF_RAM_ID, 0u,
6765  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_CF_RAM_SIZE, 4u,
6766  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_CF_ROW_WIDTH, ((bool)false) },
6767  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_DF_RAM_ID, 0u,
6768  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_DF_RAM_SIZE, 4u,
6769  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_DF_ROW_WIDTH, ((bool)false) },
6770  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_PF_RAM_ID, 0u,
6771  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_PF_RAM_SIZE, 4u,
6772  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_PF_ROW_WIDTH, ((bool)false) },
6773  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_SB_RAM_ID, 0u,
6774  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_SB_RAM_SIZE, 4u,
6775  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_SB_ROW_WIDTH, ((bool)false) },
6776  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_RAM_ID, 0u,
6777  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
6778  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
6779  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_SB_RAM_ID, 0u,
6780  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_SB_RAM_SIZE, 4u,
6781  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_SB_ROW_WIDTH, ((bool)false) },
6782  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_ARRAYCNT_ARRAYCNT_TPRAM_640X13_SWW_AR_RAM_ID, 0u,
6783  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_ARRAYCNT_ARRAYCNT_TPRAM_640X13_SWW_AR_RAM_SIZE, 4u,
6784  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_ARRAYCNT_ARRAYCNT_TPRAM_640X13_SWW_AR_ROW_WIDTH, ((bool)false) },
6785  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PSTATE_RAM_ID, 0u,
6786  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PSTATE_RAM_SIZE, 4u,
6787  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PSTATE_ROW_WIDTH, ((bool)false) },
6788  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PCONFIG_RAM_ID, 0u,
6789  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PCONFIG_RAM_SIZE, 4u,
6790  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PCONFIG_ROW_WIDTH, ((bool)false) },
6791  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PQINFO_RAM_ID, 0u,
6792  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PQINFO_RAM_SIZE, 4u,
6793  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PQINFO_ROW_WIDTH, ((bool)false) },
6794  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_CF_RAM_ID, 0u,
6795  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_CF_RAM_SIZE, 4u,
6796  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_CF_ROW_WIDTH, ((bool)false) },
6797  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_DF_RAM_ID, 0u,
6798  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_DF_RAM_SIZE, 4u,
6799  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_DF_ROW_WIDTH, ((bool)false) },
6800  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_PF_RAM_ID, 0u,
6801  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_PF_RAM_SIZE, 4u,
6802  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_PF_ROW_WIDTH, ((bool)false) },
6803  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TCF_RAM_ID, 0u,
6804  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TCF_RAM_SIZE, 4u,
6805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TCF_ROW_WIDTH, ((bool)false) },
6806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TDF_RAM_ID, 0u,
6807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TDF_RAM_SIZE, 4u,
6808  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TDF_ROW_WIDTH, ((bool)false) },
6809  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB0_RAM_ID, 0u,
6810  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB0_RAM_SIZE, 4u,
6811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB0_ROW_WIDTH, ((bool)false) },
6812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB1_RAM_ID, 0u,
6813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB1_RAM_SIZE, 4u,
6814  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB1_ROW_WIDTH, ((bool)false) },
6815  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB2_RAM_ID, 0u,
6816  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB2_RAM_SIZE, 4u,
6817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB2_ROW_WIDTH, ((bool)false) },
6818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_RAM_ID, 0u,
6819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
6820  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
6821  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB0_RAM_ID, 0u,
6822  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB0_RAM_SIZE, 4u,
6823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB0_ROW_WIDTH, ((bool)false) },
6824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB1_RAM_ID, 0u,
6825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB1_RAM_SIZE, 4u,
6826  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB1_ROW_WIDTH, ((bool)false) },
6827  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB2_RAM_ID, 0u,
6828  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB2_RAM_SIZE, 4u,
6829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB2_ROW_WIDTH, ((bool)false) },
6830  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_RAM_ID, 0u,
6831  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
6832  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
6833  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB0_RAM_ID, 0u,
6834  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB0_RAM_SIZE, 4u,
6835  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB0_ROW_WIDTH, ((bool)false) },
6836  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB1_RAM_ID, 0u,
6837  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB1_RAM_SIZE, 4u,
6838  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB1_ROW_WIDTH, ((bool)false) },
6839  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_RAM_ID, 0u,
6840  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
6841  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
6842  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TCFG_STATE_RAM_ID, 0u,
6843  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TCFG_STATE_RAM_SIZE, 4u,
6844  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TCFG_STATE_ROW_WIDTH, ((bool)false) },
6845  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F0_RAM_ID, 0u,
6846  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F0_RAM_SIZE, 4u,
6847  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F0_ROW_WIDTH, ((bool)false) },
6848  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F1_RAM_ID, 0u,
6849  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F1_RAM_SIZE, 4u,
6850  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F1_ROW_WIDTH, ((bool)false) },
6851  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_C0_RAM_ID, 0u,
6852  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_C0_RAM_SIZE, 4u,
6853  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_C0_ROW_WIDTH, ((bool)false) },
6854  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RFLOWFW_RFFW_RAM_ID, 0u,
6855  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RFLOWFW_RFFW_RAM_SIZE, 4u,
6856  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RFLOWFW_RFFW_ROW_WIDTH, ((bool)false) },
6857  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F0_RAM_ID, 0u,
6858  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F0_RAM_SIZE, 4u,
6859  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
6860  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F1_RAM_ID, 0u,
6861  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F1_RAM_SIZE, 4u,
6862  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
6863  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C0_RAM_ID, 0u,
6864  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C0_RAM_SIZE, 4u,
6865  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C0_ROW_WIDTH, ((bool)false) },
6866  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_WC0_RAM_ID, 0u,
6867  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_WC0_RAM_SIZE, 4u,
6868  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_WC0_ROW_WIDTH, ((bool)false) },
6869  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C1_RAM_ID, 0u,
6870  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C1_RAM_SIZE, 4u,
6871  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C1_ROW_WIDTH, ((bool)false) },
6872  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW0_RAM_ID, 0u,
6873  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW0_RAM_SIZE, 4u,
6874  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW0_ROW_WIDTH, ((bool)false) },
6875  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW1_RAM_ID, 0u,
6876  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW1_RAM_SIZE, 4u,
6877  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW1_ROW_WIDTH, ((bool)false) },
6878  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RSTATE_RAM_ID, 0u,
6879  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RSTATE_RAM_SIZE, 4u,
6880  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RSTATE_ROW_WIDTH, ((bool)false) },
6881  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PROXY_PCONFIG_RAM_ID, 0u,
6882  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PROXY_PCONFIG_RAM_SIZE, 4u,
6883  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PROXY_PCONFIG_ROW_WIDTH, ((bool)false) },
6884  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EHANDLER_ECONFIG_RAM_ID, 0u,
6885  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EHANDLER_ECONFIG_RAM_SIZE, 4u,
6886  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EHANDLER_ECONFIG_ROW_WIDTH, ((bool)false) },
6887  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST0_RAM_ID, 0u,
6888  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST0_RAM_SIZE, 4u,
6889  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST0_ROW_WIDTH, ((bool)false) },
6890  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST1_RAM_ID, 0u,
6891  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST1_RAM_SIZE, 4u,
6892  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST1_ROW_WIDTH, ((bool)false) },
6893  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR0_RAM_ID, 0u,
6894  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR0_RAM_SIZE, 4u,
6895  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR0_ROW_WIDTH, ((bool)false) },
6896  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR1_RAM_ID, 0u,
6897  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR1_RAM_SIZE, 4u,
6898  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR1_ROW_WIDTH, ((bool)false) },
6899  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_RAM_ID, 0u,
6900  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
6901  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
6902  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_RAM_ID, 0u,
6903  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
6904  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
6905  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC0_SB_RAM_ID, 0u,
6906  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC0_SB_RAM_SIZE, 4u,
6907  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC0_SB_ROW_WIDTH, ((bool)false) },
6908  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC1_SB_RAM_ID, 0u,
6909  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC1_SB_RAM_SIZE, 4u,
6910  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC1_SB_ROW_WIDTH, ((bool)false) },
6911  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC2_SB_RAM_ID, 0u,
6912  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC2_SB_RAM_SIZE, 4u,
6913  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC2_SB_ROW_WIDTH, ((bool)false) },
6914  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC0_SB_RAM_ID, 0u,
6915  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC0_SB_RAM_SIZE, 4u,
6916  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC0_SB_ROW_WIDTH, ((bool)false) },
6917  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC3_SB_RAM_ID, 0u,
6918  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC3_SB_RAM_SIZE, 4u,
6919  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC3_SB_ROW_WIDTH, ((bool)false) },
6920  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_RAM_ID, 0u,
6921  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_RAM_SIZE, 4u,
6922  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_ROW_WIDTH, ((bool)false) },
6923  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_TRETID_RAM_ID, 0u,
6924  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_TRETID_RAM_SIZE, 4u,
6925  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_TRETID_ROW_WIDTH, ((bool)false) },
6926  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_RAM_ID, 0u,
6927  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_RAM_SIZE, 4u,
6928  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_ROW_WIDTH, ((bool)false) },
6929  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_RAM_ID, 0u,
6930  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_RAM_SIZE, 4u,
6931  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_ROW_WIDTH, ((bool)false) },
6932  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_STRAM_RAM_ID, 0u,
6933  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_STRAM_RAM_SIZE, 4u,
6934  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_STRAM_ROW_WIDTH, ((bool)false) },
6935  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_4608X15_SWW_SR_RAM_ID, 0u,
6936  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_4608X15_SWW_SR_RAM_SIZE, 4u,
6937  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_4608X15_SWW_SR_ROW_WIDTH, ((bool)false) },
6938  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_RAM_ID, 0u,
6939  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_RAM_SIZE, 4u,
6940  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_ROW_WIDTH, ((bool)false) },
6941  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_512X32_SWW_SR_RAM_ID, 0u,
6942  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_512X32_SWW_SR_RAM_SIZE, 4u,
6943  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_512X32_SWW_SR_ROW_WIDTH, ((bool)false) },
6944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_512X48_SWW_SR_RAM_ID, 0u,
6945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_512X48_SWW_SR_RAM_SIZE, 4u,
6946  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_512X48_SWW_SR_ROW_WIDTH, ((bool)false) },
6947  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_ECC0_RAM_ID, 0u,
6948  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_ECC0_RAM_SIZE, 4u,
6949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
6950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_RAM_ID, 0u,
6951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_RAM_SIZE, 4u,
6952  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_ROW_WIDTH, ((bool)false) },
6953  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
6954  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
6955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
6956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
6957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
6958  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
6959  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
6960  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
6961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
6962 };
6963 
6969 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6970 {
6971  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6972  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
6973  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6974  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
6975  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6976  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
6977  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6978  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
6979  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6980  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
6981  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6982  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
6983 };
6984 
6990 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
6991 {
6992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_0_WIDTH },
6994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_1_WIDTH },
6996  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6997  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_2_WIDTH },
6998  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6999  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_3_WIDTH },
7000  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7001  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_4_WIDTH },
7002  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7003  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_5_WIDTH },
7004  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7005  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_6_WIDTH },
7006  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7007  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_7_WIDTH },
7008  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7009  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_8_WIDTH },
7010  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7011  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_9_WIDTH },
7012  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7013  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_10_WIDTH },
7014  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7015  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_11_WIDTH },
7016  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7017  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_12_WIDTH },
7018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_13_WIDTH },
7020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_14_WIDTH },
7022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_15_WIDTH },
7024  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7025  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_16_WIDTH },
7026  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7027  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_17_WIDTH },
7028  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7029  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_18_WIDTH },
7030  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7031  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_19_WIDTH },
7032  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7033  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_20_WIDTH },
7034  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7035  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_21_WIDTH },
7036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_22_WIDTH },
7038  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_23_WIDTH },
7040  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7041  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_24_WIDTH },
7042  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7043  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_25_WIDTH },
7044  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7045  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_26_WIDTH },
7046  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7047  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_27_WIDTH },
7048  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7049  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_28_WIDTH },
7050  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7051  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_29_WIDTH },
7052  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7053  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_30_WIDTH },
7054  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7055  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_31_WIDTH },
7056  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7057  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_32_WIDTH },
7058  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7059  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_33_WIDTH },
7060  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7061  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_34_WIDTH },
7062  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7063  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_35_WIDTH },
7064  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7065  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_36_WIDTH },
7066  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7067  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_37_WIDTH },
7068  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7069  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_38_WIDTH },
7070  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7071  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_39_WIDTH },
7072  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7073  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_40_WIDTH },
7074  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7075  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_41_WIDTH },
7076  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7077  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_42_WIDTH },
7078  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7079  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_43_WIDTH },
7080  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7081  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_44_WIDTH },
7082  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7083  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_45_WIDTH },
7084  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7085  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_46_WIDTH },
7086  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7087  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_47_WIDTH },
7088  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7089  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_48_WIDTH },
7090  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7091  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_49_WIDTH },
7092  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7093  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_50_WIDTH },
7094  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7095  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_51_WIDTH },
7096  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7097  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_52_WIDTH },
7098  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7099  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_53_WIDTH },
7100  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7101  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_54_WIDTH },
7102  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7103  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_55_WIDTH },
7104  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7105  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_56_WIDTH },
7106  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7107  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_57_WIDTH },
7108  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7109  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_58_WIDTH },
7110  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7111  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_59_WIDTH },
7112  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7113  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_60_WIDTH },
7114  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7115  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_61_WIDTH },
7116  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7117  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_62_WIDTH },
7118  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7119  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_63_WIDTH },
7120  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7121  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_64_WIDTH },
7122  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7123  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_65_WIDTH },
7124  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7125  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_66_WIDTH },
7126  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7127  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_67_WIDTH },
7128  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7129  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_68_WIDTH },
7130  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7131  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_69_WIDTH },
7132  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7133  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_70_WIDTH },
7134  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7135  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_71_WIDTH },
7136  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7137  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_72_WIDTH },
7138  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7139  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_73_WIDTH },
7140  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7141  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_74_WIDTH },
7142  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7143  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_75_WIDTH },
7144  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7145  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_76_WIDTH },
7146  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7147  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_77_WIDTH },
7148  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7149  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_78_WIDTH },
7150  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7151  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_79_WIDTH },
7152  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7153  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_80_WIDTH },
7154  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7155  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_81_WIDTH },
7156  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7157  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_82_WIDTH },
7158  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7159  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_83_WIDTH },
7160  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7161  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_84_WIDTH },
7162  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
7163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_85_WIDTH },
7164  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
7165  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_86_WIDTH },
7166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
7167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_87_WIDTH },
7168  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
7169  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_88_WIDTH },
7170  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
7171  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_89_WIDTH },
7172  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
7173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_90_WIDTH },
7174  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
7175  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_91_WIDTH },
7176  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
7177  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_92_WIDTH },
7178  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
7179  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_93_WIDTH },
7180  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
7181  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_94_WIDTH },
7182  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
7183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_95_WIDTH },
7184  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
7185  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_96_WIDTH },
7186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
7187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_97_WIDTH },
7188  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
7189  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_98_WIDTH },
7190  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
7191  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_99_WIDTH },
7192  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
7193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_100_WIDTH },
7194  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
7195  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_101_WIDTH },
7196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
7197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_102_WIDTH },
7198  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
7199  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_103_WIDTH },
7200  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
7201  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_104_WIDTH },
7202  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
7203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_105_WIDTH },
7204  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
7205  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_106_WIDTH },
7206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
7207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_107_WIDTH },
7208  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
7209  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_108_WIDTH },
7210  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
7211  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_109_WIDTH },
7212  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
7213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_110_WIDTH },
7214  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
7215  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_111_WIDTH },
7216  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
7217  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_112_WIDTH },
7218  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
7219  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_113_WIDTH },
7220  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
7221  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_114_WIDTH },
7222  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
7223  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_115_WIDTH },
7224  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
7225  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_116_WIDTH },
7226  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
7227  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_117_WIDTH },
7228  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
7229  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_118_WIDTH },
7230  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
7231  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_119_WIDTH },
7232  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
7233  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_120_WIDTH },
7234  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
7235  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_121_WIDTH },
7236  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
7237  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_122_WIDTH },
7238  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
7239  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_123_WIDTH },
7240  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
7241  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_124_WIDTH },
7242  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
7243  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_125_WIDTH },
7244  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
7245  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_126_WIDTH },
7246  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
7247  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_127_WIDTH },
7248  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
7249  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_128_WIDTH },
7250  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
7251  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_129_WIDTH },
7252  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
7253  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_130_WIDTH },
7254  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
7255  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_131_WIDTH },
7256  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
7257  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_132_WIDTH },
7258  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
7259  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_133_WIDTH },
7260  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
7261  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_134_WIDTH },
7262  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
7263  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_135_WIDTH },
7264  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
7265  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_136_WIDTH },
7266  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
7267  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_137_WIDTH },
7268  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
7269  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_138_WIDTH },
7270  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
7271  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_139_WIDTH },
7272  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
7273  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_140_WIDTH },
7274  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
7275  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_141_WIDTH },
7276  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
7277  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_142_WIDTH },
7278  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
7279  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_143_WIDTH },
7280  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
7281  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_144_WIDTH },
7282  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
7283  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_145_WIDTH },
7284  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
7285  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_146_WIDTH },
7286  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
7287  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_147_WIDTH },
7288  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
7289  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_148_WIDTH },
7290  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
7291  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_149_WIDTH },
7292  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
7293  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_150_WIDTH },
7294  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
7295  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_151_WIDTH },
7296  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
7297  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_152_WIDTH },
7298  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
7299  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_153_WIDTH },
7300  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
7301  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_154_WIDTH },
7302  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
7303  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_155_WIDTH },
7304  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
7305  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_156_WIDTH },
7306  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
7307  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_157_WIDTH },
7308  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
7309  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_158_WIDTH },
7310  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
7311  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_159_WIDTH },
7312  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
7313  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_160_WIDTH },
7314  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
7315  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_161_WIDTH },
7316  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
7317  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_162_WIDTH },
7318  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
7319  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_163_WIDTH },
7320  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
7321  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_164_WIDTH },
7322  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
7323  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_165_WIDTH },
7324  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
7325  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_166_WIDTH },
7326  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
7327  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_167_WIDTH },
7328  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
7329  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_168_WIDTH },
7330  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
7331  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_169_WIDTH },
7332  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
7333  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_170_WIDTH },
7334  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
7335  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_171_WIDTH },
7336  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
7337  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_172_WIDTH },
7338  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
7339  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_173_WIDTH },
7340  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
7341  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_174_WIDTH },
7342  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
7343  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_175_WIDTH },
7344  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
7345  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_176_WIDTH },
7346  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
7347  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_177_WIDTH },
7348  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
7349  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_178_WIDTH },
7350  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
7351  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_179_WIDTH },
7352  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
7353  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_180_WIDTH },
7354  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
7355  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_181_WIDTH },
7356  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
7357  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_182_WIDTH },
7358  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
7359  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_183_WIDTH },
7360  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
7361  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_184_WIDTH },
7362  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
7363  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_185_WIDTH },
7364  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
7365  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_186_WIDTH },
7366  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
7367  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_187_WIDTH },
7368  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
7369  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_188_WIDTH },
7370  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
7371  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_189_WIDTH },
7372  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
7373  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_190_WIDTH },
7374  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
7375  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_191_WIDTH },
7376  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
7377  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_192_WIDTH },
7378  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
7379  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_193_WIDTH },
7380  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
7381  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_194_WIDTH },
7382  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
7383  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_195_WIDTH },
7384  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
7385  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_196_WIDTH },
7386  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
7387  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_197_WIDTH },
7388  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
7389  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_198_WIDTH },
7390  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
7391  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_199_WIDTH },
7392  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
7393  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_200_WIDTH },
7394  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
7395  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_201_WIDTH },
7396  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
7397  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_202_WIDTH },
7398  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
7399  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_203_WIDTH },
7400  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
7401  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_204_WIDTH },
7402  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
7403  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_205_WIDTH },
7404  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
7405  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_206_WIDTH },
7406  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
7407  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_207_WIDTH },
7408  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
7409  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_208_WIDTH },
7410  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
7411  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_209_WIDTH },
7412  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
7413  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_210_WIDTH },
7414  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
7415  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_211_WIDTH },
7416  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
7417  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_212_WIDTH },
7418  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
7419  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_213_WIDTH },
7420  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
7421  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_214_WIDTH },
7422  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
7423  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_215_WIDTH },
7424  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
7425  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_216_WIDTH },
7426  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
7427  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_217_WIDTH },
7428  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
7429  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_218_WIDTH },
7430  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
7431  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_219_WIDTH },
7432  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
7433  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_220_WIDTH },
7434  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
7435  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_221_WIDTH },
7436  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
7437  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_222_WIDTH },
7438  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
7439  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_223_WIDTH },
7440  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
7441  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_224_WIDTH },
7442  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
7443  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_225_WIDTH },
7444  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
7445  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_226_WIDTH },
7446  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
7447  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_227_WIDTH },
7448  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
7449  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_228_WIDTH },
7450  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
7451  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_229_WIDTH },
7452  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
7453  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_230_WIDTH },
7454  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
7455  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_231_WIDTH },
7456  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
7457  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_232_WIDTH },
7458  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
7459  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_233_WIDTH },
7460  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
7461  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_234_WIDTH },
7462  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
7463  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_235_WIDTH },
7464  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
7465  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_236_WIDTH },
7466  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
7467  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_237_WIDTH },
7468  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
7469  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_238_WIDTH },
7470  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
7471  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_239_WIDTH },
7472  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
7473  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_240_WIDTH },
7474  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
7475  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_241_WIDTH },
7476  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
7477  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_242_WIDTH },
7478  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
7479  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_243_WIDTH },
7480  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
7481  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_244_WIDTH },
7482  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
7483  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_245_WIDTH },
7484  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
7485  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_246_WIDTH },
7486  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
7487  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_247_WIDTH },
7488  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
7489  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_248_WIDTH },
7490  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
7491  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_249_WIDTH },
7492  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
7493  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_250_WIDTH },
7494  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
7495  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_251_WIDTH },
7496  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
7497  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_252_WIDTH },
7498  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
7499  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_253_WIDTH },
7500  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
7501  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_254_WIDTH },
7502  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
7503  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_255_WIDTH },
7504 };
7505 
7511 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS] =
7512 {
7513  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
7514  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_0_WIDTH },
7515  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
7516  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_1_WIDTH },
7517  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
7518  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_2_WIDTH },
7519  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
7520  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_3_WIDTH },
7521  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
7522  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_4_WIDTH },
7523  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
7524  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_5_WIDTH },
7525  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
7526  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_6_WIDTH },
7527  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
7528  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_7_WIDTH },
7529  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
7530  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_8_WIDTH },
7531  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
7532  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_9_WIDTH },
7533  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
7534  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_10_WIDTH },
7535  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
7536  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_11_WIDTH },
7537  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
7538  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_12_WIDTH },
7539  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
7540  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_13_WIDTH },
7541  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
7542  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_14_WIDTH },
7543  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
7544  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_15_WIDTH },
7545  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
7546  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_16_WIDTH },
7547  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
7548  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_17_WIDTH },
7549  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
7550  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_18_WIDTH },
7551  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
7552  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_19_WIDTH },
7553  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
7554  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_20_WIDTH },
7555  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
7556  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_21_WIDTH },
7557  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
7558  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_22_WIDTH },
7559  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
7560  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_23_WIDTH },
7561  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
7562  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_24_WIDTH },
7563  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
7564  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_25_WIDTH },
7565  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
7566  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_26_WIDTH },
7567  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
7568  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_27_WIDTH },
7569  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
7570  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_28_WIDTH },
7571  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
7572  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_29_WIDTH },
7573  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
7574  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_30_WIDTH },
7575  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
7576  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_31_WIDTH },
7577  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
7578  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_32_WIDTH },
7579  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
7580  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_33_WIDTH },
7581  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
7582  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_34_WIDTH },
7583  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
7584  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_35_WIDTH },
7585  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
7586  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_36_WIDTH },
7587  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
7588  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_37_WIDTH },
7589  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
7590  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_38_WIDTH },
7591  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
7592  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_39_WIDTH },
7593  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
7594  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_40_WIDTH },
7595  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
7596  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_41_WIDTH },
7597  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
7598  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_42_WIDTH },
7599  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
7600  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_43_WIDTH },
7601  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
7602  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_44_WIDTH },
7603  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
7604  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_45_WIDTH },
7605  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
7606  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_46_WIDTH },
7607  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
7608  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_47_WIDTH },
7609  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
7610  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_48_WIDTH },
7611  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
7612  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_49_WIDTH },
7613  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
7614  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_50_WIDTH },
7615  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
7616  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_51_WIDTH },
7617  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
7618  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_52_WIDTH },
7619  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
7620  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_53_WIDTH },
7621  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
7622  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_54_WIDTH },
7623  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
7624  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_55_WIDTH },
7625  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
7626  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_56_WIDTH },
7627  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
7628  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_57_WIDTH },
7629  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
7630  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_58_WIDTH },
7631  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
7632  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_59_WIDTH },
7633  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
7634  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_60_WIDTH },
7635  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
7636  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_61_WIDTH },
7637  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
7638  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_62_WIDTH },
7639  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
7640  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_63_WIDTH },
7641  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
7642  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_64_WIDTH },
7643  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
7644  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_65_WIDTH },
7645  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
7646  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_66_WIDTH },
7647  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
7648  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_67_WIDTH },
7649  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
7650  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_68_WIDTH },
7651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
7652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_69_WIDTH },
7653  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
7654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_70_WIDTH },
7655  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
7656  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_71_WIDTH },
7657  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
7658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_72_WIDTH },
7659  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
7660  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_73_WIDTH },
7661  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
7662  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_74_WIDTH },
7663  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
7664  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_75_WIDTH },
7665  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
7666  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_76_WIDTH },
7667  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
7668  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_77_WIDTH },
7669  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
7670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_78_WIDTH },
7671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
7672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_79_WIDTH },
7673  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
7674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_80_WIDTH },
7675  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
7676  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_81_WIDTH },
7677  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
7678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_82_WIDTH },
7679  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
7680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_83_WIDTH },
7681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
7682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_84_WIDTH },
7683  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
7684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_85_WIDTH },
7685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
7686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_86_WIDTH },
7687  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
7688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_87_WIDTH },
7689  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
7690  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_88_WIDTH },
7691  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
7692  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_89_WIDTH },
7693  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
7694  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_90_WIDTH },
7695  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
7696  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_91_WIDTH },
7697  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
7698  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_92_WIDTH },
7699  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
7700  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_93_WIDTH },
7701  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
7702  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_94_WIDTH },
7703  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
7704  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_95_WIDTH },
7705  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
7706  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_96_WIDTH },
7707  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
7708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_97_WIDTH },
7709  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
7710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_98_WIDTH },
7711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
7712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_99_WIDTH },
7713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
7714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_100_WIDTH },
7715  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
7716  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_101_WIDTH },
7717  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
7718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_102_WIDTH },
7719  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
7720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_103_WIDTH },
7721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
7722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_104_WIDTH },
7723  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
7724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_105_WIDTH },
7725  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
7726  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_106_WIDTH },
7727  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
7728  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_107_WIDTH },
7729  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
7730  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_108_WIDTH },
7731  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
7732  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_109_WIDTH },
7733  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
7734  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_110_WIDTH },
7735  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
7736  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_111_WIDTH },
7737  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
7738  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_112_WIDTH },
7739  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
7740  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_113_WIDTH },
7741  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
7742  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_114_WIDTH },
7743  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
7744  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_115_WIDTH },
7745  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
7746  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_116_WIDTH },
7747  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
7748  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_117_WIDTH },
7749  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
7750  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_118_WIDTH },
7751  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
7752  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_119_WIDTH },
7753  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
7754  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_120_WIDTH },
7755  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
7756  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_121_WIDTH },
7757  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
7758  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_122_WIDTH },
7759  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
7760  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_123_WIDTH },
7761  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
7762  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_124_WIDTH },
7763  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
7764  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_125_WIDTH },
7765  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
7766  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_126_WIDTH },
7767  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
7768  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_127_WIDTH },
7769  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
7770  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_128_WIDTH },
7771  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
7772  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_129_WIDTH },
7773  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
7774  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_130_WIDTH },
7775  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
7776  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_131_WIDTH },
7777  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
7778  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_132_WIDTH },
7779  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
7780  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_133_WIDTH },
7781  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
7782  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_134_WIDTH },
7783  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
7784  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_135_WIDTH },
7785  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
7786  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_136_WIDTH },
7787  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
7788  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_137_WIDTH },
7789  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
7790  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_138_WIDTH },
7791  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
7792  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_139_WIDTH },
7793  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
7794  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_140_WIDTH },
7795  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
7796  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_141_WIDTH },
7797  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
7798  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_142_WIDTH },
7799  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
7800  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_143_WIDTH },
7801  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
7802  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_144_WIDTH },
7803  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
7804  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_145_WIDTH },
7805  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
7806  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_146_WIDTH },
7807  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
7808  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_147_WIDTH },
7809  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
7810  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_148_WIDTH },
7811  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
7812  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_149_WIDTH },
7813  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
7814  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_150_WIDTH },
7815  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
7816  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_151_WIDTH },
7817  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
7818  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_152_WIDTH },
7819  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
7820  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_153_WIDTH },
7821  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
7822  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_154_WIDTH },
7823  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
7824  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_155_WIDTH },
7825  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
7826  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_156_WIDTH },
7827  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
7828  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_157_WIDTH },
7829  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
7830  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_158_WIDTH },
7831  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
7832  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_159_WIDTH },
7833  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
7834  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_160_WIDTH },
7835  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
7836  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_161_WIDTH },
7837  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
7838  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_162_WIDTH },
7839  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
7840  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_163_WIDTH },
7841  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_164_CHECKER_TYPE,
7842  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_164_WIDTH },
7843  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_165_CHECKER_TYPE,
7844  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_165_WIDTH },
7845  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_166_CHECKER_TYPE,
7846  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_166_WIDTH },
7847  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_167_CHECKER_TYPE,
7848  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_167_WIDTH },
7849  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_168_CHECKER_TYPE,
7850  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_168_WIDTH },
7851  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_169_CHECKER_TYPE,
7852  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_169_WIDTH },
7853  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_170_CHECKER_TYPE,
7854  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_170_WIDTH },
7855  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_171_CHECKER_TYPE,
7856  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_171_WIDTH },
7857  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_172_CHECKER_TYPE,
7858  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_172_WIDTH },
7859  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_173_CHECKER_TYPE,
7860  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_173_WIDTH },
7861  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_174_CHECKER_TYPE,
7862  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_174_WIDTH },
7863  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_175_CHECKER_TYPE,
7864  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_175_WIDTH },
7865  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_176_CHECKER_TYPE,
7866  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_176_WIDTH },
7867  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_177_CHECKER_TYPE,
7868  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_177_WIDTH },
7869  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_178_CHECKER_TYPE,
7870  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_178_WIDTH },
7871  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_179_CHECKER_TYPE,
7872  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_179_WIDTH },
7873  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_180_CHECKER_TYPE,
7874  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_180_WIDTH },
7875  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_181_CHECKER_TYPE,
7876  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_181_WIDTH },
7877  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_182_CHECKER_TYPE,
7878  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_182_WIDTH },
7879  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_183_CHECKER_TYPE,
7880  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_183_WIDTH },
7881  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_184_CHECKER_TYPE,
7882  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_184_WIDTH },
7883  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_185_CHECKER_TYPE,
7884  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_185_WIDTH },
7885  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_186_CHECKER_TYPE,
7886  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_186_WIDTH },
7887  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_187_CHECKER_TYPE,
7888  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_187_WIDTH },
7889  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_188_CHECKER_TYPE,
7890  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_188_WIDTH },
7891  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_189_CHECKER_TYPE,
7892  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_189_WIDTH },
7893  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_190_CHECKER_TYPE,
7894  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_190_WIDTH },
7895  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_191_CHECKER_TYPE,
7896  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_191_WIDTH },
7897  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_192_CHECKER_TYPE,
7898  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_192_WIDTH },
7899  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_193_CHECKER_TYPE,
7900  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_193_WIDTH },
7901  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_194_CHECKER_TYPE,
7902  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_194_WIDTH },
7903  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_195_CHECKER_TYPE,
7904  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_195_WIDTH },
7905  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_196_CHECKER_TYPE,
7906  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_196_WIDTH },
7907  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_197_CHECKER_TYPE,
7908  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_197_WIDTH },
7909  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_198_CHECKER_TYPE,
7910  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_198_WIDTH },
7911  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_199_CHECKER_TYPE,
7912  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_199_WIDTH },
7913  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_200_CHECKER_TYPE,
7914  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_200_WIDTH },
7915  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_201_CHECKER_TYPE,
7916  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_201_WIDTH },
7917  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_202_CHECKER_TYPE,
7918  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_202_WIDTH },
7919  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_203_CHECKER_TYPE,
7920  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_203_WIDTH },
7921  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_204_CHECKER_TYPE,
7922  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_204_WIDTH },
7923  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_205_CHECKER_TYPE,
7924  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_205_WIDTH },
7925  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_206_CHECKER_TYPE,
7926  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_206_WIDTH },
7927  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_207_CHECKER_TYPE,
7928  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_207_WIDTH },
7929  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_208_CHECKER_TYPE,
7930  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_208_WIDTH },
7931  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_209_CHECKER_TYPE,
7932  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_209_WIDTH },
7933  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_210_CHECKER_TYPE,
7934  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_210_WIDTH },
7935  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_211_CHECKER_TYPE,
7936  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_211_WIDTH },
7937  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_212_CHECKER_TYPE,
7938  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_212_WIDTH },
7939  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_213_CHECKER_TYPE,
7940  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_213_WIDTH },
7941  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_214_CHECKER_TYPE,
7942  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_214_WIDTH },
7943  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_215_CHECKER_TYPE,
7944  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_215_WIDTH },
7945  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_216_CHECKER_TYPE,
7946  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_216_WIDTH },
7947  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_217_CHECKER_TYPE,
7948  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_217_WIDTH },
7949  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_218_CHECKER_TYPE,
7950  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_218_WIDTH },
7951  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_219_CHECKER_TYPE,
7952  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_219_WIDTH },
7953  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_220_CHECKER_TYPE,
7954  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_220_WIDTH },
7955  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_221_CHECKER_TYPE,
7956  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_221_WIDTH },
7957  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_222_CHECKER_TYPE,
7958  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_222_WIDTH },
7959  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_223_CHECKER_TYPE,
7960  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_223_WIDTH },
7961  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_224_CHECKER_TYPE,
7962  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_224_WIDTH },
7963  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_225_CHECKER_TYPE,
7964  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_225_WIDTH },
7965  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_226_CHECKER_TYPE,
7966  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_226_WIDTH },
7967  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_227_CHECKER_TYPE,
7968  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_227_WIDTH },
7969  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_228_CHECKER_TYPE,
7970  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_228_WIDTH },
7971  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_229_CHECKER_TYPE,
7972  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_229_WIDTH },
7973  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_230_CHECKER_TYPE,
7974  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_230_WIDTH },
7975  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_231_CHECKER_TYPE,
7976  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_231_WIDTH },
7977  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_232_CHECKER_TYPE,
7978  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_232_WIDTH },
7979  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_233_CHECKER_TYPE,
7980  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_233_WIDTH },
7981  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_234_CHECKER_TYPE,
7982  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_234_WIDTH },
7983  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_235_CHECKER_TYPE,
7984  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_235_WIDTH },
7985  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_236_CHECKER_TYPE,
7986  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_236_WIDTH },
7987  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_237_CHECKER_TYPE,
7988  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_237_WIDTH },
7989  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_238_CHECKER_TYPE,
7990  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_238_WIDTH },
7991  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_239_CHECKER_TYPE,
7992  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_239_WIDTH },
7993  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_240_CHECKER_TYPE,
7994  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_240_WIDTH },
7995  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_241_CHECKER_TYPE,
7996  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_241_WIDTH },
7997  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_242_CHECKER_TYPE,
7998  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_242_WIDTH },
7999  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_243_CHECKER_TYPE,
8000  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_243_WIDTH },
8001  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_244_CHECKER_TYPE,
8002  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_244_WIDTH },
8003  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_245_CHECKER_TYPE,
8004  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_245_WIDTH },
8005  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_246_CHECKER_TYPE,
8006  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_246_WIDTH },
8007  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_247_CHECKER_TYPE,
8008  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_247_WIDTH },
8009  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_248_CHECKER_TYPE,
8010  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_248_WIDTH },
8011  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_249_CHECKER_TYPE,
8012  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_249_WIDTH },
8013  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_250_CHECKER_TYPE,
8014  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_250_WIDTH },
8015  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_251_CHECKER_TYPE,
8016  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_251_WIDTH },
8017  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_252_CHECKER_TYPE,
8018  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_252_WIDTH },
8019  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_253_CHECKER_TYPE,
8020  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_253_WIDTH },
8021  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_254_CHECKER_TYPE,
8022  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_254_WIDTH },
8023  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_255_CHECKER_TYPE,
8024  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_255_WIDTH },
8025 };
8026 
8032 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS] =
8033 {
8034  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_0_CHECKER_TYPE,
8035  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_0_WIDTH },
8036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_1_CHECKER_TYPE,
8037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_1_WIDTH },
8038  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_2_CHECKER_TYPE,
8039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_2_WIDTH },
8040  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_3_CHECKER_TYPE,
8041  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_3_WIDTH },
8042  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_4_CHECKER_TYPE,
8043  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_4_WIDTH },
8044  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_5_CHECKER_TYPE,
8045  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_5_WIDTH },
8046  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_6_CHECKER_TYPE,
8047  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_6_WIDTH },
8048  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_7_CHECKER_TYPE,
8049  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_7_WIDTH },
8050  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_8_CHECKER_TYPE,
8051  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_8_WIDTH },
8052  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_9_CHECKER_TYPE,
8053  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_9_WIDTH },
8054  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_10_CHECKER_TYPE,
8055  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_10_WIDTH },
8056  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_11_CHECKER_TYPE,
8057  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_11_WIDTH },
8058  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_12_CHECKER_TYPE,
8059  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_12_WIDTH },
8060  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_13_CHECKER_TYPE,
8061  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_13_WIDTH },
8062  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_14_CHECKER_TYPE,
8063  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_14_WIDTH },
8064  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_15_CHECKER_TYPE,
8065  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_15_WIDTH },
8066  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_16_CHECKER_TYPE,
8067  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_16_WIDTH },
8068  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_17_CHECKER_TYPE,
8069  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_17_WIDTH },
8070  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_18_CHECKER_TYPE,
8071  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_18_WIDTH },
8072  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_19_CHECKER_TYPE,
8073  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_19_WIDTH },
8074  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_20_CHECKER_TYPE,
8075  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_20_WIDTH },
8076  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_21_CHECKER_TYPE,
8077  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_21_WIDTH },
8078  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_22_CHECKER_TYPE,
8079  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_22_WIDTH },
8080  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_23_CHECKER_TYPE,
8081  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_23_WIDTH },
8082  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_24_CHECKER_TYPE,
8083  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_24_WIDTH },
8084  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_25_CHECKER_TYPE,
8085  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_25_WIDTH },
8086  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_26_CHECKER_TYPE,
8087  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_26_WIDTH },
8088  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_27_CHECKER_TYPE,
8089  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_27_WIDTH },
8090  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_28_CHECKER_TYPE,
8091  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_28_WIDTH },
8092  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_29_CHECKER_TYPE,
8093  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_29_WIDTH },
8094  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_30_CHECKER_TYPE,
8095  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_30_WIDTH },
8096  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_31_CHECKER_TYPE,
8097  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_31_WIDTH },
8098  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_32_CHECKER_TYPE,
8099  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_32_WIDTH },
8100  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_33_CHECKER_TYPE,
8101  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_33_WIDTH },
8102  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_34_CHECKER_TYPE,
8103  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_34_WIDTH },
8104  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_35_CHECKER_TYPE,
8105  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_35_WIDTH },
8106  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_36_CHECKER_TYPE,
8107  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_36_WIDTH },
8108  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_37_CHECKER_TYPE,
8109  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_37_WIDTH },
8110  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_38_CHECKER_TYPE,
8111  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_38_WIDTH },
8112  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_39_CHECKER_TYPE,
8113  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_39_WIDTH },
8114  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_40_CHECKER_TYPE,
8115  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_40_WIDTH },
8116  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_41_CHECKER_TYPE,
8117  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_41_WIDTH },
8118  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_42_CHECKER_TYPE,
8119  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_42_WIDTH },
8120  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_43_CHECKER_TYPE,
8121  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_43_WIDTH },
8122  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_44_CHECKER_TYPE,
8123  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_44_WIDTH },
8124  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_45_CHECKER_TYPE,
8125  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_45_WIDTH },
8126  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_46_CHECKER_TYPE,
8127  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_46_WIDTH },
8128  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_47_CHECKER_TYPE,
8129  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_47_WIDTH },
8130  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_48_CHECKER_TYPE,
8131  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_48_WIDTH },
8132  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_49_CHECKER_TYPE,
8133  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_49_WIDTH },
8134  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_50_CHECKER_TYPE,
8135  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_50_WIDTH },
8136  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_51_CHECKER_TYPE,
8137  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_51_WIDTH },
8138  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_52_CHECKER_TYPE,
8139  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_52_WIDTH },
8140  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_53_CHECKER_TYPE,
8141  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_53_WIDTH },
8142  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_54_CHECKER_TYPE,
8143  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_54_WIDTH },
8144  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_55_CHECKER_TYPE,
8145  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_55_WIDTH },
8146  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_56_CHECKER_TYPE,
8147  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_56_WIDTH },
8148  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_57_CHECKER_TYPE,
8149  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_57_WIDTH },
8150  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_58_CHECKER_TYPE,
8151  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_58_WIDTH },
8152  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_59_CHECKER_TYPE,
8153  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_59_WIDTH },
8154  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_60_CHECKER_TYPE,
8155  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_60_WIDTH },
8156  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_61_CHECKER_TYPE,
8157  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_61_WIDTH },
8158  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_62_CHECKER_TYPE,
8159  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_62_WIDTH },
8160  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_63_CHECKER_TYPE,
8161  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_63_WIDTH },
8162  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_64_CHECKER_TYPE,
8163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_64_WIDTH },
8164  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_65_CHECKER_TYPE,
8165  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_65_WIDTH },
8166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_66_CHECKER_TYPE,
8167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_66_WIDTH },
8168  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_67_CHECKER_TYPE,
8169  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_67_WIDTH },
8170  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_68_CHECKER_TYPE,
8171  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_68_WIDTH },
8172  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_69_CHECKER_TYPE,
8173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_69_WIDTH },
8174  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_70_CHECKER_TYPE,
8175  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_70_WIDTH },
8176  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_71_CHECKER_TYPE,
8177  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_71_WIDTH },
8178  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_72_CHECKER_TYPE,
8179  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_72_WIDTH },
8180  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_73_CHECKER_TYPE,
8181  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_73_WIDTH },
8182  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_74_CHECKER_TYPE,
8183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_74_WIDTH },
8184  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_75_CHECKER_TYPE,
8185  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_75_WIDTH },
8186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_76_CHECKER_TYPE,
8187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_76_WIDTH },
8188  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_77_CHECKER_TYPE,
8189  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_77_WIDTH },
8190  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_78_CHECKER_TYPE,
8191  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_78_WIDTH },
8192  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_79_CHECKER_TYPE,
8193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_79_WIDTH },
8194  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_80_CHECKER_TYPE,
8195  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_80_WIDTH },
8196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_81_CHECKER_TYPE,
8197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_81_WIDTH },
8198  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_82_CHECKER_TYPE,
8199  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_82_WIDTH },
8200  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_83_CHECKER_TYPE,
8201  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_83_WIDTH },
8202  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_84_CHECKER_TYPE,
8203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_84_WIDTH },
8204  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_85_CHECKER_TYPE,
8205  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_85_WIDTH },
8206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_86_CHECKER_TYPE,
8207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_86_WIDTH },
8208  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_87_CHECKER_TYPE,
8209  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_87_WIDTH },
8210  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_88_CHECKER_TYPE,
8211  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_88_WIDTH },
8212  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_89_CHECKER_TYPE,
8213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_89_WIDTH },
8214  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_90_CHECKER_TYPE,
8215  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_90_WIDTH },
8216  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_91_CHECKER_TYPE,
8217  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_91_WIDTH },
8218  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_92_CHECKER_TYPE,
8219  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_92_WIDTH },
8220  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_93_CHECKER_TYPE,
8221  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_93_WIDTH },
8222  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_94_CHECKER_TYPE,
8223  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_94_WIDTH },
8224  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_95_CHECKER_TYPE,
8225  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_95_WIDTH },
8226  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_96_CHECKER_TYPE,
8227  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_96_WIDTH },
8228  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_97_CHECKER_TYPE,
8229  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_97_WIDTH },
8230  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_98_CHECKER_TYPE,
8231  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_98_WIDTH },
8232  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_99_CHECKER_TYPE,
8233  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_99_WIDTH },
8234  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_100_CHECKER_TYPE,
8235  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_100_WIDTH },
8236  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_101_CHECKER_TYPE,
8237  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_101_WIDTH },
8238  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_102_CHECKER_TYPE,
8239  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_102_WIDTH },
8240  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_103_CHECKER_TYPE,
8241  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_103_WIDTH },
8242  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_104_CHECKER_TYPE,
8243  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_104_WIDTH },
8244  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_105_CHECKER_TYPE,
8245  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_105_WIDTH },
8246  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_106_CHECKER_TYPE,
8247  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_106_WIDTH },
8248  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_107_CHECKER_TYPE,
8249  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_107_WIDTH },
8250  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_108_CHECKER_TYPE,
8251  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_108_WIDTH },
8252  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_109_CHECKER_TYPE,
8253  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_109_WIDTH },
8254  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_110_CHECKER_TYPE,
8255  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_110_WIDTH },
8256  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_111_CHECKER_TYPE,
8257  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_111_WIDTH },
8258  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_112_CHECKER_TYPE,
8259  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_112_WIDTH },
8260  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_113_CHECKER_TYPE,
8261  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_113_WIDTH },
8262  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_114_CHECKER_TYPE,
8263  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_114_WIDTH },
8264  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_115_CHECKER_TYPE,
8265  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_115_WIDTH },
8266  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_116_CHECKER_TYPE,
8267  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_116_WIDTH },
8268 };
8269 
8275 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
8276 {
8277  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
8278  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_0_WIDTH },
8279  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
8280  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_1_WIDTH },
8281  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
8282  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_2_WIDTH },
8283  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
8284  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_3_WIDTH },
8285  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
8286  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_4_WIDTH },
8287  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
8288  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_5_WIDTH },
8289  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
8290  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_6_WIDTH },
8291  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
8292  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_7_WIDTH },
8293  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
8294  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_8_WIDTH },
8295  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
8296  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_9_WIDTH },
8297  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
8298  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_10_WIDTH },
8299  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
8300  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_11_WIDTH },
8301  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
8302  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_12_WIDTH },
8303  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
8304  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_13_WIDTH },
8305  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
8306  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_14_WIDTH },
8307  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
8308  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_15_WIDTH },
8309  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
8310  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_16_WIDTH },
8311  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
8312  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_17_WIDTH },
8313  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
8314  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_18_WIDTH },
8315  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
8316  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_19_WIDTH },
8317  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
8318  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_20_WIDTH },
8319  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
8320  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_21_WIDTH },
8321  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
8322  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_22_WIDTH },
8323  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
8324  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_23_WIDTH },
8325  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
8326  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_24_WIDTH },
8327  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
8328  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_25_WIDTH },
8329  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
8330  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_26_WIDTH },
8331  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
8332  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_27_WIDTH },
8333  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
8334  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_28_WIDTH },
8335  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
8336  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_29_WIDTH },
8337  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
8338  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_30_WIDTH },
8339  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
8340  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_31_WIDTH },
8341  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
8342  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_32_WIDTH },
8343  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
8344  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_33_WIDTH },
8345  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
8346  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_34_WIDTH },
8347  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
8348  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_35_WIDTH },
8349  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
8350  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_36_WIDTH },
8351  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
8352  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_37_WIDTH },
8353  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
8354  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_38_WIDTH },
8355  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
8356  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_39_WIDTH },
8357  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
8358  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_40_WIDTH },
8359  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
8360  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_41_WIDTH },
8361  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
8362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_42_WIDTH },
8363  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
8364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_43_WIDTH },
8365  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
8366  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_44_WIDTH },
8367  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
8368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_45_WIDTH },
8369  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
8370  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_46_WIDTH },
8371  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
8372  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_47_WIDTH },
8373  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
8374  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_48_WIDTH },
8375  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
8376  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_49_WIDTH },
8377  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
8378  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_50_WIDTH },
8379  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
8380  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_51_WIDTH },
8381  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
8382  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_52_WIDTH },
8383  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
8384  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_53_WIDTH },
8385  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
8386  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_54_WIDTH },
8387  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
8388  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_55_WIDTH },
8389  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
8390  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_56_WIDTH },
8391  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
8392  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_57_WIDTH },
8393  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
8394  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_58_WIDTH },
8395  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
8396  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_59_WIDTH },
8397  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
8398  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_60_WIDTH },
8399  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
8400  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_61_WIDTH },
8401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
8402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_62_WIDTH },
8403  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
8404  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_63_WIDTH },
8405  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
8406  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_64_WIDTH },
8407  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
8408  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_65_WIDTH },
8409  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
8410  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_66_WIDTH },
8411  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
8412  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_67_WIDTH },
8413  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
8414  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_68_WIDTH },
8415  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
8416  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_69_WIDTH },
8417  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
8418  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_70_WIDTH },
8419  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
8420  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_71_WIDTH },
8421  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
8422  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_72_WIDTH },
8423  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
8424  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_73_WIDTH },
8425  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
8426  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_74_WIDTH },
8427  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
8428  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_75_WIDTH },
8429  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
8430  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_76_WIDTH },
8431  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
8432  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_77_WIDTH },
8433  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
8434  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_78_WIDTH },
8435  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
8436  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_79_WIDTH },
8437  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
8438  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_80_WIDTH },
8439  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
8440  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_81_WIDTH },
8441  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
8442  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_82_WIDTH },
8443  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
8444  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_83_WIDTH },
8445  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
8446  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_84_WIDTH },
8447  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
8448  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_85_WIDTH },
8449  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
8450  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_86_WIDTH },
8451  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
8452  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_87_WIDTH },
8453  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
8454  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_88_WIDTH },
8455  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
8456  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_89_WIDTH },
8457  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
8458  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_90_WIDTH },
8459  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
8460  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_91_WIDTH },
8461  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
8462  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_92_WIDTH },
8463  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
8464  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_93_WIDTH },
8465  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
8466  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_94_WIDTH },
8467  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
8468  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_95_WIDTH },
8469  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
8470  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_96_WIDTH },
8471  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
8472  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_97_WIDTH },
8473  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
8474  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_98_WIDTH },
8475  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
8476  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_99_WIDTH },
8477  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
8478  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_100_WIDTH },
8479  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
8480  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_101_WIDTH },
8481  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
8482  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_102_WIDTH },
8483  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
8484  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_103_WIDTH },
8485  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
8486  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_104_WIDTH },
8487  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
8488  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_105_WIDTH },
8489  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
8490  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_106_WIDTH },
8491  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
8492  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_107_WIDTH },
8493  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
8494  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_108_WIDTH },
8495  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
8496  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_109_WIDTH },
8497  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
8498  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_110_WIDTH },
8499  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
8500  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_111_WIDTH },
8501  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
8502  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_112_WIDTH },
8503  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
8504  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_113_WIDTH },
8505  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
8506  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_114_WIDTH },
8507  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
8508  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_115_WIDTH },
8509  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
8510  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_116_WIDTH },
8511  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
8512  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_117_WIDTH },
8513  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
8514  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_118_WIDTH },
8515  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
8516  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_119_WIDTH },
8517  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
8518  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_120_WIDTH },
8519  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
8520  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_121_WIDTH },
8521  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
8522  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_122_WIDTH },
8523  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
8524  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_123_WIDTH },
8525  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
8526  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_124_WIDTH },
8527  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
8528  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_125_WIDTH },
8529  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
8530  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_126_WIDTH },
8531  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
8532  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_127_WIDTH },
8533  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
8534  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_128_WIDTH },
8535  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
8536  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_129_WIDTH },
8537  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
8538  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_130_WIDTH },
8539  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
8540  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_131_WIDTH },
8541  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
8542  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_132_WIDTH },
8543  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
8544  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_133_WIDTH },
8545  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
8546  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_134_WIDTH },
8547  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
8548  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_135_WIDTH },
8549  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
8550  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_136_WIDTH },
8551  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
8552  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_137_WIDTH },
8553  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
8554  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_138_WIDTH },
8555  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
8556  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_139_WIDTH },
8557  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
8558  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_140_WIDTH },
8559  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
8560  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_141_WIDTH },
8561  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
8562  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_142_WIDTH },
8563  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
8564  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_143_WIDTH },
8565  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
8566  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_144_WIDTH },
8567  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
8568  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_145_WIDTH },
8569  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
8570  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_146_WIDTH },
8571  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
8572  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_147_WIDTH },
8573  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
8574  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_148_WIDTH },
8575  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
8576  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_149_WIDTH },
8577  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
8578  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_150_WIDTH },
8579  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
8580  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_151_WIDTH },
8581  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
8582  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_152_WIDTH },
8583  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
8584  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_153_WIDTH },
8585  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
8586  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_154_WIDTH },
8587  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
8588  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_155_WIDTH },
8589  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
8590  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_156_WIDTH },
8591  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
8592  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_157_WIDTH },
8593  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
8594  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_158_WIDTH },
8595  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
8596  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_159_WIDTH },
8597  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
8598  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_160_WIDTH },
8599  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
8600  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_161_WIDTH },
8601  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
8602  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_162_WIDTH },
8603  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
8604  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_163_WIDTH },
8605  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
8606  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_164_WIDTH },
8607  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
8608  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_165_WIDTH },
8609  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
8610  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_166_WIDTH },
8611  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
8612  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_167_WIDTH },
8613  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
8614  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_168_WIDTH },
8615  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
8616  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_169_WIDTH },
8617  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
8618  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_170_WIDTH },
8619  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
8620  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_171_WIDTH },
8621  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
8622  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_172_WIDTH },
8623  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
8624  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_173_WIDTH },
8625  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
8626  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_174_WIDTH },
8627  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
8628  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_175_WIDTH },
8629  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
8630  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_176_WIDTH },
8631  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
8632  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_177_WIDTH },
8633  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
8634  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_178_WIDTH },
8635  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
8636  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_179_WIDTH },
8637  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
8638  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_180_WIDTH },
8639  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
8640  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_181_WIDTH },
8641  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
8642  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_182_WIDTH },
8643  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
8644  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_183_WIDTH },
8645  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
8646  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_184_WIDTH },
8647  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
8648  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_185_WIDTH },
8649  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
8650  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_186_WIDTH },
8651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
8652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_187_WIDTH },
8653  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
8654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_188_WIDTH },
8655  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
8656  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_189_WIDTH },
8657  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
8658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_190_WIDTH },
8659  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
8660  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_191_WIDTH },
8661  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
8662  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_192_WIDTH },
8663  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
8664  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_193_WIDTH },
8665  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
8666  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_194_WIDTH },
8667  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
8668  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_195_WIDTH },
8669  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
8670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_196_WIDTH },
8671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
8672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_197_WIDTH },
8673  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
8674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_198_WIDTH },
8675  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
8676  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_199_WIDTH },
8677  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
8678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_200_WIDTH },
8679  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
8680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_201_WIDTH },
8681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
8682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_202_WIDTH },
8683  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
8684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_203_WIDTH },
8685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
8686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_204_WIDTH },
8687  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
8688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_205_WIDTH },
8689  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
8690  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_206_WIDTH },
8691  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
8692  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_207_WIDTH },
8693  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
8694  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_208_WIDTH },
8695  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
8696  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_209_WIDTH },
8697  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
8698  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_210_WIDTH },
8699  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
8700  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_211_WIDTH },
8701  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
8702  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_212_WIDTH },
8703  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
8704  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_213_WIDTH },
8705  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
8706  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_214_WIDTH },
8707  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
8708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_215_WIDTH },
8709  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
8710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_216_WIDTH },
8711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
8712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_217_WIDTH },
8713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
8714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_218_WIDTH },
8715  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
8716  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_219_WIDTH },
8717  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
8718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_220_WIDTH },
8719  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
8720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_221_WIDTH },
8721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
8722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_222_WIDTH },
8723  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
8724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_223_WIDTH },
8725  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
8726  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_224_WIDTH },
8727  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
8728  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_225_WIDTH },
8729  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
8730  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_226_WIDTH },
8731  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
8732  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_227_WIDTH },
8733  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
8734  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_228_WIDTH },
8735  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
8736  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_229_WIDTH },
8737  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
8738  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_230_WIDTH },
8739  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
8740  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_231_WIDTH },
8741  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
8742  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_232_WIDTH },
8743  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
8744  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_233_WIDTH },
8745  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
8746  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_234_WIDTH },
8747  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
8748  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_235_WIDTH },
8749  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
8750  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_236_WIDTH },
8751  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
8752  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_237_WIDTH },
8753  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
8754  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_238_WIDTH },
8755  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
8756  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_239_WIDTH },
8757  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
8758  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_240_WIDTH },
8759  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
8760  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_241_WIDTH },
8761  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
8762  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_242_WIDTH },
8763  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
8764  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_243_WIDTH },
8765  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
8766  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_244_WIDTH },
8767  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
8768  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_245_WIDTH },
8769  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
8770  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_246_WIDTH },
8771  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
8772  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_247_WIDTH },
8773  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
8774  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_248_WIDTH },
8775  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
8776  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_249_WIDTH },
8777  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
8778  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_250_WIDTH },
8779  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
8780  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_251_WIDTH },
8781  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
8782  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_252_WIDTH },
8783  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
8784  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_253_WIDTH },
8785  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
8786  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_254_WIDTH },
8787  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
8788  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_255_WIDTH },
8789 };
8790 
8796 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS] =
8797 {
8798  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
8799  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_0_WIDTH },
8800  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
8801  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_1_WIDTH },
8802  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
8803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_2_WIDTH },
8804  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
8805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_3_WIDTH },
8806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
8807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_4_WIDTH },
8808  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
8809  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_5_WIDTH },
8810  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
8811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_6_WIDTH },
8812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
8813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_7_WIDTH },
8814  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
8815  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_8_WIDTH },
8816  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
8817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_9_WIDTH },
8818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
8819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_10_WIDTH },
8820  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
8821  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_11_WIDTH },
8822  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
8823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_12_WIDTH },
8824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
8825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_13_WIDTH },
8826  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
8827  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_14_WIDTH },
8828  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
8829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_15_WIDTH },
8830  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
8831  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_16_WIDTH },
8832  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
8833  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_17_WIDTH },
8834  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
8835  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_18_WIDTH },
8836  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
8837  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_19_WIDTH },
8838  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
8839  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_20_WIDTH },
8840  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
8841  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_21_WIDTH },
8842  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
8843  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_22_WIDTH },
8844  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
8845  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_23_WIDTH },
8846  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
8847  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_24_WIDTH },
8848  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
8849  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_25_WIDTH },
8850  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
8851  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_26_WIDTH },
8852  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
8853  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_27_WIDTH },
8854  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
8855  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_28_WIDTH },
8856  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
8857  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_29_WIDTH },
8858  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
8859  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_30_WIDTH },
8860  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
8861  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_31_WIDTH },
8862  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
8863  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_32_WIDTH },
8864  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
8865  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_33_WIDTH },
8866  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
8867  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_34_WIDTH },
8868  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
8869  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_35_WIDTH },
8870  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
8871  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_36_WIDTH },
8872  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
8873  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_37_WIDTH },
8874  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
8875  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_38_WIDTH },
8876  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
8877  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_39_WIDTH },
8878  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
8879  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_40_WIDTH },
8880  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
8881  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_41_WIDTH },
8882  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
8883  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_42_WIDTH },
8884  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
8885  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_43_WIDTH },
8886  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
8887  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_44_WIDTH },
8888  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
8889  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_45_WIDTH },
8890  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
8891  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_46_WIDTH },
8892  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
8893  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_47_WIDTH },
8894  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
8895  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_48_WIDTH },
8896  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
8897  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_49_WIDTH },
8898  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
8899  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_50_WIDTH },
8900  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
8901  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_51_WIDTH },
8902  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
8903  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_52_WIDTH },
8904  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
8905  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_53_WIDTH },
8906  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
8907  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_54_WIDTH },
8908  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
8909  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_55_WIDTH },
8910  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
8911  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_56_WIDTH },
8912  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
8913  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_57_WIDTH },
8914  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
8915  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_58_WIDTH },
8916  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
8917  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_59_WIDTH },
8918  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
8919  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_60_WIDTH },
8920  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
8921  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_61_WIDTH },
8922  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
8923  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_62_WIDTH },
8924  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
8925  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_63_WIDTH },
8926  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
8927  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_64_WIDTH },
8928  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
8929  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_65_WIDTH },
8930  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
8931  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_66_WIDTH },
8932  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
8933  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_67_WIDTH },
8934  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
8935  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_68_WIDTH },
8936  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
8937  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_69_WIDTH },
8938  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
8939  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_70_WIDTH },
8940  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
8941  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_71_WIDTH },
8942  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
8943  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_72_WIDTH },
8944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
8945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_73_WIDTH },
8946  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
8947  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_74_WIDTH },
8948  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
8949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_75_WIDTH },
8950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
8951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_76_WIDTH },
8952  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
8953  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_77_WIDTH },
8954  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
8955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_78_WIDTH },
8956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
8957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_79_WIDTH },
8958  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
8959  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_80_WIDTH },
8960  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
8961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_81_WIDTH },
8962  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
8963  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_82_WIDTH },
8964  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
8965  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_83_WIDTH },
8966  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
8967  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_84_WIDTH },
8968  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
8969  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_85_WIDTH },
8970  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
8971  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_86_WIDTH },
8972  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
8973  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_87_WIDTH },
8974  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
8975  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_88_WIDTH },
8976  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
8977  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_89_WIDTH },
8978  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
8979  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_90_WIDTH },
8980  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
8981  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_91_WIDTH },
8982  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
8983  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_92_WIDTH },
8984  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
8985  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_93_WIDTH },
8986  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
8987  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_94_WIDTH },
8988  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
8989  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_95_WIDTH },
8990  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
8991  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_96_WIDTH },
8992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
8993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_97_WIDTH },
8994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
8995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_98_WIDTH },
8996  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
8997  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_99_WIDTH },
8998  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
8999  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_100_WIDTH },
9000  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
9001  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_101_WIDTH },
9002  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
9003  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_102_WIDTH },
9004  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
9005  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_103_WIDTH },
9006  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
9007  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_104_WIDTH },
9008  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
9009  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_105_WIDTH },
9010  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
9011  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_106_WIDTH },
9012  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
9013  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_107_WIDTH },
9014  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
9015  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_108_WIDTH },
9016  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
9017  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_109_WIDTH },
9018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
9019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_110_WIDTH },
9020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
9021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_111_WIDTH },
9022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
9023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_112_WIDTH },
9024  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
9025  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_113_WIDTH },
9026  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
9027  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_114_WIDTH },
9028  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
9029  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_115_WIDTH },
9030  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
9031  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_116_WIDTH },
9032  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
9033  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_117_WIDTH },
9034  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
9035  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_118_WIDTH },
9036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
9037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_119_WIDTH },
9038  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
9039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_120_WIDTH },
9040 };
9041 
9047 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9048 {
9049  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9050  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_0_WIDTH },
9051  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9052  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_1_WIDTH },
9053  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9054  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_2_WIDTH },
9055  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9056  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_3_WIDTH },
9057  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9058  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_4_WIDTH },
9059  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9060  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_5_WIDTH },
9061  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9062  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_6_WIDTH },
9063  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9064  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_7_WIDTH },
9065  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9066  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_8_WIDTH },
9067  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9068  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_9_WIDTH },
9069  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9070  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_10_WIDTH },
9071  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9072  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_11_WIDTH },
9073  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9074  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_12_WIDTH },
9075  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9076  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_13_WIDTH },
9077  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9078  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_14_WIDTH },
9079  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9080  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_15_WIDTH },
9081  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9082  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_16_WIDTH },
9083  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9084  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_17_WIDTH },
9085  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9086  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_18_WIDTH },
9087  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9088  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_19_WIDTH },
9089  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9090  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_20_WIDTH },
9091  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9092  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_21_WIDTH },
9093  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9094  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_22_WIDTH },
9095  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9096  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_23_WIDTH },
9097  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9098  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_24_WIDTH },
9099  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9100  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_25_WIDTH },
9101  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9102  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_26_WIDTH },
9103  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9104  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_27_WIDTH },
9105  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9106  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_28_WIDTH },
9107  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9108  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_29_WIDTH },
9109  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9110  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_30_WIDTH },
9111  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9112  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_31_WIDTH },
9113  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9114  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_32_WIDTH },
9115  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9116  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_33_WIDTH },
9117  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9118  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_34_WIDTH },
9119  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9120  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_35_WIDTH },
9121  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9122  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_36_WIDTH },
9123  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9124  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_37_WIDTH },
9125  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9126  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_38_WIDTH },
9127  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9128  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_39_WIDTH },
9129  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9130  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_40_WIDTH },
9131  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9132  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_41_WIDTH },
9133  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9134  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_42_WIDTH },
9135  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9136  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_43_WIDTH },
9137  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9138  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_44_WIDTH },
9139  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9140  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_45_WIDTH },
9141  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9142  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_46_WIDTH },
9143  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9144  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_47_WIDTH },
9145  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9146  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_48_WIDTH },
9147  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9148  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_49_WIDTH },
9149  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9150  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_50_WIDTH },
9151  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9152  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_51_WIDTH },
9153  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9154  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_52_WIDTH },
9155  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9156  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_53_WIDTH },
9157  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9158  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_54_WIDTH },
9159  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9160  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_55_WIDTH },
9161  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9162  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_56_WIDTH },
9163  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9164  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_57_WIDTH },
9165  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9166  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_58_WIDTH },
9167  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9168  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_59_WIDTH },
9169  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9170  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_60_WIDTH },
9171  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9172  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_61_WIDTH },
9173 };
9174 
9180 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9181 {
9182  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
9184  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9185  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
9186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
9188  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9189  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
9190  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9191  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
9192  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
9194  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9195  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
9196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
9198  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9199  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
9200  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9201  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
9202  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
9204  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9205  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
9206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
9208  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9209  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
9210  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9211  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
9212  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
9214  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9215  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
9216  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9217  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
9218  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9219  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
9220  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9221  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
9222  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9223  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
9224  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9225  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
9226  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9227  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
9228  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9229  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
9230  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9231  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
9232  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9233  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
9234 };
9235 
9241 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9242 {
9243  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9244  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
9245  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9246  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
9247  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9248  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
9249  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9250  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
9251  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9252  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
9253  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9254  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
9255  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9256  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
9257  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9258  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
9259  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9260  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
9261  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9262  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
9263  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9264  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
9265  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9266  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
9267  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9268  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
9269  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9270  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
9271  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9272  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
9273  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9274  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
9275  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9276  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
9277  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9278  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
9279  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9280  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
9281  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9282  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
9283  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9284  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
9285  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9286  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
9287  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9288  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
9289  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9290  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
9291  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9292  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
9293  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9294  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
9295  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9296  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
9297  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9298  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
9299  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9300  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
9301  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9302  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
9303  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9304  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
9305  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9306  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
9307  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9308  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
9309  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9310  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
9311  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9312  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
9313  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9314  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
9315  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9316  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
9317  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9318  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
9319  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9320  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
9321  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9322  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
9323  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9324  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
9325  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9326  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
9327  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9328  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
9329  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9330  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
9331  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9332  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
9333  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9334  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
9335  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9336  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
9337  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9338  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
9339 };
9340 
9346 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9347 {
9348  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9349  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
9350  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9351  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
9352  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9353  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
9354  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9355  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
9356  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9357  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
9358  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9359  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
9360  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9361  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
9362  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9363  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
9364  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9365  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
9366  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9367  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
9368  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9369  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
9370  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9371  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
9372  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9373  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
9374  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9375  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
9376  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9377  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
9378  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9379  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
9380  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9381  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
9382  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9383  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
9384  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9385  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
9386  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9387  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
9388  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9389  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
9390  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9391  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
9392  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9393  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
9394  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9395  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
9396  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9397  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
9398  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9399  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
9400  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9401  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
9402  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9403  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
9404  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9405  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
9406  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9407  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
9408  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9409  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
9410  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9411  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
9412  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9413  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
9414  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9415  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
9416  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9417  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
9418  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9419  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
9420  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9421  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
9422  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9423  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
9424 };
9425 
9431 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9432 {
9433  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9434  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
9435  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9436  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
9437  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9438  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
9439  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9440  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
9441  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9442  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
9443  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9444  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
9445  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9446  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
9447  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9448  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
9449  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9450  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
9451  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9452  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
9453  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9454  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
9455  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9456  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
9457  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9458  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
9459  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9460  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
9461  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9462  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
9463  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9464  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
9465  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9466  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
9467  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9468  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
9469  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9470  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
9471  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9472  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
9473  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9474  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
9475  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9476  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
9477  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9478  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
9479  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9480  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
9481  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9482  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
9483  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9484  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
9485  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9486  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
9487  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9488  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
9489  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9490  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
9491  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9492  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
9493  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9494  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
9495  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9496  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
9497  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9498  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
9499  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9500  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
9501  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9502  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
9503  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9504  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
9505  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9506  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
9507  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9508  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
9509 };
9510 
9516 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9517 {
9518  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9519  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
9520  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9521  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
9522  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9523  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
9524  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9525  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
9526  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9527  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
9528  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9529  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
9530  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9531  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
9532  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9533  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
9534  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9535  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
9536  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9537  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
9538  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9539  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
9540  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9541  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
9542  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9543  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
9544  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9545  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
9546  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9547  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
9548  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9549  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
9550  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9551  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
9552  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9553  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
9554  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9555  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
9556  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9557  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
9558  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9559  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
9560  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9561  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
9562  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9563  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
9564  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9565  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
9566  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9567  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
9568  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9569  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
9570  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9571  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
9572  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9573  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
9574  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9575  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
9576  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9577  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
9578  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9579  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
9580  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9581  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
9582  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9583  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
9584  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9585  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
9586  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9587  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
9588  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9589  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
9590  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9591  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
9592  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9593  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
9594  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9595  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
9596  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9597  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
9598 };
9599 
9605 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9606 {
9607  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9608  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
9609  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9610  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
9611  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9612  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
9613  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9614  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
9615  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9616  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
9617  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9618  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
9619  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9620  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
9621  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9622  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
9623  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9624  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
9625  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9626  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
9627  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9628  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
9629  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9630  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
9631  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9632  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
9633  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9634  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
9635  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9636  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
9637  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9638  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
9639  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9640  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
9641  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9642  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
9643  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9644  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
9645  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9646  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
9647  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9648  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
9649  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9650  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
9651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
9653  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
9655  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9656  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
9657  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
9659  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9660  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
9661  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9662  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
9663  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9664  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
9665  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9666  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
9667  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9668  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
9669  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
9671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
9673  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
9675  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9676  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
9677  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
9679  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
9681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
9683  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
9685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
9687 };
9688 
9694 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9695 {
9696  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9697  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
9698  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9699  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
9700  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9701  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
9702  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9703  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
9704  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9705  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
9706  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9707  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
9708  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9709  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
9710  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9711  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
9712  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9713  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
9714  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9715  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
9716  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9717  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
9718  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9719  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
9720  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9721  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
9722  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9723  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
9724  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9725  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
9726  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9727  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
9728  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9729  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
9730  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9731  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
9732  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9733  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
9734  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9735  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
9736  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9737  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
9738  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9739  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
9740  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9741  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
9742  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9743  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
9744  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9745  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
9746  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9747  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
9748  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9749  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
9750  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9751  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
9752  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9753  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
9754  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9755  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
9756  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9757  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
9758  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9759  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
9760  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9761  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
9762  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9763  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
9764  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9765  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
9766  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9767  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_35_WIDTH },
9768  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9769  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_36_WIDTH },
9770  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9771  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_37_WIDTH },
9772  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9773  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_38_WIDTH },
9774  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9775  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_39_WIDTH },
9776 };
9777 
9783 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9784 {
9785  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9786  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
9787  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9788  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
9789  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9790  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
9791 };
9792 
9798 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9799 {
9800  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9801  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9802  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9804  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9808  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9809  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9810  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9814  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9815  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9816  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9820  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
9821  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
9822  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
9823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
9824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
9825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
9826  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
9827  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
9828  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
9829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
9830  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
9831  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
9832  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
9833  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
9834  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
9835  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
9836  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
9837  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
9838  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
9839  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
9840  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
9841  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
9842  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
9843  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
9844  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
9845  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
9846  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
9847  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
9848  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
9849  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
9850  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
9851  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
9852  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
9853  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
9854  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
9855  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
9856  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
9857  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
9858  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
9859  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
9860  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
9861  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
9862  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
9863  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
9864  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
9865  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
9866  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
9867  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
9868  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
9869  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
9870  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
9871  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
9872  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
9873  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
9874  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
9875  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
9876  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
9877  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
9878  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
9879  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
9880  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
9881  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
9882  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
9883  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
9884  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
9885  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
9886  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
9887  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
9888  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
9889  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
9890  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
9891  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
9892  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
9893  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
9894  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
9895  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
9896  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
9897  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
9898  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
9899  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
9900  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
9901  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
9902  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
9903  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
9904  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
9905  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
9906  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
9907  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
9908  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
9909  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
9910  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
9911  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
9912  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
9913  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
9914  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
9915  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
9916  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
9917  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
9918  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
9919  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
9920  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
9921  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
9922  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
9923  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
9924  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
9925  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
9926  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
9927  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
9928  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
9929  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
9930  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
9931  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
9932  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
9933  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
9934  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
9935  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
9936  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
9937  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
9938  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
9939  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
9940  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
9941  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
9942  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
9943  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
9944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
9945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
9946  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
9947  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
9948  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
9949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
9950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
9951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
9952  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
9953  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
9954  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
9955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
9956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
9957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
9958  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
9959  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
9960  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
9961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
9962  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
9963  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
9964  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
9965  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
9966  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
9967  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
9968  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
9969  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
9970 };
9971 
9977 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
9978 {
9979  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
9980  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
9981  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
9982  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
9983  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
9984  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
9985  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
9986  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
9987  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
9988  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
9989  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
9990  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
9991  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
9992  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
9993  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
9994  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
9995  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
9996  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
9997  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
9998  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
9999  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10000  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10001  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10002  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10003  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10004  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10005  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10006  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10007  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10008  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10009  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10010  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10011  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10012  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10013  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10014  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10015  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10016  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10017  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10018  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10019  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10020  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10021  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10022  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10023  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10024  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10025  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10026  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10027  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10028  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10029  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10030  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10031  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10032  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10033  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10034  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10035  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10036  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10037  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10038  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10039  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10040  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10041  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10042  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10043  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10044  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10045  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10046  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10047  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10048  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10049  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10050  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10051  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10052  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10053  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10054  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10055  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10056  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10057  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10058  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10059  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10060  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10061  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10062  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10063  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10064  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10065  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10066  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10067  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10068  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10069  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10070  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10071  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10072  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10073  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10074  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10075  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10076  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10077  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10078  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10079  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10080  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10081  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10082  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10083  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10084  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10085  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10086  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10087  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10088  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10089  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10090  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10091  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10092  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10093  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10094  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10095  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10096  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10097  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10098  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10099  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10100  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10101  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10102  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10103  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10104  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10105  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10106  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10107  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10108  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10109  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10110  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10111  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10112  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10113  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10114  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10115  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10116  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10117  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10118  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10119  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10120  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10121  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10122  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10123  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10124  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10125  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10126  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10127  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10128  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10129  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10130  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10131  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10132  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10133  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10134  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10135  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10136  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10137  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10138  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10139  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10140  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10141  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10142  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10143 };
10144 
10150 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10151 {
10152  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10153  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
10154 };
10155 
10161 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10162 {
10163  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10164  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
10165  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10166  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
10167  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10168  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
10169  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10170  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
10171  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10172  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
10173  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10174  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
10175  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10176  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
10177  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10178  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
10179  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10180  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
10181  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10182  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
10183  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10184  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
10185  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10186  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
10187  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10188  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
10189  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10190  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
10191  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10192  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
10193  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10194  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
10195  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10196  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
10197  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10198  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
10199  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10200  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
10201  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10202  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
10203  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10204  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
10205  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10206  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
10207  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10208  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
10209  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10210  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
10211  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10212  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
10213  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10214  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
10215  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10216  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
10217  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10218  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
10219  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10220  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
10221  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10222  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
10223  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10224  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
10225  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10226  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
10227  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10228  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
10229  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10230  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
10231  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10232  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
10233  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10234  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
10235  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10236  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
10237  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10238  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
10239  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10240  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
10241  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10242  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
10243  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10244  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
10245  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10246  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
10247  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10248  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
10249  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10250  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
10251  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10252  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
10253  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10254  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
10255  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10256  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
10257  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10258  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
10259  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
10260  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
10261  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
10262  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
10263  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
10264  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
10265  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
10266  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
10267  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
10268  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
10269  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
10270  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
10271  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
10272  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
10273  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
10274  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
10275  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
10276  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
10277  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
10278  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
10279  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
10280  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
10281  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
10282  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
10283  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
10284  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
10285  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
10286  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
10287  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
10288  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
10289  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
10290  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
10291  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
10292  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
10293  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
10294  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
10295  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
10296  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
10297  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
10298  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
10299  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
10300  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
10301  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
10302  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
10303  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
10304  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
10305  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
10306  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
10307  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
10308  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
10309  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
10310  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
10311  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
10312  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
10313  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
10314  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
10315  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
10316  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
10317  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
10318  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
10319  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
10320  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
10321  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
10322  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
10323  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
10324  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
10325  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
10326  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
10327  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
10328  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
10329  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
10330  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
10331  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
10332  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
10333  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
10334  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
10335  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
10336  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
10337  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
10338  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
10339  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
10340  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
10341  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
10342  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
10343  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
10344  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
10345  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
10346  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
10347  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
10348  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
10349  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
10350  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
10351  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
10352  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
10353  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
10354  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
10355  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
10356  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
10357  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
10358  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
10359  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
10360  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
10361  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
10362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
10363  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
10364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
10365  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
10366  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
10367  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
10368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
10369 };
10370 
10376 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS] =
10377 {
10378  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_0_CHECKER_TYPE,
10379  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_0_WIDTH },
10380  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_1_CHECKER_TYPE,
10381  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_1_WIDTH },
10382  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_2_CHECKER_TYPE,
10383  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_2_WIDTH },
10384  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_3_CHECKER_TYPE,
10385  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_3_WIDTH },
10386  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_4_CHECKER_TYPE,
10387  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_4_WIDTH },
10388  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_5_CHECKER_TYPE,
10389  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_5_WIDTH },
10390  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_6_CHECKER_TYPE,
10391  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_6_WIDTH },
10392  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_7_CHECKER_TYPE,
10393  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_7_WIDTH },
10394  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_8_CHECKER_TYPE,
10395  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_8_WIDTH },
10396  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_9_CHECKER_TYPE,
10397  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_9_WIDTH },
10398  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_10_CHECKER_TYPE,
10399  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_10_WIDTH },
10400  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_11_CHECKER_TYPE,
10401  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_11_WIDTH },
10402  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_12_CHECKER_TYPE,
10403  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_12_WIDTH },
10404  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_13_CHECKER_TYPE,
10405  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_13_WIDTH },
10406  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_14_CHECKER_TYPE,
10407  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_14_WIDTH },
10408  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_15_CHECKER_TYPE,
10409  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_15_WIDTH },
10410  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_16_CHECKER_TYPE,
10411  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_16_WIDTH },
10412  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_17_CHECKER_TYPE,
10413  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_17_WIDTH },
10414  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_18_CHECKER_TYPE,
10415  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_18_WIDTH },
10416  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_19_CHECKER_TYPE,
10417  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_19_WIDTH },
10418  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_20_CHECKER_TYPE,
10419  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_20_WIDTH },
10420  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_21_CHECKER_TYPE,
10421  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_21_WIDTH },
10422  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_22_CHECKER_TYPE,
10423  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_22_WIDTH },
10424  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_23_CHECKER_TYPE,
10425  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_23_WIDTH },
10426  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_24_CHECKER_TYPE,
10427  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_24_WIDTH },
10428  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_25_CHECKER_TYPE,
10429  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_25_WIDTH },
10430  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_26_CHECKER_TYPE,
10431  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_26_WIDTH },
10432  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_27_CHECKER_TYPE,
10433  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_27_WIDTH },
10434  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_28_CHECKER_TYPE,
10435  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_28_WIDTH },
10436  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_29_CHECKER_TYPE,
10437  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_29_WIDTH },
10438  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_30_CHECKER_TYPE,
10439  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_30_WIDTH },
10440  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_31_CHECKER_TYPE,
10441  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_31_WIDTH },
10442  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_32_CHECKER_TYPE,
10443  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_32_WIDTH },
10444  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_33_CHECKER_TYPE,
10445  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_33_WIDTH },
10446  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_34_CHECKER_TYPE,
10447  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_34_WIDTH },
10448  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_35_CHECKER_TYPE,
10449  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_35_WIDTH },
10450  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_36_CHECKER_TYPE,
10451  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_36_WIDTH },
10452 };
10453 
10459 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS] =
10460 {
10461  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_0_CHECKER_TYPE,
10462  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_0_WIDTH },
10463  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_1_CHECKER_TYPE,
10464  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_1_WIDTH },
10465  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_2_CHECKER_TYPE,
10466  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_2_WIDTH },
10467  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_3_CHECKER_TYPE,
10468  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_3_WIDTH },
10469  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_4_CHECKER_TYPE,
10470  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_4_WIDTH },
10471  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_5_CHECKER_TYPE,
10472  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_5_WIDTH },
10473  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_6_CHECKER_TYPE,
10474  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_6_WIDTH },
10475  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_7_CHECKER_TYPE,
10476  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_7_WIDTH },
10477  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_8_CHECKER_TYPE,
10478  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_8_WIDTH },
10479  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_9_CHECKER_TYPE,
10480  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_9_WIDTH },
10481  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_10_CHECKER_TYPE,
10482  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_10_WIDTH },
10483  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_11_CHECKER_TYPE,
10484  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_11_WIDTH },
10485  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_12_CHECKER_TYPE,
10486  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_12_WIDTH },
10487  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_13_CHECKER_TYPE,
10488  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_13_WIDTH },
10489  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_14_CHECKER_TYPE,
10490  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_14_WIDTH },
10491  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_15_CHECKER_TYPE,
10492  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_15_WIDTH },
10493  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_16_CHECKER_TYPE,
10494  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_16_WIDTH },
10495  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_17_CHECKER_TYPE,
10496  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_17_WIDTH },
10497  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_18_CHECKER_TYPE,
10498  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_18_WIDTH },
10499  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_19_CHECKER_TYPE,
10500  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_19_WIDTH },
10501  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_20_CHECKER_TYPE,
10502  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_20_WIDTH },
10503  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_21_CHECKER_TYPE,
10504  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_21_WIDTH },
10505  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_22_CHECKER_TYPE,
10506  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_22_WIDTH },
10507  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_23_CHECKER_TYPE,
10508  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_23_WIDTH },
10509  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_24_CHECKER_TYPE,
10510  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_24_WIDTH },
10511  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_25_CHECKER_TYPE,
10512  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_25_WIDTH },
10513  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_26_CHECKER_TYPE,
10514  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_26_WIDTH },
10515  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_27_CHECKER_TYPE,
10516  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_27_WIDTH },
10517  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_28_CHECKER_TYPE,
10518  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_28_WIDTH },
10519  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_29_CHECKER_TYPE,
10520  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_29_WIDTH },
10521  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_30_CHECKER_TYPE,
10522  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_30_WIDTH },
10523  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_31_CHECKER_TYPE,
10524  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_31_WIDTH },
10525  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_32_CHECKER_TYPE,
10526  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_32_WIDTH },
10527  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_33_CHECKER_TYPE,
10528  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_33_WIDTH },
10529  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_34_CHECKER_TYPE,
10530  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_34_WIDTH },
10531  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_35_CHECKER_TYPE,
10532  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_35_WIDTH },
10533  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_36_CHECKER_TYPE,
10534  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_36_WIDTH },
10535 };
10536 
10542 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10543 {
10544  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10545  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
10546  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10547  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
10548  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10549  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
10550  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10551  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
10552  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10553  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
10554  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10555  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
10556  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10557  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
10558  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10559  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
10560  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10561  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
10562  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10563  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
10564  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10565  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
10566  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10567  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
10568  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10569  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
10570  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10571  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
10572  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10573  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
10574  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10575  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
10576  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10577  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
10578  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10579  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
10580  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10581  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
10582  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10583  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
10584  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10585  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
10586  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10587  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
10588  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10589  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
10590  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10591  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
10592  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10593  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
10594  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10595  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
10596  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10597  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
10598  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10599  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
10600  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10601  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
10602  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10603  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
10604  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10605  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
10606  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10607  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
10608  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10609  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
10610  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10611  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
10612  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10613  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
10614  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10615  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
10616  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10617  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
10618  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10619  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
10620 };
10621 
10627 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10628 {
10629  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10630  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
10631  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10632  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
10633  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10634  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
10635  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10636  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
10637  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10638  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
10639  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10640  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
10641  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10642  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
10643  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10644  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
10645  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10646  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
10647  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10648  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
10649  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10650  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
10651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
10653  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
10655  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10656  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
10657  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
10659  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10660  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
10661  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10662  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
10663  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10664  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
10665  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10666  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
10667  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10668  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
10669  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
10671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
10673  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
10675  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10676  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
10677  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
10679  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
10681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
10683  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
10685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
10687  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
10689  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10690  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
10691  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10692  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
10693  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10694  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
10695  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10696  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
10697  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10698  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
10699  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10700  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
10701  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10702  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
10703  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10704  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
10705  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10706  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
10707  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
10709  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
10711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
10713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
10715  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10716  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
10717  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
10719  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
10721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
10723  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
10725 };
10726 
10732 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10733 {
10734  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10735  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
10736  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10737  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
10738  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10739  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
10740  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10741  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
10742  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10743  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
10744  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10745  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
10746  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10747  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
10748  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10749  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
10750  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10751  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
10752  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10753  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
10754  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10755  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
10756  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10757  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
10758  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10759  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
10760  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10761  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
10762  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10763  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
10764  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10765  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
10766  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10767  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
10768  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10769  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
10770  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10771  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
10772  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10773  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
10774  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10775  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
10776  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10777  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
10778  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10779  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
10780  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10781  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
10782  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10783  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
10784  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10785  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
10786  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10787  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
10788  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10789  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
10790  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10791  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
10792  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10793  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
10794  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10795  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
10796  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10797  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
10798  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10799  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
10800  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10801  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
10802  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
10804  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
10806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
10808  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10809  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
10810  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
10812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
10814  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10815  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
10816  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
10818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
10820  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10821  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
10822  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
10824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
10826  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10827  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
10828  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
10830 };
10831 
10837 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10838 {
10839  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10840  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
10841  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10842  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
10843  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10844  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
10845  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10846  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
10847  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10848  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
10849  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10850  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
10851  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10852  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
10853  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10854  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
10855  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10856  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
10857  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10858  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
10859  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10860  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
10861  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10862  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
10863  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10864  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
10865  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10866  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
10867  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10868  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
10869  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10870  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
10871  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10872  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
10873  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10874  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
10875  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10876  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
10877  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10878  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
10879  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10880  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
10881  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10882  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
10883  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10884  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
10885  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10886  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
10887  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10888  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
10889  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10890  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
10891  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10892  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
10893  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10894  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
10895  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
10896  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
10897  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
10898  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
10899  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
10900  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
10901  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
10902  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
10903  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
10904  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
10905  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
10906  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
10907  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
10908  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
10909  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
10910  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
10911  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
10912  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
10913  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
10914  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
10915  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
10916  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
10917  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
10918  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
10919  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
10920  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
10921  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
10922  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
10923  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
10924  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
10925  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
10926  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
10927  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
10928  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
10929  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
10930  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
10931  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
10932  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
10933  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
10934  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
10935 };
10936 
10942 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
10943 {
10944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
10945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
10946  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
10947  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
10948  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
10949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
10950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
10951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
10952  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
10953  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
10954  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
10955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
10956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
10957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
10958  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
10959  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
10960  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
10961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
10962  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
10963  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
10964  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
10965  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
10966  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
10967  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
10968  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
10969  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
10970  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
10971  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
10972  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
10973  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
10974  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
10975  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
10976  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
10977  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
10978  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
10979  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
10980  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
10981  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
10982  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
10983  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
10984  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
10985  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
10986  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
10987  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
10988  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
10989  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
10990  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
10991  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
10992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
10993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
10994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
10995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
10996  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
10997  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
10998  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
10999  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
11000  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11001  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
11002  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11003  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
11004  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11005  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
11006  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11007  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
11008  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11009  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
11010  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11011  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
11012  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11013  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
11014  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11015  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
11016  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11017  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
11018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
11020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
11022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
11024  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
11025  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
11026  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
11027  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
11028  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
11029  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
11030  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
11031  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
11032  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
11033  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
11034  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
11035  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
11036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
11037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
11038  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
11039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
11040 };
11041 
11047 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11048 {
11049  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11050  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
11051  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11052  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
11053  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11054  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
11055  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11056  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
11057  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11058  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
11059  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11060  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
11061  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11062  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
11063  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11064  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
11065  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11066  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
11067  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11068  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
11069  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11070  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
11071  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11072  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
11073  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11074  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
11075  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11076  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
11077  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11078  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
11079  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11080  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
11081  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11082  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
11083  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11084  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
11085  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11086  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
11087  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11088  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
11089  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11090  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
11091  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11092  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
11093  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11094  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
11095  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11096  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
11097  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11098  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
11099  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11100  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
11101  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11102  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
11103  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11104  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
11105  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11106  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
11107  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11108  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
11109  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11110  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
11111  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11112  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
11113  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11114  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
11115  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11116  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
11117  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11118  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
11119  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11120  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
11121  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11122  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
11123  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11124  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
11125  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11126  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
11127  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11128  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
11129  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
11130  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
11131  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
11132  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
11133  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
11134  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
11135  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
11136  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
11137  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
11138  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
11139  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
11140  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
11141  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
11142  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
11143  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
11144  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
11145 };
11146 
11152 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11153 {
11154  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11155  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
11156  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11157  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
11158  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11159  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
11160  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11161  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
11162  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
11164  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11165  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
11166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
11168  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11169  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
11170  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11171  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
11172  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
11174  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11175  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
11176  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11177  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
11178  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11179  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
11180  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11181  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
11182  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
11184  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11185  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
11186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
11188  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11189  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
11190  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11191  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
11192  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
11194  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11195  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
11196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
11198  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11199  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
11200  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11201  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
11202  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
11204  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11205  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
11206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
11208  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11209  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
11210  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11211  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
11212  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
11214 };
11215 
11221 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11222 {
11223  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11224  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
11225  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11226  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
11227  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11228  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
11229  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11230  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
11231  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11232  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
11233  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11234  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
11235  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11236  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
11237  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11238  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
11239  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11240  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
11241  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11242  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
11243  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11244  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
11245  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11246  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
11247  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11248  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
11249  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11250  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
11251  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11252  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
11253  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11254  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
11255  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11256  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
11257  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11258  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
11259  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11260  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
11261  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11262  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
11263  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11264  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
11265  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11266  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
11267  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11268  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
11269  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11270  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
11271  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11272  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
11273  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11274  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
11275  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11276  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
11277  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11278  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
11279  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11280  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
11281  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11282  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
11283 };
11284 
11290 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11291 {
11292  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11293  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
11294  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11295  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
11296  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11297  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
11298  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11299  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
11300  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11301  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
11302  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11303  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
11304  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11305  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
11306  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11307  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
11308  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11309  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
11310  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11311  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
11312  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11313  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
11314  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11315  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
11316  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11317  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
11318  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11319  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
11320  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11321  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
11322  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11323  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
11324  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11325  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
11326  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11327  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
11328  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11329  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
11330  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11331  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
11332  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11333  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
11334  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11335  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
11336  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11337  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
11338  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11339  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
11340  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11341  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
11342  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11343  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
11344  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11345  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
11346  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11347  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
11348  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11349  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
11350  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11351  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
11352 };
11353 
11359 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11360 {
11361  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
11363  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
11365  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11366  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
11367  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
11369  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11370  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
11371  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11372  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
11373  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11374  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
11375  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11376  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
11377  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11378  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
11379  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11380  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
11381  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11382  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
11383  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11384  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
11385  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11386  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
11387  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11388  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
11389  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11390  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
11391  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11392  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
11393  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11394  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
11395  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11396  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
11397  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11398  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
11399  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11400  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
11401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
11403  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11404  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
11405  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11406  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
11407  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11408  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
11409  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11410  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
11411  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11412  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
11413  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11414  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
11415  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11416  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
11417  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11418  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
11419  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11420  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
11421  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11422  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
11423  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11424  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
11425  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11426  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
11427  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11428  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
11429  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11430  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
11431  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11432  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
11433  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11434  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
11435  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11436  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
11437  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11438  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
11439  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11440  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
11441  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
11442  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
11443  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
11444  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
11445 };
11446 
11452 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11453 {
11454  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11455  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
11456  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11457  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
11458  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11459  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
11460  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11461  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
11462  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11463  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
11464  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11465  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
11466  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11467  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
11468  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11469  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
11470  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11471  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
11472  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11473  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
11474  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11475  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
11476  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11477  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
11478  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11479  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
11480  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11481  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
11482  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11483  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
11484  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11485  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
11486  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11487  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
11488  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11489  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
11490  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11491  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
11492  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11493  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
11494  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11495  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
11496  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11497  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
11498  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11499  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
11500  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11501  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
11502  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11503  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
11504  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11505  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
11506  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11507  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
11508  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11509  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
11510  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11511  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
11512  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11513  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
11514  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11515  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
11516  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11517  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
11518  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11519  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
11520  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11521  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
11522  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11523  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
11524  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11525  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
11526  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11527  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
11528  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11529  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
11530  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11531  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
11532  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11533  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
11534  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
11535  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
11536  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
11537  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
11538  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
11539  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
11540  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
11541  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
11542  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
11543  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
11544  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
11545  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
11546  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
11547  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
11548  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
11549  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
11550  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
11551  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
11552  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
11553  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
11554  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
11555  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
11556  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
11557  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
11558  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
11559  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
11560  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
11561  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
11562  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
11563  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
11564  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
11565  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
11566  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
11567  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
11568  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
11569  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
11570  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
11571  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
11572  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
11573  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
11574  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
11575  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
11576  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
11577  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
11578  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
11579  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
11580  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
11581  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
11582  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
11583  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
11584  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
11585  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
11586  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
11587  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
11588  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
11589  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
11590  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
11591  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
11592  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
11593  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
11594  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
11595  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
11596  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
11597  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
11598  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
11599  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
11600  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
11601  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
11602  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
11603  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
11604  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
11605  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
11606  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
11607  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
11608  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
11609  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
11610  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
11611  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
11612  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
11613  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
11614  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
11615  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
11616  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
11617  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
11618  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
11619  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
11620  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
11621  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
11622  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
11623  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
11624  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
11625  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
11626  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
11627  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
11628  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
11629  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
11630  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
11631  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
11632  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
11633  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
11634  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
11635  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
11636  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
11637  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
11638  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
11639  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
11640  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
11641  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
11642  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
11643  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
11644  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
11645  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
11646  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
11647  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
11648  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
11649  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
11650  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
11651  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
11652  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
11653  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
11654  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
11655  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
11656  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
11657  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_WIDTH },
11658  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
11659  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_WIDTH },
11660  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
11661  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_WIDTH },
11662  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
11663  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_WIDTH },
11664  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
11665  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_WIDTH },
11666  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
11667  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_WIDTH },
11668  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
11669  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_WIDTH },
11670  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
11671  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_WIDTH },
11672  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
11673  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_WIDTH },
11674  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
11675  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_WIDTH },
11676 };
11677 
11683 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11684 {
11685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
11687  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
11689  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11690  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
11691  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11692  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
11693  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11694  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
11695  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11696  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
11697  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11698  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
11699  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11700  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
11701  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11702  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
11703  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11704  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
11705  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11706  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
11707  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
11709  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
11711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
11713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
11715  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11716  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
11717  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
11719  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
11721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
11723  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
11725  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11726  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
11727  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11728  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
11729  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11730  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
11731  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11732  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
11733  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11734  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
11735  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11736  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
11737  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11738  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
11739  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11740  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
11741  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11742  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
11743  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11744  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
11745  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11746  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
11747  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11748  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
11749  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11750  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
11751  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11752  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
11753  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11754  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
11755  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11756  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
11757  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11758  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
11759  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11760  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
11761  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11762  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
11763  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11764  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
11765  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
11766  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
11767  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
11768  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
11769  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
11770  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
11771  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
11772  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
11773  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
11774  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
11775  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
11776  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
11777  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
11778  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
11779  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
11780  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
11781  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
11782  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
11783  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
11784  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
11785  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
11786  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
11787  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
11788  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
11789  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
11790  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
11791  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
11792  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
11793  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
11794  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
11795  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
11796  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
11797  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
11798  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
11799  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
11800  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
11801  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
11802  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
11803  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
11804  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
11805  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
11806  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
11807  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
11808  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
11809  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
11810  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
11811  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
11812  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
11813  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
11814  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
11815  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
11816  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
11817  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
11818  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
11819  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
11820  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
11821  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
11822  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
11823  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
11824  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
11825  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
11826  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
11827  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
11828  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
11829  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
11830  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
11831  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
11832  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
11833  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
11834  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
11835  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
11836  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
11837  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
11838  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
11839  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
11840  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
11841  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
11842  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
11843  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
11844  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
11845  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
11846  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
11847  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
11848  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
11849  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
11850  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
11851  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
11852  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
11853  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
11854  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
11855  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
11856  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
11857  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
11858  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
11859  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
11860  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
11861  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
11862  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
11863  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
11864  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
11865  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
11866  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
11867  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
11868  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
11869  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
11870  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
11871  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
11872  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
11873  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
11874  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
11875  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
11876  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
11877  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
11878  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
11879  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
11880  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
11881  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
11882  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
11883  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
11884  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
11885  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
11886  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
11887  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
11888  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_WIDTH },
11889  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
11890  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_WIDTH },
11891  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
11892  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_WIDTH },
11893  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
11894  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_WIDTH },
11895  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
11896  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_WIDTH },
11897  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
11898  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_WIDTH },
11899  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
11900  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_WIDTH },
11901  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
11902  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_WIDTH },
11903  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
11904  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_WIDTH },
11905  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
11906  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_WIDTH },
11907 };
11908 
11914 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
11915 {
11916  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
11917  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
11918  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
11919  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
11920  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
11921  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
11922  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
11923  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
11924  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
11925  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
11926  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
11927  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
11928  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
11929  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
11930  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
11931  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
11932  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
11933  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
11934  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
11935  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
11936  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
11937  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
11938  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
11939  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
11940  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
11941  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
11942  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
11943  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
11944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
11945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
11946  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
11947  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
11948  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
11949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
11950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
11951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
11952  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
11953  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
11954  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
11955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
11956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
11957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
11958  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
11959  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
11960  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
11961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
11962  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
11963  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
11964  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
11965  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
11966  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
11967  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
11968  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
11969  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
11970  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
11971  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
11972  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
11973  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
11974  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
11975  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
11976  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
11977  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
11978  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
11979  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
11980  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
11981  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
11982  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
11983  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
11984  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
11985  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
11986  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
11987  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
11988  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
11989  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
11990  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
11991  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
11992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
11993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
11994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
11995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
11996 };
11997 
12003 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12004 {
12005  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12006  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
12007  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12008  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
12009  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12010  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
12011  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12012  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
12013  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12014  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
12015  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12016  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
12017  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12018  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
12019  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12020  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
12021  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12022  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
12023  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12024  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
12025  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12026  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
12027  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12028  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
12029  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12030  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
12031  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12032  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
12033  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12034  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
12035  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12036  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
12037  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12038  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
12039  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12040  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
12041  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12042  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
12043  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12044  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
12045  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12046  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
12047  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12048  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
12049  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12050  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
12051  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12052  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
12053  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12054  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
12055  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12056  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
12057  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12058  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
12059  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12060  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
12061  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12062  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
12063  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12064  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
12065  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12066  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
12067  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12068  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
12069  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12070  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
12071  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12072  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
12073  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12074  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
12075  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12076  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
12077  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12078  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
12079  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12080  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
12081  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12082  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
12083  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12084  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
12085 };
12086 
12092 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12093 {
12094  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12095  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
12096  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12097  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
12098  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12099  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
12100  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12101  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
12102  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12103  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
12104  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12105  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
12106  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12107  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
12108  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12109  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
12110  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12111  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
12112  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12113  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
12114  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12115  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
12116  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12117  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
12118  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12119  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
12120  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12121  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
12122  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12123  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
12124  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12125  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
12126  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12127  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
12128  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12129  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
12130  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12131  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
12132  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12133  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
12134  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12135  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
12136  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12137  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
12138  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12139  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
12140  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12141  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
12142  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12143  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
12144  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12145  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
12146  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12147  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
12148  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12149  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
12150  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12151  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
12152  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12153  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
12154  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12155  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
12156  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12157  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
12158  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12159  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
12160  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12161  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
12162  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
12164  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12165  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
12166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
12168  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12169  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
12170  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12171  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
12172  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
12174 };
12175 
12181 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12182 {
12183  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12184  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
12185  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12186  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
12187  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12188  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
12189  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12190  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
12191  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12192  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
12193  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12194  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
12195  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12196  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
12197  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12198  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
12199  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12200  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
12201  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12202  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
12203  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12204  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
12205  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12206  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
12207  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12208  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
12209  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12210  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
12211  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12212  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
12213  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12214  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
12215  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12216  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
12217  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12218  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
12219  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12220  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
12221  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12222  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
12223  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12224  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
12225  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12226  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
12227  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12228  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
12229  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12230  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
12231  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12232  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
12233  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12234  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
12235  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12236  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
12237  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12238  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
12239  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12240  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
12241  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12242  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
12243  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12244  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
12245  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12246  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
12247  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12248  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
12249  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12250  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
12251  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12252  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
12253  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12254  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
12255  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12256  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
12257  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12258  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
12259  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12260  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
12261  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12262  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
12263 };
12264 
12270 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12271 {
12272  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12273  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
12274  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12275  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
12276  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12277  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
12278  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12279  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
12280  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12281  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
12282  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12283  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
12284  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12285  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
12286  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12287  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
12288  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12289  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
12290  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12291  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
12292  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12293  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
12294  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12295  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
12296  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12297  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
12298  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12299  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
12300  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12301  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
12302  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12303  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
12304  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12305  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
12306  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12307  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
12308  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12309  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
12310  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12311  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
12312  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12313  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
12314  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12315  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
12316  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12317  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
12318  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12319  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
12320  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12321  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
12322  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12323  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
12324  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12325  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
12326  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12327  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
12328  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12329  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
12330  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12331  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
12332  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12333  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
12334  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12335  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
12336  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12337  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
12338  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12339  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
12340  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12341  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
12342  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12343  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
12344  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12345  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
12346  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12347  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
12348  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12349  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
12350  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12351  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
12352 };
12353 
12359 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12360 {
12361  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
12363  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
12365  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12366  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
12367  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
12369  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12370  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
12371  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12372  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
12373  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12374  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
12375  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12376  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
12377  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12378  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
12379  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12380  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
12381  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12382  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
12383  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12384  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
12385  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12386  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
12387  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12388  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
12389  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12390  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
12391  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12392  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
12393  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12394  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
12395  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12396  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
12397  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12398  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
12399  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12400  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
12401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
12403  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12404  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
12405  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12406  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
12407  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12408  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
12409  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12410  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
12411  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12412  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
12413  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12414  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
12415  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12416  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
12417  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12418  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
12419  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12420  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
12421  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12422  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
12423  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12424  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
12425  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12426  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
12427  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12428  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
12429  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12430  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
12431 };
12432 
12438 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12439 {
12440  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12441  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
12442  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12443  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
12444  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12445  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
12446  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12447  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
12448  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12449  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
12450  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12451  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
12452  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12453  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
12454  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12455  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
12456  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12457  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
12458  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12459  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
12460  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12461  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
12462  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12463  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
12464  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12465  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
12466  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12467  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
12468  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12469  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
12470  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12471  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
12472  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12473  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
12474  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12475  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
12476  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12477  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
12478  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12479  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
12480  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12481  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
12482  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12483  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
12484  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12485  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
12486  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12487  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
12488  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12489  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
12490  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12491  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
12492  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12493  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
12494  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12495  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
12496  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12497  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
12498  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12499  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
12500  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12501  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
12502  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12503  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
12504  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12505  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
12506  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12507  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
12508  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12509  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
12510 };
12511 
12517 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12518 {
12519  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12520  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
12521  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12522  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
12523  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12524  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
12525  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12526  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
12527  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12528  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
12529  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12530  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
12531  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12532  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
12533  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12534  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
12535  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12536  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
12537  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12538  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
12539  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12540  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
12541  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12542  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
12543  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12544  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
12545  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12546  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
12547  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12548  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
12549  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12550  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
12551  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12552  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
12553  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12554  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
12555  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12556  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
12557  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12558  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
12559  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12560  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
12561  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12562  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
12563  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12564  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
12565  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12566  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
12567  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12568  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
12569  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12570  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
12571  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12572  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
12573  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12574  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
12575  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12576  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
12577  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12578  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
12579  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12580  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
12581  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12582  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
12583  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12584  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
12585  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12586  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
12587  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12588  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
12589 };
12590 
12596 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12597 {
12598  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12599  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
12600  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12601  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
12602  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12603  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
12604 };
12605 
12611 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
12612 {
12613  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12614  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
12615  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12616  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
12617  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12618  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
12619  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12620  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
12621  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12622  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
12623  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12624  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
12625  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12626  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
12627  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12628  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
12629  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12630  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
12631  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12632  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
12633  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12634  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
12635  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12636  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
12637  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12638  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
12639  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12640  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
12641  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12642  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
12643  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12644  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
12645  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12646  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
12647  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12648  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
12649  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12650  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
12651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
12653  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
12655  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12656  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
12657  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
12659  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12660  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
12661  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12662  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
12663  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12664  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
12665  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12666  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
12667  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12668  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
12669  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
12671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
12673  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
12675  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12676  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
12677  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
12679  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
12681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
12683  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
12685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
12687  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
12689  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
12690  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
12691  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
12692  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
12693  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
12694  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
12695  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
12696  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
12697  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
12698  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
12699  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
12700  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
12701  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
12702  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
12703  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
12704  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
12705  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
12706  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
12707  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
12708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
12709  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
12710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
12711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
12712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
12713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
12714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
12715  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
12716  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
12717  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
12718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
12719  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
12720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
12721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
12722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
12723  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
12724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
12725  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
12726  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
12727  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
12728  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
12729  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
12730  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
12731  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
12732  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
12733  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
12734  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
12735  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
12736  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
12737  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
12738  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
12739  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
12740  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
12741  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
12742  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
12743  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
12744  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
12745  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
12746  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
12747  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
12748  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
12749  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
12750  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
12751  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
12752  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
12753  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
12754  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
12755  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
12756  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
12757  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
12758  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
12759  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
12760  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
12761  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
12762  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
12763  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
12764  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
12765  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
12766  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
12767  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
12768  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
12769  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
12770  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
12771  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
12772  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
12773  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
12774  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
12775  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
12776  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
12777  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
12778  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
12779  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
12780  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
12781  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
12782  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
12783  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
12784  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
12785  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
12786  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
12787  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
12788  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
12789  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
12790  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
12791  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
12792  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
12793  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
12794  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
12795  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
12796  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
12797  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
12798  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
12799  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
12800  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
12801  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
12802  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
12803  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
12804  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
12805  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
12806  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
12807  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
12808  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
12809  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
12810  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
12811  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
12812  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
12813  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
12814  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
12815  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
12816  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
12817  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
12818  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
12819  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
12820  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
12821  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
12822  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
12823  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
12824  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
12825  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
12826  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
12827  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
12828  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
12829  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
12830  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
12831  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
12832  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
12833  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
12834  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
12835  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
12836  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
12837  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
12838  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
12839  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
12840  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
12841  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
12842  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
12843  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
12844  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
12845  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
12846  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
12847  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
12848  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
12849  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
12850  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
12851  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
12852  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
12853  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
12854  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
12855  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
12856  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
12857  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
12858  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
12859  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
12860  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
12861  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
12862  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
12863  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
12864  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
12865  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
12866  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
12867  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
12868  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
12869  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
12870  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
12871  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
12872  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
12873  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
12874  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
12875  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
12876  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
12877  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
12878  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
12879  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
12880  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
12881  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
12882  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
12883  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
12884  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
12885  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
12886  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
12887  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
12888  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
12889  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
12890  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
12891  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
12892  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
12893  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
12894  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
12895  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
12896  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
12897  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
12898  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
12899  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
12900  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
12901  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
12902  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
12903  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
12904  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
12905  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
12906  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
12907  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
12908  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
12909  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
12910  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
12911  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
12912  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
12913  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
12914  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
12915  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
12916  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
12917  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
12918  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
12919  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
12920  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
12921  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
12922  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
12923  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
12924  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
12925  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
12926  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
12927  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
12928  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
12929  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
12930  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
12931  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
12932  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
12933  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
12934  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
12935  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
12936  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
12937  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
12938  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
12939  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
12940  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
12941  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
12942  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
12943  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
12944  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
12945  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
12946  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
12947  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
12948  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
12949  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
12950  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
12951  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
12952  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
12953  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
12954  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
12955  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
12956  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
12957  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
12958  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
12959  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
12960  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
12961  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
12962  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
12963  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
12964  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
12965  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
12966  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
12967  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
12968  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
12969  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
12970  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
12971  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
12972  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
12973  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
12974  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
12975  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
12976  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
12977  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
12978  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
12979  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
12980  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
12981  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
12982  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
12983  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
12984  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
12985  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
12986  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
12987  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
12988  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
12989  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
12990  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
12991  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
12992  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
12993  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
12994  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
12995  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
12996  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
12997  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
12998  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
12999  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
13000  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
13001  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
13002  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
13003  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
13004  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
13005  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
13006  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
13007  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
13008  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
13009 };
13010 
13016 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13017 {
13018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
13020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
13022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
13024  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13025  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
13026  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13027  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
13028  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13029  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
13030  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13031  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
13032  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13033  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
13034  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13035  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
13036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
13038  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
13040  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13041  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
13042  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13043  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
13044  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13045  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
13046  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13047  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
13048  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13049  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
13050  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13051  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
13052  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13053  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
13054  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13055  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
13056  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13057  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
13058  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13059  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
13060  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13061  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
13062  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13063  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
13064  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13065  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
13066  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13067  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
13068  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13069  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
13070  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13071  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
13072  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13073  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
13074  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13075  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
13076  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13077  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
13078  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13079  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
13080  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13081  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
13082  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13083  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
13084  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13085  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
13086  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13087  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
13088  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13089  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
13090  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13091  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
13092  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13093  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
13094  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
13095  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
13096  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
13097  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
13098  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
13099  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
13100  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
13101  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
13102  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
13103  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
13104  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
13105  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
13106  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
13107  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
13108  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
13109  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
13110  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
13111  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
13112  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
13113  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
13114  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
13115  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
13116  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
13117  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
13118  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
13119  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
13120  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
13121  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
13122  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
13123  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
13124  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
13125  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
13126  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
13127  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
13128  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
13129  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
13130  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
13131  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
13132  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
13133  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
13134  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
13135  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
13136  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
13137  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
13138  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
13139  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
13140  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
13141  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
13142  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
13143  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
13144  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
13145  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
13146  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
13147  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
13148  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
13149  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
13150  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
13151  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
13152  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
13153  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
13154  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
13155  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
13156  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
13157  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
13158  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
13159  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
13160  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
13161  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
13162  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
13163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
13164  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
13165  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
13166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
13167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
13168  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
13169  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
13170  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
13171  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
13172  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
13173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
13174  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
13175  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
13176  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
13177  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
13178  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
13179  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
13180  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
13181  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
13182  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
13183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
13184  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
13185  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
13186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
13187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
13188  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
13189  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
13190  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
13191  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
13192  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
13193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
13194  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
13195  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
13196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
13197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
13198  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
13199  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
13200  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
13201  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
13202  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
13203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
13204  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
13205  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
13206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
13207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
13208  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
13209  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
13210  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
13211  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
13212  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
13213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
13214  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
13215  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
13216  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
13217  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
13218  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
13219  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
13220  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
13221  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
13222  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
13223  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
13224  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
13225  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
13226  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
13227  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
13228  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
13229  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
13230  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
13231  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
13232  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
13233  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
13234  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
13235  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
13236  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
13237  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
13238  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
13239  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
13240  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
13241  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
13242  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
13243  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
13244  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
13245  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
13246  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
13247  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
13248  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
13249  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
13250  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
13251  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
13252  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
13253  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
13254  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
13255  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
13256  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
13257  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
13258  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
13259  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
13260  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
13261  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
13262  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
13263  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
13264  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
13265  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
13266  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
13267  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
13268  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
13269  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
13270  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
13271  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
13272  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
13273  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
13274  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
13275  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
13276  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
13277  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
13278  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
13279  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
13280  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
13281  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
13282  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
13283  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
13284  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
13285  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
13286  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
13287  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
13288  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
13289  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
13290  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
13291  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
13292  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
13293  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
13294  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
13295  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
13296  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
13297  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
13298  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
13299  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
13300  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
13301  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
13302  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
13303  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
13304  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
13305  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
13306  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
13307  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
13308  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
13309  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
13310  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
13311  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
13312  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
13313  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
13314  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
13315  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
13316  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
13317  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
13318  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
13319  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
13320  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
13321  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
13322  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
13323  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
13324  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
13325  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
13326  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
13327  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
13328  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
13329  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
13330  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
13331  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
13332  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
13333  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
13334  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
13335  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
13336  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
13337  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
13338  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
13339  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
13340  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
13341  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
13342  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
13343  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
13344  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
13345  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
13346  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
13347  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
13348  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
13349  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
13350  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
13351  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
13352  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
13353  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
13354  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
13355  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
13356  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
13357  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
13358  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
13359  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
13360  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
13361  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
13362  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
13363  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
13364  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
13365  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
13366  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
13367  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
13368  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
13369  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
13370  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
13371  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
13372  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
13373  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
13374  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
13375  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
13376  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
13377  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
13378  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
13379  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
13380  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
13381  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
13382  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
13383  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
13384  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
13385  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
13386  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
13387  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
13388  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
13389  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
13390  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
13391  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
13392 };
13393 
13399 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13400 {
13401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
13403 };
13404 
13410 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13411 {
13412  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13413  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
13414  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13415  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
13416  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13417  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
13418  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13419  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
13420  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13421  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
13422  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13423  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
13424  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13425  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
13426  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13427  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
13428  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13429  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
13430  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13431  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
13432  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13433  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
13434  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13435  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
13436  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13437  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
13438  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13439  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
13440  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13441  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
13442  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13443  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
13444  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13445  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
13446  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13447  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
13448  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13449  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
13450  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13451  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
13452  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13453  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
13454  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13455  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
13456  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13457  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
13458  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13459  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
13460  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13461  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
13462  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13463  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
13464  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13465  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
13466  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13467  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
13468  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13469  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
13470  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13471  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
13472  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13473  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
13474  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13475  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
13476  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13477  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
13478  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13479  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
13480  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13481  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
13482  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13483  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
13484  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13485  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
13486  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13487  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
13488  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
13489  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
13490  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
13491  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
13492  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
13493  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
13494  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
13495  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
13496  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
13497  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
13498  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
13499  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
13500  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
13501  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
13502  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
13503  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
13504  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
13505  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
13506  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
13507  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
13508  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
13509  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
13510  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
13511  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
13512  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
13513  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
13514  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
13515  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
13516  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
13517  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
13518  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
13519  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
13520  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
13521  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
13522  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
13523  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
13524  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
13525  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
13526  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
13527  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
13528  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
13529  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
13530  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
13531  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
13532  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
13533  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
13534  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
13535  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
13536  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
13537  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
13538  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
13539  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
13540  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
13541  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
13542  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
13543  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
13544  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
13545  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
13546  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
13547  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
13548  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
13549  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
13550  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
13551  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
13552  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
13553  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
13554  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
13555  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
13556  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
13557  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
13558  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
13559  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
13560  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
13561  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
13562  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
13563  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
13564  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
13565  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
13566  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
13567  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
13568  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
13569  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
13570  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
13571  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
13572  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
13573  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
13574  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
13575  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
13576  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
13577  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
13578  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
13579  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
13580  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
13581  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
13582  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
13583  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
13584  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
13585  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
13586  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
13587  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
13588  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
13589  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
13590  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
13591  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
13592  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
13593  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
13594  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
13595  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
13596  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
13597  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
13598  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
13599  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
13600  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
13601  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
13602  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
13603  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
13604  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
13605  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
13606  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
13607  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
13608  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
13609  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
13610  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
13611  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
13612  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
13613  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
13614  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
13615  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
13616  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
13617  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
13618  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
13619  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
13620  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
13621  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
13622  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
13623  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
13624  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
13625  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
13626  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
13627  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
13628  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
13629  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
13630  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
13631  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
13632  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
13633  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
13634  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
13635  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
13636  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
13637  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
13638  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
13639  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
13640  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
13641  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
13642  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
13643  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
13644  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
13645  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
13646  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
13647  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
13648  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
13649  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
13650  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
13651  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
13652  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
13653  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
13654  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
13655  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
13656  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
13657  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
13658  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
13659  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
13660  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
13661  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
13662  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
13663  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
13664  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
13665  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
13666  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
13667  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
13668  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
13669  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
13670  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
13671  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
13672  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
13673  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
13674  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
13675  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
13676  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
13677  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
13678  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
13679  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
13680  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
13681  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
13682  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
13683  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
13684  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
13685  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
13686  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
13687  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
13688  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
13689  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
13690  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
13691  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
13692  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
13693  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
13694  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
13695  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
13696  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
13697  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
13698  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
13699  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
13700  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
13701  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
13702 };
13703 
13709 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13710 {
13711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
13713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
13715  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13716  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
13717  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
13719  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
13721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
13723  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
13725  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13726  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
13727  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13728  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
13729  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13730  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
13731  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13732  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
13733  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13734  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
13735  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13736  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
13737  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13738  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
13739  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13740  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
13741  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13742  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
13743  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13744  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
13745  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13746  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
13747  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13748  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
13749  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13750  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
13751  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13752  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
13753  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13754  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
13755  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13756  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
13757  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13758  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
13759  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13760  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
13761  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13762  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
13763  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13764  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
13765  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13766  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
13767  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13768  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
13769  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13770  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
13771  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13772  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
13773  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13774  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
13775  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13776  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
13777  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13778  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
13779  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13780  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
13781  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13782  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
13783  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13784  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
13785  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13786  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
13787  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
13788  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
13789  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
13790  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
13791  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
13792  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
13793 };
13794 
13800 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13801 {
13802  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
13804  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
13806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
13808  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13809  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
13810  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
13812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
13814  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13815  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
13816  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
13818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
13820  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13821  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
13822  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
13824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
13826  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13827  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
13828  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
13830  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13831  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
13832  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13833  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
13834  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13835  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
13836  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13837  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
13838  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13839  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
13840  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13841  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
13842  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13843  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
13844  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13845  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
13846  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13847  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
13848  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13849  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
13850  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13851  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
13852  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13853  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
13854  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13855  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
13856  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13857  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
13858  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13859  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
13860  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13861  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
13862  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13863  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
13864  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13865  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
13866  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13867  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
13868  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13869  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
13870  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13871  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
13872  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13873  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
13874  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13875  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
13876  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13877  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
13878  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
13879  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
13880  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
13881  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
13882  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
13883  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
13884 };
13885 
13891 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13892 {
13893  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13894  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
13895  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13896  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
13897  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13898  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
13899  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13900  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
13901  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13902  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
13903  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13904  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
13905  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13906  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
13907  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13908  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
13909  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13910  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
13911  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13912  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
13913  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13914  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
13915  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13916  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
13917  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13918  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
13919  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13920  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
13921  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13922  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
13923  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13924  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
13925  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13926  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
13927  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13928  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
13929  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13930  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
13931  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13932  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
13933  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13934  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
13935  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13936  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
13937  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13938  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
13939  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13940  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
13941  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13942  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
13943  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13944  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
13945  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13946  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
13947  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13948  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
13949  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13950  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
13951  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13952  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
13953  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13954  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
13955  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13956  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
13957  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13958  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
13959  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13960  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
13961  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13962  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
13963  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13964  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
13965  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13966  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
13967  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13968  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
13969  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
13970  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
13971  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
13972  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
13973  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
13974  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
13975 };
13976 
13982 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
13983 {
13984  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13985  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
13986  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13987  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
13988  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13989  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
13990  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13991  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
13992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
13994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
13996  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13997  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
13998  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13999  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14000  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14001  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14002  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14003  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14004  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14005  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14006  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14007  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14008  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14009  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14010  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14011  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14012  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14013  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14014  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14015  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14016  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14017  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14024  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14025  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14026  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14027  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14028  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14029  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14030  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14031  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14032  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14033  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14034  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14035  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14038  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14040  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14041  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14042  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14043  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14044  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14045  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14046  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14047  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14048  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14049  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14050  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14051  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14052  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14053  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14054  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14055  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14056  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14057  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14058  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14059  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14060  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14061  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14062  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14063  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14064  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14065  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14066 };
14067 
14073 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14074 {
14075  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14076  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14077  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14078  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14079  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14080  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14081  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14082  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14083  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14084  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14085  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14086  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14087  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14088  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14089  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14090  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14091  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14092  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14093  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14094  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14095  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14096  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14097  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14098  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14099  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14100  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14101  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14102  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14103  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14104  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14105  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14106  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14107  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14108  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14109  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14110  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14111  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14112  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14113  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14114  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14115  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14116  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14117  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14118  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14119  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14120  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14121  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14122  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14123  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14124  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14125  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14126  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14127  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14128  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14129  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14130  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14131  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14132  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14133  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14134  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14135  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14136  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14137  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14138  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14139  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14140  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14141  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14142  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14143  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14144  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14145  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14146  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14147  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14148  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14149  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14150  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14151  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14152  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14153  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14154  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14155  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14156  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14157 };
14158 
14164 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14165 {
14166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14168  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14169  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14170  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14171  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14172  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14174  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14175  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14176  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14177  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14178  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14179  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14180  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14181  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14182  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14184  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14185  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14188  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14189  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14190  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14191  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14192  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14194  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14195  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14198  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14199  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14200  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14201  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14202  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14204  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14205  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14208  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14209  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14210  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14211  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14212  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14214  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14215  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14216  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14217  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14218  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14219  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14220  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14221  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14222  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14223  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14224  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14225  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14226  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14227  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14228  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14229  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14230  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14231  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14232  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14233  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14234  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14235  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14236  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14237  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14238  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14239  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14240  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14241  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14242  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14243  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14244  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14245  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14246  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14247  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14248 };
14249 
14255 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14256 {
14257  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14258  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14259  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14260  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14261  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14262  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14263  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14264  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14265  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14266  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14267  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14268  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14269  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14270  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14271  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14272  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14273  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14274  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14275  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14276  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14277  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14278  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14279  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14280  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14281  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14282  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14283  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14284  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14285  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14286  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14287  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14288  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14289  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14290  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14291  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14292  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14293  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14294  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14295  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14296  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14297  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14298  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14299  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14300  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14301  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14302  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14303  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14304  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14305  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14306  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14307  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14308  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14309  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14310  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14311  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14312  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14313  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14314  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14315  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14316  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14317  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14318  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14319  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14320  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14321  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14322  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14323  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14324  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14325  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14326  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14327  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14328  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14329  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14330  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14331  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14332  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14333  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14334  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14335  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14336  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14337  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14338  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14339 };
14340 
14346 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14347 {
14348  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14349  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
14350  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14351  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
14352  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14353  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
14354 };
14355 
14361 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14362 {
14363  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14365  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14366  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14367  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14369  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14370  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14371  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14372  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14373  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14374  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14375  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14376  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14377  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14378  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14379  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14380  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14381  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14382  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14383  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14384  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14385  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14386  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14387  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14388  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14389  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14390  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14391  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14392  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14393  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14394  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14395  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14396  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14397  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14398  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14399  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14400  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14403  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14404  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14405  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14406  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14407  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14408  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14409  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14410  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14411  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14412  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14413  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14414  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14415  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14416  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14417  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14418  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14419  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14420  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14421  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14422  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14423  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14424  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14425  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14426  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14427  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14428  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14429  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14430  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14431  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14432  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14433  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14434  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14435  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14436  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14437  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14438  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14439  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14440  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14441  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14442  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14443  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14444  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14445 };
14446 
14452 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14453 {
14454  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14455  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14456  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14457  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14458  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14459  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14460  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14461  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14462  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14463  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14464  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14465  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14466  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14467  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14468  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14469  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14470  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14471  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14472  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14473  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14474  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14475  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14476  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14477  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14478  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14479  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14480  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14481  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14482  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14483  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14484  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14485  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14486  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14487  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14488  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14489  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14490  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14491  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14492  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14493  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14494  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14495  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14496  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14497  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14498  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14499  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14500  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14501  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14502  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14503  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14504  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14505  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14506  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14507  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14508  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14509  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14510  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14511  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14512  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14513  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14514  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14515  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14516  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14517  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14518  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14519  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14520  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14521  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14522  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14523  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14524  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14525  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14526  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14527  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14528  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14529  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14530  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14531  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14532  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14533  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14534  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14535  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14536 };
14537 
14543 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14544 {
14545  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14546  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14547  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14548  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14549  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14550  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14551  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14552  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14553  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14554  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14555  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14556  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14557  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14558  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14559  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14560  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14561  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14562  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14563  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14564  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14565  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14566  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14567  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14568  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14569  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14570  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14571  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14572  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14573  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14574  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14575  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14576  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14577  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14578  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14579  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14580  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14581  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14582  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14583  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14584  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14585  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14586  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14587  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14588  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14589  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14590  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14591  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14592  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14593  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14594  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14595  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14596  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14597  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14598  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14599  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14600  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14601  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14602  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14603  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14604  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14605  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14606  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14607  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14608  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14609  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14610  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14611  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14612  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14613  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14614  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14615  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14616  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14617  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14618  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14619  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14620  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14621  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14622  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14623  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14624  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14625  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14626  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14627 };
14628 
14634 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14635 {
14636  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14637  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
14638  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14639  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
14640  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14641  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
14642  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14643  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
14644  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14645  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
14646  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14647  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
14648  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14649  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
14650  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14651  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
14652  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14653  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
14654  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14655  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
14656  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14657  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
14658  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14659  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
14660 };
14661 
14667 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14668 {
14669  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14673  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14675  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14676  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14677  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14679  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14683  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14687  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14689  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14690  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14691  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14692  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14693  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14694  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14695  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14696  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14697  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14698  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14699  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14700  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14701  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14702  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14703  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14704  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14705  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14706  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14707  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14709  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14715  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14716  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14717  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14719  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14723  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14725  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14726  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14727  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14728  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14729  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14730  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14731  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14732  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14733  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14734  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14735  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14736  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14737  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14738  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14739  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14740  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14741  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14742  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14743  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14744  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14745  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14746  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14747  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14748  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14749  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14750  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14751 };
14752 
14758 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14759 {
14760  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14761  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14762  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14763  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14764  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14765  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14766  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14767  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14768  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14769  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14770  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14771  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14772  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14773  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14774  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14775  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14776  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14777  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14778  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14779  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14780  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14781  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14782  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14783  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14784  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14785  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14786  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14787  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14788  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14789  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14790  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14791  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14792  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14793  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14794  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14795  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14796  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14797  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14798  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14799  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14800  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14801  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14802  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14804  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14808  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14809  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14810  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14814  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14815  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14816  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14820  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14821  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14822  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14826  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14827  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14828  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14830  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14831  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14832  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14833  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14834  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14835  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14836  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14837  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14838  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14839  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14840  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14841  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14842 };
14843 
14849 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14850 {
14851  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14852  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14853  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14854  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14855  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14856  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14857  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14858  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14859  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14860  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14861  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14862  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14863  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14864  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14865  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14866  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14867  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14868  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14869  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14870  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14871  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14872  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14873  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14874  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14875  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14876  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14877  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14878  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14879  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14880  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14881  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14882  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14883  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14884  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14885  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14886  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14887  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14888  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14889  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14890  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14891  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14892  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14893  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14894  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14895  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14896  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14897  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14898  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14899  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14900  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14901  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14902  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14903  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14904  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14905  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14906  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14907  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14908  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
14909  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14910  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
14911  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14912  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
14913  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14914  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
14915  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14916  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
14917  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14918  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
14919  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14920  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
14921  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14922  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
14923  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14924  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
14925  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14926  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
14927  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
14928  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
14929  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
14930  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
14931  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
14932  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
14933 };
14934 
14940 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
14941 {
14942  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14943  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
14944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
14946  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14947  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
14948  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
14950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
14952  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14953  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
14954  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
14956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
14958  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14959  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
14960  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
14962  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14963  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
14964  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14965  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
14966  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14967  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
14968  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14969  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
14970  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14971  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
14972  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14973  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
14974  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14975  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
14976  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14977  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
14978  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14979  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
14980  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14981  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
14982  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14983  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
14984  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14985  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
14986  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14987  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
14988  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14989  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
14990  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14991  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
14992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
14994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
14996  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14997  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
14998  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14999  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
15000  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
15001  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
15002  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
15003  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
15004  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
15005  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
15006  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
15007  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
15008  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
15009  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
15010  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
15011  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
15012  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
15013  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
15014  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
15015  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
15016  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
15017  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
15018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
15019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
15020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
15021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
15022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
15023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
15024 };
15025 
15031 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15032 {
15033  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15034  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
15035  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15036  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
15037  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15038  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
15039 };
15040 
15046 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15047 {
15048  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15049  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
15050  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15051  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
15052  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15053  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
15054  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
15055  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
15056  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
15057  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
15058  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
15059  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
15060  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
15061  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
15062 };
15063 
15069 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15070 {
15071  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15072  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
15073  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15074  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
15075  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15076  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
15077 };
15078 
15084 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15085 {
15086  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15087  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
15088  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15089  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
15090  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15091  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
15092  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
15093  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
15094  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
15095  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
15096  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
15097  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
15098  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
15099  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
15100 };
15101 
15107 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15108 {
15109  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15110  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
15111  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15112  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
15113  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15114  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
15115 };
15116 
15122 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15123 {
15124  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15125  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
15126  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15127  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
15128  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15129  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
15130 };
15131 
15137 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15138 {
15139  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15140  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
15141  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15142  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
15143  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15144  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
15145  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
15146  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
15147  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
15148  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
15149  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
15150  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
15151  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
15152  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
15153 };
15154 
15160 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15161 {
15162  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
15164  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15165  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
15166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
15168 };
15169 
15175 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
15176 {
15177  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
15178  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
15179  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
15180  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
15181  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
15182  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
15183  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
15184  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
15185  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
15186  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
15187  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
15188  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
15189  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
15190  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
15191  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
15192  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
15193  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
15194  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
15195  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
15196  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
15197  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
15198  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
15199  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
15200  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
15201  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
15202  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
15203  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
15204  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
15205  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
15206  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
15207  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
15208  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
15209  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
15210  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
15211  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
15212  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
15213  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
15214  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
15215  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
15216  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
15217  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
15218  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
15219  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
15220  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
15221  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
15222  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
15223  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
15224  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
15225  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
15226  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
15227  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
15228  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
15229  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
15230  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
15231  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
15232  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
15233  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
15234  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
15235  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
15236  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
15237  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
15238  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
15239  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
15240  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
15241  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
15242  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
15243  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
15244  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
15245  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
15246  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
15247  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
15248  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
15249  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
15250  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
15251  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
15252  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
15253  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
15254  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
15255  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
15256  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
15257  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
15258  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
15259  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
15260  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
15261  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
15262  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
15263  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
15264  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
15265  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
15266  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
15267  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
15268  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
15269  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
15270  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
15271  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
15272  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
15273  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
15274  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
15275  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
15276  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
15277  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
15278  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
15279  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
15280  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
15281  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
15282  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
15283  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
15284  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
15285  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
15286  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
15287  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
15288  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
15289  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
15290  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
15291  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
15292  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
15293  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
15294  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
15295  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
15296  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
15297  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
15298  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
15299  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
15300  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
15301  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
15302  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
15303  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
15304  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
15305  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
15306  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
15307  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
15308  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
15309  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
15310  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
15311  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
15312  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
15313  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
15314  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
15315  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
15316  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
15317  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
15318  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
15319  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
15320  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
15321  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
15322  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
15323  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
15324  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
15325  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
15326  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
15327  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
15328  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
15329  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
15330  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
15331  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
15332  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
15333  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
15334  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
15335  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
15336  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
15337  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
15338  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
15339  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
15340  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
15341  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
15342  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
15343  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
15344  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
15345  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
15346  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
15347  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
15348  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
15349  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
15350  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
15351  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
15352  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
15353  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
15354  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
15355  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
15356  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
15357  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
15358  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
15359  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
15360  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
15361  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
15362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
15363  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
15364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
15365  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
15366  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
15367  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
15368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
15369  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
15370  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
15371  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
15372  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
15373  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
15374  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
15375  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
15376  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
15377  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
15378  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
15379  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
15380  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
15381  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
15382  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
15383  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
15384  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
15385  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
15386  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
15387  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
15388  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
15389  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
15390  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
15391  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
15392  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
15393  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
15394  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
15395  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
15396  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
15397  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
15398  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
15399  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
15400  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
15401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
15402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
15403  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
15404  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
15405  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
15406  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
15407  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
15408  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
15409  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
15410  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
15411  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
15412  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
15413  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
15414  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
15415  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
15416  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
15417  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
15418  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
15419  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
15420  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
15421  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
15422  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
15423  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
15424  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
15425  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
15426  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
15427  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
15428  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
15429  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
15430  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
15431  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
15432  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
15433  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
15434  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
15435  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
15436  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
15437  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
15438  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
15439  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
15440  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
15441  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
15442  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
15443  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
15444  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
15445  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
15446  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
15447  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
15448  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
15449  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
15450  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
15451  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
15452  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
15453  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
15454  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
15455  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
15456  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
15457  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
15458  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
15459  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
15460  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
15461  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
15462  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
15463  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
15464  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
15465  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
15466  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
15467  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
15468  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
15469  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
15470  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
15471  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
15472  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
15473  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
15474  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
15475  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
15476  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
15477  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
15478  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
15479  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
15480  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
15481  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
15482  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
15483  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
15484  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
15485  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
15486  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
15487  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
15488  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
15489  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
15490  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
15491  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
15492  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
15493  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
15494  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
15495  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
15496  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
15497  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
15498  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
15499  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
15500  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
15501  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
15502  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
15503  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
15504  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
15505  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
15506  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
15507  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
15508  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
15509  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
15510  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
15511  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
15512  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
15513  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
15514  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
15515  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
15516  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
15517  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
15518  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
15519  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
15520  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
15521  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
15522  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
15523  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
15524  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
15525  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
15526  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
15527  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
15528  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
15529  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
15530  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
15531  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
15532  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
15533  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
15534  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
15535  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
15536  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
15537  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
15538  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
15539  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
15540  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
15541  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
15542  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
15543  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
15544  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
15545  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
15546  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
15547  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
15548  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
15549  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
15550  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
15551  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
15552  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
15553  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
15554  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
15555  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
15556  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
15557  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
15558  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
15559  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
15560  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
15561  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
15562  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
15563  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
15564  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
15565  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
15566  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
15567  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
15568  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
15569  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
15570  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
15571  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
15572  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
15573  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
15574  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
15575  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
15576  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
15577  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
15578  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
15579  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
15580  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
15581  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
15582  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
15583  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
15584  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
15585  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
15586  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
15587  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
15588  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
15589  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
15590  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
15591  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
15592  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
15593  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
15594  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
15595  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
15596  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
15597  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
15598  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
15599  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
15600  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
15601  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
15602  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
15603  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
15604  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
15605  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
15606  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
15607  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
15608  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
15609  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
15610  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
15611  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
15612  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
15613  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
15614  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
15615  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
15616  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
15617  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
15618  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
15619  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
15620  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
15621  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
15622  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
15623  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
15624  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
15625  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
15626  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
15627  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
15628  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
15629  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
15630  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
15631  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
15632  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
15633  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
15634  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
15635  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
15636  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_229_WIDTH },
15637  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
15638  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_230_WIDTH },
15639  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
15640  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_231_WIDTH },
15641  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
15642  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_232_WIDTH },
15643  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
15644  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_233_WIDTH },
15645  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
15646  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_234_WIDTH },
15647  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
15648  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_235_WIDTH },
15649  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
15650  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_236_WIDTH },
15651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
15652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_237_WIDTH },
15653  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
15654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_238_WIDTH },
15655  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
15656  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_239_WIDTH },
15657  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
15658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_240_WIDTH },
15659  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
15660  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_241_WIDTH },
15661  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
15662  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_242_WIDTH },
15663  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
15664  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_243_WIDTH },
15665  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
15666  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_244_WIDTH },
15667  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
15668  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_245_WIDTH },
15669  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
15670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_246_WIDTH },
15671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
15672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_247_WIDTH },
15673  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
15674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_248_WIDTH },
15675  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
15676  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_249_WIDTH },
15677  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
15678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_250_WIDTH },
15679  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
15680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_251_WIDTH },
15681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
15682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_252_WIDTH },
15683  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
15684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_253_WIDTH },
15685  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
15686  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_254_WIDTH },
15687  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
15688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_GROUP_255_WIDTH },
15689 };
15690 
15696 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS] =
15697 {
15698  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
15699  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_0_WIDTH },
15700  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
15701  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_1_WIDTH },
15702  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
15703  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_2_WIDTH },
15704  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
15705  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_3_WIDTH },
15706  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
15707  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_4_WIDTH },
15708  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
15709  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_5_WIDTH },
15710  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
15711  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_6_WIDTH },
15712  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
15713  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_7_WIDTH },
15714  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
15715  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_8_WIDTH },
15716  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
15717  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_9_WIDTH },
15718  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
15719  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_10_WIDTH },
15720  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
15721  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_11_WIDTH },
15722  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
15723  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_12_WIDTH },
15724  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
15725  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_13_WIDTH },
15726  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
15727  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_14_WIDTH },
15728  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
15729  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_15_WIDTH },
15730  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
15731  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_16_WIDTH },
15732  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
15733  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_17_WIDTH },
15734  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
15735  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_18_WIDTH },
15736  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
15737  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_19_WIDTH },
15738  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
15739  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_20_WIDTH },
15740  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
15741  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_21_WIDTH },
15742  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
15743  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_22_WIDTH },
15744  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
15745  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_23_WIDTH },
15746  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
15747  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_24_WIDTH },
15748  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
15749  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_25_WIDTH },
15750  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
15751  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_26_WIDTH },
15752  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
15753  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_27_WIDTH },
15754  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
15755  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_28_WIDTH },
15756  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
15757  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_29_WIDTH },
15758  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
15759  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_30_WIDTH },
15760  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
15761  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_31_WIDTH },
15762  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
15763  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_32_WIDTH },
15764  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
15765  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_33_WIDTH },
15766  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
15767  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_34_WIDTH },
15768  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
15769  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_35_WIDTH },
15770  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
15771  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_36_WIDTH },
15772  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
15773  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_37_WIDTH },
15774  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
15775  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_38_WIDTH },
15776  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
15777  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_39_WIDTH },
15778  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
15779  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_40_WIDTH },
15780  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
15781  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_41_WIDTH },
15782  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
15783  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_42_WIDTH },
15784  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
15785  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_43_WIDTH },
15786  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
15787  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_44_WIDTH },
15788  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
15789  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_45_WIDTH },
15790  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
15791  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_46_WIDTH },
15792  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
15793  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_47_WIDTH },
15794  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
15795  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_48_WIDTH },
15796  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
15797  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_49_WIDTH },
15798  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
15799  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_50_WIDTH },
15800  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
15801  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_51_WIDTH },
15802  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
15803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_52_WIDTH },
15804  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
15805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_53_WIDTH },
15806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
15807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_54_WIDTH },
15808  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
15809  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_55_WIDTH },
15810  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
15811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_56_WIDTH },
15812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
15813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_57_WIDTH },
15814  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
15815  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_58_WIDTH },
15816  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
15817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_59_WIDTH },
15818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
15819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_60_WIDTH },
15820  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
15821  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_61_WIDTH },
15822  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
15823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_62_WIDTH },
15824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
15825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_63_WIDTH },
15826  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
15827  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_64_WIDTH },
15828  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
15829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_65_WIDTH },
15830  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
15831  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_66_WIDTH },
15832  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
15833  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_67_WIDTH },
15834  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
15835  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_68_WIDTH },
15836  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
15837  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_69_WIDTH },
15838  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
15839  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_70_WIDTH },
15840  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
15841  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_71_WIDTH },
15842  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
15843  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_72_WIDTH },
15844  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
15845  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_73_WIDTH },
15846  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
15847  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_74_WIDTH },
15848  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
15849  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_75_WIDTH },
15850  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
15851  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_76_WIDTH },
15852  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
15853  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_77_WIDTH },
15854  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
15855  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_78_WIDTH },
15856  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
15857  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_79_WIDTH },
15858  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
15859  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_80_WIDTH },
15860  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
15861  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_81_WIDTH },
15862  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
15863  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_82_WIDTH },
15864  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
15865  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_83_WIDTH },
15866  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
15867  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_84_WIDTH },
15868  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
15869  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_85_WIDTH },
15870  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
15871  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_86_WIDTH },
15872  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
15873  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_87_WIDTH },
15874  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
15875  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_88_WIDTH },
15876  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
15877  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_89_WIDTH },
15878  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
15879  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_90_WIDTH },
15880  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
15881  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_91_WIDTH },
15882  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
15883  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_92_WIDTH },
15884  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
15885  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_93_WIDTH },
15886  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
15887  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_94_WIDTH },
15888  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
15889  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_95_WIDTH },
15890  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
15891  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_96_WIDTH },
15892  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
15893  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_97_WIDTH },
15894  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
15895  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_98_WIDTH },
15896  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
15897  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_99_WIDTH },
15898  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
15899  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_100_WIDTH },
15900  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
15901  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_101_WIDTH },
15902  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
15903  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_102_WIDTH },
15904  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
15905  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_103_WIDTH },
15906  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
15907  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_104_WIDTH },
15908  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
15909  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_105_WIDTH },
15910  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
15911  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_106_WIDTH },
15912  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
15913  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_107_WIDTH },
15914  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
15915  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_108_WIDTH },
15916  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
15917  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_109_WIDTH },
15918  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
15919  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_110_WIDTH },
15920  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
15921  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_111_WIDTH },
15922  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
15923  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_112_WIDTH },
15924  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
15925  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_113_WIDTH },
15926  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
15927  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_114_WIDTH },
15928  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
15929  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_115_WIDTH },
15930  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
15931  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_116_WIDTH },
15932  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
15933  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_117_WIDTH },
15934  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
15935  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_118_WIDTH },
15936  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
15937  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_119_WIDTH },
15938  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
15939  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_120_WIDTH },
15940  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
15941  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_121_WIDTH },
15942  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
15943  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_122_WIDTH },
15944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
15945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_123_WIDTH },
15946  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
15947  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_124_WIDTH },
15948  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
15949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_125_WIDTH },
15950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
15951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_126_WIDTH },
15952  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
15953  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_127_WIDTH },
15954  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
15955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_128_WIDTH },
15956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
15957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_129_WIDTH },
15958  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
15959  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_130_WIDTH },
15960  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
15961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_131_WIDTH },
15962  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
15963  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_132_WIDTH },
15964  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
15965  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_133_WIDTH },
15966  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
15967  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_134_WIDTH },
15968  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
15969  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_135_WIDTH },
15970  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
15971  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_136_WIDTH },
15972  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
15973  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_137_WIDTH },
15974  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
15975  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_138_WIDTH },
15976  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
15977  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_139_WIDTH },
15978  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
15979  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_140_WIDTH },
15980  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
15981  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_141_WIDTH },
15982  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
15983  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_142_WIDTH },
15984  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
15985  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_143_WIDTH },
15986  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
15987  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_144_WIDTH },
15988  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
15989  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_145_WIDTH },
15990  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
15991  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_146_WIDTH },
15992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
15993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_147_WIDTH },
15994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
15995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_148_WIDTH },
15996  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
15997  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_149_WIDTH },
15998  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
15999  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_150_WIDTH },
16000  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
16001  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_151_WIDTH },
16002  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
16003  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_152_WIDTH },
16004  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
16005  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_153_WIDTH },
16006  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
16007  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_154_WIDTH },
16008  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
16009  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_155_WIDTH },
16010  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
16011  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_156_WIDTH },
16012  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
16013  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_157_WIDTH },
16014  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
16015  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_158_WIDTH },
16016  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
16017  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_159_WIDTH },
16018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
16019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_160_WIDTH },
16020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
16021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_161_WIDTH },
16022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
16023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_162_WIDTH },
16024  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
16025  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_163_WIDTH },
16026  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_164_CHECKER_TYPE,
16027  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_164_WIDTH },
16028  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_165_CHECKER_TYPE,
16029  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_GROUP_165_WIDTH },
16030 };
16031 
16037 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16038 {
16039  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16040  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
16041  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16042  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
16043  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16044  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
16045  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16046  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
16047  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16048  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
16049  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16050  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
16051  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16052  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
16053  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16054  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
16055  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16056  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
16057  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16058  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
16059  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16060  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
16061  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16062  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
16063  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16064  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
16065  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16066  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
16067  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16068  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
16069  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
16070  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
16071  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
16072  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
16073  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
16074  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
16075  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
16076  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
16077  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
16078  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
16079  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
16080  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
16081  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
16082  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
16083  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
16084  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
16085  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
16086  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
16087  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
16088  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
16089  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
16090  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
16091  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
16092  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
16093  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
16094  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
16095  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
16096  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
16097  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
16098  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
16099  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
16100  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
16101  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
16102  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
16103  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
16104  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
16105  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
16106  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
16107  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
16108  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
16109  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
16110  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
16111  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
16112  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
16113  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
16114  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
16115  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
16116  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
16117  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
16118  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
16119  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
16120  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
16121  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
16122  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
16123  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
16124  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
16125  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
16126  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
16127  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
16128  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
16129  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
16130  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
16131  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
16132  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
16133  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
16134  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
16135  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
16136  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
16137  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
16138  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
16139  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
16140  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
16141  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
16142  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
16143  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
16144  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
16145  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
16146  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
16147  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
16148  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
16149  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
16150  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
16151  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
16152  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
16153  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
16154  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
16155  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
16156  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
16157  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
16158  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
16159  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
16160  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
16161  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
16162  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
16163  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
16164  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
16165  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
16166  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
16167  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
16168  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
16169  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
16170  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
16171  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
16172  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
16173  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
16174  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
16175  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
16176  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
16177  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
16178  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
16179  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
16180  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
16181  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
16182  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
16183  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
16184  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
16185  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
16186  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
16187  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
16188  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
16189  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
16190  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
16191  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
16192  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
16193  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
16194  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
16195  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
16196  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
16197  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
16198  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
16199  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
16200  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
16201  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
16202  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
16203  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
16204  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
16205  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
16206  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
16207  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
16208  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
16209  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
16210  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
16211  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
16212  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
16213  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
16214  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
16215  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
16216  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
16217  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
16218  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
16219  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
16220  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
16221  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
16222  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
16223  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
16224  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
16225  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
16226  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
16227  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
16228  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
16229  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
16230  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
16231  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
16232  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
16233  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
16234  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
16235  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
16236  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
16237  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
16238  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
16239  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
16240  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
16241  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
16242  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
16243  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
16244  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
16245  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
16246  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
16247  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
16248  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
16249  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
16250  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
16251 };
16252 
16258 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16259 {
16260  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16261  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
16262  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16263  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
16264  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16265  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
16266  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16267  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
16268  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16269  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
16270  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16271  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
16272  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16273  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
16274  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16275  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
16276  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16277  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
16278 };
16279 
16285 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16286 {
16287  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16288  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
16289  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16290  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
16291  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16292  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
16293  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16294  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
16295  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16296  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
16297  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16298  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
16299  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16300  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
16301  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16302  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
16303  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16304  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
16305  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16306  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
16307  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16308  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
16309  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16310  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
16311  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16312  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
16313  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16314  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
16315  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16316  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
16317 };
16318 
16324 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16325 {
16326  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16327  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
16328  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16329  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
16330  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16331  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
16332  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16333  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
16334 };
16335 
16341 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16342 {
16343  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16344  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
16345  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16346  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
16347  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16348  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
16349  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16350  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
16351  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16352  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
16353  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16354  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
16355  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16356  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
16357  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16358  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
16359  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16360  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
16361  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
16363  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
16365  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16366  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
16367  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
16369  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16370  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
16371  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16372  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
16373  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
16374  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
16375  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
16376  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
16377  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
16378  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
16379  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
16380  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
16381  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
16382  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
16383  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
16384  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
16385  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
16386  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
16387  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
16388  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
16389  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
16390  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
16391  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
16392  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
16393  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
16394  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
16395  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
16396  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
16397  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
16398  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
16399  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
16400  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
16401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
16402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
16403  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
16404  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
16405  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
16406  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
16407  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
16408  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
16409  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
16410  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
16411  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
16412  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
16413  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
16414  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
16415  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
16416  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
16417  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
16418  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
16419  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
16420  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
16421  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
16422  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
16423  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
16424  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
16425  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
16426  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
16427  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
16428  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
16429  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
16430  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
16431  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
16432  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
16433  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
16434  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
16435  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
16436  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
16437  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
16438  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
16439  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
16440  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
16441  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
16442  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
16443  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
16444  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
16445  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
16446  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
16447  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
16448  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
16449  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
16450  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
16451  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
16452  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
16453  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
16454  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
16455  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
16456  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
16457  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
16458  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
16459  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
16460  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
16461  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
16462  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
16463  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
16464  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
16465  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
16466  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
16467  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
16468  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
16469  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
16470  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
16471  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
16472  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
16473  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
16474  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
16475  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
16476  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
16477  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
16478  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
16479  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
16480  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
16481  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
16482  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
16483  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
16484  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
16485  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
16486  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
16487  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
16488  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
16489  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
16490  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
16491 };
16492 
16498 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16499 {
16500  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16501  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
16502  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16503  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
16504  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16505  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
16506  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16507  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
16508  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16509  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
16510  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16511  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
16512  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16513  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
16514  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16515  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
16516  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16517  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
16518  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16519  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
16520  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16521  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
16522  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16523  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
16524  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16525  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
16526  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16527  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
16528  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16529  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
16530 };
16531 
16537 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16538 {
16539  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16540  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
16541  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16542  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
16543  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16544  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
16545  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16546  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
16547 };
16548 
16554 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16555 {
16556  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16557  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
16558  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16559  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
16560  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16561  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
16562  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16563  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
16564  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16565  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
16566  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16567  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
16568  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16569  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
16570  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16571  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
16572  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16573  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
16574  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16575  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
16576  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16577  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
16578  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16579  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
16580  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16581  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
16582  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16583  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
16584  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16585  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
16586 };
16587 
16593 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16594 {
16595  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16596  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
16597  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16598  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
16599  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16600  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
16601  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16602  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
16603 };
16604 
16610 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16611 {
16612  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16613  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
16614  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16615  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
16616  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16617  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
16618  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16619  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
16620  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16621  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
16622  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16623  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
16624  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16625  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
16626  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16627  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
16628  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16629  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
16630  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16631  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
16632  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16633  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
16634  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16635  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
16636  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16637  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
16638  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16639  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
16640  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16641  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
16642 };
16643 
16649 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16650 {
16651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
16653  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
16655  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16656  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
16657  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
16659 };
16660 
16666 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16667 {
16668  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16669  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
16670  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16671  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
16672  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16673  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
16674  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16675  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
16676  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16677  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
16678  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16679  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
16680  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16681  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
16682  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16683  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
16684  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16685  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
16686  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16687  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
16688  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16689  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
16690  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16691  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
16692  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16693  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
16694  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16695  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
16696  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16697  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
16698 };
16699 
16705 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16706 {
16707  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
16709  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
16711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
16713  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
16715 };
16716 
16722 static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
16723 {
16724  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
16725  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
16726  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
16727  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
16728  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
16729  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
16730  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
16731  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
16732  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
16733  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
16734  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
16735  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
16736  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
16737  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
16738  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
16739  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
16740  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
16741  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
16742  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
16743  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
16744  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
16745  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
16746  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
16747  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
16748  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
16749  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
16750  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
16751  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
16752  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
16753  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
16754  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
16755  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
16756  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
16757  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
16758  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
16759  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
16760  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
16761  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
16762  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
16763  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
16764  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
16765  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
16766  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
16767  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
16768  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
16769  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
16770  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
16771  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
16772  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
16773  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
16774  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
16775  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
16776  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
16777  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
16778  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
16779  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
16780  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
16781  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
16782  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
16783  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
16784  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
16785  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
16786  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
16787  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
16788  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
16789  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
16790  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
16791  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
16792  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
16793  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
16794  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
16795  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
16796  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
16797  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
16798  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
16799  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
16800  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
16801  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
16802  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
16803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
16804  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
16805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
16806  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
16807  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
16808  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
16809  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
16810  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
16811  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
16812  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
16813  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
16814  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
16815  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
16816  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
16817  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
16818  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
16819  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
16820  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
16821  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
16822  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
16823  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
16824  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
16825  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
16826  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
16827  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
16828  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
16829  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
16830  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
16831  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
16832  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
16833  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
16834  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
16835  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
16836  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
16837  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
16838  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
16839  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
16840  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
16841  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
16842  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
16843  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
16844  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
16845  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
16846  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
16847  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
16848  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
16849  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_62_WIDTH },
16850  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
16851  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_63_WIDTH },
16852  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
16853  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_64_WIDTH },
16854  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
16855  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_65_WIDTH },
16856  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
16857  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_66_WIDTH },
16858  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
16859  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_67_WIDTH },
16860  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
16861  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_68_WIDTH },
16862  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
16863  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_69_WIDTH },
16864  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
16865  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_70_WIDTH },
16866  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
16867  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_71_WIDTH },
16868  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
16869  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_72_WIDTH },
16870  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
16871  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_73_WIDTH },
16872  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
16873  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_74_WIDTH },
16874  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
16875  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_75_WIDTH },
16876  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
16877  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_76_WIDTH },
16878  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
16879  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_77_WIDTH },
16880  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
16881  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_78_WIDTH },
16882  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
16883  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_79_WIDTH },
16884  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
16885  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_80_WIDTH },
16886  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
16887  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_81_WIDTH },
16888  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
16889  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_82_WIDTH },
16890  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
16891  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_83_WIDTH },
16892  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
16893  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_84_WIDTH },
16894  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
16895  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_85_WIDTH },
16896  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
16897  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_86_WIDTH },
16898  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
16899  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_87_WIDTH },
16900  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
16901  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_88_WIDTH },
16902  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
16903  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_89_WIDTH },
16904  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
16905  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_90_WIDTH },
16906  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
16907  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_91_WIDTH },
16908  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
16909  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_92_WIDTH },
16910  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
16911  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_93_WIDTH },
16912  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
16913  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_94_WIDTH },
16914  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
16915  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_95_WIDTH },
16916  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
16917  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_96_WIDTH },
16918  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
16919  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_97_WIDTH },
16920  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
16921  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_98_WIDTH },
16922  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
16923  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_99_WIDTH },
16924  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
16925  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_100_WIDTH },
16926  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
16927  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_101_WIDTH },
16928  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
16929  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_102_WIDTH },
16930  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
16931  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_103_WIDTH },
16932  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
16933  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_104_WIDTH },
16934  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
16935  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_105_WIDTH },
16936  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
16937  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_106_WIDTH },
16938  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
16939  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_107_WIDTH },
16940  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
16941  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_108_WIDTH },
16942  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
16943  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_109_WIDTH },
16944  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
16945  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_110_WIDTH },
16946  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
16947  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_111_WIDTH },
16948  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
16949  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_112_WIDTH },
16950  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
16951  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_113_WIDTH },
16952  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
16953  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_114_WIDTH },
16954  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
16955  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_115_WIDTH },
16956  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
16957  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_116_WIDTH },
16958  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
16959  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_117_WIDTH },
16960  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
16961  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_118_WIDTH },
16962  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
16963  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_119_WIDTH },
16964  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
16965  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_120_WIDTH },
16966  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
16967  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_121_WIDTH },
16968  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
16969  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_122_WIDTH },
16970  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
16971  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_123_WIDTH },
16972  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
16973  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_124_WIDTH },
16974  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
16975  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_125_WIDTH },
16976  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
16977  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_126_WIDTH },
16978  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
16979  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_127_WIDTH },
16980  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
16981  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_128_WIDTH },
16982  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
16983  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_129_WIDTH },
16984  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
16985  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_130_WIDTH },
16986  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
16987  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_131_WIDTH },
16988  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
16989  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_132_WIDTH },
16990  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
16991  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_133_WIDTH },
16992  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
16993  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_134_WIDTH },
16994  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
16995  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_135_WIDTH },
16996  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
16997  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_136_WIDTH },
16998  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
16999  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_137_WIDTH },
17000  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
17001  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_138_WIDTH },
17002  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
17003  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_139_WIDTH },
17004  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
17005  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_140_WIDTH },
17006  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
17007  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_141_WIDTH },
17008  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
17009  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_142_WIDTH },
17010  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
17011  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_143_WIDTH },
17012  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
17013  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_144_WIDTH },
17014  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
17015  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_145_WIDTH },
17016  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
17017  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_146_WIDTH },
17018  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
17019  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_147_WIDTH },
17020  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
17021  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_148_WIDTH },
17022  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
17023  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_149_WIDTH },
17024  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
17025  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_150_WIDTH },
17026  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
17027  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_151_WIDTH },
17028  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
17029  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_152_WIDTH },
17030  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
17031  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_153_WIDTH },
17032  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
17033  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_154_WIDTH },
17034  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
17035  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_155_WIDTH },
17036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
17037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_156_WIDTH },
17038  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
17039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_157_WIDTH },
17040  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
17041  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_158_WIDTH },
17042  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
17043  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_159_WIDTH },
17044  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
17045  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_160_WIDTH },
17046  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
17047  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_161_WIDTH },
17048  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
17049  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_162_WIDTH },
17050  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
17051  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_163_WIDTH },
17052  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
17053  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_164_WIDTH },
17054  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
17055  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_165_WIDTH },
17056  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
17057  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_166_WIDTH },
17058  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
17059  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_167_WIDTH },
17060  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
17061  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_168_WIDTH },
17062  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
17063  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_169_WIDTH },
17064  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
17065  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_170_WIDTH },
17066  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
17067  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_171_WIDTH },
17068  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
17069  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_172_WIDTH },
17070  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
17071  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_173_WIDTH },
17072  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
17073  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_174_WIDTH },
17074  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
17075  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_175_WIDTH },
17076  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
17077  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_176_WIDTH },
17078  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
17079  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_177_WIDTH },
17080  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
17081  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_178_WIDTH },
17082  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
17083  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_179_WIDTH },
17084  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
17085  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_180_WIDTH },
17086  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
17087  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_181_WIDTH },
17088  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
17089  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_182_WIDTH },
17090  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
17091  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_183_WIDTH },
17092  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
17093  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_184_WIDTH },
17094  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
17095  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_185_WIDTH },
17096  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
17097  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_186_WIDTH },
17098  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
17099  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_187_WIDTH },
17100  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
17101  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_188_WIDTH },
17102  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
17103  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_189_WIDTH },
17104  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
17105  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_190_WIDTH },
17106  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
17107  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_191_WIDTH },
17108  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
17109  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_192_WIDTH },
17110  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
17111  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_193_WIDTH },
17112  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
17113  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_194_WIDTH },
17114  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
17115  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_195_WIDTH },
17116  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
17117  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_196_WIDTH },
17118  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
17119  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_197_WIDTH },
17120  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
17121  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_198_WIDTH },
17122  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
17123  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_199_WIDTH },
17124  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
17125  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_200_WIDTH },
17126  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
17127  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_201_WIDTH },
17128  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
17129  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_202_WIDTH },
17130  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
17131  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_203_WIDTH },
17132  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
17133  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_204_WIDTH },
17134  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
17135  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_205_WIDTH },
17136  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
17137  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_206_WIDTH },
17138  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
17139  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_207_WIDTH },
17140  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
17141  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_208_WIDTH },
17142  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
17143  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_209_WIDTH },
17144  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
17145  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_210_WIDTH },
17146  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
17147  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_211_WIDTH },
17148  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
17149  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_212_WIDTH },
17150  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
17151  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_213_WIDTH },
17152  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
17153  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_214_WIDTH },
17154  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
17155  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_215_WIDTH },
17156  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
17157  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_216_WIDTH },
17158  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
17159  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_217_WIDTH },
17160  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
17161  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_218_WIDTH },
17162  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
17163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_219_WIDTH },
17164  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
17165  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_220_WIDTH },
17166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
17167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_221_WIDTH },
17168  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
17169  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_222_WIDTH },
17170  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
17171  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_223_WIDTH },
17172  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
17173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_224_WIDTH },
17174  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
17175  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_225_WIDTH },
17176  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
17177  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_226_WIDTH },
17178  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
17179  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_227_WIDTH },
17180  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
17181  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_228_WIDTH },
17182  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
17183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_229_WIDTH },
17184  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
17185  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_230_WIDTH },
17186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
17187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_231_WIDTH },
17188  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
17189  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_232_WIDTH },
17190  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
17191  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_233_WIDTH },
17192  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
17193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_234_WIDTH },
17194  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
17195  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_235_WIDTH },
17196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
17197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_236_WIDTH },
17198  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
17199  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_237_WIDTH },
17200  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
17201  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_238_WIDTH },
17202  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
17203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_239_WIDTH },
17204  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
17205  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_240_WIDTH },
17206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
17207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_241_WIDTH },
17208  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
17209  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_242_WIDTH },
17210  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
17211  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_243_WIDTH },
17212  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
17213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_244_WIDTH },
17214  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
17215  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_245_WIDTH },
17216  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
17217  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_246_WIDTH },
17218  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
17219  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_247_WIDTH },
17220  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
17221  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_248_WIDTH },
17222  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
17223  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_249_WIDTH },
17224 };
17225 
17230 static const SDL_MemConfig_t SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_MemEntries[SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17231 {
17232  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RX_TC0_RAM_ID, 0u,
17233  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RX_TC0_RAM_SIZE, 4u,
17234  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RX_TC0_ROW_WIDTH, ((bool)false) },
17235  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCF_RAM_ID, 0u,
17236  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCF_RAM_SIZE, 4u,
17237  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCF_ROW_WIDTH, ((bool)false) },
17238  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU7_RAM_ID, 0u,
17239  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU7_RAM_SIZE, 4u,
17240  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU7_ROW_WIDTH, ((bool)false) },
17241  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCM_RAM_ID, 0u,
17242  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCM_RAM_SIZE, 4u,
17243  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCM_ROW_WIDTH, ((bool)false) },
17244  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU6_RAM_ID, 0u,
17245  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU6_RAM_SIZE, 4u,
17246  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU6_ROW_WIDTH, ((bool)false) },
17247  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDC_RAM_ID, 0u,
17248  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDC_RAM_SIZE, 4u,
17249  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDC_ROW_WIDTH, ((bool)false) },
17250  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CIP_RAM_ID, 0u,
17251  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CIP_RAM_SIZE, 4u,
17252  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CIP_ROW_WIDTH, ((bool)false) },
17253  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_ID_RAM_ID, 0u,
17254  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_ID_RAM_SIZE, 4u,
17255  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_ID_ROW_WIDTH, ((bool)false) },
17256  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU2_RAM_ID, 0u,
17257  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU2_RAM_SIZE, 4u,
17258  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU2_ROW_WIDTH, ((bool)false) },
17259  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU4_RAM_ID, 0u,
17260  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU4_RAM_SIZE, 4u,
17261  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU4_ROW_WIDTH, ((bool)false) },
17262  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CCI_RAM_ID, 0u,
17263  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CCI_RAM_SIZE, 4u,
17264  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CCI_ROW_WIDTH, ((bool)false) },
17265  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU5_RAM_ID, 0u,
17266  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU5_RAM_SIZE, 4u,
17267  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU5_ROW_WIDTH, ((bool)false) },
17268  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDF_RAM_ID, 0u,
17269  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDF_RAM_SIZE, 4u,
17270  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDF_ROW_WIDTH, ((bool)false) },
17271  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_TMU_RAM_ID, 0u,
17272  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_TMU_RAM_SIZE, 4u,
17273  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_TMU_ROW_WIDTH, ((bool)false) },
17274  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU3_RAM_ID, 0u,
17275  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU3_RAM_SIZE, 4u,
17276  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU3_ROW_WIDTH, ((bool)false) },
17277  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDF_RAM_ID, 0u,
17278  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDF_RAM_SIZE, 4u,
17279  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDF_ROW_WIDTH, ((bool)false) },
17280  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDC_RAM_ID, 0u,
17281  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDC_RAM_SIZE, 4u,
17282  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDC_ROW_WIDTH, ((bool)false) },
17283  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RTT_RAM_ID, 0u,
17284  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RTT_RAM_SIZE, 4u,
17285  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RTT_ROW_WIDTH, ((bool)false) },
17286  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU1_RAM_ID, 0u,
17287  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU1_RAM_SIZE, 4u,
17288  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU1_ROW_WIDTH, ((bool)false) },
17289  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
17290  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
17291  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
17292 };
17293 
17298 static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17299 {
17300  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
17301  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
17302  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
17303  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
17304  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
17305  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
17306  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
17307  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
17308  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
17309  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
17310  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
17311  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
17312  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
17313  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
17314  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
17315  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
17316  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
17317  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
17318  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
17319  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
17320  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
17321  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
17322  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
17323  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
17324  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
17325  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
17326  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
17327  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
17328  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
17329  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
17330  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
17331  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
17332  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
17333  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
17334  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
17335  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
17336  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
17337  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
17338  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
17339  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
17340  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
17341  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
17342  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
17343  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
17344  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
17345  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
17346  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
17347  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
17348  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
17349  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
17350  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
17351  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
17352  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
17353  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
17354  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
17355  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
17356  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
17357  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
17358  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
17359  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
17360  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
17361  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
17362  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
17363  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0u,
17364  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
17365  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
17366  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0u,
17367  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
17368  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
17369  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0u,
17370  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
17371  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
17372  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0u,
17373  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
17374  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
17375  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0u,
17376  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
17377  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
17378  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0u,
17379  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
17380  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
17381  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0u,
17382  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
17383  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
17384 };
17385 
17391 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS] =
17392 {
17393  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17394  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_0_WIDTH },
17395  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17396  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_1_WIDTH },
17397  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17398  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_2_WIDTH },
17399  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17400  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_3_WIDTH },
17401  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17402  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_4_WIDTH },
17403  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17404  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_5_WIDTH },
17405  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
17406  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_6_WIDTH },
17407  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
17408  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_7_WIDTH },
17409  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
17410  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_8_WIDTH },
17411  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
17412  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_9_WIDTH },
17413  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
17414  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_10_WIDTH },
17415  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
17416  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_11_WIDTH },
17417  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
17418  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_12_WIDTH },
17419  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_13_CHECKER_TYPE,
17420  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_13_WIDTH },
17421  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_14_CHECKER_TYPE,
17422  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_14_WIDTH },
17423  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_15_CHECKER_TYPE,
17424  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_15_WIDTH },
17425  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_16_CHECKER_TYPE,
17426  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_16_WIDTH },
17427  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_17_CHECKER_TYPE,
17428  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_17_WIDTH },
17429  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_18_CHECKER_TYPE,
17430  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_18_WIDTH },
17431  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_19_CHECKER_TYPE,
17432  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_19_WIDTH },
17433  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_20_CHECKER_TYPE,
17434  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_20_WIDTH },
17435  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_21_CHECKER_TYPE,
17436  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_21_WIDTH },
17437  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_22_CHECKER_TYPE,
17438  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_22_WIDTH },
17439  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_23_CHECKER_TYPE,
17440  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_23_WIDTH },
17441  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_24_CHECKER_TYPE,
17442  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_24_WIDTH },
17443  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_25_CHECKER_TYPE,
17444  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_25_WIDTH },
17445  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_26_CHECKER_TYPE,
17446  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_26_WIDTH },
17447  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_27_CHECKER_TYPE,
17448  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_27_WIDTH },
17449  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_28_CHECKER_TYPE,
17450  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_28_WIDTH },
17451  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_29_CHECKER_TYPE,
17452  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_29_WIDTH },
17453  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_30_CHECKER_TYPE,
17454  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_30_WIDTH },
17455  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_31_CHECKER_TYPE,
17456  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_31_WIDTH },
17457  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_32_CHECKER_TYPE,
17458  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_32_WIDTH },
17459  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_33_CHECKER_TYPE,
17460  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_33_WIDTH },
17461  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_34_CHECKER_TYPE,
17462  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_34_WIDTH },
17463  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_35_CHECKER_TYPE,
17464  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_35_WIDTH },
17465  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_36_CHECKER_TYPE,
17466  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_36_WIDTH },
17467  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_37_CHECKER_TYPE,
17468  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_37_WIDTH },
17469  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_38_CHECKER_TYPE,
17470  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_38_WIDTH },
17471  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_39_CHECKER_TYPE,
17472  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_39_WIDTH },
17473  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_40_CHECKER_TYPE,
17474  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_40_WIDTH },
17475  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_41_CHECKER_TYPE,
17476  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_41_WIDTH },
17477  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_42_CHECKER_TYPE,
17478  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_42_WIDTH },
17479  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_43_CHECKER_TYPE,
17480  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_43_WIDTH },
17481  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_44_CHECKER_TYPE,
17482  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_44_WIDTH },
17483  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_45_CHECKER_TYPE,
17484  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_45_WIDTH },
17485  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_46_CHECKER_TYPE,
17486  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_46_WIDTH },
17487  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_47_CHECKER_TYPE,
17488  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_47_WIDTH },
17489  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_48_CHECKER_TYPE,
17490  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_48_WIDTH },
17491 };
17492 
17498 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
17499 {
17500  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17501  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
17502  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17503  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
17504  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17505  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
17506  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17507  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
17508  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17509  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
17510  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17511  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
17512  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
17513  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
17514  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
17515  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
17516  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
17517  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
17518  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
17519  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
17520  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
17521  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
17522  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
17523  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
17524  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
17525  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
17526  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
17527  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
17528  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
17529  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
17530  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
17531  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
17532  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
17533  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
17534  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
17535  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
17536  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
17537  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
17538  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
17539  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
17540  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
17541  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
17542  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
17543  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
17544  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
17545  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
17546  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
17547  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
17548  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
17549  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
17550  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
17551  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
17552  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
17553  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
17554  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
17555  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
17556  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
17557  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
17558  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
17559  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
17560  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
17561  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
17562 };
17563 
17569 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
17570 {
17571  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17572  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
17573  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17574  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
17575  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17576  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
17577  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17578  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
17579  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17580  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
17581  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17582  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
17583  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
17584  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
17585  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
17586  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
17587  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
17588  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
17589  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
17590  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
17591  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
17592  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
17593  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
17594  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
17595  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
17596  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
17597  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
17598  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
17599  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
17600  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
17601  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_CHECKER_TYPE,
17602  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_WIDTH },
17603 };
17604 
17610 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
17611 {
17612  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17613  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
17614  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17615  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
17616  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17617  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
17618  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17619  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
17620  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17621  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
17622  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17623  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
17624  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
17625  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
17626  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
17627  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
17628  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
17629  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
17630  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
17631  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
17632  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
17633  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
17634  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
17635  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
17636  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
17637  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
17638  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
17639  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
17640  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
17641  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
17642  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
17643  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
17644  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
17645  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
17646  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
17647  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
17648  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
17649  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
17650  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
17651  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
17652  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
17653  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
17654  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
17655  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
17656  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
17657  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
17658  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
17659  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
17660  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
17661  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
17662  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
17663  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
17664  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
17665  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
17666  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
17667  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
17668  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
17669  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
17670  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
17671  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
17672  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
17673  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
17674 };
17675 
17681 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
17682 {
17683  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17684  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
17685  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17686  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
17687  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17688  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
17689  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17690  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
17691  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17692  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
17693  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17694  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
17695  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
17696  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
17697  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
17698  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
17699  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
17700  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
17701  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
17702  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
17703  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
17704  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
17705  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
17706  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
17707  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
17708  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
17709  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
17710  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
17711  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
17712  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
17713 };
17714 
17720 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS] =
17721 {
17722  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17723  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_WIDTH },
17724  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17725  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_WIDTH },
17726  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17727  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_WIDTH },
17728  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17729  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_WIDTH },
17730  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17731  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_WIDTH },
17732  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17733  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_WIDTH },
17734  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
17735  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_WIDTH },
17736  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
17737  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_WIDTH },
17738  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
17739  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_WIDTH },
17740  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
17741  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_WIDTH },
17742  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
17743  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_WIDTH },
17744  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
17745  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_WIDTH },
17746  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
17747  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_WIDTH },
17748 };
17749 
17755 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
17756 {
17757  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
17758  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
17759  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
17760  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
17761  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
17762  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
17763  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
17764  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
17765  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
17766  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
17767  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
17768  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
17769 };
17770 
17775 static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17776 {
17777  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
17778  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
17779  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
17780  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
17781  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
17782  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
17783  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
17784  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
17785  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
17786  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
17787  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
17788  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
17789  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
17790  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
17791  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
17792  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
17793  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
17794  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
17795  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
17796  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
17797  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
17798 };
17799 
17805 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
17806 {
17807  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
17808  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
17809  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
17810  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
17811 };
17812 
17817 static const SDL_MemConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17818 {
17819  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
17820  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
17821  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
17822  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
17823  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
17824  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
17825  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
17826  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
17827  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
17828  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
17829  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
17830  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
17831  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
17832  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
17833  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
17834  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID, 0u,
17835  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_SIZE, 4u,
17836  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ROW_WIDTH, ((bool)false) },
17837  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID, 0u,
17838  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_SIZE, 4u,
17839  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ROW_WIDTH, ((bool)false) },
17840 };
17841 
17847 static const SDL_GrpChkConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
17848 {
17849  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
17850  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
17851  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
17852  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
17853 };
17854 
17859 static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
17860 {
17861  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x40500000u,
17862  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
17863  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
17864 };
17865 
17871 static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
17872 {
17873  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
17874  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
17875 };
17876 
17881 static const SDL_MemConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_MemEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
17882 {
17883  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_RAM_ECC_RAM_ID, 0u,
17884  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_RAM_ECC_RAM_SIZE, 4u,
17885  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_RAM_ECC_ROW_WIDTH, ((bool)false) },
17886  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_TIMER_FSM_RAM_ECC_RAM_ID, 0u,
17887  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_TIMER_FSM_RAM_ECC_RAM_SIZE, 4u,
17888  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_TIMER_FSM_RAM_ECC_ROW_WIDTH, ((bool)false) },
17889  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_REPROG_FSM_RAM_ECC_RAM_ID, 0u,
17890  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_REPROG_FSM_RAM_ECC_RAM_SIZE, 4u,
17891  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_REPROG_FSM_RAM_ECC_ROW_WIDTH, ((bool)false) },
17892  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_FIFO_RAM_ECC_RAM_ID, 0u,
17893  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_FIFO_RAM_ECC_RAM_SIZE, 4u,
17894  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_FIFO_RAM_ECC_ROW_WIDTH, ((bool)false) },
17895  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_OFFSET_RAM_ECC_RAM_ID, 0u,
17896  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_OFFSET_RAM_ECC_RAM_SIZE, 4u,
17897  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_OFFSET_RAM_ECC_ROW_WIDTH, ((bool)false) },
17898  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_TIMER_FSM_RAM_ECC_RAM_ID, 0u,
17899  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_TIMER_FSM_RAM_ECC_RAM_SIZE, 4u,
17900  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_TIMER_FSM_RAM_ECC_ROW_WIDTH, ((bool)false) },
17901  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_REPROG_FSM_RAM_ECC_RAM_ID, 0u,
17902  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_REPROG_FSM_RAM_ECC_RAM_SIZE, 4u,
17903  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_REPROG_FSM_RAM_ECC_ROW_WIDTH, ((bool)false) },
17904  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_FIFO_RAM_ECC_RAM_ID, 0u,
17905  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_FIFO_RAM_ECC_RAM_SIZE, 4u,
17906  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_FIFO_RAM_ECC_ROW_WIDTH, ((bool)false) },
17907  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_OFFSET_RAM_ECC_RAM_ID, 0u,
17908  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_OFFSET_RAM_ECC_RAM_SIZE, 4u,
17909  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_OFFSET_RAM_ECC_ROW_WIDTH, ((bool)false) },
17910  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_INTMAP_IM_SPRAM_1024X15_SWW_SR_RAM_ID, 0u,
17911  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_INTMAP_IM_SPRAM_1024X15_SWW_SR_RAM_SIZE, 4u,
17912  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_INTMAP_IM_SPRAM_1024X15_SWW_SR_ROW_WIDTH, ((bool)false) },
17913  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_STATREG_SR_SPRAM_64X128_SWW_SR_RAM_ID, 0u,
17914  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_STATREG_SR_SPRAM_64X128_SWW_SR_RAM_SIZE, 4u,
17915  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_STATREG_SR_SPRAM_64X128_SWW_SR_ROW_WIDTH, ((bool)false) },
17916  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_INTMAP_IM_SPRAM_1024X15_SWW_SR_RAM_ID, 0u,
17917  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_INTMAP_IM_SPRAM_1024X15_SWW_SR_RAM_SIZE, 4u,
17918  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_INTMAP_IM_SPRAM_1024X15_SWW_SR_ROW_WIDTH, ((bool)false) },
17919  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_STATREG_SR_SPRAM_64X128_SWW_SR_RAM_ID, 0u,
17920  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_STATREG_SR_SPRAM_64X128_SWW_SR_RAM_SIZE, 4u,
17921  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_STATREG_SR_SPRAM_64X128_SWW_SR_ROW_WIDTH, ((bool)false) },
17922  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_STRAM_RAM_ID, 0u,
17923  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_STRAM_RAM_SIZE, 4u,
17924  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_STRAM_ROW_WIDTH, ((bool)false) },
17925  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_BUFRAM_ECC_RAM_ID, 0u,
17926  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_BUFRAM_ECC_RAM_SIZE, 4u,
17927  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_BUFRAM_ECC_ROW_WIDTH, ((bool)false) },
17928  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_STRAM_RAM_ID, 0u,
17929  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_STRAM_RAM_SIZE, 4u,
17930  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_STRAM_ROW_WIDTH, ((bool)false) },
17931  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_BUFRAM_RAM_ID, 0u,
17932  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_BUFRAM_RAM_SIZE, 4u,
17933  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
17934  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
17935  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
17936  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
17937  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
17938  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
17939  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
17940  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
17941  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
17942  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
17943  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
17944  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
17945  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
17946  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
17947  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
17948  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
17949  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
17950  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
17951  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
17952  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
17953  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
17954  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
17955  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID, 0u,
17956  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_SIZE, 4u,
17957  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_ROW_WIDTH, ((bool)false) },
17958  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID, 0u,
17959  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_SIZE, 4u,
17960  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_ROW_WIDTH, ((bool)false) },
17961 };
17962 
17968 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
17969 {
17970  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
17971  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
17972  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
17973  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
17974  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
17975  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
17976  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
17977  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
17978  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
17979  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
17980  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
17981  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
17982 };
17983 
17989 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
17990 {
17991  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
17992  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_0_WIDTH },
17993  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
17994  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_1_WIDTH },
17995  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
17996  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_2_WIDTH },
17997  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
17998  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_3_WIDTH },
17999  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
18000  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_4_WIDTH },
18001  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
18002  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_5_WIDTH },
18003  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
18004  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_6_WIDTH },
18005  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
18006  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_7_WIDTH },
18007  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
18008  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_8_WIDTH },
18009  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
18010  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_9_WIDTH },
18011  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
18012  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_10_WIDTH },
18013  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
18014  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_11_WIDTH },
18015  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
18016  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_12_WIDTH },
18017  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
18018  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_13_WIDTH },
18019  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
18020  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_14_WIDTH },
18021  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
18022  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_15_WIDTH },
18023  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
18024  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_16_WIDTH },
18025  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
18026  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_17_WIDTH },
18027  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
18028  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_18_WIDTH },
18029  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
18030  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_19_WIDTH },
18031  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
18032  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_20_WIDTH },
18033  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
18034  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_21_WIDTH },
18035  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
18036  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_22_WIDTH },
18037  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
18038  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_23_WIDTH },
18039  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
18040  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_24_WIDTH },
18041  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
18042  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_25_WIDTH },
18043  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
18044  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_26_WIDTH },
18045  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
18046  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_27_WIDTH },
18047  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
18048  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_28_WIDTH },
18049  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
18050  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_29_WIDTH },
18051  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
18052  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_30_WIDTH },
18053  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
18054  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_31_WIDTH },
18055  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
18056  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_32_WIDTH },
18057  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
18058  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_33_WIDTH },
18059  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
18060  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_34_WIDTH },
18061  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
18062  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_35_WIDTH },
18063  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
18064  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_36_WIDTH },
18065  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
18066  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_37_WIDTH },
18067  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
18068  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_38_WIDTH },
18069  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
18070  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_39_WIDTH },
18071  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
18072  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_40_WIDTH },
18073  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
18074  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_41_WIDTH },
18075  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
18076  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_42_WIDTH },
18077  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
18078  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_43_WIDTH },
18079  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
18080  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_44_WIDTH },
18081  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
18082  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_45_WIDTH },
18083  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
18084  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_46_WIDTH },
18085  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
18086  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_47_WIDTH },
18087  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
18088  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_48_WIDTH },
18089  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
18090  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_49_WIDTH },
18091  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
18092  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_50_WIDTH },
18093  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
18094  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_51_WIDTH },
18095  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
18096  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_52_WIDTH },
18097  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
18098  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_53_WIDTH },
18099  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
18100  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_54_WIDTH },
18101  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
18102  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_55_WIDTH },
18103  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
18104  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_56_WIDTH },
18105  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
18106  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_57_WIDTH },
18107  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
18108  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_58_WIDTH },
18109  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
18110  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_59_WIDTH },
18111  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
18112  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_60_WIDTH },
18113  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
18114  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_61_WIDTH },
18115  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
18116  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_62_WIDTH },
18117  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
18118  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_63_WIDTH },
18119  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
18120  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_64_WIDTH },
18121  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
18122  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_65_WIDTH },
18123  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
18124  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_66_WIDTH },
18125  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
18126  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_67_WIDTH },
18127  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
18128  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_68_WIDTH },
18129  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
18130  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_69_WIDTH },
18131  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
18132  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_70_WIDTH },
18133  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
18134  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_71_WIDTH },
18135  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
18136  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_72_WIDTH },
18137  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
18138  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_73_WIDTH },
18139  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
18140  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_74_WIDTH },
18141  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
18142  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_75_WIDTH },
18143  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
18144  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_76_WIDTH },
18145  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
18146  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_77_WIDTH },
18147  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
18148  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_78_WIDTH },
18149  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
18150  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_79_WIDTH },
18151  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
18152  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_80_WIDTH },
18153  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
18154  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_81_WIDTH },
18155  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
18156  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_82_WIDTH },
18157  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
18158  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_83_WIDTH },
18159  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
18160  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_84_WIDTH },
18161  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
18162  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_85_WIDTH },
18163  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
18164  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_86_WIDTH },
18165  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
18166  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_87_WIDTH },
18167  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
18168  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_88_WIDTH },
18169  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
18170  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_89_WIDTH },
18171  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
18172  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_90_WIDTH },
18173  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
18174  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_91_WIDTH },
18175  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
18176  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_92_WIDTH },
18177  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
18178  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_93_WIDTH },
18179  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
18180  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_94_WIDTH },
18181  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
18182  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_95_WIDTH },
18183  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
18184  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_96_WIDTH },
18185  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
18186  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_97_WIDTH },
18187  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
18188  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_98_WIDTH },
18189  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
18190  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_99_WIDTH },
18191  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
18192  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_100_WIDTH },
18193  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
18194  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_101_WIDTH },
18195  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
18196  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_102_WIDTH },
18197  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
18198  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_103_WIDTH },
18199  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
18200  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_104_WIDTH },
18201  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
18202  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_105_WIDTH },
18203  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
18204  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_106_WIDTH },
18205  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
18206  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_107_WIDTH },
18207  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
18208  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_108_WIDTH },
18209  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
18210  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_109_WIDTH },
18211  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
18212  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_110_WIDTH },
18213  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
18214  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_111_WIDTH },
18215  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
18216  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_112_WIDTH },
18217  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
18218  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_113_WIDTH },
18219  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
18220  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_114_WIDTH },
18221  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
18222  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_115_WIDTH },
18223  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
18224  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_116_WIDTH },
18225  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
18226  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_117_WIDTH },
18227  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
18228  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_118_WIDTH },
18229  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
18230  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_119_WIDTH },
18231  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
18232  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_120_WIDTH },
18233  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
18234  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_121_WIDTH },
18235  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
18236  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_122_WIDTH },
18237  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
18238  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_123_WIDTH },
18239  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
18240  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_124_WIDTH },
18241  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
18242  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_125_WIDTH },
18243  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
18244  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_126_WIDTH },
18245  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
18246  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_127_WIDTH },
18247  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
18248  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_128_WIDTH },
18249  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
18250  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_129_WIDTH },
18251  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
18252  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_130_WIDTH },
18253  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
18254  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_131_WIDTH },
18255  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
18256  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_132_WIDTH },
18257  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
18258  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_133_WIDTH },
18259  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
18260  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_134_WIDTH },
18261  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
18262  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_135_WIDTH },
18263  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
18264  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_136_WIDTH },
18265  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
18266  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_137_WIDTH },
18267  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
18268  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_138_WIDTH },
18269  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
18270  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_139_WIDTH },
18271  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
18272  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_140_WIDTH },
18273  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
18274  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_141_WIDTH },
18275  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
18276  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_142_WIDTH },
18277  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
18278  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_143_WIDTH },
18279  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
18280  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_144_WIDTH },
18281  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
18282  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_145_WIDTH },
18283  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
18284  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_146_WIDTH },
18285  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
18286  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_147_WIDTH },
18287  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
18288  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_148_WIDTH },
18289  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
18290  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_149_WIDTH },
18291  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
18292  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_150_WIDTH },
18293  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
18294  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_151_WIDTH },
18295  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
18296  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_152_WIDTH },
18297  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
18298  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_153_WIDTH },
18299  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
18300  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_154_WIDTH },
18301  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
18302  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_155_WIDTH },
18303  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
18304  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_156_WIDTH },
18305  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
18306  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_157_WIDTH },
18307  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
18308  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_158_WIDTH },
18309  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
18310  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_159_WIDTH },
18311  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
18312  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_160_WIDTH },
18313  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
18314  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_161_WIDTH },
18315  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
18316  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_162_WIDTH },
18317  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
18318  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_163_WIDTH },
18319  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
18320  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_164_WIDTH },
18321  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
18322  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_165_WIDTH },
18323  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
18324  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_166_WIDTH },
18325  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
18326  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_167_WIDTH },
18327  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
18328  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_168_WIDTH },
18329  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
18330  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_169_WIDTH },
18331  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
18332  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_170_WIDTH },
18333  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
18334  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_171_WIDTH },
18335  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
18336  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_172_WIDTH },
18337  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
18338  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_173_WIDTH },
18339  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
18340  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_174_WIDTH },
18341  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
18342  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_175_WIDTH },
18343  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
18344  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_176_WIDTH },
18345  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
18346  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_177_WIDTH },
18347  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
18348  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_178_WIDTH },
18349  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
18350  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_179_WIDTH },
18351  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
18352  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_180_WIDTH },
18353  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
18354  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_181_WIDTH },
18355  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
18356  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_182_WIDTH },
18357  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
18358  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_183_WIDTH },
18359  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
18360  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_184_WIDTH },
18361  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
18362  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_185_WIDTH },
18363  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
18364  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_186_WIDTH },
18365  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
18366  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_187_WIDTH },
18367  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
18368  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_188_WIDTH },
18369  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
18370  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_189_WIDTH },
18371  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
18372  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_190_WIDTH },
18373  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
18374  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_191_WIDTH },
18375  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
18376  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_192_WIDTH },
18377  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
18378  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_193_WIDTH },
18379  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
18380  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_194_WIDTH },
18381  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
18382  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_195_WIDTH },
18383  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
18384  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_196_WIDTH },
18385  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
18386  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_197_WIDTH },
18387  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
18388  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_198_WIDTH },
18389  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
18390  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_199_WIDTH },
18391  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
18392  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_200_WIDTH },
18393  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
18394  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_201_WIDTH },
18395  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
18396  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_202_WIDTH },
18397  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
18398  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_203_WIDTH },
18399  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
18400  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_204_WIDTH },
18401  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
18402  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_205_WIDTH },
18403  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
18404  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_206_WIDTH },
18405  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
18406  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_207_WIDTH },
18407  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
18408  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_208_WIDTH },
18409  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
18410  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_209_WIDTH },
18411  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
18412  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_210_WIDTH },
18413  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
18414  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_211_WIDTH },
18415  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
18416  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_212_WIDTH },
18417  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
18418  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_213_WIDTH },
18419  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
18420  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_214_WIDTH },
18421  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
18422  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_215_WIDTH },
18423  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
18424  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_216_WIDTH },
18425  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
18426  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_217_WIDTH },
18427  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
18428  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_218_WIDTH },
18429  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
18430  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_219_WIDTH },
18431  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
18432  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_220_WIDTH },
18433  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
18434  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_221_WIDTH },
18435  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
18436  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_222_WIDTH },
18437  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
18438  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_223_WIDTH },
18439  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
18440  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_224_WIDTH },
18441  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
18442  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_225_WIDTH },
18443  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
18444  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_226_WIDTH },
18445  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
18446  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_227_WIDTH },
18447  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
18448  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_228_WIDTH },
18449  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
18450  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_229_WIDTH },
18451  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
18452  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_230_WIDTH },
18453  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
18454  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_231_WIDTH },
18455  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
18456  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_232_WIDTH },
18457  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
18458  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_233_WIDTH },
18459  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
18460  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_234_WIDTH },
18461  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
18462  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_235_WIDTH },
18463  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
18464  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_236_WIDTH },
18465  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
18466  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_237_WIDTH },
18467  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
18468  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_238_WIDTH },
18469  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
18470  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_239_WIDTH },
18471  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
18472  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_240_WIDTH },
18473  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
18474  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_241_WIDTH },
18475  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
18476  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_242_WIDTH },
18477  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
18478  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_243_WIDTH },
18479  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
18480  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_244_WIDTH },
18481  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
18482  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_245_WIDTH },
18483  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
18484  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_246_WIDTH },
18485  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
18486  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_247_WIDTH },
18487  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
18488  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_248_WIDTH },
18489  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
18490  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_249_WIDTH },
18491  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
18492  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_250_WIDTH },
18493  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
18494  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_251_WIDTH },
18495  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
18496  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_252_WIDTH },
18497  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
18498  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_253_WIDTH },
18499  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
18500  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_254_WIDTH },
18501  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
18502  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_GROUP_255_WIDTH },
18503 };
18504 
18510 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_MAX_NUM_CHECKERS] =
18511 {
18512  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
18513  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_0_WIDTH },
18514  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
18515  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_1_WIDTH },
18516  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
18517  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_2_WIDTH },
18518  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
18519  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_3_WIDTH },
18520  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
18521  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_GROUP_4_WIDTH },
18522 };
18523 
18529 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
18530 {
18531  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
18532  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_0_WIDTH },
18533  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
18534  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_1_WIDTH },
18535  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
18536  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_2_WIDTH },
18537  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
18538  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_3_WIDTH },
18539  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
18540  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_4_WIDTH },
18541  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
18542  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_5_WIDTH },
18543  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
18544  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_6_WIDTH },
18545  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
18546  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_7_WIDTH },
18547  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
18548  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_8_WIDTH },
18549  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
18550  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_9_WIDTH },
18551  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
18552  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_10_WIDTH },
18553  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
18554  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_11_WIDTH },
18555  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
18556  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_12_WIDTH },
18557  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
18558  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_13_WIDTH },
18559  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
18560  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_14_WIDTH },
18561  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
18562  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_15_WIDTH },
18563  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
18564  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_16_WIDTH },
18565  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
18566  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_17_WIDTH },
18567  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
18568  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_18_WIDTH },
18569  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
18570  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_19_WIDTH },
18571  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
18572  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_20_WIDTH },
18573  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
18574  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_21_WIDTH },
18575  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
18576  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_22_WIDTH },
18577  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
18578  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_23_WIDTH },
18579  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
18580  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_24_WIDTH },
18581  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
18582  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_25_WIDTH },
18583  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
18584  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_26_WIDTH },
18585  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
18586  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_27_WIDTH },
18587  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
18588  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_28_WIDTH },
18589  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
18590  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_29_WIDTH },
18591  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
18592  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_30_WIDTH },
18593  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
18594  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_31_WIDTH },
18595  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
18596  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_32_WIDTH },
18597  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
18598  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_33_WIDTH },
18599  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
18600  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_34_WIDTH },
18601  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
18602  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_35_WIDTH },
18603  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
18604  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_36_WIDTH },
18605  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
18606  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_37_WIDTH },
18607  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
18608  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_38_WIDTH },
18609  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
18610  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_39_WIDTH },
18611  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
18612  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_40_WIDTH },
18613  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
18614  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_41_WIDTH },
18615  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
18616  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_42_WIDTH },
18617  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
18618  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_43_WIDTH },
18619  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
18620  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_44_WIDTH },
18621  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
18622  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_45_WIDTH },
18623  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
18624  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_46_WIDTH },
18625  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
18626  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_47_WIDTH },
18627  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
18628  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_48_WIDTH },
18629  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
18630  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_49_WIDTH },
18631  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
18632  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_50_WIDTH },
18633  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
18634  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_51_WIDTH },
18635  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
18636  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_52_WIDTH },
18637  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
18638  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_53_WIDTH },
18639  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
18640  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_54_WIDTH },
18641  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
18642  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_55_WIDTH },
18643  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
18644  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_56_WIDTH },
18645  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
18646  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_57_WIDTH },
18647  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
18648  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_58_WIDTH },
18649  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
18650  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_59_WIDTH },
18651  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
18652  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_60_WIDTH },
18653  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
18654  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_61_WIDTH },
18655  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
18656  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_62_WIDTH },
18657  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
18658  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_63_WIDTH },
18659  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
18660  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_64_WIDTH },
18661  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
18662  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_65_WIDTH },
18663  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
18664  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_66_WIDTH },
18665  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
18666  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_67_WIDTH },
18667  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
18668  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_68_WIDTH },
18669  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
18670  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_69_WIDTH },
18671  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
18672  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_70_WIDTH },
18673  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
18674  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_71_WIDTH },
18675  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
18676  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_72_WIDTH },
18677  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
18678  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_73_WIDTH },
18679  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
18680  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_74_WIDTH },
18681  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
18682  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_75_WIDTH },
18683  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
18684  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_76_WIDTH },
18685  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
18686  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_77_WIDTH },
18687  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
18688  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_78_WIDTH },
18689  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
18690  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_79_WIDTH },
18691  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
18692  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_80_WIDTH },
18693  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
18694  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_81_WIDTH },
18695  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
18696  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_82_WIDTH },
18697  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
18698  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_83_WIDTH },
18699  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
18700  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_84_WIDTH },
18701  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
18702  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_85_WIDTH },
18703  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
18704  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_86_WIDTH },
18705  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
18706  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_87_WIDTH },
18707  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
18708  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_88_WIDTH },
18709  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
18710  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_89_WIDTH },
18711  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
18712  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_90_WIDTH },
18713  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
18714  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_91_WIDTH },
18715  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
18716  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_92_WIDTH },
18717  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
18718  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_93_WIDTH },
18719  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
18720  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_94_WIDTH },
18721  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
18722  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_95_WIDTH },
18723  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
18724  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_96_WIDTH },
18725  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
18726  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_97_WIDTH },
18727  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
18728  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_98_WIDTH },
18729  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
18730  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_99_WIDTH },
18731  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
18732  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_100_WIDTH },
18733  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
18734  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_101_WIDTH },
18735  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
18736  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_102_WIDTH },
18737  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
18738  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_103_WIDTH },
18739  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
18740  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_104_WIDTH },
18741  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
18742  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_105_WIDTH },
18743  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
18744  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_106_WIDTH },
18745  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
18746  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_107_WIDTH },
18747  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
18748  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_108_WIDTH },
18749  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
18750  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_109_WIDTH },
18751  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
18752  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_110_WIDTH },
18753  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
18754  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_111_WIDTH },
18755  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
18756  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_112_WIDTH },
18757  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
18758  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_113_WIDTH },
18759  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
18760  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_114_WIDTH },
18761  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
18762  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_115_WIDTH },
18763  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
18764  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_116_WIDTH },
18765  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
18766  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_117_WIDTH },
18767  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
18768  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_118_WIDTH },
18769  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
18770  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_119_WIDTH },
18771  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
18772  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_120_WIDTH },
18773  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
18774  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_121_WIDTH },
18775  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
18776  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_122_WIDTH },
18777  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
18778  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_123_WIDTH },
18779  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
18780  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_124_WIDTH },
18781  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
18782  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_125_WIDTH },
18783  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
18784  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_126_WIDTH },
18785  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
18786  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_127_WIDTH },
18787  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
18788  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_128_WIDTH },
18789  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
18790  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_129_WIDTH },
18791  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
18792  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_130_WIDTH },
18793  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
18794  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_131_WIDTH },
18795  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
18796  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_132_WIDTH },
18797  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
18798  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_133_WIDTH },
18799  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
18800  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_134_WIDTH },
18801  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
18802  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_135_WIDTH },
18803  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
18804  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_136_WIDTH },
18805  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
18806  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_137_WIDTH },
18807  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
18808  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_138_WIDTH },
18809  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
18810  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_139_WIDTH },
18811  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
18812  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_140_WIDTH },
18813  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
18814  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_141_WIDTH },
18815  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
18816  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_142_WIDTH },
18817  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
18818  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_143_WIDTH },
18819  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
18820  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_144_WIDTH },
18821  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
18822  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_145_WIDTH },
18823  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
18824  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_146_WIDTH },
18825  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
18826  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_147_WIDTH },
18827  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
18828  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_148_WIDTH },
18829  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
18830  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_149_WIDTH },
18831  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
18832  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_150_WIDTH },
18833  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
18834  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_151_WIDTH },
18835  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
18836  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_152_WIDTH },
18837  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
18838  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_153_WIDTH },
18839  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
18840  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_154_WIDTH },
18841  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
18842  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_155_WIDTH },
18843  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
18844  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_156_WIDTH },
18845  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
18846  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_157_WIDTH },
18847  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
18848  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_158_WIDTH },
18849  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
18850  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_159_WIDTH },
18851  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
18852  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_160_WIDTH },
18853  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
18854  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_161_WIDTH },
18855  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
18856  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_162_WIDTH },
18857  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
18858  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_163_WIDTH },
18859  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
18860  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_164_WIDTH },
18861  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
18862  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_165_WIDTH },
18863  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
18864  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_166_WIDTH },
18865  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
18866  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_167_WIDTH },
18867  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
18868  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_168_WIDTH },
18869  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
18870  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_169_WIDTH },
18871  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
18872  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_170_WIDTH },
18873  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
18874  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_171_WIDTH },
18875  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
18876  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_172_WIDTH },
18877  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
18878  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_173_WIDTH },
18879  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
18880  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_174_WIDTH },
18881  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
18882  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_175_WIDTH },
18883  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
18884  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_176_WIDTH },
18885  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
18886  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_177_WIDTH },
18887  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
18888  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_178_WIDTH },
18889  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
18890  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_179_WIDTH },
18891  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
18892  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_180_WIDTH },
18893  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
18894  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_181_WIDTH },
18895  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
18896  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_182_WIDTH },
18897  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
18898  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_183_WIDTH },
18899  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
18900  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_184_WIDTH },
18901  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
18902  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_185_WIDTH },
18903  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
18904  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_186_WIDTH },
18905  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
18906  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_187_WIDTH },
18907  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
18908  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_188_WIDTH },
18909  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
18910  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_189_WIDTH },
18911  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
18912  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_190_WIDTH },
18913  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
18914  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_191_WIDTH },
18915  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
18916  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_192_WIDTH },
18917  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
18918  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_193_WIDTH },
18919  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
18920  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_194_WIDTH },
18921  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
18922  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_195_WIDTH },
18923  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
18924  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_196_WIDTH },
18925  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
18926  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_197_WIDTH },
18927  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
18928  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_198_WIDTH },
18929  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
18930  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_199_WIDTH },
18931  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
18932  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_200_WIDTH },
18933  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
18934  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_201_WIDTH },
18935  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
18936  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_202_WIDTH },
18937  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
18938  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_203_WIDTH },
18939  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
18940  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_204_WIDTH },
18941  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
18942  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_205_WIDTH },
18943  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
18944  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_206_WIDTH },
18945  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
18946  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_207_WIDTH },
18947  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
18948  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_208_WIDTH },
18949  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
18950  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_209_WIDTH },
18951  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
18952  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_210_WIDTH },
18953  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
18954  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_211_WIDTH },
18955  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
18956  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_212_WIDTH },
18957  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
18958  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_213_WIDTH },
18959  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
18960  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_214_WIDTH },
18961  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
18962  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_215_WIDTH },
18963  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
18964  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_216_WIDTH },
18965  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
18966  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_217_WIDTH },
18967  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
18968  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_218_WIDTH },
18969  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
18970  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_219_WIDTH },
18971  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
18972  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_220_WIDTH },
18973  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
18974  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_221_WIDTH },
18975  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
18976  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_222_WIDTH },
18977  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
18978  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_223_WIDTH },
18979  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
18980  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_224_WIDTH },
18981  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
18982  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_225_WIDTH },
18983  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
18984  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_226_WIDTH },
18985  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
18986  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_227_WIDTH },
18987  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
18988  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_228_WIDTH },
18989  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
18990  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_229_WIDTH },
18991  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
18992  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_230_WIDTH },
18993  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
18994  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_231_WIDTH },
18995  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
18996  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_232_WIDTH },
18997  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
18998  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_233_WIDTH },
18999  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
19000  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_234_WIDTH },
19001  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
19002  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_235_WIDTH },
19003  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
19004  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_236_WIDTH },
19005  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
19006  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_237_WIDTH },
19007  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
19008  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_238_WIDTH },
19009  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
19010  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_239_WIDTH },
19011  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
19012  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_240_WIDTH },
19013  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
19014  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_241_WIDTH },
19015  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
19016  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_242_WIDTH },
19017  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
19018  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_243_WIDTH },
19019  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
19020  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_244_WIDTH },
19021  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
19022  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_245_WIDTH },
19023  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
19024  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_246_WIDTH },
19025  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
19026  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_247_WIDTH },
19027  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
19028  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_248_WIDTH },
19029  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
19030  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_249_WIDTH },
19031  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
19032  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_250_WIDTH },
19033  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
19034  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_251_WIDTH },
19035  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
19036  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_252_WIDTH },
19037  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
19038  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_253_WIDTH },
19039  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
19040  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_254_WIDTH },
19041  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
19042  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_GROUP_255_WIDTH },
19043 };
19044 
19050 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_MAX_NUM_CHECKERS] =
19051 {
19052  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
19053  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_0_WIDTH },
19054  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
19055  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_1_WIDTH },
19056  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
19057  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_2_WIDTH },
19058  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
19059  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_3_WIDTH },
19060  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
19061  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_4_WIDTH },
19062  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
19063  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_5_WIDTH },
19064  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
19065  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_6_WIDTH },
19066  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
19067  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_7_WIDTH },
19068  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
19069  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_8_WIDTH },
19070  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
19071  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_9_WIDTH },
19072  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
19073  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_10_WIDTH },
19074  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
19075  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_11_WIDTH },
19076  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
19077  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_12_WIDTH },
19078  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
19079  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_13_WIDTH },
19080  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
19081  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_14_WIDTH },
19082  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
19083  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_15_WIDTH },
19084  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
19085  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_16_WIDTH },
19086  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
19087  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_17_WIDTH },
19088  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
19089  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_18_WIDTH },
19090  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
19091  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_19_WIDTH },
19092  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
19093  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_20_WIDTH },
19094  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
19095  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_21_WIDTH },
19096  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
19097  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_22_WIDTH },
19098  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
19099  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_23_WIDTH },
19100  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
19101  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_24_WIDTH },
19102  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
19103  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_25_WIDTH },
19104  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
19105  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_26_WIDTH },
19106  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
19107  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_27_WIDTH },
19108  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
19109  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_28_WIDTH },
19110  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
19111  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_29_WIDTH },
19112  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
19113  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_30_WIDTH },
19114  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
19115  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_31_WIDTH },
19116  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
19117  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_32_WIDTH },
19118  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
19119  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_33_WIDTH },
19120  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
19121  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_34_WIDTH },
19122  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
19123  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_35_WIDTH },
19124  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
19125  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_36_WIDTH },
19126  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
19127  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_37_WIDTH },
19128  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
19129  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_38_WIDTH },
19130  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
19131  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_39_WIDTH },
19132  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
19133  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_40_WIDTH },
19134  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
19135  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_41_WIDTH },
19136  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
19137  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_42_WIDTH },
19138  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
19139  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_43_WIDTH },
19140  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
19141  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_44_WIDTH },
19142  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
19143  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_45_WIDTH },
19144  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
19145  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_46_WIDTH },
19146  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
19147  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_47_WIDTH },
19148  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
19149  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_48_WIDTH },
19150  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
19151  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_49_WIDTH },
19152  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
19153  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_50_WIDTH },
19154  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
19155  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_51_WIDTH },
19156  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
19157  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_52_WIDTH },
19158  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
19159  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_53_WIDTH },
19160  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
19161  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_54_WIDTH },
19162  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
19163  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_55_WIDTH },
19164  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
19165  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_56_WIDTH },
19166  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
19167  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_57_WIDTH },
19168  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
19169  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_58_WIDTH },
19170  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
19171  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_59_WIDTH },
19172  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
19173  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_60_WIDTH },
19174  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
19175  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_61_WIDTH },
19176  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
19177  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_62_WIDTH },
19178  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
19179  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_63_WIDTH },
19180  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
19181  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_64_WIDTH },
19182  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
19183  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_65_WIDTH },
19184  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
19185  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_66_WIDTH },
19186  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
19187  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_67_WIDTH },
19188  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
19189  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_68_WIDTH },
19190  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
19191  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_69_WIDTH },
19192  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
19193  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_70_WIDTH },
19194  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
19195  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_71_WIDTH },
19196  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
19197  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_72_WIDTH },
19198  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
19199  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_73_WIDTH },
19200  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
19201  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_74_WIDTH },
19202  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
19203  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_75_WIDTH },
19204  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
19205  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_76_WIDTH },
19206  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
19207  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_77_WIDTH },
19208  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
19209  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_78_WIDTH },
19210  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
19211  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_79_WIDTH },
19212  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
19213  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_80_WIDTH },
19214  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
19215  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_81_WIDTH },
19216  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
19217  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_82_WIDTH },
19218  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
19219  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_83_WIDTH },
19220  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
19221  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_84_WIDTH },
19222  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
19223  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_85_WIDTH },
19224  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
19225  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_86_WIDTH },
19226  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
19227  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_87_WIDTH },
19228  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
19229  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_88_WIDTH },
19230  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
19231  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_89_WIDTH },
19232  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
19233  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_90_WIDTH },
19234  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
19235  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_91_WIDTH },
19236  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
19237  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_92_WIDTH },
19238  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
19239  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_93_WIDTH },
19240  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
19241  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_94_WIDTH },
19242  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
19243  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_95_WIDTH },
19244  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
19245  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_96_WIDTH },
19246  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
19247  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_97_WIDTH },
19248  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
19249  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_98_WIDTH },
19250  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
19251  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_99_WIDTH },
19252  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
19253  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_100_WIDTH },
19254  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
19255  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_101_WIDTH },
19256  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
19257  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_102_WIDTH },
19258  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
19259  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_103_WIDTH },
19260  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
19261  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_104_WIDTH },
19262  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
19263  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_105_WIDTH },
19264  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
19265  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_106_WIDTH },
19266  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
19267  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_107_WIDTH },
19268  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
19269  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_108_WIDTH },
19270  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
19271  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_109_WIDTH },
19272  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
19273  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_110_WIDTH },
19274  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
19275  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_111_WIDTH },
19276  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
19277  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_112_WIDTH },
19278  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
19279  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_113_WIDTH },
19280  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
19281  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_114_WIDTH },
19282  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
19283  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_115_WIDTH },
19284  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
19285  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_116_WIDTH },
19286  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
19287  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_117_WIDTH },
19288  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
19289  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_118_WIDTH },
19290  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
19291  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_119_WIDTH },
19292  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
19293  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_120_WIDTH },
19294  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
19295  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_121_WIDTH },
19296  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
19297  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_122_WIDTH },
19298  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
19299  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_123_WIDTH },
19300  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
19301  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_124_WIDTH },
19302  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
19303  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_125_WIDTH },
19304  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
19305  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_126_WIDTH },
19306  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
19307  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_127_WIDTH },
19308  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
19309  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_128_WIDTH },
19310  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
19311  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_129_WIDTH },
19312  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
19313  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_130_WIDTH },
19314  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
19315  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_131_WIDTH },
19316  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
19317  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_132_WIDTH },
19318  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
19319  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_133_WIDTH },
19320  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
19321  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_134_WIDTH },
19322  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
19323  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_135_WIDTH },
19324  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
19325  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_136_WIDTH },
19326  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
19327  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_137_WIDTH },
19328  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
19329  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_138_WIDTH },
19330  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
19331  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_139_WIDTH },
19332  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
19333  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_140_WIDTH },
19334  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
19335  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_141_WIDTH },
19336  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
19337  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_142_WIDTH },
19338  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
19339  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_143_WIDTH },
19340  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
19341  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_144_WIDTH },
19342  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
19343  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_145_WIDTH },
19344  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
19345  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_146_WIDTH },
19346  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
19347  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_147_WIDTH },
19348  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
19349  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_148_WIDTH },
19350  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
19351  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_149_WIDTH },
19352  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
19353  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_150_WIDTH },
19354  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
19355  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_151_WIDTH },
19356  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
19357  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_152_WIDTH },
19358  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
19359  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_153_WIDTH },
19360  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
19361  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_154_WIDTH },
19362  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
19363  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_155_WIDTH },
19364  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
19365  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_156_WIDTH },
19366  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
19367  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_157_WIDTH },
19368  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
19369  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_158_WIDTH },
19370  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
19371  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_159_WIDTH },
19372  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
19373  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_160_WIDTH },
19374  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
19375  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_161_WIDTH },
19376  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
19377  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_162_WIDTH },
19378  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
19379  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_163_WIDTH },
19380  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_164_CHECKER_TYPE,
19381  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_164_WIDTH },
19382  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_165_CHECKER_TYPE,
19383  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_165_WIDTH },
19384  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_166_CHECKER_TYPE,
19385  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_166_WIDTH },
19386  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_167_CHECKER_TYPE,
19387  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_167_WIDTH },
19388  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_168_CHECKER_TYPE,
19389  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_168_WIDTH },
19390  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_169_CHECKER_TYPE,
19391  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_169_WIDTH },
19392  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_170_CHECKER_TYPE,
19393  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_170_WIDTH },
19394  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_171_CHECKER_TYPE,
19395  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_171_WIDTH },
19396  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_172_CHECKER_TYPE,
19397  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_172_WIDTH },
19398  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_173_CHECKER_TYPE,
19399  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_173_WIDTH },
19400  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_174_CHECKER_TYPE,
19401  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_174_WIDTH },
19402  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_175_CHECKER_TYPE,
19403  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_175_WIDTH },
19404  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_176_CHECKER_TYPE,
19405  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_176_WIDTH },
19406  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_177_CHECKER_TYPE,
19407  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_177_WIDTH },
19408  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_178_CHECKER_TYPE,
19409  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_178_WIDTH },
19410  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_179_CHECKER_TYPE,
19411  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_179_WIDTH },
19412  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_180_CHECKER_TYPE,
19413  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_180_WIDTH },
19414  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_181_CHECKER_TYPE,
19415  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_181_WIDTH },
19416  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_182_CHECKER_TYPE,
19417  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_182_WIDTH },
19418  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_183_CHECKER_TYPE,
19419  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_183_WIDTH },
19420  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_184_CHECKER_TYPE,
19421  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_184_WIDTH },
19422  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_185_CHECKER_TYPE,
19423  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_185_WIDTH },
19424  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_186_CHECKER_TYPE,
19425  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_186_WIDTH },
19426  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_187_CHECKER_TYPE,
19427  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_187_WIDTH },
19428  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_188_CHECKER_TYPE,
19429  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_188_WIDTH },
19430  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_189_CHECKER_TYPE,
19431  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_189_WIDTH },
19432  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_190_CHECKER_TYPE,
19433  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_190_WIDTH },
19434  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_191_CHECKER_TYPE,
19435  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_191_WIDTH },
19436  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_192_CHECKER_TYPE,
19437  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_192_WIDTH },
19438  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_193_CHECKER_TYPE,
19439  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_193_WIDTH },
19440  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_194_CHECKER_TYPE,
19441  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_194_WIDTH },
19442  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_195_CHECKER_TYPE,
19443  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_195_WIDTH },
19444  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_196_CHECKER_TYPE,
19445  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_196_WIDTH },
19446  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_197_CHECKER_TYPE,
19447  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_197_WIDTH },
19448  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_198_CHECKER_TYPE,
19449  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_198_WIDTH },
19450  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_199_CHECKER_TYPE,
19451  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_199_WIDTH },
19452  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_200_CHECKER_TYPE,
19453  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_200_WIDTH },
19454  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_201_CHECKER_TYPE,
19455  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_201_WIDTH },
19456  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_202_CHECKER_TYPE,
19457  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_202_WIDTH },
19458  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_203_CHECKER_TYPE,
19459  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_203_WIDTH },
19460  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_204_CHECKER_TYPE,
19461  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_204_WIDTH },
19462  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_205_CHECKER_TYPE,
19463  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_205_WIDTH },
19464  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_206_CHECKER_TYPE,
19465  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_206_WIDTH },
19466  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_207_CHECKER_TYPE,
19467  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_207_WIDTH },
19468  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_208_CHECKER_TYPE,
19469  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_208_WIDTH },
19470  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_209_CHECKER_TYPE,
19471  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_209_WIDTH },
19472  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_210_CHECKER_TYPE,
19473  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_210_WIDTH },
19474  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_211_CHECKER_TYPE,
19475  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_211_WIDTH },
19476  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_212_CHECKER_TYPE,
19477  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_212_WIDTH },
19478  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_213_CHECKER_TYPE,
19479  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_213_WIDTH },
19480  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_214_CHECKER_TYPE,
19481  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_214_WIDTH },
19482  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_215_CHECKER_TYPE,
19483  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_215_WIDTH },
19484  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_216_CHECKER_TYPE,
19485  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_216_WIDTH },
19486  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_217_CHECKER_TYPE,
19487  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_217_WIDTH },
19488  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_218_CHECKER_TYPE,
19489  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_218_WIDTH },
19490  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_219_CHECKER_TYPE,
19491  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_219_WIDTH },
19492  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_220_CHECKER_TYPE,
19493  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_220_WIDTH },
19494  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_221_CHECKER_TYPE,
19495  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_221_WIDTH },
19496  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_222_CHECKER_TYPE,
19497  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_222_WIDTH },
19498  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_223_CHECKER_TYPE,
19499  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_223_WIDTH },
19500  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_224_CHECKER_TYPE,
19501  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_224_WIDTH },
19502  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_225_CHECKER_TYPE,
19503  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_225_WIDTH },
19504  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_226_CHECKER_TYPE,
19505  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_226_WIDTH },
19506  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_227_CHECKER_TYPE,
19507  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_227_WIDTH },
19508  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_228_CHECKER_TYPE,
19509  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_228_WIDTH },
19510  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_229_CHECKER_TYPE,
19511  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_229_WIDTH },
19512  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_230_CHECKER_TYPE,
19513  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_230_WIDTH },
19514  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_231_CHECKER_TYPE,
19515  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_231_WIDTH },
19516  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_232_CHECKER_TYPE,
19517  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_232_WIDTH },
19518  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_233_CHECKER_TYPE,
19519  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_233_WIDTH },
19520  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_234_CHECKER_TYPE,
19521  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_234_WIDTH },
19522  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_235_CHECKER_TYPE,
19523  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_235_WIDTH },
19524  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_236_CHECKER_TYPE,
19525  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_236_WIDTH },
19526  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_237_CHECKER_TYPE,
19527  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_237_WIDTH },
19528  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_238_CHECKER_TYPE,
19529  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_238_WIDTH },
19530  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_239_CHECKER_TYPE,
19531  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_239_WIDTH },
19532  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_240_CHECKER_TYPE,
19533  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_240_WIDTH },
19534  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_241_CHECKER_TYPE,
19535  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_241_WIDTH },
19536  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_242_CHECKER_TYPE,
19537  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_242_WIDTH },
19538  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_243_CHECKER_TYPE,
19539  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_243_WIDTH },
19540  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_244_CHECKER_TYPE,
19541  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_244_WIDTH },
19542  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_245_CHECKER_TYPE,
19543  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_245_WIDTH },
19544  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_246_CHECKER_TYPE,
19545  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_246_WIDTH },
19546  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_247_CHECKER_TYPE,
19547  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_247_WIDTH },
19548  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_248_CHECKER_TYPE,
19549  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_248_WIDTH },
19550  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_249_CHECKER_TYPE,
19551  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_249_WIDTH },
19552  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_250_CHECKER_TYPE,
19553  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_250_WIDTH },
19554  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_251_CHECKER_TYPE,
19555  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_251_WIDTH },
19556  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_252_CHECKER_TYPE,
19557  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_252_WIDTH },
19558  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_253_CHECKER_TYPE,
19559  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_253_WIDTH },
19560  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_254_CHECKER_TYPE,
19561  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_254_WIDTH },
19562  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_255_CHECKER_TYPE,
19563  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_GROUP_255_WIDTH },
19564 };
19565 
19571 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_MAX_NUM_CHECKERS] =
19572 {
19573  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_0_CHECKER_TYPE,
19574  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_0_WIDTH },
19575  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_1_CHECKER_TYPE,
19576  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_1_WIDTH },
19577  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_2_CHECKER_TYPE,
19578  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_2_WIDTH },
19579  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_3_CHECKER_TYPE,
19580  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_3_WIDTH },
19581  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_4_CHECKER_TYPE,
19582  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_4_WIDTH },
19583  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_5_CHECKER_TYPE,
19584  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_5_WIDTH },
19585  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_6_CHECKER_TYPE,
19586  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_6_WIDTH },
19587  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_7_CHECKER_TYPE,
19588  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_7_WIDTH },
19589  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_8_CHECKER_TYPE,
19590  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_8_WIDTH },
19591  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_9_CHECKER_TYPE,
19592  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_9_WIDTH },
19593  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_10_CHECKER_TYPE,
19594  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_10_WIDTH },
19595  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_11_CHECKER_TYPE,
19596  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_11_WIDTH },
19597  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_12_CHECKER_TYPE,
19598  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_12_WIDTH },
19599  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_13_CHECKER_TYPE,
19600  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_13_WIDTH },
19601  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_14_CHECKER_TYPE,
19602  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_14_WIDTH },
19603  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_15_CHECKER_TYPE,
19604  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_15_WIDTH },
19605  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_16_CHECKER_TYPE,
19606  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_16_WIDTH },
19607  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_17_CHECKER_TYPE,
19608  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_17_WIDTH },
19609  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_18_CHECKER_TYPE,
19610  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_18_WIDTH },
19611  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_19_CHECKER_TYPE,
19612  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_19_WIDTH },
19613  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_20_CHECKER_TYPE,
19614  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_20_WIDTH },
19615  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_21_CHECKER_TYPE,
19616  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_21_WIDTH },
19617  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_22_CHECKER_TYPE,
19618  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_22_WIDTH },
19619  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_23_CHECKER_TYPE,
19620  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_23_WIDTH },
19621  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_24_CHECKER_TYPE,
19622  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_24_WIDTH },
19623  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_25_CHECKER_TYPE,
19624  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_25_WIDTH },
19625  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_26_CHECKER_TYPE,
19626  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_26_WIDTH },
19627  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_27_CHECKER_TYPE,
19628  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_27_WIDTH },
19629  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_28_CHECKER_TYPE,
19630  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_28_WIDTH },
19631  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_29_CHECKER_TYPE,
19632  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_29_WIDTH },
19633  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_30_CHECKER_TYPE,
19634  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_30_WIDTH },
19635  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_31_CHECKER_TYPE,
19636  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_31_WIDTH },
19637  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_32_CHECKER_TYPE,
19638  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_32_WIDTH },
19639  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_33_CHECKER_TYPE,
19640  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_33_WIDTH },
19641  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_34_CHECKER_TYPE,
19642  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_34_WIDTH },
19643  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_35_CHECKER_TYPE,
19644  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_35_WIDTH },
19645  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_36_CHECKER_TYPE,
19646  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_36_WIDTH },
19647  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_37_CHECKER_TYPE,
19648  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_37_WIDTH },
19649  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_38_CHECKER_TYPE,
19650  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_38_WIDTH },
19651  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_39_CHECKER_TYPE,
19652  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_39_WIDTH },
19653  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_40_CHECKER_TYPE,
19654  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_40_WIDTH },
19655  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_41_CHECKER_TYPE,
19656  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_41_WIDTH },
19657  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_42_CHECKER_TYPE,
19658  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_42_WIDTH },
19659  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_43_CHECKER_TYPE,
19660  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_43_WIDTH },
19661  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_44_CHECKER_TYPE,
19662  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_44_WIDTH },
19663  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_45_CHECKER_TYPE,
19664  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_45_WIDTH },
19665  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_46_CHECKER_TYPE,
19666  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_46_WIDTH },
19667  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_47_CHECKER_TYPE,
19668  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_47_WIDTH },
19669  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_48_CHECKER_TYPE,
19670  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_48_WIDTH },
19671  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_49_CHECKER_TYPE,
19672  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_49_WIDTH },
19673  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_50_CHECKER_TYPE,
19674  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_50_WIDTH },
19675  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_51_CHECKER_TYPE,
19676  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_51_WIDTH },
19677  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_52_CHECKER_TYPE,
19678  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_52_WIDTH },
19679  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_53_CHECKER_TYPE,
19680  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_53_WIDTH },
19681  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_54_CHECKER_TYPE,
19682  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_54_WIDTH },
19683  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_55_CHECKER_TYPE,
19684  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_55_WIDTH },
19685  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_56_CHECKER_TYPE,
19686  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_56_WIDTH },
19687  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_57_CHECKER_TYPE,
19688  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_57_WIDTH },
19689  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_58_CHECKER_TYPE,
19690  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_58_WIDTH },
19691  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_59_CHECKER_TYPE,
19692  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_59_WIDTH },
19693  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_60_CHECKER_TYPE,
19694  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_60_WIDTH },
19695  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_61_CHECKER_TYPE,
19696  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_61_WIDTH },
19697  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_62_CHECKER_TYPE,
19698  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_62_WIDTH },
19699  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_63_CHECKER_TYPE,
19700  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_63_WIDTH },
19701  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_64_CHECKER_TYPE,
19702  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_64_WIDTH },
19703  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_65_CHECKER_TYPE,
19704  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_65_WIDTH },
19705  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_66_CHECKER_TYPE,
19706  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_66_WIDTH },
19707  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_67_CHECKER_TYPE,
19708  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_67_WIDTH },
19709  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_68_CHECKER_TYPE,
19710  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_68_WIDTH },
19711  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_69_CHECKER_TYPE,
19712  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_69_WIDTH },
19713  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_70_CHECKER_TYPE,
19714  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_70_WIDTH },
19715  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_71_CHECKER_TYPE,
19716  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_71_WIDTH },
19717  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_72_CHECKER_TYPE,
19718  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_72_WIDTH },
19719  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_73_CHECKER_TYPE,
19720  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_73_WIDTH },
19721  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_74_CHECKER_TYPE,
19722  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_74_WIDTH },
19723  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_75_CHECKER_TYPE,
19724  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_75_WIDTH },
19725  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_76_CHECKER_TYPE,
19726  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_76_WIDTH },
19727  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_77_CHECKER_TYPE,
19728  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_77_WIDTH },
19729  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_78_CHECKER_TYPE,
19730  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_78_WIDTH },
19731  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_79_CHECKER_TYPE,
19732  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_79_WIDTH },
19733  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_80_CHECKER_TYPE,
19734  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_80_WIDTH },
19735  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_81_CHECKER_TYPE,
19736  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_81_WIDTH },
19737  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_82_CHECKER_TYPE,
19738  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_82_WIDTH },
19739  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_83_CHECKER_TYPE,
19740  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_83_WIDTH },
19741  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_84_CHECKER_TYPE,
19742  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_84_WIDTH },
19743  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_85_CHECKER_TYPE,
19744  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_85_WIDTH },
19745  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_86_CHECKER_TYPE,
19746  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_86_WIDTH },
19747  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_87_CHECKER_TYPE,
19748  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_87_WIDTH },
19749  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_88_CHECKER_TYPE,
19750  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_88_WIDTH },
19751  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_89_CHECKER_TYPE,
19752  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_89_WIDTH },
19753  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_90_CHECKER_TYPE,
19754  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_90_WIDTH },
19755  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_91_CHECKER_TYPE,
19756  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_91_WIDTH },
19757  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_92_CHECKER_TYPE,
19758  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_92_WIDTH },
19759  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_93_CHECKER_TYPE,
19760  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_93_WIDTH },
19761  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_94_CHECKER_TYPE,
19762  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_94_WIDTH },
19763  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_95_CHECKER_TYPE,
19764  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_95_WIDTH },
19765  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_96_CHECKER_TYPE,
19766  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_96_WIDTH },
19767  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_97_CHECKER_TYPE,
19768  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_97_WIDTH },
19769  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_98_CHECKER_TYPE,
19770  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_98_WIDTH },
19771  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_99_CHECKER_TYPE,
19772  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_99_WIDTH },
19773  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_100_CHECKER_TYPE,
19774  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_100_WIDTH },
19775  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_101_CHECKER_TYPE,
19776  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_101_WIDTH },
19777  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_102_CHECKER_TYPE,
19778  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_102_WIDTH },
19779  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_103_CHECKER_TYPE,
19780  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_103_WIDTH },
19781  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_104_CHECKER_TYPE,
19782  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_104_WIDTH },
19783  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_105_CHECKER_TYPE,
19784  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_105_WIDTH },
19785  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_106_CHECKER_TYPE,
19786  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_106_WIDTH },
19787  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_107_CHECKER_TYPE,
19788  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_107_WIDTH },
19789  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_108_CHECKER_TYPE,
19790  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_108_WIDTH },
19791  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_109_CHECKER_TYPE,
19792  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_109_WIDTH },
19793  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_110_CHECKER_TYPE,
19794  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_110_WIDTH },
19795  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_111_CHECKER_TYPE,
19796  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_111_WIDTH },
19797  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_112_CHECKER_TYPE,
19798  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_112_WIDTH },
19799  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_113_CHECKER_TYPE,
19800  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_113_WIDTH },
19801  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_114_CHECKER_TYPE,
19802  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_114_WIDTH },
19803  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_115_CHECKER_TYPE,
19804  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_115_WIDTH },
19805  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_116_CHECKER_TYPE,
19806  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_116_WIDTH },
19807  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_117_CHECKER_TYPE,
19808  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_117_WIDTH },
19809  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_118_CHECKER_TYPE,
19810  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_118_WIDTH },
19811  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_119_CHECKER_TYPE,
19812  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_119_WIDTH },
19813  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_120_CHECKER_TYPE,
19814  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_120_WIDTH },
19815  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_121_CHECKER_TYPE,
19816  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_121_WIDTH },
19817  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_122_CHECKER_TYPE,
19818  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_122_WIDTH },
19819  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_123_CHECKER_TYPE,
19820  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_123_WIDTH },
19821  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_124_CHECKER_TYPE,
19822  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_124_WIDTH },
19823  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_125_CHECKER_TYPE,
19824  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_125_WIDTH },
19825  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_126_CHECKER_TYPE,
19826  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_126_WIDTH },
19827  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_127_CHECKER_TYPE,
19828  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_127_WIDTH },
19829  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_128_CHECKER_TYPE,
19830  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_128_WIDTH },
19831  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_129_CHECKER_TYPE,
19832  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_129_WIDTH },
19833  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_130_CHECKER_TYPE,
19834  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_130_WIDTH },
19835  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_131_CHECKER_TYPE,
19836  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_131_WIDTH },
19837  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_132_CHECKER_TYPE,
19838  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_132_WIDTH },
19839  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_133_CHECKER_TYPE,
19840  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_133_WIDTH },
19841  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_134_CHECKER_TYPE,
19842  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_134_WIDTH },
19843  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_135_CHECKER_TYPE,
19844  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_135_WIDTH },
19845  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_136_CHECKER_TYPE,
19846  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_136_WIDTH },
19847  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_137_CHECKER_TYPE,
19848  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_137_WIDTH },
19849  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_138_CHECKER_TYPE,
19850  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_138_WIDTH },
19851  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_139_CHECKER_TYPE,
19852  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_139_WIDTH },
19853  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_140_CHECKER_TYPE,
19854  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_140_WIDTH },
19855  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_141_CHECKER_TYPE,
19856  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_141_WIDTH },
19857  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_142_CHECKER_TYPE,
19858  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_142_WIDTH },
19859  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_143_CHECKER_TYPE,
19860  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_143_WIDTH },
19861  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_144_CHECKER_TYPE,
19862  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_144_WIDTH },
19863  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_145_CHECKER_TYPE,
19864  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_145_WIDTH },
19865  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_146_CHECKER_TYPE,
19866  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_146_WIDTH },
19867  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_147_CHECKER_TYPE,
19868  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_147_WIDTH },
19869  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_148_CHECKER_TYPE,
19870  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_148_WIDTH },
19871  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_149_CHECKER_TYPE,
19872  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_149_WIDTH },
19873  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_150_CHECKER_TYPE,
19874  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_150_WIDTH },
19875  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_151_CHECKER_TYPE,
19876  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_151_WIDTH },
19877  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_152_CHECKER_TYPE,
19878  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_152_WIDTH },
19879  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_153_CHECKER_TYPE,
19880  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_153_WIDTH },
19881  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_154_CHECKER_TYPE,
19882  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_154_WIDTH },
19883  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_155_CHECKER_TYPE,
19884  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_155_WIDTH },
19885  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_156_CHECKER_TYPE,
19886  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_156_WIDTH },
19887  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_157_CHECKER_TYPE,
19888  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_157_WIDTH },
19889  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_158_CHECKER_TYPE,
19890  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_158_WIDTH },
19891  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_159_CHECKER_TYPE,
19892  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_159_WIDTH },
19893  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_160_CHECKER_TYPE,
19894  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_160_WIDTH },
19895  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_161_CHECKER_TYPE,
19896  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_161_WIDTH },
19897  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_162_CHECKER_TYPE,
19898  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_162_WIDTH },
19899  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_163_CHECKER_TYPE,
19900  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_163_WIDTH },
19901  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_164_CHECKER_TYPE,
19902  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_164_WIDTH },
19903  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_165_CHECKER_TYPE,
19904  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_165_WIDTH },
19905  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_166_CHECKER_TYPE,
19906  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_166_WIDTH },
19907  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_167_CHECKER_TYPE,
19908  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_167_WIDTH },
19909  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_168_CHECKER_TYPE,
19910  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_168_WIDTH },
19911  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_169_CHECKER_TYPE,
19912  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_169_WIDTH },
19913  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_170_CHECKER_TYPE,
19914  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_170_WIDTH },
19915  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_171_CHECKER_TYPE,
19916  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_171_WIDTH },
19917  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_172_CHECKER_TYPE,
19918  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_172_WIDTH },
19919  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_173_CHECKER_TYPE,
19920  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_173_WIDTH },
19921  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_174_CHECKER_TYPE,
19922  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_174_WIDTH },
19923  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_175_CHECKER_TYPE,
19924  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_175_WIDTH },
19925  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_176_CHECKER_TYPE,
19926  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_176_WIDTH },
19927  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_177_CHECKER_TYPE,
19928  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_177_WIDTH },
19929  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_178_CHECKER_TYPE,
19930  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_178_WIDTH },
19931  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_179_CHECKER_TYPE,
19932  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_179_WIDTH },
19933  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_180_CHECKER_TYPE,
19934  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_180_WIDTH },
19935  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_181_CHECKER_TYPE,
19936  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_181_WIDTH },
19937  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_182_CHECKER_TYPE,
19938  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_182_WIDTH },
19939  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_183_CHECKER_TYPE,
19940  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_183_WIDTH },
19941  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_184_CHECKER_TYPE,
19942  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_184_WIDTH },
19943  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_185_CHECKER_TYPE,
19944  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_185_WIDTH },
19945  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_186_CHECKER_TYPE,
19946  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_186_WIDTH },
19947  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_187_CHECKER_TYPE,
19948  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_187_WIDTH },
19949  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_188_CHECKER_TYPE,
19950  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_188_WIDTH },
19951  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_189_CHECKER_TYPE,
19952  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_189_WIDTH },
19953  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_190_CHECKER_TYPE,
19954  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_190_WIDTH },
19955  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_191_CHECKER_TYPE,
19956  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_191_WIDTH },
19957  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_192_CHECKER_TYPE,
19958  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_192_WIDTH },
19959  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_193_CHECKER_TYPE,
19960  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_193_WIDTH },
19961  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_194_CHECKER_TYPE,
19962  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_194_WIDTH },
19963  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_195_CHECKER_TYPE,
19964  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_195_WIDTH },
19965  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_196_CHECKER_TYPE,
19966  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_196_WIDTH },
19967  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_197_CHECKER_TYPE,
19968  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_197_WIDTH },
19969  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_198_CHECKER_TYPE,
19970  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_198_WIDTH },
19971  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_199_CHECKER_TYPE,
19972  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_199_WIDTH },
19973  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_200_CHECKER_TYPE,
19974  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_200_WIDTH },
19975  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_201_CHECKER_TYPE,
19976  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_201_WIDTH },
19977  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_202_CHECKER_TYPE,
19978  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_202_WIDTH },
19979  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_203_CHECKER_TYPE,
19980  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_203_WIDTH },
19981  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_204_CHECKER_TYPE,
19982  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_204_WIDTH },
19983  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_205_CHECKER_TYPE,
19984  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_205_WIDTH },
19985  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_206_CHECKER_TYPE,
19986  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_206_WIDTH },
19987  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_207_CHECKER_TYPE,
19988  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_207_WIDTH },
19989  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_208_CHECKER_TYPE,
19990  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_208_WIDTH },
19991  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_209_CHECKER_TYPE,
19992  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_209_WIDTH },
19993  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_210_CHECKER_TYPE,
19994  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_210_WIDTH },
19995  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_211_CHECKER_TYPE,
19996  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_211_WIDTH },
19997  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_212_CHECKER_TYPE,
19998  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_212_WIDTH },
19999  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_213_CHECKER_TYPE,
20000  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_213_WIDTH },
20001  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_214_CHECKER_TYPE,
20002  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_214_WIDTH },
20003  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_215_CHECKER_TYPE,
20004  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_GROUP_215_WIDTH },
20005 };
20006 
20012 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20013 {
20014  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20015  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_0_WIDTH },
20016  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20017  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_1_WIDTH },
20018  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20019  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_2_WIDTH },
20020  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20021  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_3_WIDTH },
20022  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20023  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_4_WIDTH },
20024  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20025  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_5_WIDTH },
20026  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20027  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_6_WIDTH },
20028  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20029  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_7_WIDTH },
20030  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20031  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_8_WIDTH },
20032  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20033  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_9_WIDTH },
20034  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20035  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_10_WIDTH },
20036  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20037  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_11_WIDTH },
20038  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20039  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_12_WIDTH },
20040  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20041  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_13_WIDTH },
20042  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20043  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_14_WIDTH },
20044  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
20045  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_15_WIDTH },
20046  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
20047  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_16_WIDTH },
20048  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
20049  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_17_WIDTH },
20050  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
20051  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_18_WIDTH },
20052  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
20053  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_19_WIDTH },
20054  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
20055  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_20_WIDTH },
20056  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
20057  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_21_WIDTH },
20058  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
20059  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_22_WIDTH },
20060  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
20061  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_23_WIDTH },
20062  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
20063  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_24_WIDTH },
20064  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
20065  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_25_WIDTH },
20066  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
20067  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_26_WIDTH },
20068  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
20069  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_27_WIDTH },
20070  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
20071  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_28_WIDTH },
20072  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
20073  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_29_WIDTH },
20074  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
20075  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_30_WIDTH },
20076  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
20077  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_31_WIDTH },
20078  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
20079  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_32_WIDTH },
20080  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
20081  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_33_WIDTH },
20082  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
20083  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_34_WIDTH },
20084  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
20085  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_35_WIDTH },
20086  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
20087  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_36_WIDTH },
20088  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
20089  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_37_WIDTH },
20090  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
20091  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_GROUP_38_WIDTH },
20092 };
20093 
20099 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20100 {
20101  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20102  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_0_WIDTH },
20103  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20104  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_1_WIDTH },
20105  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20106  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_2_WIDTH },
20107  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20108  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_3_WIDTH },
20109  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20110  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_4_WIDTH },
20111  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20112  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_5_WIDTH },
20113  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20114  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_6_WIDTH },
20115  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20116  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_7_WIDTH },
20117  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20118  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_8_WIDTH },
20119  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20120  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_9_WIDTH },
20121  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20122  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_10_WIDTH },
20123  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20124  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_11_WIDTH },
20125  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20126  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_12_WIDTH },
20127  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20128  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_13_WIDTH },
20129  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20130  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_14_WIDTH },
20131  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
20132  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_15_WIDTH },
20133  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
20134  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_16_WIDTH },
20135  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
20136  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_17_WIDTH },
20137  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
20138  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_18_WIDTH },
20139  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
20140  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_19_WIDTH },
20141  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
20142  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_20_WIDTH },
20143  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
20144  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_21_WIDTH },
20145  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
20146  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_22_WIDTH },
20147  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
20148  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_23_WIDTH },
20149  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
20150  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_24_WIDTH },
20151  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
20152  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_25_WIDTH },
20153  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
20154  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_26_WIDTH },
20155  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
20156  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_27_WIDTH },
20157  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
20158  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_28_WIDTH },
20159  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
20160  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_29_WIDTH },
20161  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
20162  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_30_WIDTH },
20163  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
20164  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_31_WIDTH },
20165  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
20166  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_32_WIDTH },
20167  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
20168  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_33_WIDTH },
20169  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
20170  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_34_WIDTH },
20171  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
20172  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_35_WIDTH },
20173  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
20174  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_36_WIDTH },
20175  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
20176  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_37_WIDTH },
20177  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
20178  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_GROUP_38_WIDTH },
20179 };
20180 
20186 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20187 {
20188  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20189  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_0_WIDTH },
20190  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20191  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_1_WIDTH },
20192  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20193  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_2_WIDTH },
20194  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20195  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_3_WIDTH },
20196  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20197  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_4_WIDTH },
20198  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20199  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_5_WIDTH },
20200  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20201  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_6_WIDTH },
20202  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20203  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_7_WIDTH },
20204  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20205  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_8_WIDTH },
20206  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20207  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_9_WIDTH },
20208  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20209  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_10_WIDTH },
20210  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20211  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_GROUP_11_WIDTH },
20212 };
20213 
20219 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20220 {
20221  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20222  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_0_WIDTH },
20223  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20224  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_1_WIDTH },
20225  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20226  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_2_WIDTH },
20227  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20228  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_3_WIDTH },
20229  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20230  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_4_WIDTH },
20231  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20232  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_5_WIDTH },
20233  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20234  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_6_WIDTH },
20235  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20236  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_7_WIDTH },
20237  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20238  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_8_WIDTH },
20239  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20240  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_9_WIDTH },
20241  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20242  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_10_WIDTH },
20243  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20244  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_GROUP_11_WIDTH },
20245 };
20246 
20252 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20253 {
20254  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20255  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
20256  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20257  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
20258  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20259  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
20260  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20261  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
20262  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20263  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
20264  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20265  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
20266  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20267  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
20268  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20269  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
20270  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20271  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
20272  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20273  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
20274  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20275  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
20276  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20277  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
20278  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20279  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
20280  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20281  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
20282  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20283  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
20284  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
20285  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
20286  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
20287  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
20288  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
20289  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
20290  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
20291  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
20292  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
20293  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
20294  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
20295  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
20296  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
20297  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
20298  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
20299  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
20300  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
20301  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
20302  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
20303  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
20304  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
20305  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
20306  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
20307  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
20308  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
20309  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
20310  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
20311  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
20312  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
20313  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
20314  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
20315  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
20316  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
20317  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
20318  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
20319  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
20320  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
20321  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
20322  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
20323  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
20324  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
20325  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
20326  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
20327  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
20328  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
20329  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
20330  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
20331  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
20332  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
20333  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
20334  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
20335  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
20336 };
20337 
20343 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20344 {
20345  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20346  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_0_WIDTH },
20347  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20348  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_1_WIDTH },
20349  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20350  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_2_WIDTH },
20351  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20352  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_3_WIDTH },
20353  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20354  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_4_WIDTH },
20355  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20356  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_5_WIDTH },
20357  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20358  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_6_WIDTH },
20359  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20360  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_7_WIDTH },
20361  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20362  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_8_WIDTH },
20363  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20364  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_9_WIDTH },
20365  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20366  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_10_WIDTH },
20367  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20368  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_11_WIDTH },
20369  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20370  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_12_WIDTH },
20371  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20372  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_13_WIDTH },
20373  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20374  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_14_WIDTH },
20375  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
20376  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_15_WIDTH },
20377  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
20378  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_16_WIDTH },
20379  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
20380  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_17_WIDTH },
20381  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
20382  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_18_WIDTH },
20383  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
20384  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_19_WIDTH },
20385  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
20386  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_20_WIDTH },
20387  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
20388  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_21_WIDTH },
20389  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
20390  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_22_WIDTH },
20391  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
20392  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_23_WIDTH },
20393  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
20394  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_24_WIDTH },
20395  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
20396  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_25_WIDTH },
20397  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
20398  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_26_WIDTH },
20399  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
20400  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_27_WIDTH },
20401  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
20402  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_28_WIDTH },
20403  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
20404  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_29_WIDTH },
20405  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
20406  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_30_WIDTH },
20407  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
20408  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_31_WIDTH },
20409  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
20410  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_32_WIDTH },
20411  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
20412  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_33_WIDTH },
20413  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
20414  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_34_WIDTH },
20415  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
20416  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_35_WIDTH },
20417  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
20418  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_36_WIDTH },
20419  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
20420  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_37_WIDTH },
20421  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
20422  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_38_WIDTH },
20423  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
20424  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_39_WIDTH },
20425  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
20426  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_40_WIDTH },
20427  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
20428  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_41_WIDTH },
20429  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
20430  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_42_WIDTH },
20431  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
20432  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_43_WIDTH },
20433  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
20434  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_44_WIDTH },
20435  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
20436  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_45_WIDTH },
20437  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
20438  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_46_WIDTH },
20439  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
20440  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_47_WIDTH },
20441  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
20442  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_48_WIDTH },
20443  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
20444  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_49_WIDTH },
20445  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
20446  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_50_WIDTH },
20447  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
20448  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_51_WIDTH },
20449  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
20450  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_52_WIDTH },
20451  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
20452  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_53_WIDTH },
20453  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
20454  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_54_WIDTH },
20455  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
20456  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_55_WIDTH },
20457  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
20458  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_56_WIDTH },
20459  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
20460  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_57_WIDTH },
20461  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
20462  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_58_WIDTH },
20463  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
20464  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_59_WIDTH },
20465  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
20466  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_60_WIDTH },
20467  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
20468  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_61_WIDTH },
20469  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
20470  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_62_WIDTH },
20471  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
20472  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_63_WIDTH },
20473  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
20474  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_64_WIDTH },
20475  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
20476  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_65_WIDTH },
20477  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
20478  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_66_WIDTH },
20479  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
20480  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_67_WIDTH },
20481  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
20482  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_68_WIDTH },
20483  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
20484  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_69_WIDTH },
20485  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
20486  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_70_WIDTH },
20487  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
20488  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_71_WIDTH },
20489  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
20490  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_72_WIDTH },
20491  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
20492  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_73_WIDTH },
20493  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
20494  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_74_WIDTH },
20495  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
20496  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_75_WIDTH },
20497  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
20498  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_76_WIDTH },
20499  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
20500  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_77_WIDTH },
20501  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
20502  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_78_WIDTH },
20503  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
20504  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_79_WIDTH },
20505  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
20506  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_80_WIDTH },
20507  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
20508  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_81_WIDTH },
20509  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
20510  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_82_WIDTH },
20511  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
20512  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_83_WIDTH },
20513  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
20514  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_84_WIDTH },
20515  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
20516  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_85_WIDTH },
20517  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
20518  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_86_WIDTH },
20519  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
20520  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_87_WIDTH },
20521  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
20522  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_88_WIDTH },
20523  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
20524  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_89_WIDTH },
20525  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
20526  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_90_WIDTH },
20527  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
20528  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_91_WIDTH },
20529  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
20530  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_92_WIDTH },
20531  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
20532  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_93_WIDTH },
20533  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
20534  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_94_WIDTH },
20535  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
20536  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_95_WIDTH },
20537  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
20538  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_96_WIDTH },
20539  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
20540  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_97_WIDTH },
20541  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
20542  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_98_WIDTH },
20543  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
20544  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_99_WIDTH },
20545  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
20546  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_100_WIDTH },
20547  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
20548  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_GROUP_101_WIDTH },
20549 };
20550 
20556 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20557 {
20558  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20559  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_0_WIDTH },
20560  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20561  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_1_WIDTH },
20562  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20563  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_2_WIDTH },
20564  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20565  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_3_WIDTH },
20566  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20567  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_4_WIDTH },
20568  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20569  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_5_WIDTH },
20570  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20571  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_6_WIDTH },
20572  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20573  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_7_WIDTH },
20574  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20575  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_8_WIDTH },
20576  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20577  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_9_WIDTH },
20578  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20579  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_10_WIDTH },
20580  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20581  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_11_WIDTH },
20582  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20583  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_12_WIDTH },
20584  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20585  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_13_WIDTH },
20586  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20587  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_14_WIDTH },
20588  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
20589  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_15_WIDTH },
20590  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
20591  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_16_WIDTH },
20592  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
20593  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_17_WIDTH },
20594  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
20595  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_18_WIDTH },
20596  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
20597  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_19_WIDTH },
20598  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
20599  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_20_WIDTH },
20600  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
20601  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_21_WIDTH },
20602  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
20603  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_22_WIDTH },
20604  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
20605  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_23_WIDTH },
20606  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
20607  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_24_WIDTH },
20608  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
20609  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_25_WIDTH },
20610  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
20611  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_26_WIDTH },
20612  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
20613  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_27_WIDTH },
20614  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
20615  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_28_WIDTH },
20616  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
20617  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_29_WIDTH },
20618  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
20619  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_30_WIDTH },
20620  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
20621  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_31_WIDTH },
20622  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
20623  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_32_WIDTH },
20624  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
20625  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_33_WIDTH },
20626  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
20627  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_34_WIDTH },
20628  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
20629  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_35_WIDTH },
20630  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
20631  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_36_WIDTH },
20632  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
20633  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_37_WIDTH },
20634  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
20635  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_38_WIDTH },
20636  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
20637  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_39_WIDTH },
20638  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
20639  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_40_WIDTH },
20640  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
20641  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_41_WIDTH },
20642  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
20643  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_42_WIDTH },
20644  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
20645  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_43_WIDTH },
20646  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
20647  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_44_WIDTH },
20648  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
20649  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_45_WIDTH },
20650  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
20651  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_46_WIDTH },
20652  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
20653  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_47_WIDTH },
20654  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
20655  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_48_WIDTH },
20656  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
20657  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_49_WIDTH },
20658  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
20659  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_50_WIDTH },
20660  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
20661  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_51_WIDTH },
20662  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
20663  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_52_WIDTH },
20664  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
20665  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_53_WIDTH },
20666  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
20667  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_54_WIDTH },
20668  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
20669  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_55_WIDTH },
20670  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
20671  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_56_WIDTH },
20672  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
20673  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_57_WIDTH },
20674  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
20675  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_58_WIDTH },
20676  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
20677  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_59_WIDTH },
20678  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
20679  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_60_WIDTH },
20680  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
20681  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_61_WIDTH },
20682  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
20683  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_62_WIDTH },
20684  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
20685  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_63_WIDTH },
20686  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
20687  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_64_WIDTH },
20688  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
20689  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_65_WIDTH },
20690  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
20691  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_66_WIDTH },
20692  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
20693  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_67_WIDTH },
20694  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
20695  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_68_WIDTH },
20696  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
20697  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_69_WIDTH },
20698  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
20699  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_70_WIDTH },
20700  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
20701  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_71_WIDTH },
20702  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
20703  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_72_WIDTH },
20704  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
20705  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_73_WIDTH },
20706  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
20707  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_74_WIDTH },
20708  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
20709  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_75_WIDTH },
20710  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
20711  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_76_WIDTH },
20712  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
20713  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_77_WIDTH },
20714  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
20715  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_78_WIDTH },
20716  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
20717  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_79_WIDTH },
20718  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
20719  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_80_WIDTH },
20720  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
20721  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_81_WIDTH },
20722  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
20723  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_82_WIDTH },
20724  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
20725  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_83_WIDTH },
20726  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
20727  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_84_WIDTH },
20728 };
20729 
20735 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20736 {
20737  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20738  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
20739  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20740  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
20741  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20742  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
20743  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20744  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
20745 };
20746 
20752 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20753 {
20754  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20755  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
20756  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20757  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
20758  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20759  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
20760  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20761  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
20762 };
20763 
20769 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20770 {
20771  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20772  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
20773  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20774  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
20775  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20776  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
20777  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20778  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
20779  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20780  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
20781  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20782  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
20783  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20784  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
20785  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20786  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
20787  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20788  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
20789  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20790  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
20791  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20792  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
20793  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20794  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
20795  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20796  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
20797  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20798  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
20799  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20800  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
20801 };
20802 
20808 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20809 {
20810  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20811  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
20812  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20813  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
20814  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20815  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
20816  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20817  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
20818  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20819  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_4_WIDTH },
20820  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20821  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_5_WIDTH },
20822  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20823  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_6_WIDTH },
20824  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20825  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_7_WIDTH },
20826  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20827  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_8_WIDTH },
20828  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20829  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_9_WIDTH },
20830  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20831  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_10_WIDTH },
20832  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20833  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_11_WIDTH },
20834  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20835  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_12_WIDTH },
20836  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20837  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_13_WIDTH },
20838 };
20839 
20845 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20846 {
20847  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20848  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
20849  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20850  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
20851  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20852  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
20853  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20854  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
20855  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20856  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
20857  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20858  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
20859  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20860  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
20861  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20862  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
20863  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20864  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
20865  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20866  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
20867  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20868  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
20869  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20870  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
20871  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20872  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
20873  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20874  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
20875  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20876  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
20877  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
20878  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
20879  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
20880  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
20881  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
20882  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
20883  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
20884  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
20885  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
20886  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
20887  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
20888  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
20889  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
20890  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
20891  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
20892  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
20893  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
20894  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
20895  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
20896  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
20897  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
20898  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
20899  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
20900  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
20901  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
20902  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
20903  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
20904  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
20905  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
20906  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
20907  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
20908  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
20909  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
20910  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
20911  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
20912  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
20913  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
20914  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
20915  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
20916  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
20917  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
20918  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
20919  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
20920  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
20921  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
20922  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
20923  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
20924  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
20925  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
20926  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
20927  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
20928  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
20929 };
20930 
20936 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
20937 {
20938  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
20939  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
20940  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
20941  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
20942  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
20943  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
20944  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
20945  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
20946  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
20947  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
20948  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
20949  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
20950  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
20951  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
20952  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
20953  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
20954  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
20955  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
20956  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
20957  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
20958  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
20959  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
20960  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
20961  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
20962  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
20963  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
20964  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
20965  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
20966  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
20967  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
20968  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
20969  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
20970  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
20971  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
20972  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
20973  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
20974  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
20975  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
20976  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
20977  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
20978  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
20979  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
20980  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
20981  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
20982  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
20983  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
20984  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
20985  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
20986  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
20987  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
20988  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
20989  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
20990  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
20991  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
20992  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
20993  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
20994  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
20995  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
20996  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
20997  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
20998  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
20999  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
21000  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
21001  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
21002  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
21003  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
21004  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
21005  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
21006  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
21007  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
21008  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
21009  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
21010  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
21011  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
21012  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
21013  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
21014  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
21015  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
21016  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
21017  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
21018  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
21019  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
21020 };
21021 
21027 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21028 {
21029  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21030  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
21031  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21032  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
21033  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21034  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
21035  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21036  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
21037  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21038  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
21039  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21040  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
21041  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21042  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
21043  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21044  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
21045  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21046  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
21047  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21048  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
21049  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21050  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
21051  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21052  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
21053  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
21054  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
21055  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
21056  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
21057  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
21058  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
21059  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
21060  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
21061  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
21062  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
21063  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
21064  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
21065  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
21066  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
21067  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
21068  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
21069  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
21070  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
21071  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
21072  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
21073  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
21074  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
21075  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
21076  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
21077  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
21078  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
21079  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
21080  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
21081  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
21082  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
21083  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
21084  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
21085  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
21086  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
21087  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
21088  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
21089  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
21090  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
21091  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
21092  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
21093  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
21094  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
21095  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
21096  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
21097  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
21098  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
21099  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
21100  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
21101  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
21102  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
21103  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
21104  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
21105  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
21106  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
21107  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
21108  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
21109  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
21110  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
21111 };
21112 
21118 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21119 {
21120  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21121  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
21122  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21123  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
21124  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21125  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
21126  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21127  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
21128  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21129  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
21130  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21131  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
21132  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21133  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
21134  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21135  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
21136  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21137  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
21138  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21139  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
21140  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21141  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
21142  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21143  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
21144  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
21145  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
21146  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
21147  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
21148  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
21149  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
21150  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
21151  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
21152  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
21153  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
21154  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
21155  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
21156  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
21157  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
21158  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
21159  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
21160  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
21161  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
21162  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
21163  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
21164  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
21165  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
21166  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
21167  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
21168  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
21169  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
21170  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
21171  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
21172  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
21173  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
21174  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
21175  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
21176  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
21177  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
21178  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
21179  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
21180  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
21181  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
21182  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
21183  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
21184  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
21185  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
21186  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
21187  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
21188  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
21189  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
21190  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
21191  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
21192  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
21193  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
21194  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
21195  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
21196  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
21197  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
21198  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
21199  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
21200  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
21201  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
21202 };
21203 
21209 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21210 {
21211  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21212  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
21213  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21214  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
21215  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21216  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
21217  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21218  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
21219  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21220  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
21221  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21222  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
21223  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21224  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
21225  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21226  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
21227  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21228  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
21229  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21230  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
21231  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21232  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
21233  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21234  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
21235  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
21236  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
21237  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
21238  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
21239  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
21240  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
21241  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
21242  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
21243  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
21244  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
21245  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
21246  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
21247  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
21248  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
21249  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
21250  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
21251  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
21252  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
21253  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
21254  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
21255  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
21256  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
21257  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
21258  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
21259  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
21260  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
21261  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
21262  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
21263  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
21264  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
21265  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
21266  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
21267  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
21268  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
21269  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
21270  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
21271  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
21272  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
21273  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
21274  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
21275  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
21276  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
21277  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
21278  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
21279  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
21280  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
21281  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
21282  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
21283  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
21284  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
21285  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
21286  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
21287  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
21288  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
21289  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
21290  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
21291  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
21292  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
21293 };
21294 
21300 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21301 {
21302  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21303  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
21304  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21305  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
21306  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21307  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
21308  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21309  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
21310  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21311  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
21312  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21313  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
21314  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21315  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
21316  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21317  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
21318  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21319  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
21320  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21321  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
21322  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21323  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
21324  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21325  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
21326  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
21327  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
21328  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
21329  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
21330  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
21331  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
21332  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
21333  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
21334  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
21335  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
21336  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
21337  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
21338  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
21339  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
21340  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
21341  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
21342  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
21343  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
21344  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
21345  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
21346  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
21347  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
21348  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
21349  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
21350  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
21351  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
21352  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
21353  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
21354  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
21355  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
21356  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
21357  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
21358  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
21359  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
21360  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
21361  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
21362  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
21363  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
21364  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
21365  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
21366  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
21367  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
21368  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
21369  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
21370  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
21371  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
21372  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
21373  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
21374  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
21375  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
21376  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
21377  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
21378  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
21379  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
21380  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
21381  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
21382  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
21383  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
21384 };
21385 
21391 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21392 {
21393  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21394  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
21395  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21396  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
21397  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21398  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
21399  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21400  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
21401  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21402  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
21403  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21404  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
21405  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21406  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
21407  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21408  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
21409  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21410  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
21411  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21412  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
21413  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21414  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
21415  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21416  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
21417  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
21418  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
21419  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
21420  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
21421  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
21422  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
21423  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
21424  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
21425  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
21426  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
21427  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
21428  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
21429  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
21430  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
21431  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
21432  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
21433  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
21434  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
21435  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
21436  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
21437  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
21438  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
21439  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
21440  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
21441  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
21442  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
21443  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
21444  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
21445  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
21446  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
21447  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
21448  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
21449  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
21450  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
21451  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
21452  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
21453  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
21454  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
21455  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
21456  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
21457  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
21458  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
21459  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
21460  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
21461  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
21462  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
21463  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
21464  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
21465  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
21466  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
21467  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
21468  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
21469  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
21470  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
21471  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
21472  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
21473  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
21474  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
21475 };
21476 
21482 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21483 {
21484  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21485  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21486  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21487  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21488  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21489  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21490 };
21491 
21497 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21498 {
21499  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21500  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21501  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21502  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21503  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21504  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21505 };
21506 
21512 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21513 {
21514  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21515  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21516  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21517  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21518  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21519  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21520 };
21521 
21527 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21528 {
21529  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21530  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
21531  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21532  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
21533  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21534  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
21535  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21536  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
21537  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21538  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
21539  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21540  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
21541  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21542  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
21543 };
21544 
21550 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21551 {
21552  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21553  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21554  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21555  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21556  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21557  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21558 };
21559 
21565 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21566 {
21567  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21568  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21569  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21570  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21571  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21572  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21573 };
21574 
21580 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21581 {
21582  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21583  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
21584  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21585  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
21586  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21587  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
21588  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21589  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
21590  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21591  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
21592  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21593  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
21594  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21595  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
21596 };
21597 
21603 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21604 {
21605  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21606  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21607  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21608  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21609  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21610  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21611 };
21612 
21618 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21619 {
21620  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21621  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21622  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21623  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21624  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21625  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21626 };
21627 
21633 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21634 {
21635  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21636  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
21637  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21638  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
21639  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21640  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
21641  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21642  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
21643  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21644  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
21645  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21646  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
21647  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21648  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
21649 };
21650 
21656 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21657 {
21658  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21659  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21660  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21661  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21662  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21663  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21664 };
21665 
21671 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21672 {
21673  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21674  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
21675  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21676  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
21677  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21678  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
21679  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21680  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
21681  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21682  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
21683  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21684  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
21685  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21686  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
21687 };
21688 
21694 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21695 {
21696  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21697  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21698  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21699  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21700  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21701  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21702 };
21703 
21709 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21710 {
21711  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21712  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
21713  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21714  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
21715  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21716  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
21717  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21718  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
21719  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21720  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
21721  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21722  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
21723  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21724  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
21725 };
21726 
21732 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21733 {
21734  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21735  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21736  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21737  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21738  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21739  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21740 };
21741 
21747 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21748 {
21749  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21750  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
21751  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21752  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
21753  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21754  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
21755  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21756  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
21757  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21758  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
21759  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21760  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
21761  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21762  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
21763 };
21764 
21770 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21771 {
21772  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21773  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21774  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21775  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21776  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21777  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21778 };
21779 
21785 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21786 {
21787  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21788  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
21789  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21790  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
21791  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21792  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
21793  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21794  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
21795  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21796  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
21797  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21798  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
21799  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21800  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
21801 };
21802 
21808 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21809 {
21810  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21811  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21812  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21813  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21814  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21815  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21816 };
21817 
21823 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21824 {
21825  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21826  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21827  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21828  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21829  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21830  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21831 };
21832 
21838 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21839 {
21840  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21841  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
21842  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21843  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
21844  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21845  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
21846 };
21847 
21853 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21854 {
21855  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21856  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
21857  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21858  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
21859  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21860  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
21861  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21862  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
21863  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21864  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
21865  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21866  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
21867  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21868  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
21869  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21870  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
21871  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21872  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
21873  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21874  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
21875  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21876  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
21877  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21878  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
21879 };
21880 
21886 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21887 {
21888  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21889  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
21890  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21891  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
21892  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21893  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
21894  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21895  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
21896  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21897  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
21898  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21899  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
21900  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21901  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
21902  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21903  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
21904  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21905  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
21906  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21907  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
21908  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21909  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
21910  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21911  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
21912 };
21913 
21919 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
21920 {
21921  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
21922  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
21923  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
21924  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
21925  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
21926  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
21927  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
21928  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
21929  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
21930  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
21931  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
21932  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
21933  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
21934  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
21935  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
21936  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
21937  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
21938  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
21939  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
21940  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
21941  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
21942  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
21943  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
21944  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
21945  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
21946  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
21947  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
21948  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
21949  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
21950  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
21951  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
21952  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
21953  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
21954  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
21955  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
21956  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
21957  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
21958  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
21959  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
21960  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
21961  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
21962  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
21963  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
21964  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
21965  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
21966  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
21967  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
21968  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
21969  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
21970  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
21971  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
21972  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
21973  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
21974  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
21975  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
21976  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
21977  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
21978  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
21979  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
21980  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
21981  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
21982  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
21983  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
21984  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
21985  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
21986  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
21987  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
21988  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
21989  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
21990  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
21991  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
21992  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
21993  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
21994  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
21995  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
21996  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
21997  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
21998  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
21999  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22000  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
22001  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22002  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
22003 };
22004 
22010 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22011 {
22012  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22013  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
22014  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22015  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
22016  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22017  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
22018  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
22019  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
22020  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
22021  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
22022  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
22023  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
22024  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
22025  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
22026  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
22027  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
22028  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
22029  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
22030  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
22031  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
22032  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
22033  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
22034  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
22035  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
22036  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
22037  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
22038  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
22039  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
22040  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
22041  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
22042  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
22043  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
22044  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
22045  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
22046  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
22047  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
22048  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
22049  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
22050  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
22051  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
22052  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
22053  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
22054  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
22055  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
22056  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
22057  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
22058  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
22059  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
22060  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
22061  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
22062  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
22063  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
22064  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
22065  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
22066  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
22067  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
22068  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
22069  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
22070  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
22071  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
22072  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
22073  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
22074  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
22075  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
22076  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
22077  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
22078  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
22079  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
22080  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
22081  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
22082  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
22083  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
22084  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
22085  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
22086  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
22087  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
22088  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
22089  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
22090  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22091  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
22092  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22093  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
22094 };
22095 
22101 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22102 {
22103  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22104  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
22105  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22106  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
22107  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22108  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
22109  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
22110  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
22111  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
22112  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
22113  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
22114  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
22115  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
22116  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
22117  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
22118  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
22119  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
22120  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
22121  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
22122  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
22123  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
22124  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
22125  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
22126  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
22127  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
22128  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
22129  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
22130  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
22131  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
22132  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
22133  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
22134  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
22135  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
22136  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
22137  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
22138  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
22139  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
22140  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
22141  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
22142  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
22143  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
22144  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
22145  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
22146  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
22147  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
22148  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
22149  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
22150  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
22151  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
22152  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
22153  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
22154  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
22155  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
22156  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
22157  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
22158  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
22159  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
22160  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
22161  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
22162  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
22163  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
22164  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
22165  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
22166  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
22167  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
22168  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
22169  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
22170  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
22171  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
22172  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
22173  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
22174  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
22175  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
22176  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
22177  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
22178  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
22179  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
22180  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
22181  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22182  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
22183  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22184  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
22185 };
22186 
22192 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22193 {
22194  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22195  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
22196  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22197  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
22198  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22199  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
22200  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
22201  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
22202  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
22203  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
22204  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
22205  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
22206  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
22207  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
22208  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
22209  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
22210  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
22211  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
22212  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
22213  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
22214  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
22215  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
22216  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
22217  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
22218  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
22219  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
22220  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
22221  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
22222  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
22223  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
22224  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
22225  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
22226  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
22227  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
22228  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
22229  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
22230  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
22231  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
22232  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
22233  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
22234  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
22235  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
22236  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
22237  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
22238  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
22239  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
22240  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
22241  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
22242  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
22243  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
22244  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
22245  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
22246  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
22247  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
22248  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
22249  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
22250  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
22251  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
22252  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
22253  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
22254  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
22255  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
22256  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
22257  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
22258  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
22259  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
22260  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
22261  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
22262  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
22263  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
22264  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
22265  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
22266  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
22267  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
22268  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
22269  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
22270  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
22271  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
22272  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22273  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
22274  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22275  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
22276 };
22277 
22283 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22284 {
22285  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22286  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
22287  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22288  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
22289  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22290  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
22291  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
22292  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
22293  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
22294  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
22295  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
22296  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
22297  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
22298  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
22299  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
22300  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
22301  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
22302  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
22303  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
22304  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
22305  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
22306  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
22307  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
22308  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
22309  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
22310  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
22311  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
22312  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
22313  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
22314  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
22315  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
22316  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
22317  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
22318  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
22319  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
22320  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
22321  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
22322  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
22323  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
22324  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
22325  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
22326  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
22327  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
22328  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
22329  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
22330  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
22331  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
22332  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
22333  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
22334  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
22335  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
22336  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
22337  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
22338  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
22339  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
22340  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
22341  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
22342  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
22343  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
22344  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
22345  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
22346  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
22347  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
22348  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
22349  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
22350  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
22351  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
22352  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
22353  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
22354  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
22355  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
22356  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
22357  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
22358  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
22359  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
22360  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
22361  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
22362  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
22363  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22364  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
22365  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22366  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
22367 };
22368 
22374 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22375 {
22376  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22377  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
22378  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22379  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
22380  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22381  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
22382  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
22383  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
22384  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
22385  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
22386  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
22387  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
22388  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
22389  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
22390  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
22391  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
22392  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
22393  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
22394  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
22395  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
22396  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
22397  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
22398  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
22399  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
22400  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
22401  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
22402  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
22403  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
22404  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
22405  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
22406  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
22407  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
22408  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
22409  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
22410  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
22411  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
22412  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
22413  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
22414  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
22415  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
22416  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
22417  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
22418  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
22419  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
22420  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
22421  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
22422  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
22423  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
22424  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
22425  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
22426  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
22427  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
22428  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
22429  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
22430  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
22431  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
22432  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
22433  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
22434  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
22435  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
22436  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
22437  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
22438  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
22439  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
22440  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
22441  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
22442  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
22443  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
22444  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
22445  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
22446  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
22447  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
22448  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
22449  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
22450  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
22451  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
22452  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
22453  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
22454  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22455  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
22456  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22457  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
22458 };
22459 
22465 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22466 {
22467  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22468  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
22469  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22470  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
22471  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22472  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
22473  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
22474  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
22475  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
22476  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
22477  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
22478  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
22479  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
22480  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
22481  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
22482  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
22483  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
22484  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
22485  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
22486  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
22487  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
22488  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
22489  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
22490  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
22491  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
22492  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
22493  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
22494  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
22495  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
22496  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
22497  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
22498  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
22499  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
22500  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
22501  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
22502  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
22503  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
22504  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
22505  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
22506  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
22507  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
22508  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
22509  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
22510  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
22511  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
22512  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
22513  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
22514  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
22515  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
22516  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
22517  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
22518  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
22519  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
22520  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
22521  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
22522  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
22523  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
22524  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
22525  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
22526  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
22527  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
22528  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
22529  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
22530  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
22531  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
22532  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
22533  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
22534  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
22535  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
22536  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
22537  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
22538  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
22539  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
22540  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
22541  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
22542  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
22543  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
22544  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
22545  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22546  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
22547  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22548  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
22549 };
22550 
22556 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22557 {
22558  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22559  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
22560  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22561  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
22562  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22563  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
22564  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
22565  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
22566  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
22567  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
22568  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
22569  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
22570  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
22571  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
22572  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
22573  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
22574  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
22575  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
22576  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
22577  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
22578  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
22579  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
22580  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
22581  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
22582  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
22583  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
22584  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
22585  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
22586  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
22587  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
22588  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
22589  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
22590  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
22591  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
22592  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
22593  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
22594  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
22595  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
22596  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
22597  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
22598  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
22599  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
22600  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
22601  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
22602  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
22603  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
22604  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
22605  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
22606  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
22607  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
22608  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
22609  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
22610  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
22611  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
22612  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
22613  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
22614  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
22615  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
22616  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
22617  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
22618  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
22619  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
22620  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
22621  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
22622  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
22623  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
22624  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
22625  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
22626  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
22627  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
22628  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
22629  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
22630  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
22631  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
22632  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
22633  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
22634  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
22635  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
22636  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
22637  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
22638  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
22639  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
22640  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
22641  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
22642  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
22643  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
22644  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
22645  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
22646  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
22647  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
22648  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
22649  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
22650  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
22651  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
22652  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
22653  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
22654  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
22655  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
22656  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
22657  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
22658  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
22659  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
22660  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
22661  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
22662  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
22663  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
22664  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
22665  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
22666  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
22667  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
22668  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
22669  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
22670  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
22671  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
22672  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
22673  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
22674  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
22675  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
22676  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
22677  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
22678  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
22679  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
22680  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
22681  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
22682  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
22683  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
22684  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
22685  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
22686  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
22687  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
22688  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
22689  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
22690  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
22691  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
22692  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
22693  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
22694  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
22695  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
22696  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
22697  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
22698  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
22699  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
22700  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
22701  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
22702  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
22703  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
22704  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
22705  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
22706  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
22707  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
22708  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
22709  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
22710  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
22711  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
22712  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
22713  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
22714  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
22715  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
22716  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
22717  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
22718  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
22719  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
22720  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
22721  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
22722  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
22723  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
22724  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
22725  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
22726  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
22727  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
22728  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
22729  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
22730  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
22731  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
22732  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
22733  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
22734  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
22735  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
22736  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
22737  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
22738  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
22739  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
22740  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
22741  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
22742  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
22743  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
22744  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
22745  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
22746  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
22747  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
22748  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
22749  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
22750  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
22751  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
22752  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
22753  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
22754  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
22755  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
22756  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
22757  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
22758  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
22759  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
22760  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
22761  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
22762  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
22763  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
22764  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
22765  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
22766  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
22767  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
22768  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
22769  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
22770  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
22771  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
22772  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
22773  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
22774  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
22775  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
22776  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
22777  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
22778  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
22779  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
22780  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
22781  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
22782  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
22783  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
22784  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
22785  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
22786  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
22787  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
22788  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
22789  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
22790  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
22791  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
22792  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
22793  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
22794  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
22795  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
22796  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
22797  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
22798  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
22799  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
22800  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
22801  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
22802  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
22803  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
22804  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
22805  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
22806  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
22807  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
22808  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
22809  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
22810  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
22811  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
22812  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
22813  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
22814  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
22815  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
22816  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
22817  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
22818  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
22819  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
22820  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
22821  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
22822  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
22823  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
22824  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
22825  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
22826  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
22827  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
22828  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
22829  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
22830  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
22831  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
22832  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
22833  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
22834  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
22835  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
22836  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
22837  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
22838  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
22839  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
22840  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
22841  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
22842  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
22843  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
22844  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
22845  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
22846  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
22847  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
22848  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
22849  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
22850  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
22851  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
22852  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
22853  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
22854  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
22855  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
22856  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
22857  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
22858  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
22859  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
22860  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
22861  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
22862  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
22863  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
22864  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
22865  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
22866  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
22867  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
22868  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
22869  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
22870  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
22871  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
22872  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
22873  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
22874  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
22875  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
22876  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
22877  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
22878  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
22879  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
22880  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
22881  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
22882  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
22883  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
22884  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
22885  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
22886  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
22887  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
22888  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
22889  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
22890  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
22891  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
22892  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
22893  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
22894  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
22895  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
22896  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
22897  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
22898  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
22899  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
22900  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
22901  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
22902  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
22903  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
22904  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
22905  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
22906  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
22907  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
22908  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
22909  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
22910  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
22911  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
22912  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
22913  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
22914  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
22915  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
22916  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
22917  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
22918  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
22919  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
22920  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
22921  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
22922  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
22923  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
22924  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
22925  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
22926  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
22927  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
22928  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
22929  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
22930  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
22931  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
22932  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
22933  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
22934  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
22935  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
22936  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
22937  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
22938  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
22939  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
22940  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
22941  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
22942  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
22943  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
22944  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
22945  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
22946  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
22947  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
22948  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
22949  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
22950  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
22951  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
22952  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
22953  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
22954  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
22955  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
22956  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
22957  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
22958  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
22959  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
22960  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
22961  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
22962  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
22963  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
22964  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
22965  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
22966  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
22967  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
22968  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
22969  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
22970  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
22971  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
22972  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
22973  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
22974  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
22975  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
22976  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
22977  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
22978  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
22979  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
22980  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
22981  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
22982  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
22983  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
22984 };
22985 
22991 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
22992 {
22993  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
22994  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
22995  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
22996  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
22997  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
22998  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
22999  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
23000  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
23001  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
23002  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
23003  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
23004  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
23005  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
23006  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
23007  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
23008  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
23009  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
23010  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
23011  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
23012  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
23013  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
23014  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
23015  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
23016  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
23017  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
23018  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
23019  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
23020  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
23021  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
23022  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
23023  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
23024  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
23025  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
23026  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
23027  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
23028  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
23029  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
23030  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
23031  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
23032  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
23033  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
23034  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
23035  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
23036  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
23037  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
23038  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
23039  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
23040  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
23041  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
23042  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
23043  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
23044  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
23045  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
23046  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
23047  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
23048  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
23049  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
23050  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
23051  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
23052  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
23053  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
23054  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
23055  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
23056  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
23057  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
23058  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
23059  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
23060  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
23061  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
23062  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
23063  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
23064  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
23065  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
23066  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
23067  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
23068  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
23069  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
23070  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
23071  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
23072  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
23073  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
23074  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
23075  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
23076  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
23077  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
23078  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
23079  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
23080  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
23081  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
23082  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
23083  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
23084  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
23085  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
23086  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
23087  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
23088  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
23089  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
23090  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
23091  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
23092  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
23093  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
23094  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
23095  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
23096  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
23097  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
23098  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
23099  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
23100  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
23101  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
23102  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
23103  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
23104  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
23105  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
23106  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
23107  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
23108  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
23109  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
23110  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
23111  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
23112  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
23113  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
23114  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
23115  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
23116  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
23117  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
23118  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
23119  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
23120  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
23121  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
23122  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
23123  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
23124  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
23125  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
23126  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
23127  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
23128  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
23129  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
23130  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
23131  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
23132  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
23133  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
23134  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
23135  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
23136  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
23137  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
23138  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
23139  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
23140  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
23141  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
23142  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
23143  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
23144  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
23145  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
23146  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
23147  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
23148  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
23149  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
23150  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
23151  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
23152  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
23153  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
23154  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
23155  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
23156  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
23157  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
23158  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
23159  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
23160  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
23161  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
23162  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
23163  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
23164  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
23165  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
23166  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
23167  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
23168  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
23169  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
23170  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
23171  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
23172  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
23173  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
23174  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
23175  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
23176  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
23177  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
23178  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
23179  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
23180  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
23181  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
23182  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
23183  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
23184  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
23185  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
23186  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
23187  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
23188  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
23189  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
23190  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
23191  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
23192  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
23193  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
23194  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
23195  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
23196  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
23197  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
23198  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
23199  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
23200  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
23201  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
23202  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
23203  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
23204  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
23205  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
23206  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
23207  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
23208  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
23209  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
23210  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
23211  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
23212  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
23213  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
23214  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
23215  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
23216  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
23217  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
23218  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
23219  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
23220  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
23221  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
23222  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
23223  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
23224  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
23225  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
23226  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
23227  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
23228  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
23229  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
23230  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
23231  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
23232  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
23233  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
23234  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
23235  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
23236  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
23237  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
23238  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
23239  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
23240  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
23241  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
23242  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
23243  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
23244  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
23245  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
23246  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
23247  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
23248  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
23249  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
23250  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
23251  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
23252  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
23253  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
23254  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
23255  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
23256  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
23257  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
23258  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
23259  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
23260  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
23261  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
23262  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
23263  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
23264  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
23265  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
23266  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
23267  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
23268  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
23269  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
23270  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
23271  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
23272  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
23273  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
23274  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
23275  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
23276  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
23277  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
23278  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
23279  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
23280  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
23281  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
23282  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
23283  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
23284  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
23285  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
23286  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
23287  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
23288  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
23289  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
23290  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
23291  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
23292  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
23293  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
23294  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
23295  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
23296  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
23297  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
23298  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
23299  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
23300  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
23301  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
23302  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
23303  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
23304  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
23305  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
23306  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
23307  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
23308  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
23309  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
23310  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
23311  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
23312  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
23313  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
23314  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
23315  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
23316  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
23317  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
23318  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
23319  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
23320  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
23321  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
23322  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
23323  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
23324  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
23325  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
23326  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
23327  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
23328  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
23329  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
23330  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
23331  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
23332  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
23333  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
23334  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
23335  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
23336  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
23337  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
23338  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
23339  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
23340  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
23341  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
23342  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
23343  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
23344  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
23345  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
23346  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
23347  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
23348  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
23349  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
23350  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
23351  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
23352  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
23353  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
23354  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
23355  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
23356  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
23357  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
23358  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
23359  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
23360  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
23361  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
23362  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
23363  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
23364  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
23365  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
23366  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
23367  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
23368  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
23369  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
23370  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
23371  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
23372  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
23373  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
23374  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
23375  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
23376  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
23377  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
23378  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
23379  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
23380  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
23381  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
23382  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
23383  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
23384  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
23385  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
23386  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
23387  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
23388  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
23389  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
23390  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
23391  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
23392  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
23393  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
23394  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
23395  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
23396  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
23397  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
23398  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
23399  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
23400  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
23401  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
23402  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
23403  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
23404  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
23405  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
23406  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
23407  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
23408  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
23409  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
23410  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
23411  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
23412  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
23413  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
23414  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
23415  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
23416  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
23417  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
23418  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
23419  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
23420  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
23421  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
23422  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
23423  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
23424  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
23425  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
23426  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
23427  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
23428  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
23429  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
23430  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
23431  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
23432  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
23433  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
23434  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
23435  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
23436  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
23437  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
23438  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
23439  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
23440  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
23441  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
23442  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
23443  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
23444  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
23445  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
23446  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
23447  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
23448  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
23449  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
23450  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
23451  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
23452  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_229_WIDTH },
23453  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
23454  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_230_WIDTH },
23455  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
23456  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_231_WIDTH },
23457  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
23458  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_232_WIDTH },
23459  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
23460  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_233_WIDTH },
23461  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
23462  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_234_WIDTH },
23463  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
23464  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_235_WIDTH },
23465  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
23466  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_236_WIDTH },
23467  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
23468  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_237_WIDTH },
23469  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
23470  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_238_WIDTH },
23471  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
23472  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_239_WIDTH },
23473  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
23474  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_240_WIDTH },
23475  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
23476  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_241_WIDTH },
23477  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
23478  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_242_WIDTH },
23479  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
23480  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_243_WIDTH },
23481  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
23482  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_244_WIDTH },
23483  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
23484  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_245_WIDTH },
23485  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
23486  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_246_WIDTH },
23487  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
23488  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_247_WIDTH },
23489  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
23490  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_248_WIDTH },
23491  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
23492  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_249_WIDTH },
23493  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
23494  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_250_WIDTH },
23495  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
23496  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_251_WIDTH },
23497  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
23498  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_252_WIDTH },
23499  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
23500  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_253_WIDTH },
23501  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
23502  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_254_WIDTH },
23503  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
23504  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_GROUP_255_WIDTH },
23505 };
23506 
23512 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS] =
23513 {
23514  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
23515  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_0_WIDTH },
23516  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
23517  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_1_WIDTH },
23518  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
23519  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_2_WIDTH },
23520  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
23521  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_3_WIDTH },
23522  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
23523  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_4_WIDTH },
23524  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
23525  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_5_WIDTH },
23526  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
23527  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_6_WIDTH },
23528  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
23529  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_7_WIDTH },
23530  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
23531  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_8_WIDTH },
23532  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
23533  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_9_WIDTH },
23534  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
23535  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_10_WIDTH },
23536  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
23537  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_11_WIDTH },
23538  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
23539  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_12_WIDTH },
23540  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
23541  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_13_WIDTH },
23542  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
23543  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_14_WIDTH },
23544  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
23545  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_15_WIDTH },
23546  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
23547  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_16_WIDTH },
23548  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
23549  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_17_WIDTH },
23550  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
23551  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_18_WIDTH },
23552  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
23553  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_19_WIDTH },
23554  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
23555  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_20_WIDTH },
23556  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
23557  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_21_WIDTH },
23558  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
23559  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_22_WIDTH },
23560  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
23561  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_23_WIDTH },
23562  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
23563  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_24_WIDTH },
23564  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
23565  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_25_WIDTH },
23566  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
23567  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_26_WIDTH },
23568  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
23569  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_27_WIDTH },
23570  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
23571  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_28_WIDTH },
23572  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
23573  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_29_WIDTH },
23574  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
23575  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_30_WIDTH },
23576  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
23577  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_31_WIDTH },
23578  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
23579  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_32_WIDTH },
23580  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
23581  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_33_WIDTH },
23582  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
23583  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_34_WIDTH },
23584  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
23585  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_35_WIDTH },
23586  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
23587  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_36_WIDTH },
23588  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
23589  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_37_WIDTH },
23590  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
23591  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_38_WIDTH },
23592  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
23593  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_39_WIDTH },
23594  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
23595  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_40_WIDTH },
23596  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
23597  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_41_WIDTH },
23598  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
23599  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_42_WIDTH },
23600  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
23601  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_43_WIDTH },
23602  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
23603  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_44_WIDTH },
23604  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
23605  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_45_WIDTH },
23606  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
23607  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_46_WIDTH },
23608  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
23609  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_47_WIDTH },
23610  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
23611  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_48_WIDTH },
23612  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
23613  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_49_WIDTH },
23614  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
23615  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_50_WIDTH },
23616  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
23617  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_51_WIDTH },
23618  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
23619  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_52_WIDTH },
23620  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
23621  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_53_WIDTH },
23622  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
23623  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_54_WIDTH },
23624  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
23625  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_55_WIDTH },
23626  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
23627  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_56_WIDTH },
23628  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
23629  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_57_WIDTH },
23630  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
23631  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_58_WIDTH },
23632  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
23633  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_59_WIDTH },
23634  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
23635  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_60_WIDTH },
23636  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
23637  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_61_WIDTH },
23638  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
23639  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_62_WIDTH },
23640  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
23641  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_63_WIDTH },
23642  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
23643  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_64_WIDTH },
23644  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
23645  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_65_WIDTH },
23646  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
23647  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_66_WIDTH },
23648  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
23649  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_67_WIDTH },
23650  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
23651  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_68_WIDTH },
23652  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
23653  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_69_WIDTH },
23654  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
23655  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_70_WIDTH },
23656  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
23657  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_71_WIDTH },
23658  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
23659  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_72_WIDTH },
23660  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
23661  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_73_WIDTH },
23662  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
23663  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_74_WIDTH },
23664  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
23665  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_75_WIDTH },
23666  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
23667  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_76_WIDTH },
23668  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
23669  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_77_WIDTH },
23670  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
23671  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_78_WIDTH },
23672  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
23673  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_79_WIDTH },
23674  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
23675  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_80_WIDTH },
23676  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
23677  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_81_WIDTH },
23678  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
23679  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_82_WIDTH },
23680  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
23681  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_83_WIDTH },
23682  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
23683  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_84_WIDTH },
23684  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
23685  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_85_WIDTH },
23686  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
23687  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_86_WIDTH },
23688  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
23689  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_87_WIDTH },
23690  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
23691  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_88_WIDTH },
23692  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
23693  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_89_WIDTH },
23694  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
23695  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_90_WIDTH },
23696  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
23697  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_91_WIDTH },
23698  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
23699  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_92_WIDTH },
23700  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
23701  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_93_WIDTH },
23702  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
23703  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_94_WIDTH },
23704  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
23705  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_95_WIDTH },
23706  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
23707  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_96_WIDTH },
23708  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
23709  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_97_WIDTH },
23710  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
23711  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_98_WIDTH },
23712  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
23713  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_99_WIDTH },
23714  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
23715  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_100_WIDTH },
23716  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
23717  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_101_WIDTH },
23718  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
23719  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_102_WIDTH },
23720  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
23721  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_103_WIDTH },
23722  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
23723  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_104_WIDTH },
23724  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
23725  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_105_WIDTH },
23726  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
23727  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_106_WIDTH },
23728  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
23729  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_107_WIDTH },
23730  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
23731  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_108_WIDTH },
23732  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
23733  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_109_WIDTH },
23734  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
23735  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_110_WIDTH },
23736  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
23737  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_111_WIDTH },
23738  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
23739  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_112_WIDTH },
23740  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
23741  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_113_WIDTH },
23742  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
23743  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_114_WIDTH },
23744  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
23745  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_115_WIDTH },
23746  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
23747  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_116_WIDTH },
23748  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
23749  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_117_WIDTH },
23750  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
23751  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_118_WIDTH },
23752  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
23753  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_119_WIDTH },
23754  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
23755  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_120_WIDTH },
23756  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
23757  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_121_WIDTH },
23758  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
23759  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_122_WIDTH },
23760  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
23761  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_123_WIDTH },
23762  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
23763  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_124_WIDTH },
23764  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
23765  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_125_WIDTH },
23766  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
23767  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_126_WIDTH },
23768  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
23769  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_127_WIDTH },
23770  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
23771  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_128_WIDTH },
23772  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
23773  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_129_WIDTH },
23774  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
23775  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_130_WIDTH },
23776  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
23777  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_131_WIDTH },
23778  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
23779  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_132_WIDTH },
23780  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
23781  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_133_WIDTH },
23782  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
23783  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_134_WIDTH },
23784  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
23785  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_135_WIDTH },
23786  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
23787  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_136_WIDTH },
23788  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
23789  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_137_WIDTH },
23790  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
23791  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_138_WIDTH },
23792  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
23793  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_139_WIDTH },
23794  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
23795  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_140_WIDTH },
23796  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
23797  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_141_WIDTH },
23798  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
23799  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_142_WIDTH },
23800  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
23801  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_143_WIDTH },
23802  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
23803  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_144_WIDTH },
23804  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
23805  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_145_WIDTH },
23806  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
23807  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_146_WIDTH },
23808  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
23809  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_147_WIDTH },
23810  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
23811  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_148_WIDTH },
23812  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
23813  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_149_WIDTH },
23814  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
23815  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_150_WIDTH },
23816  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
23817  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_151_WIDTH },
23818  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
23819  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_152_WIDTH },
23820  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
23821  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_153_WIDTH },
23822  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
23823  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_154_WIDTH },
23824  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
23825  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_155_WIDTH },
23826  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
23827  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_156_WIDTH },
23828  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
23829  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_157_WIDTH },
23830  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
23831  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_158_WIDTH },
23832  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
23833  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_159_WIDTH },
23834  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
23835  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_160_WIDTH },
23836  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
23837  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_161_WIDTH },
23838  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
23839  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_162_WIDTH },
23840  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
23841  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_163_WIDTH },
23842  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_164_CHECKER_TYPE,
23843  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_164_WIDTH },
23844  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_165_CHECKER_TYPE,
23845  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_165_WIDTH },
23846  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_166_CHECKER_TYPE,
23847  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_166_WIDTH },
23848  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_167_CHECKER_TYPE,
23849  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_167_WIDTH },
23850  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_168_CHECKER_TYPE,
23851  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_168_WIDTH },
23852  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_169_CHECKER_TYPE,
23853  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_169_WIDTH },
23854  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_170_CHECKER_TYPE,
23855  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_170_WIDTH },
23856  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_171_CHECKER_TYPE,
23857  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_171_WIDTH },
23858  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_172_CHECKER_TYPE,
23859  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_172_WIDTH },
23860  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_173_CHECKER_TYPE,
23861  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_173_WIDTH },
23862  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_174_CHECKER_TYPE,
23863  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_174_WIDTH },
23864  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_175_CHECKER_TYPE,
23865  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_175_WIDTH },
23866  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_176_CHECKER_TYPE,
23867  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_176_WIDTH },
23868  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_177_CHECKER_TYPE,
23869  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_177_WIDTH },
23870  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_178_CHECKER_TYPE,
23871  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_178_WIDTH },
23872  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_179_CHECKER_TYPE,
23873  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_179_WIDTH },
23874  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_180_CHECKER_TYPE,
23875  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_180_WIDTH },
23876  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_181_CHECKER_TYPE,
23877  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_181_WIDTH },
23878  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_182_CHECKER_TYPE,
23879  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_182_WIDTH },
23880  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_183_CHECKER_TYPE,
23881  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_183_WIDTH },
23882  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_184_CHECKER_TYPE,
23883  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_184_WIDTH },
23884  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_185_CHECKER_TYPE,
23885  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_185_WIDTH },
23886  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_186_CHECKER_TYPE,
23887  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_186_WIDTH },
23888  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_187_CHECKER_TYPE,
23889  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_187_WIDTH },
23890  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_188_CHECKER_TYPE,
23891  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_188_WIDTH },
23892  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_189_CHECKER_TYPE,
23893  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_189_WIDTH },
23894  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_190_CHECKER_TYPE,
23895  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_190_WIDTH },
23896  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_191_CHECKER_TYPE,
23897  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_191_WIDTH },
23898  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_192_CHECKER_TYPE,
23899  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_192_WIDTH },
23900  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_193_CHECKER_TYPE,
23901  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_193_WIDTH },
23902  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_194_CHECKER_TYPE,
23903  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_194_WIDTH },
23904  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_195_CHECKER_TYPE,
23905  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_195_WIDTH },
23906  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_196_CHECKER_TYPE,
23907  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_196_WIDTH },
23908  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_197_CHECKER_TYPE,
23909  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_197_WIDTH },
23910  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_198_CHECKER_TYPE,
23911  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_198_WIDTH },
23912  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_199_CHECKER_TYPE,
23913  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_199_WIDTH },
23914  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_200_CHECKER_TYPE,
23915  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_200_WIDTH },
23916  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_201_CHECKER_TYPE,
23917  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_201_WIDTH },
23918  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_202_CHECKER_TYPE,
23919  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_202_WIDTH },
23920  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_203_CHECKER_TYPE,
23921  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_203_WIDTH },
23922  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_204_CHECKER_TYPE,
23923  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_204_WIDTH },
23924  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_205_CHECKER_TYPE,
23925  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_205_WIDTH },
23926  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_206_CHECKER_TYPE,
23927  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_206_WIDTH },
23928  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_207_CHECKER_TYPE,
23929  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_207_WIDTH },
23930  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_208_CHECKER_TYPE,
23931  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_208_WIDTH },
23932  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_209_CHECKER_TYPE,
23933  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_209_WIDTH },
23934  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_210_CHECKER_TYPE,
23935  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_210_WIDTH },
23936  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_211_CHECKER_TYPE,
23937  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_211_WIDTH },
23938  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_212_CHECKER_TYPE,
23939  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_212_WIDTH },
23940  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_213_CHECKER_TYPE,
23941  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_213_WIDTH },
23942  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_214_CHECKER_TYPE,
23943  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_214_WIDTH },
23944  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_215_CHECKER_TYPE,
23945  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_215_WIDTH },
23946  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_216_CHECKER_TYPE,
23947  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_216_WIDTH },
23948  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_217_CHECKER_TYPE,
23949  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_217_WIDTH },
23950  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_218_CHECKER_TYPE,
23951  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_218_WIDTH },
23952  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_219_CHECKER_TYPE,
23953  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_219_WIDTH },
23954  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_220_CHECKER_TYPE,
23955  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_220_WIDTH },
23956  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_221_CHECKER_TYPE,
23957  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_221_WIDTH },
23958  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_222_CHECKER_TYPE,
23959  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_222_WIDTH },
23960  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_223_CHECKER_TYPE,
23961  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_223_WIDTH },
23962  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_224_CHECKER_TYPE,
23963  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_224_WIDTH },
23964  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_225_CHECKER_TYPE,
23965  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_225_WIDTH },
23966  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_226_CHECKER_TYPE,
23967  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_226_WIDTH },
23968  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_227_CHECKER_TYPE,
23969  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_227_WIDTH },
23970  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_228_CHECKER_TYPE,
23971  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_228_WIDTH },
23972  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_229_CHECKER_TYPE,
23973  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_229_WIDTH },
23974  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_230_CHECKER_TYPE,
23975  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_230_WIDTH },
23976  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_231_CHECKER_TYPE,
23977  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_231_WIDTH },
23978  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_232_CHECKER_TYPE,
23979  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_232_WIDTH },
23980  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_233_CHECKER_TYPE,
23981  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_233_WIDTH },
23982  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_234_CHECKER_TYPE,
23983  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_234_WIDTH },
23984  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_235_CHECKER_TYPE,
23985  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_235_WIDTH },
23986  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_236_CHECKER_TYPE,
23987  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_236_WIDTH },
23988  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_237_CHECKER_TYPE,
23989  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_237_WIDTH },
23990  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_238_CHECKER_TYPE,
23991  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_238_WIDTH },
23992  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_239_CHECKER_TYPE,
23993  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_239_WIDTH },
23994  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_240_CHECKER_TYPE,
23995  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_240_WIDTH },
23996  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_241_CHECKER_TYPE,
23997  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_241_WIDTH },
23998  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_242_CHECKER_TYPE,
23999  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_242_WIDTH },
24000  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_243_CHECKER_TYPE,
24001  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_243_WIDTH },
24002  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_244_CHECKER_TYPE,
24003  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_244_WIDTH },
24004  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_245_CHECKER_TYPE,
24005  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_245_WIDTH },
24006  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_246_CHECKER_TYPE,
24007  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_246_WIDTH },
24008  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_247_CHECKER_TYPE,
24009  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_247_WIDTH },
24010  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_248_CHECKER_TYPE,
24011  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_248_WIDTH },
24012  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_249_CHECKER_TYPE,
24013  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_249_WIDTH },
24014  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_250_CHECKER_TYPE,
24015  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_250_WIDTH },
24016  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_251_CHECKER_TYPE,
24017  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_251_WIDTH },
24018  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_252_CHECKER_TYPE,
24019  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_252_WIDTH },
24020  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_253_CHECKER_TYPE,
24021  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_253_WIDTH },
24022  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_254_CHECKER_TYPE,
24023  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_254_WIDTH },
24024  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_255_CHECKER_TYPE,
24025  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_GROUP_255_WIDTH },
24026 };
24027 
24033 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS] =
24034 {
24035  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_0_CHECKER_TYPE,
24036  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_0_WIDTH },
24037  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_1_CHECKER_TYPE,
24038  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_1_WIDTH },
24039  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_2_CHECKER_TYPE,
24040  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_2_WIDTH },
24041  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_3_CHECKER_TYPE,
24042  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_3_WIDTH },
24043  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_4_CHECKER_TYPE,
24044  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_4_WIDTH },
24045  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_5_CHECKER_TYPE,
24046  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_5_WIDTH },
24047  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_6_CHECKER_TYPE,
24048  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_6_WIDTH },
24049  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_7_CHECKER_TYPE,
24050  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_7_WIDTH },
24051  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_8_CHECKER_TYPE,
24052  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_8_WIDTH },
24053  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_9_CHECKER_TYPE,
24054  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_9_WIDTH },
24055  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_10_CHECKER_TYPE,
24056  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_10_WIDTH },
24057  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_11_CHECKER_TYPE,
24058  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_11_WIDTH },
24059  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_12_CHECKER_TYPE,
24060  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_12_WIDTH },
24061  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_13_CHECKER_TYPE,
24062  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_13_WIDTH },
24063  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_14_CHECKER_TYPE,
24064  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_14_WIDTH },
24065  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_15_CHECKER_TYPE,
24066  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_15_WIDTH },
24067  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_16_CHECKER_TYPE,
24068  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_16_WIDTH },
24069  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_17_CHECKER_TYPE,
24070  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_17_WIDTH },
24071  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_18_CHECKER_TYPE,
24072  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_18_WIDTH },
24073  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_19_CHECKER_TYPE,
24074  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_19_WIDTH },
24075  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_20_CHECKER_TYPE,
24076  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_20_WIDTH },
24077  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_21_CHECKER_TYPE,
24078  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_21_WIDTH },
24079  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_22_CHECKER_TYPE,
24080  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_22_WIDTH },
24081  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_23_CHECKER_TYPE,
24082  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_23_WIDTH },
24083  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_24_CHECKER_TYPE,
24084  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_24_WIDTH },
24085  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_25_CHECKER_TYPE,
24086  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_25_WIDTH },
24087  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_26_CHECKER_TYPE,
24088  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_26_WIDTH },
24089  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_27_CHECKER_TYPE,
24090  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_27_WIDTH },
24091  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_28_CHECKER_TYPE,
24092  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_28_WIDTH },
24093  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_29_CHECKER_TYPE,
24094  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_29_WIDTH },
24095  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_30_CHECKER_TYPE,
24096  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_30_WIDTH },
24097  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_31_CHECKER_TYPE,
24098  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_31_WIDTH },
24099  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_32_CHECKER_TYPE,
24100  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_32_WIDTH },
24101  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_33_CHECKER_TYPE,
24102  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_33_WIDTH },
24103  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_34_CHECKER_TYPE,
24104  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_34_WIDTH },
24105  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_35_CHECKER_TYPE,
24106  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_35_WIDTH },
24107  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_36_CHECKER_TYPE,
24108  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_36_WIDTH },
24109  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_37_CHECKER_TYPE,
24110  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_37_WIDTH },
24111  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_38_CHECKER_TYPE,
24112  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_38_WIDTH },
24113  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_39_CHECKER_TYPE,
24114  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_39_WIDTH },
24115  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_40_CHECKER_TYPE,
24116  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_40_WIDTH },
24117  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_41_CHECKER_TYPE,
24118  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_41_WIDTH },
24119  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_42_CHECKER_TYPE,
24120  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_42_WIDTH },
24121  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_43_CHECKER_TYPE,
24122  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_43_WIDTH },
24123  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_44_CHECKER_TYPE,
24124  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_44_WIDTH },
24125  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_45_CHECKER_TYPE,
24126  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_45_WIDTH },
24127  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_46_CHECKER_TYPE,
24128  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_46_WIDTH },
24129  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_47_CHECKER_TYPE,
24130  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_47_WIDTH },
24131  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_48_CHECKER_TYPE,
24132  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_48_WIDTH },
24133  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_49_CHECKER_TYPE,
24134  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_49_WIDTH },
24135  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_50_CHECKER_TYPE,
24136  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_50_WIDTH },
24137  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_51_CHECKER_TYPE,
24138  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_51_WIDTH },
24139  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_52_CHECKER_TYPE,
24140  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_52_WIDTH },
24141  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_53_CHECKER_TYPE,
24142  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_53_WIDTH },
24143  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_54_CHECKER_TYPE,
24144  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_54_WIDTH },
24145  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_55_CHECKER_TYPE,
24146  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_55_WIDTH },
24147  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_56_CHECKER_TYPE,
24148  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_56_WIDTH },
24149  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_57_CHECKER_TYPE,
24150  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_57_WIDTH },
24151  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_58_CHECKER_TYPE,
24152  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_58_WIDTH },
24153  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_59_CHECKER_TYPE,
24154  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_59_WIDTH },
24155  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_60_CHECKER_TYPE,
24156  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_60_WIDTH },
24157  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_61_CHECKER_TYPE,
24158  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_61_WIDTH },
24159  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_62_CHECKER_TYPE,
24160  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_62_WIDTH },
24161  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_63_CHECKER_TYPE,
24162  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_63_WIDTH },
24163  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_64_CHECKER_TYPE,
24164  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_64_WIDTH },
24165  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_65_CHECKER_TYPE,
24166  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_65_WIDTH },
24167  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_66_CHECKER_TYPE,
24168  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_66_WIDTH },
24169  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_67_CHECKER_TYPE,
24170  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_67_WIDTH },
24171  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_68_CHECKER_TYPE,
24172  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_68_WIDTH },
24173  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_69_CHECKER_TYPE,
24174  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_69_WIDTH },
24175  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_70_CHECKER_TYPE,
24176  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_70_WIDTH },
24177  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_71_CHECKER_TYPE,
24178  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_71_WIDTH },
24179  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_72_CHECKER_TYPE,
24180  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_72_WIDTH },
24181  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_73_CHECKER_TYPE,
24182  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_73_WIDTH },
24183  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_74_CHECKER_TYPE,
24184  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_74_WIDTH },
24185  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_75_CHECKER_TYPE,
24186  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_75_WIDTH },
24187  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_76_CHECKER_TYPE,
24188  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_76_WIDTH },
24189  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_77_CHECKER_TYPE,
24190  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_77_WIDTH },
24191  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_78_CHECKER_TYPE,
24192  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_78_WIDTH },
24193  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_79_CHECKER_TYPE,
24194  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_79_WIDTH },
24195  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_80_CHECKER_TYPE,
24196  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_80_WIDTH },
24197  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_81_CHECKER_TYPE,
24198  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_81_WIDTH },
24199  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_82_CHECKER_TYPE,
24200  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_82_WIDTH },
24201  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_83_CHECKER_TYPE,
24202  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_83_WIDTH },
24203  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_84_CHECKER_TYPE,
24204  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_84_WIDTH },
24205  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_85_CHECKER_TYPE,
24206  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_85_WIDTH },
24207  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_86_CHECKER_TYPE,
24208  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_86_WIDTH },
24209  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_87_CHECKER_TYPE,
24210  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_87_WIDTH },
24211  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_88_CHECKER_TYPE,
24212  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_88_WIDTH },
24213  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_89_CHECKER_TYPE,
24214  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_89_WIDTH },
24215  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_90_CHECKER_TYPE,
24216  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_90_WIDTH },
24217  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_91_CHECKER_TYPE,
24218  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_91_WIDTH },
24219  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_92_CHECKER_TYPE,
24220  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_92_WIDTH },
24221  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_93_CHECKER_TYPE,
24222  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_93_WIDTH },
24223  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_94_CHECKER_TYPE,
24224  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_94_WIDTH },
24225  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_95_CHECKER_TYPE,
24226  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_95_WIDTH },
24227  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_96_CHECKER_TYPE,
24228  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_96_WIDTH },
24229  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_97_CHECKER_TYPE,
24230  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_97_WIDTH },
24231  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_98_CHECKER_TYPE,
24232  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_98_WIDTH },
24233  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_99_CHECKER_TYPE,
24234  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_99_WIDTH },
24235  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_100_CHECKER_TYPE,
24236  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_100_WIDTH },
24237  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_101_CHECKER_TYPE,
24238  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_101_WIDTH },
24239  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_102_CHECKER_TYPE,
24240  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_102_WIDTH },
24241  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_103_CHECKER_TYPE,
24242  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_103_WIDTH },
24243  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_104_CHECKER_TYPE,
24244  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_104_WIDTH },
24245  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_105_CHECKER_TYPE,
24246  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_105_WIDTH },
24247  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_106_CHECKER_TYPE,
24248  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_106_WIDTH },
24249  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_107_CHECKER_TYPE,
24250  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_107_WIDTH },
24251  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_108_CHECKER_TYPE,
24252  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_108_WIDTH },
24253  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_109_CHECKER_TYPE,
24254  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_109_WIDTH },
24255  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_110_CHECKER_TYPE,
24256  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_110_WIDTH },
24257  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_111_CHECKER_TYPE,
24258  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_111_WIDTH },
24259  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_112_CHECKER_TYPE,
24260  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_112_WIDTH },
24261  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_113_CHECKER_TYPE,
24262  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_113_WIDTH },
24263  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_114_CHECKER_TYPE,
24264  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_114_WIDTH },
24265  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_115_CHECKER_TYPE,
24266  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_115_WIDTH },
24267  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_116_CHECKER_TYPE,
24268  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_116_WIDTH },
24269  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_117_CHECKER_TYPE,
24270  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_117_WIDTH },
24271  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_118_CHECKER_TYPE,
24272  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_118_WIDTH },
24273  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_119_CHECKER_TYPE,
24274  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_119_WIDTH },
24275  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_120_CHECKER_TYPE,
24276  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_120_WIDTH },
24277  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_121_CHECKER_TYPE,
24278  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_GROUP_121_WIDTH },
24279 };
24280 
24286 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24287 {
24288  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24289  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
24290  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24291  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
24292  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24293  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
24294  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24295  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
24296  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24297  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
24298  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24299  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
24300  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24301  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
24302  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24303  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
24304  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24305  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
24306 };
24307 
24313 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24314 {
24315  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24316  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24317  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24318  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24319  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24320  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24321  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24322  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24323  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24324  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24325  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24326  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24327  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24328  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24329  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24330  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24331  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24332  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24333  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24334  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24335  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24336  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24337  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24338  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24339  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24340  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24341  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24342  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24343  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24344  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24345 };
24346 
24352 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24353 {
24354  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24355  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24356  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24357  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24358  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24359  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24360  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24361  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24362 };
24363 
24369 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24370 {
24371  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24372  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
24373  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24374  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
24375  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24376  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
24377  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24378  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
24379  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24380  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
24381  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24382  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
24383  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24384  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
24385  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24386  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
24387  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24388  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
24389  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24390  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
24391  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24392  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
24393  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24394  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
24395  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24396  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
24397  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24398  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
24399  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24400  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
24401  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
24402  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
24403  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
24404  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
24405  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
24406  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
24407  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
24408  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
24409  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
24410  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
24411  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
24412  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
24413  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
24414  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
24415  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
24416  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
24417  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
24418  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
24419  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
24420  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
24421  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
24422  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
24423  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
24424  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
24425  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
24426  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
24427  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
24428  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
24429  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
24430  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
24431  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
24432  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
24433  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
24434  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
24435  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
24436  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
24437  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
24438  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
24439  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
24440  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
24441  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
24442  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
24443  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
24444  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
24445  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
24446  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
24447  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
24448  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
24449  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
24450  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
24451  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
24452  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
24453  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
24454  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
24455  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
24456  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
24457  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
24458  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
24459  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
24460  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
24461  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
24462  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
24463  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
24464  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
24465  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
24466  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
24467  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
24468  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
24469  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
24470  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
24471  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
24472  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
24473  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
24474  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
24475  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
24476  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
24477  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
24478  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
24479  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
24480  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
24481  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
24482  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
24483  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
24484  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
24485  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
24486  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
24487  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
24488  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
24489  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
24490  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
24491  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
24492  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
24493  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
24494  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
24495  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
24496  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
24497  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
24498  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
24499  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
24500  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
24501  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
24502  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
24503  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
24504  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
24505  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
24506  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
24507  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
24508  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
24509  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
24510  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
24511  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
24512  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
24513  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
24514  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
24515  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
24516  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
24517  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
24518  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
24519  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
24520  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
24521  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
24522  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
24523  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
24524  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
24525  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
24526  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
24527  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
24528  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
24529  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
24530  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
24531  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
24532  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
24533  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
24534  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
24535  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
24536  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
24537  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
24538  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
24539  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
24540  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
24541  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
24542  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
24543  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
24544  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
24545  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
24546  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
24547  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
24548  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
24549  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
24550  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
24551  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
24552  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
24553  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
24554  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
24555  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
24556  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
24557  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
24558  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
24559  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
24560  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
24561  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
24562  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
24563  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
24564  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
24565  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
24566  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
24567  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
24568  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
24569  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
24570  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
24571  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
24572  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
24573  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
24574  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
24575  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
24576  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
24577  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
24578  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
24579  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
24580  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
24581  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
24582  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
24583  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
24584  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
24585  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
24586  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
24587  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
24588  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
24589  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
24590  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
24591  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
24592  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
24593  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
24594  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
24595  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
24596  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
24597  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
24598  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
24599 };
24600 
24606 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24607 {
24608  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24609  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24610  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24611  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24612  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24613  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24614  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24615  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24616  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24617  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24618  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24619  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24620  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24621  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24622  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24623  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24624  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24625  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24626  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24627  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24628  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24629  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24630  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24631  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24632  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24633  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24634  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24635  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24636  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24637  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24638 };
24639 
24645 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24646 {
24647  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24648  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24649  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24650  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24651  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24652  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24653  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24654  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24655 };
24656 
24662 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24663 {
24664  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24665  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24666  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24667  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24668  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24669  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24670  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24671  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24672  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24673  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24674  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24675  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24676  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24677  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24678  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24679  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24680  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24681  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24682  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24683  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24684  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24685  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24686  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24687  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24688  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24689  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24690  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24691  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24692  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24693  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24694 };
24695 
24701 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24702 {
24703  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24704  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24705  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24706  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24707  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24708  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24709  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24710  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24711 };
24712 
24718 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24719 {
24720  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24721  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24722  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24723  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24724  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24725  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24726  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24727  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24728  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24729  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24730  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24731  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24732  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24733  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24734  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24735  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24736  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24737  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24738  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24739  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24740  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24741  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24742  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24743  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24744  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24745  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24746  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24747  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24748  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24749  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24750 };
24751 
24757 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24758 {
24759  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24760  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24761  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24762  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24763  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24764  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24765  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24766  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24767 };
24768 
24774 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24775 {
24776  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24777  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24778  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24779  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24780  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24781  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24782  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24783  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24784  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24785  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24786  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24787  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24788  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24789  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24790  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24791  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24792  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24793  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24794  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24795  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24796  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24797  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24798  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24799  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24800  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24801  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24802  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24803  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24804  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24805  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24806 };
24807 
24813 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24814 {
24815  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24816  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24817  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24818  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24819  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24820  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24821  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24822  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24823 };
24824 
24830 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24831 {
24832  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24833  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24834  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24835  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24836  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24837  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24838  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24839  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24840  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24841  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24842  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24843  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24844  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24845  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24846  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24847  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24848  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24849  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24850  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24851  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24852  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24853  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24854  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24855  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24856  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24857  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24858  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24859  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24860  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24861  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24862 };
24863 
24869 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24870 {
24871  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24872  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24873  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24874  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24875  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24876  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24877  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24878  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24879 };
24880 
24886 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24887 {
24888  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24889  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24890  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24891  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24892  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24893  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24894  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24895  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24896  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24897  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24898  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24899  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24900  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24901  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24902  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24903  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24904  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24905  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24906  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24907  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24908  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24909  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24910  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24911  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24912  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24913  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24914  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24915  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24916  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24917  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24918 };
24919 
24925 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24926 {
24927  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24928  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24929  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24930  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24931  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24932  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24933  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24934  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24935 };
24936 
24942 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24943 {
24944  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24945  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
24946  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24947  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
24948  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24949  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
24950  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24951  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
24952  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
24953  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
24954  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
24955  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
24956  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
24957  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
24958  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
24959  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
24960  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
24961  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
24962  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
24963  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
24964  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
24965  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
24966  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
24967  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
24968  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
24969  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
24970  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
24971  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
24972  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
24973  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
24974 };
24975 
24981 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24982 {
24983  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
24984  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
24985  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
24986  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
24987  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
24988  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
24989  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
24990  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
24991 };
24992 
24998 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
24999 {
25000  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
25001  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
25002  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
25003  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
25004  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
25005  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
25006  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
25007  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
25008  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
25009  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
25010  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
25011  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
25012  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
25013  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
25014  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
25015  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
25016  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
25017  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
25018  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
25019  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
25020  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
25021  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
25022  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
25023  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
25024  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
25025  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
25026  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
25027  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
25028  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
25029  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
25030 };
25031 
25037 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
25038 {
25039  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
25040  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
25041  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
25042  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
25043  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
25044  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
25045  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
25046  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
25047 };
25048 
25054 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
25055 {
25056  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
25057  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
25058  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
25059  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
25060  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
25061  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
25062  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
25063  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
25064  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
25065  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
25066  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
25067  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
25068  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
25069  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
25070  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
25071  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
25072  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
25073  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
25074  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
25075  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
25076  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
25077  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
25078  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
25079  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
25080  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
25081  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
25082  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
25083  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
25084  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
25085  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
25086 };
25087 
25093 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
25094 {
25095  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
25096  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
25097  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
25098  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
25099  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
25100  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
25101  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
25102  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
25103 };
25104 
25110 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
25111 {
25112  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
25113  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
25114  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
25115  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
25116  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
25117  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
25118  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
25119  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
25120  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
25121  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
25122  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
25123  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
25124  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
25125  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
25126  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
25127  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
25128  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
25129  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
25130  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
25131  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
25132  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
25133  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
25134  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
25135  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
25136  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
25137  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
25138  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
25139  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
25140  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
25141  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
25142  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
25143  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
25144  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
25145  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
25146  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
25147  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
25148  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
25149  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
25150  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
25151  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
25152  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
25153  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
25154  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
25155  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
25156  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
25157  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
25158  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
25159  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
25160  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
25161  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
25162  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
25163  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
25164  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
25165  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
25166  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
25167  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
25168  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
25169  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
25170  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
25171  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
25172  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
25173  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
25174  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
25175  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
25176  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
25177  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
25178  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
25179  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
25180  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
25181  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
25182  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
25183  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
25184  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
25185  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
25186  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
25187  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
25188  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
25189  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
25190  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
25191  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
25192  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
25193  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
25194  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
25195  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
25196  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
25197  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
25198  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
25199  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
25200  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
25201  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
25202  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
25203  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
25204  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
25205  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
25206  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
25207  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
25208  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
25209  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
25210  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
25211  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
25212  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
25213  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
25214  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
25215  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
25216  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
25217  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
25218  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
25219  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
25220  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
25221  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
25222  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
25223  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
25224  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
25225  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
25226  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
25227  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
25228  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
25229  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
25230  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
25231  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
25232  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
25233  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
25234  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
25235  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
25236  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
25237  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_62_WIDTH },
25238  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
25239  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_63_WIDTH },
25240  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
25241  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_64_WIDTH },
25242  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
25243  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_65_WIDTH },
25244  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
25245  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_66_WIDTH },
25246  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
25247  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_67_WIDTH },
25248  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
25249  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_68_WIDTH },
25250  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
25251  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_69_WIDTH },
25252  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
25253  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_70_WIDTH },
25254  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
25255  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_71_WIDTH },
25256  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
25257  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_72_WIDTH },
25258  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
25259  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_73_WIDTH },
25260  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
25261  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_74_WIDTH },
25262  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
25263  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_75_WIDTH },
25264  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
25265  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_76_WIDTH },
25266  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
25267  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_77_WIDTH },
25268  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
25269  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_78_WIDTH },
25270  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
25271  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_79_WIDTH },
25272  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
25273  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_80_WIDTH },
25274  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
25275  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_81_WIDTH },
25276  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
25277  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_82_WIDTH },
25278  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
25279  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_83_WIDTH },
25280  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
25281  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_84_WIDTH },
25282  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
25283  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_85_WIDTH },
25284  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
25285  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_86_WIDTH },
25286  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
25287  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_87_WIDTH },
25288  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
25289  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_88_WIDTH },
25290  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
25291  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_89_WIDTH },
25292  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
25293  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_90_WIDTH },
25294  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
25295  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_91_WIDTH },
25296  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
25297  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_92_WIDTH },
25298  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
25299  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_93_WIDTH },
25300  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
25301  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_94_WIDTH },
25302  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
25303  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_95_WIDTH },
25304  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
25305  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_96_WIDTH },
25306  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
25307  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_97_WIDTH },
25308  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
25309  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_98_WIDTH },
25310  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
25311  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_99_WIDTH },
25312  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
25313  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_100_WIDTH },
25314  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
25315  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_101_WIDTH },
25316  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
25317  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_102_WIDTH },
25318  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
25319  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_103_WIDTH },
25320  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
25321  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_104_WIDTH },
25322  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
25323  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_105_WIDTH },
25324  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
25325  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_106_WIDTH },
25326  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
25327  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_107_WIDTH },
25328  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
25329  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_108_WIDTH },
25330  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
25331  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_109_WIDTH },
25332  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
25333  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_110_WIDTH },
25334  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
25335  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_111_WIDTH },
25336  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
25337  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_112_WIDTH },
25338  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
25339  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_113_WIDTH },
25340  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
25341  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_114_WIDTH },
25342  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
25343  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_115_WIDTH },
25344  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
25345  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_116_WIDTH },
25346  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
25347  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_117_WIDTH },
25348  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
25349  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_118_WIDTH },
25350  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
25351  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_119_WIDTH },
25352  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
25353  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_120_WIDTH },
25354  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
25355  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_121_WIDTH },
25356  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
25357  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_122_WIDTH },
25358  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
25359  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_123_WIDTH },
25360  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
25361  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_124_WIDTH },
25362  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
25363  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_125_WIDTH },
25364  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
25365  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_126_WIDTH },
25366  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
25367  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_127_WIDTH },
25368  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
25369  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_128_WIDTH },
25370  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
25371  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_129_WIDTH },
25372  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
25373  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_130_WIDTH },
25374  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
25375  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_131_WIDTH },
25376  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
25377  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_132_WIDTH },
25378  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
25379  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_133_WIDTH },
25380  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
25381  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_134_WIDTH },
25382  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
25383  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_135_WIDTH },
25384  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
25385  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_136_WIDTH },
25386  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
25387  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_137_WIDTH },
25388  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
25389  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_138_WIDTH },
25390  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
25391  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_139_WIDTH },
25392  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
25393  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_140_WIDTH },
25394  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
25395  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_141_WIDTH },
25396  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
25397  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_142_WIDTH },
25398  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
25399  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_143_WIDTH },
25400  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
25401  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_144_WIDTH },
25402  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
25403  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_145_WIDTH },
25404  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
25405  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_146_WIDTH },
25406  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
25407  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_147_WIDTH },
25408  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
25409  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_148_WIDTH },
25410  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
25411  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_149_WIDTH },
25412  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
25413  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_150_WIDTH },
25414  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
25415  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_151_WIDTH },
25416  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
25417  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_152_WIDTH },
25418  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
25419  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_153_WIDTH },
25420  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
25421  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_154_WIDTH },
25422  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
25423  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_155_WIDTH },
25424  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
25425  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_156_WIDTH },
25426  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
25427  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_157_WIDTH },
25428  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
25429  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_158_WIDTH },
25430  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
25431  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_159_WIDTH },
25432  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
25433  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_160_WIDTH },
25434  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
25435  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_161_WIDTH },
25436  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
25437  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_162_WIDTH },
25438  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
25439  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_163_WIDTH },
25440  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
25441  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_164_WIDTH },
25442  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
25443  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_165_WIDTH },
25444  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
25445  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_166_WIDTH },
25446  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
25447  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_167_WIDTH },
25448  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
25449  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_168_WIDTH },
25450  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
25451  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_169_WIDTH },
25452  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
25453  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_170_WIDTH },
25454  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
25455  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_171_WIDTH },
25456  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
25457  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_172_WIDTH },
25458  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
25459  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_173_WIDTH },
25460  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
25461  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_174_WIDTH },
25462  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
25463  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_175_WIDTH },
25464  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
25465  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_176_WIDTH },
25466  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
25467  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_177_WIDTH },
25468  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
25469  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_178_WIDTH },
25470  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
25471  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_179_WIDTH },
25472  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
25473  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_180_WIDTH },
25474  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
25475  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_181_WIDTH },
25476  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
25477  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_182_WIDTH },
25478  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
25479  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_183_WIDTH },
25480  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
25481  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_184_WIDTH },
25482  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
25483  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_185_WIDTH },
25484  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
25485  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_186_WIDTH },
25486  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
25487  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_187_WIDTH },
25488  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
25489  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_188_WIDTH },
25490  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
25491  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_189_WIDTH },
25492  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
25493  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_190_WIDTH },
25494  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
25495  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_191_WIDTH },
25496  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
25497  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_192_WIDTH },
25498  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
25499  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_193_WIDTH },
25500  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
25501  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_194_WIDTH },
25502  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
25503  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_195_WIDTH },
25504  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
25505  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_196_WIDTH },
25506  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
25507  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_197_WIDTH },
25508  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
25509  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_198_WIDTH },
25510  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
25511  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_199_WIDTH },
25512  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
25513  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_200_WIDTH },
25514  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
25515  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_201_WIDTH },
25516  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
25517  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_202_WIDTH },
25518  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
25519  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_203_WIDTH },
25520  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
25521  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_204_WIDTH },
25522  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
25523  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_205_WIDTH },
25524  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
25525  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_206_WIDTH },
25526  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
25527  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_207_WIDTH },
25528  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
25529  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_208_WIDTH },
25530  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
25531  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_209_WIDTH },
25532  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
25533  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_210_WIDTH },
25534  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
25535  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_211_WIDTH },
25536  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
25537  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_212_WIDTH },
25538  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
25539  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_213_WIDTH },
25540  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
25541  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_214_WIDTH },
25542  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
25543  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_215_WIDTH },
25544  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
25545  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_216_WIDTH },
25546  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
25547  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_217_WIDTH },
25548  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
25549  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_218_WIDTH },
25550  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
25551  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_219_WIDTH },
25552  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
25553  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_220_WIDTH },
25554  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
25555  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_221_WIDTH },
25556  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
25557  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_222_WIDTH },
25558  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
25559  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_223_WIDTH },
25560  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
25561  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_224_WIDTH },
25562  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
25563  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_225_WIDTH },
25564  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
25565  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_226_WIDTH },
25566  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
25567  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_227_WIDTH },
25568  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
25569  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_228_WIDTH },
25570  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
25571  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_229_WIDTH },
25572  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
25573  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_230_WIDTH },
25574  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
25575  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_231_WIDTH },
25576  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
25577  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_232_WIDTH },
25578  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
25579  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_233_WIDTH },
25580  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
25581  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_234_WIDTH },
25582  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
25583  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_235_WIDTH },
25584  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
25585  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_236_WIDTH },
25586  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
25587  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_237_WIDTH },
25588  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
25589  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_238_WIDTH },
25590  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
25591  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_239_WIDTH },
25592  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
25593  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_240_WIDTH },
25594  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
25595  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_241_WIDTH },
25596  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
25597  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_242_WIDTH },
25598  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
25599  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_243_WIDTH },
25600  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
25601  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_244_WIDTH },
25602  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
25603  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_245_WIDTH },
25604  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
25605  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_246_WIDTH },
25606  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
25607  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_247_WIDTH },
25608  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
25609  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_248_WIDTH },
25610  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
25611  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_249_WIDTH },
25612  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
25613  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_250_WIDTH },
25614  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
25615  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_251_WIDTH },
25616  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
25617  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_252_WIDTH },
25618  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
25619  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_253_WIDTH },
25620  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
25621  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_254_WIDTH },
25622  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
25623  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_255_WIDTH },
25624 };
25625 
25631 static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS] =
25632 {
25633  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
25634  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_0_WIDTH },
25635  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
25636  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_1_WIDTH },
25637  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
25638  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_2_WIDTH },
25639  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
25640  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_3_WIDTH },
25641  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
25642  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_4_WIDTH },
25643  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
25644  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_5_WIDTH },
25645  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
25646  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_6_WIDTH },
25647  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
25648  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_7_WIDTH },
25649  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
25650  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_8_WIDTH },
25651  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
25652  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_9_WIDTH },
25653  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
25654  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_10_WIDTH },
25655  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
25656  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_11_WIDTH },
25657  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
25658  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_12_WIDTH },
25659  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
25660  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_13_WIDTH },
25661  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
25662  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_14_WIDTH },
25663  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
25664  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_15_WIDTH },
25665  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
25666  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_16_WIDTH },
25667  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
25668  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_17_WIDTH },
25669  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
25670  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_18_WIDTH },
25671  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
25672  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_19_WIDTH },
25673  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
25674  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_20_WIDTH },
25675  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
25676  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_21_WIDTH },
25677  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
25678  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_22_WIDTH },
25679  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
25680  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_23_WIDTH },
25681  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
25682  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_24_WIDTH },
25683  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
25684  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_25_WIDTH },
25685  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
25686  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_26_WIDTH },
25687  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
25688  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_27_WIDTH },
25689  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
25690  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_28_WIDTH },
25691  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
25692  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_29_WIDTH },
25693  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
25694  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_30_WIDTH },
25695  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
25696  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_31_WIDTH },
25697  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
25698  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_32_WIDTH },
25699  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
25700  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_33_WIDTH },
25701  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
25702  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_34_WIDTH },
25703  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
25704  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_35_WIDTH },
25705  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
25706  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_36_WIDTH },
25707  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
25708  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_37_WIDTH },
25709  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
25710  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_38_WIDTH },
25711  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
25712  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_39_WIDTH },
25713  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
25714  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_40_WIDTH },
25715  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
25716  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_41_WIDTH },
25717  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
25718  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_42_WIDTH },
25719  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
25720  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_43_WIDTH },
25721  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
25722  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_44_WIDTH },
25723  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
25724  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_45_WIDTH },
25725  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
25726  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_46_WIDTH },
25727  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
25728  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_47_WIDTH },
25729  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
25730  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_48_WIDTH },
25731  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
25732  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_49_WIDTH },
25733  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
25734  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_50_WIDTH },
25735  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
25736  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_51_WIDTH },
25737  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
25738  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_52_WIDTH },
25739  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
25740  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_53_WIDTH },
25741  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
25742  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_54_WIDTH },
25743  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
25744  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_55_WIDTH },
25745  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
25746  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_56_WIDTH },
25747  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
25748  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_57_WIDTH },
25749  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
25750  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_58_WIDTH },
25751  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
25752  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_59_WIDTH },
25753  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
25754  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_60_WIDTH },
25755  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
25756  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_61_WIDTH },
25757  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
25758  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_62_WIDTH },
25759  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
25760  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_63_WIDTH },
25761  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
25762  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_64_WIDTH },
25763  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
25764  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_65_WIDTH },
25765  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
25766  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_66_WIDTH },
25767  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
25768  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_67_WIDTH },
25769  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
25770  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_68_WIDTH },
25771  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
25772  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_69_WIDTH },
25773  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
25774  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_70_WIDTH },
25775  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
25776  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_71_WIDTH },
25777  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
25778  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_72_WIDTH },
25779  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
25780  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_73_WIDTH },
25781  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
25782  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_74_WIDTH },
25783  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
25784  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_75_WIDTH },
25785  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
25786  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_76_WIDTH },
25787  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
25788  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_77_WIDTH },
25789  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
25790  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_78_WIDTH },
25791  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
25792  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_79_WIDTH },
25793  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
25794  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_80_WIDTH },
25795  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
25796  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_81_WIDTH },
25797  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
25798  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_82_WIDTH },
25799  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
25800  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_83_WIDTH },
25801  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
25802  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_84_WIDTH },
25803  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
25804  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_85_WIDTH },
25805  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
25806  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_86_WIDTH },
25807  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
25808  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_87_WIDTH },
25809  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
25810  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_88_WIDTH },
25811  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
25812  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_89_WIDTH },
25813  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
25814  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_90_WIDTH },
25815  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
25816  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_91_WIDTH },
25817  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
25818  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_92_WIDTH },
25819  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
25820  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_93_WIDTH },
25821  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
25822  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_94_WIDTH },
25823  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
25824  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_95_WIDTH },
25825  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
25826  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_96_WIDTH },
25827  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
25828  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_97_WIDTH },
25829  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
25830  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_98_WIDTH },
25831  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
25832  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_99_WIDTH },
25833  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
25834  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_100_WIDTH },
25835  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
25836  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_101_WIDTH },
25837  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
25838  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_102_WIDTH },
25839  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
25840  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_103_WIDTH },
25841  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
25842  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_104_WIDTH },
25843  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
25844  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_105_WIDTH },
25845  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
25846  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_106_WIDTH },
25847  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
25848  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_107_WIDTH },
25849  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
25850  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_108_WIDTH },
25851  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
25852  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_109_WIDTH },
25853  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
25854  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_110_WIDTH },
25855  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
25856  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_111_WIDTH },
25857  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
25858  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_112_WIDTH },
25859  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
25860  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_113_WIDTH },
25861  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
25862  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_114_WIDTH },
25863  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
25864  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_115_WIDTH },
25865  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
25866  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_116_WIDTH },
25867  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
25868  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_117_WIDTH },
25869  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
25870  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_118_WIDTH },
25871  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
25872  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_119_WIDTH },
25873  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
25874  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_120_WIDTH },
25875  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
25876  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_121_WIDTH },
25877  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
25878  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_122_WIDTH },
25879  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
25880  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_123_WIDTH },
25881  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
25882  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_124_WIDTH },
25883  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
25884  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_125_WIDTH },
25885  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
25886  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_126_WIDTH },
25887  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
25888  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_127_WIDTH },
25889  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
25890  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_128_WIDTH },
25891  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
25892  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_129_WIDTH },
25893  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
25894  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_130_WIDTH },
25895  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
25896  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_131_WIDTH },
25897  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
25898  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_132_WIDTH },
25899  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
25900  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_133_WIDTH },
25901  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
25902  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_134_WIDTH },
25903  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
25904  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_135_WIDTH },
25905  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
25906  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_136_WIDTH },
25907  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
25908  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_137_WIDTH },
25909  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
25910  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_138_WIDTH },
25911  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
25912  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_139_WIDTH },
25913  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
25914  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_140_WIDTH },
25915  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
25916  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_141_WIDTH },
25917  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
25918  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_142_WIDTH },
25919  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
25920  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_143_WIDTH },
25921  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
25922  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_144_WIDTH },
25923  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
25924  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_145_WIDTH },
25925  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
25926  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_146_WIDTH },
25927  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
25928  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_147_WIDTH },
25929  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
25930  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_148_WIDTH },
25931  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
25932  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_149_WIDTH },
25933  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
25934  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_150_WIDTH },
25935  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
25936  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_151_WIDTH },
25937  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
25938  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_152_WIDTH },
25939  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
25940  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_153_WIDTH },
25941  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
25942  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_154_WIDTH },
25943  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
25944  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_155_WIDTH },
25945  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
25946  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_156_WIDTH },
25947  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
25948  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_157_WIDTH },
25949  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
25950  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_158_WIDTH },
25951  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
25952  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_159_WIDTH },
25953  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
25954  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_160_WIDTH },
25955  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
25956  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_161_WIDTH },
25957  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
25958  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_162_WIDTH },
25959 };
25960 
25965 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
25966 {
25967  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
25968  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
25969  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
25970  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
25971  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
25972  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
25973  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
25974  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
25975  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
25976  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
25977  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
25978  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
25979  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
25980  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
25981  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
25982  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
25983  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
25984  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
25985  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
25986  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
25987  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
25988  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
25989  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
25990  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
25991  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
25992  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
25993  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
25994  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
25995  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
25996  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
25997  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
25998  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
25999  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
26000  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
26001  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
26002  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
26003  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
26004  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
26005  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
26006  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
26007  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
26008  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
26009  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
26010  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
26011  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
26012  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
26013  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
26014  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
26015  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
26016  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
26017  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
26018  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
26019  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
26020  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
26021  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
26022  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
26023  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
26024  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
26025  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
26026  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
26027  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
26028  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
26029  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
26030  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x5c00000u,
26031  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
26032  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
26033  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x5c00004u,
26034  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
26035  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
26036  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x5c10000u,
26037  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
26038  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
26039  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x5c10004U,
26040  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
26041  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
26042  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x5c10008U,
26043  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
26044  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
26045  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x5c1000cU,
26046  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
26047  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
26048  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
26049  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
26050  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
26051 };
26052 
26058 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS] =
26059 {
26060  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26061  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_WIDTH },
26062  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26063  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_WIDTH },
26064  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26065  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_WIDTH },
26066  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
26067  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_WIDTH },
26068  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
26069  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_WIDTH },
26070  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
26071  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_WIDTH },
26072  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
26073  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_WIDTH },
26074  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
26075  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_WIDTH },
26076  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
26077  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_WIDTH },
26078  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
26079  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_WIDTH },
26080  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
26081  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_WIDTH },
26082  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
26083  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_WIDTH },
26084  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
26085  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_WIDTH },
26086  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_CHECKER_TYPE,
26087  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_WIDTH },
26088  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_CHECKER_TYPE,
26089  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_WIDTH },
26090  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_CHECKER_TYPE,
26091  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_WIDTH },
26092  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_CHECKER_TYPE,
26093  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_WIDTH },
26094  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_CHECKER_TYPE,
26095  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_WIDTH },
26096  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_CHECKER_TYPE,
26097  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_WIDTH },
26098  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_CHECKER_TYPE,
26099  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_WIDTH },
26100  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_CHECKER_TYPE,
26101  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_WIDTH },
26102  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_CHECKER_TYPE,
26103  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_WIDTH },
26104  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_CHECKER_TYPE,
26105  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_WIDTH },
26106  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_CHECKER_TYPE,
26107  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_WIDTH },
26108  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_CHECKER_TYPE,
26109  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_WIDTH },
26110  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_CHECKER_TYPE,
26111  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_WIDTH },
26112  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_CHECKER_TYPE,
26113  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_WIDTH },
26114  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_CHECKER_TYPE,
26115  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_WIDTH },
26116  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_CHECKER_TYPE,
26117  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_WIDTH },
26118  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_CHECKER_TYPE,
26119  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_WIDTH },
26120  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_CHECKER_TYPE,
26121  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_WIDTH },
26122  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_CHECKER_TYPE,
26123  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_WIDTH },
26124  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_CHECKER_TYPE,
26125  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_WIDTH },
26126  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_CHECKER_TYPE,
26127  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_WIDTH },
26128  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_CHECKER_TYPE,
26129  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_WIDTH },
26130  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_CHECKER_TYPE,
26131  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_WIDTH },
26132  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_CHECKER_TYPE,
26133  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_WIDTH },
26134  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_CHECKER_TYPE,
26135  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_WIDTH },
26136  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_CHECKER_TYPE,
26137  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_WIDTH },
26138  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_CHECKER_TYPE,
26139  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_WIDTH },
26140  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_CHECKER_TYPE,
26141  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_WIDTH },
26142  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_CHECKER_TYPE,
26143  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_WIDTH },
26144  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_CHECKER_TYPE,
26145  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_WIDTH },
26146  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_CHECKER_TYPE,
26147  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_WIDTH },
26148  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_CHECKER_TYPE,
26149  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_WIDTH },
26150  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_CHECKER_TYPE,
26151  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_WIDTH },
26152  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_CHECKER_TYPE,
26153  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_WIDTH },
26154  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_CHECKER_TYPE,
26155  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_WIDTH },
26156  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_CHECKER_TYPE,
26157  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_WIDTH },
26158 };
26159 
26165 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
26166 {
26167  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26168  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
26169  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26170  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
26171  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26172  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
26173  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
26174  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
26175  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
26176  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
26177  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
26178  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
26179  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
26180  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
26181  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
26182  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
26183  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
26184  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
26185  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
26186  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
26187  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
26188  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
26189  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
26190  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
26191  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
26192  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
26193  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
26194  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
26195  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
26196  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
26197  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
26198  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
26199  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
26200  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
26201  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
26202  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
26203  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
26204  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
26205  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
26206  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
26207  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
26208  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
26209  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
26210  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
26211  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
26212  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
26213  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
26214  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
26215  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
26216  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
26217  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
26218  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
26219  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
26220  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
26221  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
26222  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
26223  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
26224  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
26225  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
26226  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
26227  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
26228  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
26229 };
26230 
26236 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
26237 {
26238  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26239  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
26240  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26241  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
26242  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26243  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
26244  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
26245  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
26246  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
26247  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
26248  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
26249  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
26250  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
26251  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
26252  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
26253  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
26254  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
26255  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
26256  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
26257  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
26258  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
26259  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
26260  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
26261  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
26262  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
26263  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
26264  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
26265  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
26266  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
26267  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
26268  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_CHECKER_TYPE,
26269  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_WIDTH },
26270 };
26271 
26277 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
26278 {
26279  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26280  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
26281  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26282  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
26283  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26284  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
26285  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
26286  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
26287  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
26288  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
26289  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
26290  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
26291  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
26292  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
26293  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
26294  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
26295  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
26296  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
26297  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
26298  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
26299  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
26300  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
26301  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
26302  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
26303  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
26304  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
26305  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
26306  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
26307  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
26308  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
26309  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
26310  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
26311  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
26312  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
26313  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
26314  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
26315  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
26316  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
26317  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
26318  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
26319  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
26320  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
26321  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
26322  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
26323  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
26324  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
26325  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
26326  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
26327  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
26328  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
26329  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
26330  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
26331  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
26332  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
26333  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
26334  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
26335  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
26336  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
26337  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
26338  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
26339  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
26340  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
26341 };
26342 
26348 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
26349 {
26350  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26351  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
26352  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26353  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
26354  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26355  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
26356  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
26357  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
26358  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
26359  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
26360  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
26361  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
26362  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
26363  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
26364  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
26365  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
26366  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
26367  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
26368  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
26369  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
26370  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
26371  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
26372  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
26373  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
26374  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
26375  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
26376  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
26377  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
26378  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
26379  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
26380 };
26381 
26387 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS] =
26388 {
26389  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26390  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_WIDTH },
26391  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26392  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_WIDTH },
26393  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26394  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_WIDTH },
26395  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
26396  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_WIDTH },
26397  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
26398  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_WIDTH },
26399  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
26400  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_WIDTH },
26401  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
26402  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_WIDTH },
26403  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
26404  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_WIDTH },
26405  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
26406  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_WIDTH },
26407  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
26408  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_WIDTH },
26409  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
26410  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_WIDTH },
26411  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
26412  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_WIDTH },
26413  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
26414  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_WIDTH },
26415 };
26416 
26422 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS] =
26423 {
26424  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26425  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
26426  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26427  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
26428  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26429  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
26430 };
26431 
26437 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
26438 {
26439  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
26440  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
26441  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
26442  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
26443  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
26444  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
26445  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
26446  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
26447  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
26448  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
26449  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
26450  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
26451 };
26452 
26457 static const SDL_MemConfig_t SDL_PCIE0_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES] =
26458 {
26459  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
26460  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
26461  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
26462  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
26463  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
26464  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
26465  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
26466  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
26467  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
26468  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
26469  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
26470  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
26471  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
26472  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
26473  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
26474  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
26475  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
26476  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
26477  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
26478  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
26479  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
26480 };
26481 
26486 static const SDL_MemConfig_t SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries[SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
26487 {
26488  { SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
26489  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
26490  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
26491 };
26492 
26497 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES] =
26498 {
26499  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
26500  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
26501  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
26502 };
26503 
26508 static const SDL_MemConfig_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES] =
26509 {
26510  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
26511  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
26512  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
26513  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
26514  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
26515  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
26516  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
26517  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
26518  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
26519  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
26520  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
26521  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
26522  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
26523  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
26524  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
26525  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
26526  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
26527  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
26528  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
26529  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
26530  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
26531  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
26532  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
26533  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
26534 };
26535 
26541 static const SDL_GrpChkConfig_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS] =
26542 {
26543  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
26544  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_WIDTH },
26545  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
26546  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_WIDTH },
26547  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
26548  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_WIDTH },
26549  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
26550  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_WIDTH },
26551  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
26552  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_WIDTH },
26553  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
26554  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_WIDTH },
26555  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
26556  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_WIDTH },
26557  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
26558  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_WIDTH },
26559  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
26560  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_WIDTH },
26561  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
26562  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_WIDTH },
26563  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
26564  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_WIDTH },
26565  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
26566  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_WIDTH },
26567  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
26568  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_WIDTH },
26569  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
26570  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_WIDTH },
26571  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
26572  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_WIDTH },
26573  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
26574  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_WIDTH },
26575 };
26576 
26581 static const SDL_MemConfig_t SDL_I3C0_I3C_S_ECC_AGGR_MemEntries[SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
26582 {
26583  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID, 0u,
26584  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
26585  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
26586  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID, 0u,
26587  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
26588  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
26589  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID, 0u,
26590  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
26591  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
26592  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID, 0u,
26593  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
26594  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
26595  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID, 0u,
26596  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_SIZE, 4u,
26597  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_ROW_WIDTH, ((bool)false) },
26598  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID, 0u,
26599  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_SIZE, 4u,
26600  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
26601  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID, 0u,
26602  SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_SIZE, 4u,
26603  SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
26604  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID, 0u,
26605  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_SIZE, 4u,
26606  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
26607  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID, 0u,
26608  SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_SIZE, 4u,
26609  SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
26610 };
26611 
26616 static const SDL_MemConfig_t SDL_VPAC0_ECC_AGGR_MemEntries[SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
26617 {
26618  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID, 0u,
26619  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_SIZE, 4u,
26620  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_ROW_WIDTH, ((bool)false) },
26621  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID, 0u,
26622  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_SIZE, 4u,
26623  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_ROW_WIDTH, ((bool)false) },
26624  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID, 0u,
26625  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_SIZE, 4u,
26626  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_ROW_WIDTH, ((bool)false) },
26627  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID, 0u,
26628  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_SIZE, 4u,
26629  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_ROW_WIDTH, ((bool)false) },
26630  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_ID, 0u,
26631  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_SIZE, 4u,
26632  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_ROW_WIDTH, ((bool)false) },
26633  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID, 0u,
26634  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_SIZE, 4u,
26635  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_RESPONSE_BUFFER0_ROW_WIDTH, ((bool)false) },
26636  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID, 0u,
26637  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_SIZE, 4u,
26638  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER0_ROW_WIDTH, ((bool)false) },
26639  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID, 0u,
26640  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_SIZE, 4u,
26641  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER1_ROW_WIDTH, ((bool)false) },
26642  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID, 0u,
26643  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_SIZE, 4u,
26644  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER2_ROW_WIDTH, ((bool)false) },
26645  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_STATE_BUFFER0_RAM_ID, 0u,
26646  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_STATE_BUFFER0_RAM_SIZE, 4u,
26647  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_STATE_BUFFER0_ROW_WIDTH, ((bool)false) },
26648 };
26649 
26655 static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
26656 {
26657  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
26658  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
26659  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
26660  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
26661  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
26662  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
26663  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
26664  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
26665  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
26666  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_4_WIDTH },
26667  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
26668  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_5_WIDTH },
26669  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
26670  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_6_WIDTH },
26671  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
26672  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_7_WIDTH },
26673  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
26674  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_8_WIDTH },
26675  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
26676  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_9_WIDTH },
26677  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
26678  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_10_WIDTH },
26679  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
26680  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_11_WIDTH },
26681  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
26682  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_12_WIDTH },
26683  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
26684  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_13_WIDTH },
26685  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
26686  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_14_WIDTH },
26687  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
26688  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_15_WIDTH },
26689  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
26690  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_16_WIDTH },
26691  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
26692  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_17_WIDTH },
26693  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
26694  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_18_WIDTH },
26695  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
26696  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_19_WIDTH },
26697  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
26698  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_20_WIDTH },
26699  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
26700  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_21_WIDTH },
26701  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
26702  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_22_WIDTH },
26703  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
26704  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_23_WIDTH },
26705  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
26706  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_24_WIDTH },
26707  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
26708  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_25_WIDTH },
26709  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
26710  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_26_WIDTH },
26711  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
26712  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_27_WIDTH },
26713  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
26714  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_28_WIDTH },
26715  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
26716  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_29_WIDTH },
26717  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
26718  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_30_WIDTH },
26719  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
26720  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_31_WIDTH },
26721  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
26722  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_32_WIDTH },
26723  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
26724  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_33_WIDTH },
26725  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
26726  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_34_WIDTH },
26727  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
26728  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_35_WIDTH },
26729  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
26730  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_36_WIDTH },
26731  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
26732  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_37_WIDTH },
26733  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
26734  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_38_WIDTH },
26735  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
26736  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_39_WIDTH },
26737  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
26738  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_40_WIDTH },
26739  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
26740  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_41_WIDTH },
26741  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
26742  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_42_WIDTH },
26743  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
26744  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_43_WIDTH },
26745  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
26746  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_44_WIDTH },
26747 };
26748 
26754 static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
26755 {
26756  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
26757  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
26758  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
26759  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
26760  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
26761  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
26762  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
26763  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
26764  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
26765  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_WIDTH },
26766  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
26767  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_WIDTH },
26768  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
26769  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_WIDTH },
26770  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
26771  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_WIDTH },
26772  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
26773  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_WIDTH },
26774  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
26775  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_WIDTH },
26776  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
26777  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_WIDTH },
26778  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
26779  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_WIDTH },
26780  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
26781  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_WIDTH },
26782  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
26783  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_WIDTH },
26784  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
26785  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_WIDTH },
26786  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
26787  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_WIDTH },
26788  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
26789  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_WIDTH },
26790  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
26791  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_WIDTH },
26792  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
26793  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_WIDTH },
26794  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
26795  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_WIDTH },
26796  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
26797  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_WIDTH },
26798  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
26799  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_WIDTH },
26800  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
26801  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_WIDTH },
26802  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
26803  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_WIDTH },
26804  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
26805  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_WIDTH },
26806  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
26807  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_WIDTH },
26808  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
26809  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_WIDTH },
26810  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
26811  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_WIDTH },
26812  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
26813  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_WIDTH },
26814  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
26815  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_WIDTH },
26816  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
26817  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_WIDTH },
26818 };
26819 
26825 static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
26826 {
26827  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
26828  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
26829  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
26830  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
26831  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
26832  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
26833  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
26834  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
26835  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
26836  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_4_WIDTH },
26837  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
26838  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_5_WIDTH },
26839  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
26840  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_6_WIDTH },
26841  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
26842  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_7_WIDTH },
26843  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
26844  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_8_WIDTH },
26845  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
26846  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_9_WIDTH },
26847  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
26848  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_10_WIDTH },
26849  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
26850  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_11_WIDTH },
26851  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
26852  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_12_WIDTH },
26853  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
26854  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_13_WIDTH },
26855  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
26856  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_14_WIDTH },
26857  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
26858  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_15_WIDTH },
26859  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
26860  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_16_WIDTH },
26861  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
26862  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_17_WIDTH },
26863  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
26864  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_18_WIDTH },
26865  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
26866  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_19_WIDTH },
26867  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
26868  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_20_WIDTH },
26869  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
26870  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_21_WIDTH },
26871  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
26872  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_22_WIDTH },
26873  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
26874  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_23_WIDTH },
26875  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
26876  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_24_WIDTH },
26877  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
26878  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_25_WIDTH },
26879  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
26880  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_26_WIDTH },
26881  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
26882  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_27_WIDTH },
26883  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
26884  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_28_WIDTH },
26885  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
26886  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_29_WIDTH },
26887  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
26888  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_30_WIDTH },
26889  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
26890  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_31_WIDTH },
26891  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
26892  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_32_WIDTH },
26893  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
26894  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_33_WIDTH },
26895  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
26896  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_34_WIDTH },
26897  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
26898  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_35_WIDTH },
26899  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
26900  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_36_WIDTH },
26901  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
26902  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_37_WIDTH },
26903  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
26904  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_38_WIDTH },
26905  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
26906  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_39_WIDTH },
26907  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
26908  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_40_WIDTH },
26909  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
26910  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_41_WIDTH },
26911  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
26912  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_42_WIDTH },
26913  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
26914  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_43_WIDTH },
26915  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
26916  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_GROUP_44_WIDTH },
26917 };
26918 
26924 static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
26925 {
26926  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
26927  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
26928  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
26929  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
26930  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
26931  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
26932  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
26933  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
26934  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
26935  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_WIDTH },
26936  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
26937  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_WIDTH },
26938  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
26939  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_WIDTH },
26940  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
26941  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_WIDTH },
26942  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
26943  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_WIDTH },
26944  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
26945  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_WIDTH },
26946  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
26947  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_WIDTH },
26948  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
26949  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_WIDTH },
26950  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
26951  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_WIDTH },
26952  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
26953  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_WIDTH },
26954  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
26955  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_WIDTH },
26956  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
26957  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_WIDTH },
26958  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
26959  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_WIDTH },
26960  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
26961  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_WIDTH },
26962  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
26963  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_WIDTH },
26964  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
26965  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_WIDTH },
26966  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
26967  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_WIDTH },
26968  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
26969  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_WIDTH },
26970  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
26971  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_WIDTH },
26972  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
26973  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_WIDTH },
26974  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
26975  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_WIDTH },
26976  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
26977  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_WIDTH },
26978  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
26979  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_WIDTH },
26980  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
26981  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_WIDTH },
26982  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
26983  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_WIDTH },
26984  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
26985  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_WIDTH },
26986  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
26987  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_WIDTH },
26988 };
26989 
26994 static const SDL_MemConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_MemEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
26995 {
26996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_TABLE_ECC_RAM_ID, 0u,
26997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_TABLE_ECC_RAM_SIZE, 4u,
26998  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_TABLE_ECC_ROW_WIDTH, ((bool)false) },
26999  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_TABLE_ECC_RAM_ID, 0u,
27000  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_TABLE_ECC_RAM_SIZE, 4u,
27001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_TABLE_ECC_ROW_WIDTH, ((bool)false) },
27002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_TABLE_ECC_RAM_ID, 0u,
27003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_TABLE_ECC_RAM_SIZE, 4u,
27004  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_TABLE_ECC_ROW_WIDTH, ((bool)false) },
27005  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_TABLE_ECC_RAM_ID, 0u,
27006  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_TABLE_ECC_RAM_SIZE, 4u,
27007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_TABLE_ECC_ROW_WIDTH, ((bool)false) },
27008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_TABLE_ECC_RAM_ID, 0u,
27009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_TABLE_ECC_RAM_SIZE, 4u,
27010  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_TABLE_ECC_ROW_WIDTH, ((bool)false) },
27011  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_RAM_ID, 0u,
27012  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_RAM_SIZE, 4u,
27013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_ROW_WIDTH, ((bool)false) },
27014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_TLBIF_TLB_BANK_RAM_ID, 0u,
27015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_TLBIF_TLB_BANK_RAM_SIZE, 4u,
27016  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_TLBIF_TLB_BANK_ROW_WIDTH, ((bool)false) },
27017  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_TLBIF_TLB_BANK_RAM_ID, 0u,
27018  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_TLBIF_TLB_BANK_RAM_SIZE, 4u,
27019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_TLBIF_TLB_BANK_ROW_WIDTH, ((bool)false) },
27020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X594_RAM_ID, 0u,
27021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X594_RAM_SIZE, 4u,
27022  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X594_ROW_WIDTH, ((bool)false) },
27023  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_1_RAM_ID, 0u,
27024  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_1_RAM_SIZE, 4u,
27025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_1_ROW_WIDTH, ((bool)false) },
27026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_2_RAM_ID, 0u,
27027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_2_RAM_SIZE, 4u,
27028  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_2_ROW_WIDTH, ((bool)false) },
27029  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_3_RAM_ID, 0u,
27030  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_3_RAM_SIZE, 4u,
27031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_3_ROW_WIDTH, ((bool)false) },
27032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_4_RAM_ID, 0u,
27033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_4_RAM_SIZE, 4u,
27034  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_4_ROW_WIDTH, ((bool)false) },
27035  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_1_RAM_ID, 0u,
27036  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_1_RAM_SIZE, 4u,
27037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_1_ROW_WIDTH, ((bool)false) },
27038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_2_RAM_ID, 0u,
27039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_2_RAM_SIZE, 4u,
27040  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_2_ROW_WIDTH, ((bool)false) },
27041  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_3_RAM_ID, 0u,
27042  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_3_RAM_SIZE, 4u,
27043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_3_ROW_WIDTH, ((bool)false) },
27044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_4_RAM_ID, 0u,
27045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_4_RAM_SIZE, 4u,
27046  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_4_ROW_WIDTH, ((bool)false) },
27047  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X142_RAM_ID, 0u,
27048  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X142_RAM_SIZE, 4u,
27049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X142_ROW_WIDTH, ((bool)false) },
27050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X294_RAM_ID, 0u,
27051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X294_RAM_SIZE, 4u,
27052  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X294_ROW_WIDTH, ((bool)false) },
27053  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4608X68_RAM_ID, 0u,
27054  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4608X68_RAM_SIZE, 4u,
27055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4608X68_ROW_WIDTH, ((bool)false) },
27056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_1_RAM_ID, 0u,
27057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_1_RAM_SIZE, 4u,
27058  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_1_ROW_WIDTH, ((bool)false) },
27059  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_2_RAM_ID, 0u,
27060  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_2_RAM_SIZE, 4u,
27061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_2_ROW_WIDTH, ((bool)false) },
27062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_3_RAM_ID, 0u,
27063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_3_RAM_SIZE, 4u,
27064  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_3_ROW_WIDTH, ((bool)false) },
27065  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_4_RAM_ID, 0u,
27066  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_4_RAM_SIZE, 4u,
27067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_4_ROW_WIDTH, ((bool)false) },
27068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_1_RAM_ID, 0u,
27069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_1_RAM_SIZE, 4u,
27070  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_1_ROW_WIDTH, ((bool)false) },
27071  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_2_RAM_ID, 0u,
27072  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_2_RAM_SIZE, 4u,
27073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_2_ROW_WIDTH, ((bool)false) },
27074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_3_RAM_ID, 0u,
27075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_3_RAM_SIZE, 4u,
27076  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_3_ROW_WIDTH, ((bool)false) },
27077  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_4_RAM_ID, 0u,
27078  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_4_RAM_SIZE, 4u,
27079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_4_ROW_WIDTH, ((bool)false) },
27080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_ID, 0u,
27081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_SIZE, 4u,
27082  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_CFIFO_WRAP_CFIFO_IFIFO_BUF_ROW_WIDTH, ((bool)false) },
27083  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_ID, 0u,
27084  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_SIZE, 4u,
27085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_WFIFO_WRAP_WFIFO_IFIFO_BUF_ROW_WIDTH, ((bool)false) },
27086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_ID, 0u,
27087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_SIZE, 4u,
27088  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_CFIFO_WRAP_CFIFO_IFIFO_BUF_ROW_WIDTH, ((bool)false) },
27089  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_ID, 0u,
27090  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_SIZE, 4u,
27091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_WFIFO_WRAP_WFIFO_IFIFO_BUF_ROW_WIDTH, ((bool)false) },
27092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_ID, 0u,
27093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_SIZE, 4u,
27094  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_CFIFO_WRAP_CFIFO_IFIFO_BUF_ROW_WIDTH, ((bool)false) },
27095  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_ID, 0u,
27096  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_SIZE, 4u,
27097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_WFIFO_WRAP_WFIFO_IFIFO_BUF_ROW_WIDTH, ((bool)false) },
27098 };
27099 
27105 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
27106 {
27107  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
27108  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
27109  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
27110  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
27111  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
27112  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
27113  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
27114  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
27115  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
27116  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
27117  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
27118  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
27119 };
27120 
27126 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
27127 {
27128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
27129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_0_WIDTH },
27130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
27131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_1_WIDTH },
27132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
27133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_2_WIDTH },
27134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
27135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_3_WIDTH },
27136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
27137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_4_WIDTH },
27138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
27139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_5_WIDTH },
27140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
27141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_6_WIDTH },
27142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
27143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_7_WIDTH },
27144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
27145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_8_WIDTH },
27146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
27147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_9_WIDTH },
27148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
27149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_10_WIDTH },
27150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
27151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_11_WIDTH },
27152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
27153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_12_WIDTH },
27154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
27155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_13_WIDTH },
27156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
27157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_14_WIDTH },
27158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
27159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_15_WIDTH },
27160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
27161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_16_WIDTH },
27162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
27163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_17_WIDTH },
27164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
27165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_18_WIDTH },
27166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
27167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_19_WIDTH },
27168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
27169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_20_WIDTH },
27170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
27171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_21_WIDTH },
27172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
27173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_22_WIDTH },
27174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
27175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_23_WIDTH },
27176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
27177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_24_WIDTH },
27178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
27179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_25_WIDTH },
27180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
27181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_26_WIDTH },
27182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
27183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_27_WIDTH },
27184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
27185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_28_WIDTH },
27186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
27187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_29_WIDTH },
27188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
27189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_30_WIDTH },
27190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
27191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_31_WIDTH },
27192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
27193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_32_WIDTH },
27194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
27195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_33_WIDTH },
27196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
27197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_34_WIDTH },
27198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
27199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_35_WIDTH },
27200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
27201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_36_WIDTH },
27202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
27203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_37_WIDTH },
27204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
27205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_38_WIDTH },
27206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
27207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_39_WIDTH },
27208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
27209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_40_WIDTH },
27210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
27211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_41_WIDTH },
27212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
27213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_42_WIDTH },
27214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
27215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_43_WIDTH },
27216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
27217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_44_WIDTH },
27218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
27219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_45_WIDTH },
27220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
27221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_46_WIDTH },
27222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
27223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_47_WIDTH },
27224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
27225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_48_WIDTH },
27226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
27227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_49_WIDTH },
27228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
27229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_50_WIDTH },
27230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
27231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_51_WIDTH },
27232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
27233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_52_WIDTH },
27234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
27235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_53_WIDTH },
27236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
27237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_54_WIDTH },
27238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
27239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_55_WIDTH },
27240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
27241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_56_WIDTH },
27242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
27243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_57_WIDTH },
27244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
27245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_58_WIDTH },
27246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
27247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_59_WIDTH },
27248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
27249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_60_WIDTH },
27250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
27251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_61_WIDTH },
27252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
27253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_62_WIDTH },
27254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
27255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_63_WIDTH },
27256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
27257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_64_WIDTH },
27258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
27259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_65_WIDTH },
27260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
27261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_66_WIDTH },
27262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
27263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_67_WIDTH },
27264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
27265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_68_WIDTH },
27266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
27267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_69_WIDTH },
27268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
27269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_70_WIDTH },
27270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
27271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_71_WIDTH },
27272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
27273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_72_WIDTH },
27274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
27275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_73_WIDTH },
27276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
27277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_74_WIDTH },
27278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
27279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_75_WIDTH },
27280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
27281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_76_WIDTH },
27282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
27283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_77_WIDTH },
27284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
27285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_78_WIDTH },
27286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
27287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_79_WIDTH },
27288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
27289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_80_WIDTH },
27290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
27291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_81_WIDTH },
27292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
27293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_82_WIDTH },
27294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
27295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_83_WIDTH },
27296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
27297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_84_WIDTH },
27298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
27299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_85_WIDTH },
27300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
27301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_86_WIDTH },
27302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
27303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_87_WIDTH },
27304  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
27305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_88_WIDTH },
27306  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
27307  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_89_WIDTH },
27308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
27309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_90_WIDTH },
27310  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
27311  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_91_WIDTH },
27312  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
27313  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_92_WIDTH },
27314  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
27315  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_93_WIDTH },
27316  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
27317  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_94_WIDTH },
27318  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
27319  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_95_WIDTH },
27320  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
27321  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_96_WIDTH },
27322  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
27323  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_97_WIDTH },
27324  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
27325  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_98_WIDTH },
27326  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
27327  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_99_WIDTH },
27328  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
27329  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_100_WIDTH },
27330  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
27331  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_101_WIDTH },
27332  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
27333  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_102_WIDTH },
27334  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
27335  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_103_WIDTH },
27336  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
27337  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_104_WIDTH },
27338  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
27339  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_105_WIDTH },
27340  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
27341  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_106_WIDTH },
27342  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
27343  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_107_WIDTH },
27344  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
27345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_108_WIDTH },
27346  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
27347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_109_WIDTH },
27348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
27349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_110_WIDTH },
27350  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
27351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_111_WIDTH },
27352  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
27353  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_112_WIDTH },
27354  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
27355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_113_WIDTH },
27356  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
27357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_114_WIDTH },
27358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
27359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_115_WIDTH },
27360  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
27361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_116_WIDTH },
27362  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
27363  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_117_WIDTH },
27364  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
27365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_118_WIDTH },
27366  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
27367  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_119_WIDTH },
27368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
27369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_120_WIDTH },
27370  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
27371  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_121_WIDTH },
27372  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
27373  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_122_WIDTH },
27374  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
27375  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_123_WIDTH },
27376  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
27377  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_124_WIDTH },
27378  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
27379  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_125_WIDTH },
27380  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
27381  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_126_WIDTH },
27382  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
27383  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_127_WIDTH },
27384  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
27385  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_128_WIDTH },
27386  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
27387  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_129_WIDTH },
27388  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
27389  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_130_WIDTH },
27390  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
27391  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_131_WIDTH },
27392  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
27393  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_132_WIDTH },
27394  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
27395  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_133_WIDTH },
27396  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
27397  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_134_WIDTH },
27398  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
27399  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_135_WIDTH },
27400  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
27401  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_136_WIDTH },
27402  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
27403  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_137_WIDTH },
27404  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
27405  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_138_WIDTH },
27406  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
27407  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_139_WIDTH },
27408  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
27409  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_140_WIDTH },
27410  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
27411  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_141_WIDTH },
27412  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
27413  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_142_WIDTH },
27414  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
27415  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_143_WIDTH },
27416  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
27417  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_144_WIDTH },
27418  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
27419  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_145_WIDTH },
27420  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
27421  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_146_WIDTH },
27422  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
27423  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_147_WIDTH },
27424  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
27425  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_148_WIDTH },
27426  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
27427  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_149_WIDTH },
27428  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
27429  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_150_WIDTH },
27430  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
27431  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_151_WIDTH },
27432  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
27433  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_152_WIDTH },
27434  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
27435  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_153_WIDTH },
27436  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
27437  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_154_WIDTH },
27438  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
27439  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_155_WIDTH },
27440  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
27441  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_156_WIDTH },
27442  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
27443  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_157_WIDTH },
27444  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
27445  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_158_WIDTH },
27446  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
27447  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_159_WIDTH },
27448  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
27449  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_160_WIDTH },
27450  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
27451  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_161_WIDTH },
27452  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
27453  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_162_WIDTH },
27454  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
27455  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_163_WIDTH },
27456  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
27457  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_164_WIDTH },
27458  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
27459  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_GROUP_165_WIDTH },
27460 };
27461 
27467 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_MAX_NUM_CHECKERS] =
27468 {
27469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
27470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_0_WIDTH },
27471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
27472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_1_WIDTH },
27473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
27474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_2_WIDTH },
27475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
27476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_3_WIDTH },
27477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
27478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_4_WIDTH },
27479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
27480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_5_WIDTH },
27481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
27482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_6_WIDTH },
27483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
27484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_7_WIDTH },
27485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
27486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_8_WIDTH },
27487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
27488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_9_WIDTH },
27489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
27490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_10_WIDTH },
27491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
27492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_11_WIDTH },
27493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
27494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_12_WIDTH },
27495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
27496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_13_WIDTH },
27497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
27498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_14_WIDTH },
27499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
27500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_15_WIDTH },
27501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
27502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_16_WIDTH },
27503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
27504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_17_WIDTH },
27505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
27506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_18_WIDTH },
27507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
27508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_19_WIDTH },
27509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
27510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_20_WIDTH },
27511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
27512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_21_WIDTH },
27513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
27514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_22_WIDTH },
27515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
27516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_23_WIDTH },
27517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
27518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_24_WIDTH },
27519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
27520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_25_WIDTH },
27521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
27522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_26_WIDTH },
27523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
27524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_27_WIDTH },
27525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
27526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_28_WIDTH },
27527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
27528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_29_WIDTH },
27529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
27530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_30_WIDTH },
27531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
27532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_31_WIDTH },
27533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
27534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_32_WIDTH },
27535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
27536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_33_WIDTH },
27537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
27538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_34_WIDTH },
27539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
27540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_35_WIDTH },
27541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
27542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_36_WIDTH },
27543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
27544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_37_WIDTH },
27545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
27546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_38_WIDTH },
27547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
27548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_39_WIDTH },
27549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
27550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_40_WIDTH },
27551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
27552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_41_WIDTH },
27553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
27554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_42_WIDTH },
27555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
27556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_43_WIDTH },
27557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
27558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_44_WIDTH },
27559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
27560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_45_WIDTH },
27561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
27562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_46_WIDTH },
27563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
27564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_47_WIDTH },
27565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
27566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_48_WIDTH },
27567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
27568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_49_WIDTH },
27569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
27570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_50_WIDTH },
27571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
27572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_51_WIDTH },
27573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
27574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_52_WIDTH },
27575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
27576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_53_WIDTH },
27577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
27578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_54_WIDTH },
27579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
27580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_55_WIDTH },
27581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
27582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_56_WIDTH },
27583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
27584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_57_WIDTH },
27585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
27586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_58_WIDTH },
27587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
27588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_59_WIDTH },
27589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
27590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_60_WIDTH },
27591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
27592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_61_WIDTH },
27593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
27594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_62_WIDTH },
27595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
27596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_63_WIDTH },
27597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
27598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_64_WIDTH },
27599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
27600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_65_WIDTH },
27601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
27602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_66_WIDTH },
27603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
27604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_67_WIDTH },
27605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
27606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_68_WIDTH },
27607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
27608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_69_WIDTH },
27609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
27610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_70_WIDTH },
27611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
27612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_71_WIDTH },
27613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
27614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_72_WIDTH },
27615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
27616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_73_WIDTH },
27617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
27618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_74_WIDTH },
27619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
27620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_75_WIDTH },
27621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
27622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_76_WIDTH },
27623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
27624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_77_WIDTH },
27625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
27626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_78_WIDTH },
27627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
27628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_79_WIDTH },
27629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
27630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_80_WIDTH },
27631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
27632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_81_WIDTH },
27633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
27634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_82_WIDTH },
27635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
27636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_83_WIDTH },
27637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
27638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_84_WIDTH },
27639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
27640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_85_WIDTH },
27641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
27642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_86_WIDTH },
27643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
27644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_87_WIDTH },
27645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
27646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_88_WIDTH },
27647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
27648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_89_WIDTH },
27649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
27650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_90_WIDTH },
27651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
27652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_91_WIDTH },
27653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
27654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_92_WIDTH },
27655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
27656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_93_WIDTH },
27657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
27658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_94_WIDTH },
27659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
27660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_95_WIDTH },
27661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
27662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_96_WIDTH },
27663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
27664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_97_WIDTH },
27665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
27666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_98_WIDTH },
27667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
27668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_99_WIDTH },
27669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
27670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_100_WIDTH },
27671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
27672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_101_WIDTH },
27673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
27674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_102_WIDTH },
27675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
27676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_103_WIDTH },
27677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
27678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_104_WIDTH },
27679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
27680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_105_WIDTH },
27681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
27682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_106_WIDTH },
27683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
27684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_107_WIDTH },
27685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
27686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_108_WIDTH },
27687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
27688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_109_WIDTH },
27689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
27690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_110_WIDTH },
27691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
27692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_111_WIDTH },
27693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
27694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_112_WIDTH },
27695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
27696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_113_WIDTH },
27697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
27698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_114_WIDTH },
27699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
27700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_115_WIDTH },
27701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
27702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_116_WIDTH },
27703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
27704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_117_WIDTH },
27705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
27706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_118_WIDTH },
27707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
27708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_119_WIDTH },
27709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
27710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_120_WIDTH },
27711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
27712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_121_WIDTH },
27713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
27714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_122_WIDTH },
27715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
27716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_123_WIDTH },
27717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
27718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_124_WIDTH },
27719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
27720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_125_WIDTH },
27721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
27722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_126_WIDTH },
27723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
27724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_127_WIDTH },
27725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
27726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_128_WIDTH },
27727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
27728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_129_WIDTH },
27729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
27730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_130_WIDTH },
27731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
27732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_131_WIDTH },
27733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
27734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_132_WIDTH },
27735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
27736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_133_WIDTH },
27737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
27738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_134_WIDTH },
27739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
27740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_135_WIDTH },
27741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
27742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_136_WIDTH },
27743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
27744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_137_WIDTH },
27745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
27746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_138_WIDTH },
27747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
27748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_139_WIDTH },
27749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
27750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_140_WIDTH },
27751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
27752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_141_WIDTH },
27753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
27754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_142_WIDTH },
27755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
27756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_143_WIDTH },
27757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
27758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_144_WIDTH },
27759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
27760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_145_WIDTH },
27761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
27762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_146_WIDTH },
27763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
27764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_147_WIDTH },
27765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
27766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_148_WIDTH },
27767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
27768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_149_WIDTH },
27769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
27770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_150_WIDTH },
27771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
27772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_151_WIDTH },
27773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
27774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_152_WIDTH },
27775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
27776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_153_WIDTH },
27777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
27778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_154_WIDTH },
27779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
27780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_155_WIDTH },
27781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
27782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_156_WIDTH },
27783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
27784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_157_WIDTH },
27785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
27786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_158_WIDTH },
27787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
27788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_159_WIDTH },
27789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
27790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_160_WIDTH },
27791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
27792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_161_WIDTH },
27793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
27794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_162_WIDTH },
27795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
27796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_163_WIDTH },
27797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
27798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_164_WIDTH },
27799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
27800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_GROUP_165_WIDTH },
27801 };
27802 
27808 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_MAX_NUM_CHECKERS] =
27809 {
27810  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
27811  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_0_WIDTH },
27812  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
27813  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_1_WIDTH },
27814  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
27815  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_2_WIDTH },
27816  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
27817  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_3_WIDTH },
27818  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
27819  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_4_WIDTH },
27820  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
27821  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_5_WIDTH },
27822  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
27823  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_6_WIDTH },
27824  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
27825  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_7_WIDTH },
27826  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
27827  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_8_WIDTH },
27828  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
27829  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_9_WIDTH },
27830  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
27831  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_10_WIDTH },
27832  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
27833  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_11_WIDTH },
27834  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
27835  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_12_WIDTH },
27836  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
27837  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_13_WIDTH },
27838  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
27839  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_14_WIDTH },
27840  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
27841  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_15_WIDTH },
27842  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
27843  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_16_WIDTH },
27844  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
27845  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_17_WIDTH },
27846  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
27847  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_18_WIDTH },
27848  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
27849  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_19_WIDTH },
27850  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
27851  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_20_WIDTH },
27852  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
27853  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_21_WIDTH },
27854  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
27855  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_22_WIDTH },
27856  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
27857  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_23_WIDTH },
27858  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
27859  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_24_WIDTH },
27860  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
27861  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_25_WIDTH },
27862  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
27863  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_26_WIDTH },
27864  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
27865  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_27_WIDTH },
27866  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
27867  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_28_WIDTH },
27868  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
27869  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_29_WIDTH },
27870  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
27871  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_30_WIDTH },
27872  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
27873  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_31_WIDTH },
27874  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
27875  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_32_WIDTH },
27876  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
27877  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_33_WIDTH },
27878  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
27879  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_34_WIDTH },
27880  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
27881  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_35_WIDTH },
27882  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
27883  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_36_WIDTH },
27884  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
27885  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_37_WIDTH },
27886  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
27887  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_38_WIDTH },
27888  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
27889  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_39_WIDTH },
27890  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
27891  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_40_WIDTH },
27892  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
27893  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_41_WIDTH },
27894  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
27895  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_42_WIDTH },
27896  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
27897  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_43_WIDTH },
27898  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
27899  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_44_WIDTH },
27900  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
27901  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_45_WIDTH },
27902  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
27903  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_46_WIDTH },
27904  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
27905  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_47_WIDTH },
27906  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
27907  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_48_WIDTH },
27908  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
27909  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_49_WIDTH },
27910  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
27911  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_50_WIDTH },
27912  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
27913  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_51_WIDTH },
27914  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
27915  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_52_WIDTH },
27916  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
27917  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_53_WIDTH },
27918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
27919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_54_WIDTH },
27920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
27921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_55_WIDTH },
27922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
27923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_56_WIDTH },
27924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
27925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_57_WIDTH },
27926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
27927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_58_WIDTH },
27928  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
27929  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_59_WIDTH },
27930  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
27931  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_60_WIDTH },
27932  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
27933  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_61_WIDTH },
27934  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
27935  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_62_WIDTH },
27936  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
27937  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_63_WIDTH },
27938  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
27939  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_64_WIDTH },
27940  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
27941  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_65_WIDTH },
27942  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
27943  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_66_WIDTH },
27944  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
27945  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_67_WIDTH },
27946  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
27947  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_68_WIDTH },
27948  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
27949  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_69_WIDTH },
27950  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
27951  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_70_WIDTH },
27952  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
27953  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_71_WIDTH },
27954  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
27955  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_72_WIDTH },
27956  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
27957  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_73_WIDTH },
27958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
27959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_74_WIDTH },
27960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
27961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_75_WIDTH },
27962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
27963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_76_WIDTH },
27964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
27965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_77_WIDTH },
27966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
27967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_78_WIDTH },
27968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
27969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_79_WIDTH },
27970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
27971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_80_WIDTH },
27972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
27973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_81_WIDTH },
27974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
27975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_82_WIDTH },
27976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
27977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_83_WIDTH },
27978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
27979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_84_WIDTH },
27980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
27981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_85_WIDTH },
27982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
27983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_86_WIDTH },
27984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
27985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_87_WIDTH },
27986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
27987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_88_WIDTH },
27988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
27989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_89_WIDTH },
27990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
27991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_90_WIDTH },
27992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
27993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_91_WIDTH },
27994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
27995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_92_WIDTH },
27996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
27997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_93_WIDTH },
27998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
27999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_94_WIDTH },
28000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
28001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_95_WIDTH },
28002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
28003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_96_WIDTH },
28004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
28005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_97_WIDTH },
28006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
28007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_98_WIDTH },
28008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
28009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_99_WIDTH },
28010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
28011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_100_WIDTH },
28012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
28013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_101_WIDTH },
28014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
28015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_102_WIDTH },
28016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
28017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_103_WIDTH },
28018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
28019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_104_WIDTH },
28020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
28021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_105_WIDTH },
28022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
28023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_106_WIDTH },
28024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
28025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_107_WIDTH },
28026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
28027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_108_WIDTH },
28028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
28029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_109_WIDTH },
28030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
28031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_110_WIDTH },
28032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
28033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_111_WIDTH },
28034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
28035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_112_WIDTH },
28036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
28037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_113_WIDTH },
28038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
28039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_114_WIDTH },
28040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
28041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_115_WIDTH },
28042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
28043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_116_WIDTH },
28044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
28045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_117_WIDTH },
28046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
28047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_118_WIDTH },
28048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
28049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_119_WIDTH },
28050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
28051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_120_WIDTH },
28052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
28053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_121_WIDTH },
28054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
28055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_122_WIDTH },
28056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
28057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_123_WIDTH },
28058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
28059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_124_WIDTH },
28060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
28061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_125_WIDTH },
28062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
28063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_126_WIDTH },
28064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
28065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_127_WIDTH },
28066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
28067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_128_WIDTH },
28068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
28069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_129_WIDTH },
28070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
28071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_130_WIDTH },
28072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
28073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_131_WIDTH },
28074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
28075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_132_WIDTH },
28076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
28077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_133_WIDTH },
28078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
28079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_134_WIDTH },
28080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
28081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_135_WIDTH },
28082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
28083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_136_WIDTH },
28084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
28085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_137_WIDTH },
28086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
28087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_138_WIDTH },
28088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
28089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_139_WIDTH },
28090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
28091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_140_WIDTH },
28092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
28093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_141_WIDTH },
28094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
28095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_142_WIDTH },
28096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
28097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_143_WIDTH },
28098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
28099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_144_WIDTH },
28100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
28101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_145_WIDTH },
28102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
28103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_146_WIDTH },
28104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
28105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_147_WIDTH },
28106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
28107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_148_WIDTH },
28108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
28109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_149_WIDTH },
28110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
28111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_150_WIDTH },
28112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
28113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_151_WIDTH },
28114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
28115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_152_WIDTH },
28116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
28117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_153_WIDTH },
28118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
28119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_154_WIDTH },
28120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
28121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_155_WIDTH },
28122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
28123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_156_WIDTH },
28124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
28125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_157_WIDTH },
28126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
28127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_158_WIDTH },
28128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
28129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_159_WIDTH },
28130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
28131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_160_WIDTH },
28132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
28133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_161_WIDTH },
28134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
28135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_162_WIDTH },
28136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
28137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_163_WIDTH },
28138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
28139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_164_WIDTH },
28140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
28141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_GROUP_165_WIDTH },
28142 };
28143 
28149 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_MAX_NUM_CHECKERS] =
28150 {
28151  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
28152  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_0_WIDTH },
28153  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
28154  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_1_WIDTH },
28155  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
28156  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_2_WIDTH },
28157  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
28158  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_3_WIDTH },
28159  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
28160  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_4_WIDTH },
28161  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
28162  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_5_WIDTH },
28163  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
28164  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_6_WIDTH },
28165  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
28166  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_7_WIDTH },
28167  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
28168  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_8_WIDTH },
28169  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
28170  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_9_WIDTH },
28171  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
28172  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_10_WIDTH },
28173  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
28174  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_11_WIDTH },
28175  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
28176  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_12_WIDTH },
28177  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
28178  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_13_WIDTH },
28179  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
28180  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_14_WIDTH },
28181  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
28182  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_15_WIDTH },
28183  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
28184  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_16_WIDTH },
28185  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
28186  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_17_WIDTH },
28187  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
28188  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_18_WIDTH },
28189  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
28190  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_19_WIDTH },
28191  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
28192  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_20_WIDTH },
28193  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
28194  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_21_WIDTH },
28195  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
28196  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_22_WIDTH },
28197  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
28198  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_23_WIDTH },
28199  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
28200  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_24_WIDTH },
28201  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
28202  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_25_WIDTH },
28203  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
28204  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_26_WIDTH },
28205  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
28206  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_27_WIDTH },
28207  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
28208  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_28_WIDTH },
28209  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
28210  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_29_WIDTH },
28211  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
28212  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_30_WIDTH },
28213  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
28214  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_31_WIDTH },
28215  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
28216  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_32_WIDTH },
28217  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
28218  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_33_WIDTH },
28219  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
28220  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_34_WIDTH },
28221  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
28222  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_35_WIDTH },
28223  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
28224  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_36_WIDTH },
28225  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
28226  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_37_WIDTH },
28227  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
28228  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_38_WIDTH },
28229  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
28230  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_39_WIDTH },
28231  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
28232  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_40_WIDTH },
28233  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
28234  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_41_WIDTH },
28235  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
28236  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_42_WIDTH },
28237  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
28238  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_43_WIDTH },
28239  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
28240  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_44_WIDTH },
28241  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
28242  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_45_WIDTH },
28243  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
28244  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_46_WIDTH },
28245  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
28246  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_47_WIDTH },
28247  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
28248  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_48_WIDTH },
28249  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
28250  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_49_WIDTH },
28251  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
28252  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_50_WIDTH },
28253  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
28254  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_51_WIDTH },
28255  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
28256  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_52_WIDTH },
28257  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
28258  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_53_WIDTH },
28259  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
28260  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_54_WIDTH },
28261  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
28262  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_55_WIDTH },
28263  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
28264  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_56_WIDTH },
28265  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
28266  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_57_WIDTH },
28267  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
28268  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_58_WIDTH },
28269  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
28270  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_59_WIDTH },
28271  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
28272  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_60_WIDTH },
28273  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
28274  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_61_WIDTH },
28275  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
28276  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_62_WIDTH },
28277  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
28278  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_63_WIDTH },
28279  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
28280  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_64_WIDTH },
28281  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
28282  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_65_WIDTH },
28283  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
28284  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_66_WIDTH },
28285  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
28286  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_67_WIDTH },
28287  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
28288  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_68_WIDTH },
28289  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
28290  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_69_WIDTH },
28291  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
28292  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_70_WIDTH },
28293  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
28294  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_71_WIDTH },
28295  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
28296  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_72_WIDTH },
28297  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
28298  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_73_WIDTH },
28299  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
28300  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_74_WIDTH },
28301  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
28302  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_75_WIDTH },
28303  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
28304  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_76_WIDTH },
28305  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
28306  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_77_WIDTH },
28307  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
28308  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_78_WIDTH },
28309  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
28310  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_79_WIDTH },
28311  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
28312  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_80_WIDTH },
28313  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
28314  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_81_WIDTH },
28315  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
28316  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_82_WIDTH },
28317  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
28318  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_83_WIDTH },
28319  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
28320  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_84_WIDTH },
28321  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
28322  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_85_WIDTH },
28323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
28324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_86_WIDTH },
28325  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
28326  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_87_WIDTH },
28327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
28328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_88_WIDTH },
28329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
28330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_89_WIDTH },
28331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
28332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_90_WIDTH },
28333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
28334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_91_WIDTH },
28335  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
28336  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_92_WIDTH },
28337  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
28338  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_93_WIDTH },
28339  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
28340  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_94_WIDTH },
28341  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
28342  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_95_WIDTH },
28343  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
28344  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_96_WIDTH },
28345  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
28346  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_97_WIDTH },
28347  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
28348  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_98_WIDTH },
28349  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
28350  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_99_WIDTH },
28351  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
28352  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_100_WIDTH },
28353  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
28354  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_101_WIDTH },
28355  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
28356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_102_WIDTH },
28357  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
28358  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_103_WIDTH },
28359  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
28360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_104_WIDTH },
28361  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
28362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_105_WIDTH },
28363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
28364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_106_WIDTH },
28365  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
28366  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_107_WIDTH },
28367  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
28368  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_108_WIDTH },
28369  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
28370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_109_WIDTH },
28371  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
28372  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_110_WIDTH },
28373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
28374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_111_WIDTH },
28375  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
28376  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_112_WIDTH },
28377  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
28378  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_113_WIDTH },
28379  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
28380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_114_WIDTH },
28381  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
28382  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_115_WIDTH },
28383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
28384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_116_WIDTH },
28385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
28386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_117_WIDTH },
28387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
28388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_118_WIDTH },
28389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
28390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_119_WIDTH },
28391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
28392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_120_WIDTH },
28393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
28394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_121_WIDTH },
28395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
28396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_122_WIDTH },
28397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
28398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_123_WIDTH },
28399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
28400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_124_WIDTH },
28401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
28402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_125_WIDTH },
28403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
28404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_126_WIDTH },
28405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
28406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_127_WIDTH },
28407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
28408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_128_WIDTH },
28409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
28410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_129_WIDTH },
28411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
28412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_130_WIDTH },
28413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
28414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_131_WIDTH },
28415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
28416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_132_WIDTH },
28417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
28418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_133_WIDTH },
28419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
28420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_134_WIDTH },
28421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
28422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_135_WIDTH },
28423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
28424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_136_WIDTH },
28425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
28426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_137_WIDTH },
28427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
28428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_138_WIDTH },
28429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
28430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_139_WIDTH },
28431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
28432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_140_WIDTH },
28433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
28434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_141_WIDTH },
28435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
28436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_142_WIDTH },
28437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
28438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_143_WIDTH },
28439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
28440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_144_WIDTH },
28441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
28442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_145_WIDTH },
28443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
28444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_146_WIDTH },
28445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
28446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_147_WIDTH },
28447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
28448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_148_WIDTH },
28449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
28450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_149_WIDTH },
28451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
28452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_150_WIDTH },
28453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
28454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_151_WIDTH },
28455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
28456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_152_WIDTH },
28457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
28458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_153_WIDTH },
28459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
28460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_154_WIDTH },
28461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
28462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_155_WIDTH },
28463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
28464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_156_WIDTH },
28465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
28466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_157_WIDTH },
28467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
28468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_158_WIDTH },
28469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
28470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_159_WIDTH },
28471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
28472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_160_WIDTH },
28473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
28474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_161_WIDTH },
28475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
28476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_162_WIDTH },
28477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
28478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_163_WIDTH },
28479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
28480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_164_WIDTH },
28481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
28482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_GROUP_165_WIDTH },
28483 };
28484 
28490 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_MAX_NUM_CHECKERS] =
28491 {
28492  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
28493  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_0_WIDTH },
28494  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
28495  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_1_WIDTH },
28496  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
28497  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_2_WIDTH },
28498  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
28499  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_3_WIDTH },
28500  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
28501  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_4_WIDTH },
28502  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
28503  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_5_WIDTH },
28504  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
28505  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_6_WIDTH },
28506  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
28507  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_7_WIDTH },
28508  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
28509  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_8_WIDTH },
28510  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
28511  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_9_WIDTH },
28512  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
28513  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_10_WIDTH },
28514  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
28515  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_11_WIDTH },
28516  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
28517  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_12_WIDTH },
28518  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
28519  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_13_WIDTH },
28520  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
28521  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_14_WIDTH },
28522  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
28523  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_15_WIDTH },
28524  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
28525  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_16_WIDTH },
28526  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
28527  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_17_WIDTH },
28528  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
28529  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_18_WIDTH },
28530  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
28531  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_19_WIDTH },
28532  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
28533  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_20_WIDTH },
28534  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
28535  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_21_WIDTH },
28536  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
28537  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_22_WIDTH },
28538  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
28539  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_23_WIDTH },
28540  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
28541  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_24_WIDTH },
28542  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
28543  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_25_WIDTH },
28544  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
28545  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_26_WIDTH },
28546  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
28547  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_27_WIDTH },
28548  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
28549  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_28_WIDTH },
28550  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
28551  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_29_WIDTH },
28552  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
28553  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_30_WIDTH },
28554  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
28555  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_31_WIDTH },
28556  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
28557  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_32_WIDTH },
28558  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
28559  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_33_WIDTH },
28560  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
28561  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_34_WIDTH },
28562  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
28563  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_35_WIDTH },
28564  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
28565  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_36_WIDTH },
28566  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
28567  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_37_WIDTH },
28568  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
28569  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_38_WIDTH },
28570  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
28571  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_39_WIDTH },
28572  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
28573  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_40_WIDTH },
28574  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
28575  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_41_WIDTH },
28576  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
28577  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_42_WIDTH },
28578  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
28579  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_43_WIDTH },
28580  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
28581  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_44_WIDTH },
28582  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
28583  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_45_WIDTH },
28584  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
28585  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_46_WIDTH },
28586  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
28587  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_47_WIDTH },
28588  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
28589  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_48_WIDTH },
28590  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
28591  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_49_WIDTH },
28592  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
28593  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_50_WIDTH },
28594  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
28595  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_51_WIDTH },
28596  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
28597  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_52_WIDTH },
28598  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
28599  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_53_WIDTH },
28600  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
28601  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_54_WIDTH },
28602  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
28603  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_55_WIDTH },
28604  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
28605  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_56_WIDTH },
28606  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
28607  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_57_WIDTH },
28608  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
28609  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_58_WIDTH },
28610  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
28611  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_59_WIDTH },
28612  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
28613  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_60_WIDTH },
28614  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
28615  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_61_WIDTH },
28616  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
28617  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_62_WIDTH },
28618  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
28619  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_63_WIDTH },
28620  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
28621  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_64_WIDTH },
28622  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
28623  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_65_WIDTH },
28624  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
28625  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_66_WIDTH },
28626  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
28627  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_67_WIDTH },
28628  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
28629  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_68_WIDTH },
28630  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
28631  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_69_WIDTH },
28632  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
28633  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_70_WIDTH },
28634  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
28635  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_71_WIDTH },
28636  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
28637  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_72_WIDTH },
28638  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
28639  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_73_WIDTH },
28640  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
28641  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_74_WIDTH },
28642  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
28643  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_75_WIDTH },
28644  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
28645  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_76_WIDTH },
28646  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
28647  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_77_WIDTH },
28648  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
28649  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_78_WIDTH },
28650  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
28651  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_79_WIDTH },
28652  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
28653  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_80_WIDTH },
28654  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
28655  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_81_WIDTH },
28656  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
28657  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_82_WIDTH },
28658  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
28659  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_83_WIDTH },
28660  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
28661  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_84_WIDTH },
28662  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
28663  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_85_WIDTH },
28664  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
28665  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_86_WIDTH },
28666  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
28667  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_87_WIDTH },
28668  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
28669  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_88_WIDTH },
28670  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
28671  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_89_WIDTH },
28672  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
28673  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_90_WIDTH },
28674  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
28675  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_91_WIDTH },
28676  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
28677  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_92_WIDTH },
28678  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
28679  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_93_WIDTH },
28680  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
28681  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_94_WIDTH },
28682  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
28683  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_95_WIDTH },
28684  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
28685  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_96_WIDTH },
28686  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
28687  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_97_WIDTH },
28688  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
28689  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_98_WIDTH },
28690  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
28691  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_99_WIDTH },
28692  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
28693  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_100_WIDTH },
28694  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
28695  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_101_WIDTH },
28696  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
28697  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_102_WIDTH },
28698  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
28699  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_103_WIDTH },
28700  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
28701  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_104_WIDTH },
28702  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
28703  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_105_WIDTH },
28704  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
28705  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_106_WIDTH },
28706  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
28707  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_107_WIDTH },
28708  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
28709  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_108_WIDTH },
28710  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
28711  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_109_WIDTH },
28712  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
28713  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_110_WIDTH },
28714  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
28715  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_111_WIDTH },
28716  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
28717  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_112_WIDTH },
28718  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
28719  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_113_WIDTH },
28720  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
28721  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_114_WIDTH },
28722  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
28723  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_115_WIDTH },
28724  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
28725  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_116_WIDTH },
28726  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
28727  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_117_WIDTH },
28728  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
28729  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_118_WIDTH },
28730  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
28731  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_119_WIDTH },
28732  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
28733  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_120_WIDTH },
28734  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
28735  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_121_WIDTH },
28736  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
28737  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_122_WIDTH },
28738  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
28739  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_123_WIDTH },
28740  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
28741  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_124_WIDTH },
28742  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
28743  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_125_WIDTH },
28744  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
28745  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_126_WIDTH },
28746  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
28747  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_127_WIDTH },
28748  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
28749  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_128_WIDTH },
28750  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
28751  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_129_WIDTH },
28752  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
28753  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_130_WIDTH },
28754  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
28755  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_131_WIDTH },
28756  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
28757  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_132_WIDTH },
28758  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
28759  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_133_WIDTH },
28760  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
28761  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_134_WIDTH },
28762  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
28763  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_135_WIDTH },
28764  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
28765  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_136_WIDTH },
28766  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
28767  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_137_WIDTH },
28768  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
28769  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_138_WIDTH },
28770  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
28771  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_139_WIDTH },
28772  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
28773  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_140_WIDTH },
28774  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
28775  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_141_WIDTH },
28776  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
28777  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_142_WIDTH },
28778  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
28779  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_143_WIDTH },
28780  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
28781  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_144_WIDTH },
28782  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
28783  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_145_WIDTH },
28784  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
28785  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_146_WIDTH },
28786  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
28787  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_147_WIDTH },
28788  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
28789  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_148_WIDTH },
28790  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
28791  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_149_WIDTH },
28792  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
28793  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_150_WIDTH },
28794  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
28795  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_151_WIDTH },
28796  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
28797  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_152_WIDTH },
28798  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
28799  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_153_WIDTH },
28800  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
28801  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_154_WIDTH },
28802  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
28803  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_155_WIDTH },
28804  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
28805  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_156_WIDTH },
28806  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
28807  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_157_WIDTH },
28808  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
28809  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_158_WIDTH },
28810  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
28811  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_159_WIDTH },
28812  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
28813  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_160_WIDTH },
28814  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
28815  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_161_WIDTH },
28816  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
28817  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_162_WIDTH },
28818  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
28819  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_163_WIDTH },
28820  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
28821  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_164_WIDTH },
28822  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
28823  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_GROUP_165_WIDTH },
28824 };
28825 
28831 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
28832 {
28833  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
28834  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_0_WIDTH },
28835  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
28836  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_1_WIDTH },
28837  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
28838  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_2_WIDTH },
28839  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
28840  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_3_WIDTH },
28841  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
28842  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_4_WIDTH },
28843  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
28844  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_5_WIDTH },
28845  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
28846  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_6_WIDTH },
28847  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
28848  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_7_WIDTH },
28849  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
28850  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_8_WIDTH },
28851  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
28852  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_9_WIDTH },
28853  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
28854  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_10_WIDTH },
28855  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
28856  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_11_WIDTH },
28857  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
28858  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_12_WIDTH },
28859  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
28860  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_13_WIDTH },
28861  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
28862  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_14_WIDTH },
28863  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
28864  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_15_WIDTH },
28865  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
28866  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_16_WIDTH },
28867  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
28868  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_17_WIDTH },
28869  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
28870  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_18_WIDTH },
28871  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
28872  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_19_WIDTH },
28873  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
28874  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_20_WIDTH },
28875  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
28876  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_21_WIDTH },
28877  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
28878  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_22_WIDTH },
28879  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
28880  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_23_WIDTH },
28881  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
28882  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_24_WIDTH },
28883  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
28884  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_25_WIDTH },
28885  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
28886  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_26_WIDTH },
28887  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
28888  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_27_WIDTH },
28889  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
28890  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_28_WIDTH },
28891  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
28892  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_29_WIDTH },
28893  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
28894  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_30_WIDTH },
28895  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
28896  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_31_WIDTH },
28897  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
28898  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_32_WIDTH },
28899  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
28900  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_33_WIDTH },
28901  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
28902  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_34_WIDTH },
28903  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
28904  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_35_WIDTH },
28905  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
28906  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_36_WIDTH },
28907  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
28908  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_37_WIDTH },
28909  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
28910  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_38_WIDTH },
28911  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
28912  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_39_WIDTH },
28913  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
28914  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_40_WIDTH },
28915  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
28916  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_41_WIDTH },
28917  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
28918  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_42_WIDTH },
28919  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
28920  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_43_WIDTH },
28921  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
28922  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_44_WIDTH },
28923  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
28924  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_45_WIDTH },
28925  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
28926  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_46_WIDTH },
28927  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
28928  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_47_WIDTH },
28929  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
28930  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_48_WIDTH },
28931  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
28932  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_49_WIDTH },
28933  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
28934  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_50_WIDTH },
28935  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
28936  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_51_WIDTH },
28937  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
28938  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_52_WIDTH },
28939  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
28940  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_53_WIDTH },
28941  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
28942  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_54_WIDTH },
28943  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
28944  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_55_WIDTH },
28945  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
28946  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_56_WIDTH },
28947  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
28948  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_57_WIDTH },
28949  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
28950  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_58_WIDTH },
28951  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
28952  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_59_WIDTH },
28953  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
28954  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_60_WIDTH },
28955  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
28956  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_61_WIDTH },
28957  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
28958  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_62_WIDTH },
28959  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
28960  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_63_WIDTH },
28961  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
28962  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_64_WIDTH },
28963  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
28964  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_65_WIDTH },
28965  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
28966  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_66_WIDTH },
28967  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
28968  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_67_WIDTH },
28969  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
28970  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_68_WIDTH },
28971  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
28972  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_69_WIDTH },
28973  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
28974  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_70_WIDTH },
28975  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
28976  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_71_WIDTH },
28977  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
28978  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_72_WIDTH },
28979  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
28980  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_73_WIDTH },
28981  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
28982  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_74_WIDTH },
28983  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
28984  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_75_WIDTH },
28985  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
28986  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_76_WIDTH },
28987  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
28988  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_77_WIDTH },
28989  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
28990  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_78_WIDTH },
28991  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
28992  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_79_WIDTH },
28993  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
28994  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_80_WIDTH },
28995  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
28996  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_81_WIDTH },
28997  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
28998  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_82_WIDTH },
28999  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
29000  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_83_WIDTH },
29001  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
29002  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_84_WIDTH },
29003  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
29004  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_85_WIDTH },
29005  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
29006  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_86_WIDTH },
29007  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
29008  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_87_WIDTH },
29009  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
29010  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_88_WIDTH },
29011  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
29012  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_89_WIDTH },
29013  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
29014  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_90_WIDTH },
29015  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
29016  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_91_WIDTH },
29017  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
29018  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_92_WIDTH },
29019  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
29020  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_93_WIDTH },
29021  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
29022  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_94_WIDTH },
29023  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
29024  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_95_WIDTH },
29025  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
29026  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_96_WIDTH },
29027  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
29028  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_97_WIDTH },
29029  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
29030  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_98_WIDTH },
29031  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
29032  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_99_WIDTH },
29033  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
29034  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_100_WIDTH },
29035  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
29036  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_101_WIDTH },
29037  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
29038  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_102_WIDTH },
29039  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
29040  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_103_WIDTH },
29041  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
29042  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_104_WIDTH },
29043  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
29044  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_105_WIDTH },
29045  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
29046  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_106_WIDTH },
29047  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
29048  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_107_WIDTH },
29049  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
29050  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_108_WIDTH },
29051  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
29052  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_109_WIDTH },
29053  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
29054  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_110_WIDTH },
29055  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
29056  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_111_WIDTH },
29057  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
29058  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_112_WIDTH },
29059  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
29060  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_113_WIDTH },
29061  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
29062  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_114_WIDTH },
29063  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
29064  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_115_WIDTH },
29065  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
29066  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_116_WIDTH },
29067  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
29068  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_117_WIDTH },
29069  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
29070  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_118_WIDTH },
29071  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
29072  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_119_WIDTH },
29073  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
29074  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_120_WIDTH },
29075  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
29076  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_121_WIDTH },
29077  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
29078  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_122_WIDTH },
29079  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
29080  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_123_WIDTH },
29081  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
29082  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_124_WIDTH },
29083  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
29084  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_125_WIDTH },
29085  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
29086  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_126_WIDTH },
29087  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
29088  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_127_WIDTH },
29089  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
29090  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_128_WIDTH },
29091  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
29092  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_129_WIDTH },
29093  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
29094  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_130_WIDTH },
29095  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
29096  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_131_WIDTH },
29097  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
29098  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_GROUP_132_WIDTH },
29099 };
29100 
29106 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS] =
29107 {
29108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
29109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_0_WIDTH },
29110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
29111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_1_WIDTH },
29112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
29113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_2_WIDTH },
29114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
29115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_3_WIDTH },
29116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
29117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_4_WIDTH },
29118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
29119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_5_WIDTH },
29120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
29121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_6_WIDTH },
29122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
29123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_7_WIDTH },
29124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
29125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_8_WIDTH },
29126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
29127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_9_WIDTH },
29128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
29129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_10_WIDTH },
29130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
29131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_11_WIDTH },
29132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
29133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_12_WIDTH },
29134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
29135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_13_WIDTH },
29136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
29137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_14_WIDTH },
29138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
29139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_15_WIDTH },
29140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
29141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_16_WIDTH },
29142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
29143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_17_WIDTH },
29144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
29145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_18_WIDTH },
29146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
29147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_19_WIDTH },
29148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
29149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_20_WIDTH },
29150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
29151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_21_WIDTH },
29152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
29153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_22_WIDTH },
29154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
29155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_23_WIDTH },
29156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
29157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_24_WIDTH },
29158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
29159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_25_WIDTH },
29160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
29161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_26_WIDTH },
29162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
29163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_27_WIDTH },
29164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
29165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_28_WIDTH },
29166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
29167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_29_WIDTH },
29168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
29169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_30_WIDTH },
29170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
29171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_31_WIDTH },
29172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
29173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_32_WIDTH },
29174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
29175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_33_WIDTH },
29176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
29177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_34_WIDTH },
29178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
29179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_35_WIDTH },
29180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
29181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_36_WIDTH },
29182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
29183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_37_WIDTH },
29184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
29185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_38_WIDTH },
29186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
29187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_39_WIDTH },
29188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
29189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_40_WIDTH },
29190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
29191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_41_WIDTH },
29192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
29193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_42_WIDTH },
29194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
29195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_43_WIDTH },
29196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
29197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_44_WIDTH },
29198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
29199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_45_WIDTH },
29200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
29201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_46_WIDTH },
29202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
29203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_47_WIDTH },
29204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
29205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_48_WIDTH },
29206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
29207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_49_WIDTH },
29208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
29209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_50_WIDTH },
29210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
29211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_51_WIDTH },
29212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
29213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_52_WIDTH },
29214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
29215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_53_WIDTH },
29216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
29217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_54_WIDTH },
29218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
29219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_55_WIDTH },
29220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
29221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_56_WIDTH },
29222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
29223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_57_WIDTH },
29224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
29225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_58_WIDTH },
29226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
29227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_59_WIDTH },
29228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
29229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_60_WIDTH },
29230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
29231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_61_WIDTH },
29232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
29233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_62_WIDTH },
29234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
29235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_63_WIDTH },
29236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
29237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_64_WIDTH },
29238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
29239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_65_WIDTH },
29240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
29241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_66_WIDTH },
29242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
29243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_67_WIDTH },
29244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
29245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_68_WIDTH },
29246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
29247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_69_WIDTH },
29248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
29249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_70_WIDTH },
29250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
29251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_71_WIDTH },
29252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
29253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_72_WIDTH },
29254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
29255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_73_WIDTH },
29256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
29257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_74_WIDTH },
29258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
29259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_75_WIDTH },
29260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
29261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_76_WIDTH },
29262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
29263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_77_WIDTH },
29264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
29265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_78_WIDTH },
29266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
29267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_79_WIDTH },
29268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
29269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_80_WIDTH },
29270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
29271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_81_WIDTH },
29272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
29273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_82_WIDTH },
29274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
29275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_83_WIDTH },
29276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
29277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_84_WIDTH },
29278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
29279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_85_WIDTH },
29280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
29281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_86_WIDTH },
29282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
29283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_87_WIDTH },
29284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
29285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_88_WIDTH },
29286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
29287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_89_WIDTH },
29288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
29289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_90_WIDTH },
29290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
29291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_91_WIDTH },
29292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
29293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_92_WIDTH },
29294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
29295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_93_WIDTH },
29296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
29297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_94_WIDTH },
29298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
29299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_95_WIDTH },
29300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
29301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_96_WIDTH },
29302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
29303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_97_WIDTH },
29304  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
29305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_98_WIDTH },
29306  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
29307  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_99_WIDTH },
29308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
29309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_100_WIDTH },
29310  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
29311  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_101_WIDTH },
29312  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
29313  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_102_WIDTH },
29314  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
29315  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_103_WIDTH },
29316  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
29317  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_104_WIDTH },
29318  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
29319  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_105_WIDTH },
29320  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
29321  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_106_WIDTH },
29322  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
29323  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_107_WIDTH },
29324  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
29325  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_108_WIDTH },
29326  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
29327  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_109_WIDTH },
29328  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
29329  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_110_WIDTH },
29330  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
29331  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_111_WIDTH },
29332  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
29333  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_112_WIDTH },
29334  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
29335  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_113_WIDTH },
29336  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
29337  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_114_WIDTH },
29338  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
29339  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_115_WIDTH },
29340  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
29341  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_116_WIDTH },
29342  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
29343  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_117_WIDTH },
29344  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
29345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_118_WIDTH },
29346  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
29347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_119_WIDTH },
29348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
29349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_120_WIDTH },
29350  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
29351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_121_WIDTH },
29352  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
29353  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_122_WIDTH },
29354  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
29355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_123_WIDTH },
29356  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
29357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_124_WIDTH },
29358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
29359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_125_WIDTH },
29360  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
29361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_126_WIDTH },
29362  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
29363  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_127_WIDTH },
29364  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
29365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_128_WIDTH },
29366  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
29367  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_129_WIDTH },
29368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
29369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_130_WIDTH },
29370  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
29371  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_131_WIDTH },
29372  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
29373  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_GROUP_132_WIDTH },
29374 };
29375 
29381 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS] =
29382 {
29383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
29384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_0_WIDTH },
29385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
29386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_1_WIDTH },
29387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
29388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_2_WIDTH },
29389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
29390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_3_WIDTH },
29391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
29392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_4_WIDTH },
29393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
29394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_5_WIDTH },
29395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
29396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_6_WIDTH },
29397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
29398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_7_WIDTH },
29399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
29400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_8_WIDTH },
29401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
29402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_9_WIDTH },
29403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
29404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_10_WIDTH },
29405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
29406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_11_WIDTH },
29407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
29408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_12_WIDTH },
29409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
29410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_13_WIDTH },
29411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
29412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_14_WIDTH },
29413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
29414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_15_WIDTH },
29415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
29416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_16_WIDTH },
29417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
29418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_17_WIDTH },
29419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
29420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_18_WIDTH },
29421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
29422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_19_WIDTH },
29423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
29424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_20_WIDTH },
29425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
29426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_21_WIDTH },
29427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
29428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_22_WIDTH },
29429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
29430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_23_WIDTH },
29431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
29432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_24_WIDTH },
29433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
29434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_25_WIDTH },
29435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
29436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_26_WIDTH },
29437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
29438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_27_WIDTH },
29439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
29440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_28_WIDTH },
29441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
29442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_29_WIDTH },
29443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
29444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_30_WIDTH },
29445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
29446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_31_WIDTH },
29447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
29448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_32_WIDTH },
29449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
29450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_33_WIDTH },
29451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
29452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_34_WIDTH },
29453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
29454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_35_WIDTH },
29455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
29456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_36_WIDTH },
29457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
29458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_37_WIDTH },
29459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
29460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_38_WIDTH },
29461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
29462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_39_WIDTH },
29463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
29464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_40_WIDTH },
29465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
29466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_41_WIDTH },
29467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
29468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_42_WIDTH },
29469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
29470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_43_WIDTH },
29471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
29472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_44_WIDTH },
29473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
29474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_45_WIDTH },
29475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
29476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_46_WIDTH },
29477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
29478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_47_WIDTH },
29479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
29480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_48_WIDTH },
29481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
29482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_49_WIDTH },
29483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
29484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_50_WIDTH },
29485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
29486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_51_WIDTH },
29487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
29488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_52_WIDTH },
29489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
29490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_53_WIDTH },
29491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
29492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_54_WIDTH },
29493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
29494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_55_WIDTH },
29495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
29496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_56_WIDTH },
29497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
29498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_57_WIDTH },
29499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
29500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_58_WIDTH },
29501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
29502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_59_WIDTH },
29503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
29504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_60_WIDTH },
29505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
29506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_61_WIDTH },
29507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
29508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_62_WIDTH },
29509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
29510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_63_WIDTH },
29511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
29512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_64_WIDTH },
29513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
29514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_65_WIDTH },
29515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
29516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_66_WIDTH },
29517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
29518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_67_WIDTH },
29519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
29520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_68_WIDTH },
29521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
29522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_69_WIDTH },
29523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
29524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_70_WIDTH },
29525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
29526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_71_WIDTH },
29527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
29528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_72_WIDTH },
29529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
29530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_73_WIDTH },
29531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
29532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_74_WIDTH },
29533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
29534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_75_WIDTH },
29535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
29536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_76_WIDTH },
29537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
29538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_77_WIDTH },
29539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
29540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_78_WIDTH },
29541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
29542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_79_WIDTH },
29543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
29544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_80_WIDTH },
29545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
29546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_81_WIDTH },
29547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
29548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_82_WIDTH },
29549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
29550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_83_WIDTH },
29551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
29552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_84_WIDTH },
29553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
29554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_85_WIDTH },
29555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
29556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_86_WIDTH },
29557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
29558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_87_WIDTH },
29559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
29560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_88_WIDTH },
29561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
29562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_89_WIDTH },
29563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
29564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_90_WIDTH },
29565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
29566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_91_WIDTH },
29567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
29568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_92_WIDTH },
29569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
29570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_93_WIDTH },
29571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
29572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_94_WIDTH },
29573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
29574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_95_WIDTH },
29575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
29576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_96_WIDTH },
29577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
29578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_97_WIDTH },
29579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
29580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_98_WIDTH },
29581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
29582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_99_WIDTH },
29583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
29584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_100_WIDTH },
29585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
29586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_101_WIDTH },
29587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
29588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_102_WIDTH },
29589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
29590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_103_WIDTH },
29591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
29592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_104_WIDTH },
29593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
29594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_105_WIDTH },
29595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
29596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_106_WIDTH },
29597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
29598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_107_WIDTH },
29599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
29600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_108_WIDTH },
29601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
29602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_109_WIDTH },
29603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
29604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_110_WIDTH },
29605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
29606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_111_WIDTH },
29607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
29608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_112_WIDTH },
29609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
29610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_113_WIDTH },
29611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
29612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_114_WIDTH },
29613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
29614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_115_WIDTH },
29615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
29616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_116_WIDTH },
29617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
29618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_117_WIDTH },
29619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
29620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_118_WIDTH },
29621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
29622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_119_WIDTH },
29623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
29624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_120_WIDTH },
29625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
29626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_121_WIDTH },
29627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
29628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_122_WIDTH },
29629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
29630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_123_WIDTH },
29631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
29632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_124_WIDTH },
29633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
29634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_125_WIDTH },
29635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
29636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_126_WIDTH },
29637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
29638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_127_WIDTH },
29639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
29640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_128_WIDTH },
29641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
29642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_129_WIDTH },
29643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
29644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_130_WIDTH },
29645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
29646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_131_WIDTH },
29647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
29648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_GROUP_132_WIDTH },
29649 };
29650 
29656 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS] =
29657 {
29658  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
29659  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_0_WIDTH },
29660  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
29661  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_1_WIDTH },
29662  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
29663  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_2_WIDTH },
29664  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
29665  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_3_WIDTH },
29666  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
29667  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_4_WIDTH },
29668  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
29669  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_5_WIDTH },
29670  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
29671  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_6_WIDTH },
29672  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
29673  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_7_WIDTH },
29674  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
29675  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_8_WIDTH },
29676  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
29677  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_9_WIDTH },
29678  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
29679  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_10_WIDTH },
29680  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
29681  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_11_WIDTH },
29682  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
29683  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_12_WIDTH },
29684  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
29685  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_13_WIDTH },
29686  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
29687  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_14_WIDTH },
29688  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
29689  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_15_WIDTH },
29690  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
29691  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_16_WIDTH },
29692  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
29693  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_17_WIDTH },
29694  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
29695  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_18_WIDTH },
29696  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
29697  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_19_WIDTH },
29698  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
29699  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_20_WIDTH },
29700  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
29701  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_21_WIDTH },
29702  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
29703  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_22_WIDTH },
29704  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
29705  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_23_WIDTH },
29706  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
29707  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_24_WIDTH },
29708  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
29709  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_25_WIDTH },
29710  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
29711  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_26_WIDTH },
29712  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
29713  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_27_WIDTH },
29714  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
29715  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_28_WIDTH },
29716  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
29717  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_29_WIDTH },
29718  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
29719  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_30_WIDTH },
29720  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
29721  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_31_WIDTH },
29722  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
29723  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_32_WIDTH },
29724  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
29725  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_33_WIDTH },
29726  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
29727  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_34_WIDTH },
29728  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
29729  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_35_WIDTH },
29730  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
29731  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_36_WIDTH },
29732  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
29733  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_37_WIDTH },
29734  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
29735  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_38_WIDTH },
29736  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
29737  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_39_WIDTH },
29738  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
29739  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_40_WIDTH },
29740  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
29741  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_41_WIDTH },
29742  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
29743  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_42_WIDTH },
29744  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
29745  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_43_WIDTH },
29746  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
29747  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_44_WIDTH },
29748  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
29749  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_45_WIDTH },
29750  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
29751  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_46_WIDTH },
29752  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
29753  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_47_WIDTH },
29754  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
29755  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_48_WIDTH },
29756  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
29757  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_49_WIDTH },
29758  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
29759  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_50_WIDTH },
29760  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
29761  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_51_WIDTH },
29762  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
29763  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_52_WIDTH },
29764  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
29765  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_GROUP_53_WIDTH },
29766 };
29767 
29773 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS] =
29774 {
29775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
29776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_0_WIDTH },
29777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
29778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_1_WIDTH },
29779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
29780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_2_WIDTH },
29781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
29782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_3_WIDTH },
29783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
29784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_4_WIDTH },
29785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
29786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_5_WIDTH },
29787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
29788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_6_WIDTH },
29789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
29790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_7_WIDTH },
29791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
29792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_8_WIDTH },
29793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
29794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_9_WIDTH },
29795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
29796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_10_WIDTH },
29797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
29798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_11_WIDTH },
29799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
29800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_12_WIDTH },
29801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
29802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_13_WIDTH },
29803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
29804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_14_WIDTH },
29805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
29806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_15_WIDTH },
29807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
29808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_16_WIDTH },
29809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
29810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_17_WIDTH },
29811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
29812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_18_WIDTH },
29813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
29814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_19_WIDTH },
29815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
29816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_20_WIDTH },
29817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
29818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_21_WIDTH },
29819 };
29820 
29826 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS] =
29827 {
29828  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
29829  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_0_WIDTH },
29830  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
29831  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_1_WIDTH },
29832  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
29833  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_2_WIDTH },
29834  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
29835  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_3_WIDTH },
29836  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
29837  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_4_WIDTH },
29838  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
29839  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_5_WIDTH },
29840  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
29841  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_6_WIDTH },
29842  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
29843  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_7_WIDTH },
29844  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
29845  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_8_WIDTH },
29846  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
29847  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_9_WIDTH },
29848  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
29849  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_10_WIDTH },
29850  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
29851  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_11_WIDTH },
29852  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
29853  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_12_WIDTH },
29854  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
29855  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_13_WIDTH },
29856  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
29857  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_14_WIDTH },
29858  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
29859  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_15_WIDTH },
29860  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
29861  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_16_WIDTH },
29862  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
29863  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_17_WIDTH },
29864  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
29865  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_18_WIDTH },
29866  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
29867  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_19_WIDTH },
29868  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
29869  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_20_WIDTH },
29870  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
29871  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_21_WIDTH },
29872  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
29873  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_22_WIDTH },
29874  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
29875  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_23_WIDTH },
29876  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
29877  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_24_WIDTH },
29878  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
29879  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_25_WIDTH },
29880  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
29881  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_26_WIDTH },
29882  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
29883  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_27_WIDTH },
29884  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
29885  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_28_WIDTH },
29886  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
29887  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_29_WIDTH },
29888  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
29889  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_30_WIDTH },
29890 };
29891 
29897 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
29898 {
29899  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
29900  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
29901  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
29902  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
29903  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
29904  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
29905  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
29906  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
29907  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
29908  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
29909  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
29910  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
29911  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
29912  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
29913  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
29914  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
29915  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
29916  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
29917  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
29918  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
29919  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
29920  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
29921  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
29922  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
29923  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
29924  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
29925  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
29926  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
29927  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
29928  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
29929  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
29930  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
29931  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
29932  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
29933  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
29934  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
29935  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
29936  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
29937  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
29938  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
29939  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
29940  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
29941  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
29942  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
29943  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
29944  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
29945  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
29946  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
29947  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
29948  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
29949  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
29950  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
29951  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
29952  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
29953  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
29954  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
29955  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
29956  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
29957  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
29958  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
29959  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
29960  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
29961  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
29962  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
29963  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
29964  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
29965  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
29966  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
29967  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
29968  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
29969  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
29970  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
29971  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
29972  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
29973  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
29974  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
29975  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
29976  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
29977  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
29978  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
29979  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
29980  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
29981 };
29982 
29988 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
29989 {
29990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
29991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_0_WIDTH },
29992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
29993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_1_WIDTH },
29994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
29995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_2_WIDTH },
29996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
29997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_3_WIDTH },
29998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
29999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_4_WIDTH },
30000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_5_WIDTH },
30002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_6_WIDTH },
30004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_7_WIDTH },
30006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_8_WIDTH },
30008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_9_WIDTH },
30010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_10_WIDTH },
30012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_11_WIDTH },
30014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_12_WIDTH },
30016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_13_WIDTH },
30018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_14_WIDTH },
30020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_15_WIDTH },
30022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_16_WIDTH },
30024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_17_WIDTH },
30026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_18_WIDTH },
30028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_19_WIDTH },
30030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_20_WIDTH },
30032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_21_WIDTH },
30034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_22_WIDTH },
30036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_23_WIDTH },
30038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_24_WIDTH },
30040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_25_WIDTH },
30042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_26_WIDTH },
30044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_27_WIDTH },
30046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_28_WIDTH },
30048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
30049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_29_WIDTH },
30050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
30051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_30_WIDTH },
30052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
30053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_31_WIDTH },
30054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
30055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_32_WIDTH },
30056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
30057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_33_WIDTH },
30058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
30059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_34_WIDTH },
30060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
30061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_35_WIDTH },
30062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
30063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_36_WIDTH },
30064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
30065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_37_WIDTH },
30066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
30067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_38_WIDTH },
30068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
30069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_39_WIDTH },
30070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
30071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_40_WIDTH },
30072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
30073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_41_WIDTH },
30074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
30075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_42_WIDTH },
30076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
30077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_43_WIDTH },
30078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
30079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_44_WIDTH },
30080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
30081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_45_WIDTH },
30082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
30083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_46_WIDTH },
30084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
30085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_47_WIDTH },
30086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
30087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_48_WIDTH },
30088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
30089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_49_WIDTH },
30090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
30091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_50_WIDTH },
30092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
30093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_51_WIDTH },
30094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
30095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_52_WIDTH },
30096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
30097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_53_WIDTH },
30098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
30099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_54_WIDTH },
30100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
30101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_55_WIDTH },
30102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
30103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_56_WIDTH },
30104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
30105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_57_WIDTH },
30106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
30107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_58_WIDTH },
30108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
30109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_59_WIDTH },
30110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
30111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_60_WIDTH },
30112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
30113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_61_WIDTH },
30114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
30115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_62_WIDTH },
30116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
30117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_63_WIDTH },
30118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
30119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_64_WIDTH },
30120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
30121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_65_WIDTH },
30122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
30123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_66_WIDTH },
30124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
30125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_67_WIDTH },
30126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
30127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_68_WIDTH },
30128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
30129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_69_WIDTH },
30130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
30131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_70_WIDTH },
30132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
30133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_71_WIDTH },
30134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
30135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_72_WIDTH },
30136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
30137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_73_WIDTH },
30138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
30139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_74_WIDTH },
30140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
30141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_75_WIDTH },
30142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
30143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_76_WIDTH },
30144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
30145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_77_WIDTH },
30146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
30147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_78_WIDTH },
30148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
30149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_79_WIDTH },
30150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
30151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_80_WIDTH },
30152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
30153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_81_WIDTH },
30154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
30155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_82_WIDTH },
30156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
30157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_83_WIDTH },
30158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
30159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_84_WIDTH },
30160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
30161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_85_WIDTH },
30162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
30163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_86_WIDTH },
30164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
30165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_87_WIDTH },
30166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
30167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_88_WIDTH },
30168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
30169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_89_WIDTH },
30170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
30171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_90_WIDTH },
30172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
30173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_91_WIDTH },
30174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
30175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_92_WIDTH },
30176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
30177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_93_WIDTH },
30178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
30179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_94_WIDTH },
30180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
30181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_95_WIDTH },
30182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
30183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_96_WIDTH },
30184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
30185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_97_WIDTH },
30186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
30187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_98_WIDTH },
30188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
30189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_99_WIDTH },
30190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
30191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_100_WIDTH },
30192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
30193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_101_WIDTH },
30194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
30195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_102_WIDTH },
30196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
30197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_103_WIDTH },
30198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
30199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_104_WIDTH },
30200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
30201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_105_WIDTH },
30202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
30203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_106_WIDTH },
30204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
30205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_107_WIDTH },
30206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
30207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_108_WIDTH },
30208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
30209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_109_WIDTH },
30210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
30211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_110_WIDTH },
30212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
30213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_111_WIDTH },
30214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
30215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_112_WIDTH },
30216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
30217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_113_WIDTH },
30218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
30219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_114_WIDTH },
30220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
30221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_115_WIDTH },
30222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
30223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_116_WIDTH },
30224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
30225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_117_WIDTH },
30226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
30227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_118_WIDTH },
30228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
30229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_119_WIDTH },
30230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
30231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_120_WIDTH },
30232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
30233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_121_WIDTH },
30234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
30235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_122_WIDTH },
30236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
30237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_123_WIDTH },
30238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
30239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_124_WIDTH },
30240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
30241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_125_WIDTH },
30242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
30243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_126_WIDTH },
30244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
30245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_127_WIDTH },
30246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
30247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_128_WIDTH },
30248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
30249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_129_WIDTH },
30250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
30251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_130_WIDTH },
30252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
30253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_131_WIDTH },
30254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
30255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_132_WIDTH },
30256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
30257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_133_WIDTH },
30258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
30259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_134_WIDTH },
30260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
30261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_135_WIDTH },
30262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
30263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_136_WIDTH },
30264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
30265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_137_WIDTH },
30266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
30267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_138_WIDTH },
30268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
30269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_139_WIDTH },
30270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
30271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_140_WIDTH },
30272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
30273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_141_WIDTH },
30274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
30275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_142_WIDTH },
30276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
30277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_143_WIDTH },
30278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
30279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_144_WIDTH },
30280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
30281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_GROUP_145_WIDTH },
30282 };
30283 
30289 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30290 {
30291  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30292  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_0_WIDTH },
30293  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30294  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_1_WIDTH },
30295  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30296  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_2_WIDTH },
30297  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30298  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_3_WIDTH },
30299  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30300  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_4_WIDTH },
30301  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30302  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_5_WIDTH },
30303  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30304  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_6_WIDTH },
30305  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30306  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_7_WIDTH },
30307  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30308  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_8_WIDTH },
30309  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30310  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_9_WIDTH },
30311  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30312  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_10_WIDTH },
30313  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30314  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_11_WIDTH },
30315  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30316  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_12_WIDTH },
30317  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30318  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_13_WIDTH },
30319  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30320  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_14_WIDTH },
30321  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30322  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_15_WIDTH },
30323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_16_WIDTH },
30325  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30326  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_17_WIDTH },
30327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_18_WIDTH },
30329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_19_WIDTH },
30331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_20_WIDTH },
30333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_GROUP_21_WIDTH },
30335 };
30336 
30342 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30343 {
30344  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_0_WIDTH },
30346  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_1_WIDTH },
30348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_2_WIDTH },
30350  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_3_WIDTH },
30352  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30353  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_4_WIDTH },
30354  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_5_WIDTH },
30356  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_6_WIDTH },
30358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_7_WIDTH },
30360  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_8_WIDTH },
30362  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30363  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_9_WIDTH },
30364  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_10_WIDTH },
30366  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30367  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_11_WIDTH },
30368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_12_WIDTH },
30370  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30371  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_13_WIDTH },
30372  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30373  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_14_WIDTH },
30374  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30375  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_15_WIDTH },
30376  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30377  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_16_WIDTH },
30378  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30379  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_17_WIDTH },
30380  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30381  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_18_WIDTH },
30382  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30383  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_19_WIDTH },
30384  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30385  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_20_WIDTH },
30386  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30387  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_21_WIDTH },
30388  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30389  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_22_WIDTH },
30390  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30391  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_23_WIDTH },
30392  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30393  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_24_WIDTH },
30394  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30395  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_25_WIDTH },
30396  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30397  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_26_WIDTH },
30398  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30399  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_27_WIDTH },
30400  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30401  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_GROUP_28_WIDTH },
30402 };
30403 
30409 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30410 {
30411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
30413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
30415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
30417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
30419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
30421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
30423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
30425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
30427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
30429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
30431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
30433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
30435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
30437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
30439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
30441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
30443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
30445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
30447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
30449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
30451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
30453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
30455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
30457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
30459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
30461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
30463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
30465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
30467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
30469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
30470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
30471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
30472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
30473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
30474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
30475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
30476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
30477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
30478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
30479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
30480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
30481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
30482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
30483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
30484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
30485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
30486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
30487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
30488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
30489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
30490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
30491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
30492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
30493 };
30494 
30500 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30501 {
30502  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30503  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
30504  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30505  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
30506  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30507  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
30508  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30509  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
30510  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30511  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
30512  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30513  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
30514  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30515  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
30516  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30517  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
30518  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30519  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
30520  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30521  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
30522  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30523  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
30524  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30525  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
30526  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30527  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
30528  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30529  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
30530  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30531  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
30532  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30533  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
30534  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30535  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
30536  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30537  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
30538  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30539  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
30540  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30541  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
30542  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30543  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
30544  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30545  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
30546  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30547  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
30548  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30549  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
30550  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30551  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
30552  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30553  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
30554  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30555  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
30556  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30557  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
30558  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30559  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
30560  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
30561  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
30562  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
30563  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
30564  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
30565  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
30566  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
30567  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
30568  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
30569  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
30570  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
30571  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
30572  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
30573  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
30574  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
30575  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
30576  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
30577  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
30578  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
30579  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
30580  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
30581  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
30582  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
30583  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
30584 };
30585 
30591 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30592 {
30593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
30595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
30597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
30599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
30601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
30603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
30605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
30607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
30609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
30611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
30613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
30615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
30617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
30619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
30621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
30623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
30625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
30627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
30629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
30631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
30633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
30635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
30637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
30639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
30641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
30643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
30645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
30647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
30649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
30651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
30652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
30653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
30654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
30655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
30656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
30657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
30658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
30659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
30660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
30661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
30662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
30663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
30664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
30665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
30666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
30667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
30668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
30669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
30670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
30671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
30672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
30673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
30674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
30675 };
30676 
30682 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30683 {
30684  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30685  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
30686  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30687  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
30688  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30689  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
30690  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30691  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
30692  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30693  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
30694  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30695  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
30696  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30697  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
30698  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30699  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
30700  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30701  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
30702  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30703  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
30704  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30705  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
30706  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30707  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
30708  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30709  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
30710  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30711  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
30712  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30713  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
30714  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30715  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
30716  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30717  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
30718  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30719  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
30720  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30721  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
30722  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30723  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
30724  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30725  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
30726  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30727  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
30728  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30729  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
30730  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30731  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
30732  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30733  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
30734  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30735  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
30736  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30737  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
30738  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30739  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
30740  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30741  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
30742  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
30743  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
30744  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
30745  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
30746  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
30747  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
30748  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
30749  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
30750  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
30751  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
30752  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
30753  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
30754  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
30755  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
30756  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
30757  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
30758  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
30759  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
30760  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
30761  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
30762  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
30763  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
30764  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
30765  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
30766 };
30767 
30773 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30774 {
30775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
30777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
30779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
30781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
30783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
30785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
30787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
30789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
30791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
30793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
30795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
30797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
30799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
30801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
30803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
30805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
30807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
30809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
30811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
30813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
30815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
30817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
30819  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30820  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
30821  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30822  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
30823  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30824  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
30825  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30826  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
30827  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30828  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
30829  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30830  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
30831  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30832  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
30833  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
30834  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
30835  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
30836  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
30837  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
30838  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
30839  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
30840  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
30841  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
30842  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
30843  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
30844  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
30845  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
30846  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
30847  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
30848  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
30849  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
30850  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
30851  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
30852  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
30853  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
30854  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
30855  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
30856  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
30857 };
30858 
30864 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30865 {
30866  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30867  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
30868  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30869  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
30870  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30871  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
30872  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30873  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
30874  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30875  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
30876  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30877  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
30878  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30879  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
30880  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30881  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
30882  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30883  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
30884  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30885  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
30886  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30887  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
30888  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30889  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
30890  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30891  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
30892  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30893  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
30894  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30895  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
30896  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30897  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
30898  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30899  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
30900  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30901  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
30902  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30903  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
30904  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30905  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
30906  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30907  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
30908  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
30909  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
30910  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
30911  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
30912  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
30913  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
30914  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
30915  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
30916  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
30917  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
30918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
30919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
30920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
30921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
30922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
30923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
30924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
30925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
30926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
30927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
30928  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
30929  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
30930  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
30931  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
30932  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
30933  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
30934  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
30935  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
30936  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
30937  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
30938  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
30939  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
30940  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
30941  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
30942  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
30943  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
30944  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
30945  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
30946  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
30947  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
30948 };
30949 
30955 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
30956 {
30957  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
30958  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
30959  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
30960  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
30961  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
30962  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
30963  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
30964  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
30965  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
30966  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
30967  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
30968  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
30969  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
30970  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
30971  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
30972  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
30973  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
30974  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
30975  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
30976  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
30977  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
30978  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
30979  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
30980  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
30981  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
30982  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
30983  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
30984  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
30985  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
30986  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
30987  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
30988  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
30989  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
30990  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
30991  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
30992  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
30993  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
30994  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
30995  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
30996  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
30997  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
30998  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
30999  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31000  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31001  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31002  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31003  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31004  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31005  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31006  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31007  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31008  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31009  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31010  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31011  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31012  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31013  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31014  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31015  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31016  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31017  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31018  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31019  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31020  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31021  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31022  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31023  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31024  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31025  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31026  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31027  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31028  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31029  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31030  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31031  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31032  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31033  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31034  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31035  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31036  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31037  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31038  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31039 };
31040 
31046 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31047 {
31048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31130 };
31131 
31137 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31138 {
31139  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31140  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31141  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31142  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31143  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31144  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31145  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31146  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31147  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31148  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31149  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31150  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31151  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31152  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31153  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31154  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31155  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31156  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31157  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31158  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31159  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31160  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31161  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31162  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31163  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31164  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31165  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31166  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31167  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31168  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31169  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31170  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31171  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31172  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31173  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31174  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31175  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31176  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31177  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31178  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31179  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31180  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31181  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31182  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31183  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31184  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31185  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31186  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31187  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31188  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31189  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31190  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31191  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31192  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31193  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31194  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31195  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31196  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31197  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31198  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31199  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31200  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31201  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31202  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31203  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31204  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31205  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31206  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31207  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31208  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31209  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31210  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31211  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31212  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31213  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31214  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31215  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31216  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31217  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31218  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31219  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31220  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31221 };
31222 
31228 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31229 {
31230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31304  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31306  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31307  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31310  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31311  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31312 };
31313 
31319 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31320 {
31321  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31322  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31325  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31326  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31335  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31336  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31337  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31338  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31339  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31340  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31341  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31342  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31343  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31344  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31345  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31346  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31347  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31348  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31349  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31350  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31351  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31352  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31353  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31354  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31355  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31357  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31358  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31359  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31361  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31365  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31366  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31367  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31368  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31369  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31371  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31372  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31375  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31376  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31377  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31378  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31379  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31381  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31382  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31403 };
31404 
31410 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31411 {
31412  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31413  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31414  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31415  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31416  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31417  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31418  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31419  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31420  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31421  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31422  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31423  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31424  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31425  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31426  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31427  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31428  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31429  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31430  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31431  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31432  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31433  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31434  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31435  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31436  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31437  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31438  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31439  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31440  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31441  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31442  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31443  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31444  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31445  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31446  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31447  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31448  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31449  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31450  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31451  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31452  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31453  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31454  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31455  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31456  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31457  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31458  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31459  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31460  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31461  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31462  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31463  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31464  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31465  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31466  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31467  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31468  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31469  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31470  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31471  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31472  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31473  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31474  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31475  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31476  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31477  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31478  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31479  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31480  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31481  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31482  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31483  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31484  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31485  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31486  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31487  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31488  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31489  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31490  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31491  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31492  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31493  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31494 };
31495 
31501 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31502 {
31503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31585 };
31586 
31592 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31593 {
31594  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31595  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31596  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31597  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31598  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31599  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31600  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31601  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31602  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31603  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31604  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31605  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31606  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31607  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31608  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31609  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31610  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31611  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31612  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31613  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31614  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31615  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31616  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31617  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31618  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31619  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31620  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31621  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31622  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31623  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31624  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31625  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31626  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31627  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31628  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31629  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31630  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31631  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31632  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31633  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31634  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31635  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31636  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31637  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31638  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31639  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31640  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31641  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31642  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31643  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31644  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31645  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31646  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31647  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31648  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31649  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31650  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31651  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31652  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31653  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31654  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31655  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31656  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31657  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31658  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31659  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31660  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31661  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31662  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31663  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31664  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31665  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31666  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31667  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31668  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31669  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31670  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31671  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31672  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31673  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31674  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31675  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31676 };
31677 
31683 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31684 {
31685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31767 };
31768 
31774 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31775 {
31776  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31777  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31778  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31779  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31780  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31781  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31782  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31783  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31784  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31785  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31786  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31787  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31788  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31789  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31790  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31791  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31792  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31793  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31794  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31795  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31796  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31797  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31798  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31799  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31800  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31801  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31802  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31803  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31804  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31805  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31806  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31807  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31808  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31809  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31810  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31811  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31812  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31813  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31814  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31815  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31816  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31817  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31818  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31819  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31820  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31821  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31822  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31823  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31824  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31825  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31826  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31827  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31828  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31829  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31830  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31831  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31832  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31833  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31834  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31835  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31836  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31837  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31838  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31839  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31840  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31841  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31842  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31843  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31844  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31845  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31846  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31847  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31848  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31849  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31850  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31851  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31852  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31853  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31854  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31855  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31856  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31857  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31858 };
31859 
31865 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31866 {
31867  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31868  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31869  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31870  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31871  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31872  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31873  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31874  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31875  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31876  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31877  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31878  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31879  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31880  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31881  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31882  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31883  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31884  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31885  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31886  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31887  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31888  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31889  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31890  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31891  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31892  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31893  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31894  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31895  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31896  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31897  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31898  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31899  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31900  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31901  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31902  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31903  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31904  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31905  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31906  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31907  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31908  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
31909  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
31910  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
31911  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
31912  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
31913  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
31914  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
31915  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
31916  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
31917  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
31918  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
31919  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
31920  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
31921  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
31922  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
31923  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
31924  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
31925  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
31926  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
31927  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
31928  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
31929  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
31930  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
31931  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
31932  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
31933  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
31934  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
31935  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
31936  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
31937  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
31938  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
31939  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
31940  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
31941  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
31942  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
31943  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
31944  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
31945  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
31946  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
31947  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
31948  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
31949 };
31950 
31956 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
31957 {
31958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
31959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
31960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
31961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
31962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
31963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
31964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
31965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
31966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
31967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
31968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
31969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
31970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
31971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
31972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
31973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
31974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
31975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
31976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
31977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
31978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
31979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
31980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
31981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
31982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
31983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
31984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
31985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
31986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
31987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
31988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
31989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
31990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
31991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
31992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
31993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
31994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
31995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
31996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
31997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
31998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
31999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32040 };
32041 
32047 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32048 {
32049  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32050  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32051  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32052  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32053  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32054  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32055  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32056  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32057  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32058  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32059  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32060  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32061  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32062  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32063  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32064  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32065  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32066  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32067  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32068  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32069  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32070  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32071  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32072  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32073  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32074  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32075  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32076  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32077  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32078  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32079  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32080  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32081  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32082  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32083  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32084  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32085  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32086  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32087  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32088  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32089  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32090  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32091  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32092  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32093  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32094  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32095  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32096  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32097  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32098  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32099  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32100  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32101  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32102  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32103  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32104  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32105  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32106  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32107  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32108  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32109  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32110  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32111  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32112  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32113  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32114  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32115  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32116  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32117  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32118  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32119  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32120  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32121  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32122  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32123  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32124  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32125  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32126  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32127  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32128  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32129  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32130  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32131 };
32132 
32138 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32139 {
32140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32222 };
32223 
32229 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32230 {
32231  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32232  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32233  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32234  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32235  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32236  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32237  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32238  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32239  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32240  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32241  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32242  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32243  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32244  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32245  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32246  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32247  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32248  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32249  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32250  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32251  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32252  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32253  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32254  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32255  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32256  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32257  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32258  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32259  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32260  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32261  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32262  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32263  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32264  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32265  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32266  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32267  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32268  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32269  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32270  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32271  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32272  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32273  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32274  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32275  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32276  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32277  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32278  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32279  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32280  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32281  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32282  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32283  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32284  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32285  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32286  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32287  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32288  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32289  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32290  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32291  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32292  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32293  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32294  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32295  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32296  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32297  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32298  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32299  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32300  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32301  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32302  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32303  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32304  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32305  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32306  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32307  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32308  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32309  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32310  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32311  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32312  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32313 };
32314 
32320 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32321 {
32322  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32323  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32324  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32325  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32326  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32327  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32328  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32329  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32330  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32331  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32332  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32333  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32334  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32335  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32336  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32337  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32338  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32339  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32340  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32341  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32342  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32343  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32344  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32346  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32350  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32352  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32353  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32354  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32356  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32360  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32362  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32363  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32364  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32366  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32367  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32370  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32371  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32372  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32373  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32374  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32375  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32376  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32377  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32378  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32379  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32380  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32381  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32382  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32383  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32384  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32385  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32386  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32387  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32388  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32389  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32390  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32391  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32392  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32393  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32394  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32395  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32396  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32397  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32398  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32399  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32400  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32401  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32402  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32403  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32404 };
32405 
32411 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32412 {
32413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32495 };
32496 
32502 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32503 {
32504  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32505  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32506  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32507  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32508  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32509  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32510  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32511  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32512  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32513  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32514  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32515  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32516  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32517  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32518  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32519  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32520  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32521  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32522  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32523  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32524  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32525  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32526  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32527  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32528  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32529  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32530  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32531  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32532  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32533  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32534  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32535  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32536  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32537  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32538  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32539  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32540  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32541  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32542  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32543  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32544  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32545  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32546  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32547  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32548  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32549  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32550  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32551  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32552  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32553  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32554  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32555  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32556  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32557  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32558  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32559  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32560  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32561  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32562  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32563  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32564  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32565  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32566  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32567  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32568  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32569  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32570  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32571  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32572  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32573  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32574  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32575  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32576  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32577  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32578  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32579  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32580  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32581  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32582  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32583  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32584  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32585  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32586 };
32587 
32593 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32594 {
32595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
32597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
32599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
32601 };
32602 
32608 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32609 {
32610  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32611  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32612  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32613  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32614  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32615  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32616  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32617  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32618  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32619  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32620  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32621  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32622  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32623  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32624  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32625  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32626  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32627  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32628  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32629  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32630  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32631  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32632  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32633  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32634  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32635  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32636  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32637  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32638  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32639  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32640  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32641  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32642  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32643  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32644  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32645  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32646  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32647  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32648  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32649  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32650  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32651  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32652  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32653  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32654  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32655  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32656  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32657  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32658  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32659  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32660  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32661  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32662  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32663  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32664  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32665  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32666  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32667  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32668  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32669  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32670  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32671  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32672  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32673  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32674  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32675  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32676  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32677  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32678  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32679  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32680  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32681  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32682  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32683  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32684  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32685  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32686  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32687  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32688  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32689  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32690  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32691  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32692 };
32693 
32699 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32700 {
32701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
32784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
32785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
32786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
32787 };
32788 
32794 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32795 {
32796  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32797  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32798  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32799  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32800  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32801  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32802  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32803  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32804  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32805  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32806  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32807  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32808  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32809  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32810  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32811  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32812  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32813  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32814  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32815  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32816  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32817  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32818  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32819  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32820  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32821  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32822  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32823  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32824  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32825  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32826  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32827  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32828  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32829  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32830  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32831  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32832  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32833  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32834  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32835  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32836  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32837  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32838  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32839  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32840  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32841  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32842  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32843  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32844  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32845  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32846  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32847  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32848  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32849  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32850  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32851  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32852  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32853  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32854  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32855  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32856  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32857  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32858  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32859  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32860  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32861  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32862  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32863  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32864  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32865  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32866  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32867  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32868  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32869  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32870  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32871  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32872  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32873  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32874  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32875  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32876  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32877  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32878  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
32879  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
32880  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
32881  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
32882 };
32883 
32889 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32890 {
32891  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32892  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32893  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32894  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32895  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32896  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32897  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32898  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32899  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32900  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32901  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32902  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32903  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32904  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32905  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32906  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32907  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32908  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
32909  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
32910  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
32911  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
32912  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
32913  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
32914  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
32915  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
32916  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
32917  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
32918  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
32919  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
32920  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
32921  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
32922  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
32923  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
32924  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
32925  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
32926  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
32927  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
32928  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
32929  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
32930  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
32931  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
32932  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
32933  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
32934  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
32935  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
32936  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
32937  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
32938  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
32939  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
32940  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
32941  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
32942  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
32943  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
32944  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
32945  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
32946  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
32947  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
32948  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
32949  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
32950  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
32951  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
32952  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
32953  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
32954  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
32955  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
32956  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
32957  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
32958  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
32959  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
32960  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
32961  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
32962  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
32963  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
32964  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
32965  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
32966  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
32967  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
32968  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
32969  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
32970  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
32971  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
32972  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
32973 };
32974 
32980 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
32981 {
32982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
32983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
32984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
32985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
32986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
32987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
32988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
32989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
32990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
32991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
32992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
32993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
32994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
32995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
32996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
32997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
32998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
32999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33064 };
33065 
33071 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33072 {
33073  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33074  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33075  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33076  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33077  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33078  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33079  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33080  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33081  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33082  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33083  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33084  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33085  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33086  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33087  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33088  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33089  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33090  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33091  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33092  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33093  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33094  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33095  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33096  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33097  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33098  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33099  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33100  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33101  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33102  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33103  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33104  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33105  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33106  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33107  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33108  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33109  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33110  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33111  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33112  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33113  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33114  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33115  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33116  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33117  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33118  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33119  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33120  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33121  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33122  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33123  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33124  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33125  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33126  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33127  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33128  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33129  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33130  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33131  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33132  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33133  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33134  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33135  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33136  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33137  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33138  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33139  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33140  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33141  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33142  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33143  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33144  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33145  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33146  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33147  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33148  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33149  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33150  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33151  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33152  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33153  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33154  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33155 };
33156 
33162 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33163 {
33164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33246 };
33247 
33253 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33254 {
33255  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33256  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33257  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33258  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33259  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33260  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33261  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33262  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33263  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33264  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33265  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33266  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33267  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33268  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33269  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33270  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33271  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33272  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33273  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33274  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33275  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33276  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33277  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33278  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33279  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33280  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33281  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33282  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33283  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33284  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33285  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33286  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33287  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33288  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33289  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33290  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33291  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33292  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33293  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33294  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33295  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33296  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33297  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33298  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33299  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33300  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33301  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33302  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33303  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33304  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33305  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33306  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33307  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33308  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33309  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33310  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33311  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33312  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33313  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33314  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33315  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33316  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33317  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33318  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33319  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33320  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33321  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33322  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33325  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33326  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33335  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33336  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33337 };
33338 
33344 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33345 {
33346  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33350  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33352  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33353  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33354  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33356  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33360  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33362  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33363  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33364  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33366  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33367  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33370  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33371  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33372  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33373  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33374  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33375  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33376  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33377  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33378  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33379  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33380  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33381  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33382  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33383  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33384  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33385  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33386  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33387  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33388  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33389  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33390  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33391  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33392  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33393  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33394  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33395  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33396  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33397  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33398  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33399  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33400  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33401  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33402  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33403  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33404  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33405  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33406  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33407  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33408  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33409  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33410  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33411  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33412  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33413  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33414  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33415  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33416  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33417  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33418  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33419  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33420  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33421  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33422  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33423  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33424  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33425  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33426  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33427  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33428 };
33429 
33435 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33436 {
33437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33519 };
33520 
33526 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33527 {
33528  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33529  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33530  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33531  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33532  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33533  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33534  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33535  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33536  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33537  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33538  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33539  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33540  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33541  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33542  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33543  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33544  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33545  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33546  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33547  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33548  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33549  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33550  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33551  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33552  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33553  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33554  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33555  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33556  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33557  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33558  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33559  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33560  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33561  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33562  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33563  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33564  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33565  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33566  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33567  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33568  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33569  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33570  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33571  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33572  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33573  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33574  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33575  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33576  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33577  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33578  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33579  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33580  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33581  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33582  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33583  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33584  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33585  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33586  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33587  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33588  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33589  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33590  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33591  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33592  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33593  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33594  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33595  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33596  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33597  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33598  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33599  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33600  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33601  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33602  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33603  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33604  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33605  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33606  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33607  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33608  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33609  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33610 };
33611 
33617 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33618 {
33619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33701 };
33702 
33708 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33709 {
33710  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33711  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33712  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33713  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33714  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33715  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33716  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33717  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33718  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33719  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33720  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33721  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33722  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33723  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33724  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33725  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33726  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33727  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33728  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33729  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33730  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33731  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33732  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33733  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33734  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33735  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33736  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33737  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33738  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33739  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33740  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33741  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33742  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33743  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33744  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33745  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33746  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33747  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33748  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33749  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33750  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33751  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33752  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33753  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33754  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33755  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33756  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33757  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33758  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33759  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33760  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33761  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33762  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33763  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33764  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33765  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33766  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33767  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33768  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33769  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33770  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33771  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33772  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33773  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33774  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33775  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33776  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33777  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33778  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33779  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33780  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33781  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33782  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33783  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33784  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33785  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33786  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33787  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33788  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33789  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33790  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33791  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33792 };
33793 
33799 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33800 {
33801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33819  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33820  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33821  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33822  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33823  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33824  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33825  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33826  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33827  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33828  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33829  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33830  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33831  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33832  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33833  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33834  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33835  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33836  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33837  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33838  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33839  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33840  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33841  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33842  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33843  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33844  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33845  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33846  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33847  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33848  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33849  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33850  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33851  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33852  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33853  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33854  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33855  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33856  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33857  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33858  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33859  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33860  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33861  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33862  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33863  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33864  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33865  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33866  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33867  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33868  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33869  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33870  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33871  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33872  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33873  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33874  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33875  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33876  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33877  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33878  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33879  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33880  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33881  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33882  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33883 };
33884 
33890 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33891 {
33892  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33893  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33894  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33895  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33896  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33897  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33898  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33899  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33900  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33901  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33902  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33903  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33904  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33905  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33906  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33907  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33908  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
33909  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
33910  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
33911  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
33912  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
33913  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
33914  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
33915  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
33916  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
33917  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
33918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
33919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
33920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
33921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
33922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
33923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
33924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
33925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
33926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
33927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
33928  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
33929  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
33930  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
33931  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
33932  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
33933  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
33934  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
33935  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
33936  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
33937  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
33938  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
33939  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
33940  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
33941  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
33942  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
33943  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
33944  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
33945  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
33946  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
33947  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
33948  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
33949  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
33950  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
33951  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
33952  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
33953  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
33954  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
33955  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
33956  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
33957  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
33958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
33959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
33960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
33961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
33962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
33963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
33964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
33965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
33966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
33967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
33968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
33969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
33970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
33971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
33972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
33973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
33974 };
33975 
33981 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
33982 {
33983  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
33984  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
33985  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
33986  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
33987  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
33988  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
33989  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
33990  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
33991  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
33992  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
33993  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
33994  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
33995  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
33996  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
33997  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
33998  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
33999  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
34000  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
34001  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
34002  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
34003  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
34004  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
34005  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
34006  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
34007  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
34008  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
34009  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
34010  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
34011  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
34012  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
34013  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
34014  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
34015  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
34016  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
34017  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
34018  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
34019  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
34020  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
34021  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
34022  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
34023  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
34024  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
34025  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
34026  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
34027  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
34028  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
34029  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
34030  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
34031  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
34032  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
34033  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
34034  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
34035  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
34036  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
34037  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
34038  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
34039  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
34040  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
34041  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
34042  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
34043  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
34044  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
34045  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
34046  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
34047  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
34048  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
34049  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
34050  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
34051  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
34052  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
34053  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
34054  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
34055  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
34056  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
34057  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
34058  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
34059  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
34060  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
34061  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
34062  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
34063  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
34064  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
34065 };
34066 
34072 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
34073 {
34074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
34075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
34076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
34077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
34078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
34079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
34080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
34081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
34082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
34083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
34084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
34085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
34086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
34087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
34088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
34089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
34090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
34091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
34092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
34093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
34094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
34095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
34096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
34097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
34098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
34099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
34100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
34101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
34102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
34103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
34104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
34105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
34106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
34107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
34108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
34109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
34110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
34111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
34112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
34113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
34114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
34115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
34116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
34117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
34118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
34119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
34120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
34121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
34122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
34123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
34124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
34125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
34126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
34127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
34128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
34129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
34130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
34131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
34132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
34133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
34134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
34135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
34136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
34137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
34138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
34139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
34140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
34141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
34142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
34143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
34144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
34145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
34146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
34147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
34148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
34149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
34150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
34151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
34152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
34153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
34154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
34155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
34156 };
34157 
34163 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
34164 {
34165  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
34166  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
34167  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
34168  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
34169  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
34170  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
34171  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
34172  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
34173  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
34174  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
34175  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
34176  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
34177  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
34178  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
34179  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
34180  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
34181  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
34182  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
34183  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
34184  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
34185  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
34186  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
34187  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
34188  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
34189  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
34190  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
34191  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
34192  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
34193  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
34194  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
34195  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
34196  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
34197  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
34198  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
34199  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
34200  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
34201  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
34202  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
34203  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
34204  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
34205  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
34206  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
34207  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
34208  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
34209  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
34210  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
34211  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
34212  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
34213  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
34214  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
34215  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
34216  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
34217  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
34218  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
34219  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
34220  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
34221  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
34222  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
34223  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
34224  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
34225  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
34226  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
34227  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
34228  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
34229  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
34230  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
34231  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
34232  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
34233  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
34234  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
34235  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
34236  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
34237  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
34238  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
34239  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
34240  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
34241  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
34242  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
34243  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
34244  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
34245  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
34246  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
34247 };
34248 
34254 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
34255 {
34256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
34257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
34258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
34259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
34260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
34261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
34262 };
34263 
34269 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
34270 {
34271  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
34272  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
34273  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
34274  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
34275  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
34276  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
34277  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
34278  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
34279  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
34280  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
34281  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
34282  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
34283  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
34284  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
34285  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
34286  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
34287  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
34288  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
34289  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
34290  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
34291  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
34292  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
34293  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
34294  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
34295  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
34296  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
34297  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
34298  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
34299  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
34300  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
34301  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
34302  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
34303  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
34304  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
34305  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
34306  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
34307  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
34308  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
34309  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
34310  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
34311  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
34312  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
34313  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
34314  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
34315  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
34316  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
34317  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
34318  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
34319  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
34320  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
34321  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
34322  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
34323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
34324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
34325  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
34326  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
34327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
34328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
34329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
34330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
34331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
34332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
34333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
34334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
34335  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
34336  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
34337  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
34338  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
34339  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
34340  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
34341  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
34342  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
34343  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
34344  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
34345  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
34346  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
34347  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
34348  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
34349  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
34350  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
34351  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
34352  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
34353  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
34354  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
34355  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
34356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
34357  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
34358  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
34359  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
34360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
34361  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
34362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
34363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
34364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
34365  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
34366  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
34367  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
34368  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
34369  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
34370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
34371  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
34372  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
34373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
34374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
34375  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
34376  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
34377  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
34378  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
34379  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
34380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
34381  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
34382  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
34383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
34384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
34385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
34386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
34387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
34388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
34389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
34390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
34391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
34392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
34393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
34394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
34395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
34396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
34397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
34398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
34399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
34400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
34401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
34402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
34403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
34404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
34405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
34406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
34407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
34408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
34409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
34410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
34411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
34412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
34413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
34414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
34415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
34416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
34417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
34418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
34419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
34420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
34421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
34422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
34423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
34424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
34425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
34426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
34427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
34428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
34429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
34430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
34431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
34432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
34433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
34434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
34435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
34436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
34437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
34438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
34439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
34440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
34441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
34442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
34443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
34444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
34445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
34446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
34447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
34448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
34449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
34450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
34451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
34452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
34453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
34454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
34455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
34456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
34457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
34458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
34459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
34460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
34461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
34462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
34463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
34464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
34465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
34466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
34467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
34468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
34469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
34470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
34471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
34472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
34473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
34474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
34475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
34476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
34477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
34478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
34479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
34480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
34481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
34482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
34483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
34484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
34485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
34486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
34487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
34488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
34489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
34490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
34491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
34492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
34493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
34494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
34495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
34496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
34497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
34498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
34499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
34500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
34501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
34502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
34503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
34504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
34505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
34506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
34507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
34508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
34509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
34510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
34511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
34512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
34513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
34514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
34515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
34516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
34517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
34518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
34519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
34520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
34521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
34522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
34523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
34524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
34525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
34526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
34527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
34528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
34529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
34530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
34531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
34532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
34533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
34534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
34535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
34536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
34537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
34538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
34539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
34540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
34541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
34542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
34543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
34544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
34545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
34546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
34547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
34548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
34549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
34550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
34551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
34552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
34553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
34554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
34555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
34556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
34557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
34558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
34559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
34560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
34561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
34562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
34563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
34564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
34565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
34566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
34567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
34568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
34569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
34570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
34571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
34572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
34573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
34574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
34575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
34576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
34577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
34578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
34579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
34580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
34581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
34582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
34583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
34584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
34585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
34586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
34587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
34588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
34589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
34590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
34591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
34592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
34593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
34594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
34595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
34596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
34597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
34598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
34599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
34600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
34601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
34602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
34603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
34604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
34605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
34606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
34607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
34608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
34609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
34610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
34611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
34612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
34613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
34614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
34615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
34616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
34617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
34618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
34619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
34620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
34621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
34622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
34623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
34624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
34625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
34626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
34627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
34628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
34629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
34630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
34631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
34632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
34633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
34634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
34635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
34636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
34637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
34638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
34639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
34640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
34641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
34642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
34643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
34644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
34645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
34646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
34647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
34648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
34649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
34650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
34651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
34652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
34653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
34654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
34655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
34656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
34657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
34658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
34659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
34660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
34661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
34662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
34663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
34664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
34665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
34666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
34667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
34668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
34669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
34670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
34671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
34672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
34673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
34674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
34675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
34676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
34677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
34678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
34679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
34680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
34681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
34682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
34683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
34684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
34685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
34686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
34687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
34688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
34689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
34690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
34691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
34692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
34693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
34694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
34695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
34696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
34697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
34698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
34699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
34700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
34701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
34702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
34703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
34704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
34705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
34706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
34707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
34708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
34709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
34710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
34711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
34712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
34713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
34714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
34715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
34716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
34717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
34718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
34719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
34720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
34721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
34722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
34723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
34724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
34725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
34726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
34727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
34728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
34729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
34730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_229_WIDTH },
34731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
34732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_230_WIDTH },
34733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
34734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_231_WIDTH },
34735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
34736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_232_WIDTH },
34737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
34738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_233_WIDTH },
34739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
34740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_234_WIDTH },
34741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
34742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_235_WIDTH },
34743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
34744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_236_WIDTH },
34745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
34746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_237_WIDTH },
34747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
34748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_238_WIDTH },
34749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
34750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_239_WIDTH },
34751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
34752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_240_WIDTH },
34753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
34754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_241_WIDTH },
34755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
34756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_242_WIDTH },
34757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
34758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_243_WIDTH },
34759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
34760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_244_WIDTH },
34761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
34762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_245_WIDTH },
34763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
34764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_246_WIDTH },
34765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
34766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_247_WIDTH },
34767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
34768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_248_WIDTH },
34769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
34770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_249_WIDTH },
34771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
34772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_250_WIDTH },
34773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
34774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_251_WIDTH },
34775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
34776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_252_WIDTH },
34777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
34778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_253_WIDTH },
34779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
34780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_254_WIDTH },
34781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
34782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_255_WIDTH },
34783 };
34784 
34790 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS] =
34791 {
34792  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
34793  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_0_WIDTH },
34794  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
34795  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_1_WIDTH },
34796  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
34797  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_2_WIDTH },
34798  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
34799  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_3_WIDTH },
34800  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
34801  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_4_WIDTH },
34802  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
34803  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_5_WIDTH },
34804  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
34805  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_6_WIDTH },
34806  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
34807  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_7_WIDTH },
34808  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
34809  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_8_WIDTH },
34810  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
34811  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_9_WIDTH },
34812  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
34813  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_10_WIDTH },
34814  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
34815  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_11_WIDTH },
34816  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
34817  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_12_WIDTH },
34818  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
34819  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_13_WIDTH },
34820  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
34821  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_14_WIDTH },
34822  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
34823  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_15_WIDTH },
34824  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
34825  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_16_WIDTH },
34826  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
34827  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_17_WIDTH },
34828  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
34829  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_18_WIDTH },
34830  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
34831  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_19_WIDTH },
34832  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
34833  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_20_WIDTH },
34834  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
34835  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_21_WIDTH },
34836  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
34837  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_22_WIDTH },
34838  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
34839  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_23_WIDTH },
34840  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
34841  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_24_WIDTH },
34842  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
34843  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_25_WIDTH },
34844  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
34845  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_26_WIDTH },
34846  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
34847  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_27_WIDTH },
34848  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
34849  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_28_WIDTH },
34850  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
34851  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_29_WIDTH },
34852  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
34853  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_30_WIDTH },
34854  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
34855  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_31_WIDTH },
34856  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
34857  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_32_WIDTH },
34858  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
34859  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_33_WIDTH },
34860  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
34861  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_34_WIDTH },
34862  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
34863  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_35_WIDTH },
34864  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
34865  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_36_WIDTH },
34866  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
34867  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_37_WIDTH },
34868  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
34869  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_38_WIDTH },
34870  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
34871  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_39_WIDTH },
34872  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
34873  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_40_WIDTH },
34874  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
34875  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_41_WIDTH },
34876  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
34877  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_42_WIDTH },
34878  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
34879  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_43_WIDTH },
34880  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
34881  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_44_WIDTH },
34882  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
34883  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_45_WIDTH },
34884  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
34885  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_46_WIDTH },
34886  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
34887  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_47_WIDTH },
34888  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
34889  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_48_WIDTH },
34890  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
34891  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_49_WIDTH },
34892  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
34893  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_50_WIDTH },
34894  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
34895  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_51_WIDTH },
34896  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
34897  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_52_WIDTH },
34898  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
34899  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_53_WIDTH },
34900  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
34901  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_54_WIDTH },
34902  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
34903  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_55_WIDTH },
34904  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
34905  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_56_WIDTH },
34906  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
34907  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_57_WIDTH },
34908  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
34909  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_58_WIDTH },
34910  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
34911  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_59_WIDTH },
34912  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
34913  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_60_WIDTH },
34914  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
34915  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_61_WIDTH },
34916  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
34917  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_62_WIDTH },
34918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
34919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_63_WIDTH },
34920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
34921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_64_WIDTH },
34922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
34923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_65_WIDTH },
34924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
34925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_66_WIDTH },
34926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
34927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_67_WIDTH },
34928  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
34929  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_68_WIDTH },
34930  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
34931  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_69_WIDTH },
34932  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
34933  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_70_WIDTH },
34934  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
34935  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_71_WIDTH },
34936  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
34937  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_72_WIDTH },
34938  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
34939  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_73_WIDTH },
34940  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
34941  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_74_WIDTH },
34942  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
34943  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_75_WIDTH },
34944  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
34945  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_76_WIDTH },
34946  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
34947  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_77_WIDTH },
34948  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
34949  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_78_WIDTH },
34950  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
34951  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_79_WIDTH },
34952  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
34953  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_80_WIDTH },
34954  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
34955  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_81_WIDTH },
34956  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
34957  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_82_WIDTH },
34958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
34959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_83_WIDTH },
34960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
34961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_84_WIDTH },
34962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
34963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_85_WIDTH },
34964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
34965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_86_WIDTH },
34966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
34967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_87_WIDTH },
34968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
34969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_88_WIDTH },
34970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
34971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_89_WIDTH },
34972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
34973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_90_WIDTH },
34974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
34975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_91_WIDTH },
34976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
34977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_92_WIDTH },
34978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
34979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_93_WIDTH },
34980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
34981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_94_WIDTH },
34982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
34983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_95_WIDTH },
34984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
34985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_96_WIDTH },
34986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
34987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_97_WIDTH },
34988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
34989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_98_WIDTH },
34990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
34991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_99_WIDTH },
34992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
34993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_100_WIDTH },
34994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
34995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_101_WIDTH },
34996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
34997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_102_WIDTH },
34998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
34999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_103_WIDTH },
35000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
35001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_104_WIDTH },
35002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
35003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_105_WIDTH },
35004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
35005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_106_WIDTH },
35006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
35007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_107_WIDTH },
35008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
35009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_108_WIDTH },
35010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
35011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_109_WIDTH },
35012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
35013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_110_WIDTH },
35014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
35015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_111_WIDTH },
35016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
35017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_112_WIDTH },
35018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
35019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_113_WIDTH },
35020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
35021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_114_WIDTH },
35022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
35023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_115_WIDTH },
35024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
35025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_116_WIDTH },
35026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
35027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_117_WIDTH },
35028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
35029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_118_WIDTH },
35030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
35031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_119_WIDTH },
35032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
35033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_120_WIDTH },
35034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
35035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_121_WIDTH },
35036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
35037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_122_WIDTH },
35038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
35039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_123_WIDTH },
35040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
35041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_124_WIDTH },
35042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
35043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_125_WIDTH },
35044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
35045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_126_WIDTH },
35046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
35047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_127_WIDTH },
35048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
35049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_128_WIDTH },
35050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
35051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_129_WIDTH },
35052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
35053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_130_WIDTH },
35054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
35055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_131_WIDTH },
35056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
35057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_132_WIDTH },
35058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
35059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_133_WIDTH },
35060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
35061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_134_WIDTH },
35062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
35063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_135_WIDTH },
35064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
35065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_136_WIDTH },
35066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
35067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_137_WIDTH },
35068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
35069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_138_WIDTH },
35070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
35071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_139_WIDTH },
35072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
35073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_140_WIDTH },
35074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
35075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_141_WIDTH },
35076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
35077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_142_WIDTH },
35078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
35079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_143_WIDTH },
35080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
35081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_144_WIDTH },
35082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
35083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_145_WIDTH },
35084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
35085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_146_WIDTH },
35086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
35087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_147_WIDTH },
35088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
35089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_148_WIDTH },
35090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
35091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_149_WIDTH },
35092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
35093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_150_WIDTH },
35094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
35095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_151_WIDTH },
35096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
35097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_152_WIDTH },
35098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
35099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_153_WIDTH },
35100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
35101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_154_WIDTH },
35102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
35103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_155_WIDTH },
35104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
35105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_156_WIDTH },
35106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
35107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_157_WIDTH },
35108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
35109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_158_WIDTH },
35110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
35111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_159_WIDTH },
35112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
35113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_160_WIDTH },
35114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
35115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_161_WIDTH },
35116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
35117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_162_WIDTH },
35118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
35119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_163_WIDTH },
35120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_164_CHECKER_TYPE,
35121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_164_WIDTH },
35122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_165_CHECKER_TYPE,
35123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_165_WIDTH },
35124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_166_CHECKER_TYPE,
35125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_166_WIDTH },
35126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_167_CHECKER_TYPE,
35127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_167_WIDTH },
35128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_168_CHECKER_TYPE,
35129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_168_WIDTH },
35130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_169_CHECKER_TYPE,
35131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_169_WIDTH },
35132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_170_CHECKER_TYPE,
35133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_170_WIDTH },
35134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_171_CHECKER_TYPE,
35135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_171_WIDTH },
35136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_172_CHECKER_TYPE,
35137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_172_WIDTH },
35138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_173_CHECKER_TYPE,
35139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_173_WIDTH },
35140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_174_CHECKER_TYPE,
35141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_174_WIDTH },
35142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_175_CHECKER_TYPE,
35143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_175_WIDTH },
35144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_176_CHECKER_TYPE,
35145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_176_WIDTH },
35146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_177_CHECKER_TYPE,
35147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_177_WIDTH },
35148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_178_CHECKER_TYPE,
35149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_178_WIDTH },
35150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_179_CHECKER_TYPE,
35151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_179_WIDTH },
35152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_180_CHECKER_TYPE,
35153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_180_WIDTH },
35154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_181_CHECKER_TYPE,
35155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_181_WIDTH },
35156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_182_CHECKER_TYPE,
35157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_182_WIDTH },
35158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_183_CHECKER_TYPE,
35159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_183_WIDTH },
35160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_184_CHECKER_TYPE,
35161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_184_WIDTH },
35162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_185_CHECKER_TYPE,
35163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_185_WIDTH },
35164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_186_CHECKER_TYPE,
35165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_186_WIDTH },
35166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_187_CHECKER_TYPE,
35167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_187_WIDTH },
35168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_188_CHECKER_TYPE,
35169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_188_WIDTH },
35170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_189_CHECKER_TYPE,
35171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_189_WIDTH },
35172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_190_CHECKER_TYPE,
35173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_190_WIDTH },
35174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_191_CHECKER_TYPE,
35175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_191_WIDTH },
35176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_192_CHECKER_TYPE,
35177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_192_WIDTH },
35178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_193_CHECKER_TYPE,
35179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_193_WIDTH },
35180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_194_CHECKER_TYPE,
35181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_194_WIDTH },
35182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_195_CHECKER_TYPE,
35183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_195_WIDTH },
35184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_196_CHECKER_TYPE,
35185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_196_WIDTH },
35186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_197_CHECKER_TYPE,
35187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_197_WIDTH },
35188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_198_CHECKER_TYPE,
35189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_198_WIDTH },
35190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_199_CHECKER_TYPE,
35191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_199_WIDTH },
35192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_200_CHECKER_TYPE,
35193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_200_WIDTH },
35194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_201_CHECKER_TYPE,
35195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_201_WIDTH },
35196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_202_CHECKER_TYPE,
35197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_202_WIDTH },
35198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_203_CHECKER_TYPE,
35199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_203_WIDTH },
35200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_204_CHECKER_TYPE,
35201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_204_WIDTH },
35202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_205_CHECKER_TYPE,
35203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_205_WIDTH },
35204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_206_CHECKER_TYPE,
35205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_206_WIDTH },
35206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_207_CHECKER_TYPE,
35207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_207_WIDTH },
35208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_208_CHECKER_TYPE,
35209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_208_WIDTH },
35210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_209_CHECKER_TYPE,
35211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_209_WIDTH },
35212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_210_CHECKER_TYPE,
35213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_210_WIDTH },
35214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_211_CHECKER_TYPE,
35215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_211_WIDTH },
35216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_212_CHECKER_TYPE,
35217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_212_WIDTH },
35218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_213_CHECKER_TYPE,
35219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_213_WIDTH },
35220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_214_CHECKER_TYPE,
35221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_214_WIDTH },
35222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_215_CHECKER_TYPE,
35223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_215_WIDTH },
35224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_216_CHECKER_TYPE,
35225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_216_WIDTH },
35226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_217_CHECKER_TYPE,
35227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_217_WIDTH },
35228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_218_CHECKER_TYPE,
35229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_218_WIDTH },
35230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_219_CHECKER_TYPE,
35231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_219_WIDTH },
35232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_220_CHECKER_TYPE,
35233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_220_WIDTH },
35234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_221_CHECKER_TYPE,
35235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_221_WIDTH },
35236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_222_CHECKER_TYPE,
35237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_222_WIDTH },
35238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_223_CHECKER_TYPE,
35239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_223_WIDTH },
35240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_224_CHECKER_TYPE,
35241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_224_WIDTH },
35242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_225_CHECKER_TYPE,
35243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_225_WIDTH },
35244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_226_CHECKER_TYPE,
35245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_226_WIDTH },
35246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_227_CHECKER_TYPE,
35247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_227_WIDTH },
35248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_228_CHECKER_TYPE,
35249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_228_WIDTH },
35250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_229_CHECKER_TYPE,
35251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_229_WIDTH },
35252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_230_CHECKER_TYPE,
35253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_230_WIDTH },
35254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_231_CHECKER_TYPE,
35255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_231_WIDTH },
35256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_232_CHECKER_TYPE,
35257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_232_WIDTH },
35258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_233_CHECKER_TYPE,
35259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_233_WIDTH },
35260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_234_CHECKER_TYPE,
35261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_234_WIDTH },
35262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_235_CHECKER_TYPE,
35263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_235_WIDTH },
35264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_236_CHECKER_TYPE,
35265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_236_WIDTH },
35266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_237_CHECKER_TYPE,
35267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_237_WIDTH },
35268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_238_CHECKER_TYPE,
35269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_238_WIDTH },
35270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_239_CHECKER_TYPE,
35271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_239_WIDTH },
35272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_240_CHECKER_TYPE,
35273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_240_WIDTH },
35274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_241_CHECKER_TYPE,
35275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_241_WIDTH },
35276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_242_CHECKER_TYPE,
35277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_242_WIDTH },
35278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_243_CHECKER_TYPE,
35279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_243_WIDTH },
35280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_244_CHECKER_TYPE,
35281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_244_WIDTH },
35282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_245_CHECKER_TYPE,
35283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_245_WIDTH },
35284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_246_CHECKER_TYPE,
35285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_246_WIDTH },
35286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_247_CHECKER_TYPE,
35287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_247_WIDTH },
35288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_248_CHECKER_TYPE,
35289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_248_WIDTH },
35290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_249_CHECKER_TYPE,
35291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_249_WIDTH },
35292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_250_CHECKER_TYPE,
35293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_250_WIDTH },
35294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_251_CHECKER_TYPE,
35295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_251_WIDTH },
35296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_252_CHECKER_TYPE,
35297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_252_WIDTH },
35298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_253_CHECKER_TYPE,
35299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_253_WIDTH },
35300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_254_CHECKER_TYPE,
35301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_254_WIDTH },
35302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_255_CHECKER_TYPE,
35303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_GROUP_255_WIDTH },
35304 };
35305 
35311 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS] =
35312 {
35313  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_0_CHECKER_TYPE,
35314  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_0_WIDTH },
35315  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_1_CHECKER_TYPE,
35316  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_1_WIDTH },
35317  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_2_CHECKER_TYPE,
35318  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_2_WIDTH },
35319  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_3_CHECKER_TYPE,
35320  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_3_WIDTH },
35321  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_4_CHECKER_TYPE,
35322  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_4_WIDTH },
35323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_5_CHECKER_TYPE,
35324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_5_WIDTH },
35325  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_6_CHECKER_TYPE,
35326  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_6_WIDTH },
35327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_7_CHECKER_TYPE,
35328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_7_WIDTH },
35329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_8_CHECKER_TYPE,
35330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_8_WIDTH },
35331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_9_CHECKER_TYPE,
35332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_9_WIDTH },
35333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_10_CHECKER_TYPE,
35334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_10_WIDTH },
35335  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_11_CHECKER_TYPE,
35336  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_11_WIDTH },
35337  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_12_CHECKER_TYPE,
35338  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_12_WIDTH },
35339  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_13_CHECKER_TYPE,
35340  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_13_WIDTH },
35341  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_14_CHECKER_TYPE,
35342  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_14_WIDTH },
35343  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_15_CHECKER_TYPE,
35344  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_15_WIDTH },
35345  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_16_CHECKER_TYPE,
35346  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_16_WIDTH },
35347  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_17_CHECKER_TYPE,
35348  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_17_WIDTH },
35349  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_18_CHECKER_TYPE,
35350  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_18_WIDTH },
35351  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_19_CHECKER_TYPE,
35352  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_19_WIDTH },
35353  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_20_CHECKER_TYPE,
35354  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_20_WIDTH },
35355  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_21_CHECKER_TYPE,
35356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_21_WIDTH },
35357  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_22_CHECKER_TYPE,
35358  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_22_WIDTH },
35359  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_23_CHECKER_TYPE,
35360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_23_WIDTH },
35361  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_24_CHECKER_TYPE,
35362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_24_WIDTH },
35363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_25_CHECKER_TYPE,
35364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_25_WIDTH },
35365  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_26_CHECKER_TYPE,
35366  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_26_WIDTH },
35367  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_27_CHECKER_TYPE,
35368  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_27_WIDTH },
35369  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_28_CHECKER_TYPE,
35370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_28_WIDTH },
35371  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_29_CHECKER_TYPE,
35372  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_29_WIDTH },
35373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_30_CHECKER_TYPE,
35374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_30_WIDTH },
35375  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_31_CHECKER_TYPE,
35376  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_31_WIDTH },
35377  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_32_CHECKER_TYPE,
35378  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_32_WIDTH },
35379  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_33_CHECKER_TYPE,
35380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_33_WIDTH },
35381  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_34_CHECKER_TYPE,
35382  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_34_WIDTH },
35383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_35_CHECKER_TYPE,
35384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_35_WIDTH },
35385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_36_CHECKER_TYPE,
35386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_36_WIDTH },
35387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_37_CHECKER_TYPE,
35388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_37_WIDTH },
35389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_38_CHECKER_TYPE,
35390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_38_WIDTH },
35391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_39_CHECKER_TYPE,
35392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_39_WIDTH },
35393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_40_CHECKER_TYPE,
35394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_40_WIDTH },
35395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_41_CHECKER_TYPE,
35396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_41_WIDTH },
35397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_42_CHECKER_TYPE,
35398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_42_WIDTH },
35399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_43_CHECKER_TYPE,
35400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_43_WIDTH },
35401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_44_CHECKER_TYPE,
35402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_44_WIDTH },
35403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_45_CHECKER_TYPE,
35404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_45_WIDTH },
35405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_46_CHECKER_TYPE,
35406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_46_WIDTH },
35407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_47_CHECKER_TYPE,
35408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_47_WIDTH },
35409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_48_CHECKER_TYPE,
35410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_48_WIDTH },
35411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_49_CHECKER_TYPE,
35412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_49_WIDTH },
35413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_50_CHECKER_TYPE,
35414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_50_WIDTH },
35415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_51_CHECKER_TYPE,
35416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_51_WIDTH },
35417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_52_CHECKER_TYPE,
35418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_52_WIDTH },
35419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_53_CHECKER_TYPE,
35420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_53_WIDTH },
35421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_54_CHECKER_TYPE,
35422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_54_WIDTH },
35423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_55_CHECKER_TYPE,
35424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_55_WIDTH },
35425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_56_CHECKER_TYPE,
35426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_56_WIDTH },
35427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_57_CHECKER_TYPE,
35428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_57_WIDTH },
35429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_58_CHECKER_TYPE,
35430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_58_WIDTH },
35431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_59_CHECKER_TYPE,
35432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_59_WIDTH },
35433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_60_CHECKER_TYPE,
35434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_60_WIDTH },
35435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_61_CHECKER_TYPE,
35436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_61_WIDTH },
35437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_62_CHECKER_TYPE,
35438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_62_WIDTH },
35439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_63_CHECKER_TYPE,
35440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_63_WIDTH },
35441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_64_CHECKER_TYPE,
35442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_64_WIDTH },
35443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_65_CHECKER_TYPE,
35444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_65_WIDTH },
35445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_66_CHECKER_TYPE,
35446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_66_WIDTH },
35447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_67_CHECKER_TYPE,
35448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_67_WIDTH },
35449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_68_CHECKER_TYPE,
35450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_68_WIDTH },
35451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_69_CHECKER_TYPE,
35452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_69_WIDTH },
35453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_70_CHECKER_TYPE,
35454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_70_WIDTH },
35455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_71_CHECKER_TYPE,
35456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_71_WIDTH },
35457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_72_CHECKER_TYPE,
35458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_72_WIDTH },
35459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_73_CHECKER_TYPE,
35460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_73_WIDTH },
35461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_74_CHECKER_TYPE,
35462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_74_WIDTH },
35463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_75_CHECKER_TYPE,
35464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_75_WIDTH },
35465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_76_CHECKER_TYPE,
35466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_76_WIDTH },
35467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_77_CHECKER_TYPE,
35468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_77_WIDTH },
35469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_78_CHECKER_TYPE,
35470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_78_WIDTH },
35471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_79_CHECKER_TYPE,
35472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_79_WIDTH },
35473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_80_CHECKER_TYPE,
35474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_80_WIDTH },
35475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_81_CHECKER_TYPE,
35476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_81_WIDTH },
35477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_82_CHECKER_TYPE,
35478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_82_WIDTH },
35479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_83_CHECKER_TYPE,
35480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_83_WIDTH },
35481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_84_CHECKER_TYPE,
35482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_84_WIDTH },
35483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_85_CHECKER_TYPE,
35484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_85_WIDTH },
35485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_86_CHECKER_TYPE,
35486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_86_WIDTH },
35487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_87_CHECKER_TYPE,
35488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_87_WIDTH },
35489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_88_CHECKER_TYPE,
35490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_88_WIDTH },
35491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_89_CHECKER_TYPE,
35492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_89_WIDTH },
35493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_90_CHECKER_TYPE,
35494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_90_WIDTH },
35495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_91_CHECKER_TYPE,
35496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_91_WIDTH },
35497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_92_CHECKER_TYPE,
35498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_92_WIDTH },
35499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_93_CHECKER_TYPE,
35500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_93_WIDTH },
35501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_94_CHECKER_TYPE,
35502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_94_WIDTH },
35503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_95_CHECKER_TYPE,
35504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_95_WIDTH },
35505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_96_CHECKER_TYPE,
35506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_96_WIDTH },
35507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_97_CHECKER_TYPE,
35508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_97_WIDTH },
35509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_98_CHECKER_TYPE,
35510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_98_WIDTH },
35511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_99_CHECKER_TYPE,
35512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_99_WIDTH },
35513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_100_CHECKER_TYPE,
35514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_100_WIDTH },
35515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_101_CHECKER_TYPE,
35516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_101_WIDTH },
35517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_102_CHECKER_TYPE,
35518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_102_WIDTH },
35519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_103_CHECKER_TYPE,
35520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_103_WIDTH },
35521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_104_CHECKER_TYPE,
35522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_104_WIDTH },
35523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_105_CHECKER_TYPE,
35524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_105_WIDTH },
35525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_106_CHECKER_TYPE,
35526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_106_WIDTH },
35527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_107_CHECKER_TYPE,
35528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_107_WIDTH },
35529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_108_CHECKER_TYPE,
35530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_108_WIDTH },
35531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_109_CHECKER_TYPE,
35532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_109_WIDTH },
35533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_110_CHECKER_TYPE,
35534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_110_WIDTH },
35535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_111_CHECKER_TYPE,
35536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_111_WIDTH },
35537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_112_CHECKER_TYPE,
35538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_112_WIDTH },
35539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_113_CHECKER_TYPE,
35540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_113_WIDTH },
35541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_114_CHECKER_TYPE,
35542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_114_WIDTH },
35543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_115_CHECKER_TYPE,
35544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_115_WIDTH },
35545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_116_CHECKER_TYPE,
35546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_116_WIDTH },
35547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_117_CHECKER_TYPE,
35548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_117_WIDTH },
35549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_118_CHECKER_TYPE,
35550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_118_WIDTH },
35551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_119_CHECKER_TYPE,
35552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_119_WIDTH },
35553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_120_CHECKER_TYPE,
35554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_120_WIDTH },
35555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_121_CHECKER_TYPE,
35556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_121_WIDTH },
35557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_122_CHECKER_TYPE,
35558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_122_WIDTH },
35559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_123_CHECKER_TYPE,
35560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_123_WIDTH },
35561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_124_CHECKER_TYPE,
35562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_124_WIDTH },
35563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_125_CHECKER_TYPE,
35564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_125_WIDTH },
35565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_126_CHECKER_TYPE,
35566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_126_WIDTH },
35567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_127_CHECKER_TYPE,
35568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_127_WIDTH },
35569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_128_CHECKER_TYPE,
35570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_128_WIDTH },
35571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_129_CHECKER_TYPE,
35572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_129_WIDTH },
35573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_130_CHECKER_TYPE,
35574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_130_WIDTH },
35575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_131_CHECKER_TYPE,
35576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_131_WIDTH },
35577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_132_CHECKER_TYPE,
35578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_132_WIDTH },
35579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_133_CHECKER_TYPE,
35580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_133_WIDTH },
35581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_134_CHECKER_TYPE,
35582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_134_WIDTH },
35583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_135_CHECKER_TYPE,
35584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_135_WIDTH },
35585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_136_CHECKER_TYPE,
35586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_136_WIDTH },
35587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_137_CHECKER_TYPE,
35588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_137_WIDTH },
35589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_138_CHECKER_TYPE,
35590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_138_WIDTH },
35591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_139_CHECKER_TYPE,
35592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_139_WIDTH },
35593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_140_CHECKER_TYPE,
35594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_140_WIDTH },
35595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_141_CHECKER_TYPE,
35596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_141_WIDTH },
35597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_142_CHECKER_TYPE,
35598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_142_WIDTH },
35599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_143_CHECKER_TYPE,
35600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_143_WIDTH },
35601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_144_CHECKER_TYPE,
35602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_144_WIDTH },
35603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_145_CHECKER_TYPE,
35604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_145_WIDTH },
35605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_146_CHECKER_TYPE,
35606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_146_WIDTH },
35607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_147_CHECKER_TYPE,
35608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_147_WIDTH },
35609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_148_CHECKER_TYPE,
35610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_148_WIDTH },
35611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_149_CHECKER_TYPE,
35612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_149_WIDTH },
35613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_150_CHECKER_TYPE,
35614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_150_WIDTH },
35615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_151_CHECKER_TYPE,
35616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_151_WIDTH },
35617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_152_CHECKER_TYPE,
35618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_152_WIDTH },
35619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_153_CHECKER_TYPE,
35620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_153_WIDTH },
35621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_154_CHECKER_TYPE,
35622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_154_WIDTH },
35623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_155_CHECKER_TYPE,
35624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_155_WIDTH },
35625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_156_CHECKER_TYPE,
35626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_156_WIDTH },
35627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_157_CHECKER_TYPE,
35628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_157_WIDTH },
35629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_158_CHECKER_TYPE,
35630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_158_WIDTH },
35631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_159_CHECKER_TYPE,
35632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_159_WIDTH },
35633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_160_CHECKER_TYPE,
35634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_160_WIDTH },
35635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_161_CHECKER_TYPE,
35636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_161_WIDTH },
35637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_162_CHECKER_TYPE,
35638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_162_WIDTH },
35639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_163_CHECKER_TYPE,
35640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_163_WIDTH },
35641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_164_CHECKER_TYPE,
35642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_164_WIDTH },
35643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_165_CHECKER_TYPE,
35644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_165_WIDTH },
35645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_166_CHECKER_TYPE,
35646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_166_WIDTH },
35647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_167_CHECKER_TYPE,
35648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_167_WIDTH },
35649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_168_CHECKER_TYPE,
35650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_168_WIDTH },
35651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_169_CHECKER_TYPE,
35652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_169_WIDTH },
35653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_170_CHECKER_TYPE,
35654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_170_WIDTH },
35655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_171_CHECKER_TYPE,
35656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_171_WIDTH },
35657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_172_CHECKER_TYPE,
35658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_172_WIDTH },
35659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_173_CHECKER_TYPE,
35660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_173_WIDTH },
35661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_174_CHECKER_TYPE,
35662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_174_WIDTH },
35663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_175_CHECKER_TYPE,
35664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_175_WIDTH },
35665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_176_CHECKER_TYPE,
35666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_176_WIDTH },
35667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_177_CHECKER_TYPE,
35668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_177_WIDTH },
35669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_178_CHECKER_TYPE,
35670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_178_WIDTH },
35671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_179_CHECKER_TYPE,
35672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_179_WIDTH },
35673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_180_CHECKER_TYPE,
35674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_180_WIDTH },
35675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_181_CHECKER_TYPE,
35676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_181_WIDTH },
35677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_182_CHECKER_TYPE,
35678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_182_WIDTH },
35679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_183_CHECKER_TYPE,
35680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_183_WIDTH },
35681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_184_CHECKER_TYPE,
35682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_184_WIDTH },
35683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_185_CHECKER_TYPE,
35684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_185_WIDTH },
35685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_186_CHECKER_TYPE,
35686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_186_WIDTH },
35687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_187_CHECKER_TYPE,
35688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_187_WIDTH },
35689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_188_CHECKER_TYPE,
35690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_188_WIDTH },
35691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_189_CHECKER_TYPE,
35692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_189_WIDTH },
35693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_190_CHECKER_TYPE,
35694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_190_WIDTH },
35695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_191_CHECKER_TYPE,
35696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_191_WIDTH },
35697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_192_CHECKER_TYPE,
35698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_192_WIDTH },
35699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_193_CHECKER_TYPE,
35700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_193_WIDTH },
35701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_194_CHECKER_TYPE,
35702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_194_WIDTH },
35703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_195_CHECKER_TYPE,
35704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_195_WIDTH },
35705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_196_CHECKER_TYPE,
35706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_196_WIDTH },
35707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_197_CHECKER_TYPE,
35708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_197_WIDTH },
35709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_198_CHECKER_TYPE,
35710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_198_WIDTH },
35711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_199_CHECKER_TYPE,
35712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_199_WIDTH },
35713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_200_CHECKER_TYPE,
35714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_200_WIDTH },
35715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_201_CHECKER_TYPE,
35716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_201_WIDTH },
35717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_202_CHECKER_TYPE,
35718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_202_WIDTH },
35719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_203_CHECKER_TYPE,
35720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_203_WIDTH },
35721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_204_CHECKER_TYPE,
35722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_204_WIDTH },
35723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_205_CHECKER_TYPE,
35724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_205_WIDTH },
35725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_206_CHECKER_TYPE,
35726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_206_WIDTH },
35727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_207_CHECKER_TYPE,
35728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_207_WIDTH },
35729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_208_CHECKER_TYPE,
35730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_208_WIDTH },
35731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_209_CHECKER_TYPE,
35732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_209_WIDTH },
35733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_210_CHECKER_TYPE,
35734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_210_WIDTH },
35735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_211_CHECKER_TYPE,
35736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_211_WIDTH },
35737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_212_CHECKER_TYPE,
35738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_212_WIDTH },
35739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_213_CHECKER_TYPE,
35740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_213_WIDTH },
35741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_214_CHECKER_TYPE,
35742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_214_WIDTH },
35743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_215_CHECKER_TYPE,
35744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_215_WIDTH },
35745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_216_CHECKER_TYPE,
35746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_216_WIDTH },
35747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_217_CHECKER_TYPE,
35748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_217_WIDTH },
35749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_218_CHECKER_TYPE,
35750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_218_WIDTH },
35751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_219_CHECKER_TYPE,
35752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_219_WIDTH },
35753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_220_CHECKER_TYPE,
35754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_220_WIDTH },
35755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_221_CHECKER_TYPE,
35756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_221_WIDTH },
35757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_222_CHECKER_TYPE,
35758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_222_WIDTH },
35759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_223_CHECKER_TYPE,
35760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_223_WIDTH },
35761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_224_CHECKER_TYPE,
35762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_224_WIDTH },
35763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_225_CHECKER_TYPE,
35764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_225_WIDTH },
35765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_226_CHECKER_TYPE,
35766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_226_WIDTH },
35767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_227_CHECKER_TYPE,
35768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_227_WIDTH },
35769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_228_CHECKER_TYPE,
35770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_228_WIDTH },
35771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_229_CHECKER_TYPE,
35772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_229_WIDTH },
35773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_230_CHECKER_TYPE,
35774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_230_WIDTH },
35775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_231_CHECKER_TYPE,
35776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_231_WIDTH },
35777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_232_CHECKER_TYPE,
35778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_232_WIDTH },
35779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_233_CHECKER_TYPE,
35780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_233_WIDTH },
35781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_234_CHECKER_TYPE,
35782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_234_WIDTH },
35783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_235_CHECKER_TYPE,
35784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_235_WIDTH },
35785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_236_CHECKER_TYPE,
35786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_236_WIDTH },
35787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_237_CHECKER_TYPE,
35788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_237_WIDTH },
35789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_238_CHECKER_TYPE,
35790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_238_WIDTH },
35791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_239_CHECKER_TYPE,
35792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_239_WIDTH },
35793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_240_CHECKER_TYPE,
35794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_240_WIDTH },
35795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_241_CHECKER_TYPE,
35796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_241_WIDTH },
35797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_242_CHECKER_TYPE,
35798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_242_WIDTH },
35799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_243_CHECKER_TYPE,
35800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_243_WIDTH },
35801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_244_CHECKER_TYPE,
35802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_244_WIDTH },
35803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_245_CHECKER_TYPE,
35804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_245_WIDTH },
35805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_246_CHECKER_TYPE,
35806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_246_WIDTH },
35807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_247_CHECKER_TYPE,
35808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_247_WIDTH },
35809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_248_CHECKER_TYPE,
35810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_248_WIDTH },
35811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_249_CHECKER_TYPE,
35812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_249_WIDTH },
35813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_250_CHECKER_TYPE,
35814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_250_WIDTH },
35815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_251_CHECKER_TYPE,
35816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_251_WIDTH },
35817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_252_CHECKER_TYPE,
35818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_252_WIDTH },
35819  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_253_CHECKER_TYPE,
35820  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_253_WIDTH },
35821  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_254_CHECKER_TYPE,
35822  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_254_WIDTH },
35823  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_255_CHECKER_TYPE,
35824  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_GROUP_255_WIDTH },
35825 };
35826 
35832 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_MAX_NUM_CHECKERS] =
35833 {
35834  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_0_CHECKER_TYPE,
35835  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_0_WIDTH },
35836  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_1_CHECKER_TYPE,
35837  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_1_WIDTH },
35838  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_2_CHECKER_TYPE,
35839  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_2_WIDTH },
35840  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_3_CHECKER_TYPE,
35841  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_3_WIDTH },
35842  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_4_CHECKER_TYPE,
35843  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_4_WIDTH },
35844  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_5_CHECKER_TYPE,
35845  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_5_WIDTH },
35846  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_6_CHECKER_TYPE,
35847  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_6_WIDTH },
35848  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_7_CHECKER_TYPE,
35849  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_7_WIDTH },
35850  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_8_CHECKER_TYPE,
35851  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_8_WIDTH },
35852  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_9_CHECKER_TYPE,
35853  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_9_WIDTH },
35854  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_10_CHECKER_TYPE,
35855  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_10_WIDTH },
35856  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_11_CHECKER_TYPE,
35857  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_11_WIDTH },
35858  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_12_CHECKER_TYPE,
35859  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_12_WIDTH },
35860  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_13_CHECKER_TYPE,
35861  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_13_WIDTH },
35862  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_14_CHECKER_TYPE,
35863  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_14_WIDTH },
35864  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_15_CHECKER_TYPE,
35865  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_15_WIDTH },
35866  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_16_CHECKER_TYPE,
35867  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_16_WIDTH },
35868  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_17_CHECKER_TYPE,
35869  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_17_WIDTH },
35870  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_18_CHECKER_TYPE,
35871  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_18_WIDTH },
35872  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_19_CHECKER_TYPE,
35873  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_19_WIDTH },
35874  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_20_CHECKER_TYPE,
35875  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_20_WIDTH },
35876  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_21_CHECKER_TYPE,
35877  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_21_WIDTH },
35878  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_22_CHECKER_TYPE,
35879  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_22_WIDTH },
35880  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_23_CHECKER_TYPE,
35881  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_23_WIDTH },
35882  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_24_CHECKER_TYPE,
35883  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_24_WIDTH },
35884  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_25_CHECKER_TYPE,
35885  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_25_WIDTH },
35886  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_26_CHECKER_TYPE,
35887  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_26_WIDTH },
35888  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_27_CHECKER_TYPE,
35889  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_27_WIDTH },
35890  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_28_CHECKER_TYPE,
35891  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_28_WIDTH },
35892  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_29_CHECKER_TYPE,
35893  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_29_WIDTH },
35894  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_30_CHECKER_TYPE,
35895  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_30_WIDTH },
35896  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_31_CHECKER_TYPE,
35897  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_31_WIDTH },
35898  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_32_CHECKER_TYPE,
35899  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_32_WIDTH },
35900  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_33_CHECKER_TYPE,
35901  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_33_WIDTH },
35902  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_34_CHECKER_TYPE,
35903  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_34_WIDTH },
35904  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_35_CHECKER_TYPE,
35905  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_35_WIDTH },
35906  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_36_CHECKER_TYPE,
35907  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_36_WIDTH },
35908  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_37_CHECKER_TYPE,
35909  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_37_WIDTH },
35910  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_38_CHECKER_TYPE,
35911  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_38_WIDTH },
35912  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_39_CHECKER_TYPE,
35913  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_39_WIDTH },
35914  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_40_CHECKER_TYPE,
35915  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_40_WIDTH },
35916  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_41_CHECKER_TYPE,
35917  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_41_WIDTH },
35918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_42_CHECKER_TYPE,
35919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_42_WIDTH },
35920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_43_CHECKER_TYPE,
35921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_43_WIDTH },
35922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_44_CHECKER_TYPE,
35923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_44_WIDTH },
35924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_45_CHECKER_TYPE,
35925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_45_WIDTH },
35926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_46_CHECKER_TYPE,
35927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_46_WIDTH },
35928  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_47_CHECKER_TYPE,
35929  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_47_WIDTH },
35930  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_48_CHECKER_TYPE,
35931  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_48_WIDTH },
35932  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_49_CHECKER_TYPE,
35933  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_49_WIDTH },
35934  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_50_CHECKER_TYPE,
35935  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_50_WIDTH },
35936  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_51_CHECKER_TYPE,
35937  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_51_WIDTH },
35938  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_52_CHECKER_TYPE,
35939  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_52_WIDTH },
35940  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_53_CHECKER_TYPE,
35941  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_53_WIDTH },
35942  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_54_CHECKER_TYPE,
35943  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_54_WIDTH },
35944  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_55_CHECKER_TYPE,
35945  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_55_WIDTH },
35946  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_56_CHECKER_TYPE,
35947  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_56_WIDTH },
35948  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_57_CHECKER_TYPE,
35949  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_57_WIDTH },
35950  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_58_CHECKER_TYPE,
35951  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_58_WIDTH },
35952  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_59_CHECKER_TYPE,
35953  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_59_WIDTH },
35954  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_60_CHECKER_TYPE,
35955  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_60_WIDTH },
35956  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_61_CHECKER_TYPE,
35957  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_61_WIDTH },
35958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_62_CHECKER_TYPE,
35959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_62_WIDTH },
35960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_63_CHECKER_TYPE,
35961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_63_WIDTH },
35962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_64_CHECKER_TYPE,
35963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_64_WIDTH },
35964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_65_CHECKER_TYPE,
35965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_65_WIDTH },
35966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_66_CHECKER_TYPE,
35967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_66_WIDTH },
35968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_67_CHECKER_TYPE,
35969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_67_WIDTH },
35970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_68_CHECKER_TYPE,
35971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_68_WIDTH },
35972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_69_CHECKER_TYPE,
35973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_69_WIDTH },
35974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_70_CHECKER_TYPE,
35975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_70_WIDTH },
35976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_71_CHECKER_TYPE,
35977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_71_WIDTH },
35978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_72_CHECKER_TYPE,
35979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_72_WIDTH },
35980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_73_CHECKER_TYPE,
35981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_73_WIDTH },
35982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_74_CHECKER_TYPE,
35983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_74_WIDTH },
35984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_75_CHECKER_TYPE,
35985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_75_WIDTH },
35986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_76_CHECKER_TYPE,
35987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_76_WIDTH },
35988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_77_CHECKER_TYPE,
35989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_77_WIDTH },
35990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_78_CHECKER_TYPE,
35991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_78_WIDTH },
35992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_79_CHECKER_TYPE,
35993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_79_WIDTH },
35994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_80_CHECKER_TYPE,
35995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_80_WIDTH },
35996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_81_CHECKER_TYPE,
35997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_81_WIDTH },
35998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_82_CHECKER_TYPE,
35999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_82_WIDTH },
36000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_83_CHECKER_TYPE,
36001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_83_WIDTH },
36002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_84_CHECKER_TYPE,
36003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_84_WIDTH },
36004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_85_CHECKER_TYPE,
36005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_85_WIDTH },
36006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_86_CHECKER_TYPE,
36007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_86_WIDTH },
36008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_87_CHECKER_TYPE,
36009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_87_WIDTH },
36010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_88_CHECKER_TYPE,
36011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_88_WIDTH },
36012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_89_CHECKER_TYPE,
36013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_89_WIDTH },
36014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_90_CHECKER_TYPE,
36015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_90_WIDTH },
36016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_91_CHECKER_TYPE,
36017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_91_WIDTH },
36018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_92_CHECKER_TYPE,
36019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_92_WIDTH },
36020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_93_CHECKER_TYPE,
36021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_93_WIDTH },
36022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_94_CHECKER_TYPE,
36023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_94_WIDTH },
36024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_95_CHECKER_TYPE,
36025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_95_WIDTH },
36026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_96_CHECKER_TYPE,
36027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_96_WIDTH },
36028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_97_CHECKER_TYPE,
36029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_97_WIDTH },
36030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_98_CHECKER_TYPE,
36031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_98_WIDTH },
36032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_99_CHECKER_TYPE,
36033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_99_WIDTH },
36034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_100_CHECKER_TYPE,
36035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_100_WIDTH },
36036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_101_CHECKER_TYPE,
36037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_101_WIDTH },
36038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_102_CHECKER_TYPE,
36039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_102_WIDTH },
36040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_103_CHECKER_TYPE,
36041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_103_WIDTH },
36042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_104_CHECKER_TYPE,
36043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_104_WIDTH },
36044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_105_CHECKER_TYPE,
36045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_105_WIDTH },
36046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_106_CHECKER_TYPE,
36047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_106_WIDTH },
36048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_107_CHECKER_TYPE,
36049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_107_WIDTH },
36050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_108_CHECKER_TYPE,
36051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_108_WIDTH },
36052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_109_CHECKER_TYPE,
36053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_109_WIDTH },
36054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_110_CHECKER_TYPE,
36055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_110_WIDTH },
36056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_111_CHECKER_TYPE,
36057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_111_WIDTH },
36058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_112_CHECKER_TYPE,
36059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_112_WIDTH },
36060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_113_CHECKER_TYPE,
36061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_113_WIDTH },
36062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_114_CHECKER_TYPE,
36063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_114_WIDTH },
36064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_115_CHECKER_TYPE,
36065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_115_WIDTH },
36066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_116_CHECKER_TYPE,
36067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_116_WIDTH },
36068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_117_CHECKER_TYPE,
36069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_117_WIDTH },
36070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_118_CHECKER_TYPE,
36071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_118_WIDTH },
36072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_119_CHECKER_TYPE,
36073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_119_WIDTH },
36074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_120_CHECKER_TYPE,
36075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_120_WIDTH },
36076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_121_CHECKER_TYPE,
36077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_121_WIDTH },
36078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_122_CHECKER_TYPE,
36079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_122_WIDTH },
36080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_123_CHECKER_TYPE,
36081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_123_WIDTH },
36082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_124_CHECKER_TYPE,
36083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_124_WIDTH },
36084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_125_CHECKER_TYPE,
36085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_125_WIDTH },
36086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_126_CHECKER_TYPE,
36087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_126_WIDTH },
36088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_127_CHECKER_TYPE,
36089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_127_WIDTH },
36090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_128_CHECKER_TYPE,
36091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_128_WIDTH },
36092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_129_CHECKER_TYPE,
36093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_129_WIDTH },
36094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_130_CHECKER_TYPE,
36095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_130_WIDTH },
36096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_131_CHECKER_TYPE,
36097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_131_WIDTH },
36098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_132_CHECKER_TYPE,
36099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_132_WIDTH },
36100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_133_CHECKER_TYPE,
36101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_133_WIDTH },
36102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_134_CHECKER_TYPE,
36103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_134_WIDTH },
36104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_135_CHECKER_TYPE,
36105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_135_WIDTH },
36106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_136_CHECKER_TYPE,
36107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_136_WIDTH },
36108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_137_CHECKER_TYPE,
36109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_137_WIDTH },
36110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_138_CHECKER_TYPE,
36111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_138_WIDTH },
36112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_139_CHECKER_TYPE,
36113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_139_WIDTH },
36114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_140_CHECKER_TYPE,
36115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_140_WIDTH },
36116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_141_CHECKER_TYPE,
36117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_141_WIDTH },
36118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_142_CHECKER_TYPE,
36119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_142_WIDTH },
36120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_143_CHECKER_TYPE,
36121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_143_WIDTH },
36122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_144_CHECKER_TYPE,
36123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_144_WIDTH },
36124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_145_CHECKER_TYPE,
36125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_145_WIDTH },
36126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_146_CHECKER_TYPE,
36127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_146_WIDTH },
36128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_147_CHECKER_TYPE,
36129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_147_WIDTH },
36130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_148_CHECKER_TYPE,
36131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_148_WIDTH },
36132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_149_CHECKER_TYPE,
36133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_149_WIDTH },
36134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_150_CHECKER_TYPE,
36135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_150_WIDTH },
36136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_151_CHECKER_TYPE,
36137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_151_WIDTH },
36138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_152_CHECKER_TYPE,
36139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_152_WIDTH },
36140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_153_CHECKER_TYPE,
36141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_153_WIDTH },
36142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_154_CHECKER_TYPE,
36143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_154_WIDTH },
36144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_155_CHECKER_TYPE,
36145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_155_WIDTH },
36146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_156_CHECKER_TYPE,
36147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_156_WIDTH },
36148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_157_CHECKER_TYPE,
36149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_157_WIDTH },
36150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_158_CHECKER_TYPE,
36151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_158_WIDTH },
36152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_159_CHECKER_TYPE,
36153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_159_WIDTH },
36154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_160_CHECKER_TYPE,
36155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_160_WIDTH },
36156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_161_CHECKER_TYPE,
36157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_161_WIDTH },
36158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_162_CHECKER_TYPE,
36159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_162_WIDTH },
36160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_163_CHECKER_TYPE,
36161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_163_WIDTH },
36162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_164_CHECKER_TYPE,
36163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_164_WIDTH },
36164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_165_CHECKER_TYPE,
36165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_165_WIDTH },
36166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_166_CHECKER_TYPE,
36167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_166_WIDTH },
36168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_167_CHECKER_TYPE,
36169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_167_WIDTH },
36170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_168_CHECKER_TYPE,
36171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_168_WIDTH },
36172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_169_CHECKER_TYPE,
36173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_169_WIDTH },
36174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_170_CHECKER_TYPE,
36175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_170_WIDTH },
36176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_171_CHECKER_TYPE,
36177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_171_WIDTH },
36178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_172_CHECKER_TYPE,
36179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_172_WIDTH },
36180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_173_CHECKER_TYPE,
36181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_173_WIDTH },
36182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_174_CHECKER_TYPE,
36183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_174_WIDTH },
36184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_175_CHECKER_TYPE,
36185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_175_WIDTH },
36186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_176_CHECKER_TYPE,
36187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_176_WIDTH },
36188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_177_CHECKER_TYPE,
36189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_177_WIDTH },
36190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_178_CHECKER_TYPE,
36191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_178_WIDTH },
36192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_179_CHECKER_TYPE,
36193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_179_WIDTH },
36194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_180_CHECKER_TYPE,
36195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_180_WIDTH },
36196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_181_CHECKER_TYPE,
36197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_181_WIDTH },
36198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_182_CHECKER_TYPE,
36199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_182_WIDTH },
36200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_183_CHECKER_TYPE,
36201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_183_WIDTH },
36202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_184_CHECKER_TYPE,
36203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_184_WIDTH },
36204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_185_CHECKER_TYPE,
36205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_185_WIDTH },
36206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_186_CHECKER_TYPE,
36207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_186_WIDTH },
36208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_187_CHECKER_TYPE,
36209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_187_WIDTH },
36210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_188_CHECKER_TYPE,
36211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_188_WIDTH },
36212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_189_CHECKER_TYPE,
36213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_189_WIDTH },
36214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_190_CHECKER_TYPE,
36215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_190_WIDTH },
36216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_191_CHECKER_TYPE,
36217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_191_WIDTH },
36218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_192_CHECKER_TYPE,
36219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_192_WIDTH },
36220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_193_CHECKER_TYPE,
36221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_193_WIDTH },
36222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_194_CHECKER_TYPE,
36223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_194_WIDTH },
36224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_195_CHECKER_TYPE,
36225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_195_WIDTH },
36226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_196_CHECKER_TYPE,
36227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_196_WIDTH },
36228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_197_CHECKER_TYPE,
36229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_197_WIDTH },
36230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_198_CHECKER_TYPE,
36231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_198_WIDTH },
36232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_199_CHECKER_TYPE,
36233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_199_WIDTH },
36234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_200_CHECKER_TYPE,
36235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_200_WIDTH },
36236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_201_CHECKER_TYPE,
36237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_201_WIDTH },
36238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_202_CHECKER_TYPE,
36239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_202_WIDTH },
36240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_203_CHECKER_TYPE,
36241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_203_WIDTH },
36242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_204_CHECKER_TYPE,
36243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_204_WIDTH },
36244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_205_CHECKER_TYPE,
36245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_205_WIDTH },
36246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_206_CHECKER_TYPE,
36247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_206_WIDTH },
36248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_207_CHECKER_TYPE,
36249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_207_WIDTH },
36250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_208_CHECKER_TYPE,
36251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_208_WIDTH },
36252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_209_CHECKER_TYPE,
36253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_209_WIDTH },
36254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_210_CHECKER_TYPE,
36255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_210_WIDTH },
36256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_211_CHECKER_TYPE,
36257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_211_WIDTH },
36258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_212_CHECKER_TYPE,
36259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_212_WIDTH },
36260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_213_CHECKER_TYPE,
36261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_213_WIDTH },
36262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_214_CHECKER_TYPE,
36263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_214_WIDTH },
36264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_215_CHECKER_TYPE,
36265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_215_WIDTH },
36266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_216_CHECKER_TYPE,
36267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_216_WIDTH },
36268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_217_CHECKER_TYPE,
36269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_217_WIDTH },
36270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_218_CHECKER_TYPE,
36271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_218_WIDTH },
36272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_219_CHECKER_TYPE,
36273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_219_WIDTH },
36274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_220_CHECKER_TYPE,
36275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_220_WIDTH },
36276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_221_CHECKER_TYPE,
36277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_221_WIDTH },
36278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_222_CHECKER_TYPE,
36279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_222_WIDTH },
36280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_223_CHECKER_TYPE,
36281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_223_WIDTH },
36282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_224_CHECKER_TYPE,
36283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_224_WIDTH },
36284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_225_CHECKER_TYPE,
36285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_225_WIDTH },
36286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_226_CHECKER_TYPE,
36287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_226_WIDTH },
36288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_227_CHECKER_TYPE,
36289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_227_WIDTH },
36290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_228_CHECKER_TYPE,
36291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_228_WIDTH },
36292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_229_CHECKER_TYPE,
36293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_229_WIDTH },
36294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_230_CHECKER_TYPE,
36295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_230_WIDTH },
36296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_231_CHECKER_TYPE,
36297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_231_WIDTH },
36298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_232_CHECKER_TYPE,
36299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_232_WIDTH },
36300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_233_CHECKER_TYPE,
36301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_233_WIDTH },
36302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_234_CHECKER_TYPE,
36303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_234_WIDTH },
36304  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_235_CHECKER_TYPE,
36305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_235_WIDTH },
36306  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_236_CHECKER_TYPE,
36307  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_236_WIDTH },
36308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_237_CHECKER_TYPE,
36309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_237_WIDTH },
36310  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_238_CHECKER_TYPE,
36311  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_238_WIDTH },
36312  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_239_CHECKER_TYPE,
36313  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_239_WIDTH },
36314  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_240_CHECKER_TYPE,
36315  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_240_WIDTH },
36316  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_241_CHECKER_TYPE,
36317  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_241_WIDTH },
36318  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_242_CHECKER_TYPE,
36319  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_242_WIDTH },
36320  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_243_CHECKER_TYPE,
36321  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_243_WIDTH },
36322  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_244_CHECKER_TYPE,
36323  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_244_WIDTH },
36324  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_245_CHECKER_TYPE,
36325  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_245_WIDTH },
36326  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_246_CHECKER_TYPE,
36327  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_246_WIDTH },
36328  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_247_CHECKER_TYPE,
36329  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_247_WIDTH },
36330  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_248_CHECKER_TYPE,
36331  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_248_WIDTH },
36332  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_249_CHECKER_TYPE,
36333  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_249_WIDTH },
36334  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_250_CHECKER_TYPE,
36335  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_250_WIDTH },
36336  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_251_CHECKER_TYPE,
36337  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_251_WIDTH },
36338  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_252_CHECKER_TYPE,
36339  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_252_WIDTH },
36340  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_253_CHECKER_TYPE,
36341  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_253_WIDTH },
36342  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_254_CHECKER_TYPE,
36343  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_254_WIDTH },
36344  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_255_CHECKER_TYPE,
36345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_GROUP_255_WIDTH },
36346 };
36347 
36353 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_MAX_NUM_CHECKERS] =
36354 {
36355  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_0_CHECKER_TYPE,
36356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_0_WIDTH },
36357  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_1_CHECKER_TYPE,
36358  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_1_WIDTH },
36359  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_2_CHECKER_TYPE,
36360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_2_WIDTH },
36361  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_3_CHECKER_TYPE,
36362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_3_WIDTH },
36363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_4_CHECKER_TYPE,
36364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_4_WIDTH },
36365  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_5_CHECKER_TYPE,
36366  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_5_WIDTH },
36367  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_6_CHECKER_TYPE,
36368  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_6_WIDTH },
36369  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_7_CHECKER_TYPE,
36370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_7_WIDTH },
36371  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_8_CHECKER_TYPE,
36372  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_8_WIDTH },
36373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_9_CHECKER_TYPE,
36374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_9_WIDTH },
36375  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_10_CHECKER_TYPE,
36376  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_10_WIDTH },
36377  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_11_CHECKER_TYPE,
36378  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_11_WIDTH },
36379  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_12_CHECKER_TYPE,
36380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_12_WIDTH },
36381  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_13_CHECKER_TYPE,
36382  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_13_WIDTH },
36383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_14_CHECKER_TYPE,
36384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_14_WIDTH },
36385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_15_CHECKER_TYPE,
36386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_15_WIDTH },
36387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_16_CHECKER_TYPE,
36388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_16_WIDTH },
36389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_17_CHECKER_TYPE,
36390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_17_WIDTH },
36391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_18_CHECKER_TYPE,
36392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_18_WIDTH },
36393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_19_CHECKER_TYPE,
36394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_19_WIDTH },
36395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_20_CHECKER_TYPE,
36396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_20_WIDTH },
36397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_21_CHECKER_TYPE,
36398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_21_WIDTH },
36399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_22_CHECKER_TYPE,
36400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_22_WIDTH },
36401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_23_CHECKER_TYPE,
36402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_23_WIDTH },
36403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_24_CHECKER_TYPE,
36404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_24_WIDTH },
36405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_25_CHECKER_TYPE,
36406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_25_WIDTH },
36407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_26_CHECKER_TYPE,
36408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_26_WIDTH },
36409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_27_CHECKER_TYPE,
36410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_27_WIDTH },
36411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_28_CHECKER_TYPE,
36412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_28_WIDTH },
36413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_29_CHECKER_TYPE,
36414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_29_WIDTH },
36415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_30_CHECKER_TYPE,
36416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_30_WIDTH },
36417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_31_CHECKER_TYPE,
36418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_31_WIDTH },
36419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_32_CHECKER_TYPE,
36420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_32_WIDTH },
36421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_33_CHECKER_TYPE,
36422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_33_WIDTH },
36423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_34_CHECKER_TYPE,
36424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_34_WIDTH },
36425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_35_CHECKER_TYPE,
36426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_35_WIDTH },
36427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_36_CHECKER_TYPE,
36428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_36_WIDTH },
36429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_37_CHECKER_TYPE,
36430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_37_WIDTH },
36431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_38_CHECKER_TYPE,
36432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_38_WIDTH },
36433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_39_CHECKER_TYPE,
36434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_39_WIDTH },
36435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_40_CHECKER_TYPE,
36436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_40_WIDTH },
36437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_41_CHECKER_TYPE,
36438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_41_WIDTH },
36439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_42_CHECKER_TYPE,
36440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_42_WIDTH },
36441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_43_CHECKER_TYPE,
36442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_43_WIDTH },
36443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_44_CHECKER_TYPE,
36444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_44_WIDTH },
36445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_45_CHECKER_TYPE,
36446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_45_WIDTH },
36447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_46_CHECKER_TYPE,
36448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_46_WIDTH },
36449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_47_CHECKER_TYPE,
36450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_47_WIDTH },
36451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_48_CHECKER_TYPE,
36452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_48_WIDTH },
36453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_49_CHECKER_TYPE,
36454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_49_WIDTH },
36455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_50_CHECKER_TYPE,
36456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_50_WIDTH },
36457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_51_CHECKER_TYPE,
36458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_51_WIDTH },
36459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_52_CHECKER_TYPE,
36460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_52_WIDTH },
36461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_53_CHECKER_TYPE,
36462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_53_WIDTH },
36463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_54_CHECKER_TYPE,
36464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_54_WIDTH },
36465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_55_CHECKER_TYPE,
36466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_55_WIDTH },
36467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_56_CHECKER_TYPE,
36468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_56_WIDTH },
36469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_57_CHECKER_TYPE,
36470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_57_WIDTH },
36471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_58_CHECKER_TYPE,
36472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_58_WIDTH },
36473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_59_CHECKER_TYPE,
36474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_59_WIDTH },
36475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_60_CHECKER_TYPE,
36476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_60_WIDTH },
36477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_61_CHECKER_TYPE,
36478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_61_WIDTH },
36479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_62_CHECKER_TYPE,
36480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_62_WIDTH },
36481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_63_CHECKER_TYPE,
36482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_63_WIDTH },
36483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_64_CHECKER_TYPE,
36484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_64_WIDTH },
36485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_65_CHECKER_TYPE,
36486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_65_WIDTH },
36487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_66_CHECKER_TYPE,
36488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_66_WIDTH },
36489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_67_CHECKER_TYPE,
36490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_67_WIDTH },
36491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_68_CHECKER_TYPE,
36492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_68_WIDTH },
36493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_69_CHECKER_TYPE,
36494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_69_WIDTH },
36495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_70_CHECKER_TYPE,
36496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_70_WIDTH },
36497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_71_CHECKER_TYPE,
36498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_71_WIDTH },
36499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_72_CHECKER_TYPE,
36500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_72_WIDTH },
36501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_73_CHECKER_TYPE,
36502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_73_WIDTH },
36503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_74_CHECKER_TYPE,
36504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_74_WIDTH },
36505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_75_CHECKER_TYPE,
36506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_75_WIDTH },
36507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_76_CHECKER_TYPE,
36508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_76_WIDTH },
36509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_77_CHECKER_TYPE,
36510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_77_WIDTH },
36511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_78_CHECKER_TYPE,
36512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_78_WIDTH },
36513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_79_CHECKER_TYPE,
36514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_79_WIDTH },
36515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_80_CHECKER_TYPE,
36516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_80_WIDTH },
36517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_81_CHECKER_TYPE,
36518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_81_WIDTH },
36519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_82_CHECKER_TYPE,
36520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_82_WIDTH },
36521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_83_CHECKER_TYPE,
36522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_83_WIDTH },
36523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_84_CHECKER_TYPE,
36524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_84_WIDTH },
36525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_85_CHECKER_TYPE,
36526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_85_WIDTH },
36527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_86_CHECKER_TYPE,
36528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_86_WIDTH },
36529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_87_CHECKER_TYPE,
36530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_87_WIDTH },
36531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_88_CHECKER_TYPE,
36532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_88_WIDTH },
36533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_89_CHECKER_TYPE,
36534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_89_WIDTH },
36535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_90_CHECKER_TYPE,
36536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_90_WIDTH },
36537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_91_CHECKER_TYPE,
36538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_91_WIDTH },
36539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_92_CHECKER_TYPE,
36540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_92_WIDTH },
36541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_93_CHECKER_TYPE,
36542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_93_WIDTH },
36543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_94_CHECKER_TYPE,
36544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_94_WIDTH },
36545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_95_CHECKER_TYPE,
36546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_95_WIDTH },
36547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_96_CHECKER_TYPE,
36548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_96_WIDTH },
36549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_97_CHECKER_TYPE,
36550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_97_WIDTH },
36551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_98_CHECKER_TYPE,
36552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_98_WIDTH },
36553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_99_CHECKER_TYPE,
36554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_99_WIDTH },
36555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_100_CHECKER_TYPE,
36556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_100_WIDTH },
36557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_101_CHECKER_TYPE,
36558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_101_WIDTH },
36559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_102_CHECKER_TYPE,
36560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_102_WIDTH },
36561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_103_CHECKER_TYPE,
36562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_103_WIDTH },
36563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_104_CHECKER_TYPE,
36564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_104_WIDTH },
36565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_105_CHECKER_TYPE,
36566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_105_WIDTH },
36567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_106_CHECKER_TYPE,
36568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_106_WIDTH },
36569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_107_CHECKER_TYPE,
36570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_107_WIDTH },
36571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_108_CHECKER_TYPE,
36572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_108_WIDTH },
36573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_109_CHECKER_TYPE,
36574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_109_WIDTH },
36575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_110_CHECKER_TYPE,
36576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_110_WIDTH },
36577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_111_CHECKER_TYPE,
36578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_111_WIDTH },
36579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_112_CHECKER_TYPE,
36580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_112_WIDTH },
36581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_113_CHECKER_TYPE,
36582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_113_WIDTH },
36583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_114_CHECKER_TYPE,
36584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_114_WIDTH },
36585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_115_CHECKER_TYPE,
36586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_115_WIDTH },
36587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_116_CHECKER_TYPE,
36588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_116_WIDTH },
36589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_117_CHECKER_TYPE,
36590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_117_WIDTH },
36591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_118_CHECKER_TYPE,
36592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_118_WIDTH },
36593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_119_CHECKER_TYPE,
36594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_119_WIDTH },
36595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_120_CHECKER_TYPE,
36596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_120_WIDTH },
36597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_121_CHECKER_TYPE,
36598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_121_WIDTH },
36599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_122_CHECKER_TYPE,
36600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_122_WIDTH },
36601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_123_CHECKER_TYPE,
36602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_123_WIDTH },
36603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_124_CHECKER_TYPE,
36604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_124_WIDTH },
36605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_125_CHECKER_TYPE,
36606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_125_WIDTH },
36607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_126_CHECKER_TYPE,
36608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_126_WIDTH },
36609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_127_CHECKER_TYPE,
36610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_127_WIDTH },
36611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_128_CHECKER_TYPE,
36612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_128_WIDTH },
36613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_129_CHECKER_TYPE,
36614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_129_WIDTH },
36615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_130_CHECKER_TYPE,
36616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_130_WIDTH },
36617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_131_CHECKER_TYPE,
36618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_131_WIDTH },
36619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_132_CHECKER_TYPE,
36620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_132_WIDTH },
36621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_133_CHECKER_TYPE,
36622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_133_WIDTH },
36623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_134_CHECKER_TYPE,
36624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_134_WIDTH },
36625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_135_CHECKER_TYPE,
36626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_135_WIDTH },
36627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_136_CHECKER_TYPE,
36628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_136_WIDTH },
36629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_137_CHECKER_TYPE,
36630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_137_WIDTH },
36631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_138_CHECKER_TYPE,
36632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_138_WIDTH },
36633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_139_CHECKER_TYPE,
36634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_139_WIDTH },
36635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_140_CHECKER_TYPE,
36636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_140_WIDTH },
36637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_141_CHECKER_TYPE,
36638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_141_WIDTH },
36639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_142_CHECKER_TYPE,
36640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_142_WIDTH },
36641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_143_CHECKER_TYPE,
36642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_143_WIDTH },
36643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_144_CHECKER_TYPE,
36644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_144_WIDTH },
36645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_145_CHECKER_TYPE,
36646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_145_WIDTH },
36647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_146_CHECKER_TYPE,
36648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_146_WIDTH },
36649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_147_CHECKER_TYPE,
36650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_147_WIDTH },
36651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_148_CHECKER_TYPE,
36652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_148_WIDTH },
36653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_149_CHECKER_TYPE,
36654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_149_WIDTH },
36655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_150_CHECKER_TYPE,
36656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_150_WIDTH },
36657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_151_CHECKER_TYPE,
36658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_151_WIDTH },
36659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_152_CHECKER_TYPE,
36660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_152_WIDTH },
36661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_153_CHECKER_TYPE,
36662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_153_WIDTH },
36663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_154_CHECKER_TYPE,
36664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_154_WIDTH },
36665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_155_CHECKER_TYPE,
36666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_155_WIDTH },
36667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_156_CHECKER_TYPE,
36668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_156_WIDTH },
36669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_157_CHECKER_TYPE,
36670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_157_WIDTH },
36671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_158_CHECKER_TYPE,
36672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_158_WIDTH },
36673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_159_CHECKER_TYPE,
36674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_159_WIDTH },
36675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_160_CHECKER_TYPE,
36676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_160_WIDTH },
36677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_161_CHECKER_TYPE,
36678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_161_WIDTH },
36679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_162_CHECKER_TYPE,
36680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_162_WIDTH },
36681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_163_CHECKER_TYPE,
36682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_163_WIDTH },
36683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_164_CHECKER_TYPE,
36684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_164_WIDTH },
36685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_165_CHECKER_TYPE,
36686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_165_WIDTH },
36687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_166_CHECKER_TYPE,
36688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_166_WIDTH },
36689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_167_CHECKER_TYPE,
36690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_167_WIDTH },
36691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_168_CHECKER_TYPE,
36692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_168_WIDTH },
36693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_169_CHECKER_TYPE,
36694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_169_WIDTH },
36695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_170_CHECKER_TYPE,
36696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_170_WIDTH },
36697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_171_CHECKER_TYPE,
36698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_171_WIDTH },
36699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_172_CHECKER_TYPE,
36700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_172_WIDTH },
36701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_173_CHECKER_TYPE,
36702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_173_WIDTH },
36703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_174_CHECKER_TYPE,
36704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_174_WIDTH },
36705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_175_CHECKER_TYPE,
36706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_175_WIDTH },
36707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_176_CHECKER_TYPE,
36708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_176_WIDTH },
36709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_177_CHECKER_TYPE,
36710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_177_WIDTH },
36711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_178_CHECKER_TYPE,
36712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_178_WIDTH },
36713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_179_CHECKER_TYPE,
36714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_179_WIDTH },
36715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_180_CHECKER_TYPE,
36716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_180_WIDTH },
36717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_181_CHECKER_TYPE,
36718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_181_WIDTH },
36719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_182_CHECKER_TYPE,
36720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_182_WIDTH },
36721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_183_CHECKER_TYPE,
36722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_183_WIDTH },
36723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_184_CHECKER_TYPE,
36724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_184_WIDTH },
36725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_185_CHECKER_TYPE,
36726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_185_WIDTH },
36727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_186_CHECKER_TYPE,
36728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_186_WIDTH },
36729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_187_CHECKER_TYPE,
36730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_187_WIDTH },
36731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_188_CHECKER_TYPE,
36732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_188_WIDTH },
36733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_189_CHECKER_TYPE,
36734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_189_WIDTH },
36735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_190_CHECKER_TYPE,
36736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_190_WIDTH },
36737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_191_CHECKER_TYPE,
36738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_191_WIDTH },
36739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_192_CHECKER_TYPE,
36740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_192_WIDTH },
36741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_193_CHECKER_TYPE,
36742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_193_WIDTH },
36743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_194_CHECKER_TYPE,
36744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_194_WIDTH },
36745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_195_CHECKER_TYPE,
36746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_195_WIDTH },
36747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_196_CHECKER_TYPE,
36748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_196_WIDTH },
36749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_197_CHECKER_TYPE,
36750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_197_WIDTH },
36751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_198_CHECKER_TYPE,
36752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_198_WIDTH },
36753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_199_CHECKER_TYPE,
36754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_199_WIDTH },
36755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_200_CHECKER_TYPE,
36756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_200_WIDTH },
36757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_201_CHECKER_TYPE,
36758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_201_WIDTH },
36759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_202_CHECKER_TYPE,
36760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_202_WIDTH },
36761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_203_CHECKER_TYPE,
36762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_203_WIDTH },
36763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_204_CHECKER_TYPE,
36764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_204_WIDTH },
36765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_205_CHECKER_TYPE,
36766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_205_WIDTH },
36767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_206_CHECKER_TYPE,
36768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_206_WIDTH },
36769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_207_CHECKER_TYPE,
36770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_207_WIDTH },
36771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_208_CHECKER_TYPE,
36772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_208_WIDTH },
36773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_209_CHECKER_TYPE,
36774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_209_WIDTH },
36775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_210_CHECKER_TYPE,
36776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_210_WIDTH },
36777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_211_CHECKER_TYPE,
36778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_211_WIDTH },
36779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_212_CHECKER_TYPE,
36780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_212_WIDTH },
36781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_213_CHECKER_TYPE,
36782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_213_WIDTH },
36783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_214_CHECKER_TYPE,
36784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_214_WIDTH },
36785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_215_CHECKER_TYPE,
36786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_215_WIDTH },
36787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_216_CHECKER_TYPE,
36788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_216_WIDTH },
36789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_217_CHECKER_TYPE,
36790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_217_WIDTH },
36791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_218_CHECKER_TYPE,
36792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_218_WIDTH },
36793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_219_CHECKER_TYPE,
36794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_219_WIDTH },
36795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_220_CHECKER_TYPE,
36796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_220_WIDTH },
36797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_221_CHECKER_TYPE,
36798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_221_WIDTH },
36799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_222_CHECKER_TYPE,
36800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_222_WIDTH },
36801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_223_CHECKER_TYPE,
36802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_223_WIDTH },
36803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_224_CHECKER_TYPE,
36804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_224_WIDTH },
36805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_225_CHECKER_TYPE,
36806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_225_WIDTH },
36807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_226_CHECKER_TYPE,
36808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_226_WIDTH },
36809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_227_CHECKER_TYPE,
36810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_227_WIDTH },
36811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_228_CHECKER_TYPE,
36812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_228_WIDTH },
36813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_229_CHECKER_TYPE,
36814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_229_WIDTH },
36815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_230_CHECKER_TYPE,
36816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_230_WIDTH },
36817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_231_CHECKER_TYPE,
36818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_231_WIDTH },
36819  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_232_CHECKER_TYPE,
36820  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_232_WIDTH },
36821  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_233_CHECKER_TYPE,
36822  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_233_WIDTH },
36823  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_234_CHECKER_TYPE,
36824  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_234_WIDTH },
36825  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_235_CHECKER_TYPE,
36826  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_235_WIDTH },
36827  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_236_CHECKER_TYPE,
36828  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_236_WIDTH },
36829  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_237_CHECKER_TYPE,
36830  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_237_WIDTH },
36831  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_238_CHECKER_TYPE,
36832  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_238_WIDTH },
36833  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_239_CHECKER_TYPE,
36834  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_239_WIDTH },
36835  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_240_CHECKER_TYPE,
36836  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_240_WIDTH },
36837  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_241_CHECKER_TYPE,
36838  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_241_WIDTH },
36839  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_242_CHECKER_TYPE,
36840  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_242_WIDTH },
36841  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_243_CHECKER_TYPE,
36842  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_243_WIDTH },
36843  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_244_CHECKER_TYPE,
36844  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_244_WIDTH },
36845  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_245_CHECKER_TYPE,
36846  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_245_WIDTH },
36847  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_246_CHECKER_TYPE,
36848  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_246_WIDTH },
36849  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_247_CHECKER_TYPE,
36850  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_247_WIDTH },
36851  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_248_CHECKER_TYPE,
36852  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_248_WIDTH },
36853  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_249_CHECKER_TYPE,
36854  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_249_WIDTH },
36855  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_250_CHECKER_TYPE,
36856  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_250_WIDTH },
36857  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_251_CHECKER_TYPE,
36858  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_251_WIDTH },
36859  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_252_CHECKER_TYPE,
36860  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_252_WIDTH },
36861  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_253_CHECKER_TYPE,
36862  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_253_WIDTH },
36863  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_254_CHECKER_TYPE,
36864  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_254_WIDTH },
36865  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_255_CHECKER_TYPE,
36866  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_GROUP_255_WIDTH },
36867 };
36868 
36874 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_MAX_NUM_CHECKERS] =
36875 {
36876  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_0_CHECKER_TYPE,
36877  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_0_WIDTH },
36878  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_1_CHECKER_TYPE,
36879  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_1_WIDTH },
36880  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_2_CHECKER_TYPE,
36881  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_2_WIDTH },
36882  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_3_CHECKER_TYPE,
36883  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_3_WIDTH },
36884  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_4_CHECKER_TYPE,
36885  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_4_WIDTH },
36886  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_5_CHECKER_TYPE,
36887  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_5_WIDTH },
36888  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_6_CHECKER_TYPE,
36889  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_6_WIDTH },
36890  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_7_CHECKER_TYPE,
36891  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_7_WIDTH },
36892  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_8_CHECKER_TYPE,
36893  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_8_WIDTH },
36894  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_9_CHECKER_TYPE,
36895  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_9_WIDTH },
36896  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_10_CHECKER_TYPE,
36897  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_10_WIDTH },
36898  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_11_CHECKER_TYPE,
36899  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_11_WIDTH },
36900  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_12_CHECKER_TYPE,
36901  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_12_WIDTH },
36902  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_13_CHECKER_TYPE,
36903  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_13_WIDTH },
36904  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_14_CHECKER_TYPE,
36905  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_14_WIDTH },
36906  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_15_CHECKER_TYPE,
36907  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_15_WIDTH },
36908  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_16_CHECKER_TYPE,
36909  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_16_WIDTH },
36910  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_17_CHECKER_TYPE,
36911  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_17_WIDTH },
36912  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_18_CHECKER_TYPE,
36913  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_18_WIDTH },
36914  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_19_CHECKER_TYPE,
36915  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_19_WIDTH },
36916  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_20_CHECKER_TYPE,
36917  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_20_WIDTH },
36918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_21_CHECKER_TYPE,
36919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_21_WIDTH },
36920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_22_CHECKER_TYPE,
36921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_22_WIDTH },
36922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_23_CHECKER_TYPE,
36923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_23_WIDTH },
36924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_24_CHECKER_TYPE,
36925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_24_WIDTH },
36926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_25_CHECKER_TYPE,
36927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_25_WIDTH },
36928  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_26_CHECKER_TYPE,
36929  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_26_WIDTH },
36930  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_27_CHECKER_TYPE,
36931  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_27_WIDTH },
36932  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_28_CHECKER_TYPE,
36933  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_28_WIDTH },
36934  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_29_CHECKER_TYPE,
36935  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_29_WIDTH },
36936  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_30_CHECKER_TYPE,
36937  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_30_WIDTH },
36938  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_31_CHECKER_TYPE,
36939  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_31_WIDTH },
36940  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_32_CHECKER_TYPE,
36941  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_32_WIDTH },
36942  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_33_CHECKER_TYPE,
36943  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_33_WIDTH },
36944  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_34_CHECKER_TYPE,
36945  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_34_WIDTH },
36946  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_35_CHECKER_TYPE,
36947  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_35_WIDTH },
36948  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_36_CHECKER_TYPE,
36949  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_36_WIDTH },
36950  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_37_CHECKER_TYPE,
36951  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_37_WIDTH },
36952  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_38_CHECKER_TYPE,
36953  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_38_WIDTH },
36954  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_39_CHECKER_TYPE,
36955  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_39_WIDTH },
36956  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_40_CHECKER_TYPE,
36957  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_40_WIDTH },
36958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_41_CHECKER_TYPE,
36959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_41_WIDTH },
36960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_42_CHECKER_TYPE,
36961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_42_WIDTH },
36962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_43_CHECKER_TYPE,
36963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_43_WIDTH },
36964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_44_CHECKER_TYPE,
36965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_44_WIDTH },
36966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_45_CHECKER_TYPE,
36967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_45_WIDTH },
36968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_46_CHECKER_TYPE,
36969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_46_WIDTH },
36970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_47_CHECKER_TYPE,
36971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_47_WIDTH },
36972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_48_CHECKER_TYPE,
36973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_48_WIDTH },
36974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_49_CHECKER_TYPE,
36975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_49_WIDTH },
36976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_50_CHECKER_TYPE,
36977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_50_WIDTH },
36978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_51_CHECKER_TYPE,
36979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_51_WIDTH },
36980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_52_CHECKER_TYPE,
36981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_52_WIDTH },
36982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_53_CHECKER_TYPE,
36983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_53_WIDTH },
36984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_54_CHECKER_TYPE,
36985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_54_WIDTH },
36986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_55_CHECKER_TYPE,
36987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_55_WIDTH },
36988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_56_CHECKER_TYPE,
36989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_56_WIDTH },
36990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_57_CHECKER_TYPE,
36991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_57_WIDTH },
36992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_58_CHECKER_TYPE,
36993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_58_WIDTH },
36994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_59_CHECKER_TYPE,
36995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_59_WIDTH },
36996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_60_CHECKER_TYPE,
36997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_60_WIDTH },
36998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_61_CHECKER_TYPE,
36999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_61_WIDTH },
37000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_62_CHECKER_TYPE,
37001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_62_WIDTH },
37002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_63_CHECKER_TYPE,
37003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_63_WIDTH },
37004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_64_CHECKER_TYPE,
37005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_64_WIDTH },
37006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_65_CHECKER_TYPE,
37007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_65_WIDTH },
37008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_66_CHECKER_TYPE,
37009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_66_WIDTH },
37010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_67_CHECKER_TYPE,
37011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_67_WIDTH },
37012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_68_CHECKER_TYPE,
37013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_68_WIDTH },
37014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_69_CHECKER_TYPE,
37015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_69_WIDTH },
37016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_70_CHECKER_TYPE,
37017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_70_WIDTH },
37018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_71_CHECKER_TYPE,
37019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_71_WIDTH },
37020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_72_CHECKER_TYPE,
37021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_72_WIDTH },
37022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_73_CHECKER_TYPE,
37023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_73_WIDTH },
37024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_74_CHECKER_TYPE,
37025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_74_WIDTH },
37026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_75_CHECKER_TYPE,
37027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_75_WIDTH },
37028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_76_CHECKER_TYPE,
37029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_76_WIDTH },
37030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_77_CHECKER_TYPE,
37031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_77_WIDTH },
37032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_78_CHECKER_TYPE,
37033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_78_WIDTH },
37034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_79_CHECKER_TYPE,
37035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_79_WIDTH },
37036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_80_CHECKER_TYPE,
37037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_80_WIDTH },
37038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_81_CHECKER_TYPE,
37039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_81_WIDTH },
37040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_82_CHECKER_TYPE,
37041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_82_WIDTH },
37042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_83_CHECKER_TYPE,
37043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_83_WIDTH },
37044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_84_CHECKER_TYPE,
37045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_84_WIDTH },
37046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_85_CHECKER_TYPE,
37047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_85_WIDTH },
37048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_86_CHECKER_TYPE,
37049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_86_WIDTH },
37050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_87_CHECKER_TYPE,
37051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_87_WIDTH },
37052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_88_CHECKER_TYPE,
37053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_88_WIDTH },
37054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_89_CHECKER_TYPE,
37055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_89_WIDTH },
37056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_90_CHECKER_TYPE,
37057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_90_WIDTH },
37058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_91_CHECKER_TYPE,
37059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_91_WIDTH },
37060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_92_CHECKER_TYPE,
37061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_92_WIDTH },
37062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_93_CHECKER_TYPE,
37063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_93_WIDTH },
37064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_94_CHECKER_TYPE,
37065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_94_WIDTH },
37066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_95_CHECKER_TYPE,
37067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_95_WIDTH },
37068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_96_CHECKER_TYPE,
37069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_96_WIDTH },
37070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_97_CHECKER_TYPE,
37071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_97_WIDTH },
37072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_98_CHECKER_TYPE,
37073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_98_WIDTH },
37074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_99_CHECKER_TYPE,
37075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_99_WIDTH },
37076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_100_CHECKER_TYPE,
37077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_100_WIDTH },
37078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_101_CHECKER_TYPE,
37079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_101_WIDTH },
37080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_102_CHECKER_TYPE,
37081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_102_WIDTH },
37082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_103_CHECKER_TYPE,
37083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_103_WIDTH },
37084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_104_CHECKER_TYPE,
37085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_104_WIDTH },
37086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_105_CHECKER_TYPE,
37087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_105_WIDTH },
37088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_106_CHECKER_TYPE,
37089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_106_WIDTH },
37090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_107_CHECKER_TYPE,
37091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_107_WIDTH },
37092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_108_CHECKER_TYPE,
37093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_108_WIDTH },
37094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_109_CHECKER_TYPE,
37095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_109_WIDTH },
37096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_110_CHECKER_TYPE,
37097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_110_WIDTH },
37098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_111_CHECKER_TYPE,
37099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_111_WIDTH },
37100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_112_CHECKER_TYPE,
37101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_112_WIDTH },
37102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_113_CHECKER_TYPE,
37103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_113_WIDTH },
37104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_114_CHECKER_TYPE,
37105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_114_WIDTH },
37106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_115_CHECKER_TYPE,
37107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_115_WIDTH },
37108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_116_CHECKER_TYPE,
37109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_116_WIDTH },
37110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_117_CHECKER_TYPE,
37111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_117_WIDTH },
37112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_118_CHECKER_TYPE,
37113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_118_WIDTH },
37114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_119_CHECKER_TYPE,
37115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_119_WIDTH },
37116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_120_CHECKER_TYPE,
37117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_120_WIDTH },
37118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_121_CHECKER_TYPE,
37119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_121_WIDTH },
37120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_122_CHECKER_TYPE,
37121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_122_WIDTH },
37122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_123_CHECKER_TYPE,
37123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_123_WIDTH },
37124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_124_CHECKER_TYPE,
37125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_124_WIDTH },
37126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_125_CHECKER_TYPE,
37127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_125_WIDTH },
37128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_126_CHECKER_TYPE,
37129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_126_WIDTH },
37130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_127_CHECKER_TYPE,
37131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_127_WIDTH },
37132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_128_CHECKER_TYPE,
37133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_128_WIDTH },
37134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_129_CHECKER_TYPE,
37135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_129_WIDTH },
37136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_130_CHECKER_TYPE,
37137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_130_WIDTH },
37138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_131_CHECKER_TYPE,
37139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_131_WIDTH },
37140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_132_CHECKER_TYPE,
37141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_132_WIDTH },
37142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_133_CHECKER_TYPE,
37143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_133_WIDTH },
37144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_134_CHECKER_TYPE,
37145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_134_WIDTH },
37146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_135_CHECKER_TYPE,
37147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_135_WIDTH },
37148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_136_CHECKER_TYPE,
37149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_136_WIDTH },
37150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_137_CHECKER_TYPE,
37151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_137_WIDTH },
37152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_138_CHECKER_TYPE,
37153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_138_WIDTH },
37154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_139_CHECKER_TYPE,
37155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_139_WIDTH },
37156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_140_CHECKER_TYPE,
37157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_140_WIDTH },
37158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_141_CHECKER_TYPE,
37159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_141_WIDTH },
37160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_142_CHECKER_TYPE,
37161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_142_WIDTH },
37162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_143_CHECKER_TYPE,
37163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_143_WIDTH },
37164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_144_CHECKER_TYPE,
37165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_144_WIDTH },
37166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_145_CHECKER_TYPE,
37167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_145_WIDTH },
37168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_146_CHECKER_TYPE,
37169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_146_WIDTH },
37170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_147_CHECKER_TYPE,
37171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_147_WIDTH },
37172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_148_CHECKER_TYPE,
37173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_148_WIDTH },
37174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_149_CHECKER_TYPE,
37175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_149_WIDTH },
37176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_150_CHECKER_TYPE,
37177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_150_WIDTH },
37178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_151_CHECKER_TYPE,
37179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_151_WIDTH },
37180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_152_CHECKER_TYPE,
37181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_152_WIDTH },
37182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_153_CHECKER_TYPE,
37183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_153_WIDTH },
37184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_154_CHECKER_TYPE,
37185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_154_WIDTH },
37186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_155_CHECKER_TYPE,
37187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_155_WIDTH },
37188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_156_CHECKER_TYPE,
37189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_156_WIDTH },
37190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_157_CHECKER_TYPE,
37191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_157_WIDTH },
37192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_158_CHECKER_TYPE,
37193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_158_WIDTH },
37194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_159_CHECKER_TYPE,
37195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_159_WIDTH },
37196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_160_CHECKER_TYPE,
37197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_160_WIDTH },
37198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_161_CHECKER_TYPE,
37199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_161_WIDTH },
37200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_162_CHECKER_TYPE,
37201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_162_WIDTH },
37202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_163_CHECKER_TYPE,
37203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_163_WIDTH },
37204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_164_CHECKER_TYPE,
37205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_164_WIDTH },
37206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_165_CHECKER_TYPE,
37207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_165_WIDTH },
37208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_166_CHECKER_TYPE,
37209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_166_WIDTH },
37210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_167_CHECKER_TYPE,
37211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_167_WIDTH },
37212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_168_CHECKER_TYPE,
37213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_168_WIDTH },
37214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_169_CHECKER_TYPE,
37215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_169_WIDTH },
37216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_170_CHECKER_TYPE,
37217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_170_WIDTH },
37218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_171_CHECKER_TYPE,
37219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_171_WIDTH },
37220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_172_CHECKER_TYPE,
37221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_172_WIDTH },
37222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_173_CHECKER_TYPE,
37223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_173_WIDTH },
37224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_174_CHECKER_TYPE,
37225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_174_WIDTH },
37226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_175_CHECKER_TYPE,
37227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_175_WIDTH },
37228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_176_CHECKER_TYPE,
37229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_176_WIDTH },
37230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_177_CHECKER_TYPE,
37231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_177_WIDTH },
37232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_178_CHECKER_TYPE,
37233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_178_WIDTH },
37234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_179_CHECKER_TYPE,
37235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_179_WIDTH },
37236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_180_CHECKER_TYPE,
37237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_180_WIDTH },
37238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_181_CHECKER_TYPE,
37239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_181_WIDTH },
37240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_182_CHECKER_TYPE,
37241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_182_WIDTH },
37242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_183_CHECKER_TYPE,
37243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_183_WIDTH },
37244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_184_CHECKER_TYPE,
37245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_184_WIDTH },
37246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_185_CHECKER_TYPE,
37247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_185_WIDTH },
37248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_186_CHECKER_TYPE,
37249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_186_WIDTH },
37250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_187_CHECKER_TYPE,
37251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_187_WIDTH },
37252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_188_CHECKER_TYPE,
37253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_188_WIDTH },
37254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_189_CHECKER_TYPE,
37255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_189_WIDTH },
37256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_190_CHECKER_TYPE,
37257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_190_WIDTH },
37258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_191_CHECKER_TYPE,
37259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_191_WIDTH },
37260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_192_CHECKER_TYPE,
37261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_192_WIDTH },
37262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_193_CHECKER_TYPE,
37263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_193_WIDTH },
37264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_194_CHECKER_TYPE,
37265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_194_WIDTH },
37266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_195_CHECKER_TYPE,
37267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_195_WIDTH },
37268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_196_CHECKER_TYPE,
37269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_196_WIDTH },
37270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_197_CHECKER_TYPE,
37271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_197_WIDTH },
37272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_198_CHECKER_TYPE,
37273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_198_WIDTH },
37274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_199_CHECKER_TYPE,
37275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_199_WIDTH },
37276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_200_CHECKER_TYPE,
37277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_200_WIDTH },
37278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_201_CHECKER_TYPE,
37279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_201_WIDTH },
37280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_202_CHECKER_TYPE,
37281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_202_WIDTH },
37282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_203_CHECKER_TYPE,
37283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_203_WIDTH },
37284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_204_CHECKER_TYPE,
37285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_204_WIDTH },
37286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_205_CHECKER_TYPE,
37287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_205_WIDTH },
37288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_206_CHECKER_TYPE,
37289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_206_WIDTH },
37290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_207_CHECKER_TYPE,
37291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_207_WIDTH },
37292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_208_CHECKER_TYPE,
37293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_208_WIDTH },
37294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_209_CHECKER_TYPE,
37295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_209_WIDTH },
37296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_210_CHECKER_TYPE,
37297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_210_WIDTH },
37298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_211_CHECKER_TYPE,
37299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_211_WIDTH },
37300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_212_CHECKER_TYPE,
37301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_212_WIDTH },
37302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_213_CHECKER_TYPE,
37303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_213_WIDTH },
37304  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_214_CHECKER_TYPE,
37305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_214_WIDTH },
37306  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_215_CHECKER_TYPE,
37307  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_215_WIDTH },
37308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_216_CHECKER_TYPE,
37309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_216_WIDTH },
37310  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_217_CHECKER_TYPE,
37311  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_217_WIDTH },
37312  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_218_CHECKER_TYPE,
37313  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_218_WIDTH },
37314  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_219_CHECKER_TYPE,
37315  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_219_WIDTH },
37316  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_220_CHECKER_TYPE,
37317  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_220_WIDTH },
37318  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_221_CHECKER_TYPE,
37319  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_221_WIDTH },
37320  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_222_CHECKER_TYPE,
37321  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_222_WIDTH },
37322  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_223_CHECKER_TYPE,
37323  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_223_WIDTH },
37324  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_224_CHECKER_TYPE,
37325  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_224_WIDTH },
37326  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_225_CHECKER_TYPE,
37327  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_225_WIDTH },
37328  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_226_CHECKER_TYPE,
37329  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_226_WIDTH },
37330  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_227_CHECKER_TYPE,
37331  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_227_WIDTH },
37332  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_228_CHECKER_TYPE,
37333  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_228_WIDTH },
37334  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_229_CHECKER_TYPE,
37335  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_229_WIDTH },
37336  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_230_CHECKER_TYPE,
37337  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_230_WIDTH },
37338  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_231_CHECKER_TYPE,
37339  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_231_WIDTH },
37340  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_232_CHECKER_TYPE,
37341  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_232_WIDTH },
37342  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_233_CHECKER_TYPE,
37343  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_233_WIDTH },
37344  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_234_CHECKER_TYPE,
37345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_234_WIDTH },
37346  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_235_CHECKER_TYPE,
37347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_235_WIDTH },
37348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_236_CHECKER_TYPE,
37349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_236_WIDTH },
37350  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_237_CHECKER_TYPE,
37351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_237_WIDTH },
37352  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_238_CHECKER_TYPE,
37353  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_238_WIDTH },
37354  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_239_CHECKER_TYPE,
37355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_239_WIDTH },
37356  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_240_CHECKER_TYPE,
37357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_240_WIDTH },
37358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_241_CHECKER_TYPE,
37359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_241_WIDTH },
37360  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_242_CHECKER_TYPE,
37361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_242_WIDTH },
37362  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_243_CHECKER_TYPE,
37363  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_243_WIDTH },
37364  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_244_CHECKER_TYPE,
37365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_244_WIDTH },
37366  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_245_CHECKER_TYPE,
37367  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_245_WIDTH },
37368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_246_CHECKER_TYPE,
37369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_246_WIDTH },
37370  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_247_CHECKER_TYPE,
37371  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_247_WIDTH },
37372  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_248_CHECKER_TYPE,
37373  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_248_WIDTH },
37374  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_249_CHECKER_TYPE,
37375  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_249_WIDTH },
37376  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_250_CHECKER_TYPE,
37377  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_250_WIDTH },
37378  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_251_CHECKER_TYPE,
37379  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_251_WIDTH },
37380  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_252_CHECKER_TYPE,
37381  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_252_WIDTH },
37382  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_253_CHECKER_TYPE,
37383  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_253_WIDTH },
37384  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_254_CHECKER_TYPE,
37385  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_254_WIDTH },
37386  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_255_CHECKER_TYPE,
37387  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_GROUP_255_WIDTH },
37388 };
37389 
37395 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_MAX_NUM_CHECKERS] =
37396 {
37397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_0_CHECKER_TYPE,
37398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_0_WIDTH },
37399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_1_CHECKER_TYPE,
37400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_1_WIDTH },
37401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_2_CHECKER_TYPE,
37402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_2_WIDTH },
37403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_3_CHECKER_TYPE,
37404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_3_WIDTH },
37405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_4_CHECKER_TYPE,
37406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_4_WIDTH },
37407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_5_CHECKER_TYPE,
37408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_5_WIDTH },
37409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_6_CHECKER_TYPE,
37410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_6_WIDTH },
37411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_7_CHECKER_TYPE,
37412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_7_WIDTH },
37413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_8_CHECKER_TYPE,
37414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_8_WIDTH },
37415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_9_CHECKER_TYPE,
37416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_9_WIDTH },
37417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_10_CHECKER_TYPE,
37418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_10_WIDTH },
37419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_11_CHECKER_TYPE,
37420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_11_WIDTH },
37421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_12_CHECKER_TYPE,
37422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_12_WIDTH },
37423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_13_CHECKER_TYPE,
37424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_13_WIDTH },
37425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_14_CHECKER_TYPE,
37426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_14_WIDTH },
37427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_15_CHECKER_TYPE,
37428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_15_WIDTH },
37429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_16_CHECKER_TYPE,
37430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_16_WIDTH },
37431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_17_CHECKER_TYPE,
37432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_17_WIDTH },
37433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_18_CHECKER_TYPE,
37434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_18_WIDTH },
37435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_19_CHECKER_TYPE,
37436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_19_WIDTH },
37437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_20_CHECKER_TYPE,
37438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_20_WIDTH },
37439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_21_CHECKER_TYPE,
37440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_21_WIDTH },
37441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_22_CHECKER_TYPE,
37442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_22_WIDTH },
37443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_23_CHECKER_TYPE,
37444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_23_WIDTH },
37445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_24_CHECKER_TYPE,
37446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_24_WIDTH },
37447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_25_CHECKER_TYPE,
37448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_25_WIDTH },
37449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_26_CHECKER_TYPE,
37450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_26_WIDTH },
37451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_27_CHECKER_TYPE,
37452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_27_WIDTH },
37453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_28_CHECKER_TYPE,
37454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_28_WIDTH },
37455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_29_CHECKER_TYPE,
37456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_29_WIDTH },
37457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_30_CHECKER_TYPE,
37458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_30_WIDTH },
37459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_31_CHECKER_TYPE,
37460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_31_WIDTH },
37461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_32_CHECKER_TYPE,
37462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_32_WIDTH },
37463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_33_CHECKER_TYPE,
37464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_33_WIDTH },
37465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_34_CHECKER_TYPE,
37466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_34_WIDTH },
37467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_35_CHECKER_TYPE,
37468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_35_WIDTH },
37469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_36_CHECKER_TYPE,
37470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_36_WIDTH },
37471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_37_CHECKER_TYPE,
37472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_37_WIDTH },
37473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_38_CHECKER_TYPE,
37474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_38_WIDTH },
37475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_39_CHECKER_TYPE,
37476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_39_WIDTH },
37477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_40_CHECKER_TYPE,
37478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_40_WIDTH },
37479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_41_CHECKER_TYPE,
37480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_41_WIDTH },
37481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_42_CHECKER_TYPE,
37482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_42_WIDTH },
37483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_43_CHECKER_TYPE,
37484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_43_WIDTH },
37485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_44_CHECKER_TYPE,
37486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_44_WIDTH },
37487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_45_CHECKER_TYPE,
37488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_45_WIDTH },
37489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_46_CHECKER_TYPE,
37490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_46_WIDTH },
37491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_47_CHECKER_TYPE,
37492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_47_WIDTH },
37493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_48_CHECKER_TYPE,
37494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_48_WIDTH },
37495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_49_CHECKER_TYPE,
37496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_49_WIDTH },
37497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_50_CHECKER_TYPE,
37498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_50_WIDTH },
37499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_51_CHECKER_TYPE,
37500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_51_WIDTH },
37501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_52_CHECKER_TYPE,
37502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_52_WIDTH },
37503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_53_CHECKER_TYPE,
37504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_53_WIDTH },
37505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_54_CHECKER_TYPE,
37506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_54_WIDTH },
37507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_55_CHECKER_TYPE,
37508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_55_WIDTH },
37509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_56_CHECKER_TYPE,
37510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_56_WIDTH },
37511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_57_CHECKER_TYPE,
37512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_57_WIDTH },
37513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_58_CHECKER_TYPE,
37514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_58_WIDTH },
37515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_59_CHECKER_TYPE,
37516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_59_WIDTH },
37517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_60_CHECKER_TYPE,
37518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_60_WIDTH },
37519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_61_CHECKER_TYPE,
37520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_61_WIDTH },
37521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_62_CHECKER_TYPE,
37522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_62_WIDTH },
37523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_63_CHECKER_TYPE,
37524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_63_WIDTH },
37525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_64_CHECKER_TYPE,
37526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_64_WIDTH },
37527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_65_CHECKER_TYPE,
37528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_65_WIDTH },
37529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_66_CHECKER_TYPE,
37530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_66_WIDTH },
37531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_67_CHECKER_TYPE,
37532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_67_WIDTH },
37533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_68_CHECKER_TYPE,
37534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_68_WIDTH },
37535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_69_CHECKER_TYPE,
37536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_69_WIDTH },
37537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_70_CHECKER_TYPE,
37538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_70_WIDTH },
37539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_71_CHECKER_TYPE,
37540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_71_WIDTH },
37541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_72_CHECKER_TYPE,
37542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_72_WIDTH },
37543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_73_CHECKER_TYPE,
37544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_73_WIDTH },
37545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_74_CHECKER_TYPE,
37546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_74_WIDTH },
37547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_75_CHECKER_TYPE,
37548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_75_WIDTH },
37549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_76_CHECKER_TYPE,
37550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_76_WIDTH },
37551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_77_CHECKER_TYPE,
37552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_77_WIDTH },
37553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_78_CHECKER_TYPE,
37554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_78_WIDTH },
37555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_79_CHECKER_TYPE,
37556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_79_WIDTH },
37557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_80_CHECKER_TYPE,
37558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_80_WIDTH },
37559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_81_CHECKER_TYPE,
37560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_81_WIDTH },
37561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_82_CHECKER_TYPE,
37562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_82_WIDTH },
37563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_83_CHECKER_TYPE,
37564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_83_WIDTH },
37565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_84_CHECKER_TYPE,
37566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_84_WIDTH },
37567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_85_CHECKER_TYPE,
37568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_85_WIDTH },
37569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_86_CHECKER_TYPE,
37570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_86_WIDTH },
37571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_87_CHECKER_TYPE,
37572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_87_WIDTH },
37573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_88_CHECKER_TYPE,
37574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_88_WIDTH },
37575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_89_CHECKER_TYPE,
37576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_89_WIDTH },
37577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_90_CHECKER_TYPE,
37578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_90_WIDTH },
37579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_91_CHECKER_TYPE,
37580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_91_WIDTH },
37581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_92_CHECKER_TYPE,
37582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_92_WIDTH },
37583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_93_CHECKER_TYPE,
37584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_93_WIDTH },
37585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_94_CHECKER_TYPE,
37586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_94_WIDTH },
37587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_95_CHECKER_TYPE,
37588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_95_WIDTH },
37589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_96_CHECKER_TYPE,
37590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_96_WIDTH },
37591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_97_CHECKER_TYPE,
37592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_97_WIDTH },
37593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_98_CHECKER_TYPE,
37594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_98_WIDTH },
37595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_99_CHECKER_TYPE,
37596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_99_WIDTH },
37597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_100_CHECKER_TYPE,
37598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_100_WIDTH },
37599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_101_CHECKER_TYPE,
37600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_101_WIDTH },
37601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_102_CHECKER_TYPE,
37602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_102_WIDTH },
37603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_103_CHECKER_TYPE,
37604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_103_WIDTH },
37605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_104_CHECKER_TYPE,
37606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_104_WIDTH },
37607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_105_CHECKER_TYPE,
37608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_105_WIDTH },
37609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_106_CHECKER_TYPE,
37610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_106_WIDTH },
37611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_107_CHECKER_TYPE,
37612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_107_WIDTH },
37613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_108_CHECKER_TYPE,
37614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_108_WIDTH },
37615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_109_CHECKER_TYPE,
37616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_109_WIDTH },
37617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_110_CHECKER_TYPE,
37618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_110_WIDTH },
37619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_111_CHECKER_TYPE,
37620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_111_WIDTH },
37621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_112_CHECKER_TYPE,
37622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_112_WIDTH },
37623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_113_CHECKER_TYPE,
37624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_113_WIDTH },
37625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_114_CHECKER_TYPE,
37626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_114_WIDTH },
37627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_115_CHECKER_TYPE,
37628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_115_WIDTH },
37629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_116_CHECKER_TYPE,
37630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_116_WIDTH },
37631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_117_CHECKER_TYPE,
37632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_117_WIDTH },
37633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_118_CHECKER_TYPE,
37634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_118_WIDTH },
37635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_119_CHECKER_TYPE,
37636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_119_WIDTH },
37637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_120_CHECKER_TYPE,
37638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_120_WIDTH },
37639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_121_CHECKER_TYPE,
37640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_121_WIDTH },
37641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_122_CHECKER_TYPE,
37642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_122_WIDTH },
37643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_123_CHECKER_TYPE,
37644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_123_WIDTH },
37645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_124_CHECKER_TYPE,
37646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_124_WIDTH },
37647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_125_CHECKER_TYPE,
37648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_125_WIDTH },
37649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_126_CHECKER_TYPE,
37650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_126_WIDTH },
37651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_127_CHECKER_TYPE,
37652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_127_WIDTH },
37653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_128_CHECKER_TYPE,
37654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_128_WIDTH },
37655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_129_CHECKER_TYPE,
37656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_129_WIDTH },
37657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_130_CHECKER_TYPE,
37658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_130_WIDTH },
37659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_131_CHECKER_TYPE,
37660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_131_WIDTH },
37661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_132_CHECKER_TYPE,
37662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_132_WIDTH },
37663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_133_CHECKER_TYPE,
37664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_133_WIDTH },
37665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_134_CHECKER_TYPE,
37666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_134_WIDTH },
37667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_135_CHECKER_TYPE,
37668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_135_WIDTH },
37669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_136_CHECKER_TYPE,
37670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_136_WIDTH },
37671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_137_CHECKER_TYPE,
37672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_137_WIDTH },
37673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_138_CHECKER_TYPE,
37674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_138_WIDTH },
37675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_139_CHECKER_TYPE,
37676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_139_WIDTH },
37677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_140_CHECKER_TYPE,
37678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_140_WIDTH },
37679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_141_CHECKER_TYPE,
37680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_141_WIDTH },
37681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_142_CHECKER_TYPE,
37682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_142_WIDTH },
37683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_143_CHECKER_TYPE,
37684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_143_WIDTH },
37685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_144_CHECKER_TYPE,
37686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_144_WIDTH },
37687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_145_CHECKER_TYPE,
37688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_145_WIDTH },
37689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_146_CHECKER_TYPE,
37690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_146_WIDTH },
37691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_147_CHECKER_TYPE,
37692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_147_WIDTH },
37693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_148_CHECKER_TYPE,
37694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_148_WIDTH },
37695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_149_CHECKER_TYPE,
37696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_149_WIDTH },
37697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_150_CHECKER_TYPE,
37698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_150_WIDTH },
37699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_151_CHECKER_TYPE,
37700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_151_WIDTH },
37701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_152_CHECKER_TYPE,
37702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_152_WIDTH },
37703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_153_CHECKER_TYPE,
37704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_153_WIDTH },
37705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_154_CHECKER_TYPE,
37706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_154_WIDTH },
37707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_155_CHECKER_TYPE,
37708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_155_WIDTH },
37709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_156_CHECKER_TYPE,
37710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_156_WIDTH },
37711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_157_CHECKER_TYPE,
37712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_157_WIDTH },
37713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_158_CHECKER_TYPE,
37714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_158_WIDTH },
37715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_159_CHECKER_TYPE,
37716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_159_WIDTH },
37717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_160_CHECKER_TYPE,
37718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_160_WIDTH },
37719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_161_CHECKER_TYPE,
37720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_161_WIDTH },
37721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_162_CHECKER_TYPE,
37722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_162_WIDTH },
37723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_163_CHECKER_TYPE,
37724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_163_WIDTH },
37725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_164_CHECKER_TYPE,
37726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_164_WIDTH },
37727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_165_CHECKER_TYPE,
37728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_165_WIDTH },
37729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_166_CHECKER_TYPE,
37730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_166_WIDTH },
37731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_167_CHECKER_TYPE,
37732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_167_WIDTH },
37733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_168_CHECKER_TYPE,
37734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_168_WIDTH },
37735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_169_CHECKER_TYPE,
37736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_169_WIDTH },
37737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_170_CHECKER_TYPE,
37738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_170_WIDTH },
37739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_171_CHECKER_TYPE,
37740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_171_WIDTH },
37741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_172_CHECKER_TYPE,
37742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_172_WIDTH },
37743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_173_CHECKER_TYPE,
37744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_173_WIDTH },
37745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_174_CHECKER_TYPE,
37746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_174_WIDTH },
37747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_175_CHECKER_TYPE,
37748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_175_WIDTH },
37749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_176_CHECKER_TYPE,
37750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_176_WIDTH },
37751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_177_CHECKER_TYPE,
37752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_177_WIDTH },
37753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_178_CHECKER_TYPE,
37754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_178_WIDTH },
37755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_179_CHECKER_TYPE,
37756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_179_WIDTH },
37757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_180_CHECKER_TYPE,
37758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_180_WIDTH },
37759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_181_CHECKER_TYPE,
37760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_181_WIDTH },
37761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_182_CHECKER_TYPE,
37762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_182_WIDTH },
37763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_183_CHECKER_TYPE,
37764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_183_WIDTH },
37765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_184_CHECKER_TYPE,
37766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_184_WIDTH },
37767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_185_CHECKER_TYPE,
37768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_185_WIDTH },
37769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_186_CHECKER_TYPE,
37770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_186_WIDTH },
37771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_187_CHECKER_TYPE,
37772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_187_WIDTH },
37773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_188_CHECKER_TYPE,
37774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_188_WIDTH },
37775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_189_CHECKER_TYPE,
37776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_189_WIDTH },
37777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_190_CHECKER_TYPE,
37778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_190_WIDTH },
37779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_191_CHECKER_TYPE,
37780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_191_WIDTH },
37781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_192_CHECKER_TYPE,
37782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_192_WIDTH },
37783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_193_CHECKER_TYPE,
37784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_193_WIDTH },
37785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_194_CHECKER_TYPE,
37786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_194_WIDTH },
37787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_195_CHECKER_TYPE,
37788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_195_WIDTH },
37789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_196_CHECKER_TYPE,
37790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_196_WIDTH },
37791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_197_CHECKER_TYPE,
37792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_197_WIDTH },
37793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_198_CHECKER_TYPE,
37794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_198_WIDTH },
37795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_199_CHECKER_TYPE,
37796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_199_WIDTH },
37797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_200_CHECKER_TYPE,
37798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_200_WIDTH },
37799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_201_CHECKER_TYPE,
37800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_201_WIDTH },
37801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_202_CHECKER_TYPE,
37802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_202_WIDTH },
37803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_203_CHECKER_TYPE,
37804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_203_WIDTH },
37805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_204_CHECKER_TYPE,
37806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_204_WIDTH },
37807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_205_CHECKER_TYPE,
37808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_205_WIDTH },
37809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_206_CHECKER_TYPE,
37810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_206_WIDTH },
37811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_207_CHECKER_TYPE,
37812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_207_WIDTH },
37813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_208_CHECKER_TYPE,
37814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_208_WIDTH },
37815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_209_CHECKER_TYPE,
37816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_209_WIDTH },
37817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_210_CHECKER_TYPE,
37818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_210_WIDTH },
37819  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_211_CHECKER_TYPE,
37820  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_211_WIDTH },
37821  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_212_CHECKER_TYPE,
37822  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_212_WIDTH },
37823  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_213_CHECKER_TYPE,
37824  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_213_WIDTH },
37825  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_214_CHECKER_TYPE,
37826  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_214_WIDTH },
37827  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_215_CHECKER_TYPE,
37828  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_215_WIDTH },
37829  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_216_CHECKER_TYPE,
37830  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_216_WIDTH },
37831  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_217_CHECKER_TYPE,
37832  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_217_WIDTH },
37833  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_218_CHECKER_TYPE,
37834  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_218_WIDTH },
37835  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_219_CHECKER_TYPE,
37836  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_219_WIDTH },
37837  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_220_CHECKER_TYPE,
37838  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_220_WIDTH },
37839  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_221_CHECKER_TYPE,
37840  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_221_WIDTH },
37841  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_222_CHECKER_TYPE,
37842  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_222_WIDTH },
37843  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_223_CHECKER_TYPE,
37844  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_223_WIDTH },
37845  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_224_CHECKER_TYPE,
37846  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_224_WIDTH },
37847  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_225_CHECKER_TYPE,
37848  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_225_WIDTH },
37849  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_226_CHECKER_TYPE,
37850  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_226_WIDTH },
37851  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_227_CHECKER_TYPE,
37852  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_227_WIDTH },
37853  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_228_CHECKER_TYPE,
37854  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_228_WIDTH },
37855  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_229_CHECKER_TYPE,
37856  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_229_WIDTH },
37857  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_230_CHECKER_TYPE,
37858  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_230_WIDTH },
37859  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_231_CHECKER_TYPE,
37860  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_231_WIDTH },
37861  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_232_CHECKER_TYPE,
37862  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_232_WIDTH },
37863  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_233_CHECKER_TYPE,
37864  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_233_WIDTH },
37865  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_234_CHECKER_TYPE,
37866  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_234_WIDTH },
37867  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_235_CHECKER_TYPE,
37868  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_235_WIDTH },
37869  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_236_CHECKER_TYPE,
37870  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_236_WIDTH },
37871  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_237_CHECKER_TYPE,
37872  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_237_WIDTH },
37873  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_238_CHECKER_TYPE,
37874  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_238_WIDTH },
37875  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_239_CHECKER_TYPE,
37876  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_239_WIDTH },
37877  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_240_CHECKER_TYPE,
37878  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_240_WIDTH },
37879  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_241_CHECKER_TYPE,
37880  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_241_WIDTH },
37881  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_242_CHECKER_TYPE,
37882  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_242_WIDTH },
37883  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_243_CHECKER_TYPE,
37884  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_243_WIDTH },
37885  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_244_CHECKER_TYPE,
37886  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_244_WIDTH },
37887  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_245_CHECKER_TYPE,
37888  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_245_WIDTH },
37889  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_246_CHECKER_TYPE,
37890  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_246_WIDTH },
37891  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_247_CHECKER_TYPE,
37892  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_247_WIDTH },
37893  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_248_CHECKER_TYPE,
37894  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_248_WIDTH },
37895  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_249_CHECKER_TYPE,
37896  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_249_WIDTH },
37897  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_250_CHECKER_TYPE,
37898  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_250_WIDTH },
37899  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_251_CHECKER_TYPE,
37900  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_251_WIDTH },
37901  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_252_CHECKER_TYPE,
37902  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_252_WIDTH },
37903  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_253_CHECKER_TYPE,
37904  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_253_WIDTH },
37905  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_254_CHECKER_TYPE,
37906  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_254_WIDTH },
37907  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_255_CHECKER_TYPE,
37908  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_GROUP_255_WIDTH },
37909 };
37910 
37916 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_MAX_NUM_CHECKERS] =
37917 {
37918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_0_CHECKER_TYPE,
37919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_0_WIDTH },
37920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_1_CHECKER_TYPE,
37921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_1_WIDTH },
37922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_2_CHECKER_TYPE,
37923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_2_WIDTH },
37924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_3_CHECKER_TYPE,
37925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_3_WIDTH },
37926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_4_CHECKER_TYPE,
37927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_4_WIDTH },
37928  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_5_CHECKER_TYPE,
37929  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_5_WIDTH },
37930  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_6_CHECKER_TYPE,
37931  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_6_WIDTH },
37932  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_7_CHECKER_TYPE,
37933  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_7_WIDTH },
37934  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_8_CHECKER_TYPE,
37935  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_8_WIDTH },
37936  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_9_CHECKER_TYPE,
37937  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_9_WIDTH },
37938  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_10_CHECKER_TYPE,
37939  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_10_WIDTH },
37940  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_11_CHECKER_TYPE,
37941  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_11_WIDTH },
37942  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_12_CHECKER_TYPE,
37943  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_12_WIDTH },
37944  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_13_CHECKER_TYPE,
37945  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_13_WIDTH },
37946  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_14_CHECKER_TYPE,
37947  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_14_WIDTH },
37948  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_15_CHECKER_TYPE,
37949  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_15_WIDTH },
37950  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_16_CHECKER_TYPE,
37951  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_16_WIDTH },
37952  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_17_CHECKER_TYPE,
37953  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_17_WIDTH },
37954  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_18_CHECKER_TYPE,
37955  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_18_WIDTH },
37956  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_19_CHECKER_TYPE,
37957  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_19_WIDTH },
37958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_20_CHECKER_TYPE,
37959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_20_WIDTH },
37960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_21_CHECKER_TYPE,
37961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_21_WIDTH },
37962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_22_CHECKER_TYPE,
37963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_22_WIDTH },
37964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_23_CHECKER_TYPE,
37965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_23_WIDTH },
37966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_24_CHECKER_TYPE,
37967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_24_WIDTH },
37968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_25_CHECKER_TYPE,
37969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_25_WIDTH },
37970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_26_CHECKER_TYPE,
37971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_26_WIDTH },
37972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_27_CHECKER_TYPE,
37973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_27_WIDTH },
37974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_28_CHECKER_TYPE,
37975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_28_WIDTH },
37976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_29_CHECKER_TYPE,
37977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_29_WIDTH },
37978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_30_CHECKER_TYPE,
37979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_30_WIDTH },
37980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_31_CHECKER_TYPE,
37981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_31_WIDTH },
37982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_32_CHECKER_TYPE,
37983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_32_WIDTH },
37984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_33_CHECKER_TYPE,
37985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_33_WIDTH },
37986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_34_CHECKER_TYPE,
37987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_34_WIDTH },
37988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_35_CHECKER_TYPE,
37989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_35_WIDTH },
37990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_36_CHECKER_TYPE,
37991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_36_WIDTH },
37992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_37_CHECKER_TYPE,
37993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_37_WIDTH },
37994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_38_CHECKER_TYPE,
37995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_38_WIDTH },
37996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_39_CHECKER_TYPE,
37997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_39_WIDTH },
37998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_40_CHECKER_TYPE,
37999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_40_WIDTH },
38000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_41_CHECKER_TYPE,
38001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_41_WIDTH },
38002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_42_CHECKER_TYPE,
38003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_42_WIDTH },
38004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_43_CHECKER_TYPE,
38005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_43_WIDTH },
38006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_44_CHECKER_TYPE,
38007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_44_WIDTH },
38008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_45_CHECKER_TYPE,
38009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_45_WIDTH },
38010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_46_CHECKER_TYPE,
38011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_46_WIDTH },
38012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_47_CHECKER_TYPE,
38013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_47_WIDTH },
38014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_48_CHECKER_TYPE,
38015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_48_WIDTH },
38016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_49_CHECKER_TYPE,
38017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_49_WIDTH },
38018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_50_CHECKER_TYPE,
38019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_50_WIDTH },
38020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_51_CHECKER_TYPE,
38021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_51_WIDTH },
38022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_52_CHECKER_TYPE,
38023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_52_WIDTH },
38024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_53_CHECKER_TYPE,
38025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_53_WIDTH },
38026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_54_CHECKER_TYPE,
38027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_54_WIDTH },
38028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_55_CHECKER_TYPE,
38029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_55_WIDTH },
38030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_56_CHECKER_TYPE,
38031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_56_WIDTH },
38032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_57_CHECKER_TYPE,
38033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_57_WIDTH },
38034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_58_CHECKER_TYPE,
38035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_58_WIDTH },
38036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_59_CHECKER_TYPE,
38037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_59_WIDTH },
38038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_60_CHECKER_TYPE,
38039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_60_WIDTH },
38040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_61_CHECKER_TYPE,
38041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_61_WIDTH },
38042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_62_CHECKER_TYPE,
38043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_62_WIDTH },
38044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_63_CHECKER_TYPE,
38045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_63_WIDTH },
38046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_64_CHECKER_TYPE,
38047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_64_WIDTH },
38048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_65_CHECKER_TYPE,
38049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_65_WIDTH },
38050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_66_CHECKER_TYPE,
38051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_66_WIDTH },
38052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_67_CHECKER_TYPE,
38053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_67_WIDTH },
38054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_68_CHECKER_TYPE,
38055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_68_WIDTH },
38056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_69_CHECKER_TYPE,
38057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_69_WIDTH },
38058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_70_CHECKER_TYPE,
38059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_70_WIDTH },
38060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_71_CHECKER_TYPE,
38061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_71_WIDTH },
38062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_72_CHECKER_TYPE,
38063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_72_WIDTH },
38064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_73_CHECKER_TYPE,
38065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_73_WIDTH },
38066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_74_CHECKER_TYPE,
38067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_74_WIDTH },
38068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_75_CHECKER_TYPE,
38069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_75_WIDTH },
38070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_76_CHECKER_TYPE,
38071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_76_WIDTH },
38072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_77_CHECKER_TYPE,
38073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_77_WIDTH },
38074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_78_CHECKER_TYPE,
38075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_78_WIDTH },
38076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_79_CHECKER_TYPE,
38077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_79_WIDTH },
38078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_80_CHECKER_TYPE,
38079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_80_WIDTH },
38080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_81_CHECKER_TYPE,
38081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_81_WIDTH },
38082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_82_CHECKER_TYPE,
38083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_82_WIDTH },
38084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_83_CHECKER_TYPE,
38085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_83_WIDTH },
38086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_84_CHECKER_TYPE,
38087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_84_WIDTH },
38088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_85_CHECKER_TYPE,
38089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_85_WIDTH },
38090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_86_CHECKER_TYPE,
38091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_86_WIDTH },
38092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_87_CHECKER_TYPE,
38093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_87_WIDTH },
38094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_88_CHECKER_TYPE,
38095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_88_WIDTH },
38096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_89_CHECKER_TYPE,
38097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_89_WIDTH },
38098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_90_CHECKER_TYPE,
38099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_90_WIDTH },
38100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_91_CHECKER_TYPE,
38101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_91_WIDTH },
38102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_92_CHECKER_TYPE,
38103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_92_WIDTH },
38104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_93_CHECKER_TYPE,
38105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_93_WIDTH },
38106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_94_CHECKER_TYPE,
38107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_94_WIDTH },
38108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_95_CHECKER_TYPE,
38109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_95_WIDTH },
38110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_96_CHECKER_TYPE,
38111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_96_WIDTH },
38112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_97_CHECKER_TYPE,
38113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_97_WIDTH },
38114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_98_CHECKER_TYPE,
38115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_98_WIDTH },
38116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_99_CHECKER_TYPE,
38117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_99_WIDTH },
38118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_100_CHECKER_TYPE,
38119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_100_WIDTH },
38120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_101_CHECKER_TYPE,
38121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_101_WIDTH },
38122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_102_CHECKER_TYPE,
38123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_102_WIDTH },
38124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_103_CHECKER_TYPE,
38125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_103_WIDTH },
38126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_104_CHECKER_TYPE,
38127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_104_WIDTH },
38128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_105_CHECKER_TYPE,
38129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_105_WIDTH },
38130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_106_CHECKER_TYPE,
38131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_106_WIDTH },
38132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_107_CHECKER_TYPE,
38133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_107_WIDTH },
38134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_108_CHECKER_TYPE,
38135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_108_WIDTH },
38136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_109_CHECKER_TYPE,
38137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_109_WIDTH },
38138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_110_CHECKER_TYPE,
38139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_110_WIDTH },
38140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_111_CHECKER_TYPE,
38141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_111_WIDTH },
38142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_112_CHECKER_TYPE,
38143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_112_WIDTH },
38144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_113_CHECKER_TYPE,
38145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_113_WIDTH },
38146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_114_CHECKER_TYPE,
38147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_114_WIDTH },
38148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_115_CHECKER_TYPE,
38149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_115_WIDTH },
38150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_116_CHECKER_TYPE,
38151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_116_WIDTH },
38152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_117_CHECKER_TYPE,
38153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_117_WIDTH },
38154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_118_CHECKER_TYPE,
38155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_118_WIDTH },
38156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_119_CHECKER_TYPE,
38157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_119_WIDTH },
38158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_120_CHECKER_TYPE,
38159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_120_WIDTH },
38160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_121_CHECKER_TYPE,
38161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_121_WIDTH },
38162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_122_CHECKER_TYPE,
38163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_122_WIDTH },
38164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_123_CHECKER_TYPE,
38165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_123_WIDTH },
38166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_124_CHECKER_TYPE,
38167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_124_WIDTH },
38168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_125_CHECKER_TYPE,
38169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_125_WIDTH },
38170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_126_CHECKER_TYPE,
38171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_126_WIDTH },
38172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_127_CHECKER_TYPE,
38173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_127_WIDTH },
38174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_128_CHECKER_TYPE,
38175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_128_WIDTH },
38176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_129_CHECKER_TYPE,
38177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_129_WIDTH },
38178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_130_CHECKER_TYPE,
38179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_130_WIDTH },
38180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_131_CHECKER_TYPE,
38181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_131_WIDTH },
38182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_132_CHECKER_TYPE,
38183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_132_WIDTH },
38184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_133_CHECKER_TYPE,
38185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_133_WIDTH },
38186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_134_CHECKER_TYPE,
38187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_134_WIDTH },
38188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_135_CHECKER_TYPE,
38189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_135_WIDTH },
38190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_136_CHECKER_TYPE,
38191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_136_WIDTH },
38192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_137_CHECKER_TYPE,
38193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_137_WIDTH },
38194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_138_CHECKER_TYPE,
38195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_138_WIDTH },
38196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_139_CHECKER_TYPE,
38197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_139_WIDTH },
38198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_140_CHECKER_TYPE,
38199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_140_WIDTH },
38200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_141_CHECKER_TYPE,
38201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_141_WIDTH },
38202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_142_CHECKER_TYPE,
38203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_142_WIDTH },
38204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_143_CHECKER_TYPE,
38205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_143_WIDTH },
38206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_144_CHECKER_TYPE,
38207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_144_WIDTH },
38208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_145_CHECKER_TYPE,
38209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_145_WIDTH },
38210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_146_CHECKER_TYPE,
38211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_146_WIDTH },
38212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_147_CHECKER_TYPE,
38213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_147_WIDTH },
38214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_148_CHECKER_TYPE,
38215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_148_WIDTH },
38216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_149_CHECKER_TYPE,
38217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_149_WIDTH },
38218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_150_CHECKER_TYPE,
38219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_150_WIDTH },
38220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_151_CHECKER_TYPE,
38221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_151_WIDTH },
38222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_152_CHECKER_TYPE,
38223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_152_WIDTH },
38224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_153_CHECKER_TYPE,
38225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_153_WIDTH },
38226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_154_CHECKER_TYPE,
38227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_154_WIDTH },
38228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_155_CHECKER_TYPE,
38229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_155_WIDTH },
38230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_156_CHECKER_TYPE,
38231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_156_WIDTH },
38232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_157_CHECKER_TYPE,
38233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_157_WIDTH },
38234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_158_CHECKER_TYPE,
38235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_158_WIDTH },
38236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_159_CHECKER_TYPE,
38237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_159_WIDTH },
38238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_160_CHECKER_TYPE,
38239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_160_WIDTH },
38240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_161_CHECKER_TYPE,
38241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_161_WIDTH },
38242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_162_CHECKER_TYPE,
38243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_162_WIDTH },
38244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_163_CHECKER_TYPE,
38245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_163_WIDTH },
38246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_164_CHECKER_TYPE,
38247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_164_WIDTH },
38248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_165_CHECKER_TYPE,
38249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_165_WIDTH },
38250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_166_CHECKER_TYPE,
38251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_166_WIDTH },
38252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_167_CHECKER_TYPE,
38253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_167_WIDTH },
38254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_168_CHECKER_TYPE,
38255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_168_WIDTH },
38256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_169_CHECKER_TYPE,
38257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_169_WIDTH },
38258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_170_CHECKER_TYPE,
38259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_170_WIDTH },
38260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_171_CHECKER_TYPE,
38261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_171_WIDTH },
38262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_172_CHECKER_TYPE,
38263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_172_WIDTH },
38264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_173_CHECKER_TYPE,
38265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_173_WIDTH },
38266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_174_CHECKER_TYPE,
38267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_174_WIDTH },
38268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_175_CHECKER_TYPE,
38269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_175_WIDTH },
38270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_176_CHECKER_TYPE,
38271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_176_WIDTH },
38272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_177_CHECKER_TYPE,
38273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_177_WIDTH },
38274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_178_CHECKER_TYPE,
38275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_178_WIDTH },
38276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_179_CHECKER_TYPE,
38277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_179_WIDTH },
38278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_180_CHECKER_TYPE,
38279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_180_WIDTH },
38280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_181_CHECKER_TYPE,
38281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_181_WIDTH },
38282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_182_CHECKER_TYPE,
38283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_182_WIDTH },
38284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_183_CHECKER_TYPE,
38285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_183_WIDTH },
38286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_184_CHECKER_TYPE,
38287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_184_WIDTH },
38288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_185_CHECKER_TYPE,
38289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_185_WIDTH },
38290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_186_CHECKER_TYPE,
38291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_186_WIDTH },
38292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_187_CHECKER_TYPE,
38293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_187_WIDTH },
38294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_188_CHECKER_TYPE,
38295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_188_WIDTH },
38296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_189_CHECKER_TYPE,
38297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_189_WIDTH },
38298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_190_CHECKER_TYPE,
38299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_190_WIDTH },
38300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_191_CHECKER_TYPE,
38301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_191_WIDTH },
38302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_192_CHECKER_TYPE,
38303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_192_WIDTH },
38304  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_193_CHECKER_TYPE,
38305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_193_WIDTH },
38306  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_194_CHECKER_TYPE,
38307  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_194_WIDTH },
38308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_195_CHECKER_TYPE,
38309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_195_WIDTH },
38310  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_196_CHECKER_TYPE,
38311  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_196_WIDTH },
38312  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_197_CHECKER_TYPE,
38313  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_197_WIDTH },
38314  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_198_CHECKER_TYPE,
38315  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_198_WIDTH },
38316  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_199_CHECKER_TYPE,
38317  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_199_WIDTH },
38318  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_200_CHECKER_TYPE,
38319  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_200_WIDTH },
38320  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_201_CHECKER_TYPE,
38321  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_201_WIDTH },
38322  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_202_CHECKER_TYPE,
38323  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_202_WIDTH },
38324  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_203_CHECKER_TYPE,
38325  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_203_WIDTH },
38326  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_204_CHECKER_TYPE,
38327  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_204_WIDTH },
38328  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_205_CHECKER_TYPE,
38329  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_205_WIDTH },
38330  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_206_CHECKER_TYPE,
38331  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_206_WIDTH },
38332  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_207_CHECKER_TYPE,
38333  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_207_WIDTH },
38334  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_208_CHECKER_TYPE,
38335  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_208_WIDTH },
38336  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_209_CHECKER_TYPE,
38337  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_209_WIDTH },
38338  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_210_CHECKER_TYPE,
38339  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_210_WIDTH },
38340  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_211_CHECKER_TYPE,
38341  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_211_WIDTH },
38342  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_212_CHECKER_TYPE,
38343  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_212_WIDTH },
38344  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_213_CHECKER_TYPE,
38345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_213_WIDTH },
38346  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_214_CHECKER_TYPE,
38347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_214_WIDTH },
38348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_215_CHECKER_TYPE,
38349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_215_WIDTH },
38350  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_216_CHECKER_TYPE,
38351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_216_WIDTH },
38352  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_217_CHECKER_TYPE,
38353  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_217_WIDTH },
38354  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_218_CHECKER_TYPE,
38355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_218_WIDTH },
38356  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_219_CHECKER_TYPE,
38357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_219_WIDTH },
38358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_220_CHECKER_TYPE,
38359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_220_WIDTH },
38360  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_221_CHECKER_TYPE,
38361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_221_WIDTH },
38362  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_222_CHECKER_TYPE,
38363  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_222_WIDTH },
38364  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_223_CHECKER_TYPE,
38365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_223_WIDTH },
38366  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_224_CHECKER_TYPE,
38367  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_224_WIDTH },
38368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_225_CHECKER_TYPE,
38369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_225_WIDTH },
38370  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_226_CHECKER_TYPE,
38371  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_226_WIDTH },
38372  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_227_CHECKER_TYPE,
38373  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_227_WIDTH },
38374  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_228_CHECKER_TYPE,
38375  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_228_WIDTH },
38376  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_229_CHECKER_TYPE,
38377  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_229_WIDTH },
38378  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_230_CHECKER_TYPE,
38379  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_230_WIDTH },
38380  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_231_CHECKER_TYPE,
38381  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_231_WIDTH },
38382  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_232_CHECKER_TYPE,
38383  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_232_WIDTH },
38384  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_233_CHECKER_TYPE,
38385  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_233_WIDTH },
38386  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_234_CHECKER_TYPE,
38387  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_234_WIDTH },
38388  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_235_CHECKER_TYPE,
38389  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_235_WIDTH },
38390  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_236_CHECKER_TYPE,
38391  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_236_WIDTH },
38392  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_237_CHECKER_TYPE,
38393  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_237_WIDTH },
38394  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_238_CHECKER_TYPE,
38395  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_238_WIDTH },
38396  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_239_CHECKER_TYPE,
38397  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_239_WIDTH },
38398  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_240_CHECKER_TYPE,
38399  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_240_WIDTH },
38400  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_241_CHECKER_TYPE,
38401  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_241_WIDTH },
38402  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_242_CHECKER_TYPE,
38403  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_242_WIDTH },
38404  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_243_CHECKER_TYPE,
38405  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_243_WIDTH },
38406  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_244_CHECKER_TYPE,
38407  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_244_WIDTH },
38408  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_245_CHECKER_TYPE,
38409  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_245_WIDTH },
38410  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_246_CHECKER_TYPE,
38411  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_246_WIDTH },
38412  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_247_CHECKER_TYPE,
38413  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_247_WIDTH },
38414  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_248_CHECKER_TYPE,
38415  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_248_WIDTH },
38416  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_249_CHECKER_TYPE,
38417  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_249_WIDTH },
38418  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_250_CHECKER_TYPE,
38419  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_250_WIDTH },
38420  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_251_CHECKER_TYPE,
38421  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_251_WIDTH },
38422  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_252_CHECKER_TYPE,
38423  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_252_WIDTH },
38424  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_253_CHECKER_TYPE,
38425  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_253_WIDTH },
38426  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_254_CHECKER_TYPE,
38427  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_254_WIDTH },
38428  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_255_CHECKER_TYPE,
38429  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_GROUP_255_WIDTH },
38430 };
38431 
38437 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_MAX_NUM_CHECKERS] =
38438 {
38439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_0_CHECKER_TYPE,
38440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_0_WIDTH },
38441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_1_CHECKER_TYPE,
38442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_1_WIDTH },
38443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_2_CHECKER_TYPE,
38444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_2_WIDTH },
38445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_3_CHECKER_TYPE,
38446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_3_WIDTH },
38447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_4_CHECKER_TYPE,
38448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_4_WIDTH },
38449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_5_CHECKER_TYPE,
38450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_5_WIDTH },
38451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_6_CHECKER_TYPE,
38452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_6_WIDTH },
38453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_7_CHECKER_TYPE,
38454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_7_WIDTH },
38455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_8_CHECKER_TYPE,
38456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_8_WIDTH },
38457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_9_CHECKER_TYPE,
38458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_9_WIDTH },
38459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_10_CHECKER_TYPE,
38460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_10_WIDTH },
38461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_11_CHECKER_TYPE,
38462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_11_WIDTH },
38463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_12_CHECKER_TYPE,
38464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_12_WIDTH },
38465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_13_CHECKER_TYPE,
38466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_13_WIDTH },
38467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_14_CHECKER_TYPE,
38468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_14_WIDTH },
38469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_15_CHECKER_TYPE,
38470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_15_WIDTH },
38471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_16_CHECKER_TYPE,
38472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_16_WIDTH },
38473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_17_CHECKER_TYPE,
38474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_17_WIDTH },
38475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_18_CHECKER_TYPE,
38476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_18_WIDTH },
38477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_19_CHECKER_TYPE,
38478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_19_WIDTH },
38479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_20_CHECKER_TYPE,
38480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_20_WIDTH },
38481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_21_CHECKER_TYPE,
38482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_21_WIDTH },
38483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_22_CHECKER_TYPE,
38484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_22_WIDTH },
38485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_23_CHECKER_TYPE,
38486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_23_WIDTH },
38487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_24_CHECKER_TYPE,
38488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_24_WIDTH },
38489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_25_CHECKER_TYPE,
38490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_25_WIDTH },
38491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_26_CHECKER_TYPE,
38492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_26_WIDTH },
38493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_27_CHECKER_TYPE,
38494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_27_WIDTH },
38495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_28_CHECKER_TYPE,
38496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_28_WIDTH },
38497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_29_CHECKER_TYPE,
38498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_29_WIDTH },
38499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_30_CHECKER_TYPE,
38500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_30_WIDTH },
38501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_31_CHECKER_TYPE,
38502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_31_WIDTH },
38503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_32_CHECKER_TYPE,
38504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_32_WIDTH },
38505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_33_CHECKER_TYPE,
38506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_33_WIDTH },
38507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_34_CHECKER_TYPE,
38508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_34_WIDTH },
38509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_35_CHECKER_TYPE,
38510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_35_WIDTH },
38511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_36_CHECKER_TYPE,
38512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_36_WIDTH },
38513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_37_CHECKER_TYPE,
38514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_37_WIDTH },
38515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_38_CHECKER_TYPE,
38516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_38_WIDTH },
38517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_39_CHECKER_TYPE,
38518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_39_WIDTH },
38519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_40_CHECKER_TYPE,
38520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_40_WIDTH },
38521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_41_CHECKER_TYPE,
38522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_41_WIDTH },
38523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_42_CHECKER_TYPE,
38524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_42_WIDTH },
38525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_43_CHECKER_TYPE,
38526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_43_WIDTH },
38527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_44_CHECKER_TYPE,
38528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_44_WIDTH },
38529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_45_CHECKER_TYPE,
38530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_45_WIDTH },
38531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_46_CHECKER_TYPE,
38532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_46_WIDTH },
38533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_47_CHECKER_TYPE,
38534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_47_WIDTH },
38535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_48_CHECKER_TYPE,
38536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_48_WIDTH },
38537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_49_CHECKER_TYPE,
38538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_49_WIDTH },
38539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_50_CHECKER_TYPE,
38540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_50_WIDTH },
38541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_51_CHECKER_TYPE,
38542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_51_WIDTH },
38543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_52_CHECKER_TYPE,
38544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_52_WIDTH },
38545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_53_CHECKER_TYPE,
38546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_53_WIDTH },
38547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_54_CHECKER_TYPE,
38548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_54_WIDTH },
38549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_55_CHECKER_TYPE,
38550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_55_WIDTH },
38551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_56_CHECKER_TYPE,
38552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_56_WIDTH },
38553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_57_CHECKER_TYPE,
38554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_57_WIDTH },
38555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_58_CHECKER_TYPE,
38556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_58_WIDTH },
38557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_59_CHECKER_TYPE,
38558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_59_WIDTH },
38559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_60_CHECKER_TYPE,
38560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_60_WIDTH },
38561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_61_CHECKER_TYPE,
38562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_61_WIDTH },
38563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_62_CHECKER_TYPE,
38564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_62_WIDTH },
38565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_63_CHECKER_TYPE,
38566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_63_WIDTH },
38567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_64_CHECKER_TYPE,
38568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_64_WIDTH },
38569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_65_CHECKER_TYPE,
38570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_65_WIDTH },
38571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_66_CHECKER_TYPE,
38572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_66_WIDTH },
38573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_67_CHECKER_TYPE,
38574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_67_WIDTH },
38575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_68_CHECKER_TYPE,
38576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_68_WIDTH },
38577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_69_CHECKER_TYPE,
38578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_69_WIDTH },
38579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_70_CHECKER_TYPE,
38580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_70_WIDTH },
38581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_71_CHECKER_TYPE,
38582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_71_WIDTH },
38583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_72_CHECKER_TYPE,
38584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_72_WIDTH },
38585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_73_CHECKER_TYPE,
38586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_73_WIDTH },
38587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_74_CHECKER_TYPE,
38588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_74_WIDTH },
38589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_75_CHECKER_TYPE,
38590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_75_WIDTH },
38591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_76_CHECKER_TYPE,
38592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_76_WIDTH },
38593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_77_CHECKER_TYPE,
38594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_77_WIDTH },
38595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_78_CHECKER_TYPE,
38596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_78_WIDTH },
38597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_79_CHECKER_TYPE,
38598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_79_WIDTH },
38599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_80_CHECKER_TYPE,
38600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_80_WIDTH },
38601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_81_CHECKER_TYPE,
38602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_81_WIDTH },
38603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_82_CHECKER_TYPE,
38604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_82_WIDTH },
38605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_83_CHECKER_TYPE,
38606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_83_WIDTH },
38607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_84_CHECKER_TYPE,
38608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_84_WIDTH },
38609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_85_CHECKER_TYPE,
38610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_85_WIDTH },
38611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_86_CHECKER_TYPE,
38612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_86_WIDTH },
38613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_87_CHECKER_TYPE,
38614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_87_WIDTH },
38615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_88_CHECKER_TYPE,
38616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_88_WIDTH },
38617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_89_CHECKER_TYPE,
38618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_89_WIDTH },
38619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_90_CHECKER_TYPE,
38620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_90_WIDTH },
38621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_91_CHECKER_TYPE,
38622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_91_WIDTH },
38623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_92_CHECKER_TYPE,
38624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_92_WIDTH },
38625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_93_CHECKER_TYPE,
38626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_93_WIDTH },
38627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_94_CHECKER_TYPE,
38628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_94_WIDTH },
38629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_95_CHECKER_TYPE,
38630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_95_WIDTH },
38631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_96_CHECKER_TYPE,
38632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_96_WIDTH },
38633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_97_CHECKER_TYPE,
38634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_97_WIDTH },
38635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_98_CHECKER_TYPE,
38636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_98_WIDTH },
38637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_99_CHECKER_TYPE,
38638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_99_WIDTH },
38639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_100_CHECKER_TYPE,
38640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_100_WIDTH },
38641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_101_CHECKER_TYPE,
38642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_101_WIDTH },
38643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_102_CHECKER_TYPE,
38644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_102_WIDTH },
38645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_103_CHECKER_TYPE,
38646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_103_WIDTH },
38647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_104_CHECKER_TYPE,
38648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_104_WIDTH },
38649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_105_CHECKER_TYPE,
38650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_105_WIDTH },
38651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_106_CHECKER_TYPE,
38652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_106_WIDTH },
38653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_107_CHECKER_TYPE,
38654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_107_WIDTH },
38655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_108_CHECKER_TYPE,
38656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_108_WIDTH },
38657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_109_CHECKER_TYPE,
38658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_109_WIDTH },
38659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_110_CHECKER_TYPE,
38660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_110_WIDTH },
38661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_111_CHECKER_TYPE,
38662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_111_WIDTH },
38663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_112_CHECKER_TYPE,
38664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_112_WIDTH },
38665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_113_CHECKER_TYPE,
38666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_113_WIDTH },
38667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_114_CHECKER_TYPE,
38668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_114_WIDTH },
38669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_115_CHECKER_TYPE,
38670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_115_WIDTH },
38671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_116_CHECKER_TYPE,
38672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_116_WIDTH },
38673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_117_CHECKER_TYPE,
38674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_117_WIDTH },
38675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_118_CHECKER_TYPE,
38676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_118_WIDTH },
38677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_119_CHECKER_TYPE,
38678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_119_WIDTH },
38679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_120_CHECKER_TYPE,
38680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_120_WIDTH },
38681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_121_CHECKER_TYPE,
38682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_121_WIDTH },
38683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_122_CHECKER_TYPE,
38684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_122_WIDTH },
38685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_123_CHECKER_TYPE,
38686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_123_WIDTH },
38687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_124_CHECKER_TYPE,
38688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_124_WIDTH },
38689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_125_CHECKER_TYPE,
38690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_125_WIDTH },
38691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_126_CHECKER_TYPE,
38692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_126_WIDTH },
38693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_127_CHECKER_TYPE,
38694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_127_WIDTH },
38695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_128_CHECKER_TYPE,
38696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_128_WIDTH },
38697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_129_CHECKER_TYPE,
38698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_129_WIDTH },
38699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_130_CHECKER_TYPE,
38700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_130_WIDTH },
38701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_131_CHECKER_TYPE,
38702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_131_WIDTH },
38703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_132_CHECKER_TYPE,
38704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_132_WIDTH },
38705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_133_CHECKER_TYPE,
38706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_133_WIDTH },
38707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_134_CHECKER_TYPE,
38708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_134_WIDTH },
38709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_135_CHECKER_TYPE,
38710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_135_WIDTH },
38711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_136_CHECKER_TYPE,
38712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_136_WIDTH },
38713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_137_CHECKER_TYPE,
38714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_137_WIDTH },
38715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_138_CHECKER_TYPE,
38716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_138_WIDTH },
38717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_139_CHECKER_TYPE,
38718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_139_WIDTH },
38719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_140_CHECKER_TYPE,
38720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_140_WIDTH },
38721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_141_CHECKER_TYPE,
38722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_141_WIDTH },
38723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_142_CHECKER_TYPE,
38724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_142_WIDTH },
38725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_143_CHECKER_TYPE,
38726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_143_WIDTH },
38727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_144_CHECKER_TYPE,
38728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_144_WIDTH },
38729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_145_CHECKER_TYPE,
38730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_145_WIDTH },
38731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_146_CHECKER_TYPE,
38732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_146_WIDTH },
38733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_147_CHECKER_TYPE,
38734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_147_WIDTH },
38735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_148_CHECKER_TYPE,
38736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_148_WIDTH },
38737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_149_CHECKER_TYPE,
38738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_149_WIDTH },
38739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_150_CHECKER_TYPE,
38740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_150_WIDTH },
38741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_151_CHECKER_TYPE,
38742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_151_WIDTH },
38743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_152_CHECKER_TYPE,
38744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_152_WIDTH },
38745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_153_CHECKER_TYPE,
38746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_153_WIDTH },
38747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_154_CHECKER_TYPE,
38748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_154_WIDTH },
38749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_155_CHECKER_TYPE,
38750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_155_WIDTH },
38751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_156_CHECKER_TYPE,
38752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_156_WIDTH },
38753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_157_CHECKER_TYPE,
38754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_157_WIDTH },
38755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_158_CHECKER_TYPE,
38756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_158_WIDTH },
38757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_159_CHECKER_TYPE,
38758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_159_WIDTH },
38759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_160_CHECKER_TYPE,
38760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_160_WIDTH },
38761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_161_CHECKER_TYPE,
38762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_161_WIDTH },
38763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_162_CHECKER_TYPE,
38764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_162_WIDTH },
38765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_163_CHECKER_TYPE,
38766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_163_WIDTH },
38767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_164_CHECKER_TYPE,
38768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_164_WIDTH },
38769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_165_CHECKER_TYPE,
38770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_165_WIDTH },
38771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_166_CHECKER_TYPE,
38772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_166_WIDTH },
38773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_167_CHECKER_TYPE,
38774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_167_WIDTH },
38775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_168_CHECKER_TYPE,
38776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_168_WIDTH },
38777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_169_CHECKER_TYPE,
38778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_169_WIDTH },
38779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_170_CHECKER_TYPE,
38780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_170_WIDTH },
38781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_171_CHECKER_TYPE,
38782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_171_WIDTH },
38783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_172_CHECKER_TYPE,
38784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_172_WIDTH },
38785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_173_CHECKER_TYPE,
38786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_173_WIDTH },
38787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_174_CHECKER_TYPE,
38788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_174_WIDTH },
38789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_175_CHECKER_TYPE,
38790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_175_WIDTH },
38791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_176_CHECKER_TYPE,
38792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_176_WIDTH },
38793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_177_CHECKER_TYPE,
38794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_177_WIDTH },
38795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_178_CHECKER_TYPE,
38796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_178_WIDTH },
38797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_179_CHECKER_TYPE,
38798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_179_WIDTH },
38799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_180_CHECKER_TYPE,
38800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_180_WIDTH },
38801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_181_CHECKER_TYPE,
38802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_181_WIDTH },
38803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_182_CHECKER_TYPE,
38804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_182_WIDTH },
38805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_183_CHECKER_TYPE,
38806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_183_WIDTH },
38807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_184_CHECKER_TYPE,
38808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_184_WIDTH },
38809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_185_CHECKER_TYPE,
38810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_185_WIDTH },
38811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_186_CHECKER_TYPE,
38812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_186_WIDTH },
38813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_187_CHECKER_TYPE,
38814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_187_WIDTH },
38815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_188_CHECKER_TYPE,
38816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_188_WIDTH },
38817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_189_CHECKER_TYPE,
38818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_189_WIDTH },
38819  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_190_CHECKER_TYPE,
38820  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_190_WIDTH },
38821  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_191_CHECKER_TYPE,
38822  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_191_WIDTH },
38823  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_192_CHECKER_TYPE,
38824  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_192_WIDTH },
38825  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_193_CHECKER_TYPE,
38826  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_193_WIDTH },
38827  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_194_CHECKER_TYPE,
38828  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_194_WIDTH },
38829  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_195_CHECKER_TYPE,
38830  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_195_WIDTH },
38831  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_196_CHECKER_TYPE,
38832  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_196_WIDTH },
38833  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_197_CHECKER_TYPE,
38834  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_197_WIDTH },
38835  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_198_CHECKER_TYPE,
38836  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_198_WIDTH },
38837  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_199_CHECKER_TYPE,
38838  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_199_WIDTH },
38839  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_200_CHECKER_TYPE,
38840  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_200_WIDTH },
38841  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_201_CHECKER_TYPE,
38842  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_201_WIDTH },
38843  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_202_CHECKER_TYPE,
38844  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_202_WIDTH },
38845  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_203_CHECKER_TYPE,
38846  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_203_WIDTH },
38847  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_204_CHECKER_TYPE,
38848  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_204_WIDTH },
38849  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_205_CHECKER_TYPE,
38850  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_205_WIDTH },
38851  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_206_CHECKER_TYPE,
38852  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_206_WIDTH },
38853  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_207_CHECKER_TYPE,
38854  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_207_WIDTH },
38855  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_208_CHECKER_TYPE,
38856  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_208_WIDTH },
38857  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_209_CHECKER_TYPE,
38858  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_209_WIDTH },
38859  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_210_CHECKER_TYPE,
38860  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_210_WIDTH },
38861  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_211_CHECKER_TYPE,
38862  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_211_WIDTH },
38863  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_212_CHECKER_TYPE,
38864  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_212_WIDTH },
38865  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_213_CHECKER_TYPE,
38866  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_213_WIDTH },
38867  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_214_CHECKER_TYPE,
38868  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_214_WIDTH },
38869  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_215_CHECKER_TYPE,
38870  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_215_WIDTH },
38871  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_216_CHECKER_TYPE,
38872  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_216_WIDTH },
38873  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_217_CHECKER_TYPE,
38874  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_217_WIDTH },
38875  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_218_CHECKER_TYPE,
38876  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_218_WIDTH },
38877  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_219_CHECKER_TYPE,
38878  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_219_WIDTH },
38879  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_220_CHECKER_TYPE,
38880  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_220_WIDTH },
38881  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_221_CHECKER_TYPE,
38882  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_221_WIDTH },
38883  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_222_CHECKER_TYPE,
38884  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_222_WIDTH },
38885  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_223_CHECKER_TYPE,
38886  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_223_WIDTH },
38887  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_224_CHECKER_TYPE,
38888  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_224_WIDTH },
38889  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_225_CHECKER_TYPE,
38890  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_225_WIDTH },
38891  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_226_CHECKER_TYPE,
38892  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_226_WIDTH },
38893  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_227_CHECKER_TYPE,
38894  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_227_WIDTH },
38895  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_228_CHECKER_TYPE,
38896  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_228_WIDTH },
38897  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_229_CHECKER_TYPE,
38898  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_229_WIDTH },
38899  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_230_CHECKER_TYPE,
38900  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_230_WIDTH },
38901  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_231_CHECKER_TYPE,
38902  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_231_WIDTH },
38903  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_232_CHECKER_TYPE,
38904  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_232_WIDTH },
38905  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_233_CHECKER_TYPE,
38906  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_233_WIDTH },
38907  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_234_CHECKER_TYPE,
38908  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_234_WIDTH },
38909  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_235_CHECKER_TYPE,
38910  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_235_WIDTH },
38911  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_236_CHECKER_TYPE,
38912  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_236_WIDTH },
38913  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_237_CHECKER_TYPE,
38914  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_237_WIDTH },
38915  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_238_CHECKER_TYPE,
38916  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_238_WIDTH },
38917  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_239_CHECKER_TYPE,
38918  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_239_WIDTH },
38919  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_240_CHECKER_TYPE,
38920  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_240_WIDTH },
38921  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_241_CHECKER_TYPE,
38922  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_241_WIDTH },
38923  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_242_CHECKER_TYPE,
38924  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_242_WIDTH },
38925  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_243_CHECKER_TYPE,
38926  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_243_WIDTH },
38927  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_244_CHECKER_TYPE,
38928  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_244_WIDTH },
38929  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_245_CHECKER_TYPE,
38930  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_245_WIDTH },
38931  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_246_CHECKER_TYPE,
38932  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_246_WIDTH },
38933  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_247_CHECKER_TYPE,
38934  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_247_WIDTH },
38935  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_248_CHECKER_TYPE,
38936  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_248_WIDTH },
38937  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_249_CHECKER_TYPE,
38938  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_249_WIDTH },
38939  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_250_CHECKER_TYPE,
38940  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_250_WIDTH },
38941  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_251_CHECKER_TYPE,
38942  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_251_WIDTH },
38943  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_252_CHECKER_TYPE,
38944  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_252_WIDTH },
38945  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_253_CHECKER_TYPE,
38946  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_253_WIDTH },
38947  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_254_CHECKER_TYPE,
38948  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_254_WIDTH },
38949  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_255_CHECKER_TYPE,
38950  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_GROUP_255_WIDTH },
38951 };
38952 
38958 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_MAX_NUM_CHECKERS] =
38959 {
38960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_0_CHECKER_TYPE,
38961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_0_WIDTH },
38962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_1_CHECKER_TYPE,
38963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_1_WIDTH },
38964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_2_CHECKER_TYPE,
38965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_2_WIDTH },
38966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_3_CHECKER_TYPE,
38967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_3_WIDTH },
38968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_4_CHECKER_TYPE,
38969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_4_WIDTH },
38970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_5_CHECKER_TYPE,
38971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_5_WIDTH },
38972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_6_CHECKER_TYPE,
38973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_6_WIDTH },
38974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_7_CHECKER_TYPE,
38975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_7_WIDTH },
38976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_8_CHECKER_TYPE,
38977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_8_WIDTH },
38978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_9_CHECKER_TYPE,
38979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_9_WIDTH },
38980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_10_CHECKER_TYPE,
38981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_10_WIDTH },
38982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_11_CHECKER_TYPE,
38983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_11_WIDTH },
38984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_12_CHECKER_TYPE,
38985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_12_WIDTH },
38986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_13_CHECKER_TYPE,
38987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_13_WIDTH },
38988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_14_CHECKER_TYPE,
38989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_14_WIDTH },
38990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_15_CHECKER_TYPE,
38991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_15_WIDTH },
38992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_16_CHECKER_TYPE,
38993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_16_WIDTH },
38994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_17_CHECKER_TYPE,
38995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_17_WIDTH },
38996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_18_CHECKER_TYPE,
38997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_18_WIDTH },
38998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_19_CHECKER_TYPE,
38999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_19_WIDTH },
39000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_20_CHECKER_TYPE,
39001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_20_WIDTH },
39002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_21_CHECKER_TYPE,
39003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_21_WIDTH },
39004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_22_CHECKER_TYPE,
39005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_22_WIDTH },
39006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_23_CHECKER_TYPE,
39007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_23_WIDTH },
39008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_24_CHECKER_TYPE,
39009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_24_WIDTH },
39010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_25_CHECKER_TYPE,
39011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_25_WIDTH },
39012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_26_CHECKER_TYPE,
39013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_26_WIDTH },
39014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_27_CHECKER_TYPE,
39015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_27_WIDTH },
39016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_28_CHECKER_TYPE,
39017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_28_WIDTH },
39018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_29_CHECKER_TYPE,
39019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_29_WIDTH },
39020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_30_CHECKER_TYPE,
39021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_30_WIDTH },
39022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_31_CHECKER_TYPE,
39023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_31_WIDTH },
39024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_32_CHECKER_TYPE,
39025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_32_WIDTH },
39026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_33_CHECKER_TYPE,
39027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_33_WIDTH },
39028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_34_CHECKER_TYPE,
39029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_34_WIDTH },
39030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_35_CHECKER_TYPE,
39031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_35_WIDTH },
39032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_36_CHECKER_TYPE,
39033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_36_WIDTH },
39034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_37_CHECKER_TYPE,
39035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_37_WIDTH },
39036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_38_CHECKER_TYPE,
39037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_38_WIDTH },
39038  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_39_CHECKER_TYPE,
39039  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_39_WIDTH },
39040  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_40_CHECKER_TYPE,
39041  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_40_WIDTH },
39042  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_41_CHECKER_TYPE,
39043  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_41_WIDTH },
39044  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_42_CHECKER_TYPE,
39045  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_42_WIDTH },
39046  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_43_CHECKER_TYPE,
39047  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_43_WIDTH },
39048  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_44_CHECKER_TYPE,
39049  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_44_WIDTH },
39050  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_45_CHECKER_TYPE,
39051  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_45_WIDTH },
39052  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_46_CHECKER_TYPE,
39053  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_46_WIDTH },
39054  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_47_CHECKER_TYPE,
39055  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_47_WIDTH },
39056  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_48_CHECKER_TYPE,
39057  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_48_WIDTH },
39058  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_49_CHECKER_TYPE,
39059  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_49_WIDTH },
39060  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_50_CHECKER_TYPE,
39061  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_50_WIDTH },
39062  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_51_CHECKER_TYPE,
39063  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_51_WIDTH },
39064  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_52_CHECKER_TYPE,
39065  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_52_WIDTH },
39066  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_53_CHECKER_TYPE,
39067  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_53_WIDTH },
39068  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_54_CHECKER_TYPE,
39069  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_54_WIDTH },
39070  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_55_CHECKER_TYPE,
39071  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_55_WIDTH },
39072  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_56_CHECKER_TYPE,
39073  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_56_WIDTH },
39074  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_57_CHECKER_TYPE,
39075  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_57_WIDTH },
39076  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_58_CHECKER_TYPE,
39077  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_58_WIDTH },
39078  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_59_CHECKER_TYPE,
39079  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_59_WIDTH },
39080  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_60_CHECKER_TYPE,
39081  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_60_WIDTH },
39082  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_61_CHECKER_TYPE,
39083  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_61_WIDTH },
39084  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_62_CHECKER_TYPE,
39085  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_62_WIDTH },
39086  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_63_CHECKER_TYPE,
39087  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_63_WIDTH },
39088  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_64_CHECKER_TYPE,
39089  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_64_WIDTH },
39090  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_65_CHECKER_TYPE,
39091  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_65_WIDTH },
39092  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_66_CHECKER_TYPE,
39093  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_66_WIDTH },
39094  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_67_CHECKER_TYPE,
39095  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_67_WIDTH },
39096  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_68_CHECKER_TYPE,
39097  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_68_WIDTH },
39098  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_69_CHECKER_TYPE,
39099  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_69_WIDTH },
39100  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_70_CHECKER_TYPE,
39101  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_70_WIDTH },
39102  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_71_CHECKER_TYPE,
39103  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_71_WIDTH },
39104  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_72_CHECKER_TYPE,
39105  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_72_WIDTH },
39106  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_73_CHECKER_TYPE,
39107  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_73_WIDTH },
39108  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_74_CHECKER_TYPE,
39109  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_74_WIDTH },
39110  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_75_CHECKER_TYPE,
39111  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_75_WIDTH },
39112  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_76_CHECKER_TYPE,
39113  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_76_WIDTH },
39114  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_77_CHECKER_TYPE,
39115  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_77_WIDTH },
39116  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_78_CHECKER_TYPE,
39117  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_78_WIDTH },
39118  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_79_CHECKER_TYPE,
39119  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_79_WIDTH },
39120  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_80_CHECKER_TYPE,
39121  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_80_WIDTH },
39122  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_81_CHECKER_TYPE,
39123  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_81_WIDTH },
39124  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_82_CHECKER_TYPE,
39125  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_82_WIDTH },
39126  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_83_CHECKER_TYPE,
39127  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_83_WIDTH },
39128  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_84_CHECKER_TYPE,
39129  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_84_WIDTH },
39130  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_85_CHECKER_TYPE,
39131  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_85_WIDTH },
39132  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_86_CHECKER_TYPE,
39133  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_86_WIDTH },
39134  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_87_CHECKER_TYPE,
39135  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_87_WIDTH },
39136  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_88_CHECKER_TYPE,
39137  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_88_WIDTH },
39138  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_89_CHECKER_TYPE,
39139  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_89_WIDTH },
39140  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_90_CHECKER_TYPE,
39141  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_90_WIDTH },
39142  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_91_CHECKER_TYPE,
39143  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_91_WIDTH },
39144  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_92_CHECKER_TYPE,
39145  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_92_WIDTH },
39146  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_93_CHECKER_TYPE,
39147  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_93_WIDTH },
39148  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_94_CHECKER_TYPE,
39149  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_94_WIDTH },
39150  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_95_CHECKER_TYPE,
39151  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_95_WIDTH },
39152  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_96_CHECKER_TYPE,
39153  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_96_WIDTH },
39154  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_97_CHECKER_TYPE,
39155  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_97_WIDTH },
39156  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_98_CHECKER_TYPE,
39157  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_98_WIDTH },
39158  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_99_CHECKER_TYPE,
39159  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_99_WIDTH },
39160  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_100_CHECKER_TYPE,
39161  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_100_WIDTH },
39162  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_101_CHECKER_TYPE,
39163  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_101_WIDTH },
39164  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_102_CHECKER_TYPE,
39165  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_102_WIDTH },
39166  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_103_CHECKER_TYPE,
39167  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_103_WIDTH },
39168  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_104_CHECKER_TYPE,
39169  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_104_WIDTH },
39170  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_105_CHECKER_TYPE,
39171  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_105_WIDTH },
39172  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_106_CHECKER_TYPE,
39173  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_106_WIDTH },
39174  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_107_CHECKER_TYPE,
39175  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_107_WIDTH },
39176  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_108_CHECKER_TYPE,
39177  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_108_WIDTH },
39178  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_109_CHECKER_TYPE,
39179  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_109_WIDTH },
39180  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_110_CHECKER_TYPE,
39181  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_110_WIDTH },
39182  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_111_CHECKER_TYPE,
39183  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_111_WIDTH },
39184  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_112_CHECKER_TYPE,
39185  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_112_WIDTH },
39186  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_113_CHECKER_TYPE,
39187  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_113_WIDTH },
39188  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_114_CHECKER_TYPE,
39189  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_114_WIDTH },
39190  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_115_CHECKER_TYPE,
39191  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_115_WIDTH },
39192  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_116_CHECKER_TYPE,
39193  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_116_WIDTH },
39194  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_117_CHECKER_TYPE,
39195  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_117_WIDTH },
39196  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_118_CHECKER_TYPE,
39197  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_118_WIDTH },
39198  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_119_CHECKER_TYPE,
39199  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_119_WIDTH },
39200  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_120_CHECKER_TYPE,
39201  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_120_WIDTH },
39202  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_121_CHECKER_TYPE,
39203  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_121_WIDTH },
39204  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_122_CHECKER_TYPE,
39205  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_122_WIDTH },
39206  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_123_CHECKER_TYPE,
39207  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_123_WIDTH },
39208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_124_CHECKER_TYPE,
39209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_124_WIDTH },
39210  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_125_CHECKER_TYPE,
39211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_125_WIDTH },
39212  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_126_CHECKER_TYPE,
39213  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_126_WIDTH },
39214  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_127_CHECKER_TYPE,
39215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_127_WIDTH },
39216  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_128_CHECKER_TYPE,
39217  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_128_WIDTH },
39218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_129_CHECKER_TYPE,
39219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_129_WIDTH },
39220  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_130_CHECKER_TYPE,
39221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_130_WIDTH },
39222  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_131_CHECKER_TYPE,
39223  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_131_WIDTH },
39224  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_132_CHECKER_TYPE,
39225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_132_WIDTH },
39226  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_133_CHECKER_TYPE,
39227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_133_WIDTH },
39228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_134_CHECKER_TYPE,
39229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_134_WIDTH },
39230  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_135_CHECKER_TYPE,
39231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_135_WIDTH },
39232  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_136_CHECKER_TYPE,
39233  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_136_WIDTH },
39234  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_137_CHECKER_TYPE,
39235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_137_WIDTH },
39236  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_138_CHECKER_TYPE,
39237  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_138_WIDTH },
39238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_139_CHECKER_TYPE,
39239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_139_WIDTH },
39240  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_140_CHECKER_TYPE,
39241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_140_WIDTH },
39242  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_141_CHECKER_TYPE,
39243  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_141_WIDTH },
39244  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_142_CHECKER_TYPE,
39245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_142_WIDTH },
39246  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_143_CHECKER_TYPE,
39247  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_143_WIDTH },
39248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_144_CHECKER_TYPE,
39249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_144_WIDTH },
39250  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_145_CHECKER_TYPE,
39251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_145_WIDTH },
39252  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_146_CHECKER_TYPE,
39253  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_146_WIDTH },
39254  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_147_CHECKER_TYPE,
39255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_147_WIDTH },
39256  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_148_CHECKER_TYPE,
39257  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_148_WIDTH },
39258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_149_CHECKER_TYPE,
39259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_149_WIDTH },
39260  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_150_CHECKER_TYPE,
39261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_150_WIDTH },
39262  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_151_CHECKER_TYPE,
39263  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_151_WIDTH },
39264  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_152_CHECKER_TYPE,
39265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_152_WIDTH },
39266  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_153_CHECKER_TYPE,
39267  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_153_WIDTH },
39268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_154_CHECKER_TYPE,
39269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_154_WIDTH },
39270  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_155_CHECKER_TYPE,
39271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_155_WIDTH },
39272  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_156_CHECKER_TYPE,
39273  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_156_WIDTH },
39274  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_157_CHECKER_TYPE,
39275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_157_WIDTH },
39276  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_158_CHECKER_TYPE,
39277  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_158_WIDTH },
39278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_159_CHECKER_TYPE,
39279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_159_WIDTH },
39280  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_160_CHECKER_TYPE,
39281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_160_WIDTH },
39282  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_161_CHECKER_TYPE,
39283  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_161_WIDTH },
39284  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_162_CHECKER_TYPE,
39285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_162_WIDTH },
39286  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_163_CHECKER_TYPE,
39287  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_163_WIDTH },
39288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_164_CHECKER_TYPE,
39289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_164_WIDTH },
39290  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_165_CHECKER_TYPE,
39291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_165_WIDTH },
39292  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_166_CHECKER_TYPE,
39293  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_166_WIDTH },
39294  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_167_CHECKER_TYPE,
39295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_167_WIDTH },
39296  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_168_CHECKER_TYPE,
39297  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_168_WIDTH },
39298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_169_CHECKER_TYPE,
39299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_169_WIDTH },
39300  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_170_CHECKER_TYPE,
39301  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_170_WIDTH },
39302  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_171_CHECKER_TYPE,
39303  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_171_WIDTH },
39304  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_172_CHECKER_TYPE,
39305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_172_WIDTH },
39306  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_173_CHECKER_TYPE,
39307  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_173_WIDTH },
39308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_174_CHECKER_TYPE,
39309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_174_WIDTH },
39310  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_175_CHECKER_TYPE,
39311  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_175_WIDTH },
39312  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_176_CHECKER_TYPE,
39313  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_176_WIDTH },
39314  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_177_CHECKER_TYPE,
39315  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_177_WIDTH },
39316  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_178_CHECKER_TYPE,
39317  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_GROUP_178_WIDTH },
39318 };
39319 
39325 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
39326 {
39327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
39328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
39329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
39330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
39331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
39332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
39333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
39334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
39335  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
39336  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
39337  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
39338  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
39339  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
39340  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
39341  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
39342  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
39343  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
39344  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
39345  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
39346  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
39347  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
39348  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
39349  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
39350  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
39351  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
39352  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
39353  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
39354  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
39355  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
39356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
39357  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
39358  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
39359  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
39360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
39361  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
39362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
39363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
39364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
39365  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
39366  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
39367  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
39368  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
39369  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
39370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
39371  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
39372  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
39373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
39374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
39375  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
39376  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
39377  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
39378  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
39379  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
39380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
39381  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
39382  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
39383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
39384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
39385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
39386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
39387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
39388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
39389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
39390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
39391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
39392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
39393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
39394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
39395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
39396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
39397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
39398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
39399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
39400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
39401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
39402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
39403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
39404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
39405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
39406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
39407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
39408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
39409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
39410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
39411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
39412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
39413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
39414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
39415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
39416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
39417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
39418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
39419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
39420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
39421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
39422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
39423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
39424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
39425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
39426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
39427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
39428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
39429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
39430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
39431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
39432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
39433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
39434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
39435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
39436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
39437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
39438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
39439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
39440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
39441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
39442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
39443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
39444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
39445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
39446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
39447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
39448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
39449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
39450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
39451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
39452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
39453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
39454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
39455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
39456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
39457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
39458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
39459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
39460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
39461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
39462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
39463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
39464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
39465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
39466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
39467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
39468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
39469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
39470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
39471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
39472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
39473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
39474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
39475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
39476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
39477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
39478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
39479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
39480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
39481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
39482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
39483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
39484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
39485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
39486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
39487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
39488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
39489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
39490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
39491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
39492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
39493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
39494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
39495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
39496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
39497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
39498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
39499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
39500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
39501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
39502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
39503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
39504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
39505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
39506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
39507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
39508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
39509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
39510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
39511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
39512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
39513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
39514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
39515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
39516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
39517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
39518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
39519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
39520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
39521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
39522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
39523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
39524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
39525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
39526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
39527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
39528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
39529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
39530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
39531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
39532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
39533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
39534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
39535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
39536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
39537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
39538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
39539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
39540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
39541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
39542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
39543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
39544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
39545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
39546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
39547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
39548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
39549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
39550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
39551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
39552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
39553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
39554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
39555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
39556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
39557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
39558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
39559  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
39560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
39561  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
39562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
39563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
39564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
39565  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
39566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
39567  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
39568  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
39569  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
39570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
39571  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
39572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
39573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
39574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
39575  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
39576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
39577  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
39578  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
39579  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
39580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
39581  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
39582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
39583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
39584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
39585  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
39586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
39587  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
39588  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
39589  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
39590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
39591  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
39592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
39593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
39594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
39595  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
39596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
39597  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
39598  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
39599  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
39600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
39601  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
39602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
39603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
39604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
39605  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
39606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
39607  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
39608  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
39609  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
39610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
39611  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
39612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
39613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
39614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
39615  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
39616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
39617  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
39618  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
39619  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
39620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
39621  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
39622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
39623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
39624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
39625  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
39626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
39627  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
39628  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
39629  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
39630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
39631  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
39632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
39633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
39634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
39635  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
39636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
39637  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
39638  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
39639  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
39640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
39641  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
39642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
39643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
39644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
39645  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
39646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
39647  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
39648  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
39649  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
39650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
39651  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
39652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
39653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
39654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
39655  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
39656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
39657  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
39658  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
39659  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
39660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
39661  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
39662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
39663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
39664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
39665  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
39666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
39667  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
39668  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
39669  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
39670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
39671  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
39672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
39673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
39674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
39675  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
39676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
39677  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
39678  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
39679  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
39680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
39681  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
39682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
39683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
39684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
39685  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
39686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
39687  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
39688  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
39689  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
39690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
39691  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
39692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
39693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
39694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
39695  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
39696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
39697  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
39698  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
39699  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
39700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
39701  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
39702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
39703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
39704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
39705  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
39706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
39707  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
39708  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
39709  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
39710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
39711  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
39712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
39713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
39714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
39715  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
39716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
39717  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
39718  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
39719  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
39720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
39721  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
39722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
39723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
39724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
39725  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
39726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
39727  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
39728  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
39729  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
39730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
39731  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
39732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
39733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
39734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
39735  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
39736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
39737  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
39738  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
39739  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
39740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
39741  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
39742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
39743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
39744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
39745  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
39746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
39747  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
39748  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
39749  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
39750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
39751  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
39752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
39753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
39754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
39755  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
39756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
39757  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
39758  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
39759  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
39760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
39761  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
39762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
39763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
39764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
39765  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
39766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
39767  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
39768  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
39769  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
39770  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
39771  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
39772  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
39773  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
39774  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
39775  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
39776  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
39777  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
39778  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
39779  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
39780  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
39781  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
39782  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
39783  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
39784  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
39785  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
39786  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_229_WIDTH },
39787  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
39788  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_230_WIDTH },
39789  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
39790  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_231_WIDTH },
39791  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
39792  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_232_WIDTH },
39793  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
39794  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_233_WIDTH },
39795  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
39796  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_234_WIDTH },
39797  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
39798  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_235_WIDTH },
39799  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
39800  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_236_WIDTH },
39801  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
39802  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_237_WIDTH },
39803  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
39804  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_238_WIDTH },
39805  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
39806  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_239_WIDTH },
39807  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
39808  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_240_WIDTH },
39809  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
39810  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_241_WIDTH },
39811  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
39812  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_242_WIDTH },
39813  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
39814  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_243_WIDTH },
39815  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
39816  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_244_WIDTH },
39817  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
39818  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_245_WIDTH },
39819  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
39820  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_246_WIDTH },
39821  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
39822  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_247_WIDTH },
39823  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
39824  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_248_WIDTH },
39825  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
39826  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_249_WIDTH },
39827  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
39828  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_250_WIDTH },
39829  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
39830  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_251_WIDTH },
39831  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
39832  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_252_WIDTH },
39833  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
39834  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_253_WIDTH },
39835  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
39836  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_254_WIDTH },
39837  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
39838  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_255_WIDTH },
39839 };
39840 
39846 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS] =
39847 {
39848  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
39849  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_0_WIDTH },
39850  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
39851  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_1_WIDTH },
39852  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
39853  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_2_WIDTH },
39854  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
39855  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_3_WIDTH },
39856  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
39857  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_4_WIDTH },
39858  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
39859  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_5_WIDTH },
39860  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
39861  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_GROUP_6_WIDTH },
39862 };
39863 
39869 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
39870 {
39871  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
39872  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
39873  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
39874  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
39875  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
39876  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
39877  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
39878  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
39879  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
39880  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
39881  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
39882  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
39883  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
39884  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
39885  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
39886  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
39887  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
39888  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
39889 };
39890 
39896 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
39897 {
39898  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
39899  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
39900  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
39901  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
39902  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
39903  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
39904  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
39905  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
39906  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
39907  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
39908  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
39909  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
39910  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
39911  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
39912  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
39913  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
39914  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
39915  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
39916  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
39917  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
39918  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
39919  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
39920  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
39921  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
39922  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
39923  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
39924  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
39925  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
39926  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
39927  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
39928 };
39929 
39935 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
39936 {
39937  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
39938  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
39939  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
39940  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
39941  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
39942  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
39943  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
39944  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
39945 };
39946 
39952 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
39953 {
39954  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
39955  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
39956  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
39957  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
39958  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
39959  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
39960  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
39961  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
39962  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
39963  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
39964  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
39965  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
39966  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
39967  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
39968  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
39969  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
39970  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
39971  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
39972  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
39973  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
39974  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
39975  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
39976  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
39977  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
39978  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
39979  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
39980  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
39981  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
39982  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
39983  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
39984  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
39985  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
39986  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
39987  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
39988  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
39989  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
39990  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
39991  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
39992  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
39993  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
39994  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
39995  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
39996  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
39997  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
39998  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
39999  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
40000  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
40001  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
40002  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
40003  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
40004  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
40005  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
40006  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
40007  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
40008  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
40009  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
40010  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
40011  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
40012  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
40013  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
40014  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
40015  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
40016  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
40017  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
40018  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
40019  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
40020  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
40021  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
40022  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
40023  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
40024  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
40025  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
40026  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
40027  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
40028  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
40029  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
40030  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
40031  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
40032  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
40033  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
40034  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
40035  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
40036  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
40037  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
40038 };
40039 
40045 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
40046 {
40047  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
40048  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
40049  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
40050  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
40051  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
40052  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
40053  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
40054  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
40055  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
40056  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
40057  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
40058  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
40059  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
40060  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
40061  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
40062  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
40063  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
40064  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
40065  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
40066  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
40067  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
40068  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
40069  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
40070  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
40071  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
40072  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
40073  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
40074  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
40075  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
40076  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
40077  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
40078  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
40079  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
40080  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
40081  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
40082  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
40083  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
40084  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
40085  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
40086  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
40087  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
40088  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
40089  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
40090  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
40091  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
40092  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
40093  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
40094  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
40095  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
40096  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
40097  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
40098  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
40099  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
40100  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
40101  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
40102  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
40103  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
40104  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
40105  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
40106  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
40107  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
40108  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
40109  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
40110  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
40111  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
40112  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
40113  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
40114  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
40115  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
40116  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
40117  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
40118  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
40119  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
40120  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
40121  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
40122  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
40123  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
40124  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
40125  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
40126  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
40127  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
40128  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
40129  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
40130  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
40131  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
40132  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
40133  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
40134  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
40135  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
40136  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
40137  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
40138  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
40139  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
40140  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
40141  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
40142  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
40143  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
40144  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
40145  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
40146  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
40147  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
40148  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
40149  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
40150  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
40151  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
40152  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
40153  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
40154  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
40155  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
40156  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
40157  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
40158  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
40159  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
40160  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
40161  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
40162  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
40163  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
40164  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
40165  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
40166  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
40167  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
40168  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
40169  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
40170  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
40171  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
40172  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_62_WIDTH },
40173  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
40174  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_63_WIDTH },
40175  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
40176  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_64_WIDTH },
40177  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
40178  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_65_WIDTH },
40179  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
40180  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_66_WIDTH },
40181  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
40182  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_67_WIDTH },
40183  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
40184  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_68_WIDTH },
40185  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
40186  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_69_WIDTH },
40187  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
40188  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_70_WIDTH },
40189  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
40190  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_71_WIDTH },
40191  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
40192  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_72_WIDTH },
40193  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
40194  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_73_WIDTH },
40195  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
40196  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_74_WIDTH },
40197  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
40198  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_75_WIDTH },
40199  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
40200  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_76_WIDTH },
40201  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
40202  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_77_WIDTH },
40203  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
40204  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_78_WIDTH },
40205  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
40206  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_79_WIDTH },
40207  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
40208  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_80_WIDTH },
40209  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
40210  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_81_WIDTH },
40211  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
40212  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_82_WIDTH },
40213  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
40214  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_83_WIDTH },
40215  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
40216  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_84_WIDTH },
40217  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
40218  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_85_WIDTH },
40219  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
40220  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_86_WIDTH },
40221  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
40222  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_87_WIDTH },
40223  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
40224  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_88_WIDTH },
40225  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
40226  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_89_WIDTH },
40227  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
40228  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_90_WIDTH },
40229  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
40230  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_91_WIDTH },
40231  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
40232  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_92_WIDTH },
40233  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
40234  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_93_WIDTH },
40235  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
40236  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_94_WIDTH },
40237  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
40238  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_95_WIDTH },
40239  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
40240  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_96_WIDTH },
40241  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
40242  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_97_WIDTH },
40243  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
40244  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_98_WIDTH },
40245  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
40246  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_99_WIDTH },
40247  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
40248  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_100_WIDTH },
40249  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
40250  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_101_WIDTH },
40251  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
40252  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_102_WIDTH },
40253  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
40254  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_103_WIDTH },
40255  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
40256  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_104_WIDTH },
40257  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
40258  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_105_WIDTH },
40259  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
40260  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_106_WIDTH },
40261  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
40262  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_107_WIDTH },
40263  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
40264  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_108_WIDTH },
40265  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
40266  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_109_WIDTH },
40267  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
40268  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_110_WIDTH },
40269  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
40270  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_111_WIDTH },
40271  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
40272  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_112_WIDTH },
40273  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
40274  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_113_WIDTH },
40275  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
40276  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_114_WIDTH },
40277  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
40278  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_115_WIDTH },
40279  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
40280  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_116_WIDTH },
40281  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
40282  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_117_WIDTH },
40283  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
40284  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_118_WIDTH },
40285  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
40286  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_119_WIDTH },
40287  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
40288  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_120_WIDTH },
40289  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
40290  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_121_WIDTH },
40291  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
40292  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_122_WIDTH },
40293  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
40294  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_123_WIDTH },
40295  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
40296  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_124_WIDTH },
40297  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
40298  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_125_WIDTH },
40299  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
40300  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_126_WIDTH },
40301  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
40302  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_127_WIDTH },
40303  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
40304  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_128_WIDTH },
40305  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
40306  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_129_WIDTH },
40307  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
40308  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_130_WIDTH },
40309  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
40310  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_131_WIDTH },
40311  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
40312  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_132_WIDTH },
40313  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
40314  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_133_WIDTH },
40315  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
40316  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_134_WIDTH },
40317  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
40318  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_135_WIDTH },
40319  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
40320  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_136_WIDTH },
40321  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
40322  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_137_WIDTH },
40323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
40324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_138_WIDTH },
40325  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
40326  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_139_WIDTH },
40327  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
40328  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_140_WIDTH },
40329  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
40330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_141_WIDTH },
40331  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
40332  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_142_WIDTH },
40333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
40334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_143_WIDTH },
40335  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
40336  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_144_WIDTH },
40337  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
40338  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_145_WIDTH },
40339  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
40340  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_146_WIDTH },
40341  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
40342  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_147_WIDTH },
40343  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
40344  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_148_WIDTH },
40345  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
40346  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_149_WIDTH },
40347  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
40348  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_150_WIDTH },
40349  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
40350  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_151_WIDTH },
40351  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
40352  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_152_WIDTH },
40353  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
40354  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_153_WIDTH },
40355  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
40356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_154_WIDTH },
40357  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
40358  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_155_WIDTH },
40359  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
40360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_156_WIDTH },
40361  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
40362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_157_WIDTH },
40363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
40364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_158_WIDTH },
40365  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
40366  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_159_WIDTH },
40367  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
40368  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_160_WIDTH },
40369  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
40370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_161_WIDTH },
40371  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
40372  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_162_WIDTH },
40373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
40374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_163_WIDTH },
40375  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
40376  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_164_WIDTH },
40377  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
40378  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_165_WIDTH },
40379  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
40380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_166_WIDTH },
40381  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
40382  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_167_WIDTH },
40383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
40384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_168_WIDTH },
40385  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
40386  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_169_WIDTH },
40387  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
40388  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_170_WIDTH },
40389  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
40390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_171_WIDTH },
40391  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
40392  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_172_WIDTH },
40393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
40394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_173_WIDTH },
40395  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
40396  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_174_WIDTH },
40397  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
40398  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_175_WIDTH },
40399  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
40400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_176_WIDTH },
40401  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
40402  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_177_WIDTH },
40403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
40404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_178_WIDTH },
40405  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
40406  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_179_WIDTH },
40407  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
40408  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_180_WIDTH },
40409  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
40410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_181_WIDTH },
40411  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
40412  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_182_WIDTH },
40413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
40414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_183_WIDTH },
40415  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
40416  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_184_WIDTH },
40417  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
40418  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_185_WIDTH },
40419  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
40420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_186_WIDTH },
40421  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
40422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_187_WIDTH },
40423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
40424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_188_WIDTH },
40425  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
40426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_189_WIDTH },
40427  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
40428  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_190_WIDTH },
40429  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
40430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_191_WIDTH },
40431  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
40432  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_192_WIDTH },
40433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
40434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_193_WIDTH },
40435  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
40436  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_194_WIDTH },
40437  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
40438  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_195_WIDTH },
40439  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
40440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_196_WIDTH },
40441  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
40442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_197_WIDTH },
40443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
40444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_198_WIDTH },
40445  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
40446  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_199_WIDTH },
40447  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
40448  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_200_WIDTH },
40449  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
40450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_201_WIDTH },
40451  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
40452  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_202_WIDTH },
40453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
40454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_203_WIDTH },
40455  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
40456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_204_WIDTH },
40457  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
40458  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_205_WIDTH },
40459  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
40460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_206_WIDTH },
40461  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
40462  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_207_WIDTH },
40463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
40464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_208_WIDTH },
40465  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
40466  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_209_WIDTH },
40467  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
40468  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_210_WIDTH },
40469  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
40470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_211_WIDTH },
40471  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
40472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_212_WIDTH },
40473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
40474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_213_WIDTH },
40475  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
40476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_214_WIDTH },
40477  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
40478  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_215_WIDTH },
40479  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
40480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_216_WIDTH },
40481  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
40482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_217_WIDTH },
40483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
40484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_218_WIDTH },
40485  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
40486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_219_WIDTH },
40487  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
40488  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_220_WIDTH },
40489  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
40490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_221_WIDTH },
40491  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
40492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_222_WIDTH },
40493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
40494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_223_WIDTH },
40495  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
40496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_224_WIDTH },
40497  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
40498  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_225_WIDTH },
40499  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
40500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_226_WIDTH },
40501  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
40502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_227_WIDTH },
40503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
40504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_228_WIDTH },
40505  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
40506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_229_WIDTH },
40507  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
40508  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_230_WIDTH },
40509  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
40510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_231_WIDTH },
40511  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
40512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_232_WIDTH },
40513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
40514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_233_WIDTH },
40515  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
40516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_234_WIDTH },
40517  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
40518  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_235_WIDTH },
40519  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
40520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_236_WIDTH },
40521  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
40522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_237_WIDTH },
40523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
40524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_238_WIDTH },
40525  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
40526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_239_WIDTH },
40527  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
40528  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_240_WIDTH },
40529  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
40530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_241_WIDTH },
40531  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
40532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_242_WIDTH },
40533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
40534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_243_WIDTH },
40535  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
40536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_244_WIDTH },
40537  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
40538  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_245_WIDTH },
40539  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
40540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_246_WIDTH },
40541  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
40542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_247_WIDTH },
40543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
40544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_248_WIDTH },
40545  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
40546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_249_WIDTH },
40547  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
40548  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_250_WIDTH },
40549  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
40550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_251_WIDTH },
40551  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
40552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_252_WIDTH },
40553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
40554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_253_WIDTH },
40555  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
40556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_254_WIDTH },
40557  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
40558  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_GROUP_255_WIDTH },
40559 };
40560 
40566 static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS] =
40567 {
40568  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
40569  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_0_WIDTH },
40570  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
40571  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_1_WIDTH },
40572  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
40573  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_2_WIDTH },
40574  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
40575  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_3_WIDTH },
40576  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
40577  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_4_WIDTH },
40578  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
40579  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_5_WIDTH },
40580  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
40581  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_6_WIDTH },
40582  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
40583  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_7_WIDTH },
40584  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
40585  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_8_WIDTH },
40586  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
40587  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_9_WIDTH },
40588  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
40589  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_10_WIDTH },
40590  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
40591  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_11_WIDTH },
40592  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
40593  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_12_WIDTH },
40594  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
40595  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_13_WIDTH },
40596  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
40597  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_14_WIDTH },
40598  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
40599  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_15_WIDTH },
40600  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
40601  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_16_WIDTH },
40602  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
40603  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_17_WIDTH },
40604  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
40605  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_18_WIDTH },
40606  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
40607  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_19_WIDTH },
40608  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
40609  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_20_WIDTH },
40610  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
40611  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_21_WIDTH },
40612  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
40613  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_22_WIDTH },
40614  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
40615  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_23_WIDTH },
40616  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
40617  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_24_WIDTH },
40618  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
40619  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_25_WIDTH },
40620  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
40621  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_26_WIDTH },
40622  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
40623  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_27_WIDTH },
40624  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
40625  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_28_WIDTH },
40626  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
40627  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_29_WIDTH },
40628  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
40629  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_30_WIDTH },
40630  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
40631  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_31_WIDTH },
40632  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
40633  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_32_WIDTH },
40634  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
40635  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_33_WIDTH },
40636  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
40637  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_34_WIDTH },
40638  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
40639  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_35_WIDTH },
40640  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
40641  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_36_WIDTH },
40642  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
40643  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_37_WIDTH },
40644  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
40645  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_38_WIDTH },
40646  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
40647  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_39_WIDTH },
40648  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
40649  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_40_WIDTH },
40650  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
40651  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_41_WIDTH },
40652  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
40653  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_42_WIDTH },
40654  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
40655  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_43_WIDTH },
40656  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
40657  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_44_WIDTH },
40658  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
40659  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_45_WIDTH },
40660  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
40661  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_46_WIDTH },
40662  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
40663  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_47_WIDTH },
40664  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
40665  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_48_WIDTH },
40666  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
40667  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_49_WIDTH },
40668  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
40669  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_50_WIDTH },
40670  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
40671  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_51_WIDTH },
40672  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
40673  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_52_WIDTH },
40674  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
40675  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_53_WIDTH },
40676  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
40677  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_54_WIDTH },
40678  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
40679  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_55_WIDTH },
40680  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
40681  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_56_WIDTH },
40682  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
40683  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_57_WIDTH },
40684  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
40685  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_58_WIDTH },
40686  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
40687  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_59_WIDTH },
40688  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
40689  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_60_WIDTH },
40690  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
40691  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_61_WIDTH },
40692  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
40693  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_62_WIDTH },
40694  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
40695  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_63_WIDTH },
40696  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
40697  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_64_WIDTH },
40698  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
40699  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_65_WIDTH },
40700  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
40701  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_66_WIDTH },
40702  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
40703  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_67_WIDTH },
40704  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
40705  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_68_WIDTH },
40706  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
40707  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_69_WIDTH },
40708  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
40709  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_70_WIDTH },
40710  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
40711  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_71_WIDTH },
40712  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
40713  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_72_WIDTH },
40714  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
40715  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_GROUP_73_WIDTH },
40716 };
40717 
40723 static const SDL_GrpChkConfig_t SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS] =
40724 {
40725  { SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
40726  SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
40727  { SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
40728  SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
40729 };
40730 
40735 static const SDL_MemConfig_t SDL_PCIE1_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES] =
40736 {
40737  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
40738  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
40739  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
40740  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
40741  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
40742  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
40743  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
40744  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
40745  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
40746  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
40747  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
40748  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
40749  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
40750  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
40751  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
40752  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
40753  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
40754  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
40755  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
40756  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
40757  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
40758 };
40759 
40764 static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
40765 {
40766  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
40767  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
40768  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
40769  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
40770  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
40771  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
40772  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
40773  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
40774  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
40775  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
40776  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
40777  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
40778  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
40779  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
40780  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
40781  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
40782  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
40783  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
40784  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
40785  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
40786  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
40787  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
40788  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
40789  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
40790  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
40791  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
40792  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
40793  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
40794  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
40795  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
40796  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
40797  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
40798  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
40799  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
40800  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
40801  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
40802  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
40803  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
40804  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
40805  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
40806  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
40807  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
40808  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
40809  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
40810  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
40811  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
40812  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
40813  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
40814  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
40815  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
40816  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
40817  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
40818  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
40819  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
40820  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
40821  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
40822  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
40823  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
40824  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
40825  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
40826  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
40827  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
40828  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
40829  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0u,
40830  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
40831  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
40832  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0u,
40833  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
40834  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
40835  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0u,
40836  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
40837  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
40838  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0u,
40839  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
40840  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
40841  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0u,
40842  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
40843  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
40844  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0u,
40845  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
40846  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
40847  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
40848  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
40849  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
40850 };
40851 
40857 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS] =
40858 {
40859  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
40860  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_WIDTH },
40861  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
40862  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_WIDTH },
40863  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
40864  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_WIDTH },
40865  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
40866  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_WIDTH },
40867  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
40868  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_WIDTH },
40869  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
40870  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_WIDTH },
40871  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
40872  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_WIDTH },
40873  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
40874  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_WIDTH },
40875  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
40876  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_WIDTH },
40877  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
40878  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_WIDTH },
40879  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
40880  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_WIDTH },
40881  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
40882  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_WIDTH },
40883  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
40884  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_WIDTH },
40885  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_CHECKER_TYPE,
40886  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_WIDTH },
40887  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_CHECKER_TYPE,
40888  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_WIDTH },
40889  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_CHECKER_TYPE,
40890  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_WIDTH },
40891  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_CHECKER_TYPE,
40892  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_WIDTH },
40893  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_CHECKER_TYPE,
40894  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_WIDTH },
40895  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_CHECKER_TYPE,
40896  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_WIDTH },
40897  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_CHECKER_TYPE,
40898  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_WIDTH },
40899  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_CHECKER_TYPE,
40900  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_WIDTH },
40901  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_CHECKER_TYPE,
40902  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_WIDTH },
40903  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_CHECKER_TYPE,
40904  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_WIDTH },
40905  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_CHECKER_TYPE,
40906  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_WIDTH },
40907  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_CHECKER_TYPE,
40908  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_WIDTH },
40909  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_CHECKER_TYPE,
40910  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_WIDTH },
40911  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_CHECKER_TYPE,
40912  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_WIDTH },
40913  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_CHECKER_TYPE,
40914  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_WIDTH },
40915  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_CHECKER_TYPE,
40916  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_WIDTH },
40917  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_CHECKER_TYPE,
40918  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_WIDTH },
40919  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_CHECKER_TYPE,
40920  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_WIDTH },
40921  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_CHECKER_TYPE,
40922  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_WIDTH },
40923  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_CHECKER_TYPE,
40924  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_WIDTH },
40925  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_CHECKER_TYPE,
40926  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_WIDTH },
40927  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_CHECKER_TYPE,
40928  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_WIDTH },
40929  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_CHECKER_TYPE,
40930  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_WIDTH },
40931  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_CHECKER_TYPE,
40932  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_WIDTH },
40933  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_CHECKER_TYPE,
40934  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_WIDTH },
40935  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_CHECKER_TYPE,
40936  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_WIDTH },
40937  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_CHECKER_TYPE,
40938  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_WIDTH },
40939  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_CHECKER_TYPE,
40940  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_WIDTH },
40941  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_CHECKER_TYPE,
40942  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_WIDTH },
40943  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_CHECKER_TYPE,
40944  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_WIDTH },
40945  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_CHECKER_TYPE,
40946  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_WIDTH },
40947  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_CHECKER_TYPE,
40948  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_WIDTH },
40949  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_CHECKER_TYPE,
40950  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_WIDTH },
40951  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_CHECKER_TYPE,
40952  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_WIDTH },
40953  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_CHECKER_TYPE,
40954  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_WIDTH },
40955  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_CHECKER_TYPE,
40956  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_WIDTH },
40957 };
40958 
40964 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
40965 {
40966  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
40967  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
40968  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
40969  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
40970  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
40971  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
40972  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
40973  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
40974  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
40975  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
40976  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
40977  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
40978  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
40979  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
40980  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
40981  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
40982  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
40983  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
40984  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
40985  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
40986  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
40987  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
40988  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
40989  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
40990  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
40991  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
40992  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
40993  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
40994  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
40995  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
40996  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
40997  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
40998  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
40999  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
41000  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
41001  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
41002  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
41003  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
41004  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
41005  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
41006  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
41007  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
41008  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
41009  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
41010  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
41011  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
41012  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
41013  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
41014  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
41015  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
41016  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
41017  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
41018  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
41019  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
41020  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
41021  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
41022  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
41023  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
41024  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
41025  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
41026  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
41027  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
41028 };
41029 
41035 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
41036 {
41037  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
41038  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
41039  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
41040  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
41041  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
41042  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
41043  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
41044  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
41045  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
41046  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
41047  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
41048  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
41049  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
41050  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
41051  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
41052  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
41053  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
41054  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
41055  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
41056  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
41057  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
41058  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
41059  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
41060  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
41061  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
41062  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
41063  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
41064  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
41065  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
41066  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
41067  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_CHECKER_TYPE,
41068  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_WIDTH },
41069 };
41070 
41076 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
41077 {
41078  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
41079  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
41080  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
41081  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
41082  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
41083  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
41084  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
41085  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
41086  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
41087  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
41088  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
41089  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
41090  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
41091  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
41092  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
41093  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
41094  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
41095  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
41096  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
41097  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
41098  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
41099  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
41100  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
41101  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
41102  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
41103  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
41104  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
41105  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
41106  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
41107  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
41108  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
41109  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
41110  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
41111  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
41112  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
41113  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
41114  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
41115  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
41116  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
41117  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
41118  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
41119  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
41120  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
41121  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
41122  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
41123  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
41124  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
41125  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
41126  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
41127  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
41128  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
41129  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
41130  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
41131  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
41132  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
41133  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
41134  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
41135  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
41136  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
41137  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
41138  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
41139  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
41140 };
41141 
41147 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
41148 {
41149  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
41150  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
41151  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
41152  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
41153  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
41154  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
41155  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
41156  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
41157  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
41158  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
41159  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
41160  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
41161  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
41162  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
41163  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
41164  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
41165  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
41166  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
41167  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
41168  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
41169  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
41170  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
41171  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
41172  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
41173  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
41174  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
41175  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
41176  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
41177  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
41178  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
41179 };
41180 
41186 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS] =
41187 {
41188  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
41189  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_0_WIDTH },
41190  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
41191  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_1_WIDTH },
41192  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
41193  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_2_WIDTH },
41194  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
41195  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_3_WIDTH },
41196  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
41197  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_4_WIDTH },
41198  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
41199  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_5_WIDTH },
41200  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
41201  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_6_WIDTH },
41202  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
41203  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_7_WIDTH },
41204  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
41205  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_8_WIDTH },
41206  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
41207  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_9_WIDTH },
41208  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
41209  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_10_WIDTH },
41210  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
41211  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_11_WIDTH },
41212  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
41213  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_GROUP_12_WIDTH },
41214 };
41215 
41221 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS] =
41222 {
41223  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
41224  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
41225  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
41226  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
41227  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
41228  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
41229 };
41230 
41236 static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
41237 {
41238  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
41239  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
41240  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
41241  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
41242  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
41243  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
41244  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
41245  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
41246  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
41247  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
41248  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
41249  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
41250 };
41251 
41256 static const SDL_MemConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_MemEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
41257 {
41258  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_RAM_ID, 0x0u,
41259  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_RAM_SIZE, 4u,
41260  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
41261 };
41262 
41268 static const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41269 {
41270  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41271  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
41272  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41273  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
41274  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41275  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
41276  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41277  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
41278  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41279  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
41280  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41281  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
41282  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41283  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
41284  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41285  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
41286  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41287  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
41288  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41289  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
41290  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41291  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
41292  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41293  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
41294  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41295  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
41296  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41297  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
41298  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41299  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
41300  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41301  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
41302  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41303  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
41304 };
41305 
41311 static const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
41312 {
41313  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
41314  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
41315  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
41316  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
41317  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
41318  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
41319  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
41320  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
41321  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
41322  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
41323  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
41324  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
41325 };
41326 
41331 static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
41332 {
41333  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
41334  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
41335  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
41336 };
41337 
41343 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41344 {
41345  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41346  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
41347  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41348  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
41349  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41350  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
41351  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41352  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
41353  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41354  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
41355  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41356  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
41357 };
41358 
41364 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41365 {
41366  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41367  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
41368  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41369  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
41370  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41371  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
41372  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41373  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
41374  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41375  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
41376  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41377  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
41378  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41379  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
41380  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41381  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
41382  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41383  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
41384  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41385  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
41386  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41387  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
41388  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41389  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
41390  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41391  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
41392  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41393  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
41394  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41395  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
41396  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41397  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
41398  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41399  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
41400  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41401  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
41402  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
41403  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
41404  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
41405  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
41406  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
41407  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
41408  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
41409  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
41410  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
41411  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
41412  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
41413  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
41414  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
41415  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
41416  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
41417  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
41418  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
41419  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
41420  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
41421  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
41422  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
41423  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
41424  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
41425  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
41426  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
41427  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
41428  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
41429  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
41430  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
41431  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
41432  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
41433  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
41434  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
41435  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
41436  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
41437  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
41438  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
41439  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
41440  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
41441  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
41442  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
41443  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
41444  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
41445  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
41446  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
41447  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
41448  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
41449  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
41450  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
41451  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
41452  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
41453  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
41454  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
41455  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
41456  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
41457  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
41458  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
41459  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
41460  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
41461  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
41462  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
41463  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
41464 };
41465 
41471 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41472 {
41473  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41474  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
41475  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41476  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
41477  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41478  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
41479  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41480  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
41481  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41482  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
41483  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41484  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
41485  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41486  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
41487  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41488  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
41489  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41490  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
41491  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41492  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
41493  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41494  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
41495  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41496  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
41497  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41498  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
41499  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41500  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
41501  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41502  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
41503  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41504  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
41505  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41506  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
41507  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41508  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
41509  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
41510  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
41511  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
41512  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
41513  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
41514  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
41515  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
41516  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
41517  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
41518  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
41519  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
41520  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
41521  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
41522  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
41523  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
41524  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
41525  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
41526  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
41527  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
41528  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
41529  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
41530  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
41531  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
41532  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
41533  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
41534  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
41535  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
41536  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
41537  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
41538  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
41539  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
41540  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
41541  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
41542  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
41543  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
41544  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
41545  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
41546  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
41547  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
41548  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
41549  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
41550  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
41551  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
41552  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
41553  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
41554  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
41555  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
41556  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
41557  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
41558  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
41559  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
41560  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
41561  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
41562  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
41563  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
41564  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
41565  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
41566  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
41567  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
41568  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
41569  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
41570  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
41571 };
41572 
41578 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41579 {
41580  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41581  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
41582  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41583  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
41584  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41585  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
41586  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41587  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
41588  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41589  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
41590  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41591  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
41592  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41593  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
41594  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41595  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
41596  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41597  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
41598  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41599  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
41600  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41601  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
41602  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41603  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
41604  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41605  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
41606  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41607  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
41608  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41609  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
41610  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41611  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
41612  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41613  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
41614  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41615  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
41616 };
41617 
41623 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41624 {
41625  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41626  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_0_WIDTH },
41627  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41628  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_1_WIDTH },
41629  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41630  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_2_WIDTH },
41631  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41632  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_3_WIDTH },
41633  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41634  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_4_WIDTH },
41635  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41636  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_5_WIDTH },
41637  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41638  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_6_WIDTH },
41639  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41640  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_7_WIDTH },
41641  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41642  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_8_WIDTH },
41643  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41644  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_9_WIDTH },
41645  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41646  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_10_WIDTH },
41647  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41648  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_11_WIDTH },
41649  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41650  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_12_WIDTH },
41651  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41652  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_13_WIDTH },
41653  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41654  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_14_WIDTH },
41655  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41656  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_15_WIDTH },
41657  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41658  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_16_WIDTH },
41659  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41660  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_17_WIDTH },
41661  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
41662  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_18_WIDTH },
41663  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
41664  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_19_WIDTH },
41665  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
41666  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_20_WIDTH },
41667  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
41668  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_21_WIDTH },
41669  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
41670  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_22_WIDTH },
41671  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
41672  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_23_WIDTH },
41673  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
41674  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_24_WIDTH },
41675  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
41676  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_25_WIDTH },
41677  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
41678  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_GROUP_26_WIDTH },
41679 };
41680 
41686 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41687 {
41688  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41689  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
41690  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41691  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
41692  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41693  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
41694  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41695  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
41696  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41697  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
41698  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41699  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
41700  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41701  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
41702  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41703  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
41704  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41705  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
41706  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41707  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
41708  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41709  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
41710  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41711  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
41712  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41713  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
41714  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41715  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
41716  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41717  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
41718  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41719  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
41720  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41721  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
41722  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41723  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
41724 };
41725 
41731 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41732 {
41733  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41734  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_0_WIDTH },
41735  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41736  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_1_WIDTH },
41737  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41738  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_2_WIDTH },
41739  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41740  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_3_WIDTH },
41741  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41742  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_4_WIDTH },
41743  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41744  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_5_WIDTH },
41745  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41746  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_6_WIDTH },
41747  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41748  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_7_WIDTH },
41749  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41750  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_8_WIDTH },
41751  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41752  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_9_WIDTH },
41753  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41754  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_10_WIDTH },
41755  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41756  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_11_WIDTH },
41757  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41758  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_12_WIDTH },
41759  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41760  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_13_WIDTH },
41761  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41762  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_14_WIDTH },
41763  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41764  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_15_WIDTH },
41765  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41766  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_16_WIDTH },
41767  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41768  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_17_WIDTH },
41769  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
41770  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_18_WIDTH },
41771  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
41772  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_19_WIDTH },
41773  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
41774  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_20_WIDTH },
41775  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
41776  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_21_WIDTH },
41777  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
41778  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_22_WIDTH },
41779  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
41780  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_23_WIDTH },
41781  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
41782  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_24_WIDTH },
41783  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
41784  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_25_WIDTH },
41785  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
41786  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_GROUP_26_WIDTH },
41787 };
41788 
41794 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41795 {
41796  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41797  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
41798  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41799  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
41800  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41801  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
41802  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41803  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
41804  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41805  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
41806  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41807  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
41808  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41809  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
41810  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41811  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
41812  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41813  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
41814  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41815  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
41816  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41817  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
41818  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41819  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
41820  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41821  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
41822  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41823  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
41824  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41825  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
41826  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41827  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
41828  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41829  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
41830  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41831  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
41832  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
41833  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
41834  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
41835  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
41836  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
41837  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
41838  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
41839  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
41840 };
41841 
41847 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41848 {
41849  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41850  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_0_WIDTH },
41851  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41852  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_1_WIDTH },
41853  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41854  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_2_WIDTH },
41855  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41856  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_3_WIDTH },
41857  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41858  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_4_WIDTH },
41859  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41860  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_5_WIDTH },
41861  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41862  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_6_WIDTH },
41863  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41864  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_7_WIDTH },
41865  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41866  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_8_WIDTH },
41867  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41868  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_9_WIDTH },
41869  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41870  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_10_WIDTH },
41871  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41872  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_11_WIDTH },
41873  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41874  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_12_WIDTH },
41875  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41876  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_13_WIDTH },
41877  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41878  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_14_WIDTH },
41879  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41880  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_15_WIDTH },
41881  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41882  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_16_WIDTH },
41883  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41884  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_17_WIDTH },
41885  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
41886  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_18_WIDTH },
41887  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
41888  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_19_WIDTH },
41889  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
41890  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_20_WIDTH },
41891  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
41892  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_21_WIDTH },
41893  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
41894  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_22_WIDTH },
41895  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
41896  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_23_WIDTH },
41897  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
41898  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_GROUP_24_WIDTH },
41899 };
41900 
41906 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
41907 {
41908  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
41909  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_0_WIDTH },
41910  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
41911  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_1_WIDTH },
41912  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
41913  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_2_WIDTH },
41914  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
41915  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_3_WIDTH },
41916  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
41917  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_4_WIDTH },
41918  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
41919  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_5_WIDTH },
41920  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
41921  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_6_WIDTH },
41922  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
41923  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_7_WIDTH },
41924  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
41925  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_8_WIDTH },
41926  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
41927  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_9_WIDTH },
41928  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
41929  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_10_WIDTH },
41930  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
41931  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_11_WIDTH },
41932  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
41933  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_12_WIDTH },
41934  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
41935  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_13_WIDTH },
41936  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
41937  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_14_WIDTH },
41938  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
41939  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_15_WIDTH },
41940  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
41941  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_16_WIDTH },
41942  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
41943  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_17_WIDTH },
41944  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
41945  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_18_WIDTH },
41946  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
41947  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_19_WIDTH },
41948  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
41949  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_20_WIDTH },
41950  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
41951  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_21_WIDTH },
41952  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
41953  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_22_WIDTH },
41954  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
41955  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_23_WIDTH },
41956  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
41957  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_24_WIDTH },
41958  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
41959  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_25_WIDTH },
41960  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
41961  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_26_WIDTH },
41962  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
41963  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_27_WIDTH },
41964  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
41965  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_28_WIDTH },
41966  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
41967  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_29_WIDTH },
41968  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
41969  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_30_WIDTH },
41970  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
41971  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_31_WIDTH },
41972  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
41973  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_32_WIDTH },
41974  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
41975  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_33_WIDTH },
41976  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
41977  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_34_WIDTH },
41978  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
41979  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_35_WIDTH },
41980  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
41981  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_36_WIDTH },
41982  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
41983  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_37_WIDTH },
41984  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
41985  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_38_WIDTH },
41986  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
41987  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_39_WIDTH },
41988  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
41989  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_40_WIDTH },
41990  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
41991  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_41_WIDTH },
41992  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
41993  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_42_WIDTH },
41994  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
41995  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_43_WIDTH },
41996  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
41997  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_44_WIDTH },
41998  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
41999  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_45_WIDTH },
42000  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
42001  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_46_WIDTH },
42002  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
42003  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_47_WIDTH },
42004  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
42005  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_48_WIDTH },
42006  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
42007  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_49_WIDTH },
42008  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
42009  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_50_WIDTH },
42010  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
42011  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_51_WIDTH },
42012  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
42013  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_52_WIDTH },
42014  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
42015  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_53_WIDTH },
42016  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
42017  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_54_WIDTH },
42018  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
42019  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_55_WIDTH },
42020  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
42021  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_56_WIDTH },
42022  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
42023  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_57_WIDTH },
42024  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
42025  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_58_WIDTH },
42026  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
42027  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_59_WIDTH },
42028  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
42029  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_60_WIDTH },
42030  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
42031  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_61_WIDTH },
42032  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
42033  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_62_WIDTH },
42034  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
42035  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_63_WIDTH },
42036  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
42037  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_64_WIDTH },
42038  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
42039  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_65_WIDTH },
42040  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
42041  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_66_WIDTH },
42042  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
42043  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_67_WIDTH },
42044  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
42045  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_68_WIDTH },
42046  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
42047  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_69_WIDTH },
42048  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
42049  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_70_WIDTH },
42050  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
42051  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_71_WIDTH },
42052  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
42053  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_72_WIDTH },
42054  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
42055  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_73_WIDTH },
42056  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
42057  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_74_WIDTH },
42058  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
42059  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_75_WIDTH },
42060  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
42061  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_76_WIDTH },
42062  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
42063  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_77_WIDTH },
42064  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
42065  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_78_WIDTH },
42066  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
42067  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_79_WIDTH },
42068  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
42069  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_80_WIDTH },
42070  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
42071  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_81_WIDTH },
42072  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
42073  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_82_WIDTH },
42074  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
42075  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_83_WIDTH },
42076  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
42077  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_84_WIDTH },
42078  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
42079  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_85_WIDTH },
42080  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
42081  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_86_WIDTH },
42082  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
42083  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_87_WIDTH },
42084  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
42085  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_88_WIDTH },
42086  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
42087  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_89_WIDTH },
42088  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
42089  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_90_WIDTH },
42090  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
42091  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_91_WIDTH },
42092  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
42093  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_92_WIDTH },
42094  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
42095  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_93_WIDTH },
42096  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
42097  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_94_WIDTH },
42098  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
42099  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_95_WIDTH },
42100  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
42101  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_96_WIDTH },
42102  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
42103  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_97_WIDTH },
42104  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
42105  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_98_WIDTH },
42106  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
42107  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_99_WIDTH },
42108  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
42109  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_100_WIDTH },
42110  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
42111  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_101_WIDTH },
42112  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
42113  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_102_WIDTH },
42114  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
42115  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_103_WIDTH },
42116  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
42117  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_104_WIDTH },
42118  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
42119  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_105_WIDTH },
42120  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
42121  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_106_WIDTH },
42122  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
42123  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_107_WIDTH },
42124  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
42125  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_108_WIDTH },
42126  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
42127  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_109_WIDTH },
42128  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
42129  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_110_WIDTH },
42130  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
42131  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_111_WIDTH },
42132  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
42133  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_112_WIDTH },
42134  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
42135  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_113_WIDTH },
42136  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
42137  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_114_WIDTH },
42138  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
42139  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_115_WIDTH },
42140  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
42141  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_116_WIDTH },
42142  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
42143  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_117_WIDTH },
42144  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
42145  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_118_WIDTH },
42146  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
42147  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_119_WIDTH },
42148  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
42149  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_120_WIDTH },
42150  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
42151  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_121_WIDTH },
42152  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
42153  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_122_WIDTH },
42154  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
42155  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_123_WIDTH },
42156  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
42157  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_124_WIDTH },
42158  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
42159  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_125_WIDTH },
42160  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
42161  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_126_WIDTH },
42162  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
42163  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_127_WIDTH },
42164  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
42165  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_128_WIDTH },
42166  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
42167  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_129_WIDTH },
42168  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
42169  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_130_WIDTH },
42170  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
42171  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_131_WIDTH },
42172  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
42173  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_132_WIDTH },
42174  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
42175  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_133_WIDTH },
42176  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
42177  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_134_WIDTH },
42178  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
42179  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_135_WIDTH },
42180  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
42181  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_136_WIDTH },
42182  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
42183  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_137_WIDTH },
42184  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
42185  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_138_WIDTH },
42186  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
42187  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_139_WIDTH },
42188  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
42189  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_140_WIDTH },
42190  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
42191  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_141_WIDTH },
42192  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
42193  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_142_WIDTH },
42194  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
42195  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_143_WIDTH },
42196  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
42197  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_144_WIDTH },
42198  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
42199  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_145_WIDTH },
42200  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
42201  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_146_WIDTH },
42202  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
42203  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_147_WIDTH },
42204  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
42205  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_148_WIDTH },
42206  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
42207  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_149_WIDTH },
42208  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
42209  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_150_WIDTH },
42210  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
42211  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_151_WIDTH },
42212  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
42213  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_152_WIDTH },
42214  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
42215  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_153_WIDTH },
42216  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
42217  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_154_WIDTH },
42218  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
42219  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_155_WIDTH },
42220  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
42221  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_156_WIDTH },
42222  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
42223  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_157_WIDTH },
42224  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
42225  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_158_WIDTH },
42226  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
42227  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_159_WIDTH },
42228  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
42229  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_160_WIDTH },
42230  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
42231  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_161_WIDTH },
42232  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
42233  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_162_WIDTH },
42234  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
42235  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_163_WIDTH },
42236  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
42237  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_164_WIDTH },
42238  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
42239  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_165_WIDTH },
42240  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
42241  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_166_WIDTH },
42242  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
42243  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_167_WIDTH },
42244  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
42245  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_168_WIDTH },
42246  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
42247  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_169_WIDTH },
42248  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
42249  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_170_WIDTH },
42250  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
42251  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_171_WIDTH },
42252  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
42253  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_172_WIDTH },
42254  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
42255  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_173_WIDTH },
42256  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
42257  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_174_WIDTH },
42258  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
42259  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_175_WIDTH },
42260  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
42261  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_176_WIDTH },
42262  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
42263  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_177_WIDTH },
42264  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
42265  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_178_WIDTH },
42266  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
42267  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_179_WIDTH },
42268  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
42269  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_180_WIDTH },
42270  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
42271  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_181_WIDTH },
42272  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
42273  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_182_WIDTH },
42274  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
42275  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_183_WIDTH },
42276  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
42277  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_184_WIDTH },
42278  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
42279  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_185_WIDTH },
42280  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
42281  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_186_WIDTH },
42282  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
42283  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_187_WIDTH },
42284  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
42285  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_188_WIDTH },
42286  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
42287  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_189_WIDTH },
42288  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
42289  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_190_WIDTH },
42290  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
42291  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_191_WIDTH },
42292  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
42293  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_192_WIDTH },
42294  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
42295  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_193_WIDTH },
42296  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
42297  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_194_WIDTH },
42298  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
42299  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_195_WIDTH },
42300  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
42301  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_196_WIDTH },
42302  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
42303  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_197_WIDTH },
42304  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
42305  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_198_WIDTH },
42306  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
42307  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_199_WIDTH },
42308  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
42309  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_200_WIDTH },
42310  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
42311  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_201_WIDTH },
42312  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
42313  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_202_WIDTH },
42314  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
42315  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_203_WIDTH },
42316  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
42317  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_204_WIDTH },
42318  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
42319  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_205_WIDTH },
42320  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
42321  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_206_WIDTH },
42322  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
42323  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_207_WIDTH },
42324  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
42325  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_208_WIDTH },
42326  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
42327  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_209_WIDTH },
42328  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
42329  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_GROUP_210_WIDTH },
42330 };
42331 
42337 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42338 {
42339  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42340  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
42341 };
42342 
42348 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42349 {
42350  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42351  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
42352  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42353  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
42354  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42355  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
42356  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42357  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
42358  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42359  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
42360  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42361  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
42362  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42363  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
42364  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42365  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
42366  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42367  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
42368  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42369  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
42370  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42371  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
42372  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42373  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
42374  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42375  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
42376  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42377  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
42378  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42379  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
42380 };
42381 
42387 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42388 {
42389  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42390  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
42391  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42392  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
42393  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42394  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
42395  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42396  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
42397 };
42398 
42404 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42405 {
42406  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42407  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
42408  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42409  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
42410  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42411  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
42412  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42413  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
42414  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42415  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
42416  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42417  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
42418  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42419  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
42420  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42421  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
42422  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42423  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
42424  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42425  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
42426  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42427  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
42428  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42429  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
42430  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42431  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
42432  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42433  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
42434  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42435  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
42436  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42437  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
42438  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42439  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
42440  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42441  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
42442  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
42443  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
42444  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
42445  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
42446  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
42447  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
42448  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
42449  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
42450  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
42451  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
42452  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
42453  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
42454  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
42455  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
42456  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
42457  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
42458  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
42459  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
42460  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
42461  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
42462  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
42463  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
42464  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
42465  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
42466  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
42467  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
42468  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
42469  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
42470  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
42471  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
42472  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
42473  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
42474  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
42475  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
42476  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
42477  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
42478  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
42479  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
42480  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
42481  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
42482  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
42483  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
42484  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
42485  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
42486  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
42487  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
42488  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
42489  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
42490 };
42491 
42497 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42498 {
42499  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42500  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_0_WIDTH },
42501  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42502  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_1_WIDTH },
42503  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42504  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_2_WIDTH },
42505  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42506  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_3_WIDTH },
42507  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42508  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_4_WIDTH },
42509  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42510  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_GROUP_5_WIDTH },
42511 };
42512 
42518 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42519 {
42520  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42521  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
42522  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42523  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
42524  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42525  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
42526  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42527  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
42528  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42529  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
42530  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42531  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
42532  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42533  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
42534  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42535  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
42536  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42537  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
42538  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42539  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
42540  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42541  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
42542  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42543  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
42544  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42545  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
42546  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42547  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
42548  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42549  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
42550  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42551  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
42552  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42553  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
42554  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42555  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
42556  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
42557  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
42558  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
42559  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
42560  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
42561  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
42562  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
42563  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
42564  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
42565  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
42566  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
42567  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
42568  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
42569  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
42570  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
42571  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
42572  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
42573  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
42574  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
42575  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
42576  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
42577  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
42578  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
42579  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
42580  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
42581  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
42582  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
42583  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
42584  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
42585  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
42586  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
42587  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
42588  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
42589  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
42590  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
42591  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
42592  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
42593  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
42594  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
42595  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
42596  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
42597  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
42598  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
42599  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
42600  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
42601  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
42602  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
42603  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
42604  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
42605  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
42606  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
42607  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
42608  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
42609  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
42610  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
42611  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
42612  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
42613  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
42614  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
42615  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
42616  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
42617  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
42618 };
42619 
42625 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42626 {
42627  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42628  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
42629  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42630  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
42631  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42632  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
42633  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42634  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
42635  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42636  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
42637  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42638  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
42639  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42640  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
42641  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42642  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
42643  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42644  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
42645  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42646  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
42647  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42648  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
42649  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42650  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
42651  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42652  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
42653  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42654  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
42655  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42656  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
42657  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42658  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
42659  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42660  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
42661  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42662  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
42663  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
42664  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
42665  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
42666  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
42667  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
42668  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
42669  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
42670  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
42671  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
42672  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
42673  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
42674  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
42675  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
42676  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
42677  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
42678  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
42679  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
42680  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
42681  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
42682  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
42683  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
42684  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
42685  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
42686  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
42687  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
42688  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
42689  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
42690  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
42691  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
42692  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
42693  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
42694  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
42695  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
42696  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
42697  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
42698  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
42699  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
42700  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
42701  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
42702  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
42703  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
42704  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
42705  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
42706  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
42707  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
42708  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
42709  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
42710  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
42711  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
42712  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
42713  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
42714  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
42715  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
42716  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
42717  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
42718  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
42719  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
42720  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
42721  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
42722  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
42723  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
42724  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
42725 };
42726 
42732 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42733 {
42734  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42735  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
42736  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42737  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
42738  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42739  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
42740  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42741  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
42742  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42743  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
42744  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42745  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
42746  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42747  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
42748  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42749  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
42750  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42751  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
42752  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42753  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
42754  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42755  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
42756  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42757  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
42758  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42759  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
42760  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42761  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
42762  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42763  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
42764  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42765  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
42766  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42767  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
42768  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42769  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
42770 };
42771 
42777 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42778 {
42779  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42780  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_0_WIDTH },
42781  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42782  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_1_WIDTH },
42783  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42784  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_2_WIDTH },
42785  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42786  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_3_WIDTH },
42787  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42788  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_4_WIDTH },
42789  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42790  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_5_WIDTH },
42791  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42792  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_6_WIDTH },
42793  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42794  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_7_WIDTH },
42795  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42796  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_8_WIDTH },
42797  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42798  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_9_WIDTH },
42799  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42800  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_10_WIDTH },
42801  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42802  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_11_WIDTH },
42803  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42804  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_12_WIDTH },
42805  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42806  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_13_WIDTH },
42807  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42808  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_14_WIDTH },
42809  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42810  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_15_WIDTH },
42811  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42812  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_16_WIDTH },
42813  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42814  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_17_WIDTH },
42815  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
42816  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_18_WIDTH },
42817  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
42818  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_19_WIDTH },
42819  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
42820  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_20_WIDTH },
42821  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
42822  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_21_WIDTH },
42823  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
42824  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_22_WIDTH },
42825  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
42826  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_23_WIDTH },
42827  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
42828  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_24_WIDTH },
42829  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
42830  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_25_WIDTH },
42831  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
42832  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_GROUP_26_WIDTH },
42833 };
42834 
42840 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42841 {
42842  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42843  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
42844  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42845  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
42846  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42847  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
42848  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42849  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
42850  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42851  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
42852  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42853  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
42854  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42855  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
42856  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42857  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
42858  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42859  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
42860  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42861  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
42862  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42863  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
42864  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42865  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
42866  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42867  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
42868  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42869  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
42870  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42871  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
42872  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42873  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
42874  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42875  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
42876  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42877  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
42878 };
42879 
42885 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42886 {
42887  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42888  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_0_WIDTH },
42889  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42890  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_1_WIDTH },
42891  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42892  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_2_WIDTH },
42893  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42894  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_3_WIDTH },
42895  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42896  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_4_WIDTH },
42897  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42898  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_5_WIDTH },
42899  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42900  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_6_WIDTH },
42901  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42902  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_7_WIDTH },
42903  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42904  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_8_WIDTH },
42905  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42906  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_9_WIDTH },
42907  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42908  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_10_WIDTH },
42909  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42910  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_11_WIDTH },
42911  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42912  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_12_WIDTH },
42913  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42914  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_13_WIDTH },
42915  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42916  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_14_WIDTH },
42917  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42918  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_15_WIDTH },
42919  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42920  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_16_WIDTH },
42921  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42922  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_17_WIDTH },
42923  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
42924  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_18_WIDTH },
42925  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
42926  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_19_WIDTH },
42927  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
42928  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_20_WIDTH },
42929  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
42930  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_21_WIDTH },
42931  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
42932  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_22_WIDTH },
42933  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
42934  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_23_WIDTH },
42935  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
42936  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_24_WIDTH },
42937  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
42938  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_25_WIDTH },
42939  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
42940  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_GROUP_26_WIDTH },
42941 };
42942 
42948 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
42949 {
42950  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
42951  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
42952  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
42953  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
42954  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
42955  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
42956  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
42957  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
42958  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
42959  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
42960  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
42961  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
42962  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
42963  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
42964  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
42965  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
42966  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
42967  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
42968  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
42969  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
42970  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
42971  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
42972  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
42973  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
42974  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
42975  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
42976  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
42977  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
42978  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
42979  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
42980  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
42981  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
42982  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
42983  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
42984  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
42985  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
42986  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
42987  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
42988  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
42989  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
42990  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
42991  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
42992  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
42993  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
42994 };
42995 
43001 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43002 {
43003  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43004  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_0_WIDTH },
43005  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43006  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_1_WIDTH },
43007  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43008  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_2_WIDTH },
43009  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43010  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_3_WIDTH },
43011  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
43012  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_4_WIDTH },
43013  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
43014  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_5_WIDTH },
43015  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
43016  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_6_WIDTH },
43017  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
43018  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_7_WIDTH },
43019  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
43020  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_8_WIDTH },
43021  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
43022  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_9_WIDTH },
43023  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
43024  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_10_WIDTH },
43025  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
43026  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_11_WIDTH },
43027  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
43028  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_12_WIDTH },
43029  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
43030  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_13_WIDTH },
43031  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
43032  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_14_WIDTH },
43033  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
43034  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_15_WIDTH },
43035  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
43036  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_16_WIDTH },
43037  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
43038  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_17_WIDTH },
43039  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
43040  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_18_WIDTH },
43041  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
43042  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_19_WIDTH },
43043  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
43044  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_20_WIDTH },
43045  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
43046  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_21_WIDTH },
43047  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
43048  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_22_WIDTH },
43049  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
43050  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_23_WIDTH },
43051  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
43052  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_GROUP_24_WIDTH },
43053 };
43054 
43060 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43061 {
43062  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43063  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_0_WIDTH },
43064  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43065  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_1_WIDTH },
43066  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43067  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_2_WIDTH },
43068  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43069  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_3_WIDTH },
43070  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
43071  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_4_WIDTH },
43072  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
43073  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_5_WIDTH },
43074  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
43075  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_6_WIDTH },
43076  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
43077  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_7_WIDTH },
43078  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
43079  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_8_WIDTH },
43080  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
43081  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_9_WIDTH },
43082  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
43083  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_10_WIDTH },
43084  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
43085  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_11_WIDTH },
43086  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
43087  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_12_WIDTH },
43088  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
43089  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_13_WIDTH },
43090  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
43091  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_14_WIDTH },
43092  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
43093  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_15_WIDTH },
43094  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
43095  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_16_WIDTH },
43096  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
43097  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_17_WIDTH },
43098  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
43099  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_18_WIDTH },
43100  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
43101  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_19_WIDTH },
43102  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
43103  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_20_WIDTH },
43104  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
43105  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_21_WIDTH },
43106  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
43107  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_22_WIDTH },
43108  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
43109  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_23_WIDTH },
43110  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
43111  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_24_WIDTH },
43112  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
43113  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_25_WIDTH },
43114  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
43115  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_26_WIDTH },
43116  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
43117  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_27_WIDTH },
43118  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
43119  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_28_WIDTH },
43120  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
43121  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_29_WIDTH },
43122  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
43123  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_30_WIDTH },
43124  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
43125  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_31_WIDTH },
43126  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
43127  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_32_WIDTH },
43128  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
43129  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_33_WIDTH },
43130  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
43131  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_34_WIDTH },
43132  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
43133  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_35_WIDTH },
43134  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
43135  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_36_WIDTH },
43136  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
43137  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_37_WIDTH },
43138  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
43139  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_38_WIDTH },
43140  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
43141  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_39_WIDTH },
43142  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
43143  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_40_WIDTH },
43144  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
43145  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_41_WIDTH },
43146  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
43147  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_42_WIDTH },
43148  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
43149  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_43_WIDTH },
43150  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
43151  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_44_WIDTH },
43152  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
43153  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_45_WIDTH },
43154  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
43155  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_46_WIDTH },
43156  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
43157  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_47_WIDTH },
43158  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
43159  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_48_WIDTH },
43160  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
43161  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_49_WIDTH },
43162  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
43163  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_50_WIDTH },
43164  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
43165  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_51_WIDTH },
43166  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
43167  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_52_WIDTH },
43168  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
43169  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_53_WIDTH },
43170  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
43171  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_54_WIDTH },
43172  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
43173  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_55_WIDTH },
43174  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
43175  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_56_WIDTH },
43176  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
43177  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_57_WIDTH },
43178  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
43179  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_58_WIDTH },
43180  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
43181  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_59_WIDTH },
43182  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
43183  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_60_WIDTH },
43184  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
43185  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_61_WIDTH },
43186  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
43187  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_62_WIDTH },
43188  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
43189  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_63_WIDTH },
43190  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
43191  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_64_WIDTH },
43192  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
43193  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_65_WIDTH },
43194  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
43195  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_66_WIDTH },
43196  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
43197  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_67_WIDTH },
43198  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
43199  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_68_WIDTH },
43200  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
43201  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_69_WIDTH },
43202  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
43203  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_70_WIDTH },
43204  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
43205  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_71_WIDTH },
43206  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
43207  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_72_WIDTH },
43208  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
43209  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_73_WIDTH },
43210  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
43211  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_74_WIDTH },
43212  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
43213  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_75_WIDTH },
43214  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
43215  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_76_WIDTH },
43216  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
43217  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_77_WIDTH },
43218  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
43219  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_78_WIDTH },
43220  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
43221  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_79_WIDTH },
43222  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
43223  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_80_WIDTH },
43224  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
43225  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_81_WIDTH },
43226  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
43227  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_82_WIDTH },
43228  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
43229  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_83_WIDTH },
43230  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
43231  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_84_WIDTH },
43232  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
43233  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_85_WIDTH },
43234  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
43235  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_86_WIDTH },
43236  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
43237  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_87_WIDTH },
43238  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
43239  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_88_WIDTH },
43240  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
43241  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_89_WIDTH },
43242  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
43243  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_90_WIDTH },
43244  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
43245  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_91_WIDTH },
43246  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
43247  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_92_WIDTH },
43248  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
43249  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_93_WIDTH },
43250  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
43251  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_94_WIDTH },
43252  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
43253  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_95_WIDTH },
43254  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
43255  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_96_WIDTH },
43256  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
43257  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_97_WIDTH },
43258  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
43259  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_98_WIDTH },
43260  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
43261  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_99_WIDTH },
43262  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
43263  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_100_WIDTH },
43264  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
43265  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_101_WIDTH },
43266  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
43267  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_102_WIDTH },
43268  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
43269  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_103_WIDTH },
43270  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
43271  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_104_WIDTH },
43272  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
43273  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_105_WIDTH },
43274  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
43275  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_106_WIDTH },
43276  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
43277  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_107_WIDTH },
43278  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
43279  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_108_WIDTH },
43280  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
43281  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_109_WIDTH },
43282  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
43283  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_110_WIDTH },
43284  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
43285  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_111_WIDTH },
43286  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
43287  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_112_WIDTH },
43288  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
43289  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_113_WIDTH },
43290  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
43291  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_114_WIDTH },
43292  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
43293  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_115_WIDTH },
43294  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
43295  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_116_WIDTH },
43296  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
43297  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_117_WIDTH },
43298  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
43299  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_118_WIDTH },
43300  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
43301  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_119_WIDTH },
43302  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
43303  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_120_WIDTH },
43304  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
43305  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_121_WIDTH },
43306  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
43307  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_122_WIDTH },
43308  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
43309  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_123_WIDTH },
43310  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
43311  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_124_WIDTH },
43312  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
43313  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_125_WIDTH },
43314  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
43315  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_126_WIDTH },
43316  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
43317  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_127_WIDTH },
43318  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
43319  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_128_WIDTH },
43320  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
43321  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_129_WIDTH },
43322  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
43323  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_130_WIDTH },
43324  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
43325  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_131_WIDTH },
43326  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
43327  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_132_WIDTH },
43328  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
43329  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_133_WIDTH },
43330  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
43331  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_134_WIDTH },
43332  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
43333  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_135_WIDTH },
43334  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
43335  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_136_WIDTH },
43336  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
43337  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_137_WIDTH },
43338  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
43339  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_138_WIDTH },
43340  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
43341  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_139_WIDTH },
43342  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
43343  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_140_WIDTH },
43344  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
43345  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_141_WIDTH },
43346  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
43347  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_142_WIDTH },
43348  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
43349  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_143_WIDTH },
43350  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
43351  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_144_WIDTH },
43352  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
43353  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_145_WIDTH },
43354  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
43355  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_146_WIDTH },
43356  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
43357  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_147_WIDTH },
43358  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
43359  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_148_WIDTH },
43360  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
43361  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_149_WIDTH },
43362  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
43363  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_150_WIDTH },
43364  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
43365  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_151_WIDTH },
43366  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
43367  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_152_WIDTH },
43368  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
43369  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_153_WIDTH },
43370  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
43371  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_154_WIDTH },
43372  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
43373  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_155_WIDTH },
43374  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
43375  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_156_WIDTH },
43376  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
43377  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_157_WIDTH },
43378  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
43379  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_158_WIDTH },
43380  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
43381  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_159_WIDTH },
43382  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
43383  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_160_WIDTH },
43384  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
43385  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_161_WIDTH },
43386  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
43387  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_162_WIDTH },
43388  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
43389  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_163_WIDTH },
43390  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
43391  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_164_WIDTH },
43392  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
43393  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_165_WIDTH },
43394  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
43395  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_166_WIDTH },
43396  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
43397  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_167_WIDTH },
43398  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
43399  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_168_WIDTH },
43400  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
43401  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_169_WIDTH },
43402  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
43403  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_170_WIDTH },
43404  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
43405  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_171_WIDTH },
43406  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
43407  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_172_WIDTH },
43408  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
43409  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_173_WIDTH },
43410  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
43411  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_174_WIDTH },
43412  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
43413  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_175_WIDTH },
43414  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
43415  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_176_WIDTH },
43416  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
43417  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_177_WIDTH },
43418  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
43419  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_178_WIDTH },
43420  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
43421  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_179_WIDTH },
43422  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
43423  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_180_WIDTH },
43424  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
43425  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_181_WIDTH },
43426  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
43427  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_182_WIDTH },
43428  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
43429  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_183_WIDTH },
43430  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
43431  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_184_WIDTH },
43432  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
43433  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_185_WIDTH },
43434  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
43435  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_186_WIDTH },
43436  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
43437  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_187_WIDTH },
43438  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
43439  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_188_WIDTH },
43440  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
43441  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_189_WIDTH },
43442  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
43443  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_190_WIDTH },
43444  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
43445  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_191_WIDTH },
43446  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
43447  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_192_WIDTH },
43448  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
43449  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_193_WIDTH },
43450  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
43451  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_194_WIDTH },
43452  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
43453  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_195_WIDTH },
43454  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
43455  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_196_WIDTH },
43456  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
43457  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_197_WIDTH },
43458  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
43459  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_198_WIDTH },
43460  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
43461  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_199_WIDTH },
43462  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
43463  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_200_WIDTH },
43464  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
43465  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_201_WIDTH },
43466  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
43467  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_202_WIDTH },
43468  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
43469  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_203_WIDTH },
43470  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
43471  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_204_WIDTH },
43472  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
43473  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_205_WIDTH },
43474  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
43475  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_206_WIDTH },
43476  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
43477  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_207_WIDTH },
43478  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
43479  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_208_WIDTH },
43480  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
43481  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_209_WIDTH },
43482  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
43483  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_GROUP_210_WIDTH },
43484 };
43485 
43491 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43492 {
43493  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43494  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
43495 };
43496 
43502 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43503 {
43504  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43505  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
43506  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43507  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
43508  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43509  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
43510  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43511  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
43512  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
43513  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
43514  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
43515  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
43516  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
43517  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
43518  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
43519  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
43520  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
43521  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
43522  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
43523  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
43524  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
43525  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
43526  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
43527  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
43528  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
43529  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
43530  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
43531  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
43532  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
43533  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
43534 };
43535 
43541 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43542 {
43543  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43544  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
43545  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43546  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
43547  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43548  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
43549  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43550  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
43551 };
43552 
43558 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43559 {
43560  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43561  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
43562  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43563  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
43564  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43565  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
43566  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43567  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
43568  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
43569  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
43570  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
43571  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
43572  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
43573  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
43574  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
43575  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
43576  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
43577  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
43578  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
43579  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
43580  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
43581  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
43582  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
43583  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
43584  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
43585  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
43586  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
43587  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
43588  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
43589  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
43590  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
43591  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
43592  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
43593  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
43594  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
43595  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
43596  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
43597  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
43598  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
43599  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
43600  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
43601  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
43602  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
43603  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
43604  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
43605  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
43606  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
43607  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
43608  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
43609  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
43610  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
43611  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
43612  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
43613  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
43614  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
43615  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
43616  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
43617  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
43618  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
43619  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
43620  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
43621  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
43622  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
43623  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
43624  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
43625  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
43626  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
43627  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
43628  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
43629  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
43630  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
43631  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
43632  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
43633  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
43634  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
43635  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
43636  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
43637  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
43638  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
43639  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
43640  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
43641  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
43642  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
43643  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
43644 };
43645 
43651 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43652 {
43653  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43654  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_0_WIDTH },
43655  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43656  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_1_WIDTH },
43657  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43658  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_2_WIDTH },
43659  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43660  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_3_WIDTH },
43661  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
43662  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_4_WIDTH },
43663  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
43664  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_GROUP_5_WIDTH },
43665 };
43666 
43672 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43673 {
43674  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43675  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_0_WIDTH },
43676  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43677  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_1_WIDTH },
43678  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43679  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_2_WIDTH },
43680  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43681  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_GROUP_3_WIDTH },
43682 };
43683 
43689 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43690 {
43691  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43692  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
43693  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43694  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
43695  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43696  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
43697  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43698  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
43699  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
43700  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
43701  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
43702  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
43703  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
43704  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
43705  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
43706  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
43707  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
43708  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
43709  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
43710  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
43711  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
43712  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
43713  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
43714  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
43715  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
43716  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
43717  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
43718  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
43719  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
43720  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
43721  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
43722  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
43723  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
43724  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
43725  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
43726  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
43727  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
43728  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
43729  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
43730  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
43731  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
43732  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
43733  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
43734  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
43735  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
43736  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
43737  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
43738  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
43739  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
43740  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
43741  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
43742  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
43743  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
43744  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
43745  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
43746  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
43747  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
43748  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
43749  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
43750  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
43751  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
43752  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
43753  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
43754  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
43755  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
43756  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
43757  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
43758  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
43759  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
43760  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
43761  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
43762  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
43763  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
43764  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
43765  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
43766  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
43767  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
43768  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
43769  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
43770  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
43771  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
43772  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
43773  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
43774  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
43775  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
43776  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
43777  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
43778  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
43779  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
43780  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
43781  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
43782  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
43783  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
43784  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
43785  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
43786  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
43787  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
43788  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
43789  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
43790  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
43791  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
43792  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
43793  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
43794  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
43795  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
43796  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
43797  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
43798  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
43799  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
43800  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
43801  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
43802  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
43803  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
43804  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
43805  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
43806  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
43807  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
43808  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
43809  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
43810  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
43811  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
43812  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
43813  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
43814  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
43815  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
43816  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
43817  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
43818  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
43819  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
43820  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
43821  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
43822  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
43823  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
43824  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
43825  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
43826  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
43827  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
43828  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
43829  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
43830  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
43831  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
43832  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
43833  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
43834  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
43835  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
43836  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
43837  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
43838  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
43839 };
43840 
43846 static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
43847 {
43848  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
43849  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
43850  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
43851  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
43852  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
43853  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
43854  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
43855  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
43856  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
43857  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
43858  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
43859  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
43860  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
43861  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
43862  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
43863  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
43864  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
43865  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
43866  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
43867  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
43868  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
43869  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
43870  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
43871  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
43872  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
43873  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
43874  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
43875  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
43876  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
43877  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
43878  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
43879  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
43880  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
43881  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
43882  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
43883  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
43884  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
43885  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
43886 };
43887 
43892 static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
43893 {
43894  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x40540000u,
43895  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
43896  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
43897 };
43898 
43904 static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
43905 {
43906  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
43907  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
43908 };
43909 
43914 static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
43915 {
43916  { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID, 0u,
43917  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
43918  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
43919 };
43920 
43926 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
43927 {
43928  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
43929  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
43930  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
43931  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
43932  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
43933  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
43934  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
43935  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
43936  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
43937  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
43938  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
43939  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
43940  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
43941  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
43942  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
43943  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
43944  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
43945  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
43946  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
43947  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
43948  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
43949  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
43950  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
43951  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
43952  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
43953  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
43954  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
43955  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
43956  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
43957  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
43958  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
43959  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
43960  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
43961  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
43962  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
43963  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
43964 };
43965 
43971 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
43972 {
43973  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
43974  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
43975  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
43976  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
43977  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
43978  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
43979  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
43980  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
43981  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
43982  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
43983  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
43984  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
43985  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
43986  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
43987  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
43988  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
43989  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
43990  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
43991  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
43992  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
43993  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
43994  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
43995  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
43996  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
43997  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
43998  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
43999  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44000  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44001  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44002  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44003  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44004  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44005  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44006  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44007  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44008  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44009  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44010  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44011  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44012  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44013  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44014  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44015  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44016  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44017  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44018  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44019 };
44020 
44026 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44027 {
44028  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44029  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44030  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44031  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44032  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44033  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44034  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44035  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44036  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44037  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44038  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44039  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44040  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44041  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44042  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44043  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44044  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44045  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44046  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44047  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44048  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44049  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44050  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44051  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44052  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44053  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44054  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44055  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44056  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44057  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44058 };
44059 
44065 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44066 {
44067  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44068  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44069  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44070  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44071  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44072  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44073  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44074  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44075 };
44076 
44082 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44083 {
44084  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44085  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44086  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44087  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44088  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44089  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44090  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44091  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44092  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44093  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44094  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44095  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44096  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44097  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44098  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44099  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44100  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44101  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44102  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44103  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44104  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44105  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44106  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44107  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44108  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44109  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44110  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44111  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44112  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44113  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44114  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44115  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44116  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44117  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44118  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44119  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44120 };
44121 
44127 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44128 {
44129  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44130  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44131  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44132  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44133  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44134  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44135  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44136  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44137  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44138  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44139  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44140  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44141  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44142  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44143  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44144  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44145  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44146  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44147  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44148  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44149  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44150  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44151  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44152  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44153  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44154  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44155  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44156  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44157  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44158  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44159  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44160  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44161  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44162  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44163  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44164  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44165  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44166  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44167  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44168  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44169  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44170  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44171  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44172  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44173  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44174  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44175 };
44176 
44182 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44183 {
44184  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44185  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44186  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44187  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44188  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44189  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44190  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44191  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44192  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44193  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44194  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44195  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44196  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44197  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44198  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44199  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44200  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44201  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44202  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44203  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44204  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44205  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44206  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44207  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44208  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44209  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44210  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44211  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44212  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44213  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44214  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44215  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44216  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44217  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44218  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44219  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44220 };
44221 
44227 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44228 {
44229  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44230  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44231  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44232  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44233  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44234  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44235  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44236  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44237  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44238  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44239  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44240  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44241  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44242  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44243  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44244  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44245  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44246  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44247  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44248  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44249  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44250  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44251  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44252  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44253  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44254  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44255  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44256  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44257  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44258  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44259  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44260  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44261  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44262  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44263  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44264  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44265  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44266  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44267  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44268  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44269  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44270  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44271  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44272  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44273  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44274  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44275 };
44276 
44282 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44283 {
44284  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44285  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44286  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44287  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44288  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44289  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44290  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44291  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44292  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44293  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44294  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44295  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44296  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44297  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44298  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44299  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44300  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44301  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44302  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44303  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44304  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44305  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44306  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44307  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44308  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44309  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44310  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44311  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44312  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44313  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44314  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44315  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44316  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44317  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44318  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44319  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44320 };
44321 
44327 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44328 {
44329  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44330  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44331  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44332  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44333  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44334  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44335  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44336  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44337  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44338  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44339  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44340  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44341  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44342  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44343  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44344  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44345  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44346  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44347  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44348  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44349  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44350  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44351  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44352  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44353  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44354  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44355  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44356  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44357  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44358  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44359  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44360  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44361  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44362  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44363  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44364  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44365  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44366  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44367  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44368  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44369  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44370  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44371  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44372  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44373  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44374  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44375 };
44376 
44382 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44383 {
44384  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44385  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44386  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44387  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44388  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44389  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44390  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44391  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44392  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44393  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44394  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44395  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44396  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44397  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44398  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44399  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44400  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44401  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44402  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44403  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44404  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44405  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44406  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44407  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44408  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44409  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44410  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44411  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44412  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44413  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44414  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44415  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44416  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44417  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44418  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44419  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44420 };
44421 
44427 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44428 {
44429  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44430  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44431  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44432  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44433  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44434  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44435  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44436  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44437  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44438  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44439  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44440  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44441  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44442  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44443  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44444  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44445  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44446  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44447  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44448  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44449  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44450  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44451  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44452  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44453  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44454  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44455  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44456  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44457  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44458  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44459  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44460  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44461  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44462  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44463  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44464  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44465  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44466  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44467  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44468  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44469  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44470  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44471  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44472  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44473  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44474  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44475 };
44476 
44482 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
44483 {
44484  { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
44485  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
44486  { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
44487  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
44488  { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
44489  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
44490  { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
44491  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
44492  { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
44493  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
44494  { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
44495  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
44496 };
44497 
44503 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44504 {
44505  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44506  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44507  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44508  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44509  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44510  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44511  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44512  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44513  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44514  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44515  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44516  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44517  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44518  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44519  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44520  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44521  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44522  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44523  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44524  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44525  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44526  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44527  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44528  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44529  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44530  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44531  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44532  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44533  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44534  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44535 };
44536 
44542 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44543 {
44544  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44545  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44546  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44547  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44548  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44549  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44550  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44551  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44552 };
44553 
44559 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44560 {
44561  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44562  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44563  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44564  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44565  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44566  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44567  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44568  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44569  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44570  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44571  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44572  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44573  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44574  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44575  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44576  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44577  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44578  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44579  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44580  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44581  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44582  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44583  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44584  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44585  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44586  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44587  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44588  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44589  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44590  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44591  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44592  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44593  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44594  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44595  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44596  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44597 };
44598 
44604 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44605 {
44606  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44607  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44608  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44609  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44610  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44611  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44612  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44613  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44614  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44615  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44616  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44617  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44618  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44619  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44620  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44621  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44622  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44623  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44624  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44625  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44626  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44627  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44628  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44629  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44630  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44631  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44632  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44633  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44634  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44635  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44636  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44637  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44638  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44639  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44640  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44641  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44642  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44643  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44644  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44645  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44646  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44647  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44648  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44649  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44650  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44651  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44652 };
44653 
44659 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44660 {
44661  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44662  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44663  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44664  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44665  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44666  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44667  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44668  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44669  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44670  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44671  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44672  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44673  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44674  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44675  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44676  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44677  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44678  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44679  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44680  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44681  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44682  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44683  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44684  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44685  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44686  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44687  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44688  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44689  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44690  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44691 };
44692 
44698 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44699 {
44700  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44701  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44702  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44703  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44704  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44705  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44706  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44707  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44708 };
44709 
44715 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44716 {
44717  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44718  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44719  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44720  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44721  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44722  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44723  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44724  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44725  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44726  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44727  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44728  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44729  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44730  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44731  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44732  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44733  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44734  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44735  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44736  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44737  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44738  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44739  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44740  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44741  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44742  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44743  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44744  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44745  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44746  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44747  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44748  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44749  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44750  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44751  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44752  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44753 };
44754 
44760 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44761 {
44762  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44763  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44764  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44765  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44766  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44767  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44768  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44769  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44770  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44771  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44772  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44773  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44774  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44775  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44776  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44777  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44778  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44779  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44780  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44781  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44782  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44783  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44784  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44785  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44786  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44787  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44788  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44789  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44790  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44791  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44792  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44793  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44794  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44795  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44796  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44797  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44798  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44799  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44800  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44801  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44802  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44803  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44804  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44805  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44806  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44807  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44808 };
44809 
44815 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44816 {
44817  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44818  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44819  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44820  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44821  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44822  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44823  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44824  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44825  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44826  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44827  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44828  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44829  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44830  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44831  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44832  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44833  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44834  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44835  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44836  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44837  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44838  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44839  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44840  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44841  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44842  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44843  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44844  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44845  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44846  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44847  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44848  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44849  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44850  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44851  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44852  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44853 };
44854 
44860 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44861 {
44862  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44863  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44864  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44865  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44866  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44867  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44868  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44869  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44870  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44871  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44872  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44873  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44874  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44875  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44876  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44877  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44878  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44879  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44880  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44881  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44882  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44883  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44884  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44885  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44886  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44887  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44888  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44889  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44890  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44891  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44892  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44893  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44894  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44895  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44896  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44897  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44898  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44899  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
44900  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
44901  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
44902  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
44903  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
44904  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
44905  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
44906  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
44907  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
44908 };
44909 
44915 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44916 {
44917  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44918  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44919  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44920  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44921  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44922  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44923  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44924  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44925  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44926  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44927  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44928  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44929  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44930  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44931  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44932  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44933  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44934  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44935  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44936  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44937  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44938  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44939  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44940  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44941  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44942  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44943  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44944  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44945  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44946  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44947  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44948  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44949  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44950  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44951  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44952  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44953 };
44954 
44960 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
44961 {
44962  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
44963  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
44964  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
44965  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
44966  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
44967  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
44968  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
44969  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
44970  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
44971  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
44972  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
44973  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
44974  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
44975  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
44976  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
44977  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
44978  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
44979  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
44980  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
44981  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
44982  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
44983  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
44984  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
44985  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
44986  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
44987  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
44988  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
44989  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
44990  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
44991  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
44992  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
44993  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
44994  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
44995  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
44996  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
44997  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
44998  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
44999  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
45000  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
45001  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
45002  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
45003  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
45004  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
45005  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
45006  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
45007  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
45008 };
45009 
45015 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45016 {
45017  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45018  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45019  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45020  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45021  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45022  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45023  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45024  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45025  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45026  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45027  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45028  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45029  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45030  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45031  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45032  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45033  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45034  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45035  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45036  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45037  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45038  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45039  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45040  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45041  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45042  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45043  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45044  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45045  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45046  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45047  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45048  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45049  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45050  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45051  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45052  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45053 };
45054 
45060 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45061 {
45062  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45063  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45064  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45065  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45066  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45067  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45068  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45069  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45070  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45071  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45072  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45073  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45074  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45075  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45076  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45077  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45078  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45079  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45080  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45081  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45082  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45083  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45084  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45085  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45086  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45087  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45088  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45089  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45090  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45091  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45092  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45093  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45094  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45095  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45096  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45097  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45098  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
45099  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
45100  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
45101  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
45102  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
45103  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
45104  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
45105  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
45106  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
45107  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
45108 };
45109 
45115 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
45116 {
45117  { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
45118  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
45119  { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
45120  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
45121  { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
45122  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
45123  { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
45124  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
45125  { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
45126  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
45127  { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
45128  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
45129 };
45130 
45136 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45137 {
45138  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45139  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45140  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45141  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45142  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45143  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45144  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45145  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45146  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45147  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45148  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45149  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45150  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45151  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45152  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45153  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45154  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45155  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45156  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45157  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45158  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45159  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45160  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45161  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45162  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45163  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45164  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45165  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45166  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45167  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45168 };
45169 
45175 static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45176 {
45177  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45178  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45179  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45180  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45181  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45182  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45183  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45184  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45185 };
45186 
45192 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45193 {
45194  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45195  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45196  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45197  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45198  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45199  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45200  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45201  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45202  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45203  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45204  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45205  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45206  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45207  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45208  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45209  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45210  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45211  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45212  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45213  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45214  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45215  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45216  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45217  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45218  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45219  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45220  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45221  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45222  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45223  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45224  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45225  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45226  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45227  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45228  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45229  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45230 };
45231 
45237 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45238 {
45239  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45240  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45241  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45242  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45243  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45244  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45245  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45246  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45247  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45248  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45249  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45250  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45251  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45252  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45253  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45254  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45255  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45256  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45257  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45258  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45259  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45260  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45261  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45262  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45263  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45264  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45265  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45266  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45267  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45268  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45269  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45270  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45271  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45272  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45273  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45274  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45275  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
45276  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
45277  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
45278  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
45279  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
45280  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
45281  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
45282  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
45283  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
45284  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
45285 };
45286 
45292 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45293 {
45294  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45295  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45296  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45297  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45298  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45299  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45300  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45301  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45302  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45303  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45304  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45305  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45306  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45307  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45308  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45309  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45310  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45311  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45312  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45313  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45314  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45315  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45316  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45317  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45318  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45319  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45320  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45321  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45322  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45323  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45324 };
45325 
45331 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45332 {
45333  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45334  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45335  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45336  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45337  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45338  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45339  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45340  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45341 };
45342 
45348 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45349 {
45350  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45351  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45352  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45353  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45354  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45355  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45356  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45357  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45358  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45359  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45360  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45361  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45362  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45363  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45364  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45365  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45366  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45367  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45368  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45369  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45370  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45371  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45372  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45373  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45374  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45375  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45376  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45377  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45378  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45379  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45380  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45381  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45382  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45383  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45384  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45385  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45386 };
45387 
45393 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45394 {
45395  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45396  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45397  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45398  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45399  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45400  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45401  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45402  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45403  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45404  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45405  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45406  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45407  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45408  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45409  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45410  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45411  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45412  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45413  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45414  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45415  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45416  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45417  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45418  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45419  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45420  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45421  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45422  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45423  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45424  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45425  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45426  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45427  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45428  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45429  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45430  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45431  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
45432  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
45433  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
45434  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
45435  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
45436  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
45437  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
45438  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
45439  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
45440  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
45441 };
45442 
45448 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45449 {
45450  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45451  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45452  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45453  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45454  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45455  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45456  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45457  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45458  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45459  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45460  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45461  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45462  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45463  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45464  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45465  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45466  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45467  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45468  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45469  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45470  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45471  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45472  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45473  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45474  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45475  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45476  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45477  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45478  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45479  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45480  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45481  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45482  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45483  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45484  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45485  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45486 };
45487 
45493 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45494 {
45495  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45496  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45497  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45498  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45499  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45500  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45501  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45502  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45503  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45504  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45505  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45506  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45507  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45508  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45509  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45510  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45511  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45512  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45513  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45514  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45515  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45516  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45517  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45518  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45519  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45520  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45521  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45522  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45523  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45524  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45525  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45526  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45527  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45528  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45529  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45530  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45531  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
45532  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
45533  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
45534  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
45535  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
45536  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
45537  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
45538  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
45539  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
45540  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
45541 };
45542 
45548 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45549 {
45550  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45551  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45552  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45553  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45554  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45555  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45556  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45557  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45558  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45559  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45560  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45561  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45562  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45563  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45564  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45565  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45566  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45567  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45568  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45569  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45570  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45571  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45572  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45573  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45574  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45575  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45576  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45577  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45578  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45579  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45580  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45581  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45582  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45583  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45584  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45585  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45586 };
45587 
45593 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45594 {
45595  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45596  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45597  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45598  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45599  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45600  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45601  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45602  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45603  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45604  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45605  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45606  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45607  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45608  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45609  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45610  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45611  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45612  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45613  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45614  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45615  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45616  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45617  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45618  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45619  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45620  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45621  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45622  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45623  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45624  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45625  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45626  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45627  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45628  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45629  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45630  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45631  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
45632  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
45633  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
45634  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
45635  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
45636  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
45637  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
45638  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
45639  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
45640  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
45641 };
45642 
45648 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45649 {
45650  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45651  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45652  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45653  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45654  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45655  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45656  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45657  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45658  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45659  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45660  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45661  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45662  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45663  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45664  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45665  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45666  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45667  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45668  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45669  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45670  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45671  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45672  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45673  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45674  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45675  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45676  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45677  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45678  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45679  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45680  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45681  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45682  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45683  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45684  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45685  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45686 };
45687 
45693 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
45694 {
45695  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
45696  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
45697  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
45698  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
45699  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
45700  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
45701  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
45702  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
45703  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
45704  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
45705  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
45706  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
45707  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
45708  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
45709  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
45710  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
45711  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
45712  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
45713  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
45714  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
45715  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
45716  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
45717  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
45718  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
45719  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
45720  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
45721  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
45722  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
45723  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
45724  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
45725  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
45726  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
45727  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
45728  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
45729  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
45730  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
45731  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
45732  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
45733  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
45734  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
45735  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
45736  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
45737  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
45738  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
45739  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
45740  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
45741 };
45742 
45748 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
45749 {
45750  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
45751  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
45752  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
45753  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
45754  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
45755  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
45756  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
45757  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
45758  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
45759  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
45760  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
45761  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
45762 };
45763 
45768 static const SDL_MemConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
45769 {
45770  { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2748000u,
45771  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
45772  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
45773 };
45774 
45780 static const SDL_GrpChkConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
45781 {
45782  { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
45783  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
45784 };
45785 
45790 static const SDL_MemConfig_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES] =
45791 {
45792  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
45793  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
45794  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
45795  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
45796  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
45797  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
45798  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
45799  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
45800  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
45801  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
45802  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
45803  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
45804  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
45805  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
45806  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
45807  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
45808  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
45809  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
45810  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
45811  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
45812  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
45813  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
45814  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
45815  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
45816 };
45817 
45823 static const SDL_GrpChkConfig_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS] =
45824 {
45825  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
45826  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_WIDTH },
45827  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
45828  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_WIDTH },
45829  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
45830  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_WIDTH },
45831  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
45832  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_WIDTH },
45833  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
45834  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_WIDTH },
45835  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
45836  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_WIDTH },
45837  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
45838  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_WIDTH },
45839  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
45840  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_WIDTH },
45841  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
45842  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_WIDTH },
45843  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
45844  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_WIDTH },
45845  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
45846  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_WIDTH },
45847  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
45848  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_WIDTH },
45849  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
45850  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_WIDTH },
45851  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
45852  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_WIDTH },
45853  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
45854  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_WIDTH },
45855  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
45856  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_WIDTH },
45857 };
45858 
45863 static const SDL_MemConfig_t SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries[SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
45864 {
45865  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_ID, 0u,
45866  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_SIZE, 4u,
45867  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_ROW_WIDTH, ((bool)false) },
45868  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_ID, 0u,
45869  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_SIZE, 4u,
45870  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_ROW_WIDTH, ((bool)false) },
45871  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_ID, 0u,
45872  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
45873  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)false) },
45874  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
45875  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
45876  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
45877  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
45878  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
45879  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
45880  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
45881  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 4u,
45882  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)false) },
45883  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
45884  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
45885  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
45886  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
45887  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
45888  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
45889  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
45890  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 4u,
45891  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)false) },
45892  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
45893  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 4u,
45894  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)false) },
45895  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
45896  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 4u,
45897  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)false) },
45898  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
45899  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 4u,
45900  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)false) },
45901 };
45902 
45907 static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
45908 {
45909  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2718000u,
45910  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
45911  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
45912 };
45913 
45919 static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
45920 {
45921  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
45922  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
45923 };
45924 
45929 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
45930 {
45931  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2708000u,
45932  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
45933  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
45934 };
45935 
45941 static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
45942 {
45943  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
45944  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
45945 };
45946 
45951 static const SDL_MemConfig_t SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
45952 {
45953  { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
45954  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
45955  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
45956  { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
45957  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
45958  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
45959 };
45960 
45965 static const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
45966 {
45967  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_RAM_ID, 0u,
45968  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_RAM_SIZE, 4u,
45969  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_ROW_WIDTH, ((bool)false) },
45970  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_ID, 0u,
45971  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_SIZE, 4u,
45972  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_ROW_WIDTH, ((bool)false) },
45973 };
45974 
45980 static const SDL_GrpChkConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS] =
45981 {
45982  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
45983  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_0_WIDTH },
45984  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
45985  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_1_WIDTH },
45986  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
45987  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_2_WIDTH },
45988  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
45989  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_3_WIDTH },
45990  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
45991  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_4_WIDTH },
45992  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
45993  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_GROUP_5_WIDTH },
45994 };
45995 
46001 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46002 {
46003  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46004  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46005  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46006  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46007  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46008  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46009  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46010  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46011  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46012  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46013  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46014  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46015  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46016  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46017  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46018  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46019  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46020  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46021  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46022  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46023  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46024  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46025  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46026  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46027  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46028  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46029  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46030  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46031  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46032  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46033  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46034  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46035  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46036  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46037  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46038  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46039 };
46040 
46046 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46047 {
46048  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46049  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46050  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46051  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46052  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46053  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46054  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46055  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46056  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46057  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46058  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46059  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46060  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46061  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46062  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46063  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46064  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46065  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46066  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46067  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46068  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46069  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46070  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46071  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46072  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46073  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46074  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46075  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46076  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46077  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46078  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46079  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46080  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46081  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46082  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46083  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46084  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
46085  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
46086  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
46087  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
46088  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
46089  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
46090  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
46091  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
46092  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
46093  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
46094 };
46095 
46101 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46102 {
46103  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46104  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46105  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46106  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46107  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46108  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46109  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46110  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46111  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46112  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46113  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46114  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46115  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46116  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46117  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46118  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46119  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46120  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46121  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46122  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46123  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46124  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46125  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46126  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46127  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46128  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46129  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46130  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46131  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46132  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46133 };
46134 
46140 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46141 {
46142  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46143  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46144  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46145  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46146  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46147  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46148  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46149  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46150 };
46151 
46157 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46158 {
46159  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46160  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46161  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46162  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46163  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46164  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46165  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46166  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46167  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46168  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46169  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46170  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46171  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46172  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46173  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46174  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46175  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46176  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46177  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46178  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46179  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46180  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46181  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46182  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46183  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46184  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46185  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46186  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46187  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46188  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46189  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46190  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46191  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46192  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46193  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46194  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46195 };
46196 
46202 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46203 {
46204  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46205  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46206  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46207  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46208  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46209  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46210  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46211  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46212  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46213  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46214  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46215  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46216  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46217  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46218  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46219  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46220  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46221  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46222  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46223  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46224  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46225  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46226  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46227  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46228  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46229  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46230  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46231  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46232  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46233  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46234  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46235  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46236  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46237  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46238  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46239  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46240  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
46241  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
46242  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
46243  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
46244  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
46245  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
46246  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
46247  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
46248  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
46249  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
46250 };
46251 
46257 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46258 {
46259  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46260  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46261  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46262  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46263  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46264  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46265  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46266  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46267  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46268  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46269  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46270  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46271  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46272  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46273  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46274  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46275  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46276  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46277  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46278  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46279  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46280  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46281  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46282  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46283  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46284  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46285  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46286  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46287  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46288  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46289  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46290  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46291  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46292  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46293  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46294  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46295 };
46296 
46302 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46303 {
46304  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46305  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46306  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46307  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46308  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46309  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46310  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46311  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46312  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46313  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46314  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46315  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46316  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46317  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46318  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46319  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46320  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46321  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46322  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46323  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46324  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46325  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46326  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46327  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46328  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46329  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46330  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46331  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46332  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46333  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46334  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46335  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46336  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46337  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46338  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46339  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46340  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
46341  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
46342  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
46343  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
46344  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
46345  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
46346  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
46347  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
46348  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
46349  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
46350 };
46351 
46357 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46358 {
46359  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46360  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46361  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46362  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46363  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46364  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46365  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46366  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46367  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46368  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46369  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46370  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46371  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46372  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46373  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46374  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46375  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46376  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46377  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46378  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46379  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46380  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46381  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46382  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46383  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46384  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46385  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46386  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46387  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46388  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46389  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46390  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46391  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46392  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46393  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46394  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46395 };
46396 
46402 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46403 {
46404  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46405  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46406  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46407  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46408  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46409  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46410  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46411  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46412  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46413  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46414  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46415  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46416  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46417  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46418  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46419  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46420  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46421  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46422  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46423  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46424  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46425  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46426  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46427  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46428  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46429  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46430  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46431  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46432  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46433  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46434  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46435  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46436  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46437  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46438  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46439  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46440  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
46441  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
46442  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
46443  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
46444  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
46445  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
46446  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
46447  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
46448  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
46449  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
46450 };
46451 
46457 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46458 {
46459  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46460  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46461  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46462  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46463  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46464  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46465  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46466  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46467  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46468  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46469  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46470  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46471  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46472  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46473  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46474  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46475  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46476  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46477  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46478  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46479  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46480  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46481  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46482  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46483  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46484  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46485  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46486  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46487  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46488  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46489  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46490  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46491  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46492  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46493  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46494  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46495 };
46496 
46502 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46503 {
46504  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46505  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46506  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46507  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46508  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46509  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46510  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46511  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46512  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46513  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46514  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46515  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46516  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46517  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46518  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46519  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46520  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46521  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46522  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46523  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46524  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46525  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46526  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46527  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46528  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46529  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46530  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46531  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46532  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46533  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46534  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46535  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46536  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46537  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46538  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46539  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46540  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
46541  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
46542  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
46543  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
46544  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
46545  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
46546  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
46547  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
46548  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
46549  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
46550 };
46551 
46557 static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
46558 {
46559  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
46560  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
46561  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
46562  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
46563  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
46564  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
46565  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
46566  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
46567  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
46568  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
46569  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
46570  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
46571 };
46572 
46577 static const SDL_MemConfig_t SDL_MCU_I3C1_I3C_S_ECC_AGGR_MemEntries[SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
46578 {
46579  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID, 0u,
46580  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_SIZE, 4u,
46581  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ROW_WIDTH, ((bool)false) },
46582  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID, 0u,
46583  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_SIZE, 4u,
46584  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ROW_WIDTH, ((bool)false) },
46585  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID, 0u,
46586  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_SIZE, 4u,
46587  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ROW_WIDTH, ((bool)false) },
46588  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID, 0u,
46589  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_SIZE, 4u,
46590  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ROW_WIDTH, ((bool)false) },
46591  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID, 0u,
46592  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_RAM_SIZE, 4u,
46593  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_ROW_WIDTH, ((bool)false) },
46594  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID, 0u,
46595  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_SIZE, 4u,
46596  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ROW_WIDTH, ((bool)false) },
46597  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID, 0u,
46598  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_SIZE, 4u,
46599  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_ROW_WIDTH, ((bool)false) },
46600  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID, 0u,
46601  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_SIZE, 4u,
46602  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ROW_WIDTH, ((bool)false) },
46603  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID, 0u,
46604  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_SIZE, 4u,
46605  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_ROW_WIDTH, ((bool)false) },
46606 };
46607 
46613 static const SDL_GrpChkConfig_t SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS] =
46614 {
46615  { SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
46616  SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
46617  { SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
46618  SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
46619 };
46620 
46625 static const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES] =
46626 {
46627  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_RAM_ID, 0u,
46628  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_RAM_SIZE, 4u,
46629  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_ROW_WIDTH, ((bool)false) },
46630  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_RAM_ID, 0u,
46631  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_RAM_SIZE, 4u,
46632  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_ROW_WIDTH, ((bool)false) },
46633  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_RAM_ID, 0u,
46634  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_RAM_SIZE, 4u,
46635  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_ROW_WIDTH, ((bool)false) },
46636  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_RAM_ID, 0u,
46637  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_RAM_SIZE, 4u,
46638  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_ROW_WIDTH, ((bool)false) },
46639 };
46640 
46645 static const SDL_MemConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_MemEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
46646 {
46647  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_ID, 0u,
46648  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_SIZE, 4u,
46649  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
46650  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_ID, 0u,
46651  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_SIZE, 4u,
46652  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
46653 };
46654 
46660 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46661 {
46662  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46663  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46664  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46665  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46666  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46667  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46668  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46669  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46670  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46671  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46672 };
46673 
46679 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
46680 {
46681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
46682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
46683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
46684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
46685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
46686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
46687 };
46688 
46694 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
46695 {
46696  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
46697  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
46698  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
46699  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
46700  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
46701  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
46702  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
46703  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
46704  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
46705  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
46706  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
46707  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
46708  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
46709  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
46710  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
46711  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
46712  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
46713  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
46714  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
46715  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
46716  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
46717  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
46718  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
46719  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
46720  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
46721  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
46722  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
46723  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
46724  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
46725  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
46726  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
46727  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
46728  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
46729  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
46730  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
46731  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
46732  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
46733  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
46734  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
46735  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
46736  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
46737  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
46738  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
46739  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
46740  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
46741  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
46742  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
46743  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
46744  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
46745  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
46746  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
46747  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
46748  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
46749  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
46750  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
46751  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
46752  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
46753  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
46754  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
46755  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
46756  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
46757  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
46758  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
46759  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
46760  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
46761  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
46762  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
46763  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
46764  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
46765  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
46766  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
46767  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
46768  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
46769  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
46770  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
46771  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
46772  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
46773  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
46774  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
46775  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
46776  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
46777  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
46778  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
46779  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
46780  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
46781  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
46782  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
46783  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
46784  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
46785  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
46786  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
46787  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
46788  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
46789  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
46790  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
46791  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
46792  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
46793  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
46794  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
46795  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
46796  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
46797  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
46798  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
46799  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
46800  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
46801  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
46802  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
46803  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
46804  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
46805  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
46806  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
46807  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
46808  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
46809  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
46810  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
46811  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
46812  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
46813  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
46814  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
46815  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
46816  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
46817  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
46818  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
46819  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
46820  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
46821  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
46822  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
46823  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
46824  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
46825  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
46826  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
46827  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
46828  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
46829  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
46830  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
46831  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
46832  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
46833  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
46834  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
46835  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
46836  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
46837  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
46838  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
46839  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
46840  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
46841  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
46842  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
46843  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
46844  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
46845  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
46846  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
46847  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
46848  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
46849  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
46850  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
46851  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
46852  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
46853  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
46854  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
46855  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
46856  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
46857  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
46858  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
46859  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
46860  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
46861  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
46862  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
46863  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
46864  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
46865  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
46866  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
46867  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
46868  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
46869  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
46870  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
46871  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
46872  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
46873  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
46874  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
46875  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
46876  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
46877  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
46878  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
46879  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
46880  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
46881  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
46882  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
46883  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
46884  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
46885  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
46886  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
46887  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
46888  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
46889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
46890  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
46891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
46892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
46893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
46894  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
46895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
46896  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
46897  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
46898  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
46899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
46900  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
46901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
46902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
46903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
46904  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
46905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
46906  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
46907  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
46908  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
46909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
46910  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
46911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
46912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
46913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
46914  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
46915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
46916  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
46917  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
46918  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
46919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
46920  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
46921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
46922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
46923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
46924  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
46925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
46926  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
46927  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
46928  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
46929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
46930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
46931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
46932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
46933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
46934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
46935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
46936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
46937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
46938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
46939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
46940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
46941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
46942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
46943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
46944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
46945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
46946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
46947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
46948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
46949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
46950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
46951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
46952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
46953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
46954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
46955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
46956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
46957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
46958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
46959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
46960  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
46961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
46962 };
46963 
46969 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
46970 {
46971  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
46972  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
46973  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
46974  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
46975  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
46976  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
46977  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
46978  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
46979  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
46980  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
46981  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
46982  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
46983  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
46984  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
46985  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
46986  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
46987  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
46988  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
46989  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
46990  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
46991  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
46992  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
46993  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
46994  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
46995  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
46996  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
46997  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
46998  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
46999  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
47000  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
47001  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
47002  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
47003  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
47004  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
47005  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
47006  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
47007  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
47008  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
47009  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
47010  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
47011  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
47012  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
47013  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
47014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
47015  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
47016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
47017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
47018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
47019  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
47020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
47021  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
47022  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
47023  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
47024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
47025  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
47026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
47027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
47028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
47029  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
47030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
47031  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
47032  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
47033  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
47034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
47035  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
47036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
47037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
47038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
47039  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
47040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
47041  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
47042  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
47043  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
47044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
47045  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
47046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
47047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
47048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
47049  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
47050  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
47051  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
47052  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
47053  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
47054  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
47055  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
47056  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
47057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
47058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
47059  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
47060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
47061  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
47062  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
47063  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
47064  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
47065  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
47066  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
47067  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
47068  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
47069  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
47070  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
47071  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
47072  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
47073  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
47074  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
47075  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
47076  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
47077  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
47078  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
47079  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
47080  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
47081  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
47082  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
47083  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
47084  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
47085  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
47086  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
47087  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
47088  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
47089  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
47090  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
47091  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
47092  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
47093  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
47094  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
47095  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
47096  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
47097  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
47098  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
47099  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
47100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
47101  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
47102  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
47103  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
47104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
47105  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
47106  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
47107  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
47108  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
47109  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
47110  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
47111  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
47112  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
47113  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
47114  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
47115  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
47116  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
47117  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
47118  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
47119  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
47120  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
47121  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
47122  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
47123  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
47124  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
47125  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
47126  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
47127  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
47128  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
47129  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
47130  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
47131  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
47132  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
47133  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
47134  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
47135  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
47136  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
47137  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
47138  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
47139  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
47140  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
47141  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
47142  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
47143  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
47144  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
47145  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
47146  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
47147  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
47148  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
47149  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
47150  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
47151  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
47152  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
47153  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
47154  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
47155  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
47156  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
47157  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
47158  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
47159  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
47160  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
47161  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
47162  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
47163  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
47164  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
47165  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
47166  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
47167  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
47168  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
47169  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
47170  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
47171  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
47172  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
47173  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
47174  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
47175  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
47176  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
47177  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
47178  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
47179  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
47180  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
47181  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
47182  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
47183  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
47184  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
47185  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
47186  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
47187  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
47188  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
47189  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
47190  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
47191  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
47192  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
47193  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
47194  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
47195  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
47196  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
47197  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
47198  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
47199  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
47200  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
47201  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
47202  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
47203  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
47204  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
47205  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
47206  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
47207  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
47208  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
47209  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
47210  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
47211  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
47212  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
47213  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
47214  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
47215  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
47216  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
47217  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
47218  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
47219  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
47220  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
47221  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
47222  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
47223  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
47224  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
47225  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
47226  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
47227  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
47228  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
47229  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
47230  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
47231  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
47232  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
47233  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
47234  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
47235  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
47236  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
47237  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
47238  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
47239  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
47240  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
47241  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
47242  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
47243  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
47244  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
47245  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
47246  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
47247  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
47248  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
47249  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
47250  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
47251  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
47252  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
47253  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
47254  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
47255  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
47256  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
47257  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
47258  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
47259  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
47260  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
47261  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
47262  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
47263  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
47264  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
47265  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
47266  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
47267  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
47268  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
47269  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
47270  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
47271  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
47272  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
47273  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
47274  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
47275  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
47276  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
47277  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
47278  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
47279  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
47280  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
47281  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
47282  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
47283  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
47284  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
47285  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
47286  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
47287  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
47288  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
47289  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
47290  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
47291  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
47292  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
47293  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
47294  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
47295  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
47296  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
47297  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
47298  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
47299  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
47300  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
47301  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
47302  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
47303  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
47304  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
47305  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
47306  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
47307  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
47308  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
47309  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
47310  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
47311  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
47312  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
47313  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
47314  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
47315  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
47316  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
47317  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
47318  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
47319  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
47320  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
47321  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
47322  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
47323  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
47324  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
47325  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
47326  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
47327  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
47328  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
47329  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
47330  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
47331  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
47332  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
47333  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
47334  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
47335  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
47336  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
47337  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
47338  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
47339  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
47340  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
47341  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
47342  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
47343  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
47344  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
47345  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
47346  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
47347  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
47348  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
47349  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
47350  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
47351  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
47352  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
47353  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
47354  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
47355  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
47356  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
47357  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
47358  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
47359  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
47360  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
47361  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
47362  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
47363  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
47364  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
47365  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
47366  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
47367  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
47368  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
47369  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
47370  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
47371  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
47372  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
47373  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
47374  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
47375  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
47376  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
47377  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
47378  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
47379  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
47380  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
47381  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
47382  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
47383  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
47384  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
47385  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
47386  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
47387  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
47388  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
47389  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
47390  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
47391  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
47392  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
47393  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
47394  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
47395  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
47396  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
47397  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
47398  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
47399  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
47400  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
47401  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
47402  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
47403  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
47404  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
47405  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
47406  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
47407  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
47408  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
47409  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
47410  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
47411  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
47412  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
47413  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
47414  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
47415  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
47416  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
47417  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
47418  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
47419  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
47420  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
47421  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
47422  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
47423  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
47424  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
47425  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
47426  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
47427  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
47428  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
47429  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
47430  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
47431  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
47432  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
47433  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
47434  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
47435  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
47436  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
47437  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
47438  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
47439  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
47440  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
47441  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
47442  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
47443  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
47444  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
47445  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
47446  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
47447  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
47448  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
47449  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
47450  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
47451  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
47452  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
47453  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
47454  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
47455  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
47456  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
47457  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
47458  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
47459  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
47460  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
47461  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
47462  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
47463  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
47464  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
47465  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
47466  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
47467  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
47468  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
47469  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
47470  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
47471  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
47472  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
47473  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
47474  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
47475  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
47476  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
47477  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
47478  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
47479  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
47480  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
47481  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
47482  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
47483 };
47484 
47490 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
47491 {
47492  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
47493  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
47494  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
47495  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
47496  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
47497  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
47498  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
47499  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
47500  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
47501  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
47502  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
47503  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
47504  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
47505  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
47506  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
47507  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
47508  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
47509  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
47510  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
47511  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
47512  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
47513  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
47514  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
47515  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
47516  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
47517  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
47518  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
47519  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
47520  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
47521  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
47522  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
47523  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
47524  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
47525  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
47526  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
47527  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
47528  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
47529  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
47530  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
47531  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
47532  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
47533  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
47534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
47535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
47536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
47537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
47538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
47539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
47540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
47541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
47542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
47543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
47544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
47545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
47546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
47547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
47548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
47549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
47550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
47551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
47552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
47553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
47554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
47555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
47556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
47557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
47558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
47559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
47560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
47561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
47562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
47563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
47564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
47565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
47566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
47567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
47568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
47569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
47570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
47571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
47572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
47573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
47574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
47575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
47576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
47577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
47578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
47579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
47580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
47581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
47582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
47583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
47584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
47585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
47586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
47587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
47588  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
47589  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
47590  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
47591  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
47592  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
47593  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
47594  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
47595  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
47596  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
47597  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
47598  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
47599  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
47600  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
47601  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
47602  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
47603  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
47604  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
47605  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
47606  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
47607  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
47608  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
47609  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
47610  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
47611  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
47612  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
47613  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
47614  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
47615  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
47616  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
47617  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
47618  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
47619  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
47620  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
47621  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
47622  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
47623  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
47624  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
47625  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
47626  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
47627  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
47628  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
47629  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
47630  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
47631  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
47632  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
47633  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
47634  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
47635  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
47636  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
47637  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
47638  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
47639  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
47640  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
47641  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
47642  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
47643  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
47644  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
47645  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
47646  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
47647  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
47648  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
47649  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
47650  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
47651  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
47652  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
47653  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
47654  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
47655  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
47656  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
47657  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
47658  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
47659  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
47660  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
47661  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
47662  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
47663  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
47664  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
47665  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
47666  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
47667  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
47668  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
47669  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
47670  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
47671  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
47672  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
47673  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
47674  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
47675  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
47676  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
47677  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
47678  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
47679  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
47680  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
47681  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
47682  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
47683  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
47684  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
47685  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
47686  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
47687  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
47688  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
47689  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
47690  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
47691  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
47692  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
47693  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
47694  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
47695  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
47696  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
47697  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
47698  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
47699  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
47700  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
47701  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
47702  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
47703  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
47704  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
47705  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
47706  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
47707  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
47708  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
47709  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
47710  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
47711  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
47712  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
47713  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
47714  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
47715  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
47716  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
47717  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
47718  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
47719  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
47720  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
47721  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
47722  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
47723  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
47724  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
47725  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
47726  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
47727  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
47728  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
47729  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
47730  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
47731  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
47732  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
47733  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
47734  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
47735  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
47736  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
47737  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
47738  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
47739  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
47740  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
47741  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
47742  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
47743  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
47744  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
47745  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
47746  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
47747  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
47748  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
47749  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
47750  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
47751  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
47752  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
47753  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
47754  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
47755  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
47756  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
47757  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
47758  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
47759  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
47760  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
47761  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
47762  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
47763  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
47764  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
47765  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
47766  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
47767  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
47768  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
47769  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
47770  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
47771  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
47772  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
47773  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
47774  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
47775  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
47776  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
47777  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
47778  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
47779  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
47780  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
47781  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
47782  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
47783  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
47784  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
47785  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
47786  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
47787  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
47788  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
47789  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
47790  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
47791  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
47792  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
47793  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
47794  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
47795  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
47796  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
47797  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
47798  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
47799  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
47800  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
47801  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
47802  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
47803  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
47804  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
47805  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
47806  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
47807  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
47808  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
47809  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
47810  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
47811  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
47812  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
47813  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
47814  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
47815  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
47816  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
47817  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
47818  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
47819  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
47820  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
47821  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
47822  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
47823  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
47824  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
47825  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
47826  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
47827  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
47828  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
47829  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
47830  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
47831  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
47832  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
47833  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
47834  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
47835  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
47836  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
47837  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
47838  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
47839  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
47840  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
47841  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
47842  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
47843  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
47844  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
47845  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
47846  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
47847  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
47848  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
47849  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
47850  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
47851  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
47852  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
47853  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
47854  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
47855  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
47856  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
47857  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
47858  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
47859  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
47860  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
47861  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
47862  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
47863  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
47864  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
47865  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
47866  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
47867  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
47868  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
47869  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
47870  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
47871  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
47872  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
47873  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
47874  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
47875  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
47876  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
47877  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
47878  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
47879  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
47880  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
47881  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
47882  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
47883  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
47884  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
47885  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
47886  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
47887  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
47888  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
47889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
47890  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
47891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
47892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
47893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
47894  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
47895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
47896  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
47897  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
47898  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
47899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
47900  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
47901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
47902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
47903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
47904  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
47905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
47906  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
47907  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
47908  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
47909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
47910  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
47911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
47912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
47913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
47914  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
47915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
47916  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
47917  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
47918  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
47919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
47920  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
47921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
47922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
47923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
47924  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
47925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
47926  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
47927  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
47928  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
47929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
47930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
47931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
47932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
47933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
47934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
47935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
47936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
47937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
47938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
47939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
47940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
47941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
47942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
47943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
47944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
47945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
47946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
47947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
47948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
47949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
47950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
47951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
47952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
47953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
47954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
47955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
47956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
47957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
47958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
47959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
47960  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
47961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
47962  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
47963  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
47964  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
47965  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
47966  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
47967  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
47968  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
47969  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
47970  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
47971  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
47972  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
47973  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
47974  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
47975  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
47976  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
47977  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
47978  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
47979  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
47980  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
47981  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
47982  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
47983  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
47984  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
47985  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
47986  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
47987  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
47988  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
47989  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
47990  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
47991  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
47992  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
47993  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
47994  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
47995  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
47996  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
47997  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
47998  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
47999  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
48000  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
48001  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
48002  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
48003  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
48004 };
48005 
48011 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
48012 {
48013  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
48014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
48015  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
48016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
48017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
48018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
48019  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
48020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
48021  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
48022  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
48023  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
48024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
48025  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
48026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
48027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
48028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
48029  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
48030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
48031  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
48032  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
48033  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
48034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
48035  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
48036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
48037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
48038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
48039  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
48040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
48041  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
48042  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
48043  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
48044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
48045  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
48046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
48047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
48048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
48049  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
48050  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
48051  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
48052  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
48053  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
48054  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
48055  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
48056  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
48057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
48058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
48059  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
48060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
48061  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
48062  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
48063  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
48064  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
48065  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
48066  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
48067  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
48068  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
48069  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
48070  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
48071  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
48072  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
48073  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
48074  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
48075  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
48076  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
48077  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
48078  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
48079  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
48080  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
48081  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
48082  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
48083  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
48084  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
48085  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
48086  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
48087  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
48088  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
48089  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
48090  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
48091  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
48092  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
48093  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
48094  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
48095  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
48096  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
48097  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
48098  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
48099  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
48100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
48101  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
48102  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
48103  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
48104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
48105  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
48106  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
48107  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
48108  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
48109  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
48110  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
48111  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
48112  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
48113  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
48114  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
48115  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
48116  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
48117  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
48118  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
48119  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
48120  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
48121  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
48122  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
48123  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
48124  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
48125  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
48126  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
48127  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
48128  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
48129  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
48130  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
48131  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
48132  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
48133  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
48134  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
48135  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
48136  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
48137  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
48138  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
48139  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
48140  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
48141  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
48142  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
48143  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
48144  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
48145  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
48146  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
48147  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
48148  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
48149  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
48150  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
48151  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
48152  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
48153  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
48154  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
48155  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
48156  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
48157  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
48158  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
48159  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
48160  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
48161  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
48162  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
48163  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
48164  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
48165  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
48166  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
48167  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
48168  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
48169  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
48170  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
48171  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
48172  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
48173  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
48174  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
48175  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
48176  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
48177  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
48178  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
48179  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
48180  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
48181  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
48182  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
48183  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
48184  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
48185  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
48186  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
48187  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
48188  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
48189  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
48190  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
48191  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
48192  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
48193  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
48194  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
48195  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
48196  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
48197  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
48198  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
48199  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
48200  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
48201  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
48202  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
48203  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
48204  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
48205  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
48206  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
48207  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
48208  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
48209  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
48210  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
48211  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
48212  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
48213  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
48214  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
48215  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
48216  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
48217  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
48218  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
48219  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
48220  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
48221  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
48222  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
48223  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
48224  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
48225  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
48226  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
48227  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
48228  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
48229  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
48230  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
48231  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
48232  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
48233  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
48234  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
48235  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
48236  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
48237  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
48238  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
48239  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
48240  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
48241  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
48242  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
48243  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
48244  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
48245  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
48246  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
48247  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
48248  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
48249  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
48250  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
48251  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
48252  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
48253  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
48254  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
48255  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
48256  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
48257  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
48258  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
48259  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
48260  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
48261  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
48262  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
48263  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
48264  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
48265  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
48266  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
48267  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
48268  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
48269  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
48270  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
48271  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
48272  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
48273  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
48274  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
48275  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
48276  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
48277  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
48278  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
48279  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
48280  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
48281  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
48282  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
48283  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
48284  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
48285  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
48286  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
48287  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
48288  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
48289  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
48290  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
48291  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
48292  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
48293  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
48294  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
48295  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
48296  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
48297  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
48298  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
48299  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
48300  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
48301  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
48302  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
48303  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
48304  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
48305  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
48306  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
48307  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
48308  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
48309  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
48310  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
48311  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
48312  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
48313  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
48314  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
48315  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
48316  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
48317  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
48318  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
48319  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
48320  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
48321  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
48322  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
48323  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
48324  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
48325  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
48326  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
48327  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
48328  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
48329  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
48330  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
48331  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
48332  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
48333  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
48334  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
48335  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
48336  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
48337  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
48338  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
48339  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
48340  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
48341  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
48342  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
48343  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
48344  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
48345  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
48346  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
48347  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
48348  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
48349  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
48350  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
48351  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
48352  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
48353  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
48354  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
48355  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
48356  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
48357  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
48358  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
48359  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
48360  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
48361  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
48362  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
48363  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
48364  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
48365  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
48366  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
48367  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
48368  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
48369  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
48370  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
48371  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
48372  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
48373  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
48374  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
48375  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
48376  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
48377  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
48378  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
48379  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
48380  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
48381  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
48382  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
48383  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
48384  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
48385  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
48386  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
48387  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
48388  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
48389  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
48390  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
48391  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
48392  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
48393  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
48394  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
48395  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
48396  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
48397  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
48398  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
48399  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
48400  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
48401  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
48402  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
48403  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
48404  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
48405  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
48406  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
48407  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
48408  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
48409  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
48410  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
48411  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
48412  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
48413  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
48414  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
48415  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
48416  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
48417  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
48418  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
48419  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
48420  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
48421  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
48422  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
48423  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
48424  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
48425  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
48426  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
48427  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
48428  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
48429  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
48430  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
48431  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
48432  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
48433  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
48434  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
48435  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
48436  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
48437  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
48438  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
48439  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
48440  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
48441  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
48442  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
48443  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
48444  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
48445  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
48446  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
48447  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
48448  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
48449  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
48450  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
48451  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
48452  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
48453  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
48454  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
48455  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
48456  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
48457  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
48458  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
48459  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
48460  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
48461  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
48462  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
48463  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
48464  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
48465  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
48466  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
48467  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
48468  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
48469  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
48470  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
48471  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
48472  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
48473  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
48474  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
48475  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
48476  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
48477  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
48478  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
48479  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
48480  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
48481  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
48482  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
48483  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
48484  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
48485  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
48486  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
48487  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
48488  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
48489  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
48490  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
48491  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
48492  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
48493  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
48494  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
48495  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
48496  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
48497  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
48498  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
48499  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
48500  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
48501  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
48502  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
48503  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
48504  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
48505  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
48506  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
48507  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
48508  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
48509  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
48510  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
48511  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
48512  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
48513  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
48514  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
48515  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
48516  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
48517  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
48518  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
48519  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
48520  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
48521  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
48522  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
48523  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
48524  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
48525 };
48526 
48532 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
48533 {
48534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
48535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
48536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
48537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
48538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
48539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
48540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
48541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
48542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
48543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
48544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
48545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
48546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
48547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
48548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
48549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
48550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
48551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
48552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
48553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
48554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
48555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
48556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
48557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
48558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
48559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
48560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
48561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
48562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
48563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
48564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
48565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
48566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
48567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
48568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
48569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
48570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
48571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
48572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
48573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
48574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
48575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
48576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
48577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
48578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
48579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
48580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
48581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
48582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
48583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
48584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
48585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
48586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
48587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
48588  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
48589  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
48590  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
48591  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
48592  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
48593  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
48594  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
48595  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
48596  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
48597  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
48598  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
48599  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
48600  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
48601  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
48602  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
48603  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
48604  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
48605  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
48606  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
48607  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
48608  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
48609  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
48610  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
48611  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
48612  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
48613  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
48614  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
48615  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
48616  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
48617  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
48618  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
48619  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
48620  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
48621  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
48622  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
48623  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
48624  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
48625  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
48626  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
48627  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
48628  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
48629  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
48630  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
48631  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
48632  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
48633  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
48634  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
48635  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
48636  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
48637  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
48638  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
48639  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
48640  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
48641  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
48642  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
48643  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
48644  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
48645  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
48646  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
48647  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
48648  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
48649  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
48650  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
48651  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
48652  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
48653  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
48654  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
48655  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
48656  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
48657  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
48658  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
48659  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
48660  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
48661  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
48662  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
48663  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
48664  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
48665  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
48666  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
48667  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
48668  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
48669  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
48670  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
48671  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
48672  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
48673  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
48674  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
48675  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
48676  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
48677  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
48678  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
48679  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
48680  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
48681  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
48682  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
48683  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
48684  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
48685  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
48686  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
48687  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
48688  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
48689  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
48690  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
48691  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
48692  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
48693  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
48694  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
48695  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
48696  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
48697  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
48698  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
48699  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
48700  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
48701  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
48702  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
48703  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
48704  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
48705  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
48706  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
48707  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
48708  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
48709  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
48710  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
48711  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
48712  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
48713  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
48714  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
48715  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
48716  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
48717  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
48718  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
48719  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
48720  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
48721  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
48722  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
48723  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
48724  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
48725  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
48726  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
48727  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
48728  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
48729  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
48730  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
48731  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
48732  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
48733  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
48734  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
48735  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
48736  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
48737  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
48738  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
48739  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
48740  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
48741  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
48742  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
48743  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
48744  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
48745  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
48746  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
48747  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
48748  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
48749  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
48750  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
48751  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
48752  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
48753  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
48754  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
48755  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
48756  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
48757  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
48758  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
48759  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
48760  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
48761  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
48762  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
48763  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
48764  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
48765  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
48766  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
48767  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
48768  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
48769  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
48770  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
48771  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
48772  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
48773  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
48774  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
48775  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
48776  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
48777  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
48778  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
48779  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
48780  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
48781  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
48782  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
48783  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
48784  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
48785  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
48786  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
48787  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
48788  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
48789  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
48790  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
48791  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
48792  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
48793  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
48794  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
48795  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
48796  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
48797  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
48798  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
48799  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
48800  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
48801  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
48802  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
48803  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
48804  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
48805  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
48806  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
48807  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
48808  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
48809  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
48810  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
48811  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
48812  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
48813  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
48814  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
48815  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
48816  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
48817  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
48818  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
48819  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
48820  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
48821  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
48822  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
48823  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
48824  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
48825  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
48826  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
48827  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
48828  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
48829  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
48830  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
48831  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
48832  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
48833  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
48834  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
48835  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
48836  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
48837  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
48838  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
48839  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
48840  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
48841  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
48842  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
48843  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
48844  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
48845  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
48846  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
48847  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
48848  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
48849  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
48850  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
48851  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
48852  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
48853  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
48854  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
48855  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
48856  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
48857  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
48858  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
48859  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
48860  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
48861  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
48862  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
48863  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
48864  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
48865  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
48866  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
48867  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
48868  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
48869  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
48870  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
48871  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
48872  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
48873  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
48874  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
48875  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
48876  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
48877  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
48878  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
48879  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
48880  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
48881  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
48882  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
48883  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
48884  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
48885  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
48886  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
48887  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
48888  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
48889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
48890  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
48891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
48892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
48893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
48894  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
48895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
48896  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
48897  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
48898  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
48899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
48900  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
48901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
48902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
48903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
48904  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
48905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
48906  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
48907  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
48908  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_CHECKER_TYPE,
48909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_WIDTH },
48910  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_CHECKER_TYPE,
48911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_WIDTH },
48912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_CHECKER_TYPE,
48913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_WIDTH },
48914  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_CHECKER_TYPE,
48915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_WIDTH },
48916  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_CHECKER_TYPE,
48917  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_WIDTH },
48918  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_CHECKER_TYPE,
48919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_WIDTH },
48920  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_CHECKER_TYPE,
48921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_WIDTH },
48922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_CHECKER_TYPE,
48923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_WIDTH },
48924  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_CHECKER_TYPE,
48925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_WIDTH },
48926  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_CHECKER_TYPE,
48927  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_WIDTH },
48928  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_CHECKER_TYPE,
48929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_WIDTH },
48930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_CHECKER_TYPE,
48931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_WIDTH },
48932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_CHECKER_TYPE,
48933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_WIDTH },
48934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_CHECKER_TYPE,
48935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_WIDTH },
48936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_CHECKER_TYPE,
48937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_WIDTH },
48938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_CHECKER_TYPE,
48939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_WIDTH },
48940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_CHECKER_TYPE,
48941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_WIDTH },
48942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_CHECKER_TYPE,
48943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_WIDTH },
48944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_CHECKER_TYPE,
48945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_WIDTH },
48946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_CHECKER_TYPE,
48947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_WIDTH },
48948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_CHECKER_TYPE,
48949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_WIDTH },
48950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_CHECKER_TYPE,
48951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_WIDTH },
48952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_CHECKER_TYPE,
48953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_WIDTH },
48954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_CHECKER_TYPE,
48955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_WIDTH },
48956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_CHECKER_TYPE,
48957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_WIDTH },
48958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_CHECKER_TYPE,
48959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_WIDTH },
48960  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_CHECKER_TYPE,
48961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_WIDTH },
48962  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_CHECKER_TYPE,
48963  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_WIDTH },
48964  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_CHECKER_TYPE,
48965  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_WIDTH },
48966  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_CHECKER_TYPE,
48967  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_WIDTH },
48968  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_CHECKER_TYPE,
48969  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_WIDTH },
48970  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_CHECKER_TYPE,
48971  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_WIDTH },
48972  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_CHECKER_TYPE,
48973  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_WIDTH },
48974  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_CHECKER_TYPE,
48975  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_WIDTH },
48976  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_CHECKER_TYPE,
48977  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_WIDTH },
48978  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_CHECKER_TYPE,
48979  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_WIDTH },
48980  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_CHECKER_TYPE,
48981  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_WIDTH },
48982  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_CHECKER_TYPE,
48983  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_WIDTH },
48984  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_CHECKER_TYPE,
48985  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_WIDTH },
48986  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_CHECKER_TYPE,
48987  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_WIDTH },
48988  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_CHECKER_TYPE,
48989  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_WIDTH },
48990  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_CHECKER_TYPE,
48991  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_WIDTH },
48992  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_CHECKER_TYPE,
48993  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_WIDTH },
48994  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_CHECKER_TYPE,
48995  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_WIDTH },
48996  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_CHECKER_TYPE,
48997  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_WIDTH },
48998  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_CHECKER_TYPE,
48999  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_WIDTH },
49000  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_CHECKER_TYPE,
49001  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_WIDTH },
49002  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_CHECKER_TYPE,
49003  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_WIDTH },
49004  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_CHECKER_TYPE,
49005  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_WIDTH },
49006  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_CHECKER_TYPE,
49007  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_WIDTH },
49008  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_CHECKER_TYPE,
49009  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_WIDTH },
49010  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_CHECKER_TYPE,
49011  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_WIDTH },
49012  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_CHECKER_TYPE,
49013  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_WIDTH },
49014  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_CHECKER_TYPE,
49015  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_WIDTH },
49016  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_CHECKER_TYPE,
49017  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_WIDTH },
49018  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_CHECKER_TYPE,
49019  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_WIDTH },
49020  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_CHECKER_TYPE,
49021  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_WIDTH },
49022  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_CHECKER_TYPE,
49023  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_WIDTH },
49024  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_CHECKER_TYPE,
49025  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_WIDTH },
49026  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_CHECKER_TYPE,
49027  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_WIDTH },
49028  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_CHECKER_TYPE,
49029  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_WIDTH },
49030  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_CHECKER_TYPE,
49031  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_WIDTH },
49032  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_CHECKER_TYPE,
49033  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_WIDTH },
49034  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_CHECKER_TYPE,
49035  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_WIDTH },
49036  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_CHECKER_TYPE,
49037  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_WIDTH },
49038  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_CHECKER_TYPE,
49039  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_WIDTH },
49040  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_CHECKER_TYPE,
49041  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_WIDTH },
49042  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_CHECKER_TYPE,
49043  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_WIDTH },
49044  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_CHECKER_TYPE,
49045  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_WIDTH },
49046 };
49047 
49053 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
49054 {
49055  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
49056  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
49057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
49058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
49059  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
49060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
49061  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
49062  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
49063 };
49064 
49070 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
49071 {
49072  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
49073  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
49074  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
49075  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
49076  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
49077  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
49078  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
49079  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
49080  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
49081  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
49082  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
49083  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
49084  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
49085  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
49086  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
49087  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
49088  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
49089  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
49090  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
49091  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
49092  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
49093  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
49094  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
49095  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
49096  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
49097  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
49098  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
49099  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
49100  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
49101  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
49102 };
49103 
49109 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
49110 {
49111  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
49112  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
49113  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
49114  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
49115  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
49116  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
49117 };
49118 
49124 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
49125 {
49126  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
49127  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
49128  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
49129  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
49130  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
49131  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
49132  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
49133  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
49134  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
49135  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
49136  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
49137  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
49138  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
49139  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
49140  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
49141  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
49142  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
49143  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
49144  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
49145  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
49146  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
49147  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
49148  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
49149  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
49150  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
49151  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
49152  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
49153  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
49154 };
49155 
49161 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
49162 {
49163  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
49164  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
49165  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
49166  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
49167  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
49168  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
49169  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
49170  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
49171  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
49172  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
49173  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
49174  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
49175  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
49176  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
49177  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
49178  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
49179  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
49180  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
49181  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
49182  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
49183  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
49184  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
49185  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
49186  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
49187  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
49188  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
49189  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
49190  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
49191  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
49192  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
49193 };
49194 
49200 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
49201 {
49202  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
49203  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
49204  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
49205  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
49206  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
49207  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
49208  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
49209  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
49210 };
49211 
49217 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
49218 {
49219  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
49220  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
49221 };
49222 
49228 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
49229 {
49230  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
49231  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
49232  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
49233  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
49234  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
49235  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
49236  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
49237  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
49238  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
49239  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
49240  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
49241  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
49242  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
49243  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
49244  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
49245  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
49246  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
49247  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
49248  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
49249  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
49250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
49251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
49252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
49253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
49254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
49255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
49256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
49257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
49258  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
49259  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
49260 };
49261 
49267 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
49268 {
49269  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
49270  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
49271  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
49272  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
49273  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
49274  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
49275 };
49276 
49282 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
49283 {
49284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
49285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
49286  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
49287  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
49288  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
49289  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
49290 };
49291 
49297 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
49298 {
49299  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
49300  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
49301  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
49302  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
49303  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
49304  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
49305  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
49306  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
49307  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
49308  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
49309  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
49310  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
49311  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
49312  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
49313  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
49314  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
49315  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
49316  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
49317  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
49318  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
49319  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
49320  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
49321  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
49322  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
49323  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
49324  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
49325  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
49326  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
49327  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
49328  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
49329  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
49330  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
49331  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
49332  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
49333  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
49334  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
49335  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
49336  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
49337  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
49338  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
49339  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
49340  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
49341  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
49342  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
49343  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
49344  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
49345  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
49346  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
49347  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
49348  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
49349  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
49350  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
49351  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
49352  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
49353  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
49354  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
49355  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
49356  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
49357  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
49358  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
49359  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
49360  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
49361  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
49362  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
49363  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
49364  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
49365  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
49366  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
49367  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
49368  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
49369  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
49370  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
49371  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
49372  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
49373  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
49374  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
49375  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
49376  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
49377  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
49378  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
49379  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
49380  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
49381  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
49382  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
49383  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
49384  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
49385  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
49386  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
49387  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
49388  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
49389  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
49390  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
49391  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
49392  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
49393  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
49394  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
49395  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
49396  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
49397  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
49398  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
49399  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
49400  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
49401  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
49402  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
49403  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
49404  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
49405  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
49406  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
49407  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
49408  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
49409  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
49410  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
49411  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
49412  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
49413  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
49414  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
49415  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
49416  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
49417  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
49418  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
49419  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
49420  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
49421  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
49422  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
49423  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
49424  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
49425  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
49426  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
49427  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
49428  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
49429  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
49430  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
49431  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
49432  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
49433  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
49434  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
49435  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
49436  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
49437  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
49438  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
49439  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
49440  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
49441  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
49442  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
49443  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
49444  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
49445  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
49446  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
49447  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
49448  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
49449  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
49450  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
49451  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
49452  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
49453  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
49454  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
49455  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
49456  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
49457  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
49458  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
49459  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
49460  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
49461  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
49462  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
49463  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
49464  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
49465  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
49466  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
49467  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
49468  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
49469  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
49470  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
49471  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
49472  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
49473  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
49474  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
49475  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
49476  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
49477  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
49478  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
49479  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
49480  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
49481  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
49482  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
49483  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
49484  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
49485  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
49486  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
49487  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
49488  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
49489  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
49490  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
49491  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
49492  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
49493  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
49494  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
49495  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
49496  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
49497  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
49498  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
49499  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
49500  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
49501  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
49502  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
49503  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
49504  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
49505  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
49506  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
49507  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
49508  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
49509  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
49510  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
49511  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
49512  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
49513  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
49514  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
49515  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
49516  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
49517  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
49518  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
49519  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
49520  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
49521  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
49522  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
49523  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
49524  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
49525  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
49526  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
49527  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
49528  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
49529  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
49530  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
49531  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
49532  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
49533  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
49534  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
49535  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
49536  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
49537  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
49538  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
49539  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
49540  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
49541  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
49542  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
49543  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
49544  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
49545  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
49546  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
49547  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
49548  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
49549  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
49550  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
49551  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
49552  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
49553  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
49554  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
49555  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
49556  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
49557  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
49558  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
49559  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
49560  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
49561  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
49562  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
49563  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
49564  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
49565  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
49566  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
49567  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
49568  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
49569  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
49570  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
49571  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
49572  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
49573  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
49574  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
49575  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
49576  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
49577  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
49578  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
49579  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
49580  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
49581  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
49582  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
49583  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
49584  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
49585  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
49586  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
49587  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
49588  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
49589  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
49590  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
49591  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
49592  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
49593  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
49594  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
49595  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
49596  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
49597  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
49598  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
49599  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
49600  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
49601  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
49602  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
49603  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
49604  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
49605  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
49606  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
49607  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
49608  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
49609  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
49610  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
49611  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
49612  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
49613  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
49614  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
49615  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
49616  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
49617  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
49618  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
49619  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
49620  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
49621  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
49622  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
49623  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
49624  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
49625  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
49626  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
49627  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
49628  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
49629  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
49630  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
49631  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
49632  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
49633  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
49634  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
49635  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
49636  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
49637  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
49638  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
49639  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
49640  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
49641  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
49642  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
49643  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
49644  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
49645  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
49646  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
49647  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
49648  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
49649  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
49650  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
49651  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
49652  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
49653  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
49654  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
49655  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
49656  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
49657  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
49658  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
49659  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
49660  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
49661  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
49662  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
49663  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
49664  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
49665  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
49666  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
49667  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
49668  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
49669  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
49670  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
49671  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
49672  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
49673  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
49674  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
49675  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
49676  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
49677  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
49678  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
49679  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
49680  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
49681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
49682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
49683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
49684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
49685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
49686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
49687  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
49688  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
49689  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
49690  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
49691  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
49692  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
49693  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
49694  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
49695  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
49696  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
49697  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
49698  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
49699  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
49700  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
49701  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
49702  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
49703  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
49704  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
49705  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
49706  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
49707  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
49708  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
49709  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
49710  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
49711  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
49712  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
49713  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
49714  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
49715  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
49716  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
49717  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
49718  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
49719  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
49720  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
49721  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
49722  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
49723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
49724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
49725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
49726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
49727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
49728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
49729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
49730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
49731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
49732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
49733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
49734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
49735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
49736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
49737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
49738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
49739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
49740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
49741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
49742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
49743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
49744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
49745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
49746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
49747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
49748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
49749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
49750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
49751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
49752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
49753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
49754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
49755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
49756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
49757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
49758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
49759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
49760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
49761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
49762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
49763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
49764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
49765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
49766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
49767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
49768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
49769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
49770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
49771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
49772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
49773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
49774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
49775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
49776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
49777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
49778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
49779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
49780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
49781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
49782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
49783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
49784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
49785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
49786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
49787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
49788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
49789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
49790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
49791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
49792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
49793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
49794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
49795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
49796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
49797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
49798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
49799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
49800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
49801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
49802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
49803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
49804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
49805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
49806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
49807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
49808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
49809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
49810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
49811 };
49812 
49818 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
49819 {
49820  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
49821  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
49822  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
49823  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
49824  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
49825  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
49826  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
49827  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
49828  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
49829  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
49830  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
49831  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
49832  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
49833  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
49834  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
49835  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
49836  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
49837  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
49838  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
49839  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
49840  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
49841  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
49842  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
49843  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
49844  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
49845  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
49846  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
49847  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
49848  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
49849  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
49850  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
49851  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
49852  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
49853  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
49854  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
49855  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
49856  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
49857  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
49858  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
49859  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
49860  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
49861  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
49862  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
49863  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
49864  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
49865  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
49866  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
49867  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
49868  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
49869  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
49870  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
49871  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
49872  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
49873  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
49874  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
49875  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
49876  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
49877  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
49878  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
49879  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
49880  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
49881  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
49882  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
49883  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
49884  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
49885  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
49886  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
49887  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
49888  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
49889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
49890  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
49891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
49892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
49893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
49894  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
49895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
49896  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
49897  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
49898  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
49899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
49900  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
49901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
49902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
49903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
49904  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
49905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
49906  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
49907  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
49908  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
49909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
49910  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
49911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
49912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
49913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
49914  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
49915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
49916  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
49917  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
49918  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
49919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
49920  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
49921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
49922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
49923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
49924  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
49925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
49926  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
49927  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
49928  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
49929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
49930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
49931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
49932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
49933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
49934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
49935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
49936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
49937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
49938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
49939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
49940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
49941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
49942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
49943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
49944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
49945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
49946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
49947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
49948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
49949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
49950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
49951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
49952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
49953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
49954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
49955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
49956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
49957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
49958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
49959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
49960  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
49961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
49962  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
49963  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
49964  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
49965  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
49966  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
49967  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
49968  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
49969  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
49970  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
49971  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
49972  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
49973  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
49974  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
49975  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
49976  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
49977  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
49978  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
49979  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
49980  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
49981  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
49982  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
49983  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
49984  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
49985  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
49986  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
49987  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
49988  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
49989  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
49990  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
49991  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
49992  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
49993  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
49994  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
49995  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
49996  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
49997  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
49998  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
49999  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
50000  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
50001  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
50002  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
50003  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
50004  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
50005  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
50006  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
50007  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
50008  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
50009  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
50010  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
50011  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
50012  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
50013  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
50014  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
50015  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
50016  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
50017  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
50018  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
50019  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
50020  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
50021  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
50022  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
50023  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
50024  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
50025  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
50026  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
50027  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
50028  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
50029  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
50030  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
50031  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
50032  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
50033  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
50034  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
50035  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
50036  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
50037  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
50038  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
50039  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
50040  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
50041  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
50042  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
50043  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
50044  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
50045  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
50046  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
50047  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
50048  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
50049  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
50050  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
50051  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
50052  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
50053  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
50054  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
50055  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
50056  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
50057  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
50058  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
50059  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
50060  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
50061  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
50062  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
50063  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
50064  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
50065  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
50066  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
50067  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
50068  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
50069  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
50070  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
50071  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
50072  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
50073  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
50074  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
50075  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
50076  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
50077  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
50078  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
50079  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
50080  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
50081  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
50082 };
50083 
50089 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
50090 {
50091  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
50092  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
50093  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
50094  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
50095  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
50096  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
50097  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
50098  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
50099  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
50100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
50101  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
50102  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
50103  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
50104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
50105  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
50106  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
50107  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
50108  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
50109  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
50110  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
50111  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
50112  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
50113  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
50114  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
50115  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
50116  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
50117  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
50118  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
50119  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
50120  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
50121 };
50122 
50128 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
50129 {
50130  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
50131  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
50132  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
50133  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
50134  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
50135  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
50136  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
50137  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
50138  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
50139  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
50140  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
50141  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
50142  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
50143  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
50144  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
50145  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
50146  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
50147  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
50148  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
50149  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
50150  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
50151  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
50152  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
50153  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
50154  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
50155  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
50156  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
50157  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
50158  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
50159  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
50160  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
50161  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
50162  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
50163  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
50164  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
50165  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
50166  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
50167  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
50168  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
50169  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
50170  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
50171  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
50172  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
50173  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
50174  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
50175  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
50176  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
50177  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
50178  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
50179  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
50180  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
50181  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
50182  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
50183  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
50184  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
50185  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
50186  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
50187  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
50188  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
50189  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
50190  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
50191  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
50192  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
50193  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
50194  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
50195  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
50196  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
50197  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
50198  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
50199  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
50200  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
50201  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
50202  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
50203  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
50204  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
50205  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
50206  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
50207  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
50208  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
50209  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
50210  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
50211  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
50212  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
50213  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
50214  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
50215  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
50216  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
50217  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
50218  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
50219  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
50220  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
50221  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
50222  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
50223  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
50224  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
50225  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
50226  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
50227  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
50228  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
50229  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
50230  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
50231  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
50232  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
50233  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
50234  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
50235  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
50236  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
50237  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
50238  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
50239  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
50240  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
50241  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
50242  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
50243  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
50244  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
50245  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
50246  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
50247  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
50248  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
50249  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
50250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
50251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
50252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
50253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
50254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
50255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
50256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
50257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
50258  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
50259  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
50260  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
50261  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
50262  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
50263  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
50264  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
50265  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
50266  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
50267  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
50268  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
50269  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
50270  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
50271  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
50272  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
50273  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
50274  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
50275  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
50276  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
50277  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
50278  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
50279  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
50280  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
50281  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
50282  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
50283  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
50284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
50285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
50286  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
50287  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
50288  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
50289  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
50290  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
50291  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
50292  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
50293  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
50294  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
50295  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
50296  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
50297  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
50298  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
50299  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
50300  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
50301  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
50302  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
50303  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
50304  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
50305  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
50306  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
50307  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
50308  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
50309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
50310  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
50311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
50312  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
50313  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
50314  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
50315  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
50316  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
50317  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
50318  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
50319  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
50320  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
50321  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
50322  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
50323  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
50324  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
50325  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
50326  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
50327  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
50328  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
50329  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
50330  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
50331  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
50332  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
50333  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
50334  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
50335  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
50336  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
50337  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
50338  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
50339  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
50340  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
50341  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
50342  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
50343  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
50344  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
50345  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
50346  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
50347  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
50348  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
50349  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
50350  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
50351  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
50352  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
50353  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
50354  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
50355  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
50356  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
50357  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
50358  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
50359  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
50360  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
50361  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
50362  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
50363  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
50364  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
50365  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
50366  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
50367  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
50368  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
50369  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
50370  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
50371  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
50372  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
50373  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
50374  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
50375  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
50376  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
50377  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
50378  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
50379  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
50380  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
50381  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
50382  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
50383  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
50384  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
50385  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
50386  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
50387  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
50388  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
50389  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
50390  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
50391  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
50392  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
50393  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
50394  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
50395  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
50396  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
50397  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
50398  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
50399  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
50400  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
50401  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
50402  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
50403  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
50404  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
50405  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
50406  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
50407  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
50408  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
50409  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
50410  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
50411  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
50412  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
50413  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
50414  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
50415  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
50416  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
50417  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
50418  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
50419  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
50420  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
50421  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
50422  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
50423  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
50424  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
50425  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
50426  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
50427  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
50428  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
50429  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
50430  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
50431  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
50432  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
50433  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
50434  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
50435  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
50436  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
50437  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
50438  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
50439  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
50440  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
50441  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
50442  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
50443  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
50444  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
50445  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
50446  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
50447  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
50448  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
50449  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
50450  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
50451  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
50452  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
50453  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
50454  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
50455  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
50456  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
50457  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
50458  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
50459  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
50460  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
50461  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
50462  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
50463  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
50464  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
50465  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
50466  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
50467  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
50468  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
50469  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
50470  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
50471  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
50472  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
50473  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
50474  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
50475  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
50476  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
50477  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
50478  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
50479  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
50480  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
50481  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
50482  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
50483  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
50484  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
50485  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
50486  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
50487  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
50488  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
50489  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
50490  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
50491  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
50492  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
50493  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
50494  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
50495  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
50496  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
50497  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
50498  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
50499  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
50500  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
50501  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
50502  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
50503  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
50504  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
50505  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
50506  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
50507  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
50508  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
50509  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
50510  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
50511  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
50512  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
50513  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
50514  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
50515  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
50516  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
50517  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
50518  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
50519  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
50520  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
50521  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
50522  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
50523  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
50524  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
50525  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
50526  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
50527  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
50528  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
50529  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
50530  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
50531  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
50532  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
50533  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
50534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
50535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
50536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
50537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
50538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
50539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
50540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
50541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
50542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
50543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
50544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
50545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
50546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
50547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
50548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
50549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
50550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
50551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
50552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
50553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
50554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
50555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
50556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
50557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
50558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
50559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
50560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
50561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
50562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
50563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
50564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
50565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
50566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
50567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
50568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
50569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
50570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
50571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
50572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
50573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
50574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
50575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
50576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
50577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
50578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
50579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
50580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
50581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
50582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
50583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
50584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
50585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
50586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
50587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
50588  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
50589  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
50590  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
50591  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
50592  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
50593  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
50594  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
50595  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
50596  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
50597  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
50598  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
50599  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
50600  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
50601  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
50602  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
50603  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
50604  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
50605  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
50606  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
50607  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
50608  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
50609  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
50610  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
50611  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
50612  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
50613  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
50614  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
50615  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
50616  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
50617  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
50618  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
50619  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
50620  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
50621  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
50622  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
50623  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
50624  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
50625  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
50626  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
50627  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
50628  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
50629  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
50630  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
50631  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
50632  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
50633  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
50634  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
50635  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
50636  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
50637  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
50638  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
50639  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
50640  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
50641  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
50642 };
50643 
50649 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
50650 {
50651  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
50652  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
50653  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
50654  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
50655  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
50656  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
50657  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
50658  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
50659  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
50660  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
50661  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
50662  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
50663  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
50664  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
50665  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
50666  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
50667  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
50668  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
50669  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
50670  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
50671  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
50672  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
50673  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
50674  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
50675  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
50676  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
50677  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
50678  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
50679  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
50680  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
50681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
50682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
50683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
50684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
50685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
50686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
50687  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
50688  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
50689  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
50690  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
50691  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
50692  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
50693  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
50694  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
50695  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
50696  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
50697  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
50698  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
50699  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
50700  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
50701  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
50702  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
50703  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
50704  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
50705  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
50706  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
50707  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
50708  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
50709  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
50710  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
50711  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
50712  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
50713  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
50714  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
50715  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
50716  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
50717  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
50718  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
50719  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
50720  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
50721  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
50722  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
50723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
50724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
50725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
50726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
50727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
50728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
50729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
50730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
50731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
50732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
50733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
50734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
50735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
50736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
50737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
50738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
50739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
50740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
50741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
50742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
50743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
50744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
50745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
50746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
50747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
50748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
50749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
50750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
50751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
50752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
50753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
50754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
50755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
50756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
50757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
50758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
50759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
50760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
50761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
50762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
50763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
50764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
50765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
50766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
50767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
50768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
50769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
50770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
50771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
50772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
50773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
50774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
50775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
50776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
50777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
50778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
50779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
50780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
50781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
50782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
50783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
50784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
50785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
50786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
50787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
50788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
50789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
50790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
50791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
50792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
50793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
50794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
50795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
50796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
50797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
50798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
50799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
50800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
50801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
50802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
50803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
50804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
50805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
50806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
50807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
50808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
50809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
50810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
50811  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
50812  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
50813  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
50814  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
50815  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
50816  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
50817  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
50818  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
50819  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
50820  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
50821  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
50822  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
50823  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
50824  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
50825  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
50826  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
50827  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
50828  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
50829  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
50830  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
50831  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
50832  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
50833  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
50834  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
50835  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
50836  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
50837  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
50838  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
50839  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
50840  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
50841  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
50842  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
50843  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
50844  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
50845  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
50846  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
50847  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
50848  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
50849  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
50850  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
50851  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
50852  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
50853  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
50854  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
50855  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
50856  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
50857  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
50858  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
50859  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
50860  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
50861  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
50862  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
50863  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
50864  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
50865  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
50866  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
50867  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
50868  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
50869  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
50870  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
50871  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
50872  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
50873  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
50874  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
50875  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
50876  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
50877  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
50878  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
50879  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
50880  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
50881  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
50882  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
50883  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
50884  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
50885  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
50886  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
50887  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
50888  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
50889  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
50890  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
50891  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
50892  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
50893  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
50894  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
50895  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
50896  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
50897  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
50898  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
50899  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
50900  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
50901  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
50902  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
50903  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
50904  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
50905  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
50906  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
50907  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
50908  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
50909  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
50910  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
50911  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
50912  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
50913  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
50914  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
50915  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
50916  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
50917  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
50918  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
50919  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
50920  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
50921  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
50922  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
50923  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
50924  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
50925  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
50926  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
50927  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
50928  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
50929  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
50930  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
50931  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
50932  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
50933  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
50934  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
50935  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
50936  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
50937  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
50938  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
50939  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
50940  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
50941  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
50942  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
50943  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
50944  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
50945  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
50946  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
50947  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
50948  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
50949  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
50950  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
50951  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
50952  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
50953  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
50954  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
50955  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
50956  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
50957  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
50958  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
50959  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
50960  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
50961  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
50962  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
50963  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
50964  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
50965  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
50966  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
50967  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
50968  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
50969  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
50970  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
50971  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
50972  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
50973  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
50974  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
50975  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
50976  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
50977  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
50978  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
50979  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
50980  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
50981  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
50982  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
50983  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
50984  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
50985  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
50986  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
50987  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
50988  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
50989  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
50990  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
50991  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
50992  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
50993  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
50994  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
50995  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
50996  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
50997  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
50998  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
50999  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
51000  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
51001  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
51002  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
51003  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
51004  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
51005  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
51006  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
51007  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
51008  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
51009  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
51010  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
51011  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
51012  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
51013  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
51014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
51015  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
51016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
51017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
51018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
51019  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
51020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
51021  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
51022  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
51023  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
51024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
51025  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
51026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
51027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
51028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
51029  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
51030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
51031  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
51032  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
51033  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
51034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
51035  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
51036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
51037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
51038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
51039  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
51040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
51041  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
51042  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
51043  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
51044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
51045  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
51046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
51047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
51048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
51049  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
51050  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
51051  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
51052  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
51053 };
51054 
51060 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
51061 {
51062  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
51063  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
51064  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
51065  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
51066  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
51067  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
51068  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
51069  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
51070  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
51071  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
51072  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
51073  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
51074  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
51075  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
51076  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
51077  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
51078  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
51079  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
51080  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
51081  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
51082  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
51083  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
51084  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
51085  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
51086  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
51087  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
51088  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
51089  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
51090  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
51091  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
51092  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
51093  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
51094  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
51095  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
51096  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
51097  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
51098  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
51099  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
51100  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
51101  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
51102  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
51103  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
51104  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
51105  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
51106  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
51107  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
51108  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
51109  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
51110  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
51111  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
51112  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
51113  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
51114  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
51115  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
51116  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
51117  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
51118  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
51119  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
51120  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
51121  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
51122  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
51123  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
51124  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
51125  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
51126  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
51127  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
51128  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
51129  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
51130  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
51131  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
51132  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
51133  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
51134  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
51135  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
51136  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
51137  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
51138  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
51139  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
51140  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
51141  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
51142  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
51143  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
51144  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
51145  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
51146 };
51147 
51153 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
51154 {
51155  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
51156  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
51157  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
51158  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
51159  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
51160  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
51161  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
51162  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
51163 };
51164 
51170 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
51171 {
51172  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
51173  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
51174  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
51175  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
51176  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
51177  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
51178  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
51179  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
51180  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
51181  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
51182  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
51183  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
51184  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
51185  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
51186  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
51187  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
51188  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
51189  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
51190  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
51191  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
51192  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
51193  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
51194  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
51195  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
51196  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
51197  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
51198  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
51199  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
51200  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
51201  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
51202 };
51203 
51209 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
51210 {
51211  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
51212  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
51213  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
51214  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
51215  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
51216  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
51217  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
51218  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
51219  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
51220  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
51221  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
51222  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
51223  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
51224  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
51225  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
51226  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
51227  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
51228  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
51229  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
51230  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
51231  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
51232  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
51233  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
51234  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
51235  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
51236  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
51237  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
51238  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
51239  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
51240  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
51241  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
51242  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
51243  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
51244  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
51245  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
51246  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
51247  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
51248  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
51249  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
51250  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
51251  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
51252  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
51253  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
51254  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
51255  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
51256  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
51257  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
51258  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
51259  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
51260  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
51261  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
51262  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
51263  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
51264  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
51265  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
51266  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
51267  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
51268  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
51269  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
51270  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
51271  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
51272  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
51273  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
51274  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
51275  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
51276  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
51277  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
51278  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
51279  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
51280  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
51281  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
51282  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
51283  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
51284  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
51285  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
51286  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
51287  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
51288  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
51289  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
51290  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
51291  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
51292  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
51293  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
51294  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
51295 };
51296 
51302 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
51303 {
51304  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
51305  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
51306  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
51307  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
51308  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
51309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
51310  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
51311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
51312  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
51313  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
51314 };
51315 
51321 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
51322 {
51323  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
51324  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
51325  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
51326  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
51327  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
51328  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
51329  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
51330  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
51331  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
51332  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
51333  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
51334  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
51335  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
51336  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
51337  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
51338  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
51339  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
51340  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
51341  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
51342  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
51343  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
51344  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
51345  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
51346  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
51347  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
51348  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
51349  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
51350  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
51351  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
51352  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
51353  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
51354  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
51355  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
51356  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
51357  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
51358  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
51359  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
51360  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
51361  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
51362  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
51363  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
51364  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
51365  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
51366  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
51367  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
51368  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
51369  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
51370  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
51371  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
51372  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
51373  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
51374  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
51375  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
51376  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
51377  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
51378  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
51379  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
51380  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
51381  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
51382  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
51383  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
51384  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
51385  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
51386  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
51387  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
51388  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
51389  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
51390  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
51391  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
51392  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
51393  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
51394  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
51395  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
51396  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
51397  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
51398  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
51399  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
51400  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
51401  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
51402  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
51403  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
51404  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
51405  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
51406  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
51407  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
51408  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
51409  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
51410  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
51411  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
51412  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
51413  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
51414  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
51415  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
51416  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
51417  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
51418  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
51419  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
51420  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
51421  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
51422  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
51423  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
51424  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
51425  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
51426  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
51427  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
51428  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
51429  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
51430  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
51431  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
51432  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
51433  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
51434  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
51435  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
51436  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
51437  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
51438  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
51439  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
51440  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
51441  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
51442  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
51443  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
51444  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
51445  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
51446  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
51447  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
51448  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
51449  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
51450  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
51451  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
51452  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
51453  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
51454  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
51455  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
51456  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
51457  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
51458  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
51459  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
51460  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
51461  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
51462  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
51463  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
51464  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
51465  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
51466  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
51467  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
51468  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
51469  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
51470  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
51471  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
51472  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
51473  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
51474  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
51475  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
51476  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
51477  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
51478  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
51479  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
51480  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
51481  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
51482  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
51483  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
51484  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
51485  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
51486  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
51487  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
51488  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
51489  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
51490  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
51491  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
51492  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
51493  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
51494  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
51495  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
51496  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
51497  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
51498  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
51499  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
51500  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
51501  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
51502  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
51503  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
51504  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
51505  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
51506  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
51507  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
51508  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
51509  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
51510  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
51511  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
51512  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
51513  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
51514  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
51515  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
51516  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
51517  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
51518  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
51519  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
51520  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
51521  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
51522  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
51523  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
51524  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
51525  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
51526  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
51527  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
51528  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
51529  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
51530  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
51531  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
51532  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
51533  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
51534  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
51535  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
51536  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
51537  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
51538  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
51539  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
51540  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
51541  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
51542  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
51543  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
51544  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
51545  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
51546  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
51547  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
51548  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
51549  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
51550  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
51551  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
51552  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
51553  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
51554  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
51555  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
51556  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
51557  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
51558  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
51559  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
51560  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
51561  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
51562  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
51563  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
51564  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
51565  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
51566  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
51567  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
51568  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
51569  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
51570  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
51571  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
51572  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
51573  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
51574  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
51575  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
51576  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
51577  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
51578  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
51579  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
51580  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
51581  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
51582  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
51583  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
51584  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
51585  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
51586  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
51587  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
51588  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
51589  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
51590  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
51591  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
51592  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
51593  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
51594  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
51595  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
51596  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
51597  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
51598  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
51599  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
51600  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
51601  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
51602  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
51603  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
51604  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
51605  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
51606  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
51607  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
51608  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
51609  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
51610  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
51611  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
51612  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
51613  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
51614  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
51615  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
51616  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
51617  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
51618  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
51619  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
51620  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
51621  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
51622  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
51623  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
51624  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
51625  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
51626  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
51627  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
51628  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
51629  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
51630  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
51631  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
51632  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
51633  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
51634  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
51635  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
51636  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
51637  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
51638  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
51639  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
51640  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
51641  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
51642  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
51643  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
51644  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
51645  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
51646  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
51647  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
51648  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
51649  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
51650  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
51651  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
51652  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
51653  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
51654  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
51655  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
51656  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
51657  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
51658  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
51659  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
51660  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
51661  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
51662  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
51663  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
51664  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
51665  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
51666  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
51667  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
51668  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
51669  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
51670  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
51671  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
51672  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
51673  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
51674  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
51675  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
51676  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
51677  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
51678  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
51679  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
51680  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
51681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
51682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
51683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
51684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
51685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
51686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
51687  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
51688  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
51689  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
51690  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
51691  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
51692  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
51693  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
51694  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
51695  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
51696  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
51697  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
51698  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
51699  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
51700  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
51701  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
51702  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
51703  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
51704  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
51705  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
51706  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
51707  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
51708  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
51709  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
51710  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
51711  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
51712  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
51713  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
51714  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
51715  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
51716  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
51717  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
51718  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
51719  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
51720  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
51721  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
51722  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
51723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
51724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
51725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
51726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
51727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
51728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
51729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
51730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
51731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
51732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
51733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
51734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
51735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
51736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
51737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
51738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
51739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
51740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
51741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
51742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
51743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
51744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
51745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
51746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
51747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
51748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
51749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
51750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
51751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
51752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
51753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
51754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
51755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
51756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
51757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
51758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
51759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
51760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
51761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
51762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
51763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
51764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
51765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
51766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
51767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
51768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
51769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
51770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
51771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
51772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
51773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
51774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
51775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
51776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
51777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
51778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
51779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
51780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
51781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
51782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
51783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
51784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
51785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
51786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
51787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
51788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
51789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
51790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
51791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
51792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
51793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
51794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
51795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
51796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
51797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
51798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
51799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
51800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
51801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
51802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
51803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
51804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
51805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
51806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
51807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
51808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
51809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
51810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
51811  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
51812  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
51813  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
51814  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
51815  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
51816  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
51817  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
51818  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
51819  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
51820  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
51821  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
51822  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
51823  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
51824  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
51825  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
51826  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
51827  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
51828  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
51829  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
51830  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
51831  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
51832  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
51833  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
51834  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
51835 };
51836 
51842 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
51843 {
51844  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
51845  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
51846  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
51847  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
51848  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
51849  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
51850  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
51851  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
51852  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
51853  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
51854  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
51855  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
51856  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
51857  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
51858  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
51859  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
51860  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
51861  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
51862  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
51863  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
51864  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
51865  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
51866  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
51867  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
51868  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
51869  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
51870  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
51871  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
51872  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
51873  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
51874  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
51875  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
51876  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
51877  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
51878  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
51879  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
51880  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
51881  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
51882  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
51883  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
51884  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
51885  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
51886  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
51887  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
51888  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
51889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
51890  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
51891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
51892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
51893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
51894  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
51895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
51896  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
51897  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
51898  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
51899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
51900  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
51901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
51902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
51903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
51904  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
51905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
51906  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
51907  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
51908  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
51909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
51910  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
51911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
51912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
51913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
51914  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
51915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
51916  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
51917  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
51918  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
51919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
51920  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
51921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
51922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
51923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
51924  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
51925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
51926  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
51927  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
51928  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
51929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
51930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
51931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
51932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
51933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
51934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
51935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
51936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
51937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
51938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
51939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
51940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
51941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
51942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
51943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
51944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
51945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
51946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
51947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
51948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
51949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
51950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
51951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
51952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
51953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
51954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
51955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
51956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
51957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
51958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
51959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
51960  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
51961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
51962  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
51963  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
51964  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
51965  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
51966  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
51967  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
51968  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
51969  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
51970  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
51971  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
51972  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
51973  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
51974  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
51975  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
51976  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
51977  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
51978  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
51979  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
51980  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
51981  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
51982  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
51983  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
51984  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
51985  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
51986  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
51987  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
51988  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
51989  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
51990  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
51991  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
51992  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
51993  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
51994  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
51995  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
51996  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
51997  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
51998  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
51999  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
52000  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
52001  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
52002  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
52003  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
52004  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
52005  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
52006  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
52007  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
52008  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
52009  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
52010  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
52011  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
52012  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
52013  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
52014  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
52015  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
52016  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
52017  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
52018  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
52019  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
52020  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
52021  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
52022  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
52023  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
52024  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
52025  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
52026  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
52027  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
52028  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
52029  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
52030  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
52031  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
52032  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
52033  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
52034  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
52035  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
52036  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
52037  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
52038  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
52039  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
52040  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
52041  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
52042  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
52043  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
52044  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
52045  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
52046  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
52047  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
52048  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
52049  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
52050  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
52051  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
52052  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
52053  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
52054  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
52055  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
52056  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
52057  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
52058  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
52059  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
52060  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
52061  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
52062  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
52063  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
52064  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
52065  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
52066  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
52067  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
52068  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
52069  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
52070  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
52071  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
52072  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
52073  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
52074  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
52075  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
52076  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
52077  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
52078  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
52079  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
52080  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
52081  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
52082  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
52083  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
52084  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
52085  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
52086  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
52087  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
52088  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
52089  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
52090  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
52091  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
52092  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
52093  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
52094  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
52095  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
52096  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
52097  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
52098  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
52099  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
52100  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
52101  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
52102  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
52103  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
52104  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
52105  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
52106  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
52107  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
52108  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
52109  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
52110  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
52111  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
52112  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
52113  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
52114  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
52115  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
52116  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
52117  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
52118  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
52119  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
52120  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
52121  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
52122  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
52123  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
52124  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
52125  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
52126  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
52127  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
52128  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
52129  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
52130  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
52131  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
52132  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
52133  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
52134  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
52135  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
52136  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
52137  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
52138  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
52139  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
52140  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
52141  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
52142  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
52143  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
52144  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
52145  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
52146  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
52147  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
52148  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
52149  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
52150  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
52151  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
52152  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
52153  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
52154  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
52155  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
52156  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
52157  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
52158  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
52159  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
52160  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
52161  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
52162  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
52163  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
52164  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
52165  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
52166  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
52167  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
52168  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
52169  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
52170  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
52171  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
52172  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
52173  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
52174  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
52175  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
52176  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
52177  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
52178  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
52179  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
52180  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
52181  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
52182  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
52183  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
52184  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
52185  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
52186  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
52187  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
52188  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
52189  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
52190  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
52191  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
52192  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
52193  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
52194  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
52195  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
52196  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
52197  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
52198  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
52199  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
52200  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
52201  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
52202  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
52203  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
52204  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
52205  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
52206  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
52207  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
52208  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
52209  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
52210  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
52211  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
52212  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
52213  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
52214  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
52215  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
52216  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
52217  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
52218  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
52219  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
52220  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
52221  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
52222  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
52223  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
52224  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
52225  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
52226  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
52227  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
52228  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
52229  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
52230  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
52231  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
52232  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
52233  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
52234  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
52235  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
52236  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
52237  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
52238  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
52239  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
52240  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
52241  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
52242  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
52243  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
52244  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
52245  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
52246  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
52247  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
52248  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
52249  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
52250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
52251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
52252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
52253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
52254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
52255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
52256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
52257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
52258  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
52259  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
52260  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
52261  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
52262  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
52263  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
52264  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
52265  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
52266  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
52267  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
52268  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
52269  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
52270  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
52271  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
52272  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
52273  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
52274  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
52275  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
52276  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
52277  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
52278  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
52279  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
52280  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
52281  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
52282  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
52283  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
52284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
52285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
52286  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
52287  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
52288  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
52289  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
52290  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
52291  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
52292  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
52293  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
52294  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
52295  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
52296  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
52297  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
52298  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
52299  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
52300  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
52301  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
52302  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
52303  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
52304  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
52305  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
52306  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
52307  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
52308  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
52309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
52310  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
52311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
52312  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
52313  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
52314  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
52315  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
52316  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
52317  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
52318  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
52319  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
52320  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
52321  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
52322  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
52323  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
52324  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
52325  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
52326  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
52327  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
52328  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
52329  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
52330  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
52331  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
52332  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
52333  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
52334  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
52335  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
52336  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
52337  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
52338  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
52339  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
52340  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
52341  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
52342  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
52343  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
52344  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
52345  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
52346  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
52347  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
52348  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
52349  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
52350  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
52351  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
52352  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
52353  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
52354  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
52355  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
52356 };
52357 
52363 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
52364 {
52365  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
52366  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
52367  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
52368  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
52369  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
52370  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
52371  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
52372  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
52373  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
52374  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
52375  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
52376  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
52377  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
52378  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
52379  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
52380  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
52381  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
52382  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
52383  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
52384  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
52385  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
52386  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
52387  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
52388  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
52389  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
52390  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
52391  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
52392  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
52393  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
52394  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
52395  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
52396  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
52397  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
52398  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
52399  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
52400  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
52401  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
52402  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
52403  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
52404  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
52405  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
52406  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
52407  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
52408  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
52409  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
52410  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
52411  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
52412  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
52413  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
52414  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
52415  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
52416  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
52417  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
52418  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
52419  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
52420  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
52421  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
52422  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
52423  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
52424  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
52425  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
52426  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
52427  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
52428  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
52429  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
52430  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
52431  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
52432  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
52433  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
52434  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
52435  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
52436  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
52437  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
52438  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
52439  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
52440  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
52441  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
52442  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
52443  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
52444  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
52445  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
52446  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
52447  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
52448  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
52449  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
52450  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
52451  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
52452  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
52453  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
52454  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
52455  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
52456  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
52457  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
52458  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
52459  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
52460  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
52461  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
52462  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
52463  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
52464  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
52465  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
52466  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
52467  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
52468  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
52469  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
52470  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
52471  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
52472  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
52473  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
52474  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
52475  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
52476  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
52477  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
52478  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
52479  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
52480  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
52481  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
52482  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
52483  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
52484  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
52485  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
52486  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
52487  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
52488  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
52489  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
52490  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
52491  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
52492  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
52493  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
52494  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
52495  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
52496  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
52497  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
52498  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
52499  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
52500  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
52501  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
52502  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
52503  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
52504  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
52505  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
52506  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
52507  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
52508  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
52509  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
52510  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
52511  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
52512  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
52513  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
52514  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
52515  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
52516  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
52517  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
52518  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
52519  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
52520  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
52521  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
52522  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
52523  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
52524  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
52525  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
52526  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
52527  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
52528  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
52529  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
52530  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
52531  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
52532  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
52533  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
52534  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
52535  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
52536  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
52537  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
52538  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
52539  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
52540  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
52541  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
52542  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
52543  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
52544  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
52545  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
52546  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
52547  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
52548  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
52549  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
52550  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
52551  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
52552  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
52553  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
52554  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
52555  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
52556  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
52557  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
52558  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
52559  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
52560  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
52561  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
52562  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
52563  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
52564  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
52565  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
52566  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
52567  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
52568  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
52569  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
52570  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
52571  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
52572  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
52573  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
52574  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
52575  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
52576  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
52577  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
52578  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
52579  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
52580  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
52581  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
52582  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
52583  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
52584  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
52585  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
52586  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
52587  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
52588  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
52589  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
52590  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
52591  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
52592  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
52593  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
52594  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
52595  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
52596  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
52597  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
52598  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
52599  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
52600  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
52601  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
52602  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
52603  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
52604  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
52605  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
52606  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
52607  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
52608  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
52609  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
52610  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
52611  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
52612  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
52613  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
52614  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
52615  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
52616  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
52617  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
52618  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
52619  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
52620  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
52621  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
52622  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
52623  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
52624  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
52625  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
52626  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
52627  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
52628  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
52629  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
52630  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
52631  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
52632  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
52633  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
52634  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
52635  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
52636  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
52637  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
52638  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
52639  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
52640  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
52641  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
52642  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
52643  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
52644  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
52645  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
52646  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
52647  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
52648  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
52649  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
52650  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
52651  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
52652  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
52653  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
52654  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
52655  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
52656  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
52657  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
52658  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
52659  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
52660  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
52661  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
52662  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
52663  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
52664  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
52665  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
52666  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
52667  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
52668  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
52669  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
52670  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
52671  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
52672  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
52673  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
52674  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
52675  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
52676  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
52677  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
52678  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
52679  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
52680  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
52681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
52682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
52683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
52684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
52685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
52686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
52687  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
52688  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
52689  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
52690  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
52691  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
52692  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
52693  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
52694  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
52695  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
52696  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
52697  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
52698  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
52699  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
52700  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
52701  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
52702  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
52703  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
52704  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
52705  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
52706  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
52707  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
52708  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
52709  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
52710  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
52711  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
52712  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
52713  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
52714  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
52715  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
52716  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
52717  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
52718  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
52719  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
52720  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
52721  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
52722  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
52723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
52724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
52725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
52726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
52727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
52728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
52729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
52730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
52731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
52732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
52733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
52734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
52735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
52736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
52737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
52738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
52739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
52740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
52741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
52742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
52743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
52744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
52745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
52746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
52747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
52748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
52749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
52750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
52751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
52752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
52753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
52754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
52755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
52756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
52757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
52758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
52759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
52760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
52761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
52762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
52763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
52764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
52765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
52766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
52767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
52768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
52769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
52770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
52771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
52772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
52773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
52774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
52775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
52776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
52777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
52778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
52779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
52780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
52781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
52782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
52783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
52784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
52785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
52786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
52787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
52788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
52789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
52790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
52791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
52792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
52793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
52794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
52795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
52796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
52797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
52798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
52799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
52800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
52801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
52802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
52803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
52804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
52805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
52806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
52807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
52808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
52809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
52810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
52811  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
52812  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
52813  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
52814  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
52815  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
52816  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
52817  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
52818  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
52819  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
52820  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
52821  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
52822  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
52823  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
52824  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
52825  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
52826  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
52827  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
52828  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
52829  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
52830  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
52831  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
52832  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
52833  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
52834  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
52835  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
52836  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
52837  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
52838  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
52839  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
52840  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
52841  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
52842  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
52843  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
52844  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
52845  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
52846  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
52847  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
52848  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
52849  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
52850  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
52851  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
52852  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
52853  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
52854  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
52855  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
52856  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
52857  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
52858  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
52859  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
52860  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
52861  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
52862  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
52863  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
52864  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
52865  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
52866  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
52867  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
52868  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
52869  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
52870  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
52871  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
52872  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
52873  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
52874  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
52875  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
52876  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
52877 };
52878 
52884 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS] =
52885 {
52886  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_CHECKER_TYPE,
52887  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_WIDTH },
52888  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_CHECKER_TYPE,
52889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_WIDTH },
52890  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_CHECKER_TYPE,
52891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_WIDTH },
52892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_CHECKER_TYPE,
52893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_WIDTH },
52894  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_CHECKER_TYPE,
52895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_WIDTH },
52896  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_CHECKER_TYPE,
52897  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_WIDTH },
52898  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_CHECKER_TYPE,
52899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_WIDTH },
52900  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_CHECKER_TYPE,
52901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_WIDTH },
52902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_CHECKER_TYPE,
52903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_WIDTH },
52904  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_CHECKER_TYPE,
52905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_WIDTH },
52906  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_CHECKER_TYPE,
52907  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_WIDTH },
52908  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_CHECKER_TYPE,
52909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_WIDTH },
52910  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_CHECKER_TYPE,
52911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_WIDTH },
52912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_CHECKER_TYPE,
52913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_WIDTH },
52914  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_CHECKER_TYPE,
52915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_WIDTH },
52916  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_CHECKER_TYPE,
52917  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_WIDTH },
52918  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_CHECKER_TYPE,
52919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_WIDTH },
52920  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_CHECKER_TYPE,
52921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_WIDTH },
52922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_CHECKER_TYPE,
52923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_WIDTH },
52924  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_CHECKER_TYPE,
52925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_WIDTH },
52926  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_CHECKER_TYPE,
52927  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_WIDTH },
52928  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_CHECKER_TYPE,
52929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_WIDTH },
52930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_CHECKER_TYPE,
52931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_WIDTH },
52932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_CHECKER_TYPE,
52933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_WIDTH },
52934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_CHECKER_TYPE,
52935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_WIDTH },
52936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_CHECKER_TYPE,
52937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_WIDTH },
52938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_CHECKER_TYPE,
52939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_WIDTH },
52940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_CHECKER_TYPE,
52941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_WIDTH },
52942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_CHECKER_TYPE,
52943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_WIDTH },
52944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_CHECKER_TYPE,
52945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_WIDTH },
52946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_CHECKER_TYPE,
52947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_WIDTH },
52948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_CHECKER_TYPE,
52949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_WIDTH },
52950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_CHECKER_TYPE,
52951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_WIDTH },
52952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_CHECKER_TYPE,
52953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_WIDTH },
52954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_CHECKER_TYPE,
52955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_WIDTH },
52956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_CHECKER_TYPE,
52957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_WIDTH },
52958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_CHECKER_TYPE,
52959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_WIDTH },
52960  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_CHECKER_TYPE,
52961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_WIDTH },
52962  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_CHECKER_TYPE,
52963  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_WIDTH },
52964  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_CHECKER_TYPE,
52965  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_WIDTH },
52966  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_CHECKER_TYPE,
52967  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_WIDTH },
52968  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_CHECKER_TYPE,
52969  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_WIDTH },
52970  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_CHECKER_TYPE,
52971  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_WIDTH },
52972  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_CHECKER_TYPE,
52973  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_WIDTH },
52974  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_CHECKER_TYPE,
52975  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_WIDTH },
52976  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_CHECKER_TYPE,
52977  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_WIDTH },
52978  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_CHECKER_TYPE,
52979  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_WIDTH },
52980  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_CHECKER_TYPE,
52981  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_WIDTH },
52982  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_CHECKER_TYPE,
52983  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_WIDTH },
52984  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_CHECKER_TYPE,
52985  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_WIDTH },
52986  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_CHECKER_TYPE,
52987  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_WIDTH },
52988  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_CHECKER_TYPE,
52989  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_WIDTH },
52990  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_CHECKER_TYPE,
52991  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_WIDTH },
52992  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_CHECKER_TYPE,
52993  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_WIDTH },
52994  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_CHECKER_TYPE,
52995  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_WIDTH },
52996  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_CHECKER_TYPE,
52997  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_WIDTH },
52998  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_CHECKER_TYPE,
52999  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_WIDTH },
53000  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_CHECKER_TYPE,
53001  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_WIDTH },
53002  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_CHECKER_TYPE,
53003  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_WIDTH },
53004  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_CHECKER_TYPE,
53005  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_WIDTH },
53006  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_CHECKER_TYPE,
53007  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_WIDTH },
53008  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_CHECKER_TYPE,
53009  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_WIDTH },
53010  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_CHECKER_TYPE,
53011  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_WIDTH },
53012  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_CHECKER_TYPE,
53013  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_WIDTH },
53014  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_CHECKER_TYPE,
53015  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_WIDTH },
53016  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_CHECKER_TYPE,
53017  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_WIDTH },
53018  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_CHECKER_TYPE,
53019  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_WIDTH },
53020  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_CHECKER_TYPE,
53021  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_WIDTH },
53022  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_CHECKER_TYPE,
53023  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_WIDTH },
53024  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_CHECKER_TYPE,
53025  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_WIDTH },
53026  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_CHECKER_TYPE,
53027  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_WIDTH },
53028  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_CHECKER_TYPE,
53029  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_WIDTH },
53030  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_CHECKER_TYPE,
53031  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_WIDTH },
53032  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_CHECKER_TYPE,
53033  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_WIDTH },
53034  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_CHECKER_TYPE,
53035  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_WIDTH },
53036  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_CHECKER_TYPE,
53037  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_WIDTH },
53038  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_CHECKER_TYPE,
53039  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_WIDTH },
53040  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_CHECKER_TYPE,
53041  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_WIDTH },
53042  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_CHECKER_TYPE,
53043  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_WIDTH },
53044  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_CHECKER_TYPE,
53045  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_WIDTH },
53046  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_CHECKER_TYPE,
53047  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_WIDTH },
53048  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_CHECKER_TYPE,
53049  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_WIDTH },
53050  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_CHECKER_TYPE,
53051  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_WIDTH },
53052  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_CHECKER_TYPE,
53053  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_WIDTH },
53054  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_CHECKER_TYPE,
53055  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_WIDTH },
53056  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_CHECKER_TYPE,
53057  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_WIDTH },
53058  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_CHECKER_TYPE,
53059  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_WIDTH },
53060  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_CHECKER_TYPE,
53061  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_WIDTH },
53062  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_CHECKER_TYPE,
53063  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_WIDTH },
53064  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_CHECKER_TYPE,
53065  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_WIDTH },
53066  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_CHECKER_TYPE,
53067  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_WIDTH },
53068  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_CHECKER_TYPE,
53069  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_WIDTH },
53070  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_CHECKER_TYPE,
53071  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_WIDTH },
53072  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_CHECKER_TYPE,
53073  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_WIDTH },
53074  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_CHECKER_TYPE,
53075  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_WIDTH },
53076  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_CHECKER_TYPE,
53077  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_WIDTH },
53078  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_CHECKER_TYPE,
53079  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_WIDTH },
53080  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_CHECKER_TYPE,
53081  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_WIDTH },
53082  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_CHECKER_TYPE,
53083  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_WIDTH },
53084  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_CHECKER_TYPE,
53085  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_WIDTH },
53086  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_CHECKER_TYPE,
53087  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_WIDTH },
53088  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_CHECKER_TYPE,
53089  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_WIDTH },
53090 };
53091 
53097 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
53098 {
53099  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
53100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
53101  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
53102  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
53103  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
53104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
53105 };
53106 
53112 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
53113 {
53114  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
53115  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
53116  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
53117  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
53118  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
53119  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
53120  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
53121  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
53122  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
53123  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
53124  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
53125  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
53126 };
53127 
53133 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS] =
53134 {
53135  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_0_CHECKER_TYPE,
53136  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_0_WIDTH },
53137  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_1_CHECKER_TYPE,
53138  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_1_WIDTH },
53139  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_2_CHECKER_TYPE,
53140  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_2_WIDTH },
53141  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_3_CHECKER_TYPE,
53142  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_3_WIDTH },
53143  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_4_CHECKER_TYPE,
53144  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_4_WIDTH },
53145  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_5_CHECKER_TYPE,
53146  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_5_WIDTH },
53147  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_6_CHECKER_TYPE,
53148  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_6_WIDTH },
53149  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_7_CHECKER_TYPE,
53150  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_7_WIDTH },
53151  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_8_CHECKER_TYPE,
53152  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_8_WIDTH },
53153  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_9_CHECKER_TYPE,
53154  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_9_WIDTH },
53155  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_10_CHECKER_TYPE,
53156  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_10_WIDTH },
53157  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_11_CHECKER_TYPE,
53158  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_11_WIDTH },
53159  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_12_CHECKER_TYPE,
53160  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_12_WIDTH },
53161  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_13_CHECKER_TYPE,
53162  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_13_WIDTH },
53163  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_14_CHECKER_TYPE,
53164  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_14_WIDTH },
53165  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_15_CHECKER_TYPE,
53166  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_15_WIDTH },
53167  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_16_CHECKER_TYPE,
53168  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_16_WIDTH },
53169  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_17_CHECKER_TYPE,
53170  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_17_WIDTH },
53171  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_18_CHECKER_TYPE,
53172  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_18_WIDTH },
53173  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_19_CHECKER_TYPE,
53174  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_19_WIDTH },
53175  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_20_CHECKER_TYPE,
53176  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_20_WIDTH },
53177  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_21_CHECKER_TYPE,
53178  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_21_WIDTH },
53179  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_22_CHECKER_TYPE,
53180  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_22_WIDTH },
53181  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_23_CHECKER_TYPE,
53182  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_23_WIDTH },
53183  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_24_CHECKER_TYPE,
53184  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_24_WIDTH },
53185  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_25_CHECKER_TYPE,
53186  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_25_WIDTH },
53187  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_26_CHECKER_TYPE,
53188  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_26_WIDTH },
53189  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_27_CHECKER_TYPE,
53190  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_27_WIDTH },
53191  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_28_CHECKER_TYPE,
53192  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_28_WIDTH },
53193  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_29_CHECKER_TYPE,
53194  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_29_WIDTH },
53195  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_30_CHECKER_TYPE,
53196  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_30_WIDTH },
53197  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_31_CHECKER_TYPE,
53198  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_31_WIDTH },
53199  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_32_CHECKER_TYPE,
53200  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_32_WIDTH },
53201  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_33_CHECKER_TYPE,
53202  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_33_WIDTH },
53203  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_34_CHECKER_TYPE,
53204  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_34_WIDTH },
53205  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_35_CHECKER_TYPE,
53206  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_35_WIDTH },
53207  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_36_CHECKER_TYPE,
53208  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_36_WIDTH },
53209  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_37_CHECKER_TYPE,
53210  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_37_WIDTH },
53211  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_38_CHECKER_TYPE,
53212  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_38_WIDTH },
53213  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_39_CHECKER_TYPE,
53214  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_39_WIDTH },
53215  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_40_CHECKER_TYPE,
53216  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_40_WIDTH },
53217  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_41_CHECKER_TYPE,
53218  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_41_WIDTH },
53219  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_42_CHECKER_TYPE,
53220  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_42_WIDTH },
53221  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_43_CHECKER_TYPE,
53222  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_43_WIDTH },
53223  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_44_CHECKER_TYPE,
53224  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_44_WIDTH },
53225  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_45_CHECKER_TYPE,
53226  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_45_WIDTH },
53227  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_46_CHECKER_TYPE,
53228  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_46_WIDTH },
53229  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_47_CHECKER_TYPE,
53230  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_47_WIDTH },
53231  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_48_CHECKER_TYPE,
53232  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_48_WIDTH },
53233  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_49_CHECKER_TYPE,
53234  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_49_WIDTH },
53235  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_50_CHECKER_TYPE,
53236  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_50_WIDTH },
53237  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_51_CHECKER_TYPE,
53238  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_51_WIDTH },
53239  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_52_CHECKER_TYPE,
53240  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_52_WIDTH },
53241 };
53242 
53248 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS] =
53249 {
53250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
53251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_WIDTH },
53252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
53253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_WIDTH },
53254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
53255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_WIDTH },
53256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
53257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_WIDTH },
53258 };
53259 
53265 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS] =
53266 {
53267  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
53268  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
53269  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
53270  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
53271  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
53272  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
53273  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
53274  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
53275 };
53276 
53282 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
53283 {
53284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
53285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
53286 };
53287 
53293 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
53294 {
53295  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
53296  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_0_WIDTH },
53297  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
53298  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_1_WIDTH },
53299  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
53300  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_2_WIDTH },
53301  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
53302  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_3_WIDTH },
53303  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
53304  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_4_WIDTH },
53305  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
53306  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_5_WIDTH },
53307  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
53308  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_6_WIDTH },
53309  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
53310  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_7_WIDTH },
53311  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
53312  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_8_WIDTH },
53313  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
53314  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_9_WIDTH },
53315  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
53316  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_10_WIDTH },
53317  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
53318  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_11_WIDTH },
53319  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
53320  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_12_WIDTH },
53321  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
53322  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_13_WIDTH },
53323  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
53324  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_14_WIDTH },
53325 };
53326 
53332 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
53333 {
53334  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
53335  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
53336  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
53337  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
53338  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
53339  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
53340 };
53341 
53347 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS] =
53348 {
53349  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_0_CHECKER_TYPE,
53350  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_0_WIDTH },
53351  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_1_CHECKER_TYPE,
53352  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_1_WIDTH },
53353  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_2_CHECKER_TYPE,
53354  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_2_WIDTH },
53355  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_3_CHECKER_TYPE,
53356  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_3_WIDTH },
53357  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_4_CHECKER_TYPE,
53358  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_4_WIDTH },
53359  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_5_CHECKER_TYPE,
53360  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_5_WIDTH },
53361  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_6_CHECKER_TYPE,
53362  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_6_WIDTH },
53363  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_7_CHECKER_TYPE,
53364  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_7_WIDTH },
53365  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_8_CHECKER_TYPE,
53366  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_8_WIDTH },
53367  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_9_CHECKER_TYPE,
53368  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_9_WIDTH },
53369  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_10_CHECKER_TYPE,
53370  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_10_WIDTH },
53371  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_11_CHECKER_TYPE,
53372  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_11_WIDTH },
53373  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_12_CHECKER_TYPE,
53374  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_12_WIDTH },
53375  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_13_CHECKER_TYPE,
53376  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_13_WIDTH },
53377  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_14_CHECKER_TYPE,
53378  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_14_WIDTH },
53379  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_15_CHECKER_TYPE,
53380  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_15_WIDTH },
53381  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_16_CHECKER_TYPE,
53382  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_16_WIDTH },
53383  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_17_CHECKER_TYPE,
53384  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_17_WIDTH },
53385  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_18_CHECKER_TYPE,
53386  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_18_WIDTH },
53387  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_19_CHECKER_TYPE,
53388  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_19_WIDTH },
53389  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_20_CHECKER_TYPE,
53390  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_20_WIDTH },
53391  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_21_CHECKER_TYPE,
53392  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_21_WIDTH },
53393  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_22_CHECKER_TYPE,
53394  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_22_WIDTH },
53395  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_23_CHECKER_TYPE,
53396  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_23_WIDTH },
53397  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_24_CHECKER_TYPE,
53398  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_24_WIDTH },
53399  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_25_CHECKER_TYPE,
53400  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_25_WIDTH },
53401  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_26_CHECKER_TYPE,
53402  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_26_WIDTH },
53403  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_27_CHECKER_TYPE,
53404  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_27_WIDTH },
53405  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_28_CHECKER_TYPE,
53406  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_28_WIDTH },
53407  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_29_CHECKER_TYPE,
53408  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_29_WIDTH },
53409  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_30_CHECKER_TYPE,
53410  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_30_WIDTH },
53411  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_31_CHECKER_TYPE,
53412  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_31_WIDTH },
53413  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_32_CHECKER_TYPE,
53414  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_32_WIDTH },
53415  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_33_CHECKER_TYPE,
53416  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_33_WIDTH },
53417  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_34_CHECKER_TYPE,
53418  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_34_WIDTH },
53419  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_35_CHECKER_TYPE,
53420  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_35_WIDTH },
53421  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_36_CHECKER_TYPE,
53422  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_36_WIDTH },
53423  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_37_CHECKER_TYPE,
53424  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_37_WIDTH },
53425  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_38_CHECKER_TYPE,
53426  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_38_WIDTH },
53427  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_39_CHECKER_TYPE,
53428  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_39_WIDTH },
53429  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_40_CHECKER_TYPE,
53430  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_40_WIDTH },
53431  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_41_CHECKER_TYPE,
53432  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_41_WIDTH },
53433  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_42_CHECKER_TYPE,
53434  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_42_WIDTH },
53435  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_43_CHECKER_TYPE,
53436  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_43_WIDTH },
53437  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_44_CHECKER_TYPE,
53438  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_44_WIDTH },
53439  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_45_CHECKER_TYPE,
53440  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_45_WIDTH },
53441  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_46_CHECKER_TYPE,
53442  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_46_WIDTH },
53443  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_47_CHECKER_TYPE,
53444  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_47_WIDTH },
53445  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_48_CHECKER_TYPE,
53446  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_48_WIDTH },
53447  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_49_CHECKER_TYPE,
53448  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_49_WIDTH },
53449  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_50_CHECKER_TYPE,
53450  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_50_WIDTH },
53451  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_51_CHECKER_TYPE,
53452  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_GROUP_51_WIDTH },
53453 };
53454 
53460 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS] =
53461 {
53462  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_0_CHECKER_TYPE,
53463  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_0_WIDTH },
53464  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_1_CHECKER_TYPE,
53465  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_1_WIDTH },
53466  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_2_CHECKER_TYPE,
53467  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_2_WIDTH },
53468  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_3_CHECKER_TYPE,
53469  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_3_WIDTH },
53470  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_4_CHECKER_TYPE,
53471  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_4_WIDTH },
53472  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_5_CHECKER_TYPE,
53473  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_5_WIDTH },
53474  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_6_CHECKER_TYPE,
53475  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_6_WIDTH },
53476  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_7_CHECKER_TYPE,
53477  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_7_WIDTH },
53478  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_8_CHECKER_TYPE,
53479  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_8_WIDTH },
53480  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_9_CHECKER_TYPE,
53481  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_9_WIDTH },
53482  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_10_CHECKER_TYPE,
53483  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_10_WIDTH },
53484  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_11_CHECKER_TYPE,
53485  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_11_WIDTH },
53486  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_12_CHECKER_TYPE,
53487  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_12_WIDTH },
53488  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_13_CHECKER_TYPE,
53489  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_13_WIDTH },
53490  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_14_CHECKER_TYPE,
53491  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_14_WIDTH },
53492  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_15_CHECKER_TYPE,
53493  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_15_WIDTH },
53494  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_16_CHECKER_TYPE,
53495  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_16_WIDTH },
53496  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_17_CHECKER_TYPE,
53497  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_17_WIDTH },
53498  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_18_CHECKER_TYPE,
53499  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_18_WIDTH },
53500  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_19_CHECKER_TYPE,
53501  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_19_WIDTH },
53502  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_20_CHECKER_TYPE,
53503  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_20_WIDTH },
53504  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_21_CHECKER_TYPE,
53505  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_21_WIDTH },
53506  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_22_CHECKER_TYPE,
53507  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_22_WIDTH },
53508  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_23_CHECKER_TYPE,
53509  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_23_WIDTH },
53510  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_24_CHECKER_TYPE,
53511  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_24_WIDTH },
53512  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_25_CHECKER_TYPE,
53513  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_25_WIDTH },
53514  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_26_CHECKER_TYPE,
53515  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_26_WIDTH },
53516  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_27_CHECKER_TYPE,
53517  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_27_WIDTH },
53518  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_28_CHECKER_TYPE,
53519  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_28_WIDTH },
53520  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_29_CHECKER_TYPE,
53521  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_29_WIDTH },
53522  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_30_CHECKER_TYPE,
53523  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_30_WIDTH },
53524  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_31_CHECKER_TYPE,
53525  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_31_WIDTH },
53526  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_32_CHECKER_TYPE,
53527  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_32_WIDTH },
53528  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_33_CHECKER_TYPE,
53529  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_33_WIDTH },
53530  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_34_CHECKER_TYPE,
53531  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_34_WIDTH },
53532  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_35_CHECKER_TYPE,
53533  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_35_WIDTH },
53534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_36_CHECKER_TYPE,
53535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_36_WIDTH },
53536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_37_CHECKER_TYPE,
53537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_37_WIDTH },
53538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_38_CHECKER_TYPE,
53539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_38_WIDTH },
53540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_39_CHECKER_TYPE,
53541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_39_WIDTH },
53542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_40_CHECKER_TYPE,
53543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_40_WIDTH },
53544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_41_CHECKER_TYPE,
53545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_41_WIDTH },
53546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_42_CHECKER_TYPE,
53547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_42_WIDTH },
53548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_43_CHECKER_TYPE,
53549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_43_WIDTH },
53550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_44_CHECKER_TYPE,
53551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_44_WIDTH },
53552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_45_CHECKER_TYPE,
53553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_45_WIDTH },
53554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_46_CHECKER_TYPE,
53555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_46_WIDTH },
53556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_47_CHECKER_TYPE,
53557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_47_WIDTH },
53558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_48_CHECKER_TYPE,
53559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_48_WIDTH },
53560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_49_CHECKER_TYPE,
53561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_49_WIDTH },
53562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_50_CHECKER_TYPE,
53563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_50_WIDTH },
53564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_51_CHECKER_TYPE,
53565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_51_WIDTH },
53566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_52_CHECKER_TYPE,
53567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_52_WIDTH },
53568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_53_CHECKER_TYPE,
53569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_53_WIDTH },
53570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_54_CHECKER_TYPE,
53571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_54_WIDTH },
53572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_55_CHECKER_TYPE,
53573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_55_WIDTH },
53574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_56_CHECKER_TYPE,
53575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_56_WIDTH },
53576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_57_CHECKER_TYPE,
53577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_57_WIDTH },
53578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_58_CHECKER_TYPE,
53579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_58_WIDTH },
53580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_59_CHECKER_TYPE,
53581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_59_WIDTH },
53582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_60_CHECKER_TYPE,
53583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_60_WIDTH },
53584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_61_CHECKER_TYPE,
53585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_61_WIDTH },
53586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_62_CHECKER_TYPE,
53587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_62_WIDTH },
53588  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_63_CHECKER_TYPE,
53589  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_63_WIDTH },
53590  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_64_CHECKER_TYPE,
53591  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_64_WIDTH },
53592  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_65_CHECKER_TYPE,
53593  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_65_WIDTH },
53594  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_66_CHECKER_TYPE,
53595  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_66_WIDTH },
53596  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_67_CHECKER_TYPE,
53597  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_67_WIDTH },
53598  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_68_CHECKER_TYPE,
53599  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_68_WIDTH },
53600  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_69_CHECKER_TYPE,
53601  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_69_WIDTH },
53602  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_70_CHECKER_TYPE,
53603  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_70_WIDTH },
53604  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_71_CHECKER_TYPE,
53605  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_71_WIDTH },
53606  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_72_CHECKER_TYPE,
53607  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_72_WIDTH },
53608  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_73_CHECKER_TYPE,
53609  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_73_WIDTH },
53610  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_74_CHECKER_TYPE,
53611  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_74_WIDTH },
53612  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_75_CHECKER_TYPE,
53613  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_75_WIDTH },
53614  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_76_CHECKER_TYPE,
53615  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_76_WIDTH },
53616  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_77_CHECKER_TYPE,
53617  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_77_WIDTH },
53618  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_78_CHECKER_TYPE,
53619  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_78_WIDTH },
53620  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_79_CHECKER_TYPE,
53621  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_79_WIDTH },
53622  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_80_CHECKER_TYPE,
53623  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_80_WIDTH },
53624  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_81_CHECKER_TYPE,
53625  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_81_WIDTH },
53626  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_82_CHECKER_TYPE,
53627  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_82_WIDTH },
53628  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_83_CHECKER_TYPE,
53629  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_83_WIDTH },
53630  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_84_CHECKER_TYPE,
53631  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_84_WIDTH },
53632  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_85_CHECKER_TYPE,
53633  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_85_WIDTH },
53634  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_86_CHECKER_TYPE,
53635  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_86_WIDTH },
53636  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_87_CHECKER_TYPE,
53637  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_87_WIDTH },
53638  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_88_CHECKER_TYPE,
53639  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_88_WIDTH },
53640  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_89_CHECKER_TYPE,
53641  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_89_WIDTH },
53642  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_90_CHECKER_TYPE,
53643  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_90_WIDTH },
53644  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_91_CHECKER_TYPE,
53645  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_91_WIDTH },
53646  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_92_CHECKER_TYPE,
53647  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_92_WIDTH },
53648  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_93_CHECKER_TYPE,
53649  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_93_WIDTH },
53650  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_94_CHECKER_TYPE,
53651  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_94_WIDTH },
53652  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_95_CHECKER_TYPE,
53653  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_95_WIDTH },
53654  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_96_CHECKER_TYPE,
53655  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_96_WIDTH },
53656  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_97_CHECKER_TYPE,
53657  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_97_WIDTH },
53658  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_98_CHECKER_TYPE,
53659  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_98_WIDTH },
53660  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_99_CHECKER_TYPE,
53661  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_99_WIDTH },
53662  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_100_CHECKER_TYPE,
53663  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_100_WIDTH },
53664  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_101_CHECKER_TYPE,
53665  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_101_WIDTH },
53666  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_102_CHECKER_TYPE,
53667  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_102_WIDTH },
53668  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_103_CHECKER_TYPE,
53669  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_103_WIDTH },
53670  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_104_CHECKER_TYPE,
53671  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_104_WIDTH },
53672  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_105_CHECKER_TYPE,
53673  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_105_WIDTH },
53674  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_106_CHECKER_TYPE,
53675  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_106_WIDTH },
53676  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_107_CHECKER_TYPE,
53677  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_107_WIDTH },
53678  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_108_CHECKER_TYPE,
53679  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_108_WIDTH },
53680  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_109_CHECKER_TYPE,
53681  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_109_WIDTH },
53682  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_110_CHECKER_TYPE,
53683  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_110_WIDTH },
53684  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_111_CHECKER_TYPE,
53685  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_111_WIDTH },
53686  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_112_CHECKER_TYPE,
53687  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_112_WIDTH },
53688  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_113_CHECKER_TYPE,
53689  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_113_WIDTH },
53690  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_114_CHECKER_TYPE,
53691  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_114_WIDTH },
53692  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_115_CHECKER_TYPE,
53693  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_115_WIDTH },
53694  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_116_CHECKER_TYPE,
53695  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_116_WIDTH },
53696  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_117_CHECKER_TYPE,
53697  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_117_WIDTH },
53698  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_118_CHECKER_TYPE,
53699  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_118_WIDTH },
53700  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_119_CHECKER_TYPE,
53701  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_119_WIDTH },
53702  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_120_CHECKER_TYPE,
53703  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_120_WIDTH },
53704  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_121_CHECKER_TYPE,
53705  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_121_WIDTH },
53706  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_122_CHECKER_TYPE,
53707  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_122_WIDTH },
53708  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_123_CHECKER_TYPE,
53709  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_123_WIDTH },
53710  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_124_CHECKER_TYPE,
53711  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_124_WIDTH },
53712  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_125_CHECKER_TYPE,
53713  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_125_WIDTH },
53714  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_126_CHECKER_TYPE,
53715  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_126_WIDTH },
53716  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_127_CHECKER_TYPE,
53717  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_127_WIDTH },
53718  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_128_CHECKER_TYPE,
53719  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_128_WIDTH },
53720  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_129_CHECKER_TYPE,
53721  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_129_WIDTH },
53722  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_130_CHECKER_TYPE,
53723  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_130_WIDTH },
53724  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_131_CHECKER_TYPE,
53725  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_131_WIDTH },
53726  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_132_CHECKER_TYPE,
53727  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_132_WIDTH },
53728  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_133_CHECKER_TYPE,
53729  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_133_WIDTH },
53730  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_134_CHECKER_TYPE,
53731  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_134_WIDTH },
53732  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_135_CHECKER_TYPE,
53733  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_135_WIDTH },
53734  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_136_CHECKER_TYPE,
53735  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_136_WIDTH },
53736  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_137_CHECKER_TYPE,
53737  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_137_WIDTH },
53738  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_138_CHECKER_TYPE,
53739  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_138_WIDTH },
53740  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_139_CHECKER_TYPE,
53741  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_139_WIDTH },
53742  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_140_CHECKER_TYPE,
53743  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_140_WIDTH },
53744  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_141_CHECKER_TYPE,
53745  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_141_WIDTH },
53746  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_142_CHECKER_TYPE,
53747  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_142_WIDTH },
53748  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_143_CHECKER_TYPE,
53749  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_143_WIDTH },
53750  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_144_CHECKER_TYPE,
53751  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_144_WIDTH },
53752  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_145_CHECKER_TYPE,
53753  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_145_WIDTH },
53754  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_146_CHECKER_TYPE,
53755  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_146_WIDTH },
53756  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_147_CHECKER_TYPE,
53757  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_147_WIDTH },
53758  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_148_CHECKER_TYPE,
53759  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_148_WIDTH },
53760  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_149_CHECKER_TYPE,
53761  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_149_WIDTH },
53762  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_150_CHECKER_TYPE,
53763  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_150_WIDTH },
53764  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_151_CHECKER_TYPE,
53765  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_151_WIDTH },
53766  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_152_CHECKER_TYPE,
53767  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_152_WIDTH },
53768  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_153_CHECKER_TYPE,
53769  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_153_WIDTH },
53770  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_154_CHECKER_TYPE,
53771  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_154_WIDTH },
53772  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_155_CHECKER_TYPE,
53773  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_155_WIDTH },
53774  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_156_CHECKER_TYPE,
53775  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_156_WIDTH },
53776  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_157_CHECKER_TYPE,
53777  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_157_WIDTH },
53778  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_158_CHECKER_TYPE,
53779  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_158_WIDTH },
53780  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_159_CHECKER_TYPE,
53781  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_159_WIDTH },
53782  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_160_CHECKER_TYPE,
53783  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_160_WIDTH },
53784  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_161_CHECKER_TYPE,
53785  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_161_WIDTH },
53786  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_162_CHECKER_TYPE,
53787  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_162_WIDTH },
53788  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_163_CHECKER_TYPE,
53789  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_163_WIDTH },
53790  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_164_CHECKER_TYPE,
53791  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_164_WIDTH },
53792  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_165_CHECKER_TYPE,
53793  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_165_WIDTH },
53794  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_166_CHECKER_TYPE,
53795  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_166_WIDTH },
53796  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_167_CHECKER_TYPE,
53797  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_167_WIDTH },
53798  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_168_CHECKER_TYPE,
53799  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_168_WIDTH },
53800  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_169_CHECKER_TYPE,
53801  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_169_WIDTH },
53802  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_170_CHECKER_TYPE,
53803  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_170_WIDTH },
53804  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_171_CHECKER_TYPE,
53805  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_171_WIDTH },
53806  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_172_CHECKER_TYPE,
53807  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_172_WIDTH },
53808  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_173_CHECKER_TYPE,
53809  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_173_WIDTH },
53810  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_174_CHECKER_TYPE,
53811  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_174_WIDTH },
53812  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_175_CHECKER_TYPE,
53813  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_175_WIDTH },
53814  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_176_CHECKER_TYPE,
53815  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_176_WIDTH },
53816  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_177_CHECKER_TYPE,
53817  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_177_WIDTH },
53818  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_178_CHECKER_TYPE,
53819  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_178_WIDTH },
53820  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_179_CHECKER_TYPE,
53821  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_179_WIDTH },
53822  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_180_CHECKER_TYPE,
53823  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_180_WIDTH },
53824  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_181_CHECKER_TYPE,
53825  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_181_WIDTH },
53826  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_182_CHECKER_TYPE,
53827  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_182_WIDTH },
53828  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_183_CHECKER_TYPE,
53829  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_183_WIDTH },
53830  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_184_CHECKER_TYPE,
53831  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_184_WIDTH },
53832  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_185_CHECKER_TYPE,
53833  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_185_WIDTH },
53834  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_186_CHECKER_TYPE,
53835  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_186_WIDTH },
53836  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_187_CHECKER_TYPE,
53837  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_187_WIDTH },
53838  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_188_CHECKER_TYPE,
53839  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_188_WIDTH },
53840  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_189_CHECKER_TYPE,
53841  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_189_WIDTH },
53842  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_190_CHECKER_TYPE,
53843  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_190_WIDTH },
53844  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_191_CHECKER_TYPE,
53845  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_191_WIDTH },
53846  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_192_CHECKER_TYPE,
53847  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_192_WIDTH },
53848  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_193_CHECKER_TYPE,
53849  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_193_WIDTH },
53850  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_194_CHECKER_TYPE,
53851  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_194_WIDTH },
53852  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_195_CHECKER_TYPE,
53853  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_195_WIDTH },
53854  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_196_CHECKER_TYPE,
53855  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_196_WIDTH },
53856  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_197_CHECKER_TYPE,
53857  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_197_WIDTH },
53858  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_198_CHECKER_TYPE,
53859  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_198_WIDTH },
53860  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_199_CHECKER_TYPE,
53861  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_199_WIDTH },
53862  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_200_CHECKER_TYPE,
53863  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_200_WIDTH },
53864  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_201_CHECKER_TYPE,
53865  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_201_WIDTH },
53866  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_202_CHECKER_TYPE,
53867  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_202_WIDTH },
53868  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_203_CHECKER_TYPE,
53869  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_203_WIDTH },
53870  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_204_CHECKER_TYPE,
53871  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_204_WIDTH },
53872  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_205_CHECKER_TYPE,
53873  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_205_WIDTH },
53874  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_206_CHECKER_TYPE,
53875  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_206_WIDTH },
53876  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_207_CHECKER_TYPE,
53877  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_207_WIDTH },
53878  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_208_CHECKER_TYPE,
53879  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_208_WIDTH },
53880  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_209_CHECKER_TYPE,
53881  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_209_WIDTH },
53882  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_210_CHECKER_TYPE,
53883  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_210_WIDTH },
53884  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_211_CHECKER_TYPE,
53885  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_211_WIDTH },
53886  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_212_CHECKER_TYPE,
53887  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_212_WIDTH },
53888  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_213_CHECKER_TYPE,
53889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_213_WIDTH },
53890  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_214_CHECKER_TYPE,
53891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_214_WIDTH },
53892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_215_CHECKER_TYPE,
53893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_215_WIDTH },
53894  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_216_CHECKER_TYPE,
53895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_216_WIDTH },
53896  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_217_CHECKER_TYPE,
53897  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_217_WIDTH },
53898  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_218_CHECKER_TYPE,
53899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_218_WIDTH },
53900  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_219_CHECKER_TYPE,
53901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_219_WIDTH },
53902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_220_CHECKER_TYPE,
53903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_220_WIDTH },
53904  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_221_CHECKER_TYPE,
53905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_221_WIDTH },
53906  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_222_CHECKER_TYPE,
53907  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_222_WIDTH },
53908  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_223_CHECKER_TYPE,
53909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_223_WIDTH },
53910  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_224_CHECKER_TYPE,
53911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_224_WIDTH },
53912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_225_CHECKER_TYPE,
53913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_225_WIDTH },
53914  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_226_CHECKER_TYPE,
53915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_226_WIDTH },
53916  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_227_CHECKER_TYPE,
53917  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_227_WIDTH },
53918  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_228_CHECKER_TYPE,
53919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_228_WIDTH },
53920  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_229_CHECKER_TYPE,
53921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_229_WIDTH },
53922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_230_CHECKER_TYPE,
53923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_230_WIDTH },
53924  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_231_CHECKER_TYPE,
53925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_231_WIDTH },
53926  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_232_CHECKER_TYPE,
53927  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_232_WIDTH },
53928  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_233_CHECKER_TYPE,
53929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_233_WIDTH },
53930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_234_CHECKER_TYPE,
53931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_234_WIDTH },
53932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_235_CHECKER_TYPE,
53933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_235_WIDTH },
53934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_236_CHECKER_TYPE,
53935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_236_WIDTH },
53936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_237_CHECKER_TYPE,
53937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_237_WIDTH },
53938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_238_CHECKER_TYPE,
53939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_238_WIDTH },
53940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_239_CHECKER_TYPE,
53941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_239_WIDTH },
53942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_240_CHECKER_TYPE,
53943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_240_WIDTH },
53944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_241_CHECKER_TYPE,
53945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_241_WIDTH },
53946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_242_CHECKER_TYPE,
53947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_242_WIDTH },
53948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_243_CHECKER_TYPE,
53949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_243_WIDTH },
53950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_244_CHECKER_TYPE,
53951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_244_WIDTH },
53952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_245_CHECKER_TYPE,
53953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_245_WIDTH },
53954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_246_CHECKER_TYPE,
53955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_246_WIDTH },
53956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_247_CHECKER_TYPE,
53957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_247_WIDTH },
53958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_248_CHECKER_TYPE,
53959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_248_WIDTH },
53960  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_249_CHECKER_TYPE,
53961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_249_WIDTH },
53962  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_250_CHECKER_TYPE,
53963  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_250_WIDTH },
53964  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_251_CHECKER_TYPE,
53965  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_251_WIDTH },
53966  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_252_CHECKER_TYPE,
53967  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_252_WIDTH },
53968  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_253_CHECKER_TYPE,
53969  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_253_WIDTH },
53970  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_254_CHECKER_TYPE,
53971  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_254_WIDTH },
53972  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_255_CHECKER_TYPE,
53973  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_GROUP_255_WIDTH },
53974 };
53975 
53981 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS] =
53982 {
53983  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_0_CHECKER_TYPE,
53984  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_0_WIDTH },
53985  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_1_CHECKER_TYPE,
53986  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_1_WIDTH },
53987  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_2_CHECKER_TYPE,
53988  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_2_WIDTH },
53989  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_3_CHECKER_TYPE,
53990  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_3_WIDTH },
53991  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_4_CHECKER_TYPE,
53992  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_4_WIDTH },
53993  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_5_CHECKER_TYPE,
53994  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_5_WIDTH },
53995  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_6_CHECKER_TYPE,
53996  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_6_WIDTH },
53997  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_7_CHECKER_TYPE,
53998  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_7_WIDTH },
53999  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_8_CHECKER_TYPE,
54000  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_8_WIDTH },
54001  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_9_CHECKER_TYPE,
54002  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_9_WIDTH },
54003  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_10_CHECKER_TYPE,
54004  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_10_WIDTH },
54005  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_11_CHECKER_TYPE,
54006  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_11_WIDTH },
54007  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_12_CHECKER_TYPE,
54008  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_12_WIDTH },
54009  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_13_CHECKER_TYPE,
54010  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_13_WIDTH },
54011  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_14_CHECKER_TYPE,
54012  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_14_WIDTH },
54013  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_15_CHECKER_TYPE,
54014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_15_WIDTH },
54015  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_16_CHECKER_TYPE,
54016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_16_WIDTH },
54017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_17_CHECKER_TYPE,
54018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_17_WIDTH },
54019  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_18_CHECKER_TYPE,
54020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_18_WIDTH },
54021  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_19_CHECKER_TYPE,
54022  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_19_WIDTH },
54023  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_20_CHECKER_TYPE,
54024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_20_WIDTH },
54025  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_21_CHECKER_TYPE,
54026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_21_WIDTH },
54027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_22_CHECKER_TYPE,
54028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_22_WIDTH },
54029  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_23_CHECKER_TYPE,
54030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_23_WIDTH },
54031  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_24_CHECKER_TYPE,
54032  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_24_WIDTH },
54033  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_25_CHECKER_TYPE,
54034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_25_WIDTH },
54035  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_26_CHECKER_TYPE,
54036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_26_WIDTH },
54037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_27_CHECKER_TYPE,
54038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_27_WIDTH },
54039  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_28_CHECKER_TYPE,
54040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_28_WIDTH },
54041  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_29_CHECKER_TYPE,
54042  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_29_WIDTH },
54043  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_30_CHECKER_TYPE,
54044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_30_WIDTH },
54045  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_31_CHECKER_TYPE,
54046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_31_WIDTH },
54047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_32_CHECKER_TYPE,
54048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_32_WIDTH },
54049  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_33_CHECKER_TYPE,
54050  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_33_WIDTH },
54051  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_34_CHECKER_TYPE,
54052  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_34_WIDTH },
54053  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_35_CHECKER_TYPE,
54054  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_35_WIDTH },
54055  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_36_CHECKER_TYPE,
54056  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_36_WIDTH },
54057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_37_CHECKER_TYPE,
54058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_37_WIDTH },
54059  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_38_CHECKER_TYPE,
54060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_38_WIDTH },
54061  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_39_CHECKER_TYPE,
54062  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_39_WIDTH },
54063  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_40_CHECKER_TYPE,
54064  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_40_WIDTH },
54065  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_41_CHECKER_TYPE,
54066  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_GROUP_41_WIDTH },
54067 };
54068 
54074 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
54075 {
54076  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
54077  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
54078  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
54079  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
54080  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
54081  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
54082  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
54083  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
54084  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
54085  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
54086  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
54087  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
54088  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
54089  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
54090  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
54091  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
54092  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
54093  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
54094  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
54095  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
54096  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
54097  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
54098  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
54099  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
54100  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
54101  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
54102  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
54103  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
54104  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
54105  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
54106  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
54107  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
54108  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
54109  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
54110  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
54111  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
54112  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
54113  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
54114  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
54115  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
54116  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
54117  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
54118  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
54119  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
54120  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
54121  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
54122  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
54123  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
54124  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
54125  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
54126  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
54127  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
54128  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
54129  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
54130  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
54131  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
54132  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
54133  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
54134  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
54135  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
54136  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
54137  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
54138  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
54139  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
54140  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
54141  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
54142  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
54143  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
54144  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
54145  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
54146  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
54147  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
54148  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
54149  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
54150  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
54151  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
54152  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
54153  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
54154  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
54155  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
54156  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
54157  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
54158  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
54159  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
54160  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
54161  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
54162  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
54163  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
54164  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
54165  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
54166  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
54167  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
54168  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
54169  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
54170  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
54171  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
54172  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
54173  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
54174  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
54175  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
54176  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
54177  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
54178  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
54179  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
54180  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
54181  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
54182  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
54183  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
54184  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
54185  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
54186  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
54187  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
54188  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
54189  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
54190  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
54191  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
54192  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
54193  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
54194  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
54195  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
54196  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
54197  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
54198  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
54199  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
54200  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
54201  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
54202  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
54203  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
54204  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
54205  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
54206  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
54207  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
54208  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
54209  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
54210  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
54211  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
54212  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
54213  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
54214  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
54215  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
54216  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
54217  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
54218  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
54219  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
54220  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
54221  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
54222  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
54223  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
54224  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
54225  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
54226  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
54227  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
54228  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
54229  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
54230  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
54231  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
54232  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
54233  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
54234  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
54235  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
54236  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
54237  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
54238  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
54239  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
54240  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
54241  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
54242  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
54243  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
54244  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
54245  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
54246  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
54247  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
54248  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
54249  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
54250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
54251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
54252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
54253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
54254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
54255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
54256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
54257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
54258  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
54259  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
54260  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
54261  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
54262  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
54263  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
54264  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
54265  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
54266  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
54267  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
54268  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
54269  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
54270  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
54271  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
54272  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
54273  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
54274  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
54275  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
54276  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
54277  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
54278  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
54279  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
54280  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
54281  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
54282  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
54283  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
54284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
54285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
54286  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
54287  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
54288  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
54289  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
54290  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
54291  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
54292  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
54293  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
54294  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
54295  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
54296  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
54297  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
54298  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
54299  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
54300  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
54301  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
54302  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
54303  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
54304  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
54305  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
54306  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
54307  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
54308  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
54309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
54310  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
54311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
54312  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
54313  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
54314  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
54315  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
54316  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
54317  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
54318  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
54319  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
54320  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
54321  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
54322  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
54323  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
54324  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
54325  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
54326  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
54327  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
54328  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
54329  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
54330  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
54331  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
54332  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
54333  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
54334  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
54335  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
54336  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
54337  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
54338  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
54339  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
54340  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
54341  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
54342  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
54343  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
54344  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
54345  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
54346  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
54347  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
54348  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
54349  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
54350  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
54351  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
54352  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
54353  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
54354  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
54355  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
54356  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
54357  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
54358  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
54359  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
54360  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
54361  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
54362  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
54363  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
54364  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
54365  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
54366  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
54367  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
54368  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
54369  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
54370  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
54371  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
54372  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
54373  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
54374  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
54375  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
54376  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
54377  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
54378  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
54379  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
54380  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
54381  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
54382  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
54383  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
54384  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
54385  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
54386  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
54387  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
54388  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
54389  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
54390  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
54391  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
54392  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
54393  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
54394  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
54395  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
54396  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
54397  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
54398  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
54399  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
54400  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
54401  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
54402  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
54403  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
54404  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
54405  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
54406  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
54407  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
54408  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
54409  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
54410  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
54411  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
54412  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
54413  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
54414  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
54415  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
54416  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
54417  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
54418  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
54419  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
54420  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
54421  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
54422  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
54423  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
54424  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
54425  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
54426  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
54427  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
54428  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
54429  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
54430  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
54431  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
54432  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
54433  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
54434  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
54435  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
54436  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
54437  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
54438  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
54439  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
54440  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
54441  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
54442  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
54443  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
54444  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
54445  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
54446  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
54447  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
54448  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
54449  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
54450  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
54451  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
54452  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
54453  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
54454  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
54455  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
54456  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
54457  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
54458  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
54459  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
54460  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
54461  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
54462  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
54463  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
54464  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
54465  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
54466  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
54467  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
54468  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
54469  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
54470  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
54471  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
54472  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
54473  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
54474  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
54475  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
54476  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
54477  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
54478  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
54479  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
54480  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
54481  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
54482  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
54483  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
54484  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
54485  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
54486  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
54487  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
54488  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
54489  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
54490  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
54491  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
54492  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
54493  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
54494  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
54495  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
54496  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
54497  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
54498  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
54499  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
54500  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
54501  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
54502  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
54503  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
54504  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
54505  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
54506  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
54507  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
54508  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
54509  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
54510  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
54511  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
54512  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
54513  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
54514  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
54515  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
54516  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
54517  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
54518  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
54519  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
54520  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
54521  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
54522  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
54523  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
54524  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
54525  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
54526  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
54527  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
54528  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
54529  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
54530  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
54531  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
54532  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
54533  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
54534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
54535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
54536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
54537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
54538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
54539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
54540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
54541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
54542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
54543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
54544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
54545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
54546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
54547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
54548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
54549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
54550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
54551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
54552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
54553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
54554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
54555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
54556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
54557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
54558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
54559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
54560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
54561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
54562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
54563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
54564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
54565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
54566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
54567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
54568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
54569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
54570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
54571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
54572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
54573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
54574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
54575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
54576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
54577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
54578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
54579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
54580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
54581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
54582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
54583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
54584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
54585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
54586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
54587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
54588 };
54589 
54595 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
54596 {
54597  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
54598  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
54599  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
54600  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
54601  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
54602  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
54603  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
54604  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
54605  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
54606  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
54607  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
54608  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
54609  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
54610  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
54611  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
54612  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
54613  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
54614  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
54615  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
54616  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
54617  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
54618  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
54619  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
54620  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
54621  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
54622  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
54623  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
54624  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
54625  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
54626  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
54627  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
54628  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
54629  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
54630  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
54631  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
54632  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
54633  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
54634  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
54635  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
54636  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
54637  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
54638  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
54639  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
54640  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
54641  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
54642  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
54643  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
54644  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
54645  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
54646  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
54647  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
54648  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
54649  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
54650  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
54651  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
54652  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
54653  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
54654  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
54655  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
54656  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
54657  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
54658  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
54659  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
54660  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
54661  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
54662  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
54663  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
54664  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
54665  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
54666  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
54667  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
54668  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
54669  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
54670  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
54671  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
54672  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
54673  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
54674  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
54675  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
54676  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
54677  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
54678  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
54679  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
54680  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
54681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
54682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
54683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
54684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
54685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
54686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
54687  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
54688  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
54689  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
54690  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
54691  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
54692  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
54693  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
54694  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
54695  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
54696  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
54697  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
54698  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
54699  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
54700  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
54701  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
54702  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
54703  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
54704  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
54705  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
54706  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
54707  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
54708  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
54709  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
54710  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
54711  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
54712  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
54713  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
54714  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
54715  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
54716  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
54717  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
54718  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
54719  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
54720  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
54721  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
54722  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
54723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
54724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
54725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
54726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
54727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
54728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
54729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
54730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
54731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
54732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
54733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
54734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
54735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
54736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
54737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
54738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
54739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
54740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
54741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
54742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
54743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
54744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
54745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
54746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
54747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
54748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
54749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
54750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
54751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
54752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
54753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
54754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
54755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
54756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
54757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
54758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
54759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
54760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
54761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
54762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
54763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
54764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
54765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
54766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
54767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
54768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
54769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
54770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
54771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
54772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
54773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
54774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
54775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
54776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
54777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
54778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
54779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
54780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
54781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
54782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
54783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
54784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
54785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
54786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
54787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
54788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
54789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
54790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
54791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
54792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
54793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
54794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
54795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
54796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
54797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
54798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
54799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
54800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
54801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
54802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
54803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
54804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
54805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
54806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
54807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
54808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
54809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
54810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
54811  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
54812  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
54813  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
54814  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
54815  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
54816  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
54817  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
54818  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
54819  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
54820  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
54821  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
54822  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
54823  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
54824  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
54825  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
54826  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
54827  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
54828  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
54829  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
54830  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
54831  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
54832  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
54833  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
54834  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
54835  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
54836  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
54837  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
54838  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
54839  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
54840  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
54841  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
54842  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
54843  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
54844  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
54845  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
54846  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
54847  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
54848  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
54849  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
54850  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
54851  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
54852  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
54853  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
54854  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
54855  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
54856  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
54857  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
54858  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
54859  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
54860  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
54861  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
54862  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
54863  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
54864  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
54865  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
54866  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
54867  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
54868  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
54869  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
54870  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
54871  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
54872  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
54873  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
54874  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
54875  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
54876  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
54877  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
54878  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
54879  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
54880  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
54881  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
54882  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
54883  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
54884  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
54885  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
54886  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
54887  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
54888  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
54889  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
54890  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
54891  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
54892  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
54893  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
54894  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
54895  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
54896  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
54897  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
54898  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
54899  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
54900  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
54901  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
54902  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
54903  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
54904  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
54905  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
54906  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
54907  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
54908  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
54909  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
54910  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
54911  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
54912  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
54913  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
54914  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
54915  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
54916  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
54917  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
54918  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
54919  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
54920  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
54921  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
54922  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
54923  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
54924  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
54925  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
54926  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
54927  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
54928  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
54929  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
54930  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
54931  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
54932  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
54933  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
54934  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
54935  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
54936  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
54937  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
54938  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
54939  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
54940  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
54941  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
54942  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
54943  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
54944  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
54945  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
54946  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
54947  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
54948  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
54949  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
54950  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
54951  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
54952  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
54953  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
54954  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
54955  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
54956  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
54957  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
54958  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
54959  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
54960  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
54961  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
54962  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
54963  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
54964  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
54965  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
54966  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
54967  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
54968  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
54969  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
54970  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
54971  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
54972  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
54973  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
54974  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
54975  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
54976  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
54977  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
54978  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
54979  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
54980  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
54981  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
54982  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
54983  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
54984  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
54985  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
54986  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
54987  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
54988  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
54989  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
54990  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
54991  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
54992  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
54993  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
54994  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
54995  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
54996  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
54997  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
54998  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
54999  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
55000  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
55001  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
55002  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
55003  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
55004  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
55005  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
55006  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
55007  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
55008  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
55009  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
55010  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
55011  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
55012  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
55013  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
55014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
55015  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
55016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
55017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
55018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
55019  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
55020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
55021  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
55022  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
55023  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
55024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
55025  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
55026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
55027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
55028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
55029  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
55030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
55031  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
55032  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
55033  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
55034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
55035  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
55036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
55037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
55038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
55039  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
55040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
55041  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
55042  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
55043  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
55044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
55045  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
55046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
55047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
55048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
55049  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
55050  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
55051  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
55052  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
55053  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
55054  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
55055  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
55056  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
55057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
55058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
55059  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
55060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
55061  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
55062  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
55063  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
55064  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
55065  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
55066  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
55067  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
55068  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
55069  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
55070  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
55071  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
55072  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
55073  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
55074  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
55075  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
55076  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
55077  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
55078  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
55079  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
55080  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
55081  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
55082  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
55083  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
55084  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
55085  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
55086  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
55087  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
55088  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
55089  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
55090  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
55091  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
55092  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
55093  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
55094  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
55095  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
55096  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
55097  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
55098  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
55099  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
55100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
55101  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
55102  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
55103  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
55104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
55105  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
55106  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
55107  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
55108  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
55109 };
55110 
55116 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
55117 {
55118  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
55119  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
55120  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
55121  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
55122  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
55123  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
55124  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
55125  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
55126  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
55127  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
55128  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
55129  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
55130  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
55131  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
55132  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
55133  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
55134  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
55135  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
55136  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
55137  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
55138  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
55139  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
55140  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
55141  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
55142  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
55143  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
55144  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
55145  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
55146  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
55147  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
55148  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
55149  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
55150  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
55151  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
55152  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
55153  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
55154  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
55155  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
55156  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
55157  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
55158  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
55159  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
55160  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
55161  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
55162  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
55163  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
55164  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
55165  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
55166  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
55167  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
55168  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
55169  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
55170  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
55171  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
55172  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
55173  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
55174  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
55175  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
55176  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
55177  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
55178  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
55179  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
55180  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
55181  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
55182  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
55183  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
55184  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
55185  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
55186  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
55187  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
55188  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
55189  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
55190  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
55191  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
55192  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
55193  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
55194  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
55195  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
55196  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
55197  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
55198  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
55199  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
55200  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
55201  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
55202  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
55203  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
55204  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
55205  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
55206  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
55207  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
55208  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
55209  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
55210  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
55211  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
55212  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
55213  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
55214  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
55215  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
55216  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
55217  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
55218  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
55219  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
55220  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
55221  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
55222  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
55223  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
55224  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
55225  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
55226  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
55227  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
55228  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
55229  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
55230  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
55231  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
55232  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
55233  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
55234  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
55235  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
55236  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
55237  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
55238  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
55239  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
55240  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
55241  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
55242  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
55243  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
55244  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
55245  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
55246  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
55247  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
55248  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
55249  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
55250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
55251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
55252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
55253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
55254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
55255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
55256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
55257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
55258  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
55259  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
55260  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
55261  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
55262  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
55263  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
55264  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
55265  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
55266  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
55267  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
55268  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
55269  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
55270  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
55271  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
55272  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
55273  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
55274  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
55275  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
55276  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
55277  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
55278  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
55279  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
55280  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
55281  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
55282  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
55283  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
55284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
55285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
55286  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
55287  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
55288  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
55289  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
55290  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
55291  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
55292  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
55293  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
55294  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
55295  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
55296  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
55297  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
55298  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
55299  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
55300  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
55301  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
55302  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
55303  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
55304  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
55305  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
55306  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
55307  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
55308  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
55309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
55310  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
55311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
55312  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
55313  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
55314  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
55315  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
55316  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
55317  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
55318  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
55319  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
55320  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
55321  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
55322  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
55323  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
55324  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
55325  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
55326  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
55327  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
55328  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
55329  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
55330  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
55331  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
55332  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
55333  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
55334  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
55335  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
55336  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
55337  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
55338  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
55339  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
55340  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
55341  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
55342  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
55343  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
55344  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
55345  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
55346  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
55347  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
55348  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
55349  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
55350  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
55351  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
55352  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
55353  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
55354  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
55355  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
55356  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
55357  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
55358  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
55359  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
55360  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
55361  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
55362  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
55363  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
55364  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
55365  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
55366  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
55367  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
55368  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
55369  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
55370  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
55371  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
55372  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
55373  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
55374  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
55375  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
55376  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
55377  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
55378  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
55379  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
55380  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
55381  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
55382  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
55383  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
55384  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
55385  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
55386  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
55387  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
55388  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
55389  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
55390  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
55391  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
55392  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
55393  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
55394  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
55395  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
55396  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
55397  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
55398  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
55399  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
55400  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
55401  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
55402  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
55403  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
55404  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
55405  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
55406  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
55407  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
55408  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
55409  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
55410  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
55411  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
55412  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
55413  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
55414  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
55415  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
55416  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
55417  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
55418  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
55419  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
55420  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
55421  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
55422  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
55423  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
55424  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
55425  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
55426  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
55427  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
55428  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
55429  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
55430  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
55431  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
55432  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
55433  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
55434  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
55435  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
55436  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
55437  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
55438  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
55439  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
55440  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
55441  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
55442  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
55443  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
55444  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
55445  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
55446  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
55447  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
55448  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
55449  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
55450  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
55451  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
55452  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
55453  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
55454  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
55455  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
55456  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
55457  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
55458  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
55459  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
55460  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
55461  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
55462  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
55463  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
55464  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
55465  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
55466  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
55467  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
55468  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
55469  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
55470  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
55471  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
55472  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
55473  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
55474  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
55475  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
55476  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
55477  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
55478  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
55479  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
55480  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
55481  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
55482  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
55483  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
55484  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
55485  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
55486  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
55487  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
55488  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
55489  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
55490  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
55491  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
55492  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
55493  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
55494  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
55495  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
55496  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
55497  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
55498  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
55499  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
55500  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
55501  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
55502  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
55503  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
55504  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
55505  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
55506  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
55507  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
55508  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
55509  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
55510  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
55511  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
55512  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
55513  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
55514  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
55515  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
55516  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
55517  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
55518  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
55519  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
55520  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
55521  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
55522  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
55523  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
55524  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
55525  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
55526  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
55527  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
55528  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
55529  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
55530  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
55531  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
55532  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
55533  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
55534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
55535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
55536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
55537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
55538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
55539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
55540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
55541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
55542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
55543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
55544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
55545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
55546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
55547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
55548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
55549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
55550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
55551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
55552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
55553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
55554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
55555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
55556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
55557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
55558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
55559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
55560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
55561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
55562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
55563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
55564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
55565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
55566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
55567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
55568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
55569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
55570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
55571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
55572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
55573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
55574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
55575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
55576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
55577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
55578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
55579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
55580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
55581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
55582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
55583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
55584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
55585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
55586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
55587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
55588  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
55589  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
55590  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
55591  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
55592  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
55593  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
55594  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
55595  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
55596  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
55597  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
55598  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
55599  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
55600  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
55601  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
55602  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
55603  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
55604  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
55605  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
55606  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
55607  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
55608  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
55609  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
55610  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
55611  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
55612  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
55613  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
55614  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
55615  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
55616  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
55617  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
55618  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
55619  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
55620  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
55621  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
55622  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
55623  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
55624  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
55625  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
55626  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
55627  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
55628  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
55629  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
55630 };
55631 
55637 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
55638 {
55639  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
55640  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
55641  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
55642  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
55643  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
55644  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
55645  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
55646  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
55647  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
55648  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
55649  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
55650  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
55651  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
55652  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
55653  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
55654  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
55655  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
55656  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
55657  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
55658  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
55659  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
55660  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
55661  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
55662  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
55663  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
55664  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
55665  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
55666  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
55667  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
55668  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
55669  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
55670  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
55671  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
55672  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
55673  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
55674  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
55675  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
55676  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
55677  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
55678  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
55679  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
55680  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
55681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
55682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
55683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
55684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
55685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
55686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
55687  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
55688  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
55689  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
55690  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
55691  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
55692  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
55693  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
55694  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
55695  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
55696  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
55697  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
55698  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
55699  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
55700  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
55701  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
55702  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
55703  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
55704  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
55705  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
55706  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
55707  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
55708  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
55709  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
55710  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
55711  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
55712  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
55713  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
55714  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
55715  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
55716  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
55717  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
55718  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
55719  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
55720  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
55721  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
55722  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
55723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
55724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
55725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
55726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
55727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
55728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
55729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
55730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
55731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
55732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
55733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
55734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
55735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
55736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
55737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
55738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
55739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
55740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
55741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
55742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
55743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
55744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
55745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
55746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
55747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
55748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
55749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
55750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
55751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
55752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
55753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
55754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
55755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
55756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
55757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
55758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
55759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
55760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
55761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
55762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
55763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
55764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
55765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
55766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
55767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
55768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
55769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
55770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
55771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
55772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
55773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
55774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
55775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
55776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
55777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
55778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
55779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
55780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
55781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
55782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
55783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
55784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
55785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
55786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
55787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
55788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
55789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
55790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
55791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
55792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
55793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
55794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
55795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
55796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
55797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
55798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
55799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
55800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
55801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
55802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
55803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
55804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
55805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
55806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
55807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
55808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
55809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
55810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
55811  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
55812  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
55813  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
55814  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
55815  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
55816  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
55817  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
55818  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
55819  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
55820  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
55821  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
55822  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
55823  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
55824  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
55825  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
55826  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
55827  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
55828  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
55829  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
55830  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
55831  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
55832  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
55833  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
55834  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
55835  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
55836  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
55837  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
55838  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
55839  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
55840  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
55841  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
55842  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
55843  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
55844  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
55845  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
55846  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
55847  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
55848  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
55849  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
55850  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
55851  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
55852  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
55853  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
55854  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
55855  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
55856  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
55857  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
55858  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
55859  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
55860  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
55861  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
55862  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
55863  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
55864  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
55865  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
55866  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
55867  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
55868  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
55869  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
55870  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
55871  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
55872  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
55873  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
55874  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
55875  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
55876  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
55877  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
55878  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
55879  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
55880  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
55881  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
55882  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
55883  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
55884  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
55885  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
55886  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
55887  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
55888  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
55889  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
55890  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
55891  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
55892  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
55893  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
55894  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
55895  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
55896  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
55897  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
55898  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
55899  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
55900  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
55901  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
55902  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
55903  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
55904  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
55905  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
55906  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
55907  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
55908  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
55909  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
55910  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
55911  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
55912  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
55913  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
55914  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
55915  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
55916  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
55917  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
55918  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
55919  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
55920  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
55921  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
55922  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
55923  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
55924  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
55925  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
55926  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
55927  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
55928  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
55929  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
55930  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
55931  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
55932  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
55933  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
55934  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
55935  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
55936  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
55937  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
55938  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
55939  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
55940  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
55941  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
55942  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
55943  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
55944  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
55945  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
55946  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
55947  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
55948  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
55949  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
55950  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
55951  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
55952  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
55953  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
55954  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
55955  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
55956  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
55957  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
55958  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
55959  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
55960  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
55961  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
55962  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
55963  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
55964  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
55965  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
55966  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
55967  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
55968  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
55969  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
55970  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
55971  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
55972  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
55973  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
55974  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
55975  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
55976  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
55977  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
55978  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
55979  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
55980  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
55981  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
55982  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
55983  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
55984  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
55985  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
55986  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
55987  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
55988  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
55989  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
55990  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
55991  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
55992  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
55993  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
55994  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
55995  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
55996  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
55997  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
55998  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
55999  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
56000  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
56001  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
56002  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
56003  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
56004  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
56005  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
56006  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
56007  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
56008  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
56009  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
56010  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
56011  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
56012  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
56013  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
56014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
56015  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
56016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
56017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
56018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
56019  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
56020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
56021  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
56022  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
56023  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
56024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
56025  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
56026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
56027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
56028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
56029  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
56030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
56031  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
56032  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
56033  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
56034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
56035  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
56036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
56037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
56038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
56039  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
56040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
56041  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
56042  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
56043  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
56044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
56045  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
56046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
56047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
56048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
56049  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
56050  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
56051  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
56052  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
56053  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
56054  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
56055  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
56056  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
56057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
56058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
56059  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
56060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
56061  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
56062  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
56063  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
56064  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
56065  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
56066  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
56067  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
56068  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
56069  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
56070  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
56071  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
56072  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
56073  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
56074  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
56075  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
56076  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
56077  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
56078  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
56079  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
56080  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
56081  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
56082  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
56083  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
56084  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
56085  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
56086  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
56087  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
56088  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
56089  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
56090  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
56091  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
56092  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
56093  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
56094  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
56095  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
56096  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
56097  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
56098  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
56099  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
56100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
56101  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
56102  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
56103  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
56104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
56105  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
56106  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
56107  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
56108  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
56109  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
56110  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
56111  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
56112  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
56113  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
56114  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
56115  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
56116  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
56117  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
56118  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
56119  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
56120  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
56121  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
56122  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
56123  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
56124  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
56125  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
56126  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
56127  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
56128  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
56129  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
56130  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
56131  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
56132  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
56133  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
56134  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
56135  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
56136  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
56137  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
56138  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
56139  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
56140  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
56141  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
56142  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
56143  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
56144  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
56145  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
56146  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
56147  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
56148  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
56149  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
56150  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
56151 };
56152 
56158 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
56159 {
56160  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
56161  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
56162  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
56163  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
56164  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
56165  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
56166  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
56167  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
56168  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
56169  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
56170  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
56171  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
56172  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
56173  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
56174  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
56175  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
56176  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
56177  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
56178  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
56179  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
56180  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
56181  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
56182  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
56183  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
56184  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
56185  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
56186  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
56187  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
56188  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
56189  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
56190  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
56191  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
56192  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
56193  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
56194  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
56195  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
56196  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
56197  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
56198  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
56199  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
56200  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
56201  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
56202  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
56203  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
56204  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
56205  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
56206  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
56207  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
56208  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
56209  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
56210  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
56211  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
56212  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
56213  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
56214  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
56215  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
56216  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
56217  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
56218  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
56219  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
56220  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
56221  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
56222  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
56223  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
56224  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
56225  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
56226  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
56227  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
56228  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
56229  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
56230  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
56231  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
56232  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
56233  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
56234  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
56235  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
56236  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
56237  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
56238  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
56239  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
56240  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
56241  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
56242  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
56243  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
56244  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
56245  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
56246  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
56247  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
56248  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
56249  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
56250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
56251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
56252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
56253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
56254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
56255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
56256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
56257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
56258  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
56259  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
56260  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
56261  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
56262  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
56263  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
56264  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
56265  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
56266  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
56267  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
56268  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
56269  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
56270  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
56271  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
56272  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
56273  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
56274  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
56275  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
56276  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
56277  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
56278  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
56279  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
56280  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
56281  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
56282  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
56283  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
56284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
56285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
56286  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
56287  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
56288  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
56289  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
56290  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
56291  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
56292  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
56293  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
56294  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
56295  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
56296  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
56297  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
56298  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
56299  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
56300  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
56301  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
56302  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
56303  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
56304  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
56305  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
56306  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
56307  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
56308  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
56309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
56310  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
56311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
56312  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
56313  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
56314  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
56315  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
56316  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
56317  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
56318  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
56319  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
56320  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
56321  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
56322  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
56323  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
56324  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
56325  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
56326  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
56327  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
56328  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
56329  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
56330  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
56331  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
56332  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
56333  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
56334  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
56335  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
56336  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
56337  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
56338  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
56339  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
56340  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
56341  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
56342  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
56343  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
56344  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
56345  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
56346  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
56347  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
56348  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
56349  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
56350  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
56351  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
56352  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
56353  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
56354  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
56355  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
56356  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
56357  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
56358  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
56359  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
56360  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
56361  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
56362  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
56363  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
56364  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
56365  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
56366  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
56367  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
56368  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
56369  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
56370  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
56371  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
56372  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
56373  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
56374  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
56375  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
56376  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
56377  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
56378  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
56379  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
56380  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
56381  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
56382  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
56383  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
56384  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
56385  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
56386  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
56387  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
56388  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
56389  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
56390  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
56391  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
56392  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
56393  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
56394  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
56395  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
56396  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
56397  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
56398  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
56399  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
56400  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
56401  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
56402  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
56403  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
56404  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
56405  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
56406  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
56407  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
56408  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
56409  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
56410  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
56411  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
56412  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
56413  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
56414  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
56415  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
56416  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
56417  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
56418  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
56419  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
56420  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
56421  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
56422  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
56423  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
56424  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
56425  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
56426  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
56427  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
56428  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
56429  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
56430  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
56431  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
56432  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
56433  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
56434  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
56435  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
56436  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
56437  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
56438  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
56439  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
56440  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
56441  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
56442  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
56443  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
56444  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
56445  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
56446  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
56447  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
56448  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
56449  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
56450  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
56451  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
56452  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
56453  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
56454  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
56455  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
56456  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
56457  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
56458  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
56459  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
56460  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
56461  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
56462  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
56463  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
56464  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
56465  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
56466  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
56467  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
56468  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
56469  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
56470  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
56471  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
56472  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
56473  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
56474  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
56475  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
56476  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
56477  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
56478  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
56479  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
56480  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
56481  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
56482  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
56483  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
56484  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
56485  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
56486  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
56487  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
56488  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
56489  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
56490  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
56491  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
56492  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
56493  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
56494  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
56495  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
56496  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
56497  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
56498  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
56499  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
56500  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
56501  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
56502  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
56503  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
56504  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
56505  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
56506  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
56507  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
56508  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
56509  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
56510  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
56511  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
56512  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
56513  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
56514  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
56515  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
56516  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
56517  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
56518  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
56519  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
56520  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
56521  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
56522  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
56523  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
56524  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
56525  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
56526  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
56527  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
56528  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
56529  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
56530  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
56531  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
56532  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
56533  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
56534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
56535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
56536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
56537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
56538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
56539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
56540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
56541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
56542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
56543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
56544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
56545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
56546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
56547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
56548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
56549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
56550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
56551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
56552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
56553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
56554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
56555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
56556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
56557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
56558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
56559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
56560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
56561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
56562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
56563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
56564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
56565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
56566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
56567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
56568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
56569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
56570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
56571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
56572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
56573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
56574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
56575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
56576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
56577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
56578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
56579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
56580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
56581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
56582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
56583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
56584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
56585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
56586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
56587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
56588  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
56589  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
56590  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
56591  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
56592  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
56593  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
56594  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
56595  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
56596  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
56597  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
56598  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
56599  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
56600  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
56601  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
56602  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
56603  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
56604  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
56605  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
56606  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
56607  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
56608  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
56609  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
56610  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
56611  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
56612  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
56613  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
56614  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
56615  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
56616  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
56617  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
56618  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
56619  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
56620  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
56621  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
56622  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
56623  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
56624  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
56625  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
56626  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
56627  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
56628  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
56629  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
56630  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
56631  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
56632  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
56633  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
56634  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
56635  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
56636  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
56637  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
56638  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
56639  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
56640  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
56641  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
56642  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
56643  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
56644  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
56645  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
56646  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
56647  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
56648  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
56649  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
56650  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
56651  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
56652  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
56653  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
56654  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
56655  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
56656  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
56657  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
56658  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
56659  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
56660  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
56661  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
56662  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
56663  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
56664  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
56665  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
56666  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
56667  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
56668  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
56669  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
56670  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
56671  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
56672 };
56673 
56679 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
56680 {
56681  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
56682  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
56683  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
56684  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
56685  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
56686  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
56687  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
56688  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
56689  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
56690  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
56691  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
56692  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
56693  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
56694  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
56695  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
56696  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
56697  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
56698  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
56699  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
56700  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
56701  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
56702  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
56703  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
56704  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
56705  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
56706  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
56707  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
56708  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
56709  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
56710  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
56711  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
56712  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
56713  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
56714  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
56715  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
56716  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
56717  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
56718  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
56719  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
56720  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
56721  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
56722  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
56723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
56724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
56725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
56726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
56727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
56728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
56729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
56730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
56731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
56732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
56733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
56734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
56735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
56736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
56737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
56738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
56739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
56740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
56741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
56742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
56743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
56744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
56745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
56746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
56747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
56748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
56749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
56750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
56751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
56752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
56753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
56754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
56755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
56756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
56757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
56758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
56759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
56760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
56761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
56762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
56763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
56764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
56765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
56766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
56767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
56768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
56769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
56770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
56771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
56772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
56773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
56774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
56775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
56776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
56777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
56778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
56779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
56780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
56781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
56782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
56783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
56784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
56785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
56786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
56787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
56788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
56789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
56790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
56791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
56792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
56793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
56794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
56795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
56796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
56797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
56798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
56799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
56800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
56801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
56802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
56803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
56804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
56805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
56806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
56807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
56808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
56809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
56810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
56811  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
56812  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
56813  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
56814  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
56815  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
56816  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
56817  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
56818  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
56819  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
56820  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
56821  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
56822  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
56823  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
56824  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
56825  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
56826  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
56827  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
56828  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
56829  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
56830  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
56831  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
56832  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
56833  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
56834  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
56835  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
56836  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
56837  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
56838  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
56839  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
56840  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
56841  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
56842  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
56843  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
56844  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
56845  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
56846  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
56847  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
56848  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
56849  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
56850  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
56851  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
56852  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
56853  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
56854  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
56855  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
56856  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
56857  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
56858  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
56859  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
56860  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
56861  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
56862  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
56863  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
56864  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
56865  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
56866  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
56867  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
56868  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
56869  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
56870  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
56871  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
56872  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
56873  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
56874  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
56875  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
56876  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
56877  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
56878  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
56879  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
56880  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
56881  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
56882  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
56883  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
56884  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
56885  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
56886  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
56887  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
56888  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
56889  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
56890  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
56891  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
56892  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
56893  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
56894  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
56895  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
56896  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
56897  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
56898  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
56899  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
56900  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
56901  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
56902  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
56903  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
56904  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
56905  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
56906  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
56907  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
56908  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
56909  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
56910  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
56911  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
56912  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
56913  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
56914  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
56915  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
56916  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
56917  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
56918  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
56919  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
56920  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
56921  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
56922  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
56923  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
56924  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
56925  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
56926  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
56927  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
56928  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
56929  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
56930  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
56931  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
56932  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
56933  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
56934  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
56935  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
56936  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
56937  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
56938  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
56939  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
56940  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
56941  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
56942  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
56943  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
56944  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
56945  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
56946  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
56947  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
56948  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
56949  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
56950  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
56951  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
56952  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
56953  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
56954  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
56955  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
56956  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
56957  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
56958  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
56959  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
56960  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
56961  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
56962  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
56963  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
56964  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
56965  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
56966  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
56967  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
56968  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
56969  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
56970  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
56971  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
56972  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
56973  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
56974  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
56975  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
56976  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
56977  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
56978  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
56979  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
56980  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
56981  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
56982  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
56983  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
56984  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
56985  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
56986  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
56987  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
56988  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
56989  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
56990  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
56991  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
56992  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
56993  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
56994  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
56995  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
56996  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
56997  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
56998  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
56999  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
57000  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
57001  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
57002  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
57003  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
57004  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
57005  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
57006  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
57007  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
57008  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
57009  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
57010  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
57011  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
57012  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
57013  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
57014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
57015  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
57016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
57017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
57018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
57019  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
57020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
57021  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
57022  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
57023  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
57024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
57025  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
57026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
57027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
57028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
57029  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
57030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
57031  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
57032  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
57033  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
57034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
57035  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
57036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
57037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
57038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
57039  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
57040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
57041  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
57042  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
57043  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
57044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
57045  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
57046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
57047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
57048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
57049  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
57050  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
57051  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
57052  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
57053  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
57054  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
57055  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
57056  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
57057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
57058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
57059  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
57060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
57061  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
57062  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
57063  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
57064  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
57065  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
57066  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
57067  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
57068  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
57069  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
57070  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
57071  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
57072  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
57073  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
57074  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
57075  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
57076  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
57077  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
57078  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
57079  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
57080  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
57081  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
57082  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
57083  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
57084  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
57085  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
57086  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
57087  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
57088  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
57089  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
57090  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
57091  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
57092  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
57093  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
57094  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
57095  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
57096  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
57097  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
57098  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
57099  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
57100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
57101  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
57102  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
57103  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
57104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
57105  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
57106  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
57107  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
57108  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
57109  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
57110  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
57111  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
57112  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
57113  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
57114  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
57115  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
57116  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
57117  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
57118  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
57119  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
57120  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
57121  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
57122  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
57123  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
57124  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
57125  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
57126  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
57127  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
57128  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
57129  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
57130  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
57131  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
57132  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
57133  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
57134  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
57135  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
57136  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
57137  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
57138  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
57139  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
57140  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
57141  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
57142  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
57143  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
57144  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
57145  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
57146  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
57147  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
57148  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
57149  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
57150  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
57151  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
57152  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
57153  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
57154  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
57155  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
57156  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
57157  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
57158  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
57159  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
57160  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
57161  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
57162  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
57163  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
57164  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
57165  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
57166  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
57167  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
57168  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
57169  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
57170  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
57171  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
57172  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
57173  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
57174  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
57175  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
57176  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
57177  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
57178  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
57179  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
57180  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
57181  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
57182  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
57183  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
57184  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
57185  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
57186  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
57187  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
57188  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
57189  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
57190  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
57191  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
57192  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
57193 };
57194 
57200 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
57201 {
57202  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
57203  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
57204  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
57205  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
57206  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
57207  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
57208  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
57209  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
57210  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
57211  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
57212  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
57213  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
57214  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
57215  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
57216  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
57217  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
57218  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
57219  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
57220  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
57221  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
57222  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
57223  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
57224  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
57225  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
57226  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
57227  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
57228  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
57229  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
57230  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
57231  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
57232  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
57233  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
57234  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
57235  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
57236  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
57237  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
57238  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
57239  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
57240  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
57241  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
57242  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
57243  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
57244  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
57245  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
57246  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
57247  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
57248  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
57249  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
57250  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
57251  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
57252  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
57253  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
57254  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
57255  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
57256  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
57257  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
57258  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
57259  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
57260  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
57261  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
57262  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
57263  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
57264  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
57265  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
57266  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
57267  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
57268  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
57269  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
57270  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
57271  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
57272  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
57273  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
57274  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
57275  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
57276  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
57277  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
57278  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
57279  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
57280  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
57281  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
57282  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
57283  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
57284  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
57285  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
57286  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
57287  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
57288  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
57289  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
57290  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
57291  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
57292  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
57293  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
57294  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
57295  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
57296  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
57297  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
57298  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
57299  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
57300  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
57301  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
57302  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
57303  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
57304  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
57305  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
57306  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
57307  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
57308  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
57309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
57310  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
57311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
57312  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
57313  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
57314  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
57315  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
57316  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
57317  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
57318  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
57319  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
57320  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
57321  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
57322  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
57323  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
57324  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
57325  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
57326  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
57327  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
57328  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
57329  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
57330  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
57331  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
57332  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
57333  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
57334  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
57335  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
57336  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
57337  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
57338  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
57339  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
57340  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
57341  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
57342  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
57343  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
57344  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
57345  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
57346  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
57347  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
57348  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
57349  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
57350  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
57351  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
57352  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
57353  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
57354  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
57355  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
57356  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
57357  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
57358  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
57359  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
57360  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
57361  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
57362  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
57363  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
57364  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
57365  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
57366  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
57367  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
57368  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
57369  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
57370  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
57371  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
57372  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
57373  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
57374  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
57375  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
57376  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
57377  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
57378  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
57379  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
57380  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
57381  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
57382  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
57383  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
57384  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
57385  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
57386  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
57387  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
57388  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
57389  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
57390  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
57391  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
57392  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
57393  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
57394  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
57395  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
57396  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
57397  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
57398  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
57399  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
57400  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
57401  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
57402  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
57403  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
57404  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
57405  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
57406  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
57407  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
57408  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
57409  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
57410  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
57411  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
57412  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
57413  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
57414  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
57415  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
57416  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
57417  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
57418  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
57419  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
57420  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
57421  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
57422  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
57423  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
57424  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
57425  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
57426  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
57427  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
57428  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
57429  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
57430  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
57431  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
57432  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
57433  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
57434  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
57435  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
57436  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
57437  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
57438  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
57439  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
57440  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
57441  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
57442  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
57443  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
57444  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
57445  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
57446  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
57447  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
57448  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
57449  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
57450  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
57451  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
57452  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
57453  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
57454  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
57455  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
57456  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
57457  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
57458  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
57459  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
57460  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
57461  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
57462  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
57463  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
57464  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
57465  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
57466  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
57467  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
57468  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
57469  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
57470  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
57471  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
57472  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
57473  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
57474  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
57475  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
57476  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
57477  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
57478  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
57479  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
57480  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
57481  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
57482  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
57483  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
57484  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
57485  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
57486  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
57487  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
57488  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
57489  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
57490  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
57491  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
57492  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
57493  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
57494  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
57495  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
57496  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
57497  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
57498  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
57499  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
57500  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
57501  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
57502  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
57503  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
57504  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
57505  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
57506  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
57507  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
57508  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
57509  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
57510  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
57511  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
57512  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
57513  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
57514  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
57515  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
57516  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
57517  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
57518  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
57519  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
57520  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
57521  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
57522  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
57523  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
57524  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
57525  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
57526  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
57527  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
57528  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
57529  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
57530  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
57531  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
57532  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
57533  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
57534  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
57535  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
57536  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
57537  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
57538  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
57539  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
57540  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
57541  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
57542  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
57543  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
57544  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
57545  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
57546  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
57547  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
57548  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
57549  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
57550  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
57551  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
57552  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
57553  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
57554  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
57555  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
57556  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
57557  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
57558  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
57559  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
57560  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
57561  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
57562  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
57563  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
57564  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
57565  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
57566  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
57567  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
57568  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
57569  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
57570  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
57571  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
57572  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
57573  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
57574  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
57575  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
57576  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_187_CHECKER_TYPE,
57577  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_187_WIDTH },
57578  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_188_CHECKER_TYPE,
57579  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_188_WIDTH },
57580  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_189_CHECKER_TYPE,
57581  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_189_WIDTH },
57582  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_190_CHECKER_TYPE,
57583  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_190_WIDTH },
57584  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_191_CHECKER_TYPE,
57585  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_191_WIDTH },
57586  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_192_CHECKER_TYPE,
57587  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_192_WIDTH },
57588  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_193_CHECKER_TYPE,
57589  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_193_WIDTH },
57590  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_194_CHECKER_TYPE,
57591  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_194_WIDTH },
57592  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_195_CHECKER_TYPE,
57593  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_195_WIDTH },
57594  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_196_CHECKER_TYPE,
57595  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_196_WIDTH },
57596  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_197_CHECKER_TYPE,
57597  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_197_WIDTH },
57598  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_198_CHECKER_TYPE,
57599  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_198_WIDTH },
57600  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_199_CHECKER_TYPE,
57601  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_199_WIDTH },
57602  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_200_CHECKER_TYPE,
57603  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_200_WIDTH },
57604  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_201_CHECKER_TYPE,
57605  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_201_WIDTH },
57606  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_202_CHECKER_TYPE,
57607  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_202_WIDTH },
57608  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_203_CHECKER_TYPE,
57609  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_203_WIDTH },
57610  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_204_CHECKER_TYPE,
57611  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_204_WIDTH },
57612  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_205_CHECKER_TYPE,
57613  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_205_WIDTH },
57614  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_206_CHECKER_TYPE,
57615  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_206_WIDTH },
57616  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_207_CHECKER_TYPE,
57617  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_207_WIDTH },
57618  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_208_CHECKER_TYPE,
57619  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_208_WIDTH },
57620  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_209_CHECKER_TYPE,
57621  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_209_WIDTH },
57622  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_210_CHECKER_TYPE,
57623  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_210_WIDTH },
57624  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_211_CHECKER_TYPE,
57625  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_211_WIDTH },
57626  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_212_CHECKER_TYPE,
57627  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_212_WIDTH },
57628  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_213_CHECKER_TYPE,
57629  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_213_WIDTH },
57630  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_214_CHECKER_TYPE,
57631  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_214_WIDTH },
57632  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_215_CHECKER_TYPE,
57633  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_215_WIDTH },
57634  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_216_CHECKER_TYPE,
57635  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_216_WIDTH },
57636  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_217_CHECKER_TYPE,
57637  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_217_WIDTH },
57638  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_218_CHECKER_TYPE,
57639  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_218_WIDTH },
57640  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_219_CHECKER_TYPE,
57641  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_219_WIDTH },
57642  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_220_CHECKER_TYPE,
57643  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_220_WIDTH },
57644  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_221_CHECKER_TYPE,
57645  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_221_WIDTH },
57646  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_222_CHECKER_TYPE,
57647  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_222_WIDTH },
57648  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_223_CHECKER_TYPE,
57649  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_223_WIDTH },
57650  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_224_CHECKER_TYPE,
57651  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_224_WIDTH },
57652  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_225_CHECKER_TYPE,
57653  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_225_WIDTH },
57654  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_226_CHECKER_TYPE,
57655  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_226_WIDTH },
57656  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_227_CHECKER_TYPE,
57657  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_227_WIDTH },
57658  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_228_CHECKER_TYPE,
57659  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_228_WIDTH },
57660  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_229_CHECKER_TYPE,
57661  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_229_WIDTH },
57662  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_230_CHECKER_TYPE,
57663  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_230_WIDTH },
57664  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_231_CHECKER_TYPE,
57665  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_231_WIDTH },
57666  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_232_CHECKER_TYPE,
57667  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_232_WIDTH },
57668  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_233_CHECKER_TYPE,
57669  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_233_WIDTH },
57670  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_234_CHECKER_TYPE,
57671  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_234_WIDTH },
57672  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_235_CHECKER_TYPE,
57673  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_235_WIDTH },
57674  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_236_CHECKER_TYPE,
57675  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_236_WIDTH },
57676  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_237_CHECKER_TYPE,
57677  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_237_WIDTH },
57678  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_238_CHECKER_TYPE,
57679  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_238_WIDTH },
57680  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_239_CHECKER_TYPE,
57681  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_239_WIDTH },
57682  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_240_CHECKER_TYPE,
57683  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_240_WIDTH },
57684  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_241_CHECKER_TYPE,
57685  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_241_WIDTH },
57686  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_242_CHECKER_TYPE,
57687  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_242_WIDTH },
57688  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_243_CHECKER_TYPE,
57689  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_243_WIDTH },
57690  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_244_CHECKER_TYPE,
57691  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_244_WIDTH },
57692  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_245_CHECKER_TYPE,
57693  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_245_WIDTH },
57694  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_246_CHECKER_TYPE,
57695  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_246_WIDTH },
57696  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_247_CHECKER_TYPE,
57697  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_247_WIDTH },
57698  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_248_CHECKER_TYPE,
57699  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_248_WIDTH },
57700  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_249_CHECKER_TYPE,
57701  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_249_WIDTH },
57702  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_250_CHECKER_TYPE,
57703  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_250_WIDTH },
57704  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_251_CHECKER_TYPE,
57705  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_251_WIDTH },
57706  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_252_CHECKER_TYPE,
57707  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_252_WIDTH },
57708  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_253_CHECKER_TYPE,
57709  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_253_WIDTH },
57710  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_254_CHECKER_TYPE,
57711  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_254_WIDTH },
57712  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_255_CHECKER_TYPE,
57713  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_255_WIDTH },
57714 };
57715 
57721 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS] =
57722 {
57723  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_0_CHECKER_TYPE,
57724  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_0_WIDTH },
57725  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_1_CHECKER_TYPE,
57726  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_1_WIDTH },
57727  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_2_CHECKER_TYPE,
57728  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_2_WIDTH },
57729  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_3_CHECKER_TYPE,
57730  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_3_WIDTH },
57731  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_4_CHECKER_TYPE,
57732  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_4_WIDTH },
57733  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_5_CHECKER_TYPE,
57734  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_5_WIDTH },
57735  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_6_CHECKER_TYPE,
57736  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_6_WIDTH },
57737  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_7_CHECKER_TYPE,
57738  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_7_WIDTH },
57739  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_8_CHECKER_TYPE,
57740  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_8_WIDTH },
57741  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_9_CHECKER_TYPE,
57742  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_9_WIDTH },
57743  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_10_CHECKER_TYPE,
57744  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_10_WIDTH },
57745  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_11_CHECKER_TYPE,
57746  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_11_WIDTH },
57747  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_12_CHECKER_TYPE,
57748  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_12_WIDTH },
57749  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_13_CHECKER_TYPE,
57750  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_13_WIDTH },
57751  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_14_CHECKER_TYPE,
57752  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_14_WIDTH },
57753  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_15_CHECKER_TYPE,
57754  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_15_WIDTH },
57755  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_16_CHECKER_TYPE,
57756  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_16_WIDTH },
57757  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_17_CHECKER_TYPE,
57758  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_17_WIDTH },
57759  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_18_CHECKER_TYPE,
57760  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_18_WIDTH },
57761  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_19_CHECKER_TYPE,
57762  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_19_WIDTH },
57763  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_20_CHECKER_TYPE,
57764  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_20_WIDTH },
57765  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_21_CHECKER_TYPE,
57766  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_21_WIDTH },
57767  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_22_CHECKER_TYPE,
57768  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_22_WIDTH },
57769  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_23_CHECKER_TYPE,
57770  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_23_WIDTH },
57771  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_24_CHECKER_TYPE,
57772  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_24_WIDTH },
57773  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_25_CHECKER_TYPE,
57774  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_25_WIDTH },
57775  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_26_CHECKER_TYPE,
57776  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_26_WIDTH },
57777  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_27_CHECKER_TYPE,
57778  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_27_WIDTH },
57779  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_28_CHECKER_TYPE,
57780  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_28_WIDTH },
57781  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_29_CHECKER_TYPE,
57782  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_29_WIDTH },
57783  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_30_CHECKER_TYPE,
57784  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_30_WIDTH },
57785  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_31_CHECKER_TYPE,
57786  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_31_WIDTH },
57787  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_32_CHECKER_TYPE,
57788  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_32_WIDTH },
57789  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_33_CHECKER_TYPE,
57790  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_33_WIDTH },
57791  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_34_CHECKER_TYPE,
57792  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_34_WIDTH },
57793  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_35_CHECKER_TYPE,
57794  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_35_WIDTH },
57795  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_36_CHECKER_TYPE,
57796  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_36_WIDTH },
57797  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_37_CHECKER_TYPE,
57798  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_37_WIDTH },
57799  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_38_CHECKER_TYPE,
57800  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_38_WIDTH },
57801  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_39_CHECKER_TYPE,
57802  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_39_WIDTH },
57803  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_40_CHECKER_TYPE,
57804  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_40_WIDTH },
57805  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_41_CHECKER_TYPE,
57806  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_41_WIDTH },
57807  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_42_CHECKER_TYPE,
57808  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_42_WIDTH },
57809  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_43_CHECKER_TYPE,
57810  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_43_WIDTH },
57811  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_44_CHECKER_TYPE,
57812  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_44_WIDTH },
57813  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_45_CHECKER_TYPE,
57814  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_45_WIDTH },
57815  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_46_CHECKER_TYPE,
57816  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_46_WIDTH },
57817  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_47_CHECKER_TYPE,
57818  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_47_WIDTH },
57819  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_48_CHECKER_TYPE,
57820  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_48_WIDTH },
57821  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_49_CHECKER_TYPE,
57822  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_49_WIDTH },
57823  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_50_CHECKER_TYPE,
57824  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_50_WIDTH },
57825  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_51_CHECKER_TYPE,
57826  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_51_WIDTH },
57827  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_52_CHECKER_TYPE,
57828  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_52_WIDTH },
57829  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_53_CHECKER_TYPE,
57830  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_53_WIDTH },
57831  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_54_CHECKER_TYPE,
57832  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_54_WIDTH },
57833  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_55_CHECKER_TYPE,
57834  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_55_WIDTH },
57835  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_56_CHECKER_TYPE,
57836  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_56_WIDTH },
57837  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_57_CHECKER_TYPE,
57838  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_57_WIDTH },
57839  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_58_CHECKER_TYPE,
57840  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_58_WIDTH },
57841  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_59_CHECKER_TYPE,
57842  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_59_WIDTH },
57843  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_60_CHECKER_TYPE,
57844  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_60_WIDTH },
57845  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_61_CHECKER_TYPE,
57846  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_61_WIDTH },
57847  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_62_CHECKER_TYPE,
57848  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_62_WIDTH },
57849  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_63_CHECKER_TYPE,
57850  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_63_WIDTH },
57851  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_64_CHECKER_TYPE,
57852  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_64_WIDTH },
57853  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_65_CHECKER_TYPE,
57854  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_65_WIDTH },
57855  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_66_CHECKER_TYPE,
57856  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_66_WIDTH },
57857  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_67_CHECKER_TYPE,
57858  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_67_WIDTH },
57859  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_68_CHECKER_TYPE,
57860  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_68_WIDTH },
57861  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_69_CHECKER_TYPE,
57862  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_69_WIDTH },
57863  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_70_CHECKER_TYPE,
57864  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_70_WIDTH },
57865  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_71_CHECKER_TYPE,
57866  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_71_WIDTH },
57867  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_72_CHECKER_TYPE,
57868  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_72_WIDTH },
57869  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_73_CHECKER_TYPE,
57870  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_73_WIDTH },
57871  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_74_CHECKER_TYPE,
57872  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_74_WIDTH },
57873  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_75_CHECKER_TYPE,
57874  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_75_WIDTH },
57875  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_76_CHECKER_TYPE,
57876  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_76_WIDTH },
57877  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_77_CHECKER_TYPE,
57878  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_77_WIDTH },
57879  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_78_CHECKER_TYPE,
57880  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_78_WIDTH },
57881  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_79_CHECKER_TYPE,
57882  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_79_WIDTH },
57883  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_80_CHECKER_TYPE,
57884  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_80_WIDTH },
57885  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_81_CHECKER_TYPE,
57886  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_81_WIDTH },
57887  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_82_CHECKER_TYPE,
57888  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_82_WIDTH },
57889  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_83_CHECKER_TYPE,
57890  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_83_WIDTH },
57891  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_84_CHECKER_TYPE,
57892  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_84_WIDTH },
57893  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_85_CHECKER_TYPE,
57894  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_85_WIDTH },
57895  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_86_CHECKER_TYPE,
57896  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_86_WIDTH },
57897  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_87_CHECKER_TYPE,
57898  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_87_WIDTH },
57899  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_88_CHECKER_TYPE,
57900  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_88_WIDTH },
57901  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_89_CHECKER_TYPE,
57902  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_89_WIDTH },
57903  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_90_CHECKER_TYPE,
57904  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_90_WIDTH },
57905  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_91_CHECKER_TYPE,
57906  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_91_WIDTH },
57907  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_92_CHECKER_TYPE,
57908  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_92_WIDTH },
57909  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_93_CHECKER_TYPE,
57910  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_93_WIDTH },
57911  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_94_CHECKER_TYPE,
57912  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_94_WIDTH },
57913  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_95_CHECKER_TYPE,
57914  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_95_WIDTH },
57915  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_96_CHECKER_TYPE,
57916  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_96_WIDTH },
57917  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_97_CHECKER_TYPE,
57918  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_97_WIDTH },
57919  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_98_CHECKER_TYPE,
57920  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_98_WIDTH },
57921 };
57922 
57928 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
57929 {
57930  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
57931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
57932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
57933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
57934  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
57935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
57936  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
57937  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
57938  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
57939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
57940  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
57941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
57942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
57943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
57944  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
57945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
57946  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
57947  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
57948  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
57949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
57950  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
57951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
57952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
57953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
57954  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
57955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
57956  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
57957  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
57958  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
57959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
57960 };
57961 
57967 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
57968 {
57969  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
57970  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
57971  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
57972  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
57973  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
57974  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
57975  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
57976  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
57977 };
57978 
57984 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
57985 {
57986  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
57987  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
57988  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
57989  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
57990  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
57991  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
57992  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
57993  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
57994  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
57995  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
57996  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
57997  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
57998  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
57999  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
58000  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
58001  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
58002  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
58003  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
58004  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
58005  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
58006  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
58007  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
58008  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
58009  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
58010  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
58011  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
58012  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
58013  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
58014  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
58015  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
58016  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
58017  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
58018  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
58019  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
58020  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
58021  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
58022  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
58023  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
58024  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
58025  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
58026  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
58027  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
58028  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
58029  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
58030  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
58031  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
58032  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
58033  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
58034  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
58035  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
58036  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
58037  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
58038  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
58039  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
58040  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
58041  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
58042  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
58043  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
58044  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
58045  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
58046  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
58047  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
58048  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
58049  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
58050  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
58051  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
58052  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
58053  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
58054  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
58055  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
58056  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
58057  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
58058  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
58059  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
58060  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
58061  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
58062  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
58063  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
58064  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
58065  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
58066  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
58067  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
58068  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
58069  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
58070 };
58071 
58077 static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
58078 {
58079  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
58080  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
58081  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
58082  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
58083  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
58084  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
58085  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
58086  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
58087 };
58088 
58093 static const SDL_MemConfig_t SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries[SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
58094 {
58095  { SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
58096  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
58097  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
58098 };
58099 
58104 static const SDL_MemConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_MemEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
58105 {
58106  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_STRAM_RAM_ID, 0u,
58107  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_STRAM_RAM_SIZE, 4u,
58108  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_STRAM_ROW_WIDTH, ((bool)false) },
58109  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_BUFRAM_ECC_RAM_ID, 0u,
58110  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_BUFRAM_ECC_RAM_SIZE, 4u,
58111  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_BUFRAM_ECC_ROW_WIDTH, ((bool)false) },
58112  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_STRAM_RAM_ID, 0u,
58113  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_STRAM_RAM_SIZE, 4u,
58114  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_STRAM_ROW_WIDTH, ((bool)false) },
58115  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_BUFRAM_RAM_ID, 0u,
58116  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_BUFRAM_RAM_SIZE, 4u,
58117  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_BUFRAM_ROW_WIDTH, ((bool)false) },
58118  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_ECC0_RAM_ID, 0u,
58119  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_ECC0_RAM_SIZE, 4u,
58120  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
58121  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_ECC0_RAM_ID, 0u,
58122  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_ECC0_RAM_SIZE, 4u,
58123  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_ECC0_ROW_WIDTH, ((bool)false) },
58124  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
58125  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
58126  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
58127  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
58128  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
58129  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
58130  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
58131  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
58132  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
58133  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
58134  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
58135  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
58136  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_RAM_ID, 0u,
58137  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_RAM_SIZE, 4u,
58138  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_ROW_WIDTH, ((bool)false) },
58139  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID, 0u,
58140  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_SIZE, 4u,
58141  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_ROW_WIDTH, ((bool)false) },
58142  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID, 0u,
58143  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_SIZE, 4u,
58144  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_ROW_WIDTH, ((bool)false) },
58145  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_RAM_ID, 0u,
58146  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_RAM_SIZE, 4u,
58147  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_ROW_WIDTH, ((bool)false) },
58148 };
58149 
58155 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58156 {
58157  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58158  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
58159  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58160  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
58161  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58162  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
58163  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58164  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
58165  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58166  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
58167  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58168  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
58169 };
58170 
58176 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58177 {
58178  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58179  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
58180  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58181  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
58182  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58183  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
58184  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58185  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
58186  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58187  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
58188  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58189  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
58190  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58191  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
58192  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58193  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
58194  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58195  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
58196  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58197  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
58198  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58199  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
58200  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58201  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
58202  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58203  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
58204  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58205  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
58206  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58207  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
58208  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
58209  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
58210  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
58211  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
58212  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
58213  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
58214  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
58215  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
58216  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
58217  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
58218  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
58219  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
58220  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
58221  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
58222  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
58223  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
58224  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
58225  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
58226  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
58227  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
58228  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
58229  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
58230  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
58231  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
58232  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
58233  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
58234  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
58235  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
58236  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
58237  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
58238  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
58239  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
58240  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
58241  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
58242  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
58243  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
58244  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
58245  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
58246  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
58247  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
58248  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
58249  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
58250  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
58251  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
58252  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
58253  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
58254  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
58255  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
58256  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
58257  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
58258  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
58259  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
58260 };
58261 
58267 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58268 {
58269  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58270  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_0_WIDTH },
58271  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58272  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_1_WIDTH },
58273  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58274  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_2_WIDTH },
58275  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58276  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_3_WIDTH },
58277  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58278  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_4_WIDTH },
58279  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58280  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_5_WIDTH },
58281  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58282  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_6_WIDTH },
58283  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58284  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_7_WIDTH },
58285  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58286  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_8_WIDTH },
58287  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58288  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_9_WIDTH },
58289  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58290  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_10_WIDTH },
58291  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58292  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_11_WIDTH },
58293  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58294  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_12_WIDTH },
58295  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58296  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_13_WIDTH },
58297  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58298  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_14_WIDTH },
58299  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
58300  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_15_WIDTH },
58301  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
58302  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_16_WIDTH },
58303  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
58304  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_17_WIDTH },
58305  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
58306  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_18_WIDTH },
58307  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
58308  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_19_WIDTH },
58309  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
58310  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_20_WIDTH },
58311  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
58312  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_21_WIDTH },
58313  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
58314  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_22_WIDTH },
58315  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
58316  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_23_WIDTH },
58317  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
58318  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_24_WIDTH },
58319  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
58320  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_25_WIDTH },
58321  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
58322  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_26_WIDTH },
58323  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
58324  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_27_WIDTH },
58325  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
58326  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_28_WIDTH },
58327  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
58328  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_29_WIDTH },
58329  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
58330  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_30_WIDTH },
58331  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
58332  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_31_WIDTH },
58333  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
58334  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_32_WIDTH },
58335  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
58336  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_33_WIDTH },
58337  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
58338  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_34_WIDTH },
58339  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
58340  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_35_WIDTH },
58341  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
58342  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_36_WIDTH },
58343  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
58344  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_37_WIDTH },
58345  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
58346  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_38_WIDTH },
58347  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
58348  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_39_WIDTH },
58349  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
58350  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_40_WIDTH },
58351  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
58352  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_41_WIDTH },
58353  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
58354  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_42_WIDTH },
58355  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
58356  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_43_WIDTH },
58357  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
58358  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_44_WIDTH },
58359  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
58360  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_45_WIDTH },
58361  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
58362  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_46_WIDTH },
58363  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
58364  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_47_WIDTH },
58365  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
58366  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_48_WIDTH },
58367  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
58368  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_49_WIDTH },
58369  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
58370  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_50_WIDTH },
58371  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
58372  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_51_WIDTH },
58373  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
58374  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_52_WIDTH },
58375  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
58376  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_53_WIDTH },
58377  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
58378  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_54_WIDTH },
58379  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
58380  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_55_WIDTH },
58381  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
58382  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_56_WIDTH },
58383  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
58384  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_57_WIDTH },
58385  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
58386  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_58_WIDTH },
58387  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
58388  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_59_WIDTH },
58389  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
58390  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_60_WIDTH },
58391  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
58392  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_61_WIDTH },
58393  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
58394  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_62_WIDTH },
58395  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
58396  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_63_WIDTH },
58397  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
58398  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_64_WIDTH },
58399  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
58400  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_65_WIDTH },
58401  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
58402  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_66_WIDTH },
58403  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
58404  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_67_WIDTH },
58405  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
58406  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_68_WIDTH },
58407  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
58408  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_69_WIDTH },
58409  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
58410  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_70_WIDTH },
58411  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
58412  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_71_WIDTH },
58413  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
58414  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_72_WIDTH },
58415  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
58416  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_73_WIDTH },
58417  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
58418  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_74_WIDTH },
58419  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
58420  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_75_WIDTH },
58421  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
58422  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_76_WIDTH },
58423  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
58424  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_77_WIDTH },
58425  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
58426  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_78_WIDTH },
58427  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
58428  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_79_WIDTH },
58429  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
58430  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_80_WIDTH },
58431  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
58432  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_81_WIDTH },
58433  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
58434  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_82_WIDTH },
58435  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
58436  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_83_WIDTH },
58437  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
58438  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_84_WIDTH },
58439  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
58440  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_85_WIDTH },
58441  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
58442  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_86_WIDTH },
58443  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
58444  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_87_WIDTH },
58445  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
58446  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_88_WIDTH },
58447  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
58448  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_89_WIDTH },
58449  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
58450  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_90_WIDTH },
58451  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
58452  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_91_WIDTH },
58453  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
58454  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_92_WIDTH },
58455  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
58456  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_93_WIDTH },
58457  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
58458  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_94_WIDTH },
58459  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
58460  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_95_WIDTH },
58461  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
58462  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_96_WIDTH },
58463  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
58464  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_GROUP_97_WIDTH },
58465 };
58466 
58472 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58473 {
58474  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58475  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_0_WIDTH },
58476  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58477  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_1_WIDTH },
58478  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58479  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_2_WIDTH },
58480  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58481  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_3_WIDTH },
58482  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58483  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_4_WIDTH },
58484  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58485  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_5_WIDTH },
58486  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58487  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_6_WIDTH },
58488  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58489  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_7_WIDTH },
58490  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58491  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_8_WIDTH },
58492  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58493  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_9_WIDTH },
58494  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58495  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_10_WIDTH },
58496  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58497  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_11_WIDTH },
58498  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58499  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_12_WIDTH },
58500  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58501  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_13_WIDTH },
58502  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58503  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_14_WIDTH },
58504  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
58505  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_15_WIDTH },
58506  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
58507  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_16_WIDTH },
58508  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
58509  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_17_WIDTH },
58510  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
58511  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_18_WIDTH },
58512  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
58513  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_19_WIDTH },
58514  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
58515  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_20_WIDTH },
58516  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
58517  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_21_WIDTH },
58518  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
58519  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_22_WIDTH },
58520  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
58521  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_23_WIDTH },
58522  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
58523  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_24_WIDTH },
58524  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
58525  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_25_WIDTH },
58526  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
58527  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_26_WIDTH },
58528  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
58529  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_27_WIDTH },
58530  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
58531  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_28_WIDTH },
58532  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
58533  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_29_WIDTH },
58534  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
58535  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_30_WIDTH },
58536  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
58537  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_31_WIDTH },
58538  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
58539  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_32_WIDTH },
58540  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
58541  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_33_WIDTH },
58542  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
58543  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_34_WIDTH },
58544  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
58545  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_35_WIDTH },
58546  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
58547  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_36_WIDTH },
58548  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
58549  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_37_WIDTH },
58550  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
58551  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_38_WIDTH },
58552  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
58553  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_39_WIDTH },
58554  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
58555  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_40_WIDTH },
58556  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
58557  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_41_WIDTH },
58558  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
58559  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_42_WIDTH },
58560  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
58561  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_43_WIDTH },
58562  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
58563  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_44_WIDTH },
58564  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
58565  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_45_WIDTH },
58566  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
58567  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_46_WIDTH },
58568  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
58569  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_47_WIDTH },
58570  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
58571  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_48_WIDTH },
58572  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
58573  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_49_WIDTH },
58574  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
58575  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_50_WIDTH },
58576  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
58577  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_51_WIDTH },
58578  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
58579  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_52_WIDTH },
58580  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
58581  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_53_WIDTH },
58582  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
58583  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_54_WIDTH },
58584  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
58585  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_55_WIDTH },
58586  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
58587  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_56_WIDTH },
58588  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
58589  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_57_WIDTH },
58590  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
58591  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_58_WIDTH },
58592  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
58593  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_59_WIDTH },
58594  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
58595  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_60_WIDTH },
58596  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
58597  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_61_WIDTH },
58598  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
58599  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_62_WIDTH },
58600  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
58601  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_63_WIDTH },
58602  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
58603  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_64_WIDTH },
58604  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
58605  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_65_WIDTH },
58606  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
58607  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_66_WIDTH },
58608  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
58609  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_67_WIDTH },
58610  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
58611  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_68_WIDTH },
58612  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
58613  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_69_WIDTH },
58614  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
58615  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_70_WIDTH },
58616  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
58617  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_71_WIDTH },
58618  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
58619  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_72_WIDTH },
58620  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
58621  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_73_WIDTH },
58622  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
58623  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_74_WIDTH },
58624  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
58625  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_75_WIDTH },
58626  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
58627  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_76_WIDTH },
58628  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
58629  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_77_WIDTH },
58630  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
58631  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_78_WIDTH },
58632  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
58633  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_79_WIDTH },
58634  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
58635  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_GROUP_80_WIDTH },
58636 };
58637 
58643 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58644 {
58645  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58646  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
58647  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58648  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
58649  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58650  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
58651  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58652  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
58653  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58654  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
58655  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58656  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
58657  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58658  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
58659  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58660  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
58661  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58662  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
58663  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58664  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
58665  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58666  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
58667  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58668  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
58669  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58670  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
58671  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58672  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
58673  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58674  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
58675  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
58676  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
58677  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
58678  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
58679  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
58680  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
58681  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
58682  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
58683  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
58684  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
58685  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
58686  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
58687  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
58688  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
58689  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
58690  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
58691  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
58692  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
58693 };
58694 
58700 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58701 {
58702  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58703  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_0_WIDTH },
58704  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58705  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_1_WIDTH },
58706  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58707  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_2_WIDTH },
58708  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58709  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_3_WIDTH },
58710  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58711  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_4_WIDTH },
58712  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58713  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_5_WIDTH },
58714  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58715  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_6_WIDTH },
58716  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58717  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_7_WIDTH },
58718  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58719  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_8_WIDTH },
58720  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58721  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_9_WIDTH },
58722  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58723  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_10_WIDTH },
58724  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58725  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_11_WIDTH },
58726  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58727  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_12_WIDTH },
58728  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58729  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_13_WIDTH },
58730  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58731  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_14_WIDTH },
58732  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
58733  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_15_WIDTH },
58734  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
58735  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_16_WIDTH },
58736  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
58737  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_17_WIDTH },
58738  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
58739  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_18_WIDTH },
58740  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
58741  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_19_WIDTH },
58742  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
58743  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_20_WIDTH },
58744  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
58745  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_21_WIDTH },
58746  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
58747  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_22_WIDTH },
58748  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
58749  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_GROUP_23_WIDTH },
58750 };
58751 
58757 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58758 {
58759  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58760  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
58761  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58762  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
58763  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58764  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
58765  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58766  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
58767  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58768  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
58769  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58770  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
58771  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58772  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
58773  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58774  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
58775  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58776  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
58777  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58778  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
58779  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58780  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
58781  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58782  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
58783  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58784  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
58785  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58786  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
58787  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58788  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
58789 };
58790 
58796 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58797 {
58798  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58799  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
58800  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58801  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
58802  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58803  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
58804  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58805  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
58806  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58807  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_4_WIDTH },
58808  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58809  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_5_WIDTH },
58810  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58811  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_6_WIDTH },
58812  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58813  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_7_WIDTH },
58814  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58815  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_8_WIDTH },
58816  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58817  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_9_WIDTH },
58818  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58819  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_10_WIDTH },
58820  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58821  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_11_WIDTH },
58822  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58823  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_12_WIDTH },
58824  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58825  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_13_WIDTH },
58826 };
58827 
58833 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58834 {
58835  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58836  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
58837  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58838  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
58839  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58840  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
58841  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58842  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
58843  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58844  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
58845  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58846  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
58847  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58848  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
58849  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58850  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
58851  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58852  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
58853  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58854  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
58855  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58856  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
58857  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58858  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
58859  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58860  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
58861  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58862  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
58863  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58864  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
58865  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
58866  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
58867  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
58868  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
58869  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
58870  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
58871  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
58872  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
58873  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
58874  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
58875  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
58876  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
58877  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
58878  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
58879  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
58880  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
58881  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
58882  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
58883  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
58884  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
58885  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
58886  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
58887  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
58888  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
58889  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
58890  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
58891  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
58892  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
58893  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
58894  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
58895  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
58896  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
58897  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
58898  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
58899  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
58900  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
58901  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
58902  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
58903  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
58904  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
58905  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
58906  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
58907  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
58908  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
58909  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
58910  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
58911  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
58912  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
58913  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
58914  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
58915  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
58916  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
58917 };
58918 
58924 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
58925 {
58926  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
58927  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
58928  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
58929  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
58930  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
58931  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
58932  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
58933  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
58934  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
58935  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
58936  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
58937  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
58938  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
58939  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
58940  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
58941  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
58942  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
58943  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
58944  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
58945  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
58946  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
58947  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
58948  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
58949  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
58950  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
58951  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
58952  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
58953  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
58954  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
58955  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
58956  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
58957  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
58958  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
58959  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
58960  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
58961  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
58962  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
58963  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
58964  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
58965  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
58966  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
58967  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
58968  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
58969  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
58970  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
58971  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
58972  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
58973  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
58974  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
58975  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
58976  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
58977  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
58978  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
58979  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
58980  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
58981  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
58982  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
58983  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
58984  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
58985  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
58986  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
58987  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
58988  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
58989  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
58990  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
58991  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
58992  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
58993  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
58994  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
58995  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
58996  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
58997  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
58998  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
58999  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
59000  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
59001  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
59002  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
59003  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
59004  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
59005  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
59006  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
59007  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
59008  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
59009  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
59010  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
59011  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
59012 };
59013 
59019 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59020 {
59021  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59022  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
59023  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59024  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
59025  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59026  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
59027  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59028  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
59029  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59030  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
59031  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59032  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
59033  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59034  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
59035  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59036  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
59037  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59038  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
59039  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59040  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
59041  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59042  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
59043  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59044  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
59045  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
59046  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
59047  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
59048  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
59049  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
59050  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
59051  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
59052  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
59053  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
59054  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
59055  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
59056  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
59057  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
59058  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
59059  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
59060  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
59061  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
59062  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
59063  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
59064  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
59065  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
59066  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
59067  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
59068  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
59069  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
59070  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
59071  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
59072  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
59073  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
59074  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
59075  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
59076  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
59077  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
59078  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
59079  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
59080  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
59081  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
59082  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
59083  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
59084  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
59085  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
59086  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
59087  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
59088  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
59089  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
59090  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
59091  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
59092  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
59093  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
59094  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
59095  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
59096  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
59097  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
59098  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
59099  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
59100  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
59101  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
59102  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
59103  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
59104  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
59105  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
59106  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
59107 };
59108 
59114 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59115 {
59116  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59117  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
59118  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59119  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
59120  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59121  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
59122  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59123  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
59124  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59125  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
59126  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59127  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
59128  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59129  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
59130  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59131  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
59132  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59133  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
59134  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59135  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
59136  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59137  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
59138  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59139  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
59140  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
59141  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
59142  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
59143  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
59144  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
59145  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
59146  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
59147  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
59148  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
59149  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
59150  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
59151  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
59152  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
59153  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
59154  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
59155  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
59156  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
59157  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
59158  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
59159  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
59160  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
59161  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
59162  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
59163  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
59164  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
59165  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
59166  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
59167  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
59168  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
59169  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
59170  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
59171  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
59172  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
59173  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
59174  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
59175  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
59176  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
59177  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
59178  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
59179  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
59180  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
59181  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
59182  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
59183  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
59184  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
59185  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
59186  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
59187  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
59188  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
59189  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
59190  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
59191  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
59192  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
59193  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
59194  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
59195  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
59196  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
59197  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
59198  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
59199  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
59200  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
59201  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
59202 };
59203 
59209 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59210 {
59211  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59212  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
59213  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59214  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
59215  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59216  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
59217  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59218  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
59219  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59220  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
59221  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59222  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
59223  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59224  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
59225  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59226  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
59227  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59228  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
59229  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59230  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
59231  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59232  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
59233  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59234  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
59235  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
59236  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
59237  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
59238  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
59239  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
59240  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
59241  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
59242  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
59243  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
59244  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
59245  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
59246  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
59247  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
59248  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
59249  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
59250  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
59251  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
59252  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
59253  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
59254  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
59255  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
59256  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
59257  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
59258  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
59259  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
59260  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
59261  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
59262  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
59263  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
59264  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
59265  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
59266  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
59267  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
59268  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
59269  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
59270  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
59271  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
59272  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
59273  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
59274  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
59275  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
59276  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
59277  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
59278  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
59279  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
59280  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
59281  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
59282  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
59283  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
59284  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
59285  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
59286  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
59287  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
59288  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
59289  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
59290  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
59291  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
59292  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
59293  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
59294  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
59295  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
59296  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
59297 };
59298 
59304 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59305 {
59306  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59307  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
59308  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59309  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
59310  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59311  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
59312  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59313  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
59314  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59315  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
59316  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59317  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
59318  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59319  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
59320  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59321  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
59322  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59323  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
59324  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59325  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
59326  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59327  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
59328  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59329  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
59330  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
59331  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
59332  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
59333  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
59334  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
59335  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
59336  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
59337  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
59338  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
59339  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
59340  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
59341  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
59342  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
59343  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
59344  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
59345  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
59346  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
59347  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
59348  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
59349  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
59350  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
59351  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
59352  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
59353  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
59354  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
59355  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
59356  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
59357  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
59358  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
59359  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
59360  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
59361  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
59362  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
59363  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
59364  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
59365  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
59366  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
59367  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
59368  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
59369  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
59370  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
59371  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
59372  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
59373  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
59374  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
59375  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
59376  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
59377  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
59378  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
59379  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
59380  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
59381  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
59382  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
59383  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
59384  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
59385  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
59386  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
59387  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
59388 };
59389 
59395 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59396 {
59397  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59398  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59399  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59400  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59401  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59402  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59403 };
59404 
59410 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59411 {
59412  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59413  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
59414  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59415  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
59416  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59417  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
59418  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59419  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
59420  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59421  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
59422  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59423  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
59424  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59425  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
59426 };
59427 
59433 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59434 {
59435  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59436  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59437  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59438  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59439  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59440  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59441 };
59442 
59448 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59449 {
59450  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59451  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
59452  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59453  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
59454  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59455  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
59456  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59457  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
59458  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59459  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
59460  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59461  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
59462  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59463  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
59464 };
59465 
59471 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59472 {
59473  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59474  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59475  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59476  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59477  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59478  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59479 };
59480 
59486 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59487 {
59488  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59489  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
59490  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59491  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
59492  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59493  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
59494  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59495  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
59496  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59497  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
59498  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59499  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
59500  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59501  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
59502 };
59503 
59509 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59510 {
59511  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59512  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59513  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59514  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59515  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59516  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59517 };
59518 
59524 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59525 {
59526  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59527  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
59528  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59529  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
59530  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59531  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
59532  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59533  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
59534  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59535  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
59536  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59537  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
59538  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59539  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
59540 };
59541 
59547 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59548 {
59549  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59550  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59551  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59552  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59553  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59554  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59555 };
59556 
59562 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59563 {
59564  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59565  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59566  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59567  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59568  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59569  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59570 };
59571 
59577 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59578 {
59579  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59580  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_0_WIDTH },
59581  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59582  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_1_WIDTH },
59583  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59584  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_2_WIDTH },
59585  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59586  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_3_WIDTH },
59587  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59588  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_4_WIDTH },
59589  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59590  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_5_WIDTH },
59591  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59592  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_GROUP_6_WIDTH },
59593 };
59594 
59600 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59601 {
59602  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59603  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59604  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59605  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59606  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59607  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59608 };
59609 
59615 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59616 {
59617  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59618  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
59619  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59620  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
59621  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59622  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
59623 };
59624 
59630 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59631 {
59632  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59633  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
59634  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59635  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
59636  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59637  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
59638  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59639  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
59640  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59641  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
59642  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59643  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
59644  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59645  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
59646  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59647  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
59648  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59649  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
59650  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59651  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
59652  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59653  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
59654  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59655  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
59656 };
59657 
59663 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59664 {
59665  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59666  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
59667  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59668  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
59669  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59670  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
59671  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59672  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
59673  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59674  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
59675  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59676  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
59677  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59678  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
59679  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59680  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
59681  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59682  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
59683  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59684  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
59685  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59686  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
59687  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59688  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
59689 };
59690 
59696 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59697 {
59698  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59699  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
59700  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59701  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
59702  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59703  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
59704  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59705  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
59706  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59707  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
59708  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59709  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
59710  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59711  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
59712  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59713  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
59714  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59715  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
59716  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59717  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
59718  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59719  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
59720  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59721  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
59722 };
59723 
59729 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59730 {
59731  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59732  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
59733  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59734  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
59735  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59736  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
59737  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59738  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
59739  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59740  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
59741  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59742  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
59743  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59744  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
59745  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59746  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
59747  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59748  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
59749  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59750  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
59751  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59752  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
59753  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59754  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
59755  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
59756  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
59757  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
59758  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
59759  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
59760  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
59761  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
59762  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
59763  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
59764  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
59765  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
59766  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
59767  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
59768  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
59769  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
59770  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
59771  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
59772  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
59773  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
59774  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
59775  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
59776  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
59777  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
59778  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
59779  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
59780  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
59781  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
59782  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
59783  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
59784  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
59785  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
59786  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
59787  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
59788  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
59789  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
59790  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
59791  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
59792  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
59793  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
59794  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
59795  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
59796  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
59797  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
59798  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
59799  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
59800  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
59801  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
59802  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
59803  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
59804  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
59805  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
59806  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
59807  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
59808  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
59809  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
59810  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
59811  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
59812  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
59813 };
59814 
59820 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
59821 {
59822  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
59823  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
59824  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
59825  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
59826  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
59827  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
59828  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
59829  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
59830  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
59831  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
59832  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
59833  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
59834  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
59835  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
59836  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
59837  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
59838  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
59839  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
59840  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
59841  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
59842  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
59843  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
59844  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
59845  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
59846  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
59847  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
59848  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
59849  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
59850  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
59851  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
59852  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
59853  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
59854  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
59855  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
59856  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
59857  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
59858  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
59859  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
59860  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
59861  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
59862  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
59863  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
59864  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
59865  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
59866  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
59867  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
59868  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
59869  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
59870  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
59871  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
59872  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
59873  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
59874  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
59875  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
59876  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
59877  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
59878  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
59879  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
59880  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
59881  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
59882  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
59883  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
59884  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
59885  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
59886  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
59887  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
59888  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
59889  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
59890  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
59891  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
59892  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
59893  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
59894  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
59895  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
59896  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
59897  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
59898  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
59899  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
59900  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
59901  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
59902  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
59903  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
59904  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
59905  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
59906  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
59907  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
59908  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
59909  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
59910  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
59911  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
59912  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
59913  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
59914  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
59915  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
59916  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
59917  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
59918  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
59919  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
59920  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
59921  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
59922  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
59923  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
59924  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
59925  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
59926  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
59927  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
59928  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
59929  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
59930  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
59931  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
59932  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
59933  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
59934  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
59935  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
59936  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
59937  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
59938  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
59939  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
59940  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
59941  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
59942  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
59943  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
59944  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
59945  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
59946  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
59947  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
59948  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
59949  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
59950  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
59951  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
59952  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
59953  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
59954  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
59955  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
59956  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
59957  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
59958  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
59959  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
59960  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
59961  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
59962  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
59963  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
59964  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
59965  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
59966  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
59967  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
59968  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
59969  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
59970  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
59971  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
59972  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
59973  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
59974  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
59975  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
59976  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
59977  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
59978  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
59979  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
59980  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
59981  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
59982  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
59983  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
59984  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
59985  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
59986  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
59987  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
59988  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
59989  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
59990  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
59991  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
59992  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
59993  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
59994  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
59995  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
59996  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
59997  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
59998  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
59999  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
60000  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
60001  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
60002  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
60003  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
60004  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
60005  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
60006  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
60007  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
60008  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
60009  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
60010  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
60011  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
60012  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
60013  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
60014  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
60015  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
60016  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
60017  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
60018  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
60019  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
60020  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
60021  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
60022  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
60023  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
60024  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
60025  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
60026  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
60027  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
60028  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
60029  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
60030  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
60031  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
60032  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
60033  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
60034  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
60035  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
60036  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
60037  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
60038  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
60039  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
60040  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
60041  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
60042  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
60043  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
60044  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
60045  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
60046  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
60047  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
60048  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
60049  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
60050  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
60051  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
60052  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
60053  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
60054  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
60055  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
60056  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
60057  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
60058  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
60059  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
60060  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
60061  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
60062  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
60063  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
60064  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
60065  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
60066  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
60067  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
60068  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
60069  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
60070  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
60071  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
60072  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
60073  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
60074  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
60075  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
60076  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
60077  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
60078  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
60079  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
60080  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
60081  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
60082  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
60083  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
60084  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
60085  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
60086  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
60087  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
60088 };
60089 
60095 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
60096 {
60097  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
60098  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
60099  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
60100  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
60101  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
60102  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
60103  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
60104  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
60105  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
60106  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
60107  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
60108  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
60109  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
60110  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
60111  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
60112  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
60113  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
60114  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
60115  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
60116  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
60117  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
60118  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
60119  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
60120  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
60121  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
60122  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
60123  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
60124  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
60125  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
60126  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
60127  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
60128  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
60129  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
60130  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
60131  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
60132  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
60133  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
60134  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
60135  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
60136  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
60137  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
60138  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
60139  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
60140  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
60141  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
60142  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
60143  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
60144  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
60145  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
60146  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
60147  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
60148  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
60149  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
60150  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
60151  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
60152  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
60153  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
60154  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
60155  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
60156  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
60157  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
60158  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
60159  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
60160  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
60161  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
60162  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
60163  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
60164  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
60165  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
60166  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
60167  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
60168  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
60169  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
60170  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
60171  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
60172  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
60173  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
60174  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
60175  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
60176  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
60177  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
60178  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
60179  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
60180  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
60181  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
60182  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
60183  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
60184  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
60185  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
60186  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
60187  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
60188  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
60189  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
60190  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
60191  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
60192  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
60193  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
60194  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
60195  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
60196  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
60197  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
60198  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
60199  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
60200  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
60201  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
60202  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
60203  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
60204  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
60205  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
60206  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
60207  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
60208  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
60209  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
60210  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
60211  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
60212  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
60213  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
60214  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
60215  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
60216  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
60217  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
60218  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
60219  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
60220  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
60221  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
60222  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
60223  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
60224  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
60225  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
60226  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
60227  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
60228  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
60229  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
60230  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
60231  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
60232  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
60233  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
60234  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
60235  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
60236  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
60237  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
60238  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
60239  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
60240  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
60241  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
60242  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
60243  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
60244  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
60245  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
60246  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
60247  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
60248  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
60249  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
60250  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
60251  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
60252  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
60253  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
60254  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
60255  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
60256  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
60257  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
60258  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
60259  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
60260  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
60261  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
60262  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
60263  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
60264  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
60265  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
60266  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
60267  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
60268  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
60269  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
60270  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
60271  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
60272  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
60273  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
60274  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
60275  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
60276  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
60277  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
60278  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
60279  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
60280  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
60281  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
60282  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
60283  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
60284  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
60285  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
60286  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
60287  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
60288  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
60289  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
60290  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
60291  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
60292  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
60293  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
60294  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
60295  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
60296  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
60297  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
60298  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
60299  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
60300  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
60301  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
60302  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
60303  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
60304  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
60305  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
60306  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
60307  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
60308  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
60309  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
60310  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
60311  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
60312  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
60313  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
60314  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
60315  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
60316  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
60317  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
60318  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
60319  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
60320  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
60321  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
60322  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
60323  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
60324  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
60325  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
60326  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
60327  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
60328  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
60329  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
60330  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
60331  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
60332  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
60333  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
60334  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
60335  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
60336  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
60337  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
60338  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
60339  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
60340  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
60341  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
60342  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
60343  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
60344  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
60345  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
60346  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
60347  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
60348  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
60349  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
60350  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
60351  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
60352  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
60353  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
60354  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
60355  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
60356  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
60357  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
60358  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
60359  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
60360  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
60361  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
60362  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
60363  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
60364  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
60365  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
60366  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
60367  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
60368  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
60369  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
60370  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
60371  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
60372  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
60373  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
60374  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
60375  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
60376  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
60377  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
60378  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
60379  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
60380  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
60381  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
60382  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
60383  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
60384  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
60385  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
60386  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
60387  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
60388  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
60389  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
60390  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
60391  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
60392  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
60393  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
60394  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
60395  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
60396  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
60397  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
60398  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
60399  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
60400  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
60401  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
60402  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
60403  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
60404  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
60405  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
60406  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
60407  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
60408  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
60409  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
60410  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
60411  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
60412  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
60413  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
60414  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
60415  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
60416  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
60417  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
60418  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
60419  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
60420  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
60421  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
60422  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
60423  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
60424  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
60425  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
60426  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
60427  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
60428  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
60429  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
60430  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
60431  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
60432  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
60433  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
60434  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
60435  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
60436  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
60437  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
60438  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
60439  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
60440  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
60441  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
60442  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
60443  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
60444  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
60445  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
60446  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
60447  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
60448  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
60449  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
60450  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
60451  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
60452  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
60453  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
60454  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
60455  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
60456  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
60457  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
60458  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
60459  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
60460  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
60461  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
60462  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
60463  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
60464  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
60465  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
60466  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
60467  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
60468  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
60469  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
60470  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
60471  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
60472  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
60473  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
60474  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
60475  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
60476  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
60477  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
60478  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
60479  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
60480  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
60481  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
60482  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
60483  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
60484  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
60485  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
60486  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
60487  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
60488  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
60489  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
60490  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
60491  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
60492  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
60493  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
60494  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
60495  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
60496  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
60497  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
60498  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
60499  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
60500  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
60501  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
60502  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
60503  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
60504  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
60505  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
60506  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
60507  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
60508  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
60509  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
60510  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
60511  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
60512  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
60513  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
60514  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
60515  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
60516  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
60517  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
60518  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
60519  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
60520  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
60521  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
60522  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
60523  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
60524  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
60525  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
60526  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
60527  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
60528  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
60529  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
60530  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
60531  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
60532  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
60533  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
60534  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
60535  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
60536  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
60537  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
60538  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
60539  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
60540  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
60541  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
60542  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
60543  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
60544  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
60545  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
60546  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
60547  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
60548  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
60549  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
60550  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
60551  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
60552  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
60553  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
60554  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
60555  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
60556  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_229_WIDTH },
60557  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
60558  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_230_WIDTH },
60559  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
60560  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_231_WIDTH },
60561  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
60562  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_232_WIDTH },
60563  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
60564  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_233_WIDTH },
60565  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
60566  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_234_WIDTH },
60567  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
60568  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_235_WIDTH },
60569  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
60570  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_236_WIDTH },
60571  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
60572  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_237_WIDTH },
60573  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
60574  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_238_WIDTH },
60575  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
60576  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_239_WIDTH },
60577  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
60578  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_240_WIDTH },
60579  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
60580  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_241_WIDTH },
60581  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
60582  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_242_WIDTH },
60583  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
60584  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_243_WIDTH },
60585  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
60586  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_244_WIDTH },
60587  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
60588  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_245_WIDTH },
60589  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
60590  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_246_WIDTH },
60591  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
60592  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_247_WIDTH },
60593  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
60594  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_248_WIDTH },
60595  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
60596  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_249_WIDTH },
60597  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
60598  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_250_WIDTH },
60599  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
60600  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_251_WIDTH },
60601  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
60602  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_252_WIDTH },
60603  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
60604  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_253_WIDTH },
60605  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
60606  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_254_WIDTH },
60607  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
60608  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_GROUP_255_WIDTH },
60609 };
60610 
60616 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS] =
60617 {
60618  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
60619  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_0_WIDTH },
60620  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
60621  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_1_WIDTH },
60622  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
60623  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_2_WIDTH },
60624  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
60625  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_3_WIDTH },
60626  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
60627  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_4_WIDTH },
60628  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
60629  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_5_WIDTH },
60630  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
60631  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_6_WIDTH },
60632  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
60633  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_7_WIDTH },
60634  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
60635  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_8_WIDTH },
60636  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
60637  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_9_WIDTH },
60638  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
60639  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_10_WIDTH },
60640  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
60641  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_11_WIDTH },
60642  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
60643  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_12_WIDTH },
60644  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
60645  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_13_WIDTH },
60646  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
60647  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_14_WIDTH },
60648  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
60649  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_15_WIDTH },
60650  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
60651  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_16_WIDTH },
60652  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
60653  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_17_WIDTH },
60654  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
60655  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_18_WIDTH },
60656  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
60657  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_19_WIDTH },
60658  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
60659  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_20_WIDTH },
60660  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
60661  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_21_WIDTH },
60662  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
60663  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_22_WIDTH },
60664  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
60665  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_23_WIDTH },
60666  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
60667  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_24_WIDTH },
60668  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
60669  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_25_WIDTH },
60670  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
60671  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_26_WIDTH },
60672  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
60673  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_27_WIDTH },
60674  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
60675  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_28_WIDTH },
60676  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
60677  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_29_WIDTH },
60678  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
60679  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_30_WIDTH },
60680  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
60681  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_31_WIDTH },
60682  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
60683  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_32_WIDTH },
60684  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
60685  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_33_WIDTH },
60686  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
60687  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_34_WIDTH },
60688  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
60689  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_35_WIDTH },
60690  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
60691  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_36_WIDTH },
60692  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
60693  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_37_WIDTH },
60694  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
60695  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_38_WIDTH },
60696  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
60697  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_39_WIDTH },
60698  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
60699  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_40_WIDTH },
60700  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
60701  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_41_WIDTH },
60702  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
60703  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_42_WIDTH },
60704  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
60705  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_43_WIDTH },
60706  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
60707  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_44_WIDTH },
60708  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
60709  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_45_WIDTH },
60710  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
60711  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_46_WIDTH },
60712  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
60713  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_47_WIDTH },
60714  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
60715  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_48_WIDTH },
60716  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
60717  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_49_WIDTH },
60718  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
60719  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_50_WIDTH },
60720  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
60721  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_51_WIDTH },
60722  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
60723  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_52_WIDTH },
60724  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
60725  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_53_WIDTH },
60726  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
60727  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_54_WIDTH },
60728  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
60729  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_55_WIDTH },
60730  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
60731  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_56_WIDTH },
60732  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
60733  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_57_WIDTH },
60734  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
60735  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_58_WIDTH },
60736  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
60737  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_59_WIDTH },
60738  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
60739  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_60_WIDTH },
60740  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
60741  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_61_WIDTH },
60742  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
60743  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_62_WIDTH },
60744  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
60745  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_63_WIDTH },
60746  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
60747  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_64_WIDTH },
60748  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
60749  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_65_WIDTH },
60750  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
60751  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_66_WIDTH },
60752  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
60753  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_67_WIDTH },
60754  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
60755  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_68_WIDTH },
60756  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
60757  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_69_WIDTH },
60758  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
60759  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_70_WIDTH },
60760  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
60761  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_71_WIDTH },
60762  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
60763  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_72_WIDTH },
60764  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
60765  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_73_WIDTH },
60766  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
60767  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_74_WIDTH },
60768  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
60769  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_75_WIDTH },
60770  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
60771  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_76_WIDTH },
60772  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
60773  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_77_WIDTH },
60774  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
60775  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_78_WIDTH },
60776  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
60777  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_79_WIDTH },
60778  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
60779  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_80_WIDTH },
60780  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
60781  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_81_WIDTH },
60782  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
60783  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_82_WIDTH },
60784  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
60785  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_83_WIDTH },
60786  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
60787  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_84_WIDTH },
60788  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
60789  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_85_WIDTH },
60790  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
60791  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_86_WIDTH },
60792  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
60793  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_87_WIDTH },
60794  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
60795  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_88_WIDTH },
60796  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
60797  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_89_WIDTH },
60798  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
60799  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_90_WIDTH },
60800  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
60801  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_91_WIDTH },
60802  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
60803  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_92_WIDTH },
60804  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
60805  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_93_WIDTH },
60806  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
60807  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_94_WIDTH },
60808  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
60809  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_95_WIDTH },
60810  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
60811  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_96_WIDTH },
60812  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
60813  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_97_WIDTH },
60814  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
60815  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_98_WIDTH },
60816  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
60817  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_99_WIDTH },
60818  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
60819  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_100_WIDTH },
60820  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
60821  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_101_WIDTH },
60822  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
60823  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_102_WIDTH },
60824  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
60825  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_103_WIDTH },
60826  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
60827  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_104_WIDTH },
60828  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
60829  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_105_WIDTH },
60830  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
60831  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_106_WIDTH },
60832  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
60833  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_107_WIDTH },
60834  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
60835  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_108_WIDTH },
60836  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
60837  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_109_WIDTH },
60838  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
60839  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_110_WIDTH },
60840  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
60841  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_111_WIDTH },
60842  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
60843  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_112_WIDTH },
60844  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
60845  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_113_WIDTH },
60846  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
60847  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_114_WIDTH },
60848  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
60849  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_115_WIDTH },
60850  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
60851  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_116_WIDTH },
60852  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
60853  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_117_WIDTH },
60854  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
60855  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_118_WIDTH },
60856  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
60857  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_119_WIDTH },
60858  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
60859  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_120_WIDTH },
60860  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
60861  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_121_WIDTH },
60862  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
60863  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_122_WIDTH },
60864  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
60865  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_123_WIDTH },
60866  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
60867  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_124_WIDTH },
60868  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
60869  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_125_WIDTH },
60870  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
60871  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_126_WIDTH },
60872  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
60873  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_127_WIDTH },
60874  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
60875  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_128_WIDTH },
60876  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
60877  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_129_WIDTH },
60878  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
60879  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_130_WIDTH },
60880  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
60881  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_131_WIDTH },
60882  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
60883  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_132_WIDTH },
60884  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
60885  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_133_WIDTH },
60886  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
60887  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_134_WIDTH },
60888  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
60889  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_135_WIDTH },
60890  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
60891  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_136_WIDTH },
60892  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
60893  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_137_WIDTH },
60894  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
60895  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_138_WIDTH },
60896  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
60897  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_139_WIDTH },
60898  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
60899  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_140_WIDTH },
60900  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
60901  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_141_WIDTH },
60902  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
60903  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_142_WIDTH },
60904  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
60905  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_143_WIDTH },
60906  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
60907  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_144_WIDTH },
60908  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
60909  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_145_WIDTH },
60910  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
60911  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_146_WIDTH },
60912  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
60913  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_147_WIDTH },
60914  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
60915  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_148_WIDTH },
60916  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
60917  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_149_WIDTH },
60918  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
60919  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_150_WIDTH },
60920  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
60921  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_151_WIDTH },
60922  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
60923  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_152_WIDTH },
60924  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
60925  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_153_WIDTH },
60926  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
60927  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_154_WIDTH },
60928  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
60929  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_155_WIDTH },
60930  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
60931  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_156_WIDTH },
60932  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
60933  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_157_WIDTH },
60934  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
60935  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_158_WIDTH },
60936  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
60937  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_159_WIDTH },
60938  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
60939  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_160_WIDTH },
60940  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
60941  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_161_WIDTH },
60942  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
60943  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_162_WIDTH },
60944  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
60945  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_163_WIDTH },
60946  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_164_CHECKER_TYPE,
60947  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_164_WIDTH },
60948  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_165_CHECKER_TYPE,
60949  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_165_WIDTH },
60950  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_166_CHECKER_TYPE,
60951  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_166_WIDTH },
60952  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_167_CHECKER_TYPE,
60953  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_167_WIDTH },
60954  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_168_CHECKER_TYPE,
60955  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_168_WIDTH },
60956  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_169_CHECKER_TYPE,
60957  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_169_WIDTH },
60958  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_170_CHECKER_TYPE,
60959  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_170_WIDTH },
60960  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_171_CHECKER_TYPE,
60961  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_171_WIDTH },
60962  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_172_CHECKER_TYPE,
60963  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_172_WIDTH },
60964  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_173_CHECKER_TYPE,
60965  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_173_WIDTH },
60966  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_174_CHECKER_TYPE,
60967  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_174_WIDTH },
60968  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_175_CHECKER_TYPE,
60969  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_175_WIDTH },
60970  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_176_CHECKER_TYPE,
60971  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_176_WIDTH },
60972  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_177_CHECKER_TYPE,
60973  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_177_WIDTH },
60974  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_178_CHECKER_TYPE,
60975  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_178_WIDTH },
60976  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_179_CHECKER_TYPE,
60977  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_179_WIDTH },
60978  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_180_CHECKER_TYPE,
60979  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_180_WIDTH },
60980  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_181_CHECKER_TYPE,
60981  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_181_WIDTH },
60982  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_182_CHECKER_TYPE,
60983  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_182_WIDTH },
60984  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_183_CHECKER_TYPE,
60985  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_183_WIDTH },
60986  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_184_CHECKER_TYPE,
60987  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_184_WIDTH },
60988  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_185_CHECKER_TYPE,
60989  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_185_WIDTH },
60990  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_186_CHECKER_TYPE,
60991  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_186_WIDTH },
60992  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_187_CHECKER_TYPE,
60993  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_187_WIDTH },
60994  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_188_CHECKER_TYPE,
60995  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_188_WIDTH },
60996  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_189_CHECKER_TYPE,
60997  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_189_WIDTH },
60998  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_190_CHECKER_TYPE,
60999  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_190_WIDTH },
61000  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_191_CHECKER_TYPE,
61001  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_191_WIDTH },
61002  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_192_CHECKER_TYPE,
61003  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_192_WIDTH },
61004  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_193_CHECKER_TYPE,
61005  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_193_WIDTH },
61006  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_194_CHECKER_TYPE,
61007  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_194_WIDTH },
61008  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_195_CHECKER_TYPE,
61009  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_195_WIDTH },
61010  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_196_CHECKER_TYPE,
61011  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_196_WIDTH },
61012  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_197_CHECKER_TYPE,
61013  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_197_WIDTH },
61014  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_198_CHECKER_TYPE,
61015  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_198_WIDTH },
61016  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_199_CHECKER_TYPE,
61017  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_GROUP_199_WIDTH },
61018 };
61019 
61025 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61026 {
61027  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61028  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_0_WIDTH },
61029  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61030  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_1_WIDTH },
61031  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61032  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_2_WIDTH },
61033  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61034  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_3_WIDTH },
61035  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61036  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_4_WIDTH },
61037  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61038  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_5_WIDTH },
61039  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61040  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_6_WIDTH },
61041  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61042  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_7_WIDTH },
61043  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61044  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_GROUP_8_WIDTH },
61045 };
61046 
61052 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61053 {
61054  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61055  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61056  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61057  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61058  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61059  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61060  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61061  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61062  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61063  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61064  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61065  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61066  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61067  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61068  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61069  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61070  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61071  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61072  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61073  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61074  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61075  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61076  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61077  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61078  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61079  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61080  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61081  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61082  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61083  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61084 };
61085 
61091 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61092 {
61093  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61094  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61095  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61096  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61097  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61098  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61099  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61100  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61101 };
61102 
61108 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61109 {
61110  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61111  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
61112  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61113  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
61114  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61115  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
61116  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61117  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
61118  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61119  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
61120  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61121  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
61122  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61123  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
61124  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61125  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
61126  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61127  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
61128  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61129  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
61130  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61131  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
61132  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61133  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
61134  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61135  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
61136  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61137  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
61138  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61139  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
61140  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
61141  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
61142  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
61143  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
61144  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
61145  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
61146  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
61147  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
61148  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
61149  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
61150  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
61151  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
61152  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
61153  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
61154  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
61155  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
61156  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
61157  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
61158  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
61159  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
61160  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
61161  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
61162  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
61163  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
61164  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
61165  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
61166  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
61167  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
61168  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
61169  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
61170  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
61171  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
61172  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
61173  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
61174  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
61175  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
61176  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
61177  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
61178  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
61179  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
61180  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
61181  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
61182  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
61183  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
61184  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
61185  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
61186  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
61187  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
61188  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
61189  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
61190  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
61191  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
61192  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
61193  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
61194  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
61195  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
61196  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
61197  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
61198  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
61199  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
61200  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
61201  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
61202  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
61203  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
61204  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
61205  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
61206  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
61207  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
61208  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
61209  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
61210  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
61211  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
61212  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
61213  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
61214  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
61215  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
61216  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
61217  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
61218  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
61219  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
61220  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
61221  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
61222  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
61223  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
61224  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
61225  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
61226  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
61227  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
61228  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
61229  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
61230  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
61231  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
61232  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
61233  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
61234  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
61235  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
61236  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
61237  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
61238  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
61239  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
61240  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
61241  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
61242  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
61243  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
61244  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
61245  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
61246  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
61247  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
61248  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
61249  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
61250  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
61251  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
61252  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
61253  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
61254  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
61255  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
61256  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
61257  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
61258  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
61259  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
61260  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
61261  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
61262  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
61263  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
61264  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
61265  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
61266  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
61267  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
61268  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
61269  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
61270  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
61271  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
61272  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
61273  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
61274  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
61275  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
61276  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
61277  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
61278  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
61279  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
61280  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
61281  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
61282  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
61283  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
61284  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
61285  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
61286  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
61287  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
61288  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
61289  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
61290  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
61291  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
61292  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
61293  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
61294  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
61295  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
61296  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
61297  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
61298  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
61299  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
61300  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
61301  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
61302  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
61303  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
61304  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
61305  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
61306  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
61307  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
61308  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
61309  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
61310  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
61311  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
61312  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
61313  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
61314  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
61315  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
61316  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
61317  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
61318  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
61319  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
61320  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
61321  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
61322 };
61323 
61329 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61330 {
61331  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61332  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61333  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61334  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61335  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61336  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61337  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61338  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61339  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61340  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61341  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61342  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61343  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61344  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61345  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61346  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61347  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61348  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61349  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61350  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61351  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61352  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61353  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61354  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61355  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61356  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61357  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61358  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61359  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61360  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61361 };
61362 
61368 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61369 {
61370  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61371  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61372  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61373  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61374  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61375  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61376  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61377  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61378 };
61379 
61385 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61386 {
61387  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61388  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61389  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61390  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61391  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61392  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61393  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61394  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61395  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61396  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61397  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61398  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61399  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61400  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61401  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61402  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61403  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61404  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61405  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61406  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61407  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61408  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61409  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61410  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61411  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61412  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61413  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61414  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61415  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61416  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61417 };
61418 
61424 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61425 {
61426  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61427  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61428  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61429  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61430  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61431  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61432  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61433  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61434 };
61435 
61441 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61442 {
61443  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61444  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61445  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61446  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61447  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61448  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61449  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61450  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61451  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61452  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61453  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61454  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61455  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61456  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61457  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61458  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61459  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61460  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61461  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61462  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61463  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61464  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61465  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61466  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61467  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61468  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61469  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61470  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61471  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61472  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61473 };
61474 
61480 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61481 {
61482  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61483  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61484  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61485  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61486  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61487  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61488  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61489  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61490 };
61491 
61497 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61498 {
61499  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61500  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61501  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61502  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61503  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61504  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61505  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61506  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61507  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61508  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61509  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61510  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61511  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61512  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61513  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61514  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61515  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61516  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61517  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61518  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61519  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61520  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61521  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61522  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61523  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61524  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61525  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61526  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61527  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61528  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61529 };
61530 
61536 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61537 {
61538  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61539  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61540  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61541  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61542  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61543  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61544  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61545  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61546 };
61547 
61553 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61554 {
61555  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61556  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61557  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61558  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61559  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61560  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61561  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61562  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61563  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61564  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61565  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61566  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61567  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61568  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61569  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61570  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61571  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61572  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61573  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61574  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61575  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61576  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61577  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61578  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61579  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61580  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61581  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61582  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61583  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61584  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61585 };
61586 
61592 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61593 {
61594  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61595  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61596  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61597  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61598  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61599  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61600  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61601  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61602 };
61603 
61609 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61610 {
61611  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61612  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61613  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61614  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61615  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61616  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61617  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61618  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61619  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61620  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61621  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61622  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61623  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61624  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61625  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61626  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61627  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61628  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61629  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61630  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61631  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61632  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61633  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61634  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61635  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61636  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61637  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61638  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61639  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61640  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61641 };
61642 
61648 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61649 {
61650  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61651  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61652  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61653  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61654  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61655  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61656  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61657  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61658 };
61659 
61665 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61666 {
61667  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61668  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61669  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61670  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61671  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61672  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61673  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61674  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61675  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61676  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61677  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61678  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61679  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61680  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61681  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61682  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61683  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61684  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61685  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61686  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61687  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61688  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61689  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61690  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61691  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61692  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61693  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61694  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61695  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61696  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61697 };
61698 
61704 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61705 {
61706  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61707  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61708  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61709  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61710  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61711  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61712  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61713  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61714 };
61715 
61721 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61722 {
61723  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61724  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
61725  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61726  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
61727  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61728  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
61729  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61730  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
61731  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61732  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
61733  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61734  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
61735  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61736  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
61737  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61738  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
61739  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61740  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
61741  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61742  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
61743  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61744  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
61745  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61746  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
61747  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61748  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
61749  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61750  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
61751  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61752  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
61753 };
61754 
61760 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61761 {
61762  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61763  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
61764  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61765  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
61766  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61767  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
61768  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61769  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
61770 };
61771 
61777 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
61778 {
61779  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
61780  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
61781  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
61782  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
61783  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
61784  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
61785  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
61786  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
61787  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
61788  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
61789  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
61790  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
61791  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
61792  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
61793  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
61794  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
61795  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
61796  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
61797  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
61798  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
61799  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
61800  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
61801  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
61802  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
61803  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
61804  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
61805  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
61806  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
61807  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
61808  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
61809  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
61810  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
61811  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
61812  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
61813  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
61814  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
61815  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
61816  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
61817  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
61818  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
61819  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
61820  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
61821  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
61822  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
61823  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
61824  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
61825  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
61826  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
61827  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
61828  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
61829  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
61830  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
61831  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
61832  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
61833  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
61834  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
61835  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
61836  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
61837  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
61838  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
61839  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
61840  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
61841  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
61842  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
61843  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
61844  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
61845  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
61846  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
61847  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
61848  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
61849  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
61850  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
61851  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
61852  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
61853  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
61854  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
61855  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
61856  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
61857  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
61858  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
61859  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
61860  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
61861  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
61862  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
61863  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
61864  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
61865  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
61866  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
61867  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
61868  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
61869  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
61870  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
61871  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
61872  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
61873  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
61874  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
61875  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
61876  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
61877  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
61878  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
61879  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
61880  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
61881  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
61882  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
61883  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
61884  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
61885  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
61886  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
61887  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
61888  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
61889  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
61890  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
61891  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
61892  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
61893  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
61894  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
61895  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
61896  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
61897  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
61898  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
61899  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
61900  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
61901  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
61902  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
61903  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
61904  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_62_WIDTH },
61905  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
61906  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_63_WIDTH },
61907  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
61908  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_64_WIDTH },
61909  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
61910  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_65_WIDTH },
61911  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
61912  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_66_WIDTH },
61913  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
61914  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_67_WIDTH },
61915  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
61916  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_68_WIDTH },
61917  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
61918  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_69_WIDTH },
61919  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
61920  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_70_WIDTH },
61921  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
61922  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_71_WIDTH },
61923  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
61924  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_72_WIDTH },
61925  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
61926  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_73_WIDTH },
61927  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
61928  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_74_WIDTH },
61929  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
61930  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_75_WIDTH },
61931  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
61932  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_76_WIDTH },
61933  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
61934  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_77_WIDTH },
61935  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
61936  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_78_WIDTH },
61937  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
61938  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_79_WIDTH },
61939  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
61940  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_80_WIDTH },
61941  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
61942  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_81_WIDTH },
61943  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
61944  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_82_WIDTH },
61945  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
61946  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_83_WIDTH },
61947  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
61948  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_84_WIDTH },
61949  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
61950  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_85_WIDTH },
61951  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
61952  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_86_WIDTH },
61953  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
61954  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_87_WIDTH },
61955  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
61956  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_88_WIDTH },
61957  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
61958  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_89_WIDTH },
61959  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
61960  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_90_WIDTH },
61961  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
61962  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_91_WIDTH },
61963  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
61964  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_92_WIDTH },
61965  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
61966  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_93_WIDTH },
61967  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
61968  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_94_WIDTH },
61969  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
61970  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_95_WIDTH },
61971  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
61972  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_96_WIDTH },
61973  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
61974  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_97_WIDTH },
61975  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
61976  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_98_WIDTH },
61977  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
61978  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_99_WIDTH },
61979  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
61980  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_100_WIDTH },
61981  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
61982  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_101_WIDTH },
61983  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
61984  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_102_WIDTH },
61985  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
61986  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_103_WIDTH },
61987  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
61988  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_104_WIDTH },
61989  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
61990  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_105_WIDTH },
61991  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
61992  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_106_WIDTH },
61993  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
61994  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_107_WIDTH },
61995  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
61996  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_108_WIDTH },
61997  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
61998  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_109_WIDTH },
61999  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
62000  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_110_WIDTH },
62001  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
62002  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_111_WIDTH },
62003  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
62004  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_112_WIDTH },
62005  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
62006  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_113_WIDTH },
62007  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
62008  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_114_WIDTH },
62009  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
62010  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_115_WIDTH },
62011  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
62012  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_116_WIDTH },
62013  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
62014  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_117_WIDTH },
62015  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
62016  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_118_WIDTH },
62017  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
62018  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_119_WIDTH },
62019  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
62020  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_120_WIDTH },
62021  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
62022  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_121_WIDTH },
62023  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
62024  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_122_WIDTH },
62025  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
62026  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_123_WIDTH },
62027  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
62028  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_124_WIDTH },
62029  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
62030  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_125_WIDTH },
62031  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
62032  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_126_WIDTH },
62033  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
62034  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_127_WIDTH },
62035  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
62036  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_128_WIDTH },
62037  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
62038  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_129_WIDTH },
62039  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
62040  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_130_WIDTH },
62041  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
62042  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_131_WIDTH },
62043  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
62044  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_132_WIDTH },
62045  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
62046  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_133_WIDTH },
62047  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
62048  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_134_WIDTH },
62049  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
62050  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_135_WIDTH },
62051  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
62052  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_136_WIDTH },
62053  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
62054  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_137_WIDTH },
62055  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
62056  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_138_WIDTH },
62057  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
62058  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_139_WIDTH },
62059  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
62060  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_140_WIDTH },
62061  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
62062  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_141_WIDTH },
62063  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
62064  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_142_WIDTH },
62065  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
62066  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_143_WIDTH },
62067  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
62068  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_144_WIDTH },
62069  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
62070  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_145_WIDTH },
62071  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
62072  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_146_WIDTH },
62073  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
62074  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_147_WIDTH },
62075  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
62076  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_148_WIDTH },
62077  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
62078  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_149_WIDTH },
62079  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
62080  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_150_WIDTH },
62081  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
62082  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_151_WIDTH },
62083  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
62084  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_152_WIDTH },
62085  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
62086  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_153_WIDTH },
62087  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
62088  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_154_WIDTH },
62089  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
62090  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_155_WIDTH },
62091  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
62092  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_156_WIDTH },
62093  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
62094  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_157_WIDTH },
62095  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
62096  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_158_WIDTH },
62097  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
62098  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_159_WIDTH },
62099  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
62100  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_160_WIDTH },
62101  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
62102  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_161_WIDTH },
62103  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
62104  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_162_WIDTH },
62105  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
62106  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_163_WIDTH },
62107  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
62108  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_164_WIDTH },
62109  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
62110  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_165_WIDTH },
62111  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
62112  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_166_WIDTH },
62113  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
62114  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_167_WIDTH },
62115  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
62116  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_168_WIDTH },
62117  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
62118  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_169_WIDTH },
62119  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
62120  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_170_WIDTH },
62121  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
62122  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_171_WIDTH },
62123  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
62124  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_172_WIDTH },
62125  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
62126  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_173_WIDTH },
62127  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
62128  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_174_WIDTH },
62129  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
62130  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_175_WIDTH },
62131  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
62132  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_176_WIDTH },
62133  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
62134  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_177_WIDTH },
62135  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
62136  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_178_WIDTH },
62137  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
62138  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_179_WIDTH },
62139  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
62140  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_180_WIDTH },
62141  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
62142  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_181_WIDTH },
62143  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
62144  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_182_WIDTH },
62145  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
62146  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_183_WIDTH },
62147  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
62148  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_184_WIDTH },
62149  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
62150  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_185_WIDTH },
62151  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
62152  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_186_WIDTH },
62153  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
62154  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_187_WIDTH },
62155  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
62156  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_188_WIDTH },
62157  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
62158  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_189_WIDTH },
62159  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
62160  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_190_WIDTH },
62161  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
62162  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_191_WIDTH },
62163  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
62164  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_192_WIDTH },
62165  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
62166  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_193_WIDTH },
62167  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
62168  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_194_WIDTH },
62169  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
62170  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_195_WIDTH },
62171  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
62172  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_196_WIDTH },
62173  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
62174  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_197_WIDTH },
62175  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
62176  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_198_WIDTH },
62177  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
62178  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_199_WIDTH },
62179  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
62180  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_200_WIDTH },
62181  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
62182  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_201_WIDTH },
62183  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
62184  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_202_WIDTH },
62185  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
62186  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_203_WIDTH },
62187  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
62188  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_204_WIDTH },
62189  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
62190  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_205_WIDTH },
62191  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
62192  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_206_WIDTH },
62193  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
62194  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_207_WIDTH },
62195  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
62196  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_208_WIDTH },
62197  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
62198  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_209_WIDTH },
62199  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
62200  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_210_WIDTH },
62201  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
62202  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_211_WIDTH },
62203  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
62204  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_212_WIDTH },
62205  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
62206  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_213_WIDTH },
62207  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
62208  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_214_WIDTH },
62209  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
62210  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_215_WIDTH },
62211  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
62212  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_216_WIDTH },
62213  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
62214  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_217_WIDTH },
62215  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
62216  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_218_WIDTH },
62217  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
62218  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_219_WIDTH },
62219  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
62220  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_220_WIDTH },
62221  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
62222  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_221_WIDTH },
62223  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
62224  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_222_WIDTH },
62225  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
62226  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_223_WIDTH },
62227  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
62228  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_224_WIDTH },
62229  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
62230  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_225_WIDTH },
62231  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
62232  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_226_WIDTH },
62233  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
62234  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_227_WIDTH },
62235  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
62236  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_228_WIDTH },
62237  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
62238  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_229_WIDTH },
62239  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
62240  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_230_WIDTH },
62241  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
62242  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_231_WIDTH },
62243  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
62244  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_232_WIDTH },
62245  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
62246  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_233_WIDTH },
62247  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
62248  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_234_WIDTH },
62249  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
62250  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_235_WIDTH },
62251  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
62252  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_236_WIDTH },
62253  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
62254  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_237_WIDTH },
62255  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
62256  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_238_WIDTH },
62257  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
62258  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_239_WIDTH },
62259  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
62260  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_240_WIDTH },
62261  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
62262  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_241_WIDTH },
62263  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
62264  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_242_WIDTH },
62265  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
62266  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_243_WIDTH },
62267  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
62268  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_244_WIDTH },
62269  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
62270  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_245_WIDTH },
62271  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
62272  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_246_WIDTH },
62273  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
62274  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_247_WIDTH },
62275  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
62276  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_248_WIDTH },
62277  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
62278  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_249_WIDTH },
62279  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
62280  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_250_WIDTH },
62281  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
62282  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_251_WIDTH },
62283  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
62284  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_252_WIDTH },
62285  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
62286  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_253_WIDTH },
62287  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
62288  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_254_WIDTH },
62289  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
62290  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_255_WIDTH },
62291 };
62292 
62298 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS] =
62299 {
62300  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
62301  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_0_WIDTH },
62302  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
62303  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_1_WIDTH },
62304  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
62305  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_2_WIDTH },
62306  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
62307  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_3_WIDTH },
62308  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
62309  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_4_WIDTH },
62310  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
62311  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_5_WIDTH },
62312  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
62313  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_6_WIDTH },
62314  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
62315  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_7_WIDTH },
62316  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
62317  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_8_WIDTH },
62318  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
62319  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_9_WIDTH },
62320  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
62321  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_10_WIDTH },
62322  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
62323  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_11_WIDTH },
62324  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
62325  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_12_WIDTH },
62326  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
62327  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_13_WIDTH },
62328  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
62329  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_14_WIDTH },
62330  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
62331  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_15_WIDTH },
62332  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
62333  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_16_WIDTH },
62334  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
62335  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_17_WIDTH },
62336  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
62337  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_18_WIDTH },
62338  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
62339  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_19_WIDTH },
62340  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
62341  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_20_WIDTH },
62342  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
62343  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_21_WIDTH },
62344  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
62345  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_22_WIDTH },
62346  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
62347  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_23_WIDTH },
62348  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
62349  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_24_WIDTH },
62350  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
62351  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_25_WIDTH },
62352  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
62353  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_26_WIDTH },
62354  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
62355  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_27_WIDTH },
62356  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
62357  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_28_WIDTH },
62358  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
62359  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_29_WIDTH },
62360  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
62361  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_30_WIDTH },
62362  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
62363  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_31_WIDTH },
62364  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
62365  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_32_WIDTH },
62366  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
62367  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_33_WIDTH },
62368  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
62369  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_34_WIDTH },
62370  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
62371  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_35_WIDTH },
62372  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
62373  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_36_WIDTH },
62374  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
62375  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_37_WIDTH },
62376  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
62377  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_38_WIDTH },
62378  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
62379  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_39_WIDTH },
62380  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
62381  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_40_WIDTH },
62382  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
62383  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_41_WIDTH },
62384  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
62385  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_42_WIDTH },
62386  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
62387  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_43_WIDTH },
62388  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
62389  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_44_WIDTH },
62390  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
62391  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_45_WIDTH },
62392  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
62393  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_46_WIDTH },
62394  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
62395  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_47_WIDTH },
62396  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
62397  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_48_WIDTH },
62398  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
62399  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_49_WIDTH },
62400  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
62401  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_50_WIDTH },
62402  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
62403  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_51_WIDTH },
62404  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
62405  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_52_WIDTH },
62406  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
62407  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_53_WIDTH },
62408  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
62409  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_54_WIDTH },
62410  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
62411  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_55_WIDTH },
62412  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
62413  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_56_WIDTH },
62414  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
62415  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_57_WIDTH },
62416  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
62417  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_58_WIDTH },
62418  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
62419  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_59_WIDTH },
62420  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
62421  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_60_WIDTH },
62422  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
62423  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_61_WIDTH },
62424  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
62425  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_62_WIDTH },
62426  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
62427  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_63_WIDTH },
62428  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
62429  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_64_WIDTH },
62430  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
62431  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_65_WIDTH },
62432  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
62433  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_66_WIDTH },
62434  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
62435  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_67_WIDTH },
62436  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
62437  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_68_WIDTH },
62438  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
62439  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_69_WIDTH },
62440  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
62441  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_70_WIDTH },
62442  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
62443  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_71_WIDTH },
62444  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
62445  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_72_WIDTH },
62446  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
62447  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_73_WIDTH },
62448  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
62449  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_74_WIDTH },
62450  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
62451  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_75_WIDTH },
62452  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
62453  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_76_WIDTH },
62454  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
62455  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_77_WIDTH },
62456  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
62457  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_78_WIDTH },
62458  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
62459  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_79_WIDTH },
62460  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
62461  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_80_WIDTH },
62462  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
62463  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_81_WIDTH },
62464  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
62465  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_82_WIDTH },
62466  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
62467  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_83_WIDTH },
62468  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
62469  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_84_WIDTH },
62470  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
62471  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_85_WIDTH },
62472  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
62473  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_86_WIDTH },
62474  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
62475  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_87_WIDTH },
62476  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
62477  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_88_WIDTH },
62478  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
62479  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_89_WIDTH },
62480  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
62481  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_90_WIDTH },
62482  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
62483  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_91_WIDTH },
62484  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
62485  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_92_WIDTH },
62486  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
62487  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_93_WIDTH },
62488  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
62489  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_94_WIDTH },
62490  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
62491  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_95_WIDTH },
62492  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
62493  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_96_WIDTH },
62494  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
62495  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_97_WIDTH },
62496  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
62497  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_98_WIDTH },
62498  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
62499  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_99_WIDTH },
62500  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
62501  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_100_WIDTH },
62502  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
62503  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_101_WIDTH },
62504  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
62505  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_102_WIDTH },
62506  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
62507  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_103_WIDTH },
62508  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
62509  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_104_WIDTH },
62510  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
62511  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_105_WIDTH },
62512  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
62513  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_106_WIDTH },
62514  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
62515  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_107_WIDTH },
62516  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
62517  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_108_WIDTH },
62518  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
62519  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_109_WIDTH },
62520  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
62521  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_110_WIDTH },
62522  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
62523  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_111_WIDTH },
62524  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
62525  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_112_WIDTH },
62526  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
62527  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_113_WIDTH },
62528  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
62529  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_114_WIDTH },
62530  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
62531  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_115_WIDTH },
62532  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
62533  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_116_WIDTH },
62534  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
62535  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_117_WIDTH },
62536  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
62537  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_118_WIDTH },
62538  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
62539  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_119_WIDTH },
62540  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
62541  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_120_WIDTH },
62542  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
62543  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_121_WIDTH },
62544  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
62545  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_122_WIDTH },
62546  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
62547  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_123_WIDTH },
62548  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
62549  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_124_WIDTH },
62550  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
62551  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_125_WIDTH },
62552  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
62553  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_126_WIDTH },
62554  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
62555  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_127_WIDTH },
62556  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
62557  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_128_WIDTH },
62558  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
62559  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_129_WIDTH },
62560  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
62561  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_130_WIDTH },
62562  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
62563  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_131_WIDTH },
62564  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
62565  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_132_WIDTH },
62566  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
62567  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_133_WIDTH },
62568  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
62569  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_134_WIDTH },
62570  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
62571  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_135_WIDTH },
62572  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
62573  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_136_WIDTH },
62574  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
62575  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_137_WIDTH },
62576  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
62577  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_138_WIDTH },
62578  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
62579  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_139_WIDTH },
62580  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
62581  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_140_WIDTH },
62582  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
62583  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_141_WIDTH },
62584  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
62585  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_142_WIDTH },
62586  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
62587  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_143_WIDTH },
62588  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
62589  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_144_WIDTH },
62590  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
62591  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_145_WIDTH },
62592  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
62593  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_146_WIDTH },
62594  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
62595  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_147_WIDTH },
62596  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
62597  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_148_WIDTH },
62598  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
62599  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_149_WIDTH },
62600  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
62601  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_150_WIDTH },
62602  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
62603  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_151_WIDTH },
62604  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
62605  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_152_WIDTH },
62606  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
62607  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_153_WIDTH },
62608  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
62609  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_154_WIDTH },
62610  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
62611  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_155_WIDTH },
62612  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
62613  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_156_WIDTH },
62614  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
62615  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_157_WIDTH },
62616  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
62617  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_158_WIDTH },
62618  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
62619  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_159_WIDTH },
62620  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
62621  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_160_WIDTH },
62622  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
62623  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_161_WIDTH },
62624  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
62625  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_162_WIDTH },
62626  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
62627  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_GROUP_163_WIDTH },
62628 };
62629 
62634 static const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES] =
62635 {
62636  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_RAM_ID, 0u,
62637  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_RAM_SIZE, 4u,
62638  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
62639  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_RAM_ID, 0u,
62640  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_RAM_SIZE, 4u,
62641  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
62642  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_RAM_ID, 0u,
62643  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_RAM_SIZE, 4u,
62644  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
62645  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_RAM_ID, 0u,
62646  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_RAM_SIZE, 4u,
62647  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_ROW_WIDTH, ((bool)false) },
62648  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_RAM_ID, 0u,
62649  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_RAM_SIZE, 4u,
62650  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
62651 };
62652 
62658 static const SDL_GrpChkConfig_t SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries[SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS] =
62659 {
62660  { SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
62661  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_0_WIDTH },
62662  { SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
62663  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_GROUP_1_WIDTH },
62664 };
62665 
62670 static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
62671 {
62672  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2738000u,
62673  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
62674  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
62675 };
62676 
62682 static const SDL_GrpChkConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
62683 {
62684  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
62685  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
62686 };
62687 
62692 static const SDL_MemConfig_t SDL_PCIE3_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES] =
62693 {
62694  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
62695  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
62696  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
62697  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID, 0u,
62698  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_SIZE, 4u,
62699  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ROW_WIDTH, ((bool)false) },
62700  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
62701  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
62702  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
62703  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID, 0u,
62704  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_SIZE, 4u,
62705  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
62706  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
62707  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
62708  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
62709  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
62710  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
62711  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
62712  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID, 0u,
62713  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_SIZE, 4u,
62714  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ROW_WIDTH, ((bool)false) },
62715 };
62716 
62721 static const SDL_MemConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_MemEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
62722 {
62723  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PSTATE_RAM_ID, 0u,
62724  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PSTATE_RAM_SIZE, 4u,
62725  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PSTATE_ROW_WIDTH, ((bool)false) },
62726  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PCONFIG_RAM_ID, 0u,
62727  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PCONFIG_RAM_SIZE, 4u,
62728  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PCONFIG_ROW_WIDTH, ((bool)false) },
62729  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_CF_RAM_ID, 0u,
62730  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_CF_RAM_SIZE, 4u,
62731  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_CF_ROW_WIDTH, ((bool)false) },
62732  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_DF_RAM_ID, 0u,
62733  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_DF_RAM_SIZE, 4u,
62734  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_DF_ROW_WIDTH, ((bool)false) },
62735  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_PF_RAM_ID, 0u,
62736  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_PF_RAM_SIZE, 4u,
62737  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_PF_ROW_WIDTH, ((bool)false) },
62738  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_SB_RAM_ID, 0u,
62739  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_SB_RAM_SIZE, 4u,
62740  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_SB_ROW_WIDTH, ((bool)false) },
62741  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_RAM_ID, 0u,
62742  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
62743  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
62744  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PSTATE_RAM_ID, 0u,
62745  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PSTATE_RAM_SIZE, 4u,
62746  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PSTATE_ROW_WIDTH, ((bool)false) },
62747  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PCONFIG_RAM_ID, 0u,
62748  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PCONFIG_RAM_SIZE, 4u,
62749  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PCONFIG_ROW_WIDTH, ((bool)false) },
62750  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PQINFO_RAM_ID, 0u,
62751  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PQINFO_RAM_SIZE, 4u,
62752  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PQINFO_ROW_WIDTH, ((bool)false) },
62753  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_CF_RAM_ID, 0u,
62754  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_CF_RAM_SIZE, 4u,
62755  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_CF_ROW_WIDTH, ((bool)false) },
62756  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_DF_RAM_ID, 0u,
62757  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_DF_RAM_SIZE, 4u,
62758  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_DF_ROW_WIDTH, ((bool)false) },
62759  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_PF_RAM_ID, 0u,
62760  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_PF_RAM_SIZE, 4u,
62761  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_PF_ROW_WIDTH, ((bool)false) },
62762  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB0_RAM_ID, 0u,
62763  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB0_RAM_SIZE, 4u,
62764  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB0_ROW_WIDTH, ((bool)false) },
62765  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB1_RAM_ID, 0u,
62766  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB1_RAM_SIZE, 4u,
62767  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB1_ROW_WIDTH, ((bool)false) },
62768  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB2_RAM_ID, 0u,
62769  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB2_RAM_SIZE, 4u,
62770  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB2_ROW_WIDTH, ((bool)false) },
62771  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_RAM_ID, 0u,
62772  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
62773  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
62774  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB0_RAM_ID, 0u,
62775  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB0_RAM_SIZE, 4u,
62776  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB0_ROW_WIDTH, ((bool)false) },
62777  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB1_RAM_ID, 0u,
62778  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB1_RAM_SIZE, 4u,
62779  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB1_ROW_WIDTH, ((bool)false) },
62780  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB2_RAM_ID, 0u,
62781  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB2_RAM_SIZE, 4u,
62782  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB2_ROW_WIDTH, ((bool)false) },
62783  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_RAM_ID, 0u,
62784  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
62785  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
62786  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB0_RAM_ID, 0u,
62787  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB0_RAM_SIZE, 4u,
62788  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB0_ROW_WIDTH, ((bool)false) },
62789  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB1_RAM_ID, 0u,
62790  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB1_RAM_SIZE, 4u,
62791  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB1_ROW_WIDTH, ((bool)false) },
62792  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_RAM_ID, 0u,
62793  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
62794  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
62795  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TCFG_STATE_RAM_ID, 0u,
62796  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TCFG_STATE_RAM_SIZE, 4u,
62797  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TCFG_STATE_ROW_WIDTH, ((bool)false) },
62798  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F0_RAM_ID, 0u,
62799  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F0_RAM_SIZE, 4u,
62800  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F0_ROW_WIDTH, ((bool)false) },
62801  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F1_RAM_ID, 0u,
62802  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F1_RAM_SIZE, 4u,
62803  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F1_ROW_WIDTH, ((bool)false) },
62804  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_C0_RAM_ID, 0u,
62805  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_C0_RAM_SIZE, 4u,
62806  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_C0_ROW_WIDTH, ((bool)false) },
62807  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RFLOWFW_RFFW_RAM_ID, 0u,
62808  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RFLOWFW_RFFW_RAM_SIZE, 4u,
62809  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RFLOWFW_RFFW_ROW_WIDTH, ((bool)false) },
62810  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F0_RAM_ID, 0u,
62811  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F0_RAM_SIZE, 4u,
62812  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F0_ROW_WIDTH, ((bool)false) },
62813  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F1_RAM_ID, 0u,
62814  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F1_RAM_SIZE, 4u,
62815  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F1_ROW_WIDTH, ((bool)false) },
62816  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C0_RAM_ID, 0u,
62817  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C0_RAM_SIZE, 4u,
62818  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C0_ROW_WIDTH, ((bool)false) },
62819  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_WC0_RAM_ID, 0u,
62820  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_WC0_RAM_SIZE, 4u,
62821  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_WC0_ROW_WIDTH, ((bool)false) },
62822  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C1_RAM_ID, 0u,
62823  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C1_RAM_SIZE, 4u,
62824  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C1_ROW_WIDTH, ((bool)false) },
62825  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW0_RAM_ID, 0u,
62826  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW0_RAM_SIZE, 4u,
62827  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW0_ROW_WIDTH, ((bool)false) },
62828  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW1_RAM_ID, 0u,
62829  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW1_RAM_SIZE, 4u,
62830  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW1_ROW_WIDTH, ((bool)false) },
62831  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RSTATE_RAM_ID, 0u,
62832  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RSTATE_RAM_SIZE, 4u,
62833  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RSTATE_ROW_WIDTH, ((bool)false) },
62834  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PROXY_PCONFIG_RAM_ID, 0u,
62835  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PROXY_PCONFIG_RAM_SIZE, 4u,
62836  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PROXY_PCONFIG_ROW_WIDTH, ((bool)false) },
62837  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EHANDLER_ECONFIG_RAM_ID, 0u,
62838  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EHANDLER_ECONFIG_RAM_SIZE, 4u,
62839  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EHANDLER_ECONFIG_ROW_WIDTH, ((bool)false) },
62840  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST0_RAM_ID, 0u,
62841  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST0_RAM_SIZE, 4u,
62842  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST0_ROW_WIDTH, ((bool)false) },
62843  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST1_RAM_ID, 0u,
62844  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST1_RAM_SIZE, 4u,
62845  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST1_ROW_WIDTH, ((bool)false) },
62846  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR0_RAM_ID, 0u,
62847  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR0_RAM_SIZE, 4u,
62848  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR0_ROW_WIDTH, ((bool)false) },
62849  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR1_RAM_ID, 0u,
62850  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR1_RAM_SIZE, 4u,
62851  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR1_ROW_WIDTH, ((bool)false) },
62852  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_RAM_ID, 0u,
62853  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
62854  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
62855  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_RAM_ID, 0u,
62856  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_RAM_SIZE, 4u,
62857  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_ROW_WIDTH, ((bool)false) },
62858  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC0_SB_RAM_ID, 0u,
62859  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC0_SB_RAM_SIZE, 4u,
62860  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC0_SB_ROW_WIDTH, ((bool)false) },
62861  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC1_SB_RAM_ID, 0u,
62862  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC1_SB_RAM_SIZE, 4u,
62863  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC1_SB_ROW_WIDTH, ((bool)false) },
62864  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC2_SB_RAM_ID, 0u,
62865  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC2_SB_RAM_SIZE, 4u,
62866  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC2_SB_ROW_WIDTH, ((bool)false) },
62867  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC0_SB_RAM_ID, 0u,
62868  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC0_SB_RAM_SIZE, 4u,
62869  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC0_SB_ROW_WIDTH, ((bool)false) },
62870  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC3_SB_RAM_ID, 0u,
62871  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC3_SB_RAM_SIZE, 4u,
62872  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC3_SB_ROW_WIDTH, ((bool)false) },
62873  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_RAM_ID, 0u,
62874  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_RAM_SIZE, 4u,
62875  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_ROW_WIDTH, ((bool)false) },
62876  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_TRETID_RAM_ID, 0u,
62877  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_TRETID_RAM_SIZE, 4u,
62878  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_TRETID_ROW_WIDTH, ((bool)false) },
62879  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_RAM_ID, 0u,
62880  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_RAM_SIZE, 4u,
62881  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_ROW_WIDTH, ((bool)false) },
62882  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_RAM_ID, 0u,
62883  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_RAM_SIZE, 4u,
62884  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_ROW_WIDTH, ((bool)false) },
62885  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_STRAM_RAM_ID, 0u,
62886  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_STRAM_RAM_SIZE, 4u,
62887  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_STRAM_ROW_WIDTH, ((bool)false) },
62888  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_1536X15_SWW_SR_RAM_ID, 0u,
62889  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_1536X15_SWW_SR_RAM_SIZE, 4u,
62890  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_1536X15_SWW_SR_ROW_WIDTH, ((bool)false) },
62891  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_RAM_ID, 0u,
62892  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_RAM_SIZE, 4u,
62893  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_ROW_WIDTH, ((bool)false) },
62894  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_128X32_SWW_SR_RAM_ID, 0u,
62895  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_128X32_SWW_SR_RAM_SIZE, 4u,
62896  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_128X32_SWW_SR_ROW_WIDTH, ((bool)false) },
62897  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_256X48_SWW_SR_RAM_ID, 0u,
62898  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_256X48_SWW_SR_RAM_SIZE, 4u,
62899  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_256X48_SWW_SR_ROW_WIDTH, ((bool)false) },
62900 };
62901 
62907 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
62908 {
62909  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
62910  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_0_WIDTH },
62911  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
62912  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_1_WIDTH },
62913  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
62914  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_2_WIDTH },
62915  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
62916  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_3_WIDTH },
62917  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
62918  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_4_WIDTH },
62919  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
62920  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_GROUP_5_WIDTH },
62921 };
62922 
62928 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
62929 {
62930  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
62931  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_0_WIDTH },
62932  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
62933  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_1_WIDTH },
62934  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
62935  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_2_WIDTH },
62936  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
62937  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_3_WIDTH },
62938  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
62939  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_4_WIDTH },
62940  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
62941  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_5_WIDTH },
62942  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
62943  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_6_WIDTH },
62944  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
62945  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_7_WIDTH },
62946  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
62947  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_8_WIDTH },
62948  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
62949  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_9_WIDTH },
62950  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
62951  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_10_WIDTH },
62952  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
62953  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_11_WIDTH },
62954  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
62955  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_12_WIDTH },
62956  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
62957  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_13_WIDTH },
62958  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
62959  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_14_WIDTH },
62960  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
62961  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_15_WIDTH },
62962  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
62963  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_16_WIDTH },
62964  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
62965  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_17_WIDTH },
62966  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
62967  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_18_WIDTH },
62968  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
62969  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_19_WIDTH },
62970  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
62971  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_20_WIDTH },
62972  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
62973  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_21_WIDTH },
62974  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
62975  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_22_WIDTH },
62976  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
62977  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_23_WIDTH },
62978  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
62979  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_24_WIDTH },
62980  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
62981  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_25_WIDTH },
62982  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
62983  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_26_WIDTH },
62984  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
62985  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_27_WIDTH },
62986  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
62987  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_28_WIDTH },
62988  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
62989  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_29_WIDTH },
62990  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
62991  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_30_WIDTH },
62992  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
62993  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_31_WIDTH },
62994  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
62995  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_32_WIDTH },
62996  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
62997  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_33_WIDTH },
62998  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
62999  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_34_WIDTH },
63000  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
63001  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_35_WIDTH },
63002  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
63003  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_36_WIDTH },
63004  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
63005  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_37_WIDTH },
63006  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
63007  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_38_WIDTH },
63008  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
63009  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_39_WIDTH },
63010  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
63011  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_40_WIDTH },
63012  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
63013  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_41_WIDTH },
63014  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
63015  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_42_WIDTH },
63016  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
63017  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_43_WIDTH },
63018  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
63019  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_44_WIDTH },
63020  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
63021  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_45_WIDTH },
63022  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
63023  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_46_WIDTH },
63024  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
63025  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_47_WIDTH },
63026  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
63027  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_48_WIDTH },
63028  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
63029  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_49_WIDTH },
63030  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
63031  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_50_WIDTH },
63032  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
63033  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_51_WIDTH },
63034  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
63035  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_52_WIDTH },
63036  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
63037  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_53_WIDTH },
63038  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
63039  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_54_WIDTH },
63040  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
63041  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_55_WIDTH },
63042  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
63043  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_56_WIDTH },
63044  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
63045  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_57_WIDTH },
63046  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
63047  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_58_WIDTH },
63048  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
63049  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_59_WIDTH },
63050  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
63051  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_60_WIDTH },
63052  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
63053  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_61_WIDTH },
63054  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
63055  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_62_WIDTH },
63056  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
63057  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_63_WIDTH },
63058  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
63059  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_64_WIDTH },
63060  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
63061  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_65_WIDTH },
63062  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
63063  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_66_WIDTH },
63064  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
63065  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_67_WIDTH },
63066  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
63067  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_68_WIDTH },
63068  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
63069  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_69_WIDTH },
63070  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
63071  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_70_WIDTH },
63072  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
63073  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_71_WIDTH },
63074  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
63075  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_72_WIDTH },
63076  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
63077  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_73_WIDTH },
63078  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
63079  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_74_WIDTH },
63080  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
63081  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_75_WIDTH },
63082  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
63083  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_76_WIDTH },
63084  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
63085  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_77_WIDTH },
63086  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
63087  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_78_WIDTH },
63088  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
63089  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_79_WIDTH },
63090  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
63091  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_80_WIDTH },
63092  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
63093  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_81_WIDTH },
63094  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
63095  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_82_WIDTH },
63096  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
63097  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_83_WIDTH },
63098  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
63099  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_84_WIDTH },
63100  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
63101  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_85_WIDTH },
63102  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
63103  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_86_WIDTH },
63104  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
63105  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_87_WIDTH },
63106  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
63107  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_88_WIDTH },
63108  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
63109  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_89_WIDTH },
63110  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
63111  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_90_WIDTH },
63112  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
63113  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_91_WIDTH },
63114  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
63115  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_92_WIDTH },
63116  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
63117  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_93_WIDTH },
63118  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
63119  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_94_WIDTH },
63120  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
63121  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_95_WIDTH },
63122  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
63123  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_96_WIDTH },
63124  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
63125  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_97_WIDTH },
63126  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
63127  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_98_WIDTH },
63128  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
63129  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_99_WIDTH },
63130  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
63131  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_100_WIDTH },
63132  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
63133  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_101_WIDTH },
63134  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
63135  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_102_WIDTH },
63136  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
63137  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_103_WIDTH },
63138  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
63139  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_104_WIDTH },
63140  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
63141  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_105_WIDTH },
63142  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
63143  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_106_WIDTH },
63144  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
63145  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_107_WIDTH },
63146  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
63147  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_108_WIDTH },
63148  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
63149  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_109_WIDTH },
63150  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
63151  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_110_WIDTH },
63152  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
63153  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_111_WIDTH },
63154  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
63155  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_112_WIDTH },
63156  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
63157  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_113_WIDTH },
63158  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
63159  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_114_WIDTH },
63160  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
63161  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_115_WIDTH },
63162  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
63163  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_116_WIDTH },
63164  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
63165  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_117_WIDTH },
63166  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
63167  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_118_WIDTH },
63168  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
63169  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_119_WIDTH },
63170  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
63171  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_120_WIDTH },
63172  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
63173  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_121_WIDTH },
63174  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
63175  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_122_WIDTH },
63176  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
63177  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_123_WIDTH },
63178  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
63179  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_124_WIDTH },
63180  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
63181  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_125_WIDTH },
63182  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
63183  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_126_WIDTH },
63184  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
63185  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_127_WIDTH },
63186  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
63187  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_128_WIDTH },
63188  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
63189  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_129_WIDTH },
63190  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
63191  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_130_WIDTH },
63192  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
63193  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_131_WIDTH },
63194  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
63195  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_132_WIDTH },
63196  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
63197  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_133_WIDTH },
63198  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
63199  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_134_WIDTH },
63200  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
63201  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_135_WIDTH },
63202  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
63203  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_136_WIDTH },
63204  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
63205  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_137_WIDTH },
63206  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
63207  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_138_WIDTH },
63208  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
63209  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_139_WIDTH },
63210  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
63211  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_140_WIDTH },
63212  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
63213  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_141_WIDTH },
63214  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
63215  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_142_WIDTH },
63216  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
63217  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_143_WIDTH },
63218  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
63219  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_144_WIDTH },
63220  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
63221  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_145_WIDTH },
63222  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
63223  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_146_WIDTH },
63224  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
63225  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_147_WIDTH },
63226  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
63227  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_148_WIDTH },
63228  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
63229  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_149_WIDTH },
63230  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
63231  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_150_WIDTH },
63232  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
63233  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_151_WIDTH },
63234  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
63235  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_152_WIDTH },
63236  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
63237  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_153_WIDTH },
63238  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
63239  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_154_WIDTH },
63240  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
63241  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_155_WIDTH },
63242  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
63243  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_156_WIDTH },
63244  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
63245  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_157_WIDTH },
63246  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
63247  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_158_WIDTH },
63248  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
63249  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_159_WIDTH },
63250  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
63251  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_160_WIDTH },
63252  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
63253  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_161_WIDTH },
63254  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
63255  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_162_WIDTH },
63256  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
63257  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_163_WIDTH },
63258  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
63259  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_164_WIDTH },
63260  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
63261  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_165_WIDTH },
63262  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
63263  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_166_WIDTH },
63264  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
63265  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_167_WIDTH },
63266  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
63267  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_168_WIDTH },
63268  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
63269  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_169_WIDTH },
63270  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
63271  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_170_WIDTH },
63272  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
63273  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_171_WIDTH },
63274  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
63275  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_172_WIDTH },
63276  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
63277  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_173_WIDTH },
63278  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
63279  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_174_WIDTH },
63280  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
63281  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_175_WIDTH },
63282  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
63283  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_176_WIDTH },
63284  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
63285  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_177_WIDTH },
63286  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
63287  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_178_WIDTH },
63288  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
63289  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_179_WIDTH },
63290  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
63291  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_180_WIDTH },
63292  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
63293  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_181_WIDTH },
63294  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
63295  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_182_WIDTH },
63296  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
63297  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_183_WIDTH },
63298  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
63299  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_184_WIDTH },
63300  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
63301  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_185_WIDTH },
63302  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
63303  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_186_WIDTH },
63304  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
63305  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_187_WIDTH },
63306  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
63307  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_188_WIDTH },
63308  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
63309  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_189_WIDTH },
63310  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
63311  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_190_WIDTH },
63312  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
63313  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_191_WIDTH },
63314  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
63315  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_192_WIDTH },
63316  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
63317  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_193_WIDTH },
63318  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
63319  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_194_WIDTH },
63320  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
63321  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_195_WIDTH },
63322  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
63323  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_196_WIDTH },
63324  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
63325  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_197_WIDTH },
63326  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
63327  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_198_WIDTH },
63328  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
63329  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_199_WIDTH },
63330  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
63331  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_200_WIDTH },
63332  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
63333  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_201_WIDTH },
63334  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
63335  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_202_WIDTH },
63336  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
63337  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_203_WIDTH },
63338  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
63339  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_204_WIDTH },
63340  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
63341  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_205_WIDTH },
63342  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
63343  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_206_WIDTH },
63344  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
63345  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_207_WIDTH },
63346  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
63347  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_208_WIDTH },
63348  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
63349  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_209_WIDTH },
63350  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
63351  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_210_WIDTH },
63352  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
63353  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_211_WIDTH },
63354  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
63355  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_212_WIDTH },
63356  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
63357  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_213_WIDTH },
63358  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
63359  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_214_WIDTH },
63360  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
63361  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_215_WIDTH },
63362  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
63363  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_216_WIDTH },
63364  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
63365  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_217_WIDTH },
63366  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
63367  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_218_WIDTH },
63368  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
63369  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_219_WIDTH },
63370  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
63371  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_220_WIDTH },
63372  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
63373  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_221_WIDTH },
63374  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
63375  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_222_WIDTH },
63376  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
63377  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_223_WIDTH },
63378  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
63379  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_224_WIDTH },
63380  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
63381  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_225_WIDTH },
63382  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
63383  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_226_WIDTH },
63384  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
63385  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_227_WIDTH },
63386  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
63387  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_228_WIDTH },
63388  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
63389  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_229_WIDTH },
63390  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
63391  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_230_WIDTH },
63392  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
63393  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_231_WIDTH },
63394  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
63395  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_232_WIDTH },
63396  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
63397  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_233_WIDTH },
63398  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
63399  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_234_WIDTH },
63400  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
63401  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_235_WIDTH },
63402  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
63403  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_236_WIDTH },
63404  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
63405  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_237_WIDTH },
63406  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
63407  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_238_WIDTH },
63408  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
63409  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_239_WIDTH },
63410  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
63411  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_240_WIDTH },
63412  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
63413  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_241_WIDTH },
63414  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
63415  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_242_WIDTH },
63416  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
63417  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_243_WIDTH },
63418  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
63419  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_244_WIDTH },
63420  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
63421  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_245_WIDTH },
63422  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
63423  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_246_WIDTH },
63424  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
63425  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_247_WIDTH },
63426  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
63427  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_248_WIDTH },
63428  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
63429  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_249_WIDTH },
63430  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
63431  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_250_WIDTH },
63432  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
63433  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_251_WIDTH },
63434  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
63435  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_252_WIDTH },
63436  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
63437  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_253_WIDTH },
63438  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
63439  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_254_WIDTH },
63440  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
63441  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_GROUP_255_WIDTH },
63442 };
63443 
63449 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS] =
63450 {
63451  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
63452  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_0_WIDTH },
63453  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
63454  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_1_WIDTH },
63455  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
63456  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_2_WIDTH },
63457  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
63458  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_3_WIDTH },
63459  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
63460  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_4_WIDTH },
63461  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
63462  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_5_WIDTH },
63463  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
63464  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_6_WIDTH },
63465  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
63466  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_7_WIDTH },
63467  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
63468  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_8_WIDTH },
63469  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
63470  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_9_WIDTH },
63471  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
63472  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_10_WIDTH },
63473  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
63474  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_11_WIDTH },
63475  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
63476  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_12_WIDTH },
63477  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
63478  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_13_WIDTH },
63479  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
63480  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_14_WIDTH },
63481  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
63482  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_15_WIDTH },
63483  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
63484  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_16_WIDTH },
63485  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
63486  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_17_WIDTH },
63487  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
63488  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_18_WIDTH },
63489  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
63490  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_19_WIDTH },
63491  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
63492  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_20_WIDTH },
63493  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
63494  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_21_WIDTH },
63495  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
63496  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_22_WIDTH },
63497  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
63498  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_23_WIDTH },
63499  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
63500  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_24_WIDTH },
63501  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
63502  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_25_WIDTH },
63503  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
63504  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_26_WIDTH },
63505  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
63506  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_27_WIDTH },
63507  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
63508  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_28_WIDTH },
63509  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
63510  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_29_WIDTH },
63511  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
63512  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_30_WIDTH },
63513  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
63514  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_31_WIDTH },
63515  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
63516  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_32_WIDTH },
63517  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
63518  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_33_WIDTH },
63519  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
63520  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_34_WIDTH },
63521  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
63522  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_35_WIDTH },
63523  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
63524  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_36_WIDTH },
63525  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
63526  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_37_WIDTH },
63527  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
63528  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_38_WIDTH },
63529  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
63530  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_39_WIDTH },
63531  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
63532  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_40_WIDTH },
63533  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
63534  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_41_WIDTH },
63535  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
63536  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_42_WIDTH },
63537  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
63538  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_43_WIDTH },
63539  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
63540  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_44_WIDTH },
63541  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
63542  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_45_WIDTH },
63543  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
63544  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_46_WIDTH },
63545  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
63546  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_47_WIDTH },
63547  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
63548  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_48_WIDTH },
63549  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
63550  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_49_WIDTH },
63551  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
63552  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_50_WIDTH },
63553  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
63554  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_51_WIDTH },
63555  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
63556  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_52_WIDTH },
63557  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
63558  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_53_WIDTH },
63559  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
63560  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_54_WIDTH },
63561  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
63562  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_55_WIDTH },
63563  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
63564  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_56_WIDTH },
63565  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
63566  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_57_WIDTH },
63567  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
63568  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_58_WIDTH },
63569  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
63570  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_59_WIDTH },
63571  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
63572  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_60_WIDTH },
63573  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
63574  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_61_WIDTH },
63575  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
63576  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_62_WIDTH },
63577  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
63578  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_63_WIDTH },
63579  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
63580  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_64_WIDTH },
63581  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
63582  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_65_WIDTH },
63583  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
63584  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_66_WIDTH },
63585  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
63586  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_67_WIDTH },
63587  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
63588  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_68_WIDTH },
63589  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
63590  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_69_WIDTH },
63591  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
63592  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_70_WIDTH },
63593  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
63594  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_71_WIDTH },
63595  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
63596  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_72_WIDTH },
63597  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
63598  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_73_WIDTH },
63599  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
63600  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_74_WIDTH },
63601  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
63602  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_75_WIDTH },
63603  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
63604  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_76_WIDTH },
63605  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
63606  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_77_WIDTH },
63607  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
63608  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_78_WIDTH },
63609  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
63610  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_79_WIDTH },
63611  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
63612  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_80_WIDTH },
63613  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
63614  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_81_WIDTH },
63615  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
63616  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_82_WIDTH },
63617  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
63618  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_83_WIDTH },
63619  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
63620  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_84_WIDTH },
63621  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
63622  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_85_WIDTH },
63623  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
63624  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_86_WIDTH },
63625  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
63626  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_87_WIDTH },
63627  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
63628  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_88_WIDTH },
63629  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
63630  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_89_WIDTH },
63631  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
63632  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_90_WIDTH },
63633  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
63634  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_91_WIDTH },
63635  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
63636  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_92_WIDTH },
63637  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
63638  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_93_WIDTH },
63639  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
63640  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_94_WIDTH },
63641  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
63642  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_95_WIDTH },
63643  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
63644  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_96_WIDTH },
63645  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
63646  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_97_WIDTH },
63647  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
63648  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_98_WIDTH },
63649  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
63650  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_99_WIDTH },
63651  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
63652  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_100_WIDTH },
63653  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
63654  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_101_WIDTH },
63655  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
63656  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_102_WIDTH },
63657  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
63658  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_103_WIDTH },
63659  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
63660  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_104_WIDTH },
63661  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
63662  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_105_WIDTH },
63663  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
63664  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_106_WIDTH },
63665  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
63666  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_107_WIDTH },
63667  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
63668  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_108_WIDTH },
63669  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
63670  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_109_WIDTH },
63671  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
63672  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_110_WIDTH },
63673  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
63674  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_111_WIDTH },
63675  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
63676  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_112_WIDTH },
63677  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
63678  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_113_WIDTH },
63679  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
63680  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_114_WIDTH },
63681  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
63682  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_115_WIDTH },
63683  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
63684  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_116_WIDTH },
63685  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_117_CHECKER_TYPE,
63686  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_117_WIDTH },
63687  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_118_CHECKER_TYPE,
63688  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_118_WIDTH },
63689  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_119_CHECKER_TYPE,
63690  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_119_WIDTH },
63691  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_120_CHECKER_TYPE,
63692  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_120_WIDTH },
63693  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_121_CHECKER_TYPE,
63694  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_121_WIDTH },
63695  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_122_CHECKER_TYPE,
63696  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_122_WIDTH },
63697  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_123_CHECKER_TYPE,
63698  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_123_WIDTH },
63699  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_124_CHECKER_TYPE,
63700  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_124_WIDTH },
63701  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_125_CHECKER_TYPE,
63702  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_125_WIDTH },
63703  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_126_CHECKER_TYPE,
63704  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_126_WIDTH },
63705  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_127_CHECKER_TYPE,
63706  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_127_WIDTH },
63707  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_128_CHECKER_TYPE,
63708  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_128_WIDTH },
63709  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_129_CHECKER_TYPE,
63710  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_129_WIDTH },
63711  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_130_CHECKER_TYPE,
63712  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_130_WIDTH },
63713  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_131_CHECKER_TYPE,
63714  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_131_WIDTH },
63715  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_132_CHECKER_TYPE,
63716  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_132_WIDTH },
63717  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_133_CHECKER_TYPE,
63718  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_133_WIDTH },
63719  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_134_CHECKER_TYPE,
63720  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_134_WIDTH },
63721  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_135_CHECKER_TYPE,
63722  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_135_WIDTH },
63723  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_136_CHECKER_TYPE,
63724  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_136_WIDTH },
63725  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_137_CHECKER_TYPE,
63726  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_137_WIDTH },
63727  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_138_CHECKER_TYPE,
63728  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_138_WIDTH },
63729  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_139_CHECKER_TYPE,
63730  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_139_WIDTH },
63731  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_140_CHECKER_TYPE,
63732  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_140_WIDTH },
63733  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_141_CHECKER_TYPE,
63734  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_141_WIDTH },
63735  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_142_CHECKER_TYPE,
63736  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_142_WIDTH },
63737  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_143_CHECKER_TYPE,
63738  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_143_WIDTH },
63739  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_144_CHECKER_TYPE,
63740  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_144_WIDTH },
63741  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_145_CHECKER_TYPE,
63742  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_145_WIDTH },
63743  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_146_CHECKER_TYPE,
63744  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_146_WIDTH },
63745  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_147_CHECKER_TYPE,
63746  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_147_WIDTH },
63747  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_148_CHECKER_TYPE,
63748  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_148_WIDTH },
63749  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_149_CHECKER_TYPE,
63750  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_149_WIDTH },
63751  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_150_CHECKER_TYPE,
63752  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_150_WIDTH },
63753  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_151_CHECKER_TYPE,
63754  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_151_WIDTH },
63755  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_152_CHECKER_TYPE,
63756  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_152_WIDTH },
63757  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_153_CHECKER_TYPE,
63758  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_153_WIDTH },
63759  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_154_CHECKER_TYPE,
63760  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_154_WIDTH },
63761  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_155_CHECKER_TYPE,
63762  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_155_WIDTH },
63763  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_156_CHECKER_TYPE,
63764  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_156_WIDTH },
63765  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_157_CHECKER_TYPE,
63766  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_157_WIDTH },
63767  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_158_CHECKER_TYPE,
63768  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_158_WIDTH },
63769  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_159_CHECKER_TYPE,
63770  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_159_WIDTH },
63771  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_160_CHECKER_TYPE,
63772  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_160_WIDTH },
63773  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_161_CHECKER_TYPE,
63774  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_161_WIDTH },
63775  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_162_CHECKER_TYPE,
63776  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_162_WIDTH },
63777  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_163_CHECKER_TYPE,
63778  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_163_WIDTH },
63779  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_164_CHECKER_TYPE,
63780  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_164_WIDTH },
63781  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_165_CHECKER_TYPE,
63782  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_165_WIDTH },
63783  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_166_CHECKER_TYPE,
63784  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_166_WIDTH },
63785  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_167_CHECKER_TYPE,
63786  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_167_WIDTH },
63787  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_168_CHECKER_TYPE,
63788  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_168_WIDTH },
63789  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_169_CHECKER_TYPE,
63790  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_169_WIDTH },
63791  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_170_CHECKER_TYPE,
63792  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_170_WIDTH },
63793  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_171_CHECKER_TYPE,
63794  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_171_WIDTH },
63795  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_172_CHECKER_TYPE,
63796  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_172_WIDTH },
63797  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_173_CHECKER_TYPE,
63798  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_173_WIDTH },
63799  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_174_CHECKER_TYPE,
63800  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_174_WIDTH },
63801  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_175_CHECKER_TYPE,
63802  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_175_WIDTH },
63803  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_176_CHECKER_TYPE,
63804  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_176_WIDTH },
63805  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_177_CHECKER_TYPE,
63806  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_177_WIDTH },
63807  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_178_CHECKER_TYPE,
63808  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_178_WIDTH },
63809  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_179_CHECKER_TYPE,
63810  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_179_WIDTH },
63811  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_180_CHECKER_TYPE,
63812  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_180_WIDTH },
63813  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_181_CHECKER_TYPE,
63814  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_181_WIDTH },
63815  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_182_CHECKER_TYPE,
63816  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_182_WIDTH },
63817  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_183_CHECKER_TYPE,
63818  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_183_WIDTH },
63819  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_184_CHECKER_TYPE,
63820  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_184_WIDTH },
63821  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_185_CHECKER_TYPE,
63822  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_185_WIDTH },
63823  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_186_CHECKER_TYPE,
63824  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_186_WIDTH },
63825  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_187_CHECKER_TYPE,
63826  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_187_WIDTH },
63827  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_188_CHECKER_TYPE,
63828  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_188_WIDTH },
63829  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_189_CHECKER_TYPE,
63830  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_189_WIDTH },
63831  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_190_CHECKER_TYPE,
63832  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_190_WIDTH },
63833  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_191_CHECKER_TYPE,
63834  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_191_WIDTH },
63835  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_192_CHECKER_TYPE,
63836  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_192_WIDTH },
63837  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_193_CHECKER_TYPE,
63838  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_193_WIDTH },
63839  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_194_CHECKER_TYPE,
63840  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_194_WIDTH },
63841  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_195_CHECKER_TYPE,
63842  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_195_WIDTH },
63843  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_196_CHECKER_TYPE,
63844  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_196_WIDTH },
63845  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_197_CHECKER_TYPE,
63846  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_197_WIDTH },
63847  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_198_CHECKER_TYPE,
63848  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_198_WIDTH },
63849  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_199_CHECKER_TYPE,
63850  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_199_WIDTH },
63851  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_200_CHECKER_TYPE,
63852  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_200_WIDTH },
63853  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_201_CHECKER_TYPE,
63854  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_201_WIDTH },
63855  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_202_CHECKER_TYPE,
63856  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_202_WIDTH },
63857  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_203_CHECKER_TYPE,
63858  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_203_WIDTH },
63859  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_204_CHECKER_TYPE,
63860  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_204_WIDTH },
63861  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_205_CHECKER_TYPE,
63862  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_205_WIDTH },
63863  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_206_CHECKER_TYPE,
63864  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_206_WIDTH },
63865  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_207_CHECKER_TYPE,
63866  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_207_WIDTH },
63867  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_208_CHECKER_TYPE,
63868  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_208_WIDTH },
63869  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_209_CHECKER_TYPE,
63870  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_209_WIDTH },
63871  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_210_CHECKER_TYPE,
63872  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_210_WIDTH },
63873  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_211_CHECKER_TYPE,
63874  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_211_WIDTH },
63875  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_212_CHECKER_TYPE,
63876  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_212_WIDTH },
63877  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_213_CHECKER_TYPE,
63878  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_213_WIDTH },
63879  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_214_CHECKER_TYPE,
63880  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_214_WIDTH },
63881  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_215_CHECKER_TYPE,
63882  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_215_WIDTH },
63883  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_216_CHECKER_TYPE,
63884  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_216_WIDTH },
63885  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_217_CHECKER_TYPE,
63886  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_217_WIDTH },
63887  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_218_CHECKER_TYPE,
63888  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_218_WIDTH },
63889  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_219_CHECKER_TYPE,
63890  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_219_WIDTH },
63891  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_220_CHECKER_TYPE,
63892  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_220_WIDTH },
63893  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_221_CHECKER_TYPE,
63894  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_221_WIDTH },
63895  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_222_CHECKER_TYPE,
63896  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_222_WIDTH },
63897  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_223_CHECKER_TYPE,
63898  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_223_WIDTH },
63899  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_224_CHECKER_TYPE,
63900  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_224_WIDTH },
63901  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_225_CHECKER_TYPE,
63902  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_225_WIDTH },
63903  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_226_CHECKER_TYPE,
63904  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_226_WIDTH },
63905  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_227_CHECKER_TYPE,
63906  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_227_WIDTH },
63907  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_228_CHECKER_TYPE,
63908  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_228_WIDTH },
63909  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_229_CHECKER_TYPE,
63910  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_229_WIDTH },
63911  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_230_CHECKER_TYPE,
63912  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_230_WIDTH },
63913  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_231_CHECKER_TYPE,
63914  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_231_WIDTH },
63915  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_232_CHECKER_TYPE,
63916  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_232_WIDTH },
63917  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_233_CHECKER_TYPE,
63918  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_233_WIDTH },
63919  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_234_CHECKER_TYPE,
63920  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_234_WIDTH },
63921  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_235_CHECKER_TYPE,
63922  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_235_WIDTH },
63923  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_236_CHECKER_TYPE,
63924  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_236_WIDTH },
63925  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_237_CHECKER_TYPE,
63926  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_237_WIDTH },
63927  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_238_CHECKER_TYPE,
63928  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_238_WIDTH },
63929  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_239_CHECKER_TYPE,
63930  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_239_WIDTH },
63931  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_240_CHECKER_TYPE,
63932  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_240_WIDTH },
63933  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_241_CHECKER_TYPE,
63934  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_241_WIDTH },
63935  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_242_CHECKER_TYPE,
63936  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_242_WIDTH },
63937  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_243_CHECKER_TYPE,
63938  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_243_WIDTH },
63939  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_244_CHECKER_TYPE,
63940  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_244_WIDTH },
63941  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_245_CHECKER_TYPE,
63942  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_245_WIDTH },
63943  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_246_CHECKER_TYPE,
63944  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_246_WIDTH },
63945  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_247_CHECKER_TYPE,
63946  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_247_WIDTH },
63947  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_248_CHECKER_TYPE,
63948  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_248_WIDTH },
63949  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_249_CHECKER_TYPE,
63950  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_249_WIDTH },
63951  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_250_CHECKER_TYPE,
63952  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_250_WIDTH },
63953  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_251_CHECKER_TYPE,
63954  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_251_WIDTH },
63955  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_252_CHECKER_TYPE,
63956  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_252_WIDTH },
63957  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_253_CHECKER_TYPE,
63958  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_253_WIDTH },
63959  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_254_CHECKER_TYPE,
63960  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_254_WIDTH },
63961  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_255_CHECKER_TYPE,
63962  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_GROUP_255_WIDTH },
63963 };
63964 
63970 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS] =
63971 {
63972  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_0_CHECKER_TYPE,
63973  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_0_WIDTH },
63974  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_1_CHECKER_TYPE,
63975  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_1_WIDTH },
63976  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_2_CHECKER_TYPE,
63977  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_2_WIDTH },
63978  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_3_CHECKER_TYPE,
63979  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_3_WIDTH },
63980  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_4_CHECKER_TYPE,
63981  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_4_WIDTH },
63982  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_5_CHECKER_TYPE,
63983  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_5_WIDTH },
63984  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_6_CHECKER_TYPE,
63985  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_6_WIDTH },
63986  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_7_CHECKER_TYPE,
63987  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_7_WIDTH },
63988  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_8_CHECKER_TYPE,
63989  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_8_WIDTH },
63990  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_9_CHECKER_TYPE,
63991  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_9_WIDTH },
63992  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_10_CHECKER_TYPE,
63993  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_10_WIDTH },
63994  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_11_CHECKER_TYPE,
63995  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_11_WIDTH },
63996  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_12_CHECKER_TYPE,
63997  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_12_WIDTH },
63998  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_13_CHECKER_TYPE,
63999  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_13_WIDTH },
64000  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_14_CHECKER_TYPE,
64001  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_14_WIDTH },
64002  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_15_CHECKER_TYPE,
64003  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_15_WIDTH },
64004  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_16_CHECKER_TYPE,
64005  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_16_WIDTH },
64006  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_17_CHECKER_TYPE,
64007  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_17_WIDTH },
64008  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_18_CHECKER_TYPE,
64009  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_18_WIDTH },
64010  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_19_CHECKER_TYPE,
64011  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_19_WIDTH },
64012  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_20_CHECKER_TYPE,
64013  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_20_WIDTH },
64014  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_21_CHECKER_TYPE,
64015  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_21_WIDTH },
64016  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_22_CHECKER_TYPE,
64017  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_22_WIDTH },
64018  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_23_CHECKER_TYPE,
64019  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_23_WIDTH },
64020  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_24_CHECKER_TYPE,
64021  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_24_WIDTH },
64022  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_25_CHECKER_TYPE,
64023  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_25_WIDTH },
64024  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_26_CHECKER_TYPE,
64025  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_26_WIDTH },
64026  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_27_CHECKER_TYPE,
64027  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_27_WIDTH },
64028  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_28_CHECKER_TYPE,
64029  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_28_WIDTH },
64030  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_29_CHECKER_TYPE,
64031  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_29_WIDTH },
64032  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_30_CHECKER_TYPE,
64033  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_30_WIDTH },
64034  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_31_CHECKER_TYPE,
64035  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_31_WIDTH },
64036  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_32_CHECKER_TYPE,
64037  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_32_WIDTH },
64038  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_33_CHECKER_TYPE,
64039  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_33_WIDTH },
64040  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_34_CHECKER_TYPE,
64041  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_34_WIDTH },
64042  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_35_CHECKER_TYPE,
64043  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_35_WIDTH },
64044  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_36_CHECKER_TYPE,
64045  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_36_WIDTH },
64046  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_37_CHECKER_TYPE,
64047  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_37_WIDTH },
64048  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_38_CHECKER_TYPE,
64049  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_38_WIDTH },
64050  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_39_CHECKER_TYPE,
64051  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_39_WIDTH },
64052  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_40_CHECKER_TYPE,
64053  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_40_WIDTH },
64054  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_41_CHECKER_TYPE,
64055  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_41_WIDTH },
64056  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_42_CHECKER_TYPE,
64057  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_42_WIDTH },
64058  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_43_CHECKER_TYPE,
64059  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_43_WIDTH },
64060  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_44_CHECKER_TYPE,
64061  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_44_WIDTH },
64062  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_45_CHECKER_TYPE,
64063  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_45_WIDTH },
64064  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_46_CHECKER_TYPE,
64065  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_46_WIDTH },
64066  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_47_CHECKER_TYPE,
64067  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_47_WIDTH },
64068  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_48_CHECKER_TYPE,
64069  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_48_WIDTH },
64070  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_49_CHECKER_TYPE,
64071  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_49_WIDTH },
64072  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_50_CHECKER_TYPE,
64073  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_50_WIDTH },
64074  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_51_CHECKER_TYPE,
64075  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_51_WIDTH },
64076  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_52_CHECKER_TYPE,
64077  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_52_WIDTH },
64078  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_53_CHECKER_TYPE,
64079  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_53_WIDTH },
64080  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_54_CHECKER_TYPE,
64081  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_54_WIDTH },
64082  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_55_CHECKER_TYPE,
64083  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_55_WIDTH },
64084  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_56_CHECKER_TYPE,
64085  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_56_WIDTH },
64086  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_57_CHECKER_TYPE,
64087  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_57_WIDTH },
64088  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_58_CHECKER_TYPE,
64089  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_58_WIDTH },
64090  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_59_CHECKER_TYPE,
64091  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_59_WIDTH },
64092  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_60_CHECKER_TYPE,
64093  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_60_WIDTH },
64094  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_61_CHECKER_TYPE,
64095  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_61_WIDTH },
64096  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_62_CHECKER_TYPE,
64097  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_62_WIDTH },
64098  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_63_CHECKER_TYPE,
64099  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_63_WIDTH },
64100  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_64_CHECKER_TYPE,
64101  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_64_WIDTH },
64102  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_65_CHECKER_TYPE,
64103  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_65_WIDTH },
64104  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_66_CHECKER_TYPE,
64105  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_66_WIDTH },
64106  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_67_CHECKER_TYPE,
64107  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_67_WIDTH },
64108  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_68_CHECKER_TYPE,
64109  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_GROUP_68_WIDTH },
64110 };
64111 
64117 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
64118 {
64119  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
64120  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_0_WIDTH },
64121  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
64122  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_1_WIDTH },
64123  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
64124  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_2_WIDTH },
64125  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
64126  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_3_WIDTH },
64127  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
64128  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_4_WIDTH },
64129  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
64130  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_5_WIDTH },
64131  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
64132  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_6_WIDTH },
64133  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
64134  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_7_WIDTH },
64135  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
64136  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_8_WIDTH },
64137  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
64138  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_9_WIDTH },
64139  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
64140  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_10_WIDTH },
64141  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
64142  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_11_WIDTH },
64143  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
64144  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_12_WIDTH },
64145  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
64146  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_13_WIDTH },
64147  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
64148  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_14_WIDTH },
64149  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
64150  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_15_WIDTH },
64151  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
64152  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_16_WIDTH },
64153  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
64154  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_17_WIDTH },
64155  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
64156  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_18_WIDTH },
64157  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
64158  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_19_WIDTH },
64159  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
64160  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_20_WIDTH },
64161  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
64162  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_21_WIDTH },
64163  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
64164  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_22_WIDTH },
64165  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
64166  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_23_WIDTH },
64167  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
64168  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_24_WIDTH },
64169  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
64170  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_25_WIDTH },
64171  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
64172  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_26_WIDTH },
64173  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
64174  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_27_WIDTH },
64175  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
64176  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_28_WIDTH },
64177  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
64178  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_29_WIDTH },
64179  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
64180  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_30_WIDTH },
64181  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
64182  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_31_WIDTH },
64183  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
64184  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_32_WIDTH },
64185  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
64186  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_33_WIDTH },
64187  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
64188  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_34_WIDTH },
64189  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
64190  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_35_WIDTH },
64191  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
64192  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_36_WIDTH },
64193  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
64194  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_37_WIDTH },
64195  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
64196  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_38_WIDTH },
64197  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
64198  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_39_WIDTH },
64199  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
64200  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_40_WIDTH },
64201  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
64202  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_41_WIDTH },
64203  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
64204  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_42_WIDTH },
64205  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
64206  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_43_WIDTH },
64207  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
64208  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_44_WIDTH },
64209  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
64210  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_45_WIDTH },
64211  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
64212  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_46_WIDTH },
64213  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
64214  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_47_WIDTH },
64215  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
64216  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_48_WIDTH },
64217  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
64218  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_49_WIDTH },
64219  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
64220  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_50_WIDTH },
64221  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
64222  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_51_WIDTH },
64223  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
64224  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_52_WIDTH },
64225  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
64226  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_53_WIDTH },
64227  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
64228  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_54_WIDTH },
64229  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
64230  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_55_WIDTH },
64231  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
64232  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_56_WIDTH },
64233  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
64234  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_57_WIDTH },
64235  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
64236  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_58_WIDTH },
64237  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
64238  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_59_WIDTH },
64239  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
64240  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_60_WIDTH },
64241  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
64242  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_61_WIDTH },
64243  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
64244  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_62_WIDTH },
64245  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
64246  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_63_WIDTH },
64247  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
64248  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_64_WIDTH },
64249  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
64250  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_65_WIDTH },
64251  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
64252  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_66_WIDTH },
64253  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
64254  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_67_WIDTH },
64255  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
64256  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_68_WIDTH },
64257  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
64258  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_69_WIDTH },
64259  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
64260  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_70_WIDTH },
64261  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
64262  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_71_WIDTH },
64263  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
64264  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_72_WIDTH },
64265  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
64266  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_73_WIDTH },
64267  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
64268  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_74_WIDTH },
64269  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
64270  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_75_WIDTH },
64271  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
64272  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_76_WIDTH },
64273  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
64274  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_77_WIDTH },
64275  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
64276  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_78_WIDTH },
64277  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
64278  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_79_WIDTH },
64279  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
64280  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_80_WIDTH },
64281  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
64282  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_81_WIDTH },
64283  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
64284  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_82_WIDTH },
64285  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
64286  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_83_WIDTH },
64287  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
64288  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_84_WIDTH },
64289  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
64290  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_85_WIDTH },
64291  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
64292  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_86_WIDTH },
64293  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
64294  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_87_WIDTH },
64295  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
64296  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_88_WIDTH },
64297  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
64298  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_89_WIDTH },
64299  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
64300  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_90_WIDTH },
64301  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
64302  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_91_WIDTH },
64303  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
64304  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_92_WIDTH },
64305  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
64306  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_93_WIDTH },
64307  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
64308  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_94_WIDTH },
64309  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
64310  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_95_WIDTH },
64311  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
64312  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_96_WIDTH },
64313  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
64314  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_97_WIDTH },
64315  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
64316  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_98_WIDTH },
64317  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
64318  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_99_WIDTH },
64319  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
64320  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_100_WIDTH },
64321  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
64322  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_101_WIDTH },
64323  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
64324  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_102_WIDTH },
64325  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
64326  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_103_WIDTH },
64327  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
64328  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_104_WIDTH },
64329  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
64330  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_105_WIDTH },
64331  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
64332  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_106_WIDTH },
64333  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
64334  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_107_WIDTH },
64335  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
64336  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_108_WIDTH },
64337  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
64338  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_109_WIDTH },
64339  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
64340  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_110_WIDTH },
64341  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
64342  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_111_WIDTH },
64343  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
64344  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_112_WIDTH },
64345  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
64346  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_113_WIDTH },
64347  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
64348  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_114_WIDTH },
64349  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
64350  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_115_WIDTH },
64351  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
64352  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_116_WIDTH },
64353  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
64354  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_117_WIDTH },
64355  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
64356  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_118_WIDTH },
64357  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
64358  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_119_WIDTH },
64359  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
64360  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_120_WIDTH },
64361  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
64362  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_121_WIDTH },
64363  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
64364  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_122_WIDTH },
64365  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
64366  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_123_WIDTH },
64367  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
64368  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_124_WIDTH },
64369  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
64370  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_125_WIDTH },
64371  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
64372  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_126_WIDTH },
64373  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
64374  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_127_WIDTH },
64375  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
64376  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_128_WIDTH },
64377  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
64378  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_129_WIDTH },
64379  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
64380  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_130_WIDTH },
64381  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
64382  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_131_WIDTH },
64383  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
64384  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_132_WIDTH },
64385  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
64386  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_133_WIDTH },
64387  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
64388  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_134_WIDTH },
64389  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
64390  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_135_WIDTH },
64391  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
64392  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_136_WIDTH },
64393  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
64394  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_137_WIDTH },
64395  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
64396  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_138_WIDTH },
64397  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
64398  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_139_WIDTH },
64399  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
64400  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_140_WIDTH },
64401  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
64402  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_141_WIDTH },
64403  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
64404  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_142_WIDTH },
64405  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
64406  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_143_WIDTH },
64407  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
64408  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_144_WIDTH },
64409  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
64410  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_145_WIDTH },
64411  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
64412  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_146_WIDTH },
64413  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
64414  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_147_WIDTH },
64415  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
64416  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_148_WIDTH },
64417  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
64418  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_149_WIDTH },
64419  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
64420  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_150_WIDTH },
64421  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
64422  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_151_WIDTH },
64423  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
64424  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_152_WIDTH },
64425  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
64426  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_153_WIDTH },
64427  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
64428  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_154_WIDTH },
64429  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
64430  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_155_WIDTH },
64431  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
64432  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_156_WIDTH },
64433  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
64434  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_157_WIDTH },
64435  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
64436  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_158_WIDTH },
64437  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
64438  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_159_WIDTH },
64439  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
64440  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_160_WIDTH },
64441  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
64442  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_161_WIDTH },
64443  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
64444  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_162_WIDTH },
64445  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
64446  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_163_WIDTH },
64447  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
64448  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_164_WIDTH },
64449  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
64450  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_165_WIDTH },
64451  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
64452  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_166_WIDTH },
64453  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
64454  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_167_WIDTH },
64455  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
64456  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_168_WIDTH },
64457  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
64458  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_169_WIDTH },
64459  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
64460  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_170_WIDTH },
64461  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
64462  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_171_WIDTH },
64463  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
64464  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_172_WIDTH },
64465  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
64466  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_173_WIDTH },
64467  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
64468  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_174_WIDTH },
64469  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
64470  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_175_WIDTH },
64471  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
64472  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_176_WIDTH },
64473  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
64474  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_177_WIDTH },
64475  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
64476  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_178_WIDTH },
64477  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
64478  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_179_WIDTH },
64479  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
64480  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_180_WIDTH },
64481  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
64482  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_181_WIDTH },
64483  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
64484  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_182_WIDTH },
64485  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
64486  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_183_WIDTH },
64487  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
64488  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_184_WIDTH },
64489  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
64490  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_185_WIDTH },
64491  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
64492  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_186_WIDTH },
64493  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
64494  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_187_WIDTH },
64495  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
64496  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_188_WIDTH },
64497  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
64498  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_189_WIDTH },
64499  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
64500  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_190_WIDTH },
64501  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
64502  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_191_WIDTH },
64503  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
64504  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_192_WIDTH },
64505  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
64506  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_193_WIDTH },
64507  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
64508  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_194_WIDTH },
64509  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
64510  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_195_WIDTH },
64511  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
64512  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_196_WIDTH },
64513  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
64514  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_197_WIDTH },
64515  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
64516  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_198_WIDTH },
64517  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
64518  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_199_WIDTH },
64519  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
64520  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_200_WIDTH },
64521  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
64522  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_201_WIDTH },
64523  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
64524  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_202_WIDTH },
64525  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
64526  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_203_WIDTH },
64527  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
64528  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_204_WIDTH },
64529  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
64530  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_205_WIDTH },
64531  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
64532  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_206_WIDTH },
64533  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
64534  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_207_WIDTH },
64535  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
64536  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_208_WIDTH },
64537  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
64538  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_209_WIDTH },
64539  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
64540  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_210_WIDTH },
64541  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
64542  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_211_WIDTH },
64543  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
64544  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_212_WIDTH },
64545  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
64546  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_213_WIDTH },
64547  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
64548  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_214_WIDTH },
64549  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
64550  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_215_WIDTH },
64551  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
64552  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_216_WIDTH },
64553  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
64554  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_217_WIDTH },
64555  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
64556  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_218_WIDTH },
64557  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
64558  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_219_WIDTH },
64559  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
64560  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_220_WIDTH },
64561  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
64562  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_221_WIDTH },
64563  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
64564  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_222_WIDTH },
64565  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
64566  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_223_WIDTH },
64567  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
64568  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_224_WIDTH },
64569  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
64570  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_225_WIDTH },
64571  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
64572  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_226_WIDTH },
64573  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
64574  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_227_WIDTH },
64575  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
64576  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_228_WIDTH },
64577  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
64578  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_229_WIDTH },
64579  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
64580  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_230_WIDTH },
64581  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
64582  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_231_WIDTH },
64583  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
64584  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_232_WIDTH },
64585  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
64586  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_233_WIDTH },
64587  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
64588  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_234_WIDTH },
64589  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
64590  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_235_WIDTH },
64591  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
64592  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_236_WIDTH },
64593  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
64594  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_237_WIDTH },
64595  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
64596  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_238_WIDTH },
64597  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
64598  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_239_WIDTH },
64599  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
64600  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_240_WIDTH },
64601  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
64602  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_241_WIDTH },
64603  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
64604  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_242_WIDTH },
64605  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
64606  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_243_WIDTH },
64607  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
64608  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_244_WIDTH },
64609  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
64610  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_245_WIDTH },
64611  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
64612  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_246_WIDTH },
64613  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
64614  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_247_WIDTH },
64615  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
64616  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_248_WIDTH },
64617  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
64618  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_249_WIDTH },
64619  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
64620  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_250_WIDTH },
64621  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
64622  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_251_WIDTH },
64623  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
64624  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_252_WIDTH },
64625  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
64626  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_253_WIDTH },
64627  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
64628  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_254_WIDTH },
64629  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
64630  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_GROUP_255_WIDTH },
64631 };
64632 
64638 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS] =
64639 {
64640  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
64641  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_0_WIDTH },
64642  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
64643  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_1_WIDTH },
64644  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
64645  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_2_WIDTH },
64646  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
64647  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_3_WIDTH },
64648  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
64649  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_4_WIDTH },
64650  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
64651  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_5_WIDTH },
64652  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
64653  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_6_WIDTH },
64654  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
64655  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_7_WIDTH },
64656  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
64657  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_8_WIDTH },
64658  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
64659  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_9_WIDTH },
64660  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
64661  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_10_WIDTH },
64662  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
64663  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_11_WIDTH },
64664  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
64665  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_12_WIDTH },
64666  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
64667  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_13_WIDTH },
64668  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
64669  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_14_WIDTH },
64670  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
64671  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_15_WIDTH },
64672  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
64673  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_16_WIDTH },
64674  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
64675  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_17_WIDTH },
64676  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
64677  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_18_WIDTH },
64678  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
64679  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_19_WIDTH },
64680  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
64681  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_20_WIDTH },
64682  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
64683  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_21_WIDTH },
64684  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
64685  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_22_WIDTH },
64686  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
64687  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_23_WIDTH },
64688  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
64689  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_24_WIDTH },
64690  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
64691  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_25_WIDTH },
64692  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
64693  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_26_WIDTH },
64694  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
64695  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_27_WIDTH },
64696  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
64697  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_28_WIDTH },
64698  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
64699  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_29_WIDTH },
64700  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
64701  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_30_WIDTH },
64702  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
64703  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_31_WIDTH },
64704  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
64705  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_32_WIDTH },
64706  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
64707  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_33_WIDTH },
64708  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
64709  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_34_WIDTH },
64710  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
64711  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_35_WIDTH },
64712  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
64713  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_36_WIDTH },
64714  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
64715  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_37_WIDTH },
64716  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
64717  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_38_WIDTH },
64718  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
64719  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_39_WIDTH },
64720  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
64721  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_40_WIDTH },
64722  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
64723  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_41_WIDTH },
64724  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
64725  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_42_WIDTH },
64726  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
64727  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_43_WIDTH },
64728  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
64729  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_44_WIDTH },
64730  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
64731  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_45_WIDTH },
64732  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
64733  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_46_WIDTH },
64734  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
64735  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_47_WIDTH },
64736  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
64737  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_48_WIDTH },
64738  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
64739  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_49_WIDTH },
64740  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
64741  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_50_WIDTH },
64742  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
64743  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_51_WIDTH },
64744  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
64745  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_52_WIDTH },
64746  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
64747  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_53_WIDTH },
64748  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
64749  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_54_WIDTH },
64750  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
64751  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_55_WIDTH },
64752  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
64753  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_56_WIDTH },
64754  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_57_CHECKER_TYPE,
64755  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_57_WIDTH },
64756  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_58_CHECKER_TYPE,
64757  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_58_WIDTH },
64758  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_59_CHECKER_TYPE,
64759  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_59_WIDTH },
64760  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_60_CHECKER_TYPE,
64761  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_60_WIDTH },
64762  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_61_CHECKER_TYPE,
64763  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_61_WIDTH },
64764  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_62_CHECKER_TYPE,
64765  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_62_WIDTH },
64766  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_63_CHECKER_TYPE,
64767  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_63_WIDTH },
64768  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_64_CHECKER_TYPE,
64769  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_64_WIDTH },
64770  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_65_CHECKER_TYPE,
64771  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_65_WIDTH },
64772  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_66_CHECKER_TYPE,
64773  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_66_WIDTH },
64774  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_67_CHECKER_TYPE,
64775  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_67_WIDTH },
64776  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_68_CHECKER_TYPE,
64777  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_68_WIDTH },
64778  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_69_CHECKER_TYPE,
64779  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_69_WIDTH },
64780  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_70_CHECKER_TYPE,
64781  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_70_WIDTH },
64782  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_71_CHECKER_TYPE,
64783  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_71_WIDTH },
64784  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_72_CHECKER_TYPE,
64785  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_72_WIDTH },
64786  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_73_CHECKER_TYPE,
64787  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_73_WIDTH },
64788  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_74_CHECKER_TYPE,
64789  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_74_WIDTH },
64790  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_75_CHECKER_TYPE,
64791  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_75_WIDTH },
64792  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_76_CHECKER_TYPE,
64793  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_76_WIDTH },
64794  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_77_CHECKER_TYPE,
64795  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_77_WIDTH },
64796  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_78_CHECKER_TYPE,
64797  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_78_WIDTH },
64798  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_79_CHECKER_TYPE,
64799  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_79_WIDTH },
64800  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_80_CHECKER_TYPE,
64801  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_80_WIDTH },
64802  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_81_CHECKER_TYPE,
64803  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_81_WIDTH },
64804  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_82_CHECKER_TYPE,
64805  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_82_WIDTH },
64806  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_83_CHECKER_TYPE,
64807  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_83_WIDTH },
64808  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_84_CHECKER_TYPE,
64809  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_84_WIDTH },
64810  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_85_CHECKER_TYPE,
64811  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_85_WIDTH },
64812  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_86_CHECKER_TYPE,
64813  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_86_WIDTH },
64814  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_87_CHECKER_TYPE,
64815  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_87_WIDTH },
64816  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_88_CHECKER_TYPE,
64817  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_88_WIDTH },
64818  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_89_CHECKER_TYPE,
64819  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_89_WIDTH },
64820  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_90_CHECKER_TYPE,
64821  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_90_WIDTH },
64822  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_91_CHECKER_TYPE,
64823  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_91_WIDTH },
64824  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_92_CHECKER_TYPE,
64825  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_92_WIDTH },
64826  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_93_CHECKER_TYPE,
64827  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_93_WIDTH },
64828  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_94_CHECKER_TYPE,
64829  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_94_WIDTH },
64830  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_95_CHECKER_TYPE,
64831  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_95_WIDTH },
64832  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_96_CHECKER_TYPE,
64833  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_96_WIDTH },
64834  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_97_CHECKER_TYPE,
64835  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_97_WIDTH },
64836  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_98_CHECKER_TYPE,
64837  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_98_WIDTH },
64838  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_99_CHECKER_TYPE,
64839  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_99_WIDTH },
64840  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_100_CHECKER_TYPE,
64841  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_100_WIDTH },
64842  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_101_CHECKER_TYPE,
64843  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_101_WIDTH },
64844  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_102_CHECKER_TYPE,
64845  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_102_WIDTH },
64846  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_103_CHECKER_TYPE,
64847  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_103_WIDTH },
64848  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_104_CHECKER_TYPE,
64849  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_104_WIDTH },
64850  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_105_CHECKER_TYPE,
64851  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_105_WIDTH },
64852  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_106_CHECKER_TYPE,
64853  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_106_WIDTH },
64854  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_107_CHECKER_TYPE,
64855  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_107_WIDTH },
64856  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_108_CHECKER_TYPE,
64857  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_108_WIDTH },
64858  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_109_CHECKER_TYPE,
64859  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_109_WIDTH },
64860  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_110_CHECKER_TYPE,
64861  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_110_WIDTH },
64862  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_111_CHECKER_TYPE,
64863  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_111_WIDTH },
64864  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_112_CHECKER_TYPE,
64865  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_112_WIDTH },
64866  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_113_CHECKER_TYPE,
64867  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_113_WIDTH },
64868  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_114_CHECKER_TYPE,
64869  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_114_WIDTH },
64870  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_115_CHECKER_TYPE,
64871  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_115_WIDTH },
64872  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_116_CHECKER_TYPE,
64873  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_GROUP_116_WIDTH },
64874 };
64875 
64881 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
64882 {
64883  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
64884  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_0_WIDTH },
64885  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
64886  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_1_WIDTH },
64887  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
64888  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_2_WIDTH },
64889  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
64890  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_3_WIDTH },
64891  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
64892  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_4_WIDTH },
64893  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
64894  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_5_WIDTH },
64895  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
64896  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_6_WIDTH },
64897  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
64898  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_7_WIDTH },
64899  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
64900  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_8_WIDTH },
64901  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
64902  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_9_WIDTH },
64903  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
64904  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_10_WIDTH },
64905  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
64906  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_11_WIDTH },
64907  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
64908  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_12_WIDTH },
64909  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
64910  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_13_WIDTH },
64911  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
64912  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_14_WIDTH },
64913  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
64914  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_15_WIDTH },
64915  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
64916  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_16_WIDTH },
64917  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
64918  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_17_WIDTH },
64919  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
64920  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_18_WIDTH },
64921  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
64922  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_19_WIDTH },
64923  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
64924  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_20_WIDTH },
64925  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
64926  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_21_WIDTH },
64927  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
64928  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_22_WIDTH },
64929  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
64930  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_23_WIDTH },
64931  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
64932  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_24_WIDTH },
64933  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
64934  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_25_WIDTH },
64935  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
64936  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_26_WIDTH },
64937  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
64938  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_27_WIDTH },
64939  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
64940  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_28_WIDTH },
64941  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
64942  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_29_WIDTH },
64943  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
64944  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_30_WIDTH },
64945  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
64946  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_31_WIDTH },
64947  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
64948  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_32_WIDTH },
64949  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
64950  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_33_WIDTH },
64951  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
64952  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_34_WIDTH },
64953  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
64954  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_35_WIDTH },
64955  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
64956  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_36_WIDTH },
64957  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
64958  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_37_WIDTH },
64959  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
64960  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_38_WIDTH },
64961  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
64962  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_39_WIDTH },
64963  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
64964  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_40_WIDTH },
64965  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
64966  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_41_WIDTH },
64967  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
64968  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_42_WIDTH },
64969  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
64970  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_43_WIDTH },
64971  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
64972  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_44_WIDTH },
64973  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
64974  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_45_WIDTH },
64975  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
64976  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_46_WIDTH },
64977  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
64978  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_47_WIDTH },
64979  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
64980  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_48_WIDTH },
64981  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
64982  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_49_WIDTH },
64983  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
64984  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_50_WIDTH },
64985  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
64986  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_51_WIDTH },
64987  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
64988  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_52_WIDTH },
64989  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
64990  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_53_WIDTH },
64991  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
64992  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_54_WIDTH },
64993  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
64994  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_55_WIDTH },
64995  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
64996  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_56_WIDTH },
64997  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
64998  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_57_WIDTH },
64999  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
65000  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_58_WIDTH },
65001  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
65002  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_59_WIDTH },
65003  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
65004  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_60_WIDTH },
65005  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
65006  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_GROUP_61_WIDTH },
65007 };
65008 
65014 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS] =
65015 {
65016  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_0_CHECKER_TYPE,
65017  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_0_WIDTH },
65018  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_1_CHECKER_TYPE,
65019  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_1_WIDTH },
65020  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_2_CHECKER_TYPE,
65021  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_2_WIDTH },
65022  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_3_CHECKER_TYPE,
65023  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_3_WIDTH },
65024  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_4_CHECKER_TYPE,
65025  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_4_WIDTH },
65026  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_5_CHECKER_TYPE,
65027  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_5_WIDTH },
65028  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_6_CHECKER_TYPE,
65029  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_6_WIDTH },
65030  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_7_CHECKER_TYPE,
65031  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_7_WIDTH },
65032  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_8_CHECKER_TYPE,
65033  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_8_WIDTH },
65034  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_9_CHECKER_TYPE,
65035  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_9_WIDTH },
65036  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_10_CHECKER_TYPE,
65037  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_10_WIDTH },
65038  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_11_CHECKER_TYPE,
65039  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_11_WIDTH },
65040  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_12_CHECKER_TYPE,
65041  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_12_WIDTH },
65042  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_13_CHECKER_TYPE,
65043  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_13_WIDTH },
65044  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_14_CHECKER_TYPE,
65045  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_14_WIDTH },
65046  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_15_CHECKER_TYPE,
65047  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_15_WIDTH },
65048  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_16_CHECKER_TYPE,
65049  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_16_WIDTH },
65050  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_17_CHECKER_TYPE,
65051  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_17_WIDTH },
65052  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_18_CHECKER_TYPE,
65053  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_18_WIDTH },
65054  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_19_CHECKER_TYPE,
65055  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_19_WIDTH },
65056  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_20_CHECKER_TYPE,
65057  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_20_WIDTH },
65058  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_21_CHECKER_TYPE,
65059  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_21_WIDTH },
65060  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_22_CHECKER_TYPE,
65061  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_22_WIDTH },
65062  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_23_CHECKER_TYPE,
65063  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_23_WIDTH },
65064  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_24_CHECKER_TYPE,
65065  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_24_WIDTH },
65066  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_25_CHECKER_TYPE,
65067  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_25_WIDTH },
65068  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_26_CHECKER_TYPE,
65069  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_26_WIDTH },
65070  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_27_CHECKER_TYPE,
65071  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_27_WIDTH },
65072  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_28_CHECKER_TYPE,
65073  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_28_WIDTH },
65074  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_29_CHECKER_TYPE,
65075  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_29_WIDTH },
65076  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_30_CHECKER_TYPE,
65077  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_30_WIDTH },
65078  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_31_CHECKER_TYPE,
65079  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_31_WIDTH },
65080  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_32_CHECKER_TYPE,
65081  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_32_WIDTH },
65082  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_33_CHECKER_TYPE,
65083  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_33_WIDTH },
65084  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_34_CHECKER_TYPE,
65085  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_34_WIDTH },
65086  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_35_CHECKER_TYPE,
65087  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_35_WIDTH },
65088  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_36_CHECKER_TYPE,
65089  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_GROUP_36_WIDTH },
65090 };
65091 
65097 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS] =
65098 {
65099  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_0_CHECKER_TYPE,
65100  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_0_WIDTH },
65101  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_1_CHECKER_TYPE,
65102  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_1_WIDTH },
65103  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_2_CHECKER_TYPE,
65104  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_2_WIDTH },
65105  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_3_CHECKER_TYPE,
65106  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_3_WIDTH },
65107  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_4_CHECKER_TYPE,
65108  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_4_WIDTH },
65109  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_5_CHECKER_TYPE,
65110  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_5_WIDTH },
65111  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_6_CHECKER_TYPE,
65112  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_6_WIDTH },
65113  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_7_CHECKER_TYPE,
65114  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_7_WIDTH },
65115  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_8_CHECKER_TYPE,
65116  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_8_WIDTH },
65117  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_9_CHECKER_TYPE,
65118  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_9_WIDTH },
65119  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_10_CHECKER_TYPE,
65120  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_10_WIDTH },
65121  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_11_CHECKER_TYPE,
65122  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_11_WIDTH },
65123  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_12_CHECKER_TYPE,
65124  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_12_WIDTH },
65125  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_13_CHECKER_TYPE,
65126  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_13_WIDTH },
65127  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_14_CHECKER_TYPE,
65128  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_14_WIDTH },
65129  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_15_CHECKER_TYPE,
65130  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_15_WIDTH },
65131  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_16_CHECKER_TYPE,
65132  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_16_WIDTH },
65133  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_17_CHECKER_TYPE,
65134  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_17_WIDTH },
65135  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_18_CHECKER_TYPE,
65136  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_18_WIDTH },
65137  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_19_CHECKER_TYPE,
65138  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_19_WIDTH },
65139  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_20_CHECKER_TYPE,
65140  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_20_WIDTH },
65141  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_21_CHECKER_TYPE,
65142  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_21_WIDTH },
65143  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_22_CHECKER_TYPE,
65144  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_22_WIDTH },
65145  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_23_CHECKER_TYPE,
65146  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_23_WIDTH },
65147  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_24_CHECKER_TYPE,
65148  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_24_WIDTH },
65149  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_25_CHECKER_TYPE,
65150  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_25_WIDTH },
65151  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_26_CHECKER_TYPE,
65152  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_26_WIDTH },
65153  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_27_CHECKER_TYPE,
65154  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_27_WIDTH },
65155  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_28_CHECKER_TYPE,
65156  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_28_WIDTH },
65157  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_29_CHECKER_TYPE,
65158  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_29_WIDTH },
65159  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_30_CHECKER_TYPE,
65160  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_30_WIDTH },
65161  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_31_CHECKER_TYPE,
65162  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_31_WIDTH },
65163  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_32_CHECKER_TYPE,
65164  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_32_WIDTH },
65165  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_33_CHECKER_TYPE,
65166  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_33_WIDTH },
65167  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_34_CHECKER_TYPE,
65168  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_34_WIDTH },
65169  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_35_CHECKER_TYPE,
65170  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_35_WIDTH },
65171  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_36_CHECKER_TYPE,
65172  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_GROUP_36_WIDTH },
65173 };
65174 
65180 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65181 {
65182  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65183  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65184  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65185  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65186  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65187  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65188  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65189  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65190  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65191  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65192  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65193  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65194  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65195  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65196  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65197  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65198  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65199  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65200  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65201  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65202  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65203  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65204  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65205  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65206  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65207  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65208  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65209  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65210  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65211  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65212  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65213  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65214  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65215  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65216  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65217  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65218  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65219  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65220  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65221  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65222  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65223  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65224  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65225  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65226  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65227  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65228  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65229  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65230  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65231  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65232  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65233  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65234  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65235  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65236  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65237  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65238  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65239  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65240  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65241  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65242  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
65243  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
65244  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
65245  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
65246  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
65247  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
65248 };
65249 
65255 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65256 {
65257  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65258  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65259  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65260  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65261  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65262  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65263  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65264  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65265  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65266  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65267  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65268  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65269  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65270  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65271  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65272  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65273  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65274  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65275  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65276  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65277  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65278  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65279  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65280  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65281  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65282  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65283  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65284  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65285  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65286  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65287  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65288  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65289  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65290  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65291  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65292  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65293  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65294  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65295  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65296  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65297  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65298  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65299  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65300  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65301  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65302  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65303  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65304  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65305  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65306  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65307  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65308  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65309  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65310  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65311  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65312  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65313  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65314  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65315  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65316  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65317  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
65318  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
65319  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
65320  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
65321  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
65322  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
65323  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
65324  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
65325  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
65326  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
65327  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
65328  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
65329  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
65330  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
65331  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
65332  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
65333 };
65334 
65340 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65341 {
65342  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65343  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65344  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65345  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65346  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65347  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65348  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65349  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65350  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65351  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65352  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65353  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65354  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65355  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65356  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65357  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65358  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65359  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65360  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65361  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65362  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65363  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65364  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65365  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65366  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65367  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65368  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65369  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65370  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65371  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65372  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65373  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65374  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65375  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65376  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65377  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65378  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65379  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65380  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65381  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65382  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65383  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65384  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65385  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65386  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65387  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65388  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65389  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65390  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65391  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65392  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65393  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65394  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65395  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65396  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65397  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65398  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65399  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65400  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65401  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65402  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
65403  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
65404  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
65405  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
65406  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
65407  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
65408  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
65409  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
65410  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
65411  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
65412  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
65413  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
65414  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
65415  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
65416  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
65417  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
65418 };
65419 
65425 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65426 {
65427  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65428  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65429  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65430  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65431  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65432  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65433  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65434  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65435  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65436  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65437  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65438  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65439  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65440  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65441  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65442  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65443  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65444  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65445  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65446  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65447  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65448  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65449  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65450  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65451  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65452  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65453  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65454  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65455  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65456  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65457  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65458  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65459  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65460  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65461  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65462  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65463  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65464  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65465  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65466  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65467  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65468  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65469  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65470  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65471  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65472  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65473  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65474  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65475  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65476  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65477  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65478  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65479  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65480  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65481  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65482  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65483  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65484  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65485  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65486  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65487  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
65488  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
65489  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
65490  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
65491  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
65492  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
65493  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
65494  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
65495  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
65496  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
65497  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
65498  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
65499  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
65500  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
65501  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
65502  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
65503 };
65504 
65510 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65511 {
65512  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65513  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65514  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65515  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65516  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65517  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65518  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65519  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65520  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65521  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65522  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65523  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65524  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65525  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65526  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65527  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65528  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65529  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65530  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65531  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65532  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65533  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65534  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65535  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65536  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65537  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65538  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65539  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65540  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65541  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65542  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65543  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65544  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65545  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65546  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65547  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65548  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65549  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65550  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65551  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65552  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65553  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65554  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65555  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65556  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65557  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65558  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65559  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65560  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65561  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65562  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65563  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65564  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65565  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65566  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65567  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65568  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65569  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65570  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65571  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65572  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
65573  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
65574  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
65575  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
65576  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
65577  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
65578  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
65579  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
65580  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
65581  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
65582  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
65583  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
65584  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
65585  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
65586  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
65587  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
65588 };
65589 
65595 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65596 {
65597  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65598  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65599  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65600  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65601  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65602  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65603  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65604  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65605  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65606  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65607  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65608  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65609  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65610  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65611  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65612  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65613  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65614  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65615  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65616  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65617  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65618  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65619  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65620  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65621  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65622  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65623  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65624  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65625  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65626  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65627  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65628  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65629  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65630  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65631  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65632  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65633  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65634  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65635  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65636  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65637  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65638  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65639  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65640  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65641  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65642  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65643  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65644  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65645  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65646  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65647  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65648  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65649  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65650  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65651  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65652  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65653  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65654  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65655  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65656  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65657 };
65658 
65664 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65665 {
65666  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65667  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65668  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65669  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65670  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65671  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65672  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65673  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65674  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65675  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65676  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65677  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65678  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65679  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65680  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65681  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65682  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65683  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65684  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65685  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65686  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65687  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65688  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65689  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65690  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65691  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65692  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65693  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65694  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65695  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65696  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65697  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65698  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65699  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65700  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65701  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65702  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65703  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65704  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65705  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65706  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65707  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65708  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65709  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65710  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65711  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65712  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65713  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65714  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65715  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65716  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65717  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65718  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65719  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65720  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65721  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65722  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65723  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65724  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65725  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65726  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
65727  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
65728  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
65729  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
65730  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
65731  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
65732  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
65733  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_33_WIDTH },
65734  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
65735  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_34_WIDTH },
65736  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
65737  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_35_WIDTH },
65738  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
65739  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_36_WIDTH },
65740  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
65741  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_GROUP_37_WIDTH },
65742 };
65743 
65749 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65750 {
65751  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65752  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65753  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65754  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65755  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65756  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65757  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65758  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65759  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65760  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65761  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65762  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65763  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65764  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65765  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65766  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65767  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65768  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65769  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65770  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65771  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65772  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65773  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65774  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65775  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65776  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65777  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65778  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65779  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65780  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65781  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65782  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65783  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65784  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65785  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65786  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65787  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65788  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65789  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65790  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65791  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65792  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65793  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65794  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65795  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65796  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65797  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65798  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65799  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65800  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65801  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65802  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65803  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65804  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65805  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65806  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65807  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65808  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65809  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65810  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65811 };
65812 
65818 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65819 {
65820  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65821  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
65822  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65823  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
65824  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65825  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
65826  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65827  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
65828  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65829  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
65830  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65831  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
65832  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65833  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
65834  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65835  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
65836  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65837  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
65838  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65839  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
65840  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65841  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
65842  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65843  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
65844  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65845  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
65846  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65847  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
65848  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65849  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
65850  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65851  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
65852  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65853  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
65854  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65855  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
65856  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65857  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
65858  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65859  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
65860  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65861  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
65862  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65863  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
65864  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65865  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
65866  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65867  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
65868  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65869  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
65870  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65871  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
65872  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65873  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
65874  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65875  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
65876  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65877  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
65878  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65879  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
65880 };
65881 
65887 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
65888 {
65889  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
65890  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
65891  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
65892  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
65893  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
65894  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
65895  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
65896  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
65897  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
65898  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
65899  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
65900  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
65901  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
65902  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
65903  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
65904  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
65905  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
65906  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
65907  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
65908  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
65909  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
65910  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
65911  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
65912  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
65913  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
65914  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
65915  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
65916  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
65917  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
65918  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
65919  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
65920  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
65921  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
65922  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
65923  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
65924  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
65925  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
65926  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
65927  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
65928  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
65929  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
65930  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
65931  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
65932  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
65933  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
65934  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
65935  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
65936  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
65937  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
65938  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
65939  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
65940  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
65941  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
65942  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
65943  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
65944  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
65945  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
65946  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
65947  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
65948  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
65949  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
65950  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
65951  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
65952  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
65953  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
65954  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
65955  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
65956  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
65957  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
65958  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
65959  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
65960  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
65961  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
65962  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
65963  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
65964  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
65965  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
65966  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
65967  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
65968  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
65969  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
65970  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
65971  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
65972  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
65973  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
65974  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
65975  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
65976  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
65977  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
65978  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
65979  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
65980  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
65981  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
65982  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
65983  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
65984  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
65985  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
65986  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
65987  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
65988  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
65989  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
65990  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
65991  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
65992  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
65993  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
65994  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
65995  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
65996  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
65997  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
65998  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
65999  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
66000  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
66001  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
66002  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
66003  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
66004  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
66005  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
66006  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
66007  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
66008  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
66009  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
66010  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
66011  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
66012  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
66013  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
66014  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
66015  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
66016  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
66017  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
66018  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
66019  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
66020  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
66021  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
66022  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
66023  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
66024  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
66025  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
66026  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
66027  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
66028  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
66029  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
66030  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
66031  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
66032  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
66033  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
66034  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
66035  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
66036  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
66037  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
66038  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
66039  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
66040  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
66041  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
66042  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
66043  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
66044  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
66045  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
66046  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
66047  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
66048  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
66049  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
66050  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
66051  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
66052  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
66053  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
66054  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
66055  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
66056  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
66057  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
66058  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
66059  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
66060  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
66061  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
66062  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
66063  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
66064  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
66065  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
66066  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
66067  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
66068  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
66069  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
66070  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
66071  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
66072  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
66073  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
66074  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
66075  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
66076  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
66077  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
66078  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
66079  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
66080  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
66081  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
66082  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
66083  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
66084  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
66085  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
66086  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
66087  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
66088  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
66089  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
66090  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
66091  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
66092  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_101_WIDTH },
66093  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
66094  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_102_WIDTH },
66095  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
66096  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_103_WIDTH },
66097  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
66098  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_104_WIDTH },
66099  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
66100  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_105_WIDTH },
66101  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
66102  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_106_WIDTH },
66103  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
66104  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_107_WIDTH },
66105  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
66106  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_108_WIDTH },
66107  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
66108  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_109_WIDTH },
66109  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
66110  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_110_WIDTH },
66111  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
66112  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_111_WIDTH },
66113  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
66114  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_112_WIDTH },
66115  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
66116  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_113_WIDTH },
66117  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
66118  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_114_WIDTH },
66119  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
66120  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_115_WIDTH },
66121  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
66122  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_116_WIDTH },
66123  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
66124  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_117_WIDTH },
66125  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
66126  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_118_WIDTH },
66127  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
66128  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_119_WIDTH },
66129  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
66130  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_120_WIDTH },
66131  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
66132  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_121_WIDTH },
66133  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
66134  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_122_WIDTH },
66135  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
66136  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_123_WIDTH },
66137  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
66138  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_124_WIDTH },
66139  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
66140  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_125_WIDTH },
66141  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
66142  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_126_WIDTH },
66143  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
66144  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_127_WIDTH },
66145  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
66146  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_128_WIDTH },
66147  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
66148  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_129_WIDTH },
66149  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
66150  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_130_WIDTH },
66151  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
66152  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_131_WIDTH },
66153  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
66154  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_132_WIDTH },
66155  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
66156  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_133_WIDTH },
66157  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
66158  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_134_WIDTH },
66159  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
66160  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_135_WIDTH },
66161  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
66162  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_136_WIDTH },
66163  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
66164  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_137_WIDTH },
66165  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
66166  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_138_WIDTH },
66167  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
66168  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_139_WIDTH },
66169  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
66170  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_140_WIDTH },
66171  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
66172  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_141_WIDTH },
66173  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
66174  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_142_WIDTH },
66175  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
66176  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_143_WIDTH },
66177  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
66178  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_144_WIDTH },
66179  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
66180  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_145_WIDTH },
66181  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
66182  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_146_WIDTH },
66183  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
66184  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_147_WIDTH },
66185  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
66186  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_148_WIDTH },
66187  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
66188  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_149_WIDTH },
66189  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
66190  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_150_WIDTH },
66191  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
66192  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_151_WIDTH },
66193  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
66194  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_152_WIDTH },
66195  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
66196  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_153_WIDTH },
66197  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
66198  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_154_WIDTH },
66199  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
66200  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_155_WIDTH },
66201  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
66202  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_156_WIDTH },
66203  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
66204  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_157_WIDTH },
66205  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
66206  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_158_WIDTH },
66207  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
66208  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_159_WIDTH },
66209  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
66210  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_160_WIDTH },
66211  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
66212  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_161_WIDTH },
66213  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
66214  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_162_WIDTH },
66215  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
66216  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_163_WIDTH },
66217  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
66218  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_164_WIDTH },
66219  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
66220  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_165_WIDTH },
66221  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
66222  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_166_WIDTH },
66223  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
66224  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_167_WIDTH },
66225  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
66226  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_168_WIDTH },
66227  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
66228  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_169_WIDTH },
66229  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
66230  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_170_WIDTH },
66231  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
66232  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_171_WIDTH },
66233  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
66234  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_172_WIDTH },
66235  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
66236  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_173_WIDTH },
66237  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
66238  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_174_WIDTH },
66239  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
66240  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_175_WIDTH },
66241  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
66242  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_176_WIDTH },
66243  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
66244  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_177_WIDTH },
66245  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
66246  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_178_WIDTH },
66247  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
66248  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_179_WIDTH },
66249  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
66250  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_180_WIDTH },
66251  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
66252  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_181_WIDTH },
66253  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
66254  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_182_WIDTH },
66255  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
66256  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_183_WIDTH },
66257  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
66258  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_184_WIDTH },
66259  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
66260  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_185_WIDTH },
66261  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
66262  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_186_WIDTH },
66263  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
66264  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_187_WIDTH },
66265  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
66266  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_188_WIDTH },
66267  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
66268  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_189_WIDTH },
66269  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
66270  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_190_WIDTH },
66271  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
66272  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_191_WIDTH },
66273  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
66274  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_192_WIDTH },
66275  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
66276  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_193_WIDTH },
66277  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
66278  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_194_WIDTH },
66279  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
66280  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_195_WIDTH },
66281  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
66282  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_196_WIDTH },
66283  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
66284  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_197_WIDTH },
66285  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
66286  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_198_WIDTH },
66287  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
66288  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_199_WIDTH },
66289  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
66290  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_200_WIDTH },
66291  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
66292  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_201_WIDTH },
66293  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
66294  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_202_WIDTH },
66295  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
66296  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_203_WIDTH },
66297  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
66298  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_204_WIDTH },
66299  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
66300  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_205_WIDTH },
66301  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
66302  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_206_WIDTH },
66303  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
66304  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_207_WIDTH },
66305  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
66306  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_208_WIDTH },
66307  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
66308  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_209_WIDTH },
66309  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
66310  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_210_WIDTH },
66311  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
66312  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_211_WIDTH },
66313  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
66314  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_212_WIDTH },
66315  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
66316  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_213_WIDTH },
66317  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
66318  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_214_WIDTH },
66319  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
66320  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_215_WIDTH },
66321  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
66322  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_216_WIDTH },
66323  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
66324  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_217_WIDTH },
66325  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
66326  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_218_WIDTH },
66327  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
66328  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_219_WIDTH },
66329  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
66330  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_220_WIDTH },
66331  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
66332  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_221_WIDTH },
66333  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
66334  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_222_WIDTH },
66335  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
66336  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_223_WIDTH },
66337  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
66338  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_224_WIDTH },
66339  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
66340  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_225_WIDTH },
66341  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
66342  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_226_WIDTH },
66343  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
66344  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_227_WIDTH },
66345  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
66346  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_228_WIDTH },
66347  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
66348  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_229_WIDTH },
66349  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
66350  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_230_WIDTH },
66351  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
66352  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_231_WIDTH },
66353  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
66354  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_232_WIDTH },
66355  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
66356  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_233_WIDTH },
66357  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
66358  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_234_WIDTH },
66359  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
66360  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_235_WIDTH },
66361  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
66362  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_236_WIDTH },
66363  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
66364  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_237_WIDTH },
66365  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
66366  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_GROUP_238_WIDTH },
66367 };
66368 
66374 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
66375 {
66376  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
66377  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
66378  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
66379  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
66380  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
66381  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
66382  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
66383  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
66384  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
66385  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
66386  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
66387  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
66388  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
66389  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
66390  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
66391  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
66392  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
66393  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
66394  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
66395  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
66396  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
66397  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
66398  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
66399  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
66400  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
66401  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
66402  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
66403  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
66404  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
66405  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
66406  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
66407  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
66408  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
66409  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
66410  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
66411  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
66412  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
66413  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
66414  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
66415  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
66416  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
66417  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
66418  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
66419  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
66420  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
66421  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
66422  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
66423  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
66424  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
66425  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
66426  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
66427  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
66428  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
66429  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
66430  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
66431  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
66432  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
66433  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
66434  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
66435  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
66436  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
66437  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
66438  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
66439  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
66440  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
66441  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
66442  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
66443  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
66444  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
66445  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
66446  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
66447  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
66448  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
66449  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
66450  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
66451  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
66452  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
66453  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
66454  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
66455  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
66456  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
66457  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
66458  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
66459  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
66460  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
66461  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
66462  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
66463  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
66464  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
66465  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
66466  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
66467  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
66468  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
66469  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
66470  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
66471  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
66472  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
66473  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
66474  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
66475  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
66476  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
66477  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
66478  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
66479  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
66480  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
66481  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
66482  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
66483  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
66484  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
66485  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
66486  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
66487  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
66488  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
66489  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
66490  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
66491  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
66492  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
66493  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
66494  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
66495  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
66496  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
66497  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
66498  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
66499  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
66500  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
66501  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
66502  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
66503  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
66504  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
66505  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
66506  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
66507  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
66508  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
66509  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
66510  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
66511  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
66512  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
66513  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
66514  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
66515  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
66516  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
66517  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
66518  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
66519  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
66520  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
66521  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
66522  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
66523  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
66524  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
66525  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
66526  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
66527  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
66528  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
66529  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
66530  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
66531  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
66532  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
66533  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
66534  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
66535  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
66536  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
66537  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
66538  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
66539  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
66540  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
66541  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
66542  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
66543  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
66544  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
66545  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
66546  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
66547  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
66548  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
66549  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
66550  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
66551  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
66552  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
66553  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
66554  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
66555  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
66556  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
66557  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
66558  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
66559  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
66560  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
66561  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
66562  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
66563  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
66564  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
66565  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
66566  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
66567  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
66568  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
66569  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
66570  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
66571  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
66572  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
66573  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
66574  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
66575  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
66576  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
66577  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
66578  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
66579  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_WIDTH },
66580  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
66581  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_WIDTH },
66582  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
66583  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_WIDTH },
66584  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
66585  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_WIDTH },
66586  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
66587  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_WIDTH },
66588  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
66589  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_WIDTH },
66590  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
66591  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_WIDTH },
66592  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
66593  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_WIDTH },
66594  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
66595  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_WIDTH },
66596  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
66597  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_WIDTH },
66598 };
66599 
66605 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
66606 {
66607  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
66608  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
66609  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
66610  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
66611  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
66612  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
66613  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
66614  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
66615  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
66616  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
66617  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
66618  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
66619  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
66620  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
66621  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
66622  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
66623  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
66624  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
66625  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
66626  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
66627  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
66628  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
66629  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
66630  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
66631  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
66632  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
66633  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
66634  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
66635  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
66636  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
66637  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
66638  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
66639  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
66640  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
66641  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
66642  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
66643  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
66644  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
66645  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
66646  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
66647  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
66648  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
66649  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
66650  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
66651  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
66652  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
66653  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
66654  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
66655  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
66656  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
66657  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
66658  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
66659  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
66660  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
66661  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
66662  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
66663  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
66664  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
66665  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
66666  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
66667  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
66668  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
66669  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
66670  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
66671  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
66672  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
66673  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
66674  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
66675  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
66676  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
66677  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
66678  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
66679  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
66680  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
66681  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
66682  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
66683  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
66684  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
66685  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
66686  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
66687  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
66688  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
66689  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
66690  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
66691  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
66692  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
66693  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
66694  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
66695  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
66696  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
66697  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
66698  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
66699  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
66700  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
66701  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
66702  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
66703  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
66704  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
66705  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
66706  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
66707  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
66708  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
66709  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
66710  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
66711  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
66712  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
66713  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
66714  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
66715  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
66716  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
66717  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
66718  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
66719  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
66720  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
66721  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
66722  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
66723  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
66724  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
66725  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
66726  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
66727  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
66728  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
66729  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
66730  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
66731  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
66732  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
66733  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
66734  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
66735  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
66736  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
66737  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
66738  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
66739  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
66740  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
66741  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
66742  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
66743  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
66744  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
66745  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
66746  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
66747  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
66748  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
66749  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
66750  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
66751  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
66752  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
66753  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
66754  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
66755  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
66756  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
66757  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
66758  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
66759  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
66760  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
66761  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
66762  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
66763  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
66764  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
66765  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
66766  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
66767  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
66768  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
66769  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
66770  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
66771  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
66772  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
66773  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
66774  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
66775  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
66776  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
66777  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
66778  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
66779  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
66780  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
66781  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
66782  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
66783  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
66784  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
66785  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
66786  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
66787  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
66788  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
66789  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
66790  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
66791  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
66792  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
66793  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
66794  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
66795  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
66796  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
66797  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
66798  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
66799  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
66800  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
66801  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
66802  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
66803  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
66804  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
66805  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
66806  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
66807  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
66808  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
66809  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
66810  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_101_WIDTH },
66811  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
66812  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_102_WIDTH },
66813  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
66814  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_103_WIDTH },
66815  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
66816  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_104_WIDTH },
66817  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
66818  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_105_WIDTH },
66819  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
66820  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_106_WIDTH },
66821  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
66822  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_107_WIDTH },
66823  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
66824  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_108_WIDTH },
66825  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
66826  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_109_WIDTH },
66827  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
66828  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_110_WIDTH },
66829 };
66830 
66836 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
66837 {
66838  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
66839  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
66840  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
66841  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
66842  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
66843  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
66844  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
66845  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
66846  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
66847  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
66848  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
66849  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
66850  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
66851  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
66852  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
66853  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
66854  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
66855  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
66856  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
66857  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
66858  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
66859  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
66860  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
66861  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
66862  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
66863  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
66864  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
66865  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
66866  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
66867  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
66868  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
66869  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
66870  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
66871  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
66872  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
66873  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
66874  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
66875  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
66876  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
66877  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
66878  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
66879  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
66880  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
66881  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
66882  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
66883  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
66884  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
66885  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
66886  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
66887  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
66888  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
66889  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
66890  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
66891  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
66892  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
66893  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
66894  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
66895  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
66896  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
66897  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
66898  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
66899  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
66900  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
66901  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
66902  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
66903  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
66904  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
66905  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
66906  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
66907  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
66908  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
66909  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
66910  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
66911  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
66912  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
66913  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
66914  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
66915  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
66916  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
66917  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
66918 };
66919 
66925 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
66926 {
66927  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
66928  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
66929  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
66930  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
66931  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
66932  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
66933  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
66934  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
66935  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
66936  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
66937  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
66938  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
66939  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
66940  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
66941  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
66942  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
66943  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
66944  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
66945  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
66946  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
66947  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
66948  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
66949  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
66950  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
66951  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
66952  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
66953  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
66954  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
66955  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
66956  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
66957  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
66958  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
66959  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
66960  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
66961  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
66962  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
66963  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
66964  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
66965  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
66966  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
66967  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
66968  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
66969  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
66970  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
66971  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
66972  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
66973  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
66974  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
66975  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
66976  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
66977  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
66978  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
66979  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
66980  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
66981  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
66982  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
66983  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
66984  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
66985  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
66986  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
66987  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
66988  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
66989  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
66990  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
66991  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
66992  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
66993  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
66994  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
66995  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
66996  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
66997 };
66998 
67004 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67005 {
67006  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67007  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
67008  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67009  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
67010  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67011  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
67012  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67013  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
67014  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67015  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
67016  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67017  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
67018  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67019  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
67020  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67021  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
67022  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67023  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
67024  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67025  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
67026  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67027  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
67028  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67029  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
67030  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67031  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
67032  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67033  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
67034  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67035  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
67036  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67037  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
67038  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67039  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
67040  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67041  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
67042  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67043  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
67044  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67045  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
67046  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67047  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
67048  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67049  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
67050  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67051  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
67052  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67053  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
67054  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67055  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
67056  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67057  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
67058  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67059  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
67060  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67061  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
67062  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67063  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
67064  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67065  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
67066  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67067  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
67068  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67069  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
67070  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67071  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
67072  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67073  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
67074  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67075  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
67076  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
67077  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
67078  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
67079  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
67080  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
67081  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
67082  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
67083  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
67084  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
67085  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
67086 };
67087 
67093 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67094 {
67095  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67096  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
67097  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67098  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
67099  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67100  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
67101  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67102  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
67103  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67104  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
67105  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67106  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
67107  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67108  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
67109  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67110  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
67111  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67112  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
67113  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67114  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
67115  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67116  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
67117  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67118  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
67119  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67120  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
67121  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67122  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
67123  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67124  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
67125  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67126  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
67127  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67128  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
67129  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67130  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
67131  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67132  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
67133  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67134  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
67135  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67136  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
67137  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67138  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
67139  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67140  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
67141  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67142  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
67143  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67144  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
67145  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67146  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
67147  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67148  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
67149  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67150  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
67151  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67152  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
67153  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67154  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
67155  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67156  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
67157  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67158  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
67159  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67160  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
67161  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67162  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
67163  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67164  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
67165  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
67166  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
67167  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
67168  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
67169  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
67170  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
67171  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
67172  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
67173  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
67174  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
67175 };
67176 
67182 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67183 {
67184  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67185  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
67186  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67187  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
67188  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67189  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
67190  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67191  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
67192  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67193  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
67194  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67195  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
67196  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67197  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
67198  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67199  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
67200  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67201  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
67202  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67203  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
67204  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67205  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
67206  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67207  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
67208  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67209  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
67210  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67211  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
67212  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67213  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
67214  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67215  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
67216  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67217  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
67218  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67219  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
67220  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67221  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
67222  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67223  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
67224  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67225  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
67226  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67227  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
67228  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67229  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
67230  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67231  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
67232  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67233  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
67234  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67235  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
67236  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67237  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
67238  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67239  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
67240  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67241  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
67242  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67243  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
67244  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67245  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
67246  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67247  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
67248  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67249  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
67250  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67251  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
67252  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67253  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
67254  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
67255  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
67256  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
67257  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
67258  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
67259  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
67260  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
67261  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
67262  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
67263  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
67264 };
67265 
67271 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67272 {
67273  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67274  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
67275  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67276  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
67277  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67278  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
67279  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67280  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
67281  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67282  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
67283  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67284  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
67285  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67286  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
67287  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67288  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
67289  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67290  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
67291  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67292  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
67293  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67294  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
67295  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67296  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
67297  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67298  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
67299  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67300  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
67301  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67302  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
67303  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67304  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
67305  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67306  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
67307  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67308  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
67309  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67310  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
67311  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67312  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
67313  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67314  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
67315  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67316  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
67317  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67318  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
67319  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67320  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
67321  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67322  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
67323  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67324  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
67325  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67326  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
67327  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67328  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
67329  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67330  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
67331  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67332  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
67333  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67334  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
67335  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67336  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
67337  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67338  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
67339  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67340  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
67341  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67342  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
67343  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
67344  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_35_WIDTH },
67345  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
67346  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_36_WIDTH },
67347  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
67348  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_37_WIDTH },
67349  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
67350  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_38_WIDTH },
67351  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
67352  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_GROUP_39_WIDTH },
67353 };
67354 
67360 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67361 {
67362  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67363  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
67364  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67365  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
67366  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67367  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
67368  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67369  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
67370  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67371  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
67372  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67373  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
67374  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67375  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
67376  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67377  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
67378  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67379  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
67380  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67381  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
67382  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67383  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
67384  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67385  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
67386  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67387  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
67388  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67389  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
67390  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67391  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
67392  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67393  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
67394  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67395  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
67396  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67397  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
67398  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67399  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
67400  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67401  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
67402  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67403  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
67404  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67405  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
67406  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67407  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
67408  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67409  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
67410  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67411  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
67412  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67413  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
67414  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67415  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
67416  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67417  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
67418  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67419  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
67420  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67421  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
67422  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67423  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
67424  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67425  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
67426  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67427  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
67428  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67429  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
67430  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67431  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
67432 };
67433 
67439 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67440 {
67441  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67442  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
67443  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67444  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
67445  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67446  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
67447  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67448  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
67449  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67450  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
67451  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67452  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
67453  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67454  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
67455  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67456  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
67457  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67458  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
67459  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67460  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
67461  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67462  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
67463  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67464  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
67465  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67466  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
67467  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67468  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
67469  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67470  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
67471  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67472  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
67473  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67474  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
67475  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67476  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
67477  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67478  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
67479  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67480  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
67481  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67482  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
67483  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67484  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
67485  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67486  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
67487  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67488  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
67489  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67490  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
67491  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67492  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
67493  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67494  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
67495  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67496  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
67497  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67498  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
67499  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67500  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
67501  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67502  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
67503  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67504  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
67505  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67506  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
67507  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67508  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
67509  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67510  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
67511  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
67512  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_35_WIDTH },
67513  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
67514  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_36_WIDTH },
67515  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
67516  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_37_WIDTH },
67517  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
67518  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_38_WIDTH },
67519  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
67520  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_GROUP_39_WIDTH },
67521 };
67522 
67528 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67529 {
67530  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67531  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
67532  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67533  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
67534 };
67535 
67541 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67542 {
67543  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67544  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
67545  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67546  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
67547 };
67548 
67554 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67555 {
67556  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67557  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
67558  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67559  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
67560 };
67561 
67567 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67568 {
67569  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67570  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
67571  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67572  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
67573 };
67574 
67580 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67581 {
67582  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67583  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
67584  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67585  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
67586  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67587  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
67588  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67589  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
67590  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67591  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
67592  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67593  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
67594  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67595  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
67596  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67597  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
67598  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67599  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
67600  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67601  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
67602  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67603  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
67604  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67605  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
67606  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67607  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
67608  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67609  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
67610  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67611  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
67612  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67613  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
67614  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67615  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
67616  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67617  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
67618  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67619  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
67620  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67621  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
67622  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67623  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
67624  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67625  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
67626  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67627  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
67628  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67629  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
67630  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67631  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
67632  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67633  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
67634  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67635  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
67636  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67637  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
67638  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67639  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
67640  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67641  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
67642  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67643  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
67644  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67645  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
67646  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67647  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
67648  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67649  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
67650  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67651  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
67652 };
67653 
67659 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67660 {
67661  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67662  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
67663  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67664  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
67665  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67666  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
67667  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67668  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
67669  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67670  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
67671  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67672  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
67673  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67674  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
67675  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67676  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
67677  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67678  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
67679  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67680  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
67681  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67682  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
67683  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67684  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
67685  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67686  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
67687  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67688  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
67689  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67690  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
67691  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67692  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
67693  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67694  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
67695  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67696  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
67697  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67698  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
67699  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67700  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
67701  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67702  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
67703  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67704  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
67705  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67706  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
67707  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67708  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
67709  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67710  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
67711  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67712  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
67713  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67714  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
67715  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67716  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
67717  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67718  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
67719  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67720  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
67721  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67722  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
67723  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67724  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
67725  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67726  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
67727  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67728  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
67729  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67730  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
67731 };
67732 
67738 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67739 {
67740  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67741  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
67742  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67743  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
67744  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67745  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
67746 };
67747 
67753 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
67754 {
67755  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
67756  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
67757  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
67758  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
67759  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
67760  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
67761  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
67762  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
67763  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
67764  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
67765  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
67766  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
67767  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
67768  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
67769  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
67770  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
67771  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
67772  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
67773  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
67774  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
67775  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
67776  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
67777  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
67778  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
67779  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
67780  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
67781  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
67782  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
67783  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
67784  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
67785  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
67786  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
67787  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
67788  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
67789  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
67790  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
67791  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
67792  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
67793  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
67794  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
67795  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
67796  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
67797  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
67798  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
67799  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
67800  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
67801  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
67802  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
67803  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
67804  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
67805  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
67806  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
67807  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
67808  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
67809  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
67810  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
67811  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
67812  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
67813  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
67814  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
67815  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
67816  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
67817  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
67818  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
67819  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
67820  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
67821  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
67822  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
67823  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
67824  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
67825  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
67826  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
67827  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
67828  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
67829  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
67830  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
67831  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
67832  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
67833  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
67834  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
67835  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
67836  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
67837  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
67838  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
67839  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
67840  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
67841  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
67842  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
67843  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
67844  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
67845  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
67846  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
67847  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
67848  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
67849  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
67850  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
67851  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
67852  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
67853  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
67854  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
67855  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
67856  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
67857  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
67858  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
67859  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
67860  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
67861  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
67862  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
67863  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
67864  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
67865  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
67866  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
67867  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
67868  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
67869  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
67870  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
67871  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
67872  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
67873  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
67874  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
67875  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
67876  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
67877  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
67878  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
67879  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
67880  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
67881  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
67882  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
67883  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
67884  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
67885  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
67886  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
67887  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
67888  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
67889  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
67890  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
67891  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
67892  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
67893  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
67894  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
67895  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
67896  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
67897  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
67898  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
67899  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
67900  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
67901  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
67902  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
67903  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
67904  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
67905  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
67906  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
67907  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
67908  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
67909  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
67910  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
67911  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
67912  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
67913  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
67914  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
67915  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
67916  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
67917  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
67918  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
67919  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
67920  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
67921  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
67922  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
67923  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
67924  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
67925  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
67926  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
67927  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
67928  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
67929  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
67930  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
67931  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
67932  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
67933  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
67934  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
67935  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
67936  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
67937  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
67938  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
67939  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
67940  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
67941  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
67942  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
67943  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
67944  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
67945  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
67946  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
67947  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
67948  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
67949  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
67950  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
67951  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
67952  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
67953  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
67954  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
67955  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
67956  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
67957  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
67958  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
67959  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
67960  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
67961  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
67962  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
67963  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
67964  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
67965  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
67966  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
67967  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
67968  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
67969  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
67970  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
67971  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
67972  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
67973  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
67974  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
67975  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
67976  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
67977  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
67978  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
67979  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
67980  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
67981  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
67982  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
67983  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
67984  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
67985  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
67986  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
67987  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
67988  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
67989  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
67990  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
67991  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
67992  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
67993  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
67994  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
67995  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
67996  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
67997  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
67998  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
67999  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
68000  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
68001  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
68002  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
68003  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
68004  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
68005  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
68006  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
68007  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
68008  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
68009  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
68010  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
68011  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
68012  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
68013  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
68014  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
68015  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
68016  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
68017  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
68018  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
68019  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
68020  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
68021  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
68022  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
68023  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
68024  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
68025  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
68026  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
68027  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
68028  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
68029  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
68030  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
68031  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
68032  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
68033  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
68034  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
68035  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
68036  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
68037  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
68038  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
68039  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
68040  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
68041  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
68042  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
68043  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
68044  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
68045  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
68046  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
68047  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
68048  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
68049  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
68050  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
68051  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
68052  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
68053  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
68054  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
68055  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
68056  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
68057  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
68058  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
68059  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
68060  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
68061  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
68062  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
68063  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
68064  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
68065  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
68066  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
68067  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
68068  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
68069  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
68070  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
68071  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
68072  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
68073  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
68074  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
68075  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
68076  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
68077  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
68078  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
68079  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
68080  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
68081  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
68082  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
68083  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
68084  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
68085  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
68086  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
68087  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
68088  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
68089  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
68090  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
68091  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
68092  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
68093  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
68094  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
68095  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
68096  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
68097  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
68098  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
68099  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
68100  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
68101  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
68102  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
68103  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
68104  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
68105  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
68106  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
68107  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
68108  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
68109  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
68110  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
68111  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
68112  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
68113  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
68114  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
68115  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
68116  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
68117  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
68118  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
68119  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
68120  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
68121  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
68122  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
68123  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
68124  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
68125  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
68126  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
68127  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
68128  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
68129  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
68130  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
68131  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
68132  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
68133  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
68134  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
68135  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
68136  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
68137  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
68138  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
68139  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
68140  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
68141  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
68142  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
68143  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
68144  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
68145  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
68146  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
68147  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
68148  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
68149  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
68150  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
68151  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
68152  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
68153  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
68154  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
68155  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
68156  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
68157  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
68158  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
68159  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
68160  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
68161  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
68162  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
68163  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
68164  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
68165  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
68166  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
68167  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
68168  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
68169  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
68170  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
68171  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
68172  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
68173  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
68174  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
68175  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
68176  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
68177  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
68178  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
68179  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
68180  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
68181  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
68182  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
68183  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
68184  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
68185  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
68186  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
68187  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
68188  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
68189  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
68190  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
68191  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
68192  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
68193  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
68194  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
68195  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
68196  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
68197  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
68198  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
68199  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
68200  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
68201  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
68202  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
68203  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
68204  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
68205  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
68206  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
68207  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
68208  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
68209  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
68210  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
68211  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
68212  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
68213  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
68214  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_229_WIDTH },
68215  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
68216  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_230_WIDTH },
68217  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
68218  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_231_WIDTH },
68219  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
68220  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_232_WIDTH },
68221  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
68222  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_233_WIDTH },
68223  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
68224  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_234_WIDTH },
68225  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
68226  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_235_WIDTH },
68227  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
68228  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_236_WIDTH },
68229  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
68230  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_237_WIDTH },
68231  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
68232  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_238_WIDTH },
68233  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
68234  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_239_WIDTH },
68235  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
68236  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_240_WIDTH },
68237  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
68238  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_241_WIDTH },
68239 };
68240 
68246 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
68247 {
68248  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
68249  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
68250  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
68251  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
68252  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
68253  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
68254  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
68255  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
68256  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
68257  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
68258  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
68259  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
68260  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
68261  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
68262  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
68263  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
68264  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
68265  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
68266  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
68267  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
68268  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
68269  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
68270  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
68271  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
68272  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
68273  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
68274  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
68275  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
68276  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
68277  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
68278  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
68279  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
68280  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
68281  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
68282  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
68283  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
68284  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
68285  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
68286  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
68287  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
68288  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
68289  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
68290  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
68291  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
68292  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
68293  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
68294  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
68295  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
68296  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
68297  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
68298  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
68299  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
68300  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
68301  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
68302  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
68303  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
68304  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
68305  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
68306  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
68307  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
68308  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
68309  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
68310  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
68311  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
68312  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
68313  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
68314  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
68315  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
68316  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
68317  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
68318  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
68319  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
68320  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
68321  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
68322  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
68323  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
68324  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
68325  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
68326  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
68327  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
68328  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
68329  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
68330  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
68331  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
68332  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
68333  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
68334  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
68335  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
68336  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
68337  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
68338  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
68339  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
68340  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
68341  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
68342  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
68343  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
68344  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
68345  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
68346  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
68347  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
68348  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
68349  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
68350  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
68351  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
68352  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
68353  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
68354  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
68355  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
68356  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
68357  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
68358  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
68359  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
68360  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
68361  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
68362  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
68363  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
68364  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
68365  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
68366  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
68367  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
68368  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
68369  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
68370  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
68371  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
68372  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
68373  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
68374  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
68375  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
68376  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
68377  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
68378  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
68379  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
68380  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
68381  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
68382  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
68383  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
68384  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
68385  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
68386  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
68387  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
68388  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
68389  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
68390  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
68391  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
68392  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
68393  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
68394  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
68395  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
68396  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
68397  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
68398  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
68399  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
68400  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
68401  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
68402  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
68403  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
68404  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
68405  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
68406  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
68407  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
68408  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
68409  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
68410  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
68411  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
68412  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
68413  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
68414  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
68415  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
68416  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
68417  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
68418  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
68419  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
68420  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
68421  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
68422  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
68423  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
68424  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
68425  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
68426  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
68427  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
68428  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
68429  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
68430  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
68431  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
68432  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
68433  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
68434  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
68435  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
68436  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
68437  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
68438  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
68439  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
68440  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
68441  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
68442  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
68443  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
68444  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
68445  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
68446  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
68447  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
68448  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
68449  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
68450  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
68451  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
68452  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
68453  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
68454  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
68455  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
68456  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
68457  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
68458  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
68459  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
68460  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
68461  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
68462  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
68463  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
68464  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
68465  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
68466  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
68467  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
68468  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
68469  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
68470  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
68471  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
68472  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
68473  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
68474  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
68475  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
68476  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
68477  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
68478  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
68479  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
68480  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
68481  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
68482  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
68483  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
68484  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
68485  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
68486  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
68487  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
68488  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
68489  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
68490  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
68491  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
68492  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
68493  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
68494  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
68495  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
68496  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
68497  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
68498  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
68499  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
68500  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
68501  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
68502  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
68503  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
68504  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
68505  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
68506  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
68507  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
68508  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
68509  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
68510  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
68511  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
68512  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
68513  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
68514  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
68515  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
68516  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
68517  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
68518  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
68519  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
68520  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
68521  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
68522  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
68523  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
68524  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
68525  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
68526  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
68527  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
68528  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
68529  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
68530  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
68531  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
68532  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
68533  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
68534  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
68535  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
68536  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
68537  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
68538  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
68539  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
68540  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
68541  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
68542  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
68543  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
68544  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
68545  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
68546  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
68547  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
68548  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
68549  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
68550  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
68551  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
68552  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
68553  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
68554  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
68555  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
68556  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
68557  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
68558  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
68559  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
68560  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
68561  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
68562  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
68563  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
68564  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
68565  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
68566  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
68567  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
68568  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
68569  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
68570  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
68571  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
68572  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
68573  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
68574  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
68575  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
68576  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
68577  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
68578  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
68579  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
68580  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
68581  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
68582  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
68583  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
68584  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
68585  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
68586  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
68587  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
68588  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
68589  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
68590  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
68591  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
68592  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
68593  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
68594  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
68595  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
68596  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
68597  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
68598  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
68599  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
68600  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
68601  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
68602  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
68603  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
68604  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
68605  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
68606  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
68607  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
68608  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
68609  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
68610  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
68611  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
68612  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
68613  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
68614  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
68615  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
68616  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
68617  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
68618  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
68619  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
68620  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
68621  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
68622  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
68623  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
68624  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
68625  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
68626  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
68627  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
68628  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
68629  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
68630  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
68631  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
68632  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
68633  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
68634  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
68635  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
68636  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
68637  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
68638  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
68639  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
68640  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
68641  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
68642  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
68643  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
68644  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
68645  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
68646  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
68647  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
68648  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
68649  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
68650  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
68651  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
68652  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
68653  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
68654  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
68655  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
68656  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
68657  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
68658  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
68659  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
68660  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
68661  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
68662  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
68663  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
68664  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
68665  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
68666  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
68667  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
68668  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
68669  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
68670  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
68671  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
68672  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
68673  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
68674  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
68675  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
68676  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
68677  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
68678  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
68679  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
68680  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
68681  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
68682  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
68683  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
68684  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
68685  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
68686  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
68687  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
68688  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
68689  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
68690  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
68691  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
68692  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
68693  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
68694  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
68695  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
68696  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
68697  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
68698  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
68699  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
68700  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
68701  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
68702  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
68703  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
68704  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
68705  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
68706 };
68707 
68713 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
68714 {
68715  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
68716  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
68717 };
68718 
68724 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
68725 {
68726  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
68727  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
68728  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
68729  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
68730  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
68731  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
68732  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
68733  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
68734  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
68735  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
68736  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
68737  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
68738  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
68739  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
68740  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
68741  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
68742  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
68743  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
68744  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
68745  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
68746  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
68747  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
68748  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
68749  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
68750  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
68751  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
68752  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
68753  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
68754  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
68755  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
68756  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
68757  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
68758  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
68759  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
68760  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
68761  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
68762  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
68763  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
68764  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
68765  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
68766  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
68767  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
68768  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
68769  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
68770  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
68771  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
68772  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
68773  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
68774  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
68775  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
68776  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
68777  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
68778  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
68779  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
68780  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
68781  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
68782  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
68783  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
68784  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
68785  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
68786  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
68787  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
68788  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
68789  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
68790  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
68791  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
68792  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
68793  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
68794  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
68795  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
68796  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
68797  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
68798  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
68799  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
68800  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
68801  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
68802  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
68803  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
68804  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
68805  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
68806  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
68807  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
68808  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
68809  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
68810  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
68811  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
68812  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
68813  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
68814  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
68815  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
68816  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
68817  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
68818  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
68819  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
68820  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
68821  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
68822  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
68823  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
68824  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
68825  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
68826  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
68827  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
68828  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
68829  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
68830  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
68831  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
68832  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
68833  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
68834  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
68835  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
68836  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
68837  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
68838  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
68839  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
68840  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
68841  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
68842  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
68843  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
68844  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
68845  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
68846  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
68847  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
68848  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
68849  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
68850  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
68851  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
68852  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
68853  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
68854  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
68855  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
68856  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
68857  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
68858  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
68859  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
68860  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
68861  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
68862  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
68863  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
68864  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
68865  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
68866  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
68867  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
68868  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
68869  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
68870  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
68871  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
68872  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
68873  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
68874  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
68875  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
68876  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
68877  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
68878  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
68879  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
68880  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
68881  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
68882  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
68883  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
68884  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
68885  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
68886  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
68887  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
68888  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
68889  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
68890  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
68891  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
68892  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
68893  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
68894  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
68895  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
68896  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
68897  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
68898  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
68899  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
68900  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
68901  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
68902  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
68903  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
68904  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
68905  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
68906  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
68907  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
68908  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
68909  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
68910  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
68911  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
68912  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
68913  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
68914  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
68915  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
68916  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
68917  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
68918  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
68919  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
68920  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
68921  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
68922  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
68923  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
68924  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
68925  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
68926  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
68927  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
68928  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
68929  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
68930  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
68931  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
68932  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
68933  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
68934  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
68935  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
68936  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
68937  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
68938  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
68939  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
68940  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
68941  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
68942  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
68943  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
68944  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
68945  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
68946  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
68947  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
68948  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
68949  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
68950  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
68951  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
68952  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
68953  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
68954  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
68955  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
68956  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
68957  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
68958  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
68959  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
68960  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
68961  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
68962  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
68963  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
68964  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
68965  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
68966  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
68967  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
68968  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
68969  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
68970  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
68971  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
68972  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
68973  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
68974  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
68975  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
68976  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
68977  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
68978  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
68979  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
68980  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
68981  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
68982  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
68983  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
68984  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
68985  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
68986  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
68987  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
68988  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
68989  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
68990  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
68991  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
68992  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
68993  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
68994  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
68995  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
68996  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
68997  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
68998  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
68999  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
69000  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
69001  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
69002  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
69003  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
69004  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
69005  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
69006  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
69007  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
69008  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
69009  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
69010  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
69011  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
69012  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
69013  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
69014  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
69015  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
69016  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
69017  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
69018  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
69019  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
69020  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
69021  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
69022  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
69023  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
69024  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
69025  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
69026  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
69027  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
69028  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
69029  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
69030  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
69031  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
69032  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
69033  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
69034  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
69035  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
69036  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
69037  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
69038  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
69039  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
69040  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
69041  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
69042  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
69043  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
69044  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
69045  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
69046  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
69047  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
69048  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
69049  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
69050  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
69051  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
69052  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
69053  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
69054  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
69055  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
69056  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
69057  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
69058  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
69059  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
69060  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
69061  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
69062  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
69063  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
69064  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
69065  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
69066  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
69067  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
69068  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
69069  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_171_WIDTH },
69070  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
69071  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_172_WIDTH },
69072  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
69073  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_173_WIDTH },
69074  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
69075  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_174_WIDTH },
69076  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
69077  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_175_WIDTH },
69078  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
69079  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_176_WIDTH },
69080  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
69081  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_177_WIDTH },
69082  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
69083  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_178_WIDTH },
69084  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
69085  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_179_WIDTH },
69086  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
69087  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_180_WIDTH },
69088  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
69089  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_181_WIDTH },
69090  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
69091  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_182_WIDTH },
69092  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
69093  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_183_WIDTH },
69094  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
69095  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_184_WIDTH },
69096  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
69097  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_185_WIDTH },
69098  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
69099  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_186_WIDTH },
69100  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
69101  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_187_WIDTH },
69102  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
69103  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_188_WIDTH },
69104  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
69105  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_189_WIDTH },
69106  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
69107  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_190_WIDTH },
69108  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
69109  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_191_WIDTH },
69110  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
69111  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_192_WIDTH },
69112  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
69113  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_193_WIDTH },
69114  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
69115  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_194_WIDTH },
69116  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
69117  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_195_WIDTH },
69118  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
69119  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_196_WIDTH },
69120  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
69121  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_197_WIDTH },
69122  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
69123  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_198_WIDTH },
69124  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
69125  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_199_WIDTH },
69126  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
69127  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_200_WIDTH },
69128  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
69129  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_201_WIDTH },
69130  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
69131  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_202_WIDTH },
69132  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
69133  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_203_WIDTH },
69134  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
69135  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_204_WIDTH },
69136  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
69137  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_205_WIDTH },
69138  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
69139  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_206_WIDTH },
69140  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
69141  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_207_WIDTH },
69142  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
69143  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_208_WIDTH },
69144  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
69145  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_209_WIDTH },
69146  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
69147  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_210_WIDTH },
69148  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
69149  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_211_WIDTH },
69150  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
69151  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_212_WIDTH },
69152  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
69153  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_213_WIDTH },
69154  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
69155  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_214_WIDTH },
69156  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
69157  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_215_WIDTH },
69158  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
69159  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_216_WIDTH },
69160  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
69161  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_217_WIDTH },
69162  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
69163  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_218_WIDTH },
69164  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
69165  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_219_WIDTH },
69166  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
69167  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_220_WIDTH },
69168  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
69169  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_221_WIDTH },
69170  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
69171  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_222_WIDTH },
69172  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
69173  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_223_WIDTH },
69174  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
69175  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_224_WIDTH },
69176  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
69177  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_225_WIDTH },
69178  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
69179  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_226_WIDTH },
69180  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
69181  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_227_WIDTH },
69182  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
69183  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_228_WIDTH },
69184  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
69185  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_229_WIDTH },
69186  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
69187  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_230_WIDTH },
69188  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
69189  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_231_WIDTH },
69190  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
69191  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_232_WIDTH },
69192  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
69193  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_233_WIDTH },
69194  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
69195  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_234_WIDTH },
69196  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
69197  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_235_WIDTH },
69198  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
69199  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_236_WIDTH },
69200  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
69201  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_237_WIDTH },
69202  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
69203  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_238_WIDTH },
69204  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
69205  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_239_WIDTH },
69206  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
69207  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_240_WIDTH },
69208  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
69209  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_241_WIDTH },
69210  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
69211  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_242_WIDTH },
69212  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
69213  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_243_WIDTH },
69214  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
69215  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_244_WIDTH },
69216  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
69217  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_245_WIDTH },
69218  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
69219  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_246_WIDTH },
69220  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
69221  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_247_WIDTH },
69222  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
69223  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_248_WIDTH },
69224  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
69225  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_249_WIDTH },
69226  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
69227  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_250_WIDTH },
69228  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
69229  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_251_WIDTH },
69230  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
69231  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_252_WIDTH },
69232  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
69233  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_253_WIDTH },
69234  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
69235  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_254_WIDTH },
69236  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
69237  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_255_WIDTH },
69238 };
69239 
69245 static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS] =
69246 {
69247  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
69248  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_0_WIDTH },
69249  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
69250  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_1_WIDTH },
69251  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
69252  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_2_WIDTH },
69253  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
69254  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_3_WIDTH },
69255  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
69256  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_4_WIDTH },
69257  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
69258  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_5_WIDTH },
69259  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
69260  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_6_WIDTH },
69261  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
69262  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_7_WIDTH },
69263  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
69264  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_8_WIDTH },
69265  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
69266  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_9_WIDTH },
69267  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
69268  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_10_WIDTH },
69269  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
69270  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_11_WIDTH },
69271  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
69272  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_12_WIDTH },
69273  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
69274  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_13_WIDTH },
69275  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
69276  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_14_WIDTH },
69277  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
69278  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_15_WIDTH },
69279  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
69280  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_16_WIDTH },
69281  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
69282  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_17_WIDTH },
69283  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
69284  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_18_WIDTH },
69285  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
69286  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_19_WIDTH },
69287  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
69288  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_20_WIDTH },
69289  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
69290  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_21_WIDTH },
69291  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
69292  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_22_WIDTH },
69293  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
69294  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_23_WIDTH },
69295  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
69296  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_24_WIDTH },
69297  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
69298  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_25_WIDTH },
69299  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
69300  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_26_WIDTH },
69301  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
69302  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_27_WIDTH },
69303  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
69304  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_28_WIDTH },
69305  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
69306  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_29_WIDTH },
69307  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
69308  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_30_WIDTH },
69309  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
69310  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_31_WIDTH },
69311  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
69312  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_32_WIDTH },
69313  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
69314  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_33_WIDTH },
69315  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
69316  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_34_WIDTH },
69317  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
69318  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_GROUP_35_WIDTH },
69319 };
69320 
69325 static const SDL_MemConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69326 {
69327  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_RAM_ID, 0x41C00000u,
69328  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
69329  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
69330 };
69331 
69337 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
69338 {
69339  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
69340  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
69341  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
69342  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
69343  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
69344  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
69345  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
69346  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
69347  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
69348  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
69349  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
69350  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
69351  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
69352  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
69353  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
69354  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
69355  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
69356  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
69357  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
69358  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
69359  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
69360  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
69361  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
69362  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
69363  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
69364  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
69365  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
69366  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
69367  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
69368  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
69369  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
69370  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
69371  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
69372  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
69373  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
69374  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
69375  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
69376  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
69377  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
69378  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
69379  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
69380  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
69381  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
69382  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
69383  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
69384  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
69385  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
69386  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
69387 };
69388 
69394 static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
69395 {
69396  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
69397  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
69398  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
69399  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
69400  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
69401  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
69402  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
69403  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
69404  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
69405  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
69406  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
69407  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
69408 };
69409 
69414 static const SDL_MemConfig_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69415 {
69416  { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x27D8000u,
69417  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
69418  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
69419 };
69420 
69426 static const SDL_GrpChkConfig_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
69427 {
69428  { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
69429  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
69430 };
69431 
69436 static const SDL_MemConfig_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69437 {
69438  { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x27B8000u,
69439  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
69440  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
69441 };
69442 
69448 static const SDL_GrpChkConfig_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
69449 {
69450  { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
69451  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
69452 };
69453 
69458 static const SDL_MemConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69459 {
69460  { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2768000u,
69461  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
69462  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
69463 };
69464 
69470 static const SDL_GrpChkConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
69471 {
69472  { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
69473  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
69474 };
69475 
69480 static const SDL_MemConfig_t SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_MemEntries[SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES] =
69481 {
69482  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_RAM_ID, 0u,
69483  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_RAM_SIZE, 4u,
69484  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_ROW_WIDTH, ((bool)false) },
69485  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_RAM_ID, 0u,
69486  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_RAM_SIZE, 4u,
69487  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_ROW_WIDTH, ((bool)false) },
69488  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_RAM_ID, 0u,
69489  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_RAM_SIZE, 4u,
69490  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_ROW_WIDTH, ((bool)false) },
69491  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_RAM_ID, 0u,
69492  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_RAM_SIZE, 4u,
69493  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_ROW_WIDTH, ((bool)false) },
69494 };
69495 
69500 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69501 {
69502  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69503  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69504  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69505  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69506  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69507  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69508  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69509  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69510  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69511  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69512  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69513  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69514  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
69515  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
69516  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69517  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
69518  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
69519  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69520  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69521  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69522  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69523  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69524  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69525  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69526  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69527  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69528  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69529  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69530  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69531  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69532  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69533  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69534  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69535  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69536  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69537  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69538  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
69539  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
69540  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69541  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
69542  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
69543  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69544  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
69545  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
69546  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69547  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
69548  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
69549  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69550  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69551  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69552  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69553  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69554  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69555  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69556  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69557  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69558  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69559  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69560  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69561  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69562  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69563  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69564  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69565  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69566  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69567  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69568  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69569  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69570  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69571  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69572  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69573  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69574 };
69575 
69581 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_MAX_NUM_CHECKERS] =
69582 {
69583  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_0_CHECKER_TYPE,
69584  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_0_WIDTH },
69585  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_1_CHECKER_TYPE,
69586  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_1_WIDTH },
69587  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_2_CHECKER_TYPE,
69588  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_2_WIDTH },
69589  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_3_CHECKER_TYPE,
69590  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_3_WIDTH },
69591  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_4_CHECKER_TYPE,
69592  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_4_WIDTH },
69593  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_5_CHECKER_TYPE,
69594  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_GROUP_5_WIDTH },
69595 };
69596 
69601 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69602 {
69603  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69604  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69605  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69606  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69607  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69608  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69609  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69610  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69611  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69612  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69613  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69614  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69615  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
69616  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
69617  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69618  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
69619  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
69620  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69621  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69622  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69623  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69624  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69625  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69626  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69627  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69628  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69629  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69630  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69631  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69632  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69633  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69634  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69635  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69636  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69637  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69638  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69639  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID, 0u,
69640  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_SIZE, 4u,
69641  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69642  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID, 0u,
69643  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_SIZE, 4u,
69644  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69645  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID, 0u,
69646  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_SIZE, 4u,
69647  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69648  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID, 0u,
69649  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_SIZE, 4u,
69650  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69651  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69652  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69653  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69654  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69655  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69656  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69657  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69658  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69659  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69660  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69661  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69662  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69663  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID, 0u,
69664  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_SIZE, 4u,
69665  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69666  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID, 0u,
69667  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_SIZE, 4u,
69668  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69669  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID, 0u,
69670  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_SIZE, 4u,
69671  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69672  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID, 0u,
69673  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_SIZE, 4u,
69674  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ROW_WIDTH, ((bool)false) },
69675 };
69676 
69682 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_MAX_NUM_CHECKERS] =
69683 {
69684  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_0_CHECKER_TYPE,
69685  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_0_WIDTH },
69686  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_1_CHECKER_TYPE,
69687  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_1_WIDTH },
69688  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_2_CHECKER_TYPE,
69689  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_2_WIDTH },
69690  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_3_CHECKER_TYPE,
69691  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_3_WIDTH },
69692  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_4_CHECKER_TYPE,
69693  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_4_WIDTH },
69694  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_5_CHECKER_TYPE,
69695  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_GROUP_5_WIDTH },
69696 };
69697 
69702 static const SDL_MemConfig_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69703 {
69704  { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2798000u,
69705  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
69706  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
69707 };
69708 
69714 static const SDL_GrpChkConfig_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
69715 {
69716  { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
69717  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
69718 };
69719 
69724 static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69725 {
69726  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2728000u,
69727  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
69728  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
69729 };
69730 
69736 static const SDL_GrpChkConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
69737 {
69738  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
69739  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
69740 };
69741 
69746 static const SDL_MemConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69747 {
69748  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_RAM_ID, 0x3600000u,
69749  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
69750  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
69751 };
69752 
69758 static const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS] =
69759 {
69760  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
69761  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_0_WIDTH },
69762  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
69763  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_1_WIDTH },
69764  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
69765  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_2_WIDTH },
69766  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
69767  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_3_WIDTH },
69768  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
69769  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_4_WIDTH },
69770  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
69771  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_5_WIDTH },
69772  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
69773  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_6_WIDTH },
69774  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
69775  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_7_WIDTH },
69776  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
69777  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_8_WIDTH },
69778  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
69779  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_9_WIDTH },
69780  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
69781  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_10_WIDTH },
69782  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
69783  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_11_WIDTH },
69784  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
69785  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_12_WIDTH },
69786  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
69787  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_13_WIDTH },
69788  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
69789  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_14_WIDTH },
69790  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
69791  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_15_WIDTH },
69792  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
69793  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_16_WIDTH },
69794  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
69795  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_17_WIDTH },
69796  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
69797  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_18_WIDTH },
69798  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
69799  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_19_WIDTH },
69800  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
69801  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_20_WIDTH },
69802  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
69803  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_21_WIDTH },
69804  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
69805  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_22_WIDTH },
69806  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
69807  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_23_WIDTH },
69808  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
69809  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_24_WIDTH },
69810  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
69811  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_25_WIDTH },
69812  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
69813  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_26_WIDTH },
69814  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
69815  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_27_WIDTH },
69816  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
69817  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_28_WIDTH },
69818  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
69819  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_GROUP_29_WIDTH },
69820 };
69821 
69827 static const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
69828 {
69829  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
69830  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
69831  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
69832  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
69833  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
69834  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
69835  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
69836  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
69837  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
69838  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
69839  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
69840  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
69841 };
69842 
69847 static const SDL_MemConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69848 {
69849  { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2778000u,
69850  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
69851  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
69852 };
69853 
69859 static const SDL_GrpChkConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
69860 {
69861  { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
69862  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
69863 };
69864 
69869 static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES] =
69870 {
69871  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
69872  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
69873  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
69874 };
69875 
69880 static const SDL_MemConfig_t SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69881 {
69882  { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
69883  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
69884  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
69885  { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
69886  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
69887  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
69888 };
69889 
69894 static const SDL_MemConfig_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES] =
69895 {
69896  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
69897  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
69898  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
69899  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
69900  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
69901  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
69902  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
69903  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
69904  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
69905  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID, 0u,
69906  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_SIZE, 4u,
69907  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ROW_WIDTH, ((bool)false) },
69908  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID, 0u,
69909  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_SIZE, 4u,
69910  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ROW_WIDTH, ((bool)false) },
69911  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID, 0u,
69912  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_SIZE, 4u,
69913  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ROW_WIDTH, ((bool)false) },
69914  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
69915  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
69916  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
69917  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
69918  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
69919  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
69920 };
69921 
69927 static const SDL_GrpChkConfig_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS] =
69928 {
69929  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
69930  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_0_WIDTH },
69931  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
69932  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_1_WIDTH },
69933  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
69934  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_2_WIDTH },
69935  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
69936  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_3_WIDTH },
69937  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
69938  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_4_WIDTH },
69939  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
69940  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_5_WIDTH },
69941  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
69942  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_6_WIDTH },
69943  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
69944  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_7_WIDTH },
69945  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
69946  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_8_WIDTH },
69947  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
69948  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_9_WIDTH },
69949  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
69950  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_10_WIDTH },
69951  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
69952  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_11_WIDTH },
69953  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
69954  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_12_WIDTH },
69955  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
69956  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_13_WIDTH },
69957  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
69958  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_14_WIDTH },
69959  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
69960  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_GROUP_15_WIDTH },
69961 };
69962 
69968 static const SDL_GrpChkConfig_t SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS] =
69969 {
69970  { SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
69971  SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_0_WIDTH },
69972  { SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
69973  SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_GROUP_1_WIDTH },
69974 };
69975 
69980 static const SDL_MemConfig_t SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
69981 {
69982  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0xB100000u,
69983  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
69984  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
69985  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0xB102000u,
69986  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
69987  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
69988  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0xB134000u,
69989  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
69990  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
69991  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0xB138000u,
69992  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
69993  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
69994  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0xB110000u,
69995  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
69996  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
69997  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0xB104000u,
69998  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
69999  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
70000  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0xB106000u,
70001  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
70002  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)true) },
70003  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0xB10A000u,
70004  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
70005  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
70006  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0xB10C000u,
70007  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
70008  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
70009 };
70010 
70016 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
70017 {
70018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
70019  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
70020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
70021  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
70022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
70023  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
70024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
70025  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
70026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
70027  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
70028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
70029  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
70030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
70031  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
70032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
70033  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
70034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
70035  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
70036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
70037  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
70038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
70039  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
70040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
70041  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
70042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
70043  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
70044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
70045  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
70046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
70047  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
70048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
70049  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
70050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
70051  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
70052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
70053  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
70054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
70055  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
70056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
70057  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
70058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
70059  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
70060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
70061  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
70062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
70063  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
70064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
70065  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
70066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
70067  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
70068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
70069  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
70070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
70071  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
70072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
70073  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
70074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
70075  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
70076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
70077  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
70078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
70079  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
70080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
70081  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
70082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
70083  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
70084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
70085  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
70086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
70087  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
70088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
70089  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
70090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
70091  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
70092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
70093  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
70094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
70095  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
70096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
70097  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
70098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
70099  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
70100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
70101  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
70102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
70103  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
70104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
70105  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
70106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
70107  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
70108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
70109  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
70110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
70111  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
70112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
70113  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
70114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
70115  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
70116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
70117  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
70118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
70119  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
70120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
70121  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
70122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
70123  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
70124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
70125  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
70126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
70127  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
70128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
70129  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
70130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
70131  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
70132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
70133  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
70134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
70135  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
70136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
70137  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
70138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
70139  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
70140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
70141  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
70142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
70143  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
70144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
70145  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
70146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
70147  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
70148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
70149  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
70150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
70151  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
70152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
70153  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
70154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
70155  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
70156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
70157  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
70158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
70159  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
70160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
70161  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
70162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
70163  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
70164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
70165  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
70166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
70167  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
70168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
70169  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
70170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
70171  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
70172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
70173  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
70174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
70175  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
70176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
70177  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
70178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
70179  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
70180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
70181  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
70182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
70183  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
70184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
70185  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
70186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
70187  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
70188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
70189  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
70190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
70191  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
70192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
70193  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
70194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
70195  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
70196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
70197  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
70198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
70199  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
70200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
70201  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
70202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
70203  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
70204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
70205  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
70206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
70207  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
70208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
70209  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
70210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
70211  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
70212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
70213  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
70214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
70215  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
70216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
70217  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
70218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
70219  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
70220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
70221  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
70222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
70223  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
70224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
70225  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
70226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
70227  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
70228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
70229  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
70230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
70231  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
70232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
70233  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
70234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
70235  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
70236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
70237  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
70238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
70239  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
70240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
70241  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
70242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
70243  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
70244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
70245  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
70246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
70247  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
70248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
70249  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
70250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
70251  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
70252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
70253  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
70254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
70255  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
70256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
70257  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
70258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
70259  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
70260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
70261  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
70262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
70263  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
70264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
70265  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
70266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
70267  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
70268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
70269  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
70270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
70271  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
70272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
70273  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
70274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
70275  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
70276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
70277  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
70278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
70279  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
70280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
70281  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
70282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
70283  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
70284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
70285  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
70286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
70287  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
70288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
70289  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
70290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
70291  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
70292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
70293  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
70294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
70295  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
70296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
70297  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
70298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
70299  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
70300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
70301  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
70302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
70303  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
70304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
70305  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
70306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
70307  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
70308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
70309  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
70310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
70311  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
70312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
70313  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
70314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
70315  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
70316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
70317  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
70318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
70319  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
70320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
70321  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
70322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
70323  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
70324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
70325  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
70326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
70327  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
70328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
70329  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
70330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
70331  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
70332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
70333  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
70334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
70335  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
70336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
70337  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
70338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
70339  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
70340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
70341  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
70342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
70343  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
70344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
70345  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
70346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
70347  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
70348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
70349  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
70350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
70351  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
70352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
70353  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
70354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
70355  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
70356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
70357  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
70358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
70359  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
70360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
70361  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
70362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
70363  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
70364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
70365  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
70366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
70367  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
70368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
70369  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
70370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
70371  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
70372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
70373  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
70374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
70375  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
70376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
70377  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
70378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
70379  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
70380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
70381  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
70382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
70383  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
70384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
70385  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
70386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
70387  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
70388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
70389  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
70390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
70391  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
70392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
70393  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
70394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
70395  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
70396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
70397  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
70398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
70399  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
70400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
70401  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
70402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
70403  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
70404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
70405  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
70406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
70407  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
70408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
70409  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
70410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
70411  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
70412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
70413  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
70414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
70415  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
70416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
70417  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
70418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
70419  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
70420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
70421  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
70422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
70423  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
70424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
70425  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
70426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
70427  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
70428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
70429  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
70430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
70431  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
70432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
70433  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
70434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
70435  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
70436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
70437  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
70438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
70439  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
70440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
70441  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
70442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
70443  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
70444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
70445  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
70446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
70447  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
70448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
70449  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
70450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
70451  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
70452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
70453  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
70454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
70455  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
70456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
70457  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
70458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
70459  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
70460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
70461  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
70462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
70463  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
70464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
70465  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
70466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
70467  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
70468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
70469  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
70470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
70471  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
70472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
70473  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
70474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
70475  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
70476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
70477  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
70478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
70479  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
70480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
70481  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
70482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
70483  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
70484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
70485  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
70486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
70487  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
70488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
70489  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
70490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
70491  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
70492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
70493  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
70494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
70495  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
70496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
70497  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
70498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
70499  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
70500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
70501  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
70502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
70503  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
70504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
70505  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
70506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
70507  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
70508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
70509  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
70510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
70511  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
70512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
70513  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
70514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
70515  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
70516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
70517  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
70518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
70519  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
70520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
70521  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
70522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
70523  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
70524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
70525  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
70526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
70527  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
70528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
70529  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
70530 };
70531 
70537 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
70538 {
70539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
70540  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
70541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
70542  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
70543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
70544  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
70545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
70546  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
70547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
70548  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
70549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
70550  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
70551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
70552  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
70553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
70554  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
70555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
70556  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
70557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
70558  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
70559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
70560  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
70561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
70562  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
70563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
70564  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
70565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
70566  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
70567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
70568  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
70569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
70570  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
70571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
70572  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
70573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
70574  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
70575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
70576  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
70577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
70578  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
70579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
70580  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
70581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
70582  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
70583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
70584  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
70585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
70586  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
70587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
70588  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
70589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
70590  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
70591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
70592  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
70593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
70594  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
70595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
70596  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
70597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
70598  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
70599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
70600  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
70601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
70602  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
70603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
70604  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
70605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
70606  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
70607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
70608  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
70609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
70610  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
70611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
70612  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
70613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
70614  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
70615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
70616  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
70617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
70618  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
70619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
70620  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
70621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
70622  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
70623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
70624  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
70625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
70626  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
70627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
70628  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
70629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
70630  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
70631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
70632  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
70633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
70634  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
70635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
70636  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
70637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
70638  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
70639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
70640  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
70641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
70642  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
70643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
70644  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
70645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
70646  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
70647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
70648  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
70649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
70650  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
70651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
70652  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
70653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
70654  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
70655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
70656  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
70657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
70658  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
70659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
70660  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
70661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
70662  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
70663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
70664  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
70665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
70666  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
70667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
70668  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
70669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
70670  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
70671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
70672  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
70673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
70674  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
70675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
70676  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
70677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
70678  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
70679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
70680  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
70681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
70682  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
70683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
70684  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
70685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
70686  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
70687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
70688  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
70689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
70690  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
70691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
70692  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
70693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
70694  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
70695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
70696  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
70697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
70698  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
70699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
70700  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
70701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
70702  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
70703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
70704  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
70705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
70706  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
70707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
70708  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
70709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
70710  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
70711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
70712  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
70713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
70714  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
70715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
70716  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
70717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
70718  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
70719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
70720  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
70721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
70722  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
70723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
70724  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
70725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
70726  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
70727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
70728  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
70729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
70730  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
70731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
70732  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
70733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
70734  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
70735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
70736  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
70737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
70738  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
70739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
70740  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
70741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
70742  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
70743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
70744  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
70745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
70746  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
70747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
70748  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
70749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
70750  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
70751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
70752  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
70753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
70754  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
70755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
70756  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
70757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
70758  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
70759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
70760  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
70761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
70762  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
70763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
70764  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
70765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
70766  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
70767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
70768  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
70769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
70770  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
70771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
70772  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
70773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
70774  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
70775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
70776  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
70777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
70778  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
70779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
70780  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
70781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
70782  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
70783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
70784  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
70785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
70786  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
70787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
70788  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
70789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
70790  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
70791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
70792  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
70793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
70794  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
70795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
70796  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
70797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
70798  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
70799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
70800  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
70801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
70802  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
70803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
70804  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
70805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
70806  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
70807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
70808  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
70809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
70810  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
70811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
70812  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
70813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
70814  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
70815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
70816  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
70817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
70818  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
70819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
70820  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
70821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
70822  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
70823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
70824  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
70825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
70826  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
70827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
70828  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
70829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
70830  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
70831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
70832  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
70833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
70834  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
70835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
70836  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
70837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
70838  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
70839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
70840  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
70841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
70842  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
70843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
70844  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
70845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
70846  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
70847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
70848  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
70849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
70850  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
70851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
70852  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
70853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
70854  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
70855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
70856  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
70857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
70858  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
70859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
70860  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
70861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
70862  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
70863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
70864  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
70865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
70866  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
70867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
70868  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
70869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
70870  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
70871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
70872  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
70873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
70874  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
70875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
70876  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
70877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
70878  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
70879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
70880  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
70881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
70882  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
70883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
70884  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
70885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
70886  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
70887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
70888  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
70889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
70890  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
70891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
70892  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
70893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
70894  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
70895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
70896  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
70897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
70898  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
70899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
70900  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
70901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
70902  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
70903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
70904  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
70905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
70906  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
70907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
70908  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
70909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
70910  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
70911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
70912  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
70913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
70914  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
70915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
70916  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
70917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
70918  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
70919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
70920  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
70921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
70922  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
70923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
70924  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
70925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
70926  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
70927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
70928  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
70929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
70930  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
70931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
70932  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
70933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
70934  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
70935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
70936  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
70937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
70938  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
70939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
70940  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
70941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
70942  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
70943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
70944  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
70945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
70946  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
70947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
70948  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
70949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
70950  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
70951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
70952  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
70953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
70954  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
70955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
70956  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
70957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
70958  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
70959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
70960  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
70961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
70962  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
70963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
70964  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
70965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
70966  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
70967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
70968  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
70969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
70970  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
70971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
70972  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
70973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
70974  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
70975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
70976  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
70977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
70978  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
70979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
70980  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
70981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
70982  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
70983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
70984  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
70985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
70986  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
70987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
70988  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
70989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
70990  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
70991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
70992  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
70993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
70994  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
70995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
70996  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
70997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
70998  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
70999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
71000  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
71001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
71002  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
71003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
71004  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
71005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
71006  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
71007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
71008  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
71009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
71010  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
71011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
71012  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
71013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
71014  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
71015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
71016  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
71017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
71018  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
71019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
71020  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
71021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
71022  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
71023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
71024  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
71025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
71026  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
71027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
71028  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
71029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
71030  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
71031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
71032  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
71033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
71034  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
71035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
71036  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
71037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
71038  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
71039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
71040  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
71041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
71042  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
71043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
71044  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
71045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
71046  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
71047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
71048  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
71049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
71050  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
71051 };
71052 
71058 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
71059 {
71060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
71061  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
71062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
71063  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
71064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
71065  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
71066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
71067  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
71068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
71069  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
71070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
71071  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
71072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
71073  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
71074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
71075  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
71076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
71077  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
71078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
71079  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
71080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
71081  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
71082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
71083  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
71084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
71085  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
71086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
71087  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
71088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
71089  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
71090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
71091  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
71092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
71093  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
71094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
71095  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
71096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
71097  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
71098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
71099  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
71100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
71101  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
71102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
71103  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
71104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
71105  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
71106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
71107  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
71108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
71109  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
71110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
71111  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
71112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
71113  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
71114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
71115  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
71116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
71117  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
71118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
71119  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
71120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
71121  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
71122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
71123  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
71124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
71125  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
71126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
71127  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
71128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
71129  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
71130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
71131  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
71132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
71133  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
71134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
71135  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
71136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
71137  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
71138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
71139  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
71140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
71141  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
71142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
71143  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
71144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
71145  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
71146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
71147  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
71148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
71149  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
71150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
71151  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
71152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
71153  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
71154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
71155  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
71156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
71157  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
71158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
71159  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
71160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
71161  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
71162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
71163  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
71164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
71165  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
71166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
71167  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
71168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
71169  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
71170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
71171  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
71172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
71173  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
71174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
71175  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
71176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
71177  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
71178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
71179  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
71180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
71181  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
71182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
71183  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
71184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
71185  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
71186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
71187  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
71188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
71189  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
71190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
71191  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
71192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
71193  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
71194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
71195  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
71196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
71197  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
71198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
71199  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
71200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
71201  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
71202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
71203  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
71204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
71205  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
71206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
71207  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
71208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
71209  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
71210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
71211  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
71212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
71213  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
71214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
71215  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
71216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
71217  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
71218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
71219  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
71220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
71221  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
71222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
71223  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
71224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
71225  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
71226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
71227  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
71228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
71229  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
71230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
71231  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
71232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
71233  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
71234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
71235  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
71236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
71237  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
71238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
71239  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
71240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
71241  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
71242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
71243  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
71244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
71245  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
71246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
71247  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
71248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
71249  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
71250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
71251  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
71252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
71253  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
71254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
71255  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
71256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
71257  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
71258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
71259  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
71260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
71261  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
71262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
71263  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
71264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
71265  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
71266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
71267  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
71268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
71269  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
71270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
71271  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
71272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
71273  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
71274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
71275  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
71276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
71277  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
71278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
71279  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
71280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
71281  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
71282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
71283  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
71284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
71285  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
71286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
71287  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
71288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
71289  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
71290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
71291  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
71292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
71293  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
71294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
71295  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
71296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
71297  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
71298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
71299  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
71300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
71301  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
71302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
71303  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
71304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
71305  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
71306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
71307  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
71308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
71309  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
71310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
71311  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
71312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
71313  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
71314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
71315  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
71316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
71317  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
71318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
71319  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
71320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
71321  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
71322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
71323  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
71324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
71325  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
71326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
71327  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
71328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
71329  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
71330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
71331  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
71332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
71333  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
71334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
71335  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
71336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
71337  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
71338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
71339  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
71340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
71341  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
71342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
71343  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
71344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
71345  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
71346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
71347  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
71348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
71349  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
71350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
71351  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
71352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
71353  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
71354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
71355  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
71356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
71357  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
71358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
71359  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
71360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
71361  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
71362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
71363  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
71364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
71365  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
71366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
71367  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
71368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
71369  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
71370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
71371  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
71372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
71373  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
71374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
71375  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
71376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
71377  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
71378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
71379  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
71380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
71381  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
71382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
71383  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
71384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
71385  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
71386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
71387  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
71388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
71389  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
71390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
71391  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
71392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
71393  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
71394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
71395  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
71396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
71397  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
71398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
71399  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
71400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
71401  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
71402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
71403  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
71404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
71405  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
71406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
71407  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
71408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
71409  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
71410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
71411  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
71412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
71413  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
71414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
71415  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
71416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
71417  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
71418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
71419  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
71420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
71421  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
71422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
71423  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
71424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
71425  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
71426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
71427  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
71428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
71429  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
71430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
71431  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
71432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
71433  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
71434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
71435  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
71436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
71437  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
71438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
71439  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
71440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
71441  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
71442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
71443  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
71444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
71445  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
71446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
71447  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
71448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
71449  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
71450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
71451  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
71452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
71453  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
71454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
71455  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
71456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
71457  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
71458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
71459  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
71460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
71461  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
71462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
71463  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
71464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
71465  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
71466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
71467  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
71468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
71469  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
71470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
71471  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
71472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
71473  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
71474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
71475  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
71476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
71477  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
71478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
71479  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
71480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
71481  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
71482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
71483  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
71484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
71485  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
71486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
71487  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
71488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
71489  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
71490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
71491  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
71492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
71493  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
71494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
71495  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
71496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
71497  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
71498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
71499  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
71500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
71501  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
71502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
71503  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
71504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
71505  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
71506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
71507  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
71508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
71509  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
71510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
71511  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
71512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
71513  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
71514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
71515  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
71516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
71517  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
71518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
71519  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
71520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
71521  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
71522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
71523  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
71524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
71525  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
71526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
71527  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
71528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
71529  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
71530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
71531  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
71532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
71533  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
71534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
71535  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
71536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
71537  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
71538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
71539  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
71540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
71541  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
71542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
71543  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
71544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
71545  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
71546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
71547  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
71548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
71549  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
71550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
71551  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
71552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
71553  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
71554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
71555  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
71556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
71557  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
71558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
71559  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
71560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
71561  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
71562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
71563  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
71564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
71565  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
71566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
71567  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
71568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
71569  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
71570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
71571  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
71572 };
71573 
71579 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
71580 {
71581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
71582  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
71583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
71584  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
71585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
71586  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
71587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
71588  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
71589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
71590  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
71591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
71592  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
71593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
71594  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
71595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
71596  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
71597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
71598  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
71599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
71600  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
71601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
71602  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
71603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
71604  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
71605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
71606  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
71607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
71608  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
71609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
71610  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
71611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
71612  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
71613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
71614  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
71615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
71616  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
71617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
71618  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
71619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
71620  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
71621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
71622  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
71623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
71624  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
71625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
71626  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
71627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
71628  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
71629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
71630  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
71631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
71632  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
71633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
71634  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
71635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
71636  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
71637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
71638  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
71639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
71640  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
71641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
71642  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
71643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
71644  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
71645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
71646  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
71647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
71648  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
71649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
71650  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
71651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
71652  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
71653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
71654  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
71655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
71656  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
71657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
71658  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
71659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
71660  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
71661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
71662  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
71663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
71664  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
71665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
71666  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
71667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
71668  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
71669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
71670  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
71671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
71672  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
71673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
71674  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
71675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
71676  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
71677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
71678  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
71679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
71680  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
71681 };
71682 
71688 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
71689 {
71690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
71691  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
71692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
71693  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
71694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
71695  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
71696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
71697  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
71698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
71699  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
71700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
71701  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
71702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
71703  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
71704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
71705  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
71706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
71707  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
71708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
71709  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
71710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
71711  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
71712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
71713  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
71714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
71715  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
71716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
71717  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
71718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
71719  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
71720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
71721  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
71722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
71723  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
71724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
71725  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
71726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
71727  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
71728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
71729  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
71730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
71731  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
71732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
71733  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
71734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
71735  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
71736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
71737  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
71738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
71739  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
71740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
71741  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
71742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
71743  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
71744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
71745  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
71746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
71747  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
71748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
71749  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
71750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
71751  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
71752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
71753  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
71754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
71755  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
71756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
71757  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
71758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
71759  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
71760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
71761  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
71762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
71763  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
71764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
71765  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
71766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
71767  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
71768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
71769  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
71770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
71771  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
71772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
71773  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
71774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
71775  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
71776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
71777  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
71778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
71779  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
71780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
71781  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
71782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
71783  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
71784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
71785  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
71786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
71787  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
71788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
71789  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
71790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
71791  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
71792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
71793  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
71794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
71795  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
71796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
71797  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
71798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
71799  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
71800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
71801  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
71802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
71803  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
71804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
71805  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
71806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
71807  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
71808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
71809  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
71810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
71811  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
71812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
71813  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
71814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
71815  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
71816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
71817  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
71818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
71819  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
71820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
71821  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
71822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
71823  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
71824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
71825  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
71826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
71827  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
71828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
71829  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
71830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
71831  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
71832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
71833  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
71834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
71835  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
71836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
71837  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
71838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
71839  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
71840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
71841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
71842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
71843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
71844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
71845  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
71846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
71847  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
71848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
71849  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
71850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
71851  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
71852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
71853  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
71854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
71855  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
71856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
71857  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
71858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
71859  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
71860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
71861  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
71862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
71863  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
71864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
71865  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
71866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
71867  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
71868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
71869  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
71870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
71871  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
71872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
71873  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
71874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
71875  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
71876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
71877  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
71878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
71879  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
71880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
71881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
71882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
71883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
71884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
71885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
71886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
71887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
71888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
71889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
71890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
71891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
71892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
71893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
71894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
71895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
71896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
71897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
71898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
71899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
71900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
71901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
71902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
71903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
71904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
71905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
71906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
71907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
71908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
71909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
71910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
71911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
71912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
71913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
71914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
71915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
71916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
71917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
71918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
71919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
71920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
71921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
71922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
71923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
71924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
71925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
71926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
71927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
71928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
71929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
71930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
71931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
71932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
71933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
71934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
71935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
71936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
71937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
71938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
71939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
71940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
71941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
71942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
71943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
71944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
71945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
71946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
71947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
71948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
71949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
71950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
71951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
71952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
71953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
71954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
71955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
71956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
71957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
71958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
71959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
71960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
71961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
71962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
71963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
71964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
71965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
71966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
71967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
71968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
71969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
71970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
71971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
71972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
71973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
71974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
71975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
71976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
71977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
71978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
71979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
71980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
71981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
71982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
71983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
71984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
71985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
71986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
71987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
71988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
71989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
71990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
71991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
71992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
71993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
71994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
71995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
71996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
71997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
71998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
71999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
72000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
72001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
72002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
72003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
72004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
72005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
72006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
72007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
72008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
72009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
72010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
72011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
72012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
72013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
72014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
72015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
72016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
72017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
72018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
72019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
72020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
72021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
72022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
72023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
72024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
72025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
72026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
72027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
72028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
72029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
72030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
72031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
72032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
72033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
72034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
72035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
72036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
72037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
72038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
72039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
72040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
72041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
72042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
72043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
72044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
72045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
72046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
72047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
72048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
72049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
72050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
72051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
72052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
72053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
72054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
72055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
72056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
72057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
72058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
72059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
72060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
72061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
72062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
72063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
72064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
72065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
72066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
72067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
72068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
72069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
72070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
72071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
72072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
72073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
72074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
72075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
72076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
72077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
72078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
72079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
72080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
72081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
72082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
72083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
72084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
72085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
72086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
72087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
72088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
72089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
72090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
72091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
72092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
72093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
72094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
72095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
72096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
72097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
72098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
72099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
72100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
72101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
72102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
72103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
72104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
72105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
72106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
72107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
72108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
72109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
72110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
72111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
72112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
72113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
72114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
72115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
72116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
72117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
72118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
72119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
72120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
72121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
72122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
72123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
72124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
72125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
72126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
72127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
72128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
72129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
72130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
72131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
72132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
72133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
72134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
72135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
72136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
72137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
72138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
72139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
72140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
72141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
72142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
72143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
72144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
72145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
72146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
72147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
72148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
72149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
72150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
72151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
72152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
72153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
72154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
72155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
72156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
72157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
72158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
72159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
72160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
72161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
72162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
72163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
72164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
72165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
72166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
72167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
72168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
72169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
72170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
72171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
72172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
72173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
72174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
72175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
72176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
72177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
72178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
72179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
72180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
72181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
72182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
72183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
72184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
72185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
72186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
72187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
72188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
72189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
72190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
72191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
72192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
72193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
72194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
72195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
72196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
72197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
72198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
72199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
72200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
72201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
72202 };
72203 
72209 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS] =
72210 {
72211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_0_CHECKER_TYPE,
72212  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_0_WIDTH },
72213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_1_CHECKER_TYPE,
72214  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_1_WIDTH },
72215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_2_CHECKER_TYPE,
72216  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_2_WIDTH },
72217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_3_CHECKER_TYPE,
72218  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_3_WIDTH },
72219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_4_CHECKER_TYPE,
72220  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_4_WIDTH },
72221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_5_CHECKER_TYPE,
72222  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_5_WIDTH },
72223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_6_CHECKER_TYPE,
72224  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_6_WIDTH },
72225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_7_CHECKER_TYPE,
72226  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_7_WIDTH },
72227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_8_CHECKER_TYPE,
72228  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_8_WIDTH },
72229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_9_CHECKER_TYPE,
72230  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_9_WIDTH },
72231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_10_CHECKER_TYPE,
72232  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_10_WIDTH },
72233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_11_CHECKER_TYPE,
72234  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_11_WIDTH },
72235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_12_CHECKER_TYPE,
72236  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_12_WIDTH },
72237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_13_CHECKER_TYPE,
72238  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_13_WIDTH },
72239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_14_CHECKER_TYPE,
72240  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_14_WIDTH },
72241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_15_CHECKER_TYPE,
72242  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_15_WIDTH },
72243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_16_CHECKER_TYPE,
72244  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_16_WIDTH },
72245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_17_CHECKER_TYPE,
72246  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_17_WIDTH },
72247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_18_CHECKER_TYPE,
72248  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_18_WIDTH },
72249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_19_CHECKER_TYPE,
72250  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_19_WIDTH },
72251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_20_CHECKER_TYPE,
72252  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_20_WIDTH },
72253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_21_CHECKER_TYPE,
72254  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_21_WIDTH },
72255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_22_CHECKER_TYPE,
72256  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_22_WIDTH },
72257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_23_CHECKER_TYPE,
72258  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_23_WIDTH },
72259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_24_CHECKER_TYPE,
72260  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_24_WIDTH },
72261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_25_CHECKER_TYPE,
72262  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_25_WIDTH },
72263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_26_CHECKER_TYPE,
72264  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_26_WIDTH },
72265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_27_CHECKER_TYPE,
72266  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_27_WIDTH },
72267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_28_CHECKER_TYPE,
72268  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_28_WIDTH },
72269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_29_CHECKER_TYPE,
72270  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_29_WIDTH },
72271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_30_CHECKER_TYPE,
72272  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_30_WIDTH },
72273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_31_CHECKER_TYPE,
72274  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_31_WIDTH },
72275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_32_CHECKER_TYPE,
72276  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_32_WIDTH },
72277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_33_CHECKER_TYPE,
72278  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_33_WIDTH },
72279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_34_CHECKER_TYPE,
72280  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_34_WIDTH },
72281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_35_CHECKER_TYPE,
72282  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_35_WIDTH },
72283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_36_CHECKER_TYPE,
72284  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_36_WIDTH },
72285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_37_CHECKER_TYPE,
72286  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_37_WIDTH },
72287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_38_CHECKER_TYPE,
72288  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_38_WIDTH },
72289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_39_CHECKER_TYPE,
72290  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_39_WIDTH },
72291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_40_CHECKER_TYPE,
72292  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_40_WIDTH },
72293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_41_CHECKER_TYPE,
72294  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_41_WIDTH },
72295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_42_CHECKER_TYPE,
72296  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_42_WIDTH },
72297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_43_CHECKER_TYPE,
72298  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_43_WIDTH },
72299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_44_CHECKER_TYPE,
72300  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_44_WIDTH },
72301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_45_CHECKER_TYPE,
72302  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_45_WIDTH },
72303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_46_CHECKER_TYPE,
72304  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_46_WIDTH },
72305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_47_CHECKER_TYPE,
72306  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_47_WIDTH },
72307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_48_CHECKER_TYPE,
72308  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_48_WIDTH },
72309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_49_CHECKER_TYPE,
72310  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_49_WIDTH },
72311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_50_CHECKER_TYPE,
72312  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_50_WIDTH },
72313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_51_CHECKER_TYPE,
72314  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_51_WIDTH },
72315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_52_CHECKER_TYPE,
72316  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_52_WIDTH },
72317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_53_CHECKER_TYPE,
72318  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_53_WIDTH },
72319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_54_CHECKER_TYPE,
72320  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_54_WIDTH },
72321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_55_CHECKER_TYPE,
72322  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_55_WIDTH },
72323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_56_CHECKER_TYPE,
72324  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_56_WIDTH },
72325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_57_CHECKER_TYPE,
72326  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_57_WIDTH },
72327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_58_CHECKER_TYPE,
72328  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_58_WIDTH },
72329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_59_CHECKER_TYPE,
72330  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_59_WIDTH },
72331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_60_CHECKER_TYPE,
72332  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_60_WIDTH },
72333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_61_CHECKER_TYPE,
72334  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_61_WIDTH },
72335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_62_CHECKER_TYPE,
72336  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_62_WIDTH },
72337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_63_CHECKER_TYPE,
72338  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_63_WIDTH },
72339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_64_CHECKER_TYPE,
72340  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_64_WIDTH },
72341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_65_CHECKER_TYPE,
72342  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_65_WIDTH },
72343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_66_CHECKER_TYPE,
72344  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_66_WIDTH },
72345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_67_CHECKER_TYPE,
72346  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_67_WIDTH },
72347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_68_CHECKER_TYPE,
72348  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_68_WIDTH },
72349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_69_CHECKER_TYPE,
72350  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_69_WIDTH },
72351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_70_CHECKER_TYPE,
72352  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_70_WIDTH },
72353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_71_CHECKER_TYPE,
72354  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_71_WIDTH },
72355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_72_CHECKER_TYPE,
72356  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_72_WIDTH },
72357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_73_CHECKER_TYPE,
72358  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_73_WIDTH },
72359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_74_CHECKER_TYPE,
72360  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_74_WIDTH },
72361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_75_CHECKER_TYPE,
72362  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_75_WIDTH },
72363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_76_CHECKER_TYPE,
72364  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_76_WIDTH },
72365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_77_CHECKER_TYPE,
72366  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_77_WIDTH },
72367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_78_CHECKER_TYPE,
72368  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_78_WIDTH },
72369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_79_CHECKER_TYPE,
72370  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_79_WIDTH },
72371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_80_CHECKER_TYPE,
72372  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_80_WIDTH },
72373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_81_CHECKER_TYPE,
72374  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_81_WIDTH },
72375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_82_CHECKER_TYPE,
72376  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_82_WIDTH },
72377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_83_CHECKER_TYPE,
72378  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_83_WIDTH },
72379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_84_CHECKER_TYPE,
72380  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_84_WIDTH },
72381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_85_CHECKER_TYPE,
72382  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_85_WIDTH },
72383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_86_CHECKER_TYPE,
72384  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_86_WIDTH },
72385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_87_CHECKER_TYPE,
72386  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_87_WIDTH },
72387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_88_CHECKER_TYPE,
72388  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_88_WIDTH },
72389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_89_CHECKER_TYPE,
72390  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_89_WIDTH },
72391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_90_CHECKER_TYPE,
72392  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_90_WIDTH },
72393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_91_CHECKER_TYPE,
72394  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_91_WIDTH },
72395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_92_CHECKER_TYPE,
72396  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_92_WIDTH },
72397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_93_CHECKER_TYPE,
72398  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_93_WIDTH },
72399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_94_CHECKER_TYPE,
72400  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_94_WIDTH },
72401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_95_CHECKER_TYPE,
72402  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_95_WIDTH },
72403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_96_CHECKER_TYPE,
72404  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_96_WIDTH },
72405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_97_CHECKER_TYPE,
72406  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_97_WIDTH },
72407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_98_CHECKER_TYPE,
72408  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_98_WIDTH },
72409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_99_CHECKER_TYPE,
72410  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_99_WIDTH },
72411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_100_CHECKER_TYPE,
72412  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_100_WIDTH },
72413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_101_CHECKER_TYPE,
72414  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_101_WIDTH },
72415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_102_CHECKER_TYPE,
72416  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_102_WIDTH },
72417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_103_CHECKER_TYPE,
72418  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_103_WIDTH },
72419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_104_CHECKER_TYPE,
72420  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_104_WIDTH },
72421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_105_CHECKER_TYPE,
72422  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_105_WIDTH },
72423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_106_CHECKER_TYPE,
72424  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_106_WIDTH },
72425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_107_CHECKER_TYPE,
72426  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_107_WIDTH },
72427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_108_CHECKER_TYPE,
72428  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_108_WIDTH },
72429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_109_CHECKER_TYPE,
72430  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_109_WIDTH },
72431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_110_CHECKER_TYPE,
72432  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_110_WIDTH },
72433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_111_CHECKER_TYPE,
72434  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_111_WIDTH },
72435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_112_CHECKER_TYPE,
72436  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_112_WIDTH },
72437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_113_CHECKER_TYPE,
72438  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_113_WIDTH },
72439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_114_CHECKER_TYPE,
72440  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_114_WIDTH },
72441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_115_CHECKER_TYPE,
72442  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_115_WIDTH },
72443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_116_CHECKER_TYPE,
72444  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_116_WIDTH },
72445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_117_CHECKER_TYPE,
72446  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_117_WIDTH },
72447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_118_CHECKER_TYPE,
72448  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_118_WIDTH },
72449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_119_CHECKER_TYPE,
72450  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_119_WIDTH },
72451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_120_CHECKER_TYPE,
72452  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_120_WIDTH },
72453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_121_CHECKER_TYPE,
72454  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_121_WIDTH },
72455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_122_CHECKER_TYPE,
72456  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_122_WIDTH },
72457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_123_CHECKER_TYPE,
72458  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_123_WIDTH },
72459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_124_CHECKER_TYPE,
72460  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_124_WIDTH },
72461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_125_CHECKER_TYPE,
72462  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_125_WIDTH },
72463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_126_CHECKER_TYPE,
72464  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_126_WIDTH },
72465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_127_CHECKER_TYPE,
72466  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_127_WIDTH },
72467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_128_CHECKER_TYPE,
72468  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_128_WIDTH },
72469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_129_CHECKER_TYPE,
72470  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_129_WIDTH },
72471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_130_CHECKER_TYPE,
72472  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_130_WIDTH },
72473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_131_CHECKER_TYPE,
72474  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_131_WIDTH },
72475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_132_CHECKER_TYPE,
72476  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_132_WIDTH },
72477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_133_CHECKER_TYPE,
72478  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_133_WIDTH },
72479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_134_CHECKER_TYPE,
72480  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_134_WIDTH },
72481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_135_CHECKER_TYPE,
72482  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_135_WIDTH },
72483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_136_CHECKER_TYPE,
72484  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_136_WIDTH },
72485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_137_CHECKER_TYPE,
72486  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_137_WIDTH },
72487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_138_CHECKER_TYPE,
72488  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_138_WIDTH },
72489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_139_CHECKER_TYPE,
72490  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_139_WIDTH },
72491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_140_CHECKER_TYPE,
72492  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_140_WIDTH },
72493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_141_CHECKER_TYPE,
72494  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_141_WIDTH },
72495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_142_CHECKER_TYPE,
72496  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_142_WIDTH },
72497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_143_CHECKER_TYPE,
72498  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_143_WIDTH },
72499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_144_CHECKER_TYPE,
72500  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_144_WIDTH },
72501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_145_CHECKER_TYPE,
72502  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_145_WIDTH },
72503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_146_CHECKER_TYPE,
72504  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_146_WIDTH },
72505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_147_CHECKER_TYPE,
72506  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_147_WIDTH },
72507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_148_CHECKER_TYPE,
72508  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_148_WIDTH },
72509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_149_CHECKER_TYPE,
72510  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_149_WIDTH },
72511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_150_CHECKER_TYPE,
72512  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_150_WIDTH },
72513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_151_CHECKER_TYPE,
72514  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_151_WIDTH },
72515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_152_CHECKER_TYPE,
72516  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_152_WIDTH },
72517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_153_CHECKER_TYPE,
72518  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_153_WIDTH },
72519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_154_CHECKER_TYPE,
72520  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_154_WIDTH },
72521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_155_CHECKER_TYPE,
72522  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_155_WIDTH },
72523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_156_CHECKER_TYPE,
72524  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_156_WIDTH },
72525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_157_CHECKER_TYPE,
72526  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_157_WIDTH },
72527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_158_CHECKER_TYPE,
72528  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_158_WIDTH },
72529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_159_CHECKER_TYPE,
72530  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_159_WIDTH },
72531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_160_CHECKER_TYPE,
72532  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_160_WIDTH },
72533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_161_CHECKER_TYPE,
72534  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_161_WIDTH },
72535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_162_CHECKER_TYPE,
72536  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_162_WIDTH },
72537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_163_CHECKER_TYPE,
72538  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_163_WIDTH },
72539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_164_CHECKER_TYPE,
72540  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_164_WIDTH },
72541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_165_CHECKER_TYPE,
72542  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_165_WIDTH },
72543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_166_CHECKER_TYPE,
72544  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_166_WIDTH },
72545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_167_CHECKER_TYPE,
72546  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_167_WIDTH },
72547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_168_CHECKER_TYPE,
72548  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_168_WIDTH },
72549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_169_CHECKER_TYPE,
72550  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_169_WIDTH },
72551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_170_CHECKER_TYPE,
72552  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_170_WIDTH },
72553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_171_CHECKER_TYPE,
72554  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_171_WIDTH },
72555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_172_CHECKER_TYPE,
72556  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_172_WIDTH },
72557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_173_CHECKER_TYPE,
72558  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_173_WIDTH },
72559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_174_CHECKER_TYPE,
72560  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_174_WIDTH },
72561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_175_CHECKER_TYPE,
72562  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_175_WIDTH },
72563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_176_CHECKER_TYPE,
72564  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_176_WIDTH },
72565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_177_CHECKER_TYPE,
72566  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_177_WIDTH },
72567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_178_CHECKER_TYPE,
72568  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_178_WIDTH },
72569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_179_CHECKER_TYPE,
72570  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_179_WIDTH },
72571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_180_CHECKER_TYPE,
72572  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_180_WIDTH },
72573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_181_CHECKER_TYPE,
72574  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_181_WIDTH },
72575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_182_CHECKER_TYPE,
72576  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_182_WIDTH },
72577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_183_CHECKER_TYPE,
72578  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_183_WIDTH },
72579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_184_CHECKER_TYPE,
72580  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_184_WIDTH },
72581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_185_CHECKER_TYPE,
72582  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_185_WIDTH },
72583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_186_CHECKER_TYPE,
72584  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_186_WIDTH },
72585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_187_CHECKER_TYPE,
72586  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_187_WIDTH },
72587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_188_CHECKER_TYPE,
72588  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_188_WIDTH },
72589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_189_CHECKER_TYPE,
72590  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_189_WIDTH },
72591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_190_CHECKER_TYPE,
72592  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_190_WIDTH },
72593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_191_CHECKER_TYPE,
72594  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_191_WIDTH },
72595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_192_CHECKER_TYPE,
72596  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_192_WIDTH },
72597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_193_CHECKER_TYPE,
72598  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_193_WIDTH },
72599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_194_CHECKER_TYPE,
72600  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_194_WIDTH },
72601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_195_CHECKER_TYPE,
72602  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_195_WIDTH },
72603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_196_CHECKER_TYPE,
72604  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_196_WIDTH },
72605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_197_CHECKER_TYPE,
72606  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_197_WIDTH },
72607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_198_CHECKER_TYPE,
72608  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_198_WIDTH },
72609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_199_CHECKER_TYPE,
72610  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_199_WIDTH },
72611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_200_CHECKER_TYPE,
72612  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_200_WIDTH },
72613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_201_CHECKER_TYPE,
72614  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_201_WIDTH },
72615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_202_CHECKER_TYPE,
72616  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_202_WIDTH },
72617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_203_CHECKER_TYPE,
72618  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_203_WIDTH },
72619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_204_CHECKER_TYPE,
72620  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_204_WIDTH },
72621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_205_CHECKER_TYPE,
72622  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_205_WIDTH },
72623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_206_CHECKER_TYPE,
72624  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_206_WIDTH },
72625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_207_CHECKER_TYPE,
72626  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_207_WIDTH },
72627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_208_CHECKER_TYPE,
72628  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_208_WIDTH },
72629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_209_CHECKER_TYPE,
72630  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_209_WIDTH },
72631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_210_CHECKER_TYPE,
72632  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_210_WIDTH },
72633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_211_CHECKER_TYPE,
72634  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_211_WIDTH },
72635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_212_CHECKER_TYPE,
72636  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_212_WIDTH },
72637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_213_CHECKER_TYPE,
72638  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_213_WIDTH },
72639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_214_CHECKER_TYPE,
72640  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_214_WIDTH },
72641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_215_CHECKER_TYPE,
72642  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_215_WIDTH },
72643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_216_CHECKER_TYPE,
72644  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_216_WIDTH },
72645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_217_CHECKER_TYPE,
72646  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_217_WIDTH },
72647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_218_CHECKER_TYPE,
72648  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_218_WIDTH },
72649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_219_CHECKER_TYPE,
72650  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_219_WIDTH },
72651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_220_CHECKER_TYPE,
72652  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_220_WIDTH },
72653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_221_CHECKER_TYPE,
72654  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_221_WIDTH },
72655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_222_CHECKER_TYPE,
72656  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_222_WIDTH },
72657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_223_CHECKER_TYPE,
72658  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_223_WIDTH },
72659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_224_CHECKER_TYPE,
72660  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_224_WIDTH },
72661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_225_CHECKER_TYPE,
72662  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_225_WIDTH },
72663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_226_CHECKER_TYPE,
72664  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_226_WIDTH },
72665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_227_CHECKER_TYPE,
72666  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_227_WIDTH },
72667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_228_CHECKER_TYPE,
72668  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_228_WIDTH },
72669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_229_CHECKER_TYPE,
72670  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_229_WIDTH },
72671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_230_CHECKER_TYPE,
72672  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_230_WIDTH },
72673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_231_CHECKER_TYPE,
72674  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_231_WIDTH },
72675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_232_CHECKER_TYPE,
72676  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_232_WIDTH },
72677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_233_CHECKER_TYPE,
72678  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_233_WIDTH },
72679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_234_CHECKER_TYPE,
72680  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_234_WIDTH },
72681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_235_CHECKER_TYPE,
72682  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_235_WIDTH },
72683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_236_CHECKER_TYPE,
72684  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_236_WIDTH },
72685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_237_CHECKER_TYPE,
72686  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_237_WIDTH },
72687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_238_CHECKER_TYPE,
72688  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_238_WIDTH },
72689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_239_CHECKER_TYPE,
72690  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_239_WIDTH },
72691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_240_CHECKER_TYPE,
72692  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_240_WIDTH },
72693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_241_CHECKER_TYPE,
72694  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_241_WIDTH },
72695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_242_CHECKER_TYPE,
72696  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_242_WIDTH },
72697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_243_CHECKER_TYPE,
72698  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_243_WIDTH },
72699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_244_CHECKER_TYPE,
72700  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_244_WIDTH },
72701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_245_CHECKER_TYPE,
72702  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_245_WIDTH },
72703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_246_CHECKER_TYPE,
72704  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_246_WIDTH },
72705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_247_CHECKER_TYPE,
72706  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_247_WIDTH },
72707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_248_CHECKER_TYPE,
72708  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_248_WIDTH },
72709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_249_CHECKER_TYPE,
72710  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_249_WIDTH },
72711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_250_CHECKER_TYPE,
72712  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_250_WIDTH },
72713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_251_CHECKER_TYPE,
72714  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_251_WIDTH },
72715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_252_CHECKER_TYPE,
72716  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_252_WIDTH },
72717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_253_CHECKER_TYPE,
72718  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_253_WIDTH },
72719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_254_CHECKER_TYPE,
72720  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_254_WIDTH },
72721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_255_CHECKER_TYPE,
72722  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_GROUP_255_WIDTH },
72723 };
72724 
72730 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS] =
72731 {
72732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_0_CHECKER_TYPE,
72733  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_0_WIDTH },
72734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_1_CHECKER_TYPE,
72735  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_1_WIDTH },
72736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_2_CHECKER_TYPE,
72737  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_2_WIDTH },
72738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_3_CHECKER_TYPE,
72739  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_3_WIDTH },
72740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_4_CHECKER_TYPE,
72741  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_4_WIDTH },
72742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_5_CHECKER_TYPE,
72743  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_5_WIDTH },
72744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_6_CHECKER_TYPE,
72745  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_6_WIDTH },
72746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_7_CHECKER_TYPE,
72747  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_7_WIDTH },
72748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_8_CHECKER_TYPE,
72749  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_8_WIDTH },
72750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_9_CHECKER_TYPE,
72751  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_9_WIDTH },
72752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_10_CHECKER_TYPE,
72753  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_10_WIDTH },
72754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_11_CHECKER_TYPE,
72755  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_11_WIDTH },
72756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_12_CHECKER_TYPE,
72757  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_12_WIDTH },
72758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_13_CHECKER_TYPE,
72759  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_13_WIDTH },
72760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_14_CHECKER_TYPE,
72761  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_14_WIDTH },
72762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_15_CHECKER_TYPE,
72763  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_15_WIDTH },
72764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_16_CHECKER_TYPE,
72765  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_16_WIDTH },
72766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_17_CHECKER_TYPE,
72767  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_17_WIDTH },
72768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_18_CHECKER_TYPE,
72769  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_18_WIDTH },
72770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_19_CHECKER_TYPE,
72771  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_19_WIDTH },
72772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_20_CHECKER_TYPE,
72773  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_20_WIDTH },
72774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_21_CHECKER_TYPE,
72775  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_21_WIDTH },
72776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_22_CHECKER_TYPE,
72777  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_22_WIDTH },
72778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_23_CHECKER_TYPE,
72779  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_23_WIDTH },
72780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_24_CHECKER_TYPE,
72781  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_24_WIDTH },
72782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_25_CHECKER_TYPE,
72783  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_25_WIDTH },
72784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_26_CHECKER_TYPE,
72785  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_26_WIDTH },
72786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_27_CHECKER_TYPE,
72787  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_27_WIDTH },
72788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_28_CHECKER_TYPE,
72789  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_28_WIDTH },
72790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_29_CHECKER_TYPE,
72791  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_29_WIDTH },
72792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_30_CHECKER_TYPE,
72793  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_30_WIDTH },
72794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_31_CHECKER_TYPE,
72795  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_31_WIDTH },
72796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_32_CHECKER_TYPE,
72797  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_32_WIDTH },
72798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_33_CHECKER_TYPE,
72799  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_33_WIDTH },
72800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_34_CHECKER_TYPE,
72801  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_34_WIDTH },
72802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_35_CHECKER_TYPE,
72803  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_35_WIDTH },
72804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_36_CHECKER_TYPE,
72805  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_36_WIDTH },
72806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_37_CHECKER_TYPE,
72807  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_37_WIDTH },
72808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_38_CHECKER_TYPE,
72809  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_38_WIDTH },
72810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_39_CHECKER_TYPE,
72811  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_39_WIDTH },
72812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_40_CHECKER_TYPE,
72813  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_40_WIDTH },
72814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_41_CHECKER_TYPE,
72815  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_41_WIDTH },
72816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_42_CHECKER_TYPE,
72817  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_42_WIDTH },
72818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_43_CHECKER_TYPE,
72819  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_43_WIDTH },
72820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_44_CHECKER_TYPE,
72821  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_44_WIDTH },
72822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_45_CHECKER_TYPE,
72823  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_45_WIDTH },
72824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_46_CHECKER_TYPE,
72825  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_46_WIDTH },
72826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_47_CHECKER_TYPE,
72827  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_47_WIDTH },
72828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_48_CHECKER_TYPE,
72829  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_48_WIDTH },
72830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_49_CHECKER_TYPE,
72831  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_49_WIDTH },
72832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_50_CHECKER_TYPE,
72833  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_50_WIDTH },
72834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_51_CHECKER_TYPE,
72835  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_51_WIDTH },
72836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_52_CHECKER_TYPE,
72837  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_52_WIDTH },
72838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_53_CHECKER_TYPE,
72839  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_53_WIDTH },
72840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_54_CHECKER_TYPE,
72841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_54_WIDTH },
72842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_55_CHECKER_TYPE,
72843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_55_WIDTH },
72844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_56_CHECKER_TYPE,
72845  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_56_WIDTH },
72846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_57_CHECKER_TYPE,
72847  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_57_WIDTH },
72848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_58_CHECKER_TYPE,
72849  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_58_WIDTH },
72850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_59_CHECKER_TYPE,
72851  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_59_WIDTH },
72852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_60_CHECKER_TYPE,
72853  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_60_WIDTH },
72854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_61_CHECKER_TYPE,
72855  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_61_WIDTH },
72856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_62_CHECKER_TYPE,
72857  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_62_WIDTH },
72858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_63_CHECKER_TYPE,
72859  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_63_WIDTH },
72860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_64_CHECKER_TYPE,
72861  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_64_WIDTH },
72862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_65_CHECKER_TYPE,
72863  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_65_WIDTH },
72864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_66_CHECKER_TYPE,
72865  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_66_WIDTH },
72866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_67_CHECKER_TYPE,
72867  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_67_WIDTH },
72868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_68_CHECKER_TYPE,
72869  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_68_WIDTH },
72870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_69_CHECKER_TYPE,
72871  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_69_WIDTH },
72872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_70_CHECKER_TYPE,
72873  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_70_WIDTH },
72874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_71_CHECKER_TYPE,
72875  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_71_WIDTH },
72876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_72_CHECKER_TYPE,
72877  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_72_WIDTH },
72878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_73_CHECKER_TYPE,
72879  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_73_WIDTH },
72880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_74_CHECKER_TYPE,
72881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_74_WIDTH },
72882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_75_CHECKER_TYPE,
72883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_75_WIDTH },
72884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_76_CHECKER_TYPE,
72885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_76_WIDTH },
72886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_77_CHECKER_TYPE,
72887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_77_WIDTH },
72888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_78_CHECKER_TYPE,
72889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_78_WIDTH },
72890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_79_CHECKER_TYPE,
72891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_79_WIDTH },
72892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_80_CHECKER_TYPE,
72893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_80_WIDTH },
72894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_81_CHECKER_TYPE,
72895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_81_WIDTH },
72896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_82_CHECKER_TYPE,
72897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_82_WIDTH },
72898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_83_CHECKER_TYPE,
72899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_83_WIDTH },
72900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_84_CHECKER_TYPE,
72901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_84_WIDTH },
72902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_85_CHECKER_TYPE,
72903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_85_WIDTH },
72904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_86_CHECKER_TYPE,
72905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_86_WIDTH },
72906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_87_CHECKER_TYPE,
72907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_87_WIDTH },
72908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_88_CHECKER_TYPE,
72909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_88_WIDTH },
72910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_89_CHECKER_TYPE,
72911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_89_WIDTH },
72912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_90_CHECKER_TYPE,
72913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_90_WIDTH },
72914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_91_CHECKER_TYPE,
72915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_91_WIDTH },
72916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_92_CHECKER_TYPE,
72917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_92_WIDTH },
72918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_93_CHECKER_TYPE,
72919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_93_WIDTH },
72920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_94_CHECKER_TYPE,
72921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_94_WIDTH },
72922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_95_CHECKER_TYPE,
72923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_95_WIDTH },
72924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_96_CHECKER_TYPE,
72925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_96_WIDTH },
72926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_97_CHECKER_TYPE,
72927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_97_WIDTH },
72928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_98_CHECKER_TYPE,
72929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_98_WIDTH },
72930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_99_CHECKER_TYPE,
72931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_99_WIDTH },
72932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_100_CHECKER_TYPE,
72933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_100_WIDTH },
72934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_101_CHECKER_TYPE,
72935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_101_WIDTH },
72936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_102_CHECKER_TYPE,
72937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_102_WIDTH },
72938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_103_CHECKER_TYPE,
72939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_103_WIDTH },
72940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_104_CHECKER_TYPE,
72941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_104_WIDTH },
72942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_105_CHECKER_TYPE,
72943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_105_WIDTH },
72944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_106_CHECKER_TYPE,
72945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_106_WIDTH },
72946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_107_CHECKER_TYPE,
72947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_107_WIDTH },
72948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_108_CHECKER_TYPE,
72949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_108_WIDTH },
72950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_109_CHECKER_TYPE,
72951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_109_WIDTH },
72952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_110_CHECKER_TYPE,
72953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_110_WIDTH },
72954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_111_CHECKER_TYPE,
72955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_111_WIDTH },
72956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_112_CHECKER_TYPE,
72957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_112_WIDTH },
72958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_113_CHECKER_TYPE,
72959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_113_WIDTH },
72960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_114_CHECKER_TYPE,
72961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_114_WIDTH },
72962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_115_CHECKER_TYPE,
72963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_115_WIDTH },
72964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_116_CHECKER_TYPE,
72965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_116_WIDTH },
72966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_117_CHECKER_TYPE,
72967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_117_WIDTH },
72968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_118_CHECKER_TYPE,
72969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_118_WIDTH },
72970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_119_CHECKER_TYPE,
72971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_119_WIDTH },
72972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_120_CHECKER_TYPE,
72973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_120_WIDTH },
72974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_121_CHECKER_TYPE,
72975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_121_WIDTH },
72976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_122_CHECKER_TYPE,
72977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_122_WIDTH },
72978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_123_CHECKER_TYPE,
72979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_123_WIDTH },
72980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_124_CHECKER_TYPE,
72981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_124_WIDTH },
72982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_125_CHECKER_TYPE,
72983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_125_WIDTH },
72984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_126_CHECKER_TYPE,
72985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_126_WIDTH },
72986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_127_CHECKER_TYPE,
72987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_127_WIDTH },
72988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_128_CHECKER_TYPE,
72989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_128_WIDTH },
72990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_129_CHECKER_TYPE,
72991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_129_WIDTH },
72992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_130_CHECKER_TYPE,
72993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_130_WIDTH },
72994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_131_CHECKER_TYPE,
72995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_131_WIDTH },
72996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_132_CHECKER_TYPE,
72997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_132_WIDTH },
72998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_133_CHECKER_TYPE,
72999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_133_WIDTH },
73000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_134_CHECKER_TYPE,
73001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_134_WIDTH },
73002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_135_CHECKER_TYPE,
73003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_135_WIDTH },
73004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_136_CHECKER_TYPE,
73005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_136_WIDTH },
73006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_137_CHECKER_TYPE,
73007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_137_WIDTH },
73008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_138_CHECKER_TYPE,
73009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_138_WIDTH },
73010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_139_CHECKER_TYPE,
73011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_139_WIDTH },
73012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_140_CHECKER_TYPE,
73013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_140_WIDTH },
73014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_141_CHECKER_TYPE,
73015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_141_WIDTH },
73016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_142_CHECKER_TYPE,
73017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_142_WIDTH },
73018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_143_CHECKER_TYPE,
73019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_143_WIDTH },
73020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_144_CHECKER_TYPE,
73021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_144_WIDTH },
73022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_145_CHECKER_TYPE,
73023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_145_WIDTH },
73024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_146_CHECKER_TYPE,
73025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_146_WIDTH },
73026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_147_CHECKER_TYPE,
73027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_147_WIDTH },
73028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_148_CHECKER_TYPE,
73029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_148_WIDTH },
73030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_149_CHECKER_TYPE,
73031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_149_WIDTH },
73032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_150_CHECKER_TYPE,
73033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_150_WIDTH },
73034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_151_CHECKER_TYPE,
73035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_151_WIDTH },
73036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_152_CHECKER_TYPE,
73037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_152_WIDTH },
73038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_153_CHECKER_TYPE,
73039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_153_WIDTH },
73040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_154_CHECKER_TYPE,
73041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_154_WIDTH },
73042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_155_CHECKER_TYPE,
73043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_155_WIDTH },
73044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_156_CHECKER_TYPE,
73045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_156_WIDTH },
73046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_157_CHECKER_TYPE,
73047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_157_WIDTH },
73048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_158_CHECKER_TYPE,
73049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_158_WIDTH },
73050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_159_CHECKER_TYPE,
73051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_159_WIDTH },
73052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_160_CHECKER_TYPE,
73053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_160_WIDTH },
73054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_161_CHECKER_TYPE,
73055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_161_WIDTH },
73056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_162_CHECKER_TYPE,
73057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_162_WIDTH },
73058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_163_CHECKER_TYPE,
73059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_163_WIDTH },
73060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_164_CHECKER_TYPE,
73061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_164_WIDTH },
73062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_165_CHECKER_TYPE,
73063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_165_WIDTH },
73064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_166_CHECKER_TYPE,
73065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_166_WIDTH },
73066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_167_CHECKER_TYPE,
73067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_167_WIDTH },
73068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_168_CHECKER_TYPE,
73069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_168_WIDTH },
73070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_169_CHECKER_TYPE,
73071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_169_WIDTH },
73072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_170_CHECKER_TYPE,
73073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_170_WIDTH },
73074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_171_CHECKER_TYPE,
73075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_171_WIDTH },
73076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_172_CHECKER_TYPE,
73077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_172_WIDTH },
73078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_173_CHECKER_TYPE,
73079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_173_WIDTH },
73080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_174_CHECKER_TYPE,
73081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_174_WIDTH },
73082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_175_CHECKER_TYPE,
73083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_175_WIDTH },
73084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_176_CHECKER_TYPE,
73085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_176_WIDTH },
73086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_177_CHECKER_TYPE,
73087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_177_WIDTH },
73088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_178_CHECKER_TYPE,
73089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_178_WIDTH },
73090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_179_CHECKER_TYPE,
73091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_179_WIDTH },
73092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_180_CHECKER_TYPE,
73093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_180_WIDTH },
73094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_181_CHECKER_TYPE,
73095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_181_WIDTH },
73096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_182_CHECKER_TYPE,
73097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_182_WIDTH },
73098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_183_CHECKER_TYPE,
73099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_183_WIDTH },
73100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_184_CHECKER_TYPE,
73101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_184_WIDTH },
73102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_185_CHECKER_TYPE,
73103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_185_WIDTH },
73104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_186_CHECKER_TYPE,
73105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_186_WIDTH },
73106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_187_CHECKER_TYPE,
73107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_187_WIDTH },
73108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_188_CHECKER_TYPE,
73109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_188_WIDTH },
73110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_189_CHECKER_TYPE,
73111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_189_WIDTH },
73112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_190_CHECKER_TYPE,
73113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_190_WIDTH },
73114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_191_CHECKER_TYPE,
73115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_191_WIDTH },
73116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_192_CHECKER_TYPE,
73117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_192_WIDTH },
73118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_193_CHECKER_TYPE,
73119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_193_WIDTH },
73120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_194_CHECKER_TYPE,
73121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_194_WIDTH },
73122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_195_CHECKER_TYPE,
73123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_195_WIDTH },
73124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_196_CHECKER_TYPE,
73125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_196_WIDTH },
73126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_197_CHECKER_TYPE,
73127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_197_WIDTH },
73128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_198_CHECKER_TYPE,
73129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_198_WIDTH },
73130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_199_CHECKER_TYPE,
73131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_199_WIDTH },
73132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_200_CHECKER_TYPE,
73133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_200_WIDTH },
73134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_201_CHECKER_TYPE,
73135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_201_WIDTH },
73136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_202_CHECKER_TYPE,
73137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_202_WIDTH },
73138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_203_CHECKER_TYPE,
73139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_203_WIDTH },
73140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_204_CHECKER_TYPE,
73141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_204_WIDTH },
73142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_205_CHECKER_TYPE,
73143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_205_WIDTH },
73144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_206_CHECKER_TYPE,
73145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_206_WIDTH },
73146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_207_CHECKER_TYPE,
73147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_207_WIDTH },
73148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_208_CHECKER_TYPE,
73149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_208_WIDTH },
73150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_209_CHECKER_TYPE,
73151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_209_WIDTH },
73152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_210_CHECKER_TYPE,
73153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_210_WIDTH },
73154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_211_CHECKER_TYPE,
73155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_211_WIDTH },
73156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_212_CHECKER_TYPE,
73157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_212_WIDTH },
73158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_213_CHECKER_TYPE,
73159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_213_WIDTH },
73160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_214_CHECKER_TYPE,
73161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_214_WIDTH },
73162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_215_CHECKER_TYPE,
73163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_215_WIDTH },
73164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_216_CHECKER_TYPE,
73165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_216_WIDTH },
73166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_217_CHECKER_TYPE,
73167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_217_WIDTH },
73168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_218_CHECKER_TYPE,
73169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_218_WIDTH },
73170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_219_CHECKER_TYPE,
73171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_219_WIDTH },
73172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_220_CHECKER_TYPE,
73173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_220_WIDTH },
73174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_221_CHECKER_TYPE,
73175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_221_WIDTH },
73176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_222_CHECKER_TYPE,
73177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_222_WIDTH },
73178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_223_CHECKER_TYPE,
73179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_223_WIDTH },
73180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_224_CHECKER_TYPE,
73181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_224_WIDTH },
73182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_225_CHECKER_TYPE,
73183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_225_WIDTH },
73184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_226_CHECKER_TYPE,
73185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_226_WIDTH },
73186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_227_CHECKER_TYPE,
73187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_227_WIDTH },
73188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_228_CHECKER_TYPE,
73189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_228_WIDTH },
73190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_229_CHECKER_TYPE,
73191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_229_WIDTH },
73192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_230_CHECKER_TYPE,
73193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_230_WIDTH },
73194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_231_CHECKER_TYPE,
73195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_231_WIDTH },
73196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_232_CHECKER_TYPE,
73197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_232_WIDTH },
73198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_233_CHECKER_TYPE,
73199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_233_WIDTH },
73200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_234_CHECKER_TYPE,
73201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_234_WIDTH },
73202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_235_CHECKER_TYPE,
73203  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_235_WIDTH },
73204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_236_CHECKER_TYPE,
73205  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_236_WIDTH },
73206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_237_CHECKER_TYPE,
73207  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_237_WIDTH },
73208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_238_CHECKER_TYPE,
73209  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_238_WIDTH },
73210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_239_CHECKER_TYPE,
73211  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_239_WIDTH },
73212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_240_CHECKER_TYPE,
73213  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_240_WIDTH },
73214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_241_CHECKER_TYPE,
73215  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_241_WIDTH },
73216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_242_CHECKER_TYPE,
73217  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_242_WIDTH },
73218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_243_CHECKER_TYPE,
73219  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_243_WIDTH },
73220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_244_CHECKER_TYPE,
73221  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_244_WIDTH },
73222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_245_CHECKER_TYPE,
73223  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_245_WIDTH },
73224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_246_CHECKER_TYPE,
73225  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_246_WIDTH },
73226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_247_CHECKER_TYPE,
73227  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_247_WIDTH },
73228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_248_CHECKER_TYPE,
73229  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_248_WIDTH },
73230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_249_CHECKER_TYPE,
73231  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_249_WIDTH },
73232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_250_CHECKER_TYPE,
73233  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_250_WIDTH },
73234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_251_CHECKER_TYPE,
73235  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_251_WIDTH },
73236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_252_CHECKER_TYPE,
73237  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_252_WIDTH },
73238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_253_CHECKER_TYPE,
73239  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_253_WIDTH },
73240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_254_CHECKER_TYPE,
73241  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_254_WIDTH },
73242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_255_CHECKER_TYPE,
73243  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_GROUP_255_WIDTH },
73244 };
73245 
73251 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS] =
73252 {
73253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_0_CHECKER_TYPE,
73254  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_0_WIDTH },
73255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_1_CHECKER_TYPE,
73256  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_1_WIDTH },
73257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_2_CHECKER_TYPE,
73258  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_2_WIDTH },
73259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_3_CHECKER_TYPE,
73260  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_3_WIDTH },
73261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_4_CHECKER_TYPE,
73262  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_4_WIDTH },
73263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_5_CHECKER_TYPE,
73264  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_5_WIDTH },
73265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_6_CHECKER_TYPE,
73266  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_6_WIDTH },
73267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_7_CHECKER_TYPE,
73268  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_7_WIDTH },
73269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_8_CHECKER_TYPE,
73270  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_8_WIDTH },
73271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_9_CHECKER_TYPE,
73272  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_9_WIDTH },
73273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_10_CHECKER_TYPE,
73274  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_10_WIDTH },
73275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_11_CHECKER_TYPE,
73276  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_11_WIDTH },
73277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_12_CHECKER_TYPE,
73278  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_12_WIDTH },
73279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_13_CHECKER_TYPE,
73280  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_13_WIDTH },
73281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_14_CHECKER_TYPE,
73282  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_14_WIDTH },
73283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_15_CHECKER_TYPE,
73284  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_15_WIDTH },
73285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_16_CHECKER_TYPE,
73286  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_16_WIDTH },
73287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_17_CHECKER_TYPE,
73288  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_17_WIDTH },
73289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_18_CHECKER_TYPE,
73290  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_18_WIDTH },
73291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_19_CHECKER_TYPE,
73292  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_19_WIDTH },
73293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_20_CHECKER_TYPE,
73294  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_20_WIDTH },
73295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_21_CHECKER_TYPE,
73296  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_21_WIDTH },
73297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_22_CHECKER_TYPE,
73298  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_22_WIDTH },
73299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_23_CHECKER_TYPE,
73300  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_23_WIDTH },
73301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_24_CHECKER_TYPE,
73302  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_24_WIDTH },
73303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_25_CHECKER_TYPE,
73304  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_25_WIDTH },
73305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_26_CHECKER_TYPE,
73306  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_26_WIDTH },
73307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_27_CHECKER_TYPE,
73308  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_27_WIDTH },
73309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_28_CHECKER_TYPE,
73310  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_28_WIDTH },
73311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_29_CHECKER_TYPE,
73312  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_29_WIDTH },
73313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_30_CHECKER_TYPE,
73314  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_30_WIDTH },
73315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_31_CHECKER_TYPE,
73316  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_31_WIDTH },
73317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_32_CHECKER_TYPE,
73318  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_32_WIDTH },
73319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_33_CHECKER_TYPE,
73320  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_33_WIDTH },
73321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_34_CHECKER_TYPE,
73322  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_34_WIDTH },
73323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_35_CHECKER_TYPE,
73324  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_35_WIDTH },
73325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_36_CHECKER_TYPE,
73326  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_36_WIDTH },
73327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_37_CHECKER_TYPE,
73328  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_37_WIDTH },
73329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_38_CHECKER_TYPE,
73330  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_38_WIDTH },
73331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_39_CHECKER_TYPE,
73332  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_39_WIDTH },
73333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_40_CHECKER_TYPE,
73334  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_40_WIDTH },
73335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_41_CHECKER_TYPE,
73336  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_41_WIDTH },
73337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_42_CHECKER_TYPE,
73338  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_42_WIDTH },
73339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_43_CHECKER_TYPE,
73340  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_43_WIDTH },
73341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_44_CHECKER_TYPE,
73342  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_44_WIDTH },
73343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_45_CHECKER_TYPE,
73344  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_45_WIDTH },
73345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_46_CHECKER_TYPE,
73346  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_46_WIDTH },
73347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_47_CHECKER_TYPE,
73348  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_47_WIDTH },
73349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_48_CHECKER_TYPE,
73350  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_48_WIDTH },
73351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_49_CHECKER_TYPE,
73352  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_49_WIDTH },
73353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_50_CHECKER_TYPE,
73354  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_50_WIDTH },
73355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_51_CHECKER_TYPE,
73356  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_51_WIDTH },
73357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_52_CHECKER_TYPE,
73358  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_52_WIDTH },
73359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_53_CHECKER_TYPE,
73360  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_53_WIDTH },
73361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_54_CHECKER_TYPE,
73362  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_54_WIDTH },
73363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_55_CHECKER_TYPE,
73364  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_55_WIDTH },
73365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_56_CHECKER_TYPE,
73366  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_56_WIDTH },
73367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_57_CHECKER_TYPE,
73368  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_57_WIDTH },
73369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_58_CHECKER_TYPE,
73370  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_58_WIDTH },
73371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_59_CHECKER_TYPE,
73372  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_59_WIDTH },
73373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_60_CHECKER_TYPE,
73374  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_60_WIDTH },
73375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_61_CHECKER_TYPE,
73376  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_61_WIDTH },
73377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_62_CHECKER_TYPE,
73378  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_62_WIDTH },
73379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_63_CHECKER_TYPE,
73380  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_63_WIDTH },
73381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_64_CHECKER_TYPE,
73382  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_64_WIDTH },
73383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_65_CHECKER_TYPE,
73384  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_65_WIDTH },
73385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_66_CHECKER_TYPE,
73386  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_66_WIDTH },
73387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_67_CHECKER_TYPE,
73388  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_67_WIDTH },
73389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_68_CHECKER_TYPE,
73390  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_68_WIDTH },
73391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_69_CHECKER_TYPE,
73392  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_69_WIDTH },
73393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_70_CHECKER_TYPE,
73394  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_70_WIDTH },
73395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_71_CHECKER_TYPE,
73396  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_71_WIDTH },
73397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_72_CHECKER_TYPE,
73398  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_72_WIDTH },
73399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_73_CHECKER_TYPE,
73400  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_73_WIDTH },
73401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_74_CHECKER_TYPE,
73402  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_74_WIDTH },
73403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_75_CHECKER_TYPE,
73404  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_75_WIDTH },
73405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_76_CHECKER_TYPE,
73406  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_76_WIDTH },
73407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_77_CHECKER_TYPE,
73408  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_77_WIDTH },
73409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_78_CHECKER_TYPE,
73410  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_78_WIDTH },
73411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_79_CHECKER_TYPE,
73412  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_79_WIDTH },
73413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_80_CHECKER_TYPE,
73414  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_80_WIDTH },
73415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_81_CHECKER_TYPE,
73416  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_81_WIDTH },
73417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_82_CHECKER_TYPE,
73418  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_82_WIDTH },
73419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_83_CHECKER_TYPE,
73420  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_83_WIDTH },
73421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_84_CHECKER_TYPE,
73422  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_84_WIDTH },
73423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_85_CHECKER_TYPE,
73424  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_85_WIDTH },
73425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_86_CHECKER_TYPE,
73426  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_86_WIDTH },
73427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_87_CHECKER_TYPE,
73428  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_87_WIDTH },
73429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_88_CHECKER_TYPE,
73430  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_88_WIDTH },
73431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_89_CHECKER_TYPE,
73432  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_89_WIDTH },
73433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_90_CHECKER_TYPE,
73434  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_90_WIDTH },
73435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_91_CHECKER_TYPE,
73436  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_91_WIDTH },
73437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_92_CHECKER_TYPE,
73438  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_92_WIDTH },
73439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_93_CHECKER_TYPE,
73440  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_93_WIDTH },
73441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_94_CHECKER_TYPE,
73442  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_94_WIDTH },
73443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_95_CHECKER_TYPE,
73444  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_95_WIDTH },
73445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_96_CHECKER_TYPE,
73446  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_96_WIDTH },
73447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_97_CHECKER_TYPE,
73448  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_97_WIDTH },
73449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_98_CHECKER_TYPE,
73450  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_98_WIDTH },
73451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_99_CHECKER_TYPE,
73452  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_99_WIDTH },
73453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_100_CHECKER_TYPE,
73454  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_100_WIDTH },
73455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_101_CHECKER_TYPE,
73456  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_101_WIDTH },
73457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_102_CHECKER_TYPE,
73458  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_102_WIDTH },
73459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_103_CHECKER_TYPE,
73460  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_103_WIDTH },
73461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_104_CHECKER_TYPE,
73462  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_104_WIDTH },
73463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_105_CHECKER_TYPE,
73464  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_105_WIDTH },
73465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_106_CHECKER_TYPE,
73466  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_106_WIDTH },
73467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_107_CHECKER_TYPE,
73468  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_107_WIDTH },
73469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_108_CHECKER_TYPE,
73470  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_108_WIDTH },
73471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_109_CHECKER_TYPE,
73472  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_109_WIDTH },
73473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_110_CHECKER_TYPE,
73474  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_110_WIDTH },
73475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_111_CHECKER_TYPE,
73476  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_111_WIDTH },
73477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_112_CHECKER_TYPE,
73478  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_112_WIDTH },
73479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_113_CHECKER_TYPE,
73480  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_113_WIDTH },
73481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_114_CHECKER_TYPE,
73482  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_114_WIDTH },
73483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_115_CHECKER_TYPE,
73484  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_115_WIDTH },
73485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_116_CHECKER_TYPE,
73486  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_116_WIDTH },
73487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_117_CHECKER_TYPE,
73488  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_117_WIDTH },
73489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_118_CHECKER_TYPE,
73490  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_118_WIDTH },
73491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_119_CHECKER_TYPE,
73492  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_119_WIDTH },
73493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_120_CHECKER_TYPE,
73494  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_120_WIDTH },
73495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_121_CHECKER_TYPE,
73496  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_121_WIDTH },
73497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_122_CHECKER_TYPE,
73498  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_122_WIDTH },
73499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_123_CHECKER_TYPE,
73500  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_123_WIDTH },
73501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_124_CHECKER_TYPE,
73502  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_124_WIDTH },
73503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_125_CHECKER_TYPE,
73504  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_125_WIDTH },
73505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_126_CHECKER_TYPE,
73506  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_126_WIDTH },
73507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_127_CHECKER_TYPE,
73508  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_127_WIDTH },
73509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_128_CHECKER_TYPE,
73510  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_128_WIDTH },
73511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_129_CHECKER_TYPE,
73512  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_129_WIDTH },
73513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_130_CHECKER_TYPE,
73514  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_130_WIDTH },
73515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_131_CHECKER_TYPE,
73516  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_131_WIDTH },
73517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_132_CHECKER_TYPE,
73518  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_132_WIDTH },
73519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_133_CHECKER_TYPE,
73520  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_133_WIDTH },
73521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_134_CHECKER_TYPE,
73522  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_134_WIDTH },
73523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_135_CHECKER_TYPE,
73524  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_135_WIDTH },
73525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_136_CHECKER_TYPE,
73526  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_136_WIDTH },
73527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_137_CHECKER_TYPE,
73528  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_137_WIDTH },
73529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_138_CHECKER_TYPE,
73530  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_138_WIDTH },
73531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_139_CHECKER_TYPE,
73532  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_139_WIDTH },
73533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_140_CHECKER_TYPE,
73534  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_140_WIDTH },
73535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_141_CHECKER_TYPE,
73536  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_141_WIDTH },
73537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_142_CHECKER_TYPE,
73538  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_142_WIDTH },
73539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_143_CHECKER_TYPE,
73540  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_143_WIDTH },
73541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_144_CHECKER_TYPE,
73542  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_144_WIDTH },
73543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_145_CHECKER_TYPE,
73544  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_145_WIDTH },
73545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_146_CHECKER_TYPE,
73546  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_146_WIDTH },
73547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_147_CHECKER_TYPE,
73548  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_147_WIDTH },
73549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_148_CHECKER_TYPE,
73550  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_148_WIDTH },
73551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_149_CHECKER_TYPE,
73552  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_149_WIDTH },
73553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_150_CHECKER_TYPE,
73554  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_150_WIDTH },
73555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_151_CHECKER_TYPE,
73556  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_151_WIDTH },
73557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_152_CHECKER_TYPE,
73558  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_152_WIDTH },
73559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_153_CHECKER_TYPE,
73560  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_153_WIDTH },
73561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_154_CHECKER_TYPE,
73562  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_154_WIDTH },
73563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_155_CHECKER_TYPE,
73564  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_155_WIDTH },
73565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_156_CHECKER_TYPE,
73566  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_156_WIDTH },
73567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_157_CHECKER_TYPE,
73568  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_157_WIDTH },
73569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_158_CHECKER_TYPE,
73570  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_158_WIDTH },
73571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_159_CHECKER_TYPE,
73572  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_159_WIDTH },
73573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_160_CHECKER_TYPE,
73574  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_160_WIDTH },
73575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_161_CHECKER_TYPE,
73576  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_161_WIDTH },
73577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_162_CHECKER_TYPE,
73578  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_162_WIDTH },
73579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_163_CHECKER_TYPE,
73580  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_163_WIDTH },
73581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_164_CHECKER_TYPE,
73582  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_164_WIDTH },
73583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_165_CHECKER_TYPE,
73584  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_165_WIDTH },
73585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_166_CHECKER_TYPE,
73586  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_166_WIDTH },
73587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_167_CHECKER_TYPE,
73588  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_167_WIDTH },
73589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_168_CHECKER_TYPE,
73590  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_168_WIDTH },
73591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_169_CHECKER_TYPE,
73592  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_169_WIDTH },
73593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_170_CHECKER_TYPE,
73594  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_170_WIDTH },
73595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_171_CHECKER_TYPE,
73596  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_171_WIDTH },
73597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_172_CHECKER_TYPE,
73598  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_172_WIDTH },
73599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_173_CHECKER_TYPE,
73600  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_173_WIDTH },
73601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_174_CHECKER_TYPE,
73602  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_174_WIDTH },
73603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_175_CHECKER_TYPE,
73604  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_175_WIDTH },
73605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_176_CHECKER_TYPE,
73606  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_176_WIDTH },
73607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_177_CHECKER_TYPE,
73608  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_177_WIDTH },
73609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_178_CHECKER_TYPE,
73610  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_178_WIDTH },
73611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_179_CHECKER_TYPE,
73612  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_179_WIDTH },
73613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_180_CHECKER_TYPE,
73614  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_180_WIDTH },
73615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_181_CHECKER_TYPE,
73616  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_181_WIDTH },
73617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_182_CHECKER_TYPE,
73618  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_182_WIDTH },
73619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_183_CHECKER_TYPE,
73620  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_183_WIDTH },
73621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_184_CHECKER_TYPE,
73622  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_184_WIDTH },
73623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_185_CHECKER_TYPE,
73624  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_185_WIDTH },
73625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_186_CHECKER_TYPE,
73626  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_186_WIDTH },
73627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_187_CHECKER_TYPE,
73628  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_187_WIDTH },
73629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_188_CHECKER_TYPE,
73630  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_188_WIDTH },
73631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_189_CHECKER_TYPE,
73632  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_189_WIDTH },
73633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_190_CHECKER_TYPE,
73634  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_190_WIDTH },
73635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_191_CHECKER_TYPE,
73636  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_191_WIDTH },
73637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_192_CHECKER_TYPE,
73638  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_192_WIDTH },
73639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_193_CHECKER_TYPE,
73640  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_193_WIDTH },
73641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_194_CHECKER_TYPE,
73642  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_194_WIDTH },
73643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_195_CHECKER_TYPE,
73644  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_195_WIDTH },
73645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_196_CHECKER_TYPE,
73646  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_196_WIDTH },
73647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_197_CHECKER_TYPE,
73648  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_197_WIDTH },
73649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_198_CHECKER_TYPE,
73650  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_198_WIDTH },
73651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_199_CHECKER_TYPE,
73652  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_199_WIDTH },
73653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_200_CHECKER_TYPE,
73654  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_200_WIDTH },
73655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_201_CHECKER_TYPE,
73656  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_201_WIDTH },
73657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_202_CHECKER_TYPE,
73658  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_202_WIDTH },
73659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_203_CHECKER_TYPE,
73660  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_203_WIDTH },
73661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_204_CHECKER_TYPE,
73662  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_204_WIDTH },
73663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_205_CHECKER_TYPE,
73664  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_205_WIDTH },
73665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_206_CHECKER_TYPE,
73666  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_206_WIDTH },
73667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_207_CHECKER_TYPE,
73668  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_207_WIDTH },
73669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_208_CHECKER_TYPE,
73670  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_208_WIDTH },
73671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_209_CHECKER_TYPE,
73672  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_209_WIDTH },
73673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_210_CHECKER_TYPE,
73674  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_210_WIDTH },
73675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_211_CHECKER_TYPE,
73676  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_211_WIDTH },
73677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_212_CHECKER_TYPE,
73678  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_212_WIDTH },
73679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_213_CHECKER_TYPE,
73680  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_213_WIDTH },
73681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_214_CHECKER_TYPE,
73682  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_214_WIDTH },
73683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_215_CHECKER_TYPE,
73684  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_215_WIDTH },
73685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_216_CHECKER_TYPE,
73686  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_216_WIDTH },
73687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_217_CHECKER_TYPE,
73688  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_217_WIDTH },
73689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_218_CHECKER_TYPE,
73690  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_218_WIDTH },
73691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_219_CHECKER_TYPE,
73692  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_219_WIDTH },
73693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_220_CHECKER_TYPE,
73694  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_220_WIDTH },
73695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_221_CHECKER_TYPE,
73696  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_221_WIDTH },
73697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_222_CHECKER_TYPE,
73698  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_222_WIDTH },
73699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_223_CHECKER_TYPE,
73700  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_223_WIDTH },
73701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_224_CHECKER_TYPE,
73702  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_224_WIDTH },
73703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_225_CHECKER_TYPE,
73704  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_225_WIDTH },
73705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_226_CHECKER_TYPE,
73706  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_226_WIDTH },
73707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_227_CHECKER_TYPE,
73708  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_227_WIDTH },
73709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_228_CHECKER_TYPE,
73710  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_228_WIDTH },
73711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_229_CHECKER_TYPE,
73712  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_229_WIDTH },
73713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_230_CHECKER_TYPE,
73714  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_230_WIDTH },
73715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_231_CHECKER_TYPE,
73716  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_231_WIDTH },
73717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_232_CHECKER_TYPE,
73718  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_232_WIDTH },
73719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_233_CHECKER_TYPE,
73720  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_233_WIDTH },
73721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_234_CHECKER_TYPE,
73722  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_234_WIDTH },
73723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_235_CHECKER_TYPE,
73724  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_235_WIDTH },
73725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_236_CHECKER_TYPE,
73726  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_236_WIDTH },
73727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_237_CHECKER_TYPE,
73728  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_237_WIDTH },
73729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_238_CHECKER_TYPE,
73730  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_238_WIDTH },
73731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_239_CHECKER_TYPE,
73732  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_239_WIDTH },
73733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_240_CHECKER_TYPE,
73734  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_240_WIDTH },
73735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_241_CHECKER_TYPE,
73736  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_241_WIDTH },
73737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_242_CHECKER_TYPE,
73738  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_242_WIDTH },
73739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_243_CHECKER_TYPE,
73740  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_243_WIDTH },
73741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_244_CHECKER_TYPE,
73742  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_244_WIDTH },
73743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_245_CHECKER_TYPE,
73744  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_245_WIDTH },
73745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_246_CHECKER_TYPE,
73746  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_246_WIDTH },
73747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_247_CHECKER_TYPE,
73748  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_247_WIDTH },
73749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_248_CHECKER_TYPE,
73750  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_248_WIDTH },
73751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_249_CHECKER_TYPE,
73752  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_249_WIDTH },
73753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_250_CHECKER_TYPE,
73754  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_250_WIDTH },
73755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_251_CHECKER_TYPE,
73756  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_251_WIDTH },
73757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_252_CHECKER_TYPE,
73758  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_252_WIDTH },
73759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_253_CHECKER_TYPE,
73760  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_253_WIDTH },
73761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_254_CHECKER_TYPE,
73762  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_254_WIDTH },
73763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_255_CHECKER_TYPE,
73764  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_GROUP_255_WIDTH },
73765 };
73766 
73772 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS] =
73773 {
73774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_0_CHECKER_TYPE,
73775  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_0_WIDTH },
73776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_1_CHECKER_TYPE,
73777  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_1_WIDTH },
73778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_2_CHECKER_TYPE,
73779  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_2_WIDTH },
73780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_3_CHECKER_TYPE,
73781  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_3_WIDTH },
73782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_4_CHECKER_TYPE,
73783  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_4_WIDTH },
73784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_5_CHECKER_TYPE,
73785  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_5_WIDTH },
73786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_6_CHECKER_TYPE,
73787  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_6_WIDTH },
73788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_7_CHECKER_TYPE,
73789  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_7_WIDTH },
73790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_8_CHECKER_TYPE,
73791  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_8_WIDTH },
73792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_9_CHECKER_TYPE,
73793  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_9_WIDTH },
73794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_10_CHECKER_TYPE,
73795  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_10_WIDTH },
73796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_11_CHECKER_TYPE,
73797  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_11_WIDTH },
73798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_12_CHECKER_TYPE,
73799  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_12_WIDTH },
73800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_13_CHECKER_TYPE,
73801  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_13_WIDTH },
73802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_14_CHECKER_TYPE,
73803  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_14_WIDTH },
73804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_15_CHECKER_TYPE,
73805  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_15_WIDTH },
73806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_16_CHECKER_TYPE,
73807  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_16_WIDTH },
73808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_17_CHECKER_TYPE,
73809  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_17_WIDTH },
73810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_18_CHECKER_TYPE,
73811  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_18_WIDTH },
73812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_19_CHECKER_TYPE,
73813  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_19_WIDTH },
73814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_20_CHECKER_TYPE,
73815  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_20_WIDTH },
73816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_21_CHECKER_TYPE,
73817  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_21_WIDTH },
73818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_22_CHECKER_TYPE,
73819  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_22_WIDTH },
73820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_23_CHECKER_TYPE,
73821  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_23_WIDTH },
73822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_24_CHECKER_TYPE,
73823  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_24_WIDTH },
73824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_25_CHECKER_TYPE,
73825  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_25_WIDTH },
73826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_26_CHECKER_TYPE,
73827  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_26_WIDTH },
73828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_27_CHECKER_TYPE,
73829  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_27_WIDTH },
73830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_28_CHECKER_TYPE,
73831  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_28_WIDTH },
73832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_29_CHECKER_TYPE,
73833  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_29_WIDTH },
73834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_30_CHECKER_TYPE,
73835  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_30_WIDTH },
73836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_31_CHECKER_TYPE,
73837  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_31_WIDTH },
73838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_32_CHECKER_TYPE,
73839  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_32_WIDTH },
73840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_33_CHECKER_TYPE,
73841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_33_WIDTH },
73842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_34_CHECKER_TYPE,
73843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_34_WIDTH },
73844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_35_CHECKER_TYPE,
73845  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_35_WIDTH },
73846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_36_CHECKER_TYPE,
73847  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_36_WIDTH },
73848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_37_CHECKER_TYPE,
73849  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_37_WIDTH },
73850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_38_CHECKER_TYPE,
73851  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_38_WIDTH },
73852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_39_CHECKER_TYPE,
73853  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_39_WIDTH },
73854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_40_CHECKER_TYPE,
73855  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_40_WIDTH },
73856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_41_CHECKER_TYPE,
73857  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_41_WIDTH },
73858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_42_CHECKER_TYPE,
73859  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_42_WIDTH },
73860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_43_CHECKER_TYPE,
73861  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_43_WIDTH },
73862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_44_CHECKER_TYPE,
73863  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_44_WIDTH },
73864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_45_CHECKER_TYPE,
73865  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_45_WIDTH },
73866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_46_CHECKER_TYPE,
73867  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_46_WIDTH },
73868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_47_CHECKER_TYPE,
73869  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_47_WIDTH },
73870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_48_CHECKER_TYPE,
73871  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_48_WIDTH },
73872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_49_CHECKER_TYPE,
73873  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_49_WIDTH },
73874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_50_CHECKER_TYPE,
73875  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_50_WIDTH },
73876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_51_CHECKER_TYPE,
73877  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_51_WIDTH },
73878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_52_CHECKER_TYPE,
73879  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_52_WIDTH },
73880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_53_CHECKER_TYPE,
73881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_53_WIDTH },
73882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_54_CHECKER_TYPE,
73883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_54_WIDTH },
73884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_55_CHECKER_TYPE,
73885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_55_WIDTH },
73886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_56_CHECKER_TYPE,
73887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_56_WIDTH },
73888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_57_CHECKER_TYPE,
73889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_57_WIDTH },
73890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_58_CHECKER_TYPE,
73891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_58_WIDTH },
73892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_59_CHECKER_TYPE,
73893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_59_WIDTH },
73894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_60_CHECKER_TYPE,
73895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_60_WIDTH },
73896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_61_CHECKER_TYPE,
73897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_61_WIDTH },
73898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_62_CHECKER_TYPE,
73899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_62_WIDTH },
73900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_63_CHECKER_TYPE,
73901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_63_WIDTH },
73902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_64_CHECKER_TYPE,
73903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_64_WIDTH },
73904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_65_CHECKER_TYPE,
73905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_65_WIDTH },
73906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_66_CHECKER_TYPE,
73907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_66_WIDTH },
73908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_67_CHECKER_TYPE,
73909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_67_WIDTH },
73910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_68_CHECKER_TYPE,
73911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_68_WIDTH },
73912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_69_CHECKER_TYPE,
73913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_69_WIDTH },
73914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_70_CHECKER_TYPE,
73915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_70_WIDTH },
73916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_71_CHECKER_TYPE,
73917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_71_WIDTH },
73918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_72_CHECKER_TYPE,
73919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_72_WIDTH },
73920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_73_CHECKER_TYPE,
73921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_73_WIDTH },
73922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_74_CHECKER_TYPE,
73923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_74_WIDTH },
73924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_75_CHECKER_TYPE,
73925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_75_WIDTH },
73926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_76_CHECKER_TYPE,
73927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_76_WIDTH },
73928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_77_CHECKER_TYPE,
73929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_77_WIDTH },
73930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_78_CHECKER_TYPE,
73931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_78_WIDTH },
73932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_79_CHECKER_TYPE,
73933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_79_WIDTH },
73934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_80_CHECKER_TYPE,
73935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_80_WIDTH },
73936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_81_CHECKER_TYPE,
73937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_81_WIDTH },
73938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_82_CHECKER_TYPE,
73939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_82_WIDTH },
73940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_83_CHECKER_TYPE,
73941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_83_WIDTH },
73942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_84_CHECKER_TYPE,
73943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_84_WIDTH },
73944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_85_CHECKER_TYPE,
73945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_85_WIDTH },
73946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_86_CHECKER_TYPE,
73947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_86_WIDTH },
73948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_87_CHECKER_TYPE,
73949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_87_WIDTH },
73950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_88_CHECKER_TYPE,
73951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_88_WIDTH },
73952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_89_CHECKER_TYPE,
73953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_89_WIDTH },
73954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_90_CHECKER_TYPE,
73955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_90_WIDTH },
73956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_91_CHECKER_TYPE,
73957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_91_WIDTH },
73958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_92_CHECKER_TYPE,
73959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_92_WIDTH },
73960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_93_CHECKER_TYPE,
73961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_93_WIDTH },
73962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_94_CHECKER_TYPE,
73963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_94_WIDTH },
73964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_95_CHECKER_TYPE,
73965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_95_WIDTH },
73966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_96_CHECKER_TYPE,
73967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_96_WIDTH },
73968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_97_CHECKER_TYPE,
73969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_97_WIDTH },
73970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_98_CHECKER_TYPE,
73971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_98_WIDTH },
73972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_99_CHECKER_TYPE,
73973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_99_WIDTH },
73974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_100_CHECKER_TYPE,
73975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_100_WIDTH },
73976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_101_CHECKER_TYPE,
73977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_101_WIDTH },
73978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_102_CHECKER_TYPE,
73979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_102_WIDTH },
73980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_103_CHECKER_TYPE,
73981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_103_WIDTH },
73982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_104_CHECKER_TYPE,
73983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_104_WIDTH },
73984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_105_CHECKER_TYPE,
73985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_105_WIDTH },
73986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_106_CHECKER_TYPE,
73987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_106_WIDTH },
73988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_107_CHECKER_TYPE,
73989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_107_WIDTH },
73990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_108_CHECKER_TYPE,
73991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_108_WIDTH },
73992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_109_CHECKER_TYPE,
73993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_109_WIDTH },
73994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_110_CHECKER_TYPE,
73995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_110_WIDTH },
73996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_111_CHECKER_TYPE,
73997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_111_WIDTH },
73998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_112_CHECKER_TYPE,
73999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_112_WIDTH },
74000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_113_CHECKER_TYPE,
74001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_113_WIDTH },
74002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_114_CHECKER_TYPE,
74003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_114_WIDTH },
74004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_115_CHECKER_TYPE,
74005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_115_WIDTH },
74006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_116_CHECKER_TYPE,
74007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_116_WIDTH },
74008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_117_CHECKER_TYPE,
74009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_117_WIDTH },
74010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_118_CHECKER_TYPE,
74011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_118_WIDTH },
74012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_119_CHECKER_TYPE,
74013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_119_WIDTH },
74014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_120_CHECKER_TYPE,
74015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_120_WIDTH },
74016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_121_CHECKER_TYPE,
74017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_121_WIDTH },
74018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_122_CHECKER_TYPE,
74019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_122_WIDTH },
74020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_123_CHECKER_TYPE,
74021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_123_WIDTH },
74022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_124_CHECKER_TYPE,
74023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_124_WIDTH },
74024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_125_CHECKER_TYPE,
74025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_125_WIDTH },
74026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_126_CHECKER_TYPE,
74027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_126_WIDTH },
74028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_127_CHECKER_TYPE,
74029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_127_WIDTH },
74030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_128_CHECKER_TYPE,
74031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_128_WIDTH },
74032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_129_CHECKER_TYPE,
74033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_129_WIDTH },
74034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_130_CHECKER_TYPE,
74035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_130_WIDTH },
74036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_131_CHECKER_TYPE,
74037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_131_WIDTH },
74038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_132_CHECKER_TYPE,
74039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_132_WIDTH },
74040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_133_CHECKER_TYPE,
74041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_133_WIDTH },
74042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_134_CHECKER_TYPE,
74043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_134_WIDTH },
74044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_135_CHECKER_TYPE,
74045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_135_WIDTH },
74046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_136_CHECKER_TYPE,
74047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_136_WIDTH },
74048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_137_CHECKER_TYPE,
74049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_137_WIDTH },
74050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_138_CHECKER_TYPE,
74051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_138_WIDTH },
74052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_139_CHECKER_TYPE,
74053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_139_WIDTH },
74054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_140_CHECKER_TYPE,
74055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_140_WIDTH },
74056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_141_CHECKER_TYPE,
74057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_141_WIDTH },
74058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_142_CHECKER_TYPE,
74059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_142_WIDTH },
74060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_143_CHECKER_TYPE,
74061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_143_WIDTH },
74062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_144_CHECKER_TYPE,
74063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_144_WIDTH },
74064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_145_CHECKER_TYPE,
74065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_145_WIDTH },
74066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_146_CHECKER_TYPE,
74067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_146_WIDTH },
74068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_147_CHECKER_TYPE,
74069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_147_WIDTH },
74070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_148_CHECKER_TYPE,
74071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_148_WIDTH },
74072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_149_CHECKER_TYPE,
74073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_149_WIDTH },
74074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_150_CHECKER_TYPE,
74075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_150_WIDTH },
74076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_151_CHECKER_TYPE,
74077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_151_WIDTH },
74078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_152_CHECKER_TYPE,
74079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_152_WIDTH },
74080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_153_CHECKER_TYPE,
74081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_153_WIDTH },
74082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_154_CHECKER_TYPE,
74083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_154_WIDTH },
74084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_155_CHECKER_TYPE,
74085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_155_WIDTH },
74086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_156_CHECKER_TYPE,
74087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_156_WIDTH },
74088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_157_CHECKER_TYPE,
74089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_157_WIDTH },
74090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_158_CHECKER_TYPE,
74091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_158_WIDTH },
74092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_159_CHECKER_TYPE,
74093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_159_WIDTH },
74094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_160_CHECKER_TYPE,
74095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_160_WIDTH },
74096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_161_CHECKER_TYPE,
74097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_161_WIDTH },
74098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_162_CHECKER_TYPE,
74099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_162_WIDTH },
74100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_163_CHECKER_TYPE,
74101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_163_WIDTH },
74102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_164_CHECKER_TYPE,
74103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_164_WIDTH },
74104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_165_CHECKER_TYPE,
74105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_165_WIDTH },
74106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_166_CHECKER_TYPE,
74107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_166_WIDTH },
74108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_167_CHECKER_TYPE,
74109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_167_WIDTH },
74110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_168_CHECKER_TYPE,
74111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_168_WIDTH },
74112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_169_CHECKER_TYPE,
74113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_169_WIDTH },
74114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_170_CHECKER_TYPE,
74115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_170_WIDTH },
74116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_171_CHECKER_TYPE,
74117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_171_WIDTH },
74118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_172_CHECKER_TYPE,
74119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_172_WIDTH },
74120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_173_CHECKER_TYPE,
74121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_173_WIDTH },
74122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_174_CHECKER_TYPE,
74123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_174_WIDTH },
74124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_175_CHECKER_TYPE,
74125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_175_WIDTH },
74126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_176_CHECKER_TYPE,
74127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_176_WIDTH },
74128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_177_CHECKER_TYPE,
74129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_177_WIDTH },
74130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_178_CHECKER_TYPE,
74131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_178_WIDTH },
74132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_179_CHECKER_TYPE,
74133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_179_WIDTH },
74134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_180_CHECKER_TYPE,
74135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_180_WIDTH },
74136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_181_CHECKER_TYPE,
74137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_181_WIDTH },
74138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_182_CHECKER_TYPE,
74139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_182_WIDTH },
74140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_183_CHECKER_TYPE,
74141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_183_WIDTH },
74142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_184_CHECKER_TYPE,
74143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_184_WIDTH },
74144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_185_CHECKER_TYPE,
74145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_185_WIDTH },
74146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_186_CHECKER_TYPE,
74147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_186_WIDTH },
74148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_187_CHECKER_TYPE,
74149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_187_WIDTH },
74150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_188_CHECKER_TYPE,
74151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_188_WIDTH },
74152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_189_CHECKER_TYPE,
74153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_189_WIDTH },
74154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_190_CHECKER_TYPE,
74155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_190_WIDTH },
74156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_191_CHECKER_TYPE,
74157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_191_WIDTH },
74158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_192_CHECKER_TYPE,
74159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_192_WIDTH },
74160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_193_CHECKER_TYPE,
74161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_193_WIDTH },
74162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_194_CHECKER_TYPE,
74163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_194_WIDTH },
74164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_195_CHECKER_TYPE,
74165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_195_WIDTH },
74166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_196_CHECKER_TYPE,
74167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_196_WIDTH },
74168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_197_CHECKER_TYPE,
74169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_197_WIDTH },
74170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_198_CHECKER_TYPE,
74171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_198_WIDTH },
74172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_199_CHECKER_TYPE,
74173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_199_WIDTH },
74174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_200_CHECKER_TYPE,
74175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_200_WIDTH },
74176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_201_CHECKER_TYPE,
74177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_201_WIDTH },
74178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_202_CHECKER_TYPE,
74179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_202_WIDTH },
74180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_203_CHECKER_TYPE,
74181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_203_WIDTH },
74182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_204_CHECKER_TYPE,
74183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_204_WIDTH },
74184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_205_CHECKER_TYPE,
74185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_205_WIDTH },
74186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_206_CHECKER_TYPE,
74187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_206_WIDTH },
74188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_207_CHECKER_TYPE,
74189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_207_WIDTH },
74190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_208_CHECKER_TYPE,
74191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_208_WIDTH },
74192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_209_CHECKER_TYPE,
74193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_209_WIDTH },
74194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_210_CHECKER_TYPE,
74195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_210_WIDTH },
74196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_211_CHECKER_TYPE,
74197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_211_WIDTH },
74198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_212_CHECKER_TYPE,
74199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_212_WIDTH },
74200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_213_CHECKER_TYPE,
74201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_213_WIDTH },
74202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_214_CHECKER_TYPE,
74203  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_214_WIDTH },
74204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_215_CHECKER_TYPE,
74205  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_215_WIDTH },
74206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_216_CHECKER_TYPE,
74207  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_216_WIDTH },
74208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_217_CHECKER_TYPE,
74209  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_217_WIDTH },
74210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_218_CHECKER_TYPE,
74211  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_218_WIDTH },
74212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_219_CHECKER_TYPE,
74213  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_219_WIDTH },
74214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_220_CHECKER_TYPE,
74215  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_220_WIDTH },
74216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_221_CHECKER_TYPE,
74217  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_221_WIDTH },
74218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_222_CHECKER_TYPE,
74219  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_222_WIDTH },
74220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_223_CHECKER_TYPE,
74221  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_223_WIDTH },
74222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_224_CHECKER_TYPE,
74223  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_224_WIDTH },
74224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_225_CHECKER_TYPE,
74225  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_225_WIDTH },
74226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_226_CHECKER_TYPE,
74227  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_226_WIDTH },
74228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_227_CHECKER_TYPE,
74229  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_227_WIDTH },
74230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_228_CHECKER_TYPE,
74231  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_228_WIDTH },
74232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_229_CHECKER_TYPE,
74233  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_229_WIDTH },
74234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_230_CHECKER_TYPE,
74235  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_230_WIDTH },
74236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_231_CHECKER_TYPE,
74237  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_231_WIDTH },
74238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_232_CHECKER_TYPE,
74239  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_232_WIDTH },
74240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_233_CHECKER_TYPE,
74241  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_233_WIDTH },
74242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_234_CHECKER_TYPE,
74243  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_234_WIDTH },
74244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_235_CHECKER_TYPE,
74245  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_235_WIDTH },
74246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_236_CHECKER_TYPE,
74247  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_236_WIDTH },
74248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_237_CHECKER_TYPE,
74249  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_237_WIDTH },
74250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_238_CHECKER_TYPE,
74251  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_238_WIDTH },
74252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_239_CHECKER_TYPE,
74253  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_239_WIDTH },
74254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_240_CHECKER_TYPE,
74255  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_240_WIDTH },
74256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_241_CHECKER_TYPE,
74257  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_241_WIDTH },
74258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_242_CHECKER_TYPE,
74259  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_242_WIDTH },
74260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_243_CHECKER_TYPE,
74261  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_243_WIDTH },
74262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_244_CHECKER_TYPE,
74263  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_244_WIDTH },
74264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_245_CHECKER_TYPE,
74265  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_245_WIDTH },
74266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_246_CHECKER_TYPE,
74267  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_246_WIDTH },
74268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_247_CHECKER_TYPE,
74269  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_247_WIDTH },
74270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_248_CHECKER_TYPE,
74271  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_248_WIDTH },
74272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_249_CHECKER_TYPE,
74273  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_249_WIDTH },
74274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_250_CHECKER_TYPE,
74275  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_250_WIDTH },
74276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_251_CHECKER_TYPE,
74277  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_251_WIDTH },
74278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_252_CHECKER_TYPE,
74279  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_252_WIDTH },
74280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_253_CHECKER_TYPE,
74281  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_253_WIDTH },
74282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_254_CHECKER_TYPE,
74283  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_254_WIDTH },
74284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_255_CHECKER_TYPE,
74285  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_GROUP_255_WIDTH },
74286 };
74287 
74293 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS] =
74294 {
74295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_0_CHECKER_TYPE,
74296  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_0_WIDTH },
74297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_1_CHECKER_TYPE,
74298  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_1_WIDTH },
74299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_2_CHECKER_TYPE,
74300  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_2_WIDTH },
74301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_3_CHECKER_TYPE,
74302  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_3_WIDTH },
74303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_4_CHECKER_TYPE,
74304  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_4_WIDTH },
74305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_5_CHECKER_TYPE,
74306  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_5_WIDTH },
74307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_6_CHECKER_TYPE,
74308  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_6_WIDTH },
74309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_7_CHECKER_TYPE,
74310  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_7_WIDTH },
74311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_8_CHECKER_TYPE,
74312  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_8_WIDTH },
74313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_9_CHECKER_TYPE,
74314  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_9_WIDTH },
74315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_10_CHECKER_TYPE,
74316  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_10_WIDTH },
74317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_11_CHECKER_TYPE,
74318  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_11_WIDTH },
74319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_12_CHECKER_TYPE,
74320  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_12_WIDTH },
74321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_13_CHECKER_TYPE,
74322  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_13_WIDTH },
74323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_14_CHECKER_TYPE,
74324  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_14_WIDTH },
74325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_15_CHECKER_TYPE,
74326  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_15_WIDTH },
74327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_16_CHECKER_TYPE,
74328  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_16_WIDTH },
74329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_17_CHECKER_TYPE,
74330  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_17_WIDTH },
74331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_18_CHECKER_TYPE,
74332  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_18_WIDTH },
74333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_19_CHECKER_TYPE,
74334  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_19_WIDTH },
74335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_20_CHECKER_TYPE,
74336  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_20_WIDTH },
74337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_21_CHECKER_TYPE,
74338  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_21_WIDTH },
74339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_22_CHECKER_TYPE,
74340  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_22_WIDTH },
74341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_23_CHECKER_TYPE,
74342  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_23_WIDTH },
74343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_24_CHECKER_TYPE,
74344  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_24_WIDTH },
74345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_25_CHECKER_TYPE,
74346  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_25_WIDTH },
74347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_26_CHECKER_TYPE,
74348  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_26_WIDTH },
74349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_27_CHECKER_TYPE,
74350  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_27_WIDTH },
74351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_28_CHECKER_TYPE,
74352  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_28_WIDTH },
74353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_29_CHECKER_TYPE,
74354  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_29_WIDTH },
74355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_30_CHECKER_TYPE,
74356  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_30_WIDTH },
74357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_31_CHECKER_TYPE,
74358  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_31_WIDTH },
74359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_32_CHECKER_TYPE,
74360  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_32_WIDTH },
74361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_33_CHECKER_TYPE,
74362  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_33_WIDTH },
74363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_34_CHECKER_TYPE,
74364  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_34_WIDTH },
74365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_35_CHECKER_TYPE,
74366  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_35_WIDTH },
74367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_36_CHECKER_TYPE,
74368  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_36_WIDTH },
74369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_37_CHECKER_TYPE,
74370  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_37_WIDTH },
74371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_38_CHECKER_TYPE,
74372  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_38_WIDTH },
74373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_39_CHECKER_TYPE,
74374  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_39_WIDTH },
74375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_40_CHECKER_TYPE,
74376  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_40_WIDTH },
74377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_41_CHECKER_TYPE,
74378  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_41_WIDTH },
74379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_42_CHECKER_TYPE,
74380  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_42_WIDTH },
74381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_43_CHECKER_TYPE,
74382  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_43_WIDTH },
74383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_44_CHECKER_TYPE,
74384  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_44_WIDTH },
74385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_45_CHECKER_TYPE,
74386  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_45_WIDTH },
74387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_46_CHECKER_TYPE,
74388  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_46_WIDTH },
74389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_47_CHECKER_TYPE,
74390  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_47_WIDTH },
74391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_48_CHECKER_TYPE,
74392  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_48_WIDTH },
74393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_49_CHECKER_TYPE,
74394  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_49_WIDTH },
74395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_50_CHECKER_TYPE,
74396  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_50_WIDTH },
74397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_51_CHECKER_TYPE,
74398  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_51_WIDTH },
74399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_52_CHECKER_TYPE,
74400  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_52_WIDTH },
74401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_53_CHECKER_TYPE,
74402  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_53_WIDTH },
74403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_54_CHECKER_TYPE,
74404  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_54_WIDTH },
74405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_55_CHECKER_TYPE,
74406  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_55_WIDTH },
74407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_56_CHECKER_TYPE,
74408  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_56_WIDTH },
74409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_57_CHECKER_TYPE,
74410  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_57_WIDTH },
74411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_58_CHECKER_TYPE,
74412  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_58_WIDTH },
74413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_59_CHECKER_TYPE,
74414  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_59_WIDTH },
74415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_60_CHECKER_TYPE,
74416  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_60_WIDTH },
74417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_61_CHECKER_TYPE,
74418  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_61_WIDTH },
74419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_62_CHECKER_TYPE,
74420  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_62_WIDTH },
74421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_63_CHECKER_TYPE,
74422  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_63_WIDTH },
74423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_64_CHECKER_TYPE,
74424  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_64_WIDTH },
74425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_65_CHECKER_TYPE,
74426  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_65_WIDTH },
74427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_66_CHECKER_TYPE,
74428  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_66_WIDTH },
74429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_67_CHECKER_TYPE,
74430  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_67_WIDTH },
74431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_68_CHECKER_TYPE,
74432  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_68_WIDTH },
74433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_69_CHECKER_TYPE,
74434  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_69_WIDTH },
74435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_70_CHECKER_TYPE,
74436  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_70_WIDTH },
74437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_71_CHECKER_TYPE,
74438  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_71_WIDTH },
74439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_72_CHECKER_TYPE,
74440  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_72_WIDTH },
74441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_73_CHECKER_TYPE,
74442  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_73_WIDTH },
74443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_74_CHECKER_TYPE,
74444  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_74_WIDTH },
74445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_75_CHECKER_TYPE,
74446  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_75_WIDTH },
74447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_76_CHECKER_TYPE,
74448  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_76_WIDTH },
74449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_77_CHECKER_TYPE,
74450  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_77_WIDTH },
74451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_78_CHECKER_TYPE,
74452  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_78_WIDTH },
74453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_79_CHECKER_TYPE,
74454  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_79_WIDTH },
74455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_80_CHECKER_TYPE,
74456  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_80_WIDTH },
74457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_81_CHECKER_TYPE,
74458  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_81_WIDTH },
74459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_82_CHECKER_TYPE,
74460  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_82_WIDTH },
74461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_83_CHECKER_TYPE,
74462  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_83_WIDTH },
74463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_84_CHECKER_TYPE,
74464  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_84_WIDTH },
74465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_85_CHECKER_TYPE,
74466  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_85_WIDTH },
74467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_86_CHECKER_TYPE,
74468  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_86_WIDTH },
74469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_87_CHECKER_TYPE,
74470  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_87_WIDTH },
74471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_88_CHECKER_TYPE,
74472  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_88_WIDTH },
74473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_89_CHECKER_TYPE,
74474  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_89_WIDTH },
74475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_90_CHECKER_TYPE,
74476  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_90_WIDTH },
74477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_91_CHECKER_TYPE,
74478  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_91_WIDTH },
74479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_92_CHECKER_TYPE,
74480  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_92_WIDTH },
74481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_93_CHECKER_TYPE,
74482  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_93_WIDTH },
74483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_94_CHECKER_TYPE,
74484  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_94_WIDTH },
74485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_95_CHECKER_TYPE,
74486  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_95_WIDTH },
74487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_96_CHECKER_TYPE,
74488  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_96_WIDTH },
74489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_97_CHECKER_TYPE,
74490  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_97_WIDTH },
74491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_98_CHECKER_TYPE,
74492  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_98_WIDTH },
74493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_99_CHECKER_TYPE,
74494  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_99_WIDTH },
74495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_100_CHECKER_TYPE,
74496  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_100_WIDTH },
74497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_101_CHECKER_TYPE,
74498  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_101_WIDTH },
74499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_102_CHECKER_TYPE,
74500  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_102_WIDTH },
74501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_103_CHECKER_TYPE,
74502  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_103_WIDTH },
74503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_104_CHECKER_TYPE,
74504  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_104_WIDTH },
74505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_105_CHECKER_TYPE,
74506  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_105_WIDTH },
74507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_106_CHECKER_TYPE,
74508  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_106_WIDTH },
74509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_107_CHECKER_TYPE,
74510  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_107_WIDTH },
74511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_108_CHECKER_TYPE,
74512  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_108_WIDTH },
74513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_109_CHECKER_TYPE,
74514  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_109_WIDTH },
74515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_110_CHECKER_TYPE,
74516  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_110_WIDTH },
74517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_111_CHECKER_TYPE,
74518  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_111_WIDTH },
74519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_112_CHECKER_TYPE,
74520  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_112_WIDTH },
74521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_113_CHECKER_TYPE,
74522  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_113_WIDTH },
74523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_114_CHECKER_TYPE,
74524  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_114_WIDTH },
74525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_115_CHECKER_TYPE,
74526  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_115_WIDTH },
74527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_116_CHECKER_TYPE,
74528  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_116_WIDTH },
74529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_117_CHECKER_TYPE,
74530  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_117_WIDTH },
74531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_118_CHECKER_TYPE,
74532  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_118_WIDTH },
74533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_119_CHECKER_TYPE,
74534  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_119_WIDTH },
74535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_120_CHECKER_TYPE,
74536  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_120_WIDTH },
74537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_121_CHECKER_TYPE,
74538  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_121_WIDTH },
74539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_122_CHECKER_TYPE,
74540  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_122_WIDTH },
74541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_123_CHECKER_TYPE,
74542  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_123_WIDTH },
74543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_124_CHECKER_TYPE,
74544  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_124_WIDTH },
74545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_125_CHECKER_TYPE,
74546  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_125_WIDTH },
74547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_126_CHECKER_TYPE,
74548  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_126_WIDTH },
74549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_127_CHECKER_TYPE,
74550  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_127_WIDTH },
74551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_128_CHECKER_TYPE,
74552  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_128_WIDTH },
74553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_129_CHECKER_TYPE,
74554  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_129_WIDTH },
74555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_130_CHECKER_TYPE,
74556  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_130_WIDTH },
74557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_131_CHECKER_TYPE,
74558  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_131_WIDTH },
74559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_132_CHECKER_TYPE,
74560  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_132_WIDTH },
74561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_133_CHECKER_TYPE,
74562  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_133_WIDTH },
74563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_134_CHECKER_TYPE,
74564  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_134_WIDTH },
74565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_135_CHECKER_TYPE,
74566  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_135_WIDTH },
74567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_136_CHECKER_TYPE,
74568  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_136_WIDTH },
74569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_137_CHECKER_TYPE,
74570  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_137_WIDTH },
74571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_138_CHECKER_TYPE,
74572  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_138_WIDTH },
74573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_139_CHECKER_TYPE,
74574  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_139_WIDTH },
74575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_140_CHECKER_TYPE,
74576  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_140_WIDTH },
74577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_141_CHECKER_TYPE,
74578  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_141_WIDTH },
74579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_142_CHECKER_TYPE,
74580  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_142_WIDTH },
74581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_143_CHECKER_TYPE,
74582  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_143_WIDTH },
74583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_144_CHECKER_TYPE,
74584  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_144_WIDTH },
74585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_145_CHECKER_TYPE,
74586  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_145_WIDTH },
74587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_146_CHECKER_TYPE,
74588  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_146_WIDTH },
74589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_147_CHECKER_TYPE,
74590  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_147_WIDTH },
74591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_148_CHECKER_TYPE,
74592  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_148_WIDTH },
74593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_149_CHECKER_TYPE,
74594  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_149_WIDTH },
74595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_150_CHECKER_TYPE,
74596  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_150_WIDTH },
74597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_151_CHECKER_TYPE,
74598  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_151_WIDTH },
74599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_152_CHECKER_TYPE,
74600  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_152_WIDTH },
74601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_153_CHECKER_TYPE,
74602  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_153_WIDTH },
74603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_154_CHECKER_TYPE,
74604  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_154_WIDTH },
74605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_155_CHECKER_TYPE,
74606  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_155_WIDTH },
74607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_156_CHECKER_TYPE,
74608  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_156_WIDTH },
74609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_157_CHECKER_TYPE,
74610  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_157_WIDTH },
74611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_158_CHECKER_TYPE,
74612  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_158_WIDTH },
74613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_159_CHECKER_TYPE,
74614  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_159_WIDTH },
74615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_160_CHECKER_TYPE,
74616  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_160_WIDTH },
74617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_161_CHECKER_TYPE,
74618  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_161_WIDTH },
74619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_162_CHECKER_TYPE,
74620  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_162_WIDTH },
74621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_163_CHECKER_TYPE,
74622  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_163_WIDTH },
74623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_164_CHECKER_TYPE,
74624  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_164_WIDTH },
74625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_165_CHECKER_TYPE,
74626  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_165_WIDTH },
74627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_166_CHECKER_TYPE,
74628  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_166_WIDTH },
74629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_167_CHECKER_TYPE,
74630  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_167_WIDTH },
74631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_168_CHECKER_TYPE,
74632  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_168_WIDTH },
74633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_169_CHECKER_TYPE,
74634  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_169_WIDTH },
74635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_170_CHECKER_TYPE,
74636  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_170_WIDTH },
74637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_171_CHECKER_TYPE,
74638  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_171_WIDTH },
74639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_172_CHECKER_TYPE,
74640  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_172_WIDTH },
74641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_173_CHECKER_TYPE,
74642  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_173_WIDTH },
74643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_174_CHECKER_TYPE,
74644  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_174_WIDTH },
74645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_175_CHECKER_TYPE,
74646  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_175_WIDTH },
74647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_176_CHECKER_TYPE,
74648  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_176_WIDTH },
74649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_177_CHECKER_TYPE,
74650  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_177_WIDTH },
74651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_178_CHECKER_TYPE,
74652  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_178_WIDTH },
74653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_179_CHECKER_TYPE,
74654  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_179_WIDTH },
74655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_180_CHECKER_TYPE,
74656  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_180_WIDTH },
74657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_181_CHECKER_TYPE,
74658  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_181_WIDTH },
74659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_182_CHECKER_TYPE,
74660  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_182_WIDTH },
74661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_183_CHECKER_TYPE,
74662  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_183_WIDTH },
74663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_184_CHECKER_TYPE,
74664  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_184_WIDTH },
74665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_185_CHECKER_TYPE,
74666  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_185_WIDTH },
74667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_186_CHECKER_TYPE,
74668  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_186_WIDTH },
74669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_187_CHECKER_TYPE,
74670  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_187_WIDTH },
74671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_188_CHECKER_TYPE,
74672  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_188_WIDTH },
74673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_189_CHECKER_TYPE,
74674  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_189_WIDTH },
74675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_190_CHECKER_TYPE,
74676  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_190_WIDTH },
74677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_191_CHECKER_TYPE,
74678  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_191_WIDTH },
74679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_192_CHECKER_TYPE,
74680  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_192_WIDTH },
74681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_193_CHECKER_TYPE,
74682  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_193_WIDTH },
74683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_194_CHECKER_TYPE,
74684  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_194_WIDTH },
74685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_195_CHECKER_TYPE,
74686  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_195_WIDTH },
74687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_196_CHECKER_TYPE,
74688  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_196_WIDTH },
74689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_197_CHECKER_TYPE,
74690  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_197_WIDTH },
74691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_198_CHECKER_TYPE,
74692  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_198_WIDTH },
74693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_199_CHECKER_TYPE,
74694  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_199_WIDTH },
74695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_200_CHECKER_TYPE,
74696  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_200_WIDTH },
74697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_201_CHECKER_TYPE,
74698  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_201_WIDTH },
74699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_202_CHECKER_TYPE,
74700  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_202_WIDTH },
74701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_203_CHECKER_TYPE,
74702  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_GROUP_203_WIDTH },
74703 };
74704 
74710 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
74711 {
74712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
74713  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
74714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
74715  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
74716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
74717  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
74718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
74719  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
74720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
74721  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
74722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
74723  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
74724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
74725  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
74726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
74727  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
74728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
74729  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
74730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
74731  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
74732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
74733  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
74734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
74735  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
74736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
74737  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
74738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
74739  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
74740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
74741  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
74742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
74743  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
74744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
74745  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
74746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
74747  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
74748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
74749  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
74750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
74751  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
74752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
74753  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
74754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
74755  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
74756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
74757  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
74758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
74759  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
74760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
74761  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
74762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
74763  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
74764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
74765  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
74766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
74767  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
74768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
74769  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
74770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
74771  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
74772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
74773  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
74774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
74775  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
74776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
74777  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
74778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
74779  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
74780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
74781  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
74782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
74783  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
74784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
74785  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
74786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
74787  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
74788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
74789  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
74790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
74791  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
74792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
74793  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
74794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
74795  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
74796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
74797  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
74798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
74799  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
74800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
74801  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
74802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
74803  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
74804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
74805  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
74806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
74807  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
74808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
74809  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
74810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
74811  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
74812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
74813  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
74814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
74815  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
74816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
74817  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
74818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
74819  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
74820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
74821  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
74822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
74823  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
74824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
74825  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
74826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
74827  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
74828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
74829  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
74830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
74831  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
74832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
74833  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
74834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
74835  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
74836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
74837  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
74838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
74839  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
74840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
74841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
74842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
74843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
74844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
74845  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
74846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
74847  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
74848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
74849  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
74850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
74851  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
74852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
74853  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
74854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
74855  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
74856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
74857  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
74858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
74859  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
74860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
74861  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
74862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
74863  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
74864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
74865  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
74866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
74867  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
74868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
74869  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
74870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
74871  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
74872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
74873  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
74874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
74875  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
74876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
74877  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
74878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
74879  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
74880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
74881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
74882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
74883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
74884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
74885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
74886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
74887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
74888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
74889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
74890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
74891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
74892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
74893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
74894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
74895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
74896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
74897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
74898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
74899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
74900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
74901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
74902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
74903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
74904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
74905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
74906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
74907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
74908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
74909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
74910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
74911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
74912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
74913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
74914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
74915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
74916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
74917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
74918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
74919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
74920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
74921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
74922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
74923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
74924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
74925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
74926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
74927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
74928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
74929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
74930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
74931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
74932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
74933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
74934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
74935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
74936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
74937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
74938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
74939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
74940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
74941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
74942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
74943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
74944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
74945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
74946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
74947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
74948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
74949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
74950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
74951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
74952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
74953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
74954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
74955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
74956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
74957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
74958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
74959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
74960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
74961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
74962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
74963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
74964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
74965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
74966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
74967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
74968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
74969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
74970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
74971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
74972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
74973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
74974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
74975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
74976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
74977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
74978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
74979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
74980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
74981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
74982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
74983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
74984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
74985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
74986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
74987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
74988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
74989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
74990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
74991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
74992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
74993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
74994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
74995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
74996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
74997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
74998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
74999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
75000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
75001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
75002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
75003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
75004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
75005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
75006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
75007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
75008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
75009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
75010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
75011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
75012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
75013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
75014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
75015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
75016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
75017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
75018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
75019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
75020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
75021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
75022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
75023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
75024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
75025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
75026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
75027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
75028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
75029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
75030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
75031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
75032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
75033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
75034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
75035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
75036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
75037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
75038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
75039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
75040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
75041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
75042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
75043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
75044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
75045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
75046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
75047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
75048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
75049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
75050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
75051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
75052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
75053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
75054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
75055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
75056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
75057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
75058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
75059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
75060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
75061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
75062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
75063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
75064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
75065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
75066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
75067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
75068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
75069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
75070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
75071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
75072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
75073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
75074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
75075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
75076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
75077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
75078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
75079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
75080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
75081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
75082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
75083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
75084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
75085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
75086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
75087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
75088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
75089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
75090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
75091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
75092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
75093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
75094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
75095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
75096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
75097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
75098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
75099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
75100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
75101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
75102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
75103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
75104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
75105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
75106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
75107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
75108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
75109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
75110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
75111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
75112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
75113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
75114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
75115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
75116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
75117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
75118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
75119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
75120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
75121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
75122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
75123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
75124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
75125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
75126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
75127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
75128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
75129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
75130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
75131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
75132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
75133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
75134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
75135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
75136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
75137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
75138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
75139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
75140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
75141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
75142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
75143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
75144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
75145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
75146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
75147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
75148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
75149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
75150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
75151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
75152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
75153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
75154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
75155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
75156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
75157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
75158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
75159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
75160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
75161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
75162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
75163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
75164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
75165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
75166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
75167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
75168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
75169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
75170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
75171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
75172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
75173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
75174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
75175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
75176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
75177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
75178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
75179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
75180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
75181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
75182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
75183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
75184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
75185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
75186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
75187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
75188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
75189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
75190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
75191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
75192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
75193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
75194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
75195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
75196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
75197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
75198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
75199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
75200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
75201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
75202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
75203  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
75204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
75205  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
75206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
75207  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
75208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
75209  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
75210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
75211  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
75212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
75213  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
75214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
75215  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
75216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
75217  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
75218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
75219  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
75220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
75221  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
75222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
75223  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
75224 };
75225 
75231 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
75232 {
75233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
75234  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
75235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
75236  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
75237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
75238  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
75239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
75240  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
75241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
75242  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
75243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
75244  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
75245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
75246  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
75247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
75248  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
75249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
75250  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
75251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
75252  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
75253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
75254  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
75255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
75256  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
75257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
75258  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
75259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
75260  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
75261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
75262  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
75263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
75264  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
75265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
75266  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
75267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
75268  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
75269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
75270  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
75271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
75272  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
75273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
75274  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
75275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
75276  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
75277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
75278  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
75279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
75280  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
75281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
75282  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
75283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
75284  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
75285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
75286  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
75287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
75288  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
75289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
75290  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
75291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
75292  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
75293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
75294  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
75295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
75296  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
75297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
75298  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
75299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
75300  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
75301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
75302  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
75303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
75304  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
75305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
75306  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
75307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
75308  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
75309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
75310  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
75311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
75312  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
75313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
75314  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
75315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
75316  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
75317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
75318  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
75319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
75320  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
75321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
75322  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
75323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
75324  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
75325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
75326  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
75327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
75328  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
75329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
75330  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
75331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
75332  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
75333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
75334  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
75335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
75336  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
75337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
75338  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
75339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
75340  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
75341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
75342  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
75343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
75344  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
75345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
75346  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
75347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
75348  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
75349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
75350  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
75351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
75352  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
75353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
75354  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
75355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
75356  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
75357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
75358  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
75359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
75360  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
75361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
75362  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
75363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
75364  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
75365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
75366  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
75367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
75368  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
75369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
75370  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
75371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
75372  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
75373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
75374  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
75375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
75376  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
75377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
75378  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
75379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
75380  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
75381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
75382  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
75383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
75384  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
75385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
75386  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
75387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
75388  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
75389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
75390  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
75391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
75392  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
75393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
75394  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
75395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
75396  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
75397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
75398  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
75399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
75400  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
75401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
75402  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
75403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
75404  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
75405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
75406  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
75407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
75408  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
75409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
75410  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
75411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
75412  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
75413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
75414  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
75415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
75416  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
75417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
75418  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
75419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
75420  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
75421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
75422  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
75423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
75424  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
75425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
75426  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
75427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
75428  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
75429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
75430  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
75431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
75432  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
75433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
75434  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
75435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
75436  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
75437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
75438  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
75439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
75440  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
75441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
75442  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
75443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
75444  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
75445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
75446  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
75447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
75448  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
75449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
75450  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
75451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
75452  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
75453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
75454  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
75455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
75456  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
75457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
75458  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
75459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
75460  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
75461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
75462  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
75463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
75464  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
75465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
75466  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
75467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
75468  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
75469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
75470  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
75471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
75472  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
75473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
75474  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
75475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
75476  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
75477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
75478  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
75479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
75480  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
75481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
75482  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
75483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
75484  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
75485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
75486  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
75487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
75488  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
75489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
75490  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
75491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
75492  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
75493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
75494  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
75495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
75496  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
75497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
75498  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
75499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
75500  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
75501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
75502  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
75503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
75504  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
75505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
75506  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
75507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
75508  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
75509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
75510  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
75511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
75512  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
75513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
75514  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
75515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
75516  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
75517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
75518  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
75519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
75520  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
75521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
75522  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
75523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
75524  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
75525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
75526  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
75527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
75528  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
75529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
75530  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
75531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
75532  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
75533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
75534  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
75535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
75536  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
75537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
75538  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
75539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
75540  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
75541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
75542  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
75543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
75544  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
75545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
75546  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
75547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
75548  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
75549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
75550  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
75551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
75552  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
75553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
75554  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
75555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
75556  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
75557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
75558  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
75559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
75560  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
75561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
75562  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
75563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
75564  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
75565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
75566  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
75567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
75568  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
75569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
75570  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
75571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
75572  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
75573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
75574  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
75575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
75576  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
75577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
75578  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
75579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
75580  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
75581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
75582  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
75583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
75584  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
75585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
75586  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
75587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
75588  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
75589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
75590  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
75591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
75592  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
75593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
75594  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
75595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
75596  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
75597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
75598  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
75599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
75600  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
75601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
75602  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
75603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
75604  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
75605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
75606  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
75607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
75608  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
75609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
75610  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
75611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
75612  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
75613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
75614  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
75615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
75616  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
75617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
75618  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
75619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
75620  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
75621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
75622  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
75623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
75624  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
75625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
75626  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
75627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
75628  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
75629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
75630  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
75631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
75632  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
75633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
75634  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
75635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
75636  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
75637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
75638  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
75639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
75640  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
75641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
75642  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
75643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
75644  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
75645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
75646  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
75647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
75648  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
75649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
75650  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
75651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
75652  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
75653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
75654  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
75655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
75656  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
75657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
75658  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
75659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
75660  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
75661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
75662  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
75663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
75664  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
75665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
75666  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
75667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
75668  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
75669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
75670  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
75671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
75672  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
75673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
75674  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
75675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
75676  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
75677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
75678  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
75679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
75680  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
75681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
75682  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
75683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
75684  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
75685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
75686  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
75687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
75688  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
75689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
75690  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
75691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
75692  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
75693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
75694  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
75695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
75696  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
75697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
75698  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
75699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
75700  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
75701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
75702  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
75703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
75704  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
75705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
75706  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
75707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
75708  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
75709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
75710  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
75711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
75712  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
75713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
75714  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
75715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
75716  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
75717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
75718  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
75719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
75720  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
75721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
75722  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
75723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
75724  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
75725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
75726  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
75727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
75728  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
75729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
75730  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
75731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
75732  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
75733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
75734  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
75735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
75736  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
75737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
75738  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
75739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
75740  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
75741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
75742  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
75743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
75744  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
75745 };
75746 
75752 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
75753 {
75754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
75755  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
75756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
75757  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
75758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
75759  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
75760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
75761  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
75762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
75763  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
75764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
75765  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
75766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
75767  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
75768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
75769  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
75770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
75771  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
75772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
75773  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
75774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
75775  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
75776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
75777  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
75778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
75779  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
75780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
75781  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
75782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
75783  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
75784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
75785  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
75786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
75787  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
75788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
75789  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
75790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
75791  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
75792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
75793  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
75794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
75795  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
75796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
75797  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
75798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
75799  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
75800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
75801  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
75802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
75803  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
75804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
75805  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
75806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
75807  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
75808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
75809  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
75810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
75811  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
75812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
75813  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
75814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
75815  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
75816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
75817  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
75818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
75819  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
75820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
75821  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
75822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
75823  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
75824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
75825  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
75826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
75827  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
75828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
75829  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
75830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
75831  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
75832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
75833  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
75834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
75835  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
75836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
75837  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
75838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
75839  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
75840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
75841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
75842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
75843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
75844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
75845  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
75846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
75847  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
75848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
75849  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
75850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
75851  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
75852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
75853  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
75854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
75855  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
75856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
75857  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
75858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
75859  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
75860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
75861  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
75862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
75863  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
75864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
75865  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
75866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
75867  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
75868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
75869  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
75870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
75871  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
75872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
75873  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
75874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
75875  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
75876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
75877  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
75878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
75879  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
75880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
75881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
75882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
75883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
75884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
75885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
75886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
75887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
75888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
75889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
75890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
75891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
75892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
75893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
75894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
75895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
75896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
75897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
75898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
75899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
75900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
75901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
75902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
75903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
75904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
75905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
75906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
75907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
75908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
75909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
75910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
75911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
75912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
75913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
75914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
75915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
75916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
75917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
75918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
75919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
75920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
75921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
75922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
75923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
75924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
75925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
75926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
75927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
75928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
75929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
75930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
75931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
75932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
75933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
75934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
75935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
75936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
75937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
75938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
75939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
75940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
75941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
75942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
75943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
75944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
75945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
75946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
75947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
75948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
75949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
75950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
75951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
75952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
75953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
75954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
75955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
75956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
75957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
75958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
75959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
75960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
75961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
75962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
75963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
75964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
75965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
75966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
75967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
75968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
75969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
75970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
75971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
75972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
75973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
75974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
75975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
75976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
75977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
75978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
75979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
75980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
75981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
75982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
75983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
75984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
75985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
75986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
75987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
75988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
75989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
75990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
75991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
75992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
75993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
75994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
75995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
75996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
75997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
75998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
75999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
76000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
76001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
76002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
76003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
76004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
76005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
76006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
76007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
76008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
76009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
76010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
76011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
76012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
76013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
76014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
76015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
76016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
76017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
76018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
76019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
76020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
76021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
76022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
76023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
76024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
76025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
76026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
76027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
76028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
76029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
76030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
76031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
76032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
76033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
76034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
76035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
76036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
76037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
76038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
76039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
76040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
76041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
76042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
76043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
76044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
76045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
76046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
76047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
76048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
76049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
76050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
76051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
76052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
76053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
76054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
76055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
76056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
76057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
76058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
76059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
76060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
76061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
76062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
76063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
76064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
76065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
76066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
76067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
76068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
76069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
76070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
76071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
76072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
76073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
76074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
76075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
76076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
76077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
76078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
76079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
76080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
76081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
76082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
76083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
76084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
76085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
76086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
76087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
76088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
76089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
76090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
76091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
76092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
76093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
76094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
76095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
76096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
76097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
76098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
76099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
76100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
76101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
76102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
76103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
76104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
76105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
76106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
76107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
76108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
76109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
76110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
76111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
76112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
76113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
76114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
76115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
76116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
76117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
76118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
76119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
76120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
76121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
76122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
76123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
76124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
76125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
76126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
76127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
76128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
76129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
76130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
76131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
76132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
76133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
76134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
76135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
76136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
76137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
76138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
76139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
76140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
76141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
76142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
76143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
76144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
76145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
76146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
76147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
76148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
76149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
76150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
76151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
76152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
76153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
76154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
76155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
76156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
76157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
76158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
76159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
76160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
76161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
76162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
76163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
76164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
76165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
76166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
76167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
76168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
76169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
76170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
76171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
76172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
76173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
76174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
76175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
76176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
76177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
76178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
76179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
76180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
76181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
76182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
76183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
76184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
76185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
76186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
76187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
76188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
76189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
76190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
76191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
76192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
76193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
76194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
76195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
76196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
76197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
76198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
76199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
76200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
76201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
76202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
76203  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
76204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
76205  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
76206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
76207  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
76208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
76209  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
76210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
76211  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
76212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
76213  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
76214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
76215  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
76216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
76217  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
76218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
76219  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
76220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
76221  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
76222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
76223  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
76224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
76225  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
76226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
76227  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
76228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
76229  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
76230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
76231  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
76232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
76233  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
76234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
76235  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
76236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
76237  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
76238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
76239  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
76240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
76241  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
76242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
76243  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
76244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
76245  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
76246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
76247  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
76248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
76249  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
76250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
76251  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
76252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
76253  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
76254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
76255  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
76256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
76257  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
76258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
76259  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
76260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
76261  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
76262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
76263  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
76264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
76265  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
76266 };
76267 
76273 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
76274 {
76275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
76276  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
76277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
76278  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
76279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
76280  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
76281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
76282  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
76283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
76284  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
76285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
76286  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
76287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
76288  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
76289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
76290  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
76291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
76292  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
76293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
76294  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
76295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
76296  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
76297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
76298  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
76299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
76300  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
76301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
76302  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
76303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
76304  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
76305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
76306  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
76307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
76308  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
76309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
76310  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
76311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
76312  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
76313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
76314  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
76315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
76316  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
76317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
76318  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
76319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
76320  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
76321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
76322  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
76323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
76324  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
76325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
76326  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
76327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
76328  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
76329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
76330  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
76331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
76332  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
76333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
76334  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
76335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
76336  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
76337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
76338  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
76339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
76340  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
76341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
76342  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
76343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
76344  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
76345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
76346  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
76347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
76348  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
76349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
76350  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
76351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
76352  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
76353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
76354  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
76355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
76356  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
76357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
76358  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
76359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
76360  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
76361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
76362  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
76363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
76364  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
76365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
76366  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
76367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
76368  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
76369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
76370  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
76371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
76372  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
76373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
76374  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
76375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
76376  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
76377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
76378  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
76379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
76380  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
76381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
76382  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
76383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
76384  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
76385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
76386  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
76387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
76388  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
76389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
76390  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
76391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
76392  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
76393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
76394  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
76395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
76396  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
76397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
76398  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
76399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
76400  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
76401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
76402  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
76403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
76404  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
76405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
76406  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
76407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
76408  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
76409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
76410  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
76411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
76412  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
76413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
76414  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
76415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
76416  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
76417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
76418  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
76419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
76420  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
76421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
76422  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
76423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
76424  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
76425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
76426  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
76427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
76428  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
76429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
76430  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
76431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
76432  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
76433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
76434  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
76435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
76436  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
76437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
76438  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
76439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
76440  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
76441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
76442  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
76443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
76444  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
76445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
76446  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
76447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
76448  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
76449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
76450  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
76451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
76452  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
76453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
76454  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
76455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
76456  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
76457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
76458  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
76459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
76460  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
76461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
76462  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
76463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
76464  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
76465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
76466  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
76467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
76468  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
76469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
76470  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
76471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
76472  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
76473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
76474  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
76475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
76476  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
76477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
76478  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
76479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
76480  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
76481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
76482  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
76483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
76484  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
76485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
76486  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
76487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
76488  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
76489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
76490  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
76491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
76492  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
76493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
76494  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
76495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
76496  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
76497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
76498  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
76499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
76500  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
76501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
76502  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
76503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
76504  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
76505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
76506  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
76507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
76508  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
76509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
76510  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
76511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
76512  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
76513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
76514  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
76515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
76516  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
76517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
76518  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
76519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
76520  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
76521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
76522  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
76523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
76524  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
76525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
76526  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
76527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
76528  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
76529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
76530  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
76531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
76532  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
76533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
76534  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
76535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
76536  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
76537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
76538  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
76539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
76540  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
76541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
76542  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
76543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
76544  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
76545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
76546  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
76547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
76548  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
76549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
76550  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
76551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
76552  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
76553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
76554  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
76555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
76556  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
76557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
76558  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
76559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
76560  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
76561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
76562  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
76563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
76564  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
76565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
76566  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
76567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
76568  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
76569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
76570  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
76571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
76572  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
76573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
76574  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
76575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
76576  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
76577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
76578  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
76579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
76580  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
76581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
76582  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
76583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
76584  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
76585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
76586  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
76587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
76588  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
76589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
76590  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
76591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
76592  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
76593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
76594  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
76595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
76596  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
76597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
76598  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
76599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
76600  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
76601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
76602  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
76603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
76604  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
76605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
76606  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
76607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
76608  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
76609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
76610  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
76611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
76612  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
76613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
76614  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
76615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
76616  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
76617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
76618  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
76619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
76620  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
76621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
76622  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
76623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
76624  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
76625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
76626  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
76627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
76628  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
76629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
76630  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
76631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
76632  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
76633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
76634  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
76635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
76636  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
76637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
76638  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
76639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
76640  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
76641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
76642  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
76643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
76644  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
76645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
76646  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
76647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
76648  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
76649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
76650  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
76651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
76652  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
76653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
76654  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
76655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
76656  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
76657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
76658  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
76659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
76660  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
76661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
76662  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
76663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
76664  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
76665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
76666  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
76667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
76668  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
76669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
76670  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
76671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
76672  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
76673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
76674  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
76675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
76676  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
76677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
76678  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
76679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
76680  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
76681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
76682  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
76683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
76684  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
76685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
76686  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
76687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
76688  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
76689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
76690  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
76691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
76692  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
76693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
76694  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
76695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
76696  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
76697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
76698  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
76699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
76700  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
76701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
76702  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
76703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
76704  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
76705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
76706  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
76707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
76708  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
76709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
76710  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
76711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
76712  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
76713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
76714  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
76715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
76716  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
76717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
76718  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
76719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
76720  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
76721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
76722  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
76723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
76724  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
76725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
76726  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
76727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
76728  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
76729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
76730  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
76731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
76732  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
76733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
76734  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
76735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
76736  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
76737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
76738  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
76739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
76740  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
76741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
76742  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
76743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
76744  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
76745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
76746  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
76747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
76748  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
76749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
76750  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
76751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
76752  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
76753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
76754  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
76755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
76756  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
76757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
76758  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
76759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
76760  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
76761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
76762  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
76763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
76764  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
76765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
76766  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
76767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
76768  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
76769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
76770  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
76771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
76772  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
76773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
76774  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
76775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
76776  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
76777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
76778  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
76779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
76780  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
76781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
76782  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
76783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
76784  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
76785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
76786  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
76787 };
76788 
76794 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
76795 {
76796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
76797  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
76798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
76799  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
76800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
76801  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
76802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
76803  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
76804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
76805  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
76806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
76807  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
76808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
76809  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
76810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
76811  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
76812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
76813  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
76814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
76815  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
76816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
76817  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
76818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
76819  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
76820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
76821  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
76822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
76823  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
76824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
76825  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
76826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
76827  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
76828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
76829  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
76830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
76831  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
76832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
76833  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
76834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
76835  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
76836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
76837  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
76838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
76839  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
76840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
76841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
76842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
76843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
76844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
76845  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
76846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
76847  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
76848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
76849  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
76850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
76851  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
76852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
76853  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
76854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
76855  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
76856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
76857  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
76858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
76859  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
76860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
76861  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
76862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
76863  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
76864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
76865  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
76866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
76867  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
76868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
76869  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
76870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
76871  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
76872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
76873  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
76874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
76875  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
76876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
76877  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
76878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
76879  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
76880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
76881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
76882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
76883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
76884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
76885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
76886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
76887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
76888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
76889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
76890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
76891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
76892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
76893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
76894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
76895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
76896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
76897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
76898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
76899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
76900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
76901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
76902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
76903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
76904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
76905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
76906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
76907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
76908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
76909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
76910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
76911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
76912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
76913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
76914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
76915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
76916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
76917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
76918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
76919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
76920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
76921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
76922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
76923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
76924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
76925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
76926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
76927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
76928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
76929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
76930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
76931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
76932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
76933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
76934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
76935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
76936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
76937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
76938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
76939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
76940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
76941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
76942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
76943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
76944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
76945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
76946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
76947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
76948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
76949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
76950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
76951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
76952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
76953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
76954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
76955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
76956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
76957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
76958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
76959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
76960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
76961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
76962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
76963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
76964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
76965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
76966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
76967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
76968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
76969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
76970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
76971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
76972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
76973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
76974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
76975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
76976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
76977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
76978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
76979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
76980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
76981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
76982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
76983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
76984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
76985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
76986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
76987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
76988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
76989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
76990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
76991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
76992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
76993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
76994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
76995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
76996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
76997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
76998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
76999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
77000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
77001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
77002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
77003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
77004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
77005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
77006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
77007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
77008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
77009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
77010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
77011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
77012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
77013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
77014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
77015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
77016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
77017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
77018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
77019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
77020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
77021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
77022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
77023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
77024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
77025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
77026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
77027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
77028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
77029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
77030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
77031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
77032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
77033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
77034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
77035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
77036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
77037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
77038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
77039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
77040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
77041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
77042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
77043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
77044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
77045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
77046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
77047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
77048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
77049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
77050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
77051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
77052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
77053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
77054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
77055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
77056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
77057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
77058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
77059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
77060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
77061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
77062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
77063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
77064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
77065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
77066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
77067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
77068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
77069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
77070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
77071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
77072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
77073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
77074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
77075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
77076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
77077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
77078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
77079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
77080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
77081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
77082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
77083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
77084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
77085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
77086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
77087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
77088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
77089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
77090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
77091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
77092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
77093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
77094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
77095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
77096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
77097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
77098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
77099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
77100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
77101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
77102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
77103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
77104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
77105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
77106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
77107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
77108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
77109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
77110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
77111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
77112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
77113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
77114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
77115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
77116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
77117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
77118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
77119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
77120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
77121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
77122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
77123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
77124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
77125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
77126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
77127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
77128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
77129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
77130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
77131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
77132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
77133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
77134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
77135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
77136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
77137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
77138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
77139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
77140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
77141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
77142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
77143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
77144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
77145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
77146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
77147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
77148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
77149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
77150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
77151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
77152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
77153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
77154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
77155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
77156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
77157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
77158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
77159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
77160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
77161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
77162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
77163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
77164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
77165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
77166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
77167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
77168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
77169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
77170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
77171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
77172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
77173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
77174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
77175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
77176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
77177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
77178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
77179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
77180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
77181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
77182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
77183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
77184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
77185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
77186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
77187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
77188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
77189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
77190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
77191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
77192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
77193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
77194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
77195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
77196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
77197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
77198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
77199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
77200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
77201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
77202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
77203  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
77204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
77205  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
77206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
77207  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
77208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
77209  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
77210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
77211  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
77212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
77213  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
77214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
77215  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
77216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
77217  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
77218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
77219  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
77220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
77221  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
77222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
77223  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
77224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
77225  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
77226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
77227  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
77228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
77229  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
77230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
77231  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
77232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
77233  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
77234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
77235  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
77236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
77237  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
77238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
77239  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
77240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
77241  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
77242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
77243  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
77244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
77245  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
77246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
77247  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
77248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
77249  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
77250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
77251  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
77252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
77253  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
77254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
77255  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
77256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
77257  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
77258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
77259  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
77260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
77261  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
77262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
77263  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
77264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
77265  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
77266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
77267  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
77268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
77269  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
77270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
77271  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
77272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
77273  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
77274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
77275  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
77276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
77277  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
77278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
77279  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
77280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
77281  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
77282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
77283  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
77284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
77285  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
77286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
77287  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
77288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
77289  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
77290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
77291  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
77292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
77293  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
77294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
77295  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
77296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
77297  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
77298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
77299  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
77300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
77301  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
77302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
77303  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
77304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
77305  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
77306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
77307  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
77308 };
77309 
77315 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
77316 {
77317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
77318  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
77319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
77320  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
77321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
77322  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
77323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
77324  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
77325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
77326  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
77327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
77328  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
77329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
77330  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
77331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
77332  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
77333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
77334  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
77335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
77336  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
77337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
77338  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
77339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
77340  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
77341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
77342  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
77343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
77344  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
77345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
77346  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
77347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
77348  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
77349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
77350  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
77351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
77352  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
77353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
77354  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
77355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
77356  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
77357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
77358  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
77359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
77360  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
77361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
77362  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
77363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
77364  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
77365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
77366  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
77367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
77368  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
77369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
77370  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
77371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
77372  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
77373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
77374  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
77375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
77376  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
77377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
77378  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
77379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
77380  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
77381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
77382  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
77383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
77384  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
77385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
77386  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
77387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
77388  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
77389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
77390  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
77391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
77392  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
77393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
77394  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
77395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
77396  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
77397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
77398  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
77399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
77400  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
77401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
77402  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
77403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
77404  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
77405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
77406  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
77407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
77408  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
77409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
77410  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
77411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
77412  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
77413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
77414  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
77415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
77416  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
77417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
77418  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
77419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
77420  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
77421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
77422  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
77423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
77424  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
77425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
77426  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
77427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
77428  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
77429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
77430  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
77431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
77432  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
77433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
77434  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
77435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
77436  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
77437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
77438  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
77439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
77440  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
77441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
77442  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
77443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
77444  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
77445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
77446  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
77447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
77448  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
77449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
77450  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
77451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
77452  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
77453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
77454  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
77455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
77456  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
77457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
77458  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
77459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
77460  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
77461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
77462  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
77463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
77464  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
77465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
77466  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
77467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
77468  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
77469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
77470  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
77471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
77472  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
77473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
77474  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
77475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
77476  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
77477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
77478  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
77479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
77480  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
77481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
77482  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
77483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
77484  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
77485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
77486  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
77487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
77488  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
77489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
77490  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
77491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
77492  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
77493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
77494  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
77495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
77496  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
77497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
77498  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
77499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
77500  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
77501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
77502  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
77503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
77504  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
77505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
77506  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
77507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
77508  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
77509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
77510  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
77511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
77512  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
77513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
77514  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
77515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
77516  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
77517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
77518  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
77519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
77520  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
77521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
77522  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
77523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
77524  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
77525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
77526  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
77527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
77528  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
77529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
77530  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
77531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
77532  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
77533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
77534  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
77535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
77536  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
77537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
77538  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
77539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
77540  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
77541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
77542  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
77543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
77544  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
77545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
77546  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
77547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
77548  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
77549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
77550  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
77551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
77552  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
77553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
77554  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
77555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
77556  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
77557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
77558  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
77559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
77560  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
77561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
77562  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
77563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
77564  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
77565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
77566  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
77567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
77568  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
77569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
77570  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
77571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
77572  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
77573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
77574  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
77575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
77576  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
77577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
77578  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
77579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
77580  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
77581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
77582  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
77583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
77584  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
77585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
77586  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
77587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
77588  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
77589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
77590  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
77591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
77592  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
77593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
77594  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
77595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
77596  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
77597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
77598  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
77599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
77600  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
77601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
77602  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
77603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
77604  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
77605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
77606  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
77607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
77608  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
77609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
77610  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
77611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
77612  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
77613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
77614  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
77615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
77616  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
77617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
77618  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
77619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
77620  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
77621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
77622  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
77623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
77624  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
77625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
77626  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
77627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
77628  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
77629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
77630  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
77631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
77632  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
77633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
77634  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
77635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
77636  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
77637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
77638  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
77639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
77640  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
77641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
77642  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
77643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
77644  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
77645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
77646  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
77647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
77648  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
77649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
77650  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
77651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
77652  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
77653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
77654  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
77655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
77656  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
77657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
77658  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
77659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
77660  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
77661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
77662  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
77663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
77664  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
77665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
77666  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
77667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
77668  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
77669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
77670  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
77671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
77672  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
77673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
77674  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
77675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
77676  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
77677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
77678  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
77679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
77680  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
77681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
77682  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
77683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
77684  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
77685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
77686  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
77687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
77688  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
77689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
77690  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
77691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_187_CHECKER_TYPE,
77692  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_187_WIDTH },
77693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_188_CHECKER_TYPE,
77694  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_188_WIDTH },
77695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_189_CHECKER_TYPE,
77696  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_189_WIDTH },
77697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_190_CHECKER_TYPE,
77698  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_190_WIDTH },
77699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_191_CHECKER_TYPE,
77700  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_191_WIDTH },
77701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_192_CHECKER_TYPE,
77702  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_192_WIDTH },
77703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_193_CHECKER_TYPE,
77704  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_193_WIDTH },
77705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_194_CHECKER_TYPE,
77706  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_194_WIDTH },
77707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_195_CHECKER_TYPE,
77708  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_195_WIDTH },
77709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_196_CHECKER_TYPE,
77710  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_196_WIDTH },
77711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_197_CHECKER_TYPE,
77712  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_197_WIDTH },
77713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_198_CHECKER_TYPE,
77714  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_198_WIDTH },
77715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_199_CHECKER_TYPE,
77716  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_199_WIDTH },
77717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_200_CHECKER_TYPE,
77718  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_200_WIDTH },
77719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_201_CHECKER_TYPE,
77720  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_201_WIDTH },
77721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_202_CHECKER_TYPE,
77722  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_202_WIDTH },
77723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_203_CHECKER_TYPE,
77724  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_203_WIDTH },
77725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_204_CHECKER_TYPE,
77726  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_204_WIDTH },
77727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_205_CHECKER_TYPE,
77728  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_205_WIDTH },
77729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_206_CHECKER_TYPE,
77730  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_206_WIDTH },
77731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_207_CHECKER_TYPE,
77732  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_207_WIDTH },
77733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_208_CHECKER_TYPE,
77734  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_208_WIDTH },
77735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_209_CHECKER_TYPE,
77736  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_209_WIDTH },
77737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_210_CHECKER_TYPE,
77738  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_210_WIDTH },
77739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_211_CHECKER_TYPE,
77740  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_211_WIDTH },
77741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_212_CHECKER_TYPE,
77742  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_212_WIDTH },
77743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_213_CHECKER_TYPE,
77744  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_213_WIDTH },
77745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_214_CHECKER_TYPE,
77746  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_214_WIDTH },
77747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_215_CHECKER_TYPE,
77748  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_215_WIDTH },
77749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_216_CHECKER_TYPE,
77750  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_216_WIDTH },
77751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_217_CHECKER_TYPE,
77752  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_217_WIDTH },
77753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_218_CHECKER_TYPE,
77754  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_218_WIDTH },
77755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_219_CHECKER_TYPE,
77756  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_219_WIDTH },
77757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_220_CHECKER_TYPE,
77758  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_220_WIDTH },
77759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_221_CHECKER_TYPE,
77760  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_221_WIDTH },
77761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_222_CHECKER_TYPE,
77762  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_222_WIDTH },
77763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_223_CHECKER_TYPE,
77764  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_223_WIDTH },
77765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_224_CHECKER_TYPE,
77766  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_224_WIDTH },
77767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_225_CHECKER_TYPE,
77768  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_225_WIDTH },
77769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_226_CHECKER_TYPE,
77770  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_226_WIDTH },
77771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_227_CHECKER_TYPE,
77772  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_227_WIDTH },
77773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_228_CHECKER_TYPE,
77774  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_228_WIDTH },
77775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_229_CHECKER_TYPE,
77776  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_229_WIDTH },
77777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_230_CHECKER_TYPE,
77778  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_230_WIDTH },
77779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_231_CHECKER_TYPE,
77780  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_231_WIDTH },
77781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_232_CHECKER_TYPE,
77782  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_232_WIDTH },
77783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_233_CHECKER_TYPE,
77784  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_233_WIDTH },
77785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_234_CHECKER_TYPE,
77786  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_234_WIDTH },
77787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_235_CHECKER_TYPE,
77788  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_235_WIDTH },
77789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_236_CHECKER_TYPE,
77790  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_236_WIDTH },
77791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_237_CHECKER_TYPE,
77792  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_237_WIDTH },
77793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_238_CHECKER_TYPE,
77794  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_238_WIDTH },
77795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_239_CHECKER_TYPE,
77796  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_239_WIDTH },
77797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_240_CHECKER_TYPE,
77798  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_240_WIDTH },
77799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_241_CHECKER_TYPE,
77800  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_241_WIDTH },
77801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_242_CHECKER_TYPE,
77802  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_242_WIDTH },
77803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_243_CHECKER_TYPE,
77804  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_243_WIDTH },
77805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_244_CHECKER_TYPE,
77806  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_244_WIDTH },
77807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_245_CHECKER_TYPE,
77808  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_245_WIDTH },
77809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_246_CHECKER_TYPE,
77810  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_246_WIDTH },
77811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_247_CHECKER_TYPE,
77812  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_247_WIDTH },
77813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_248_CHECKER_TYPE,
77814  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_248_WIDTH },
77815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_249_CHECKER_TYPE,
77816  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_249_WIDTH },
77817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_250_CHECKER_TYPE,
77818  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_250_WIDTH },
77819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_251_CHECKER_TYPE,
77820  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_251_WIDTH },
77821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_252_CHECKER_TYPE,
77822  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_252_WIDTH },
77823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_253_CHECKER_TYPE,
77824  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_253_WIDTH },
77825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_254_CHECKER_TYPE,
77826  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_254_WIDTH },
77827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_255_CHECKER_TYPE,
77828  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_GROUP_255_WIDTH },
77829 };
77830 
77836 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS] =
77837 {
77838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_0_CHECKER_TYPE,
77839  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_0_WIDTH },
77840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_1_CHECKER_TYPE,
77841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_1_WIDTH },
77842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_2_CHECKER_TYPE,
77843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_2_WIDTH },
77844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_3_CHECKER_TYPE,
77845  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_3_WIDTH },
77846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_4_CHECKER_TYPE,
77847  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_4_WIDTH },
77848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_5_CHECKER_TYPE,
77849  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_5_WIDTH },
77850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_6_CHECKER_TYPE,
77851  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_6_WIDTH },
77852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_7_CHECKER_TYPE,
77853  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_7_WIDTH },
77854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_8_CHECKER_TYPE,
77855  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_8_WIDTH },
77856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_9_CHECKER_TYPE,
77857  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_9_WIDTH },
77858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_10_CHECKER_TYPE,
77859  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_10_WIDTH },
77860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_11_CHECKER_TYPE,
77861  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_11_WIDTH },
77862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_12_CHECKER_TYPE,
77863  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_12_WIDTH },
77864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_13_CHECKER_TYPE,
77865  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_13_WIDTH },
77866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_14_CHECKER_TYPE,
77867  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_14_WIDTH },
77868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_15_CHECKER_TYPE,
77869  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_15_WIDTH },
77870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_16_CHECKER_TYPE,
77871  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_16_WIDTH },
77872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_17_CHECKER_TYPE,
77873  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_17_WIDTH },
77874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_18_CHECKER_TYPE,
77875  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_18_WIDTH },
77876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_19_CHECKER_TYPE,
77877  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_19_WIDTH },
77878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_20_CHECKER_TYPE,
77879  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_20_WIDTH },
77880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_21_CHECKER_TYPE,
77881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_21_WIDTH },
77882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_22_CHECKER_TYPE,
77883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_22_WIDTH },
77884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_23_CHECKER_TYPE,
77885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_23_WIDTH },
77886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_24_CHECKER_TYPE,
77887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_24_WIDTH },
77888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_25_CHECKER_TYPE,
77889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_25_WIDTH },
77890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_26_CHECKER_TYPE,
77891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_26_WIDTH },
77892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_27_CHECKER_TYPE,
77893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_27_WIDTH },
77894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_28_CHECKER_TYPE,
77895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_28_WIDTH },
77896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_29_CHECKER_TYPE,
77897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_29_WIDTH },
77898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_30_CHECKER_TYPE,
77899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_30_WIDTH },
77900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_31_CHECKER_TYPE,
77901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_31_WIDTH },
77902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_32_CHECKER_TYPE,
77903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_32_WIDTH },
77904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_33_CHECKER_TYPE,
77905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_33_WIDTH },
77906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_34_CHECKER_TYPE,
77907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_34_WIDTH },
77908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_35_CHECKER_TYPE,
77909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_35_WIDTH },
77910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_36_CHECKER_TYPE,
77911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_36_WIDTH },
77912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_37_CHECKER_TYPE,
77913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_37_WIDTH },
77914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_38_CHECKER_TYPE,
77915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_38_WIDTH },
77916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_39_CHECKER_TYPE,
77917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_39_WIDTH },
77918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_40_CHECKER_TYPE,
77919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_40_WIDTH },
77920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_41_CHECKER_TYPE,
77921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_41_WIDTH },
77922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_42_CHECKER_TYPE,
77923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_42_WIDTH },
77924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_43_CHECKER_TYPE,
77925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_43_WIDTH },
77926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_44_CHECKER_TYPE,
77927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_44_WIDTH },
77928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_45_CHECKER_TYPE,
77929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_45_WIDTH },
77930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_46_CHECKER_TYPE,
77931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_46_WIDTH },
77932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_47_CHECKER_TYPE,
77933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_47_WIDTH },
77934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_48_CHECKER_TYPE,
77935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_48_WIDTH },
77936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_49_CHECKER_TYPE,
77937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_49_WIDTH },
77938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_50_CHECKER_TYPE,
77939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_50_WIDTH },
77940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_51_CHECKER_TYPE,
77941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_51_WIDTH },
77942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_52_CHECKER_TYPE,
77943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_52_WIDTH },
77944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_53_CHECKER_TYPE,
77945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_53_WIDTH },
77946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_54_CHECKER_TYPE,
77947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_54_WIDTH },
77948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_55_CHECKER_TYPE,
77949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_55_WIDTH },
77950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_56_CHECKER_TYPE,
77951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_56_WIDTH },
77952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_57_CHECKER_TYPE,
77953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_57_WIDTH },
77954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_58_CHECKER_TYPE,
77955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_58_WIDTH },
77956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_59_CHECKER_TYPE,
77957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_59_WIDTH },
77958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_60_CHECKER_TYPE,
77959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_60_WIDTH },
77960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_61_CHECKER_TYPE,
77961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_61_WIDTH },
77962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_62_CHECKER_TYPE,
77963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_62_WIDTH },
77964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_63_CHECKER_TYPE,
77965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_63_WIDTH },
77966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_64_CHECKER_TYPE,
77967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_64_WIDTH },
77968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_65_CHECKER_TYPE,
77969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_65_WIDTH },
77970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_66_CHECKER_TYPE,
77971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_66_WIDTH },
77972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_67_CHECKER_TYPE,
77973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_67_WIDTH },
77974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_68_CHECKER_TYPE,
77975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_68_WIDTH },
77976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_69_CHECKER_TYPE,
77977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_69_WIDTH },
77978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_70_CHECKER_TYPE,
77979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_70_WIDTH },
77980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_71_CHECKER_TYPE,
77981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_71_WIDTH },
77982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_72_CHECKER_TYPE,
77983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_72_WIDTH },
77984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_73_CHECKER_TYPE,
77985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_73_WIDTH },
77986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_74_CHECKER_TYPE,
77987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_74_WIDTH },
77988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_75_CHECKER_TYPE,
77989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_75_WIDTH },
77990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_76_CHECKER_TYPE,
77991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_76_WIDTH },
77992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_77_CHECKER_TYPE,
77993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_77_WIDTH },
77994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_78_CHECKER_TYPE,
77995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_78_WIDTH },
77996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_79_CHECKER_TYPE,
77997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_79_WIDTH },
77998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_80_CHECKER_TYPE,
77999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_80_WIDTH },
78000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_81_CHECKER_TYPE,
78001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_81_WIDTH },
78002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_82_CHECKER_TYPE,
78003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_82_WIDTH },
78004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_83_CHECKER_TYPE,
78005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_83_WIDTH },
78006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_84_CHECKER_TYPE,
78007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_84_WIDTH },
78008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_85_CHECKER_TYPE,
78009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_85_WIDTH },
78010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_86_CHECKER_TYPE,
78011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_86_WIDTH },
78012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_87_CHECKER_TYPE,
78013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_87_WIDTH },
78014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_88_CHECKER_TYPE,
78015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_88_WIDTH },
78016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_89_CHECKER_TYPE,
78017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_89_WIDTH },
78018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_90_CHECKER_TYPE,
78019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_90_WIDTH },
78020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_91_CHECKER_TYPE,
78021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_91_WIDTH },
78022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_92_CHECKER_TYPE,
78023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_92_WIDTH },
78024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_93_CHECKER_TYPE,
78025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_93_WIDTH },
78026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_94_CHECKER_TYPE,
78027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_94_WIDTH },
78028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_95_CHECKER_TYPE,
78029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_95_WIDTH },
78030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_96_CHECKER_TYPE,
78031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_96_WIDTH },
78032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_97_CHECKER_TYPE,
78033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_97_WIDTH },
78034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_98_CHECKER_TYPE,
78035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_98_WIDTH },
78036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_99_CHECKER_TYPE,
78037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_99_WIDTH },
78038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_100_CHECKER_TYPE,
78039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_100_WIDTH },
78040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_101_CHECKER_TYPE,
78041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_101_WIDTH },
78042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_102_CHECKER_TYPE,
78043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_102_WIDTH },
78044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_103_CHECKER_TYPE,
78045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_103_WIDTH },
78046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_104_CHECKER_TYPE,
78047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_104_WIDTH },
78048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_105_CHECKER_TYPE,
78049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_105_WIDTH },
78050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_106_CHECKER_TYPE,
78051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_106_WIDTH },
78052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_107_CHECKER_TYPE,
78053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_107_WIDTH },
78054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_108_CHECKER_TYPE,
78055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_108_WIDTH },
78056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_109_CHECKER_TYPE,
78057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_109_WIDTH },
78058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_110_CHECKER_TYPE,
78059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_110_WIDTH },
78060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_111_CHECKER_TYPE,
78061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_111_WIDTH },
78062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_112_CHECKER_TYPE,
78063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_112_WIDTH },
78064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_113_CHECKER_TYPE,
78065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_113_WIDTH },
78066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_114_CHECKER_TYPE,
78067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_114_WIDTH },
78068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_115_CHECKER_TYPE,
78069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_115_WIDTH },
78070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_116_CHECKER_TYPE,
78071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_116_WIDTH },
78072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_117_CHECKER_TYPE,
78073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_117_WIDTH },
78074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_118_CHECKER_TYPE,
78075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_118_WIDTH },
78076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_119_CHECKER_TYPE,
78077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_119_WIDTH },
78078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_120_CHECKER_TYPE,
78079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_120_WIDTH },
78080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_121_CHECKER_TYPE,
78081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_121_WIDTH },
78082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_122_CHECKER_TYPE,
78083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_122_WIDTH },
78084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_123_CHECKER_TYPE,
78085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_123_WIDTH },
78086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_124_CHECKER_TYPE,
78087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_124_WIDTH },
78088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_125_CHECKER_TYPE,
78089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_125_WIDTH },
78090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_126_CHECKER_TYPE,
78091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_126_WIDTH },
78092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_127_CHECKER_TYPE,
78093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_127_WIDTH },
78094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_128_CHECKER_TYPE,
78095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_128_WIDTH },
78096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_129_CHECKER_TYPE,
78097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_129_WIDTH },
78098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_130_CHECKER_TYPE,
78099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_130_WIDTH },
78100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_131_CHECKER_TYPE,
78101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_131_WIDTH },
78102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_132_CHECKER_TYPE,
78103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_132_WIDTH },
78104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_133_CHECKER_TYPE,
78105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_133_WIDTH },
78106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_134_CHECKER_TYPE,
78107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_134_WIDTH },
78108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_135_CHECKER_TYPE,
78109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_135_WIDTH },
78110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_136_CHECKER_TYPE,
78111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_136_WIDTH },
78112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_137_CHECKER_TYPE,
78113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_137_WIDTH },
78114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_138_CHECKER_TYPE,
78115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_138_WIDTH },
78116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_139_CHECKER_TYPE,
78117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_139_WIDTH },
78118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_140_CHECKER_TYPE,
78119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_140_WIDTH },
78120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_141_CHECKER_TYPE,
78121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_141_WIDTH },
78122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_142_CHECKER_TYPE,
78123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_142_WIDTH },
78124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_143_CHECKER_TYPE,
78125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_143_WIDTH },
78126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_144_CHECKER_TYPE,
78127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_144_WIDTH },
78128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_145_CHECKER_TYPE,
78129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_145_WIDTH },
78130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_146_CHECKER_TYPE,
78131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_146_WIDTH },
78132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_147_CHECKER_TYPE,
78133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_147_WIDTH },
78134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_148_CHECKER_TYPE,
78135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_148_WIDTH },
78136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_149_CHECKER_TYPE,
78137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_149_WIDTH },
78138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_150_CHECKER_TYPE,
78139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_150_WIDTH },
78140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_151_CHECKER_TYPE,
78141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_151_WIDTH },
78142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_152_CHECKER_TYPE,
78143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_152_WIDTH },
78144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_153_CHECKER_TYPE,
78145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_153_WIDTH },
78146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_154_CHECKER_TYPE,
78147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_154_WIDTH },
78148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_155_CHECKER_TYPE,
78149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_155_WIDTH },
78150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_156_CHECKER_TYPE,
78151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_156_WIDTH },
78152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_157_CHECKER_TYPE,
78153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_157_WIDTH },
78154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_158_CHECKER_TYPE,
78155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_158_WIDTH },
78156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_159_CHECKER_TYPE,
78157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_159_WIDTH },
78158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_160_CHECKER_TYPE,
78159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_160_WIDTH },
78160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_161_CHECKER_TYPE,
78161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_161_WIDTH },
78162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_162_CHECKER_TYPE,
78163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_162_WIDTH },
78164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_163_CHECKER_TYPE,
78165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_163_WIDTH },
78166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_164_CHECKER_TYPE,
78167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_164_WIDTH },
78168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_165_CHECKER_TYPE,
78169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_165_WIDTH },
78170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_166_CHECKER_TYPE,
78171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_166_WIDTH },
78172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_167_CHECKER_TYPE,
78173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_167_WIDTH },
78174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_168_CHECKER_TYPE,
78175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_168_WIDTH },
78176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_169_CHECKER_TYPE,
78177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_169_WIDTH },
78178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_170_CHECKER_TYPE,
78179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_170_WIDTH },
78180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_171_CHECKER_TYPE,
78181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_171_WIDTH },
78182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_172_CHECKER_TYPE,
78183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_172_WIDTH },
78184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_173_CHECKER_TYPE,
78185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_173_WIDTH },
78186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_174_CHECKER_TYPE,
78187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_174_WIDTH },
78188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_175_CHECKER_TYPE,
78189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_175_WIDTH },
78190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_176_CHECKER_TYPE,
78191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_176_WIDTH },
78192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_177_CHECKER_TYPE,
78193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_177_WIDTH },
78194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_178_CHECKER_TYPE,
78195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_178_WIDTH },
78196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_179_CHECKER_TYPE,
78197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_179_WIDTH },
78198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_180_CHECKER_TYPE,
78199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_180_WIDTH },
78200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_181_CHECKER_TYPE,
78201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_181_WIDTH },
78202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_182_CHECKER_TYPE,
78203  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_182_WIDTH },
78204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_183_CHECKER_TYPE,
78205  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_183_WIDTH },
78206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_184_CHECKER_TYPE,
78207  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_184_WIDTH },
78208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_185_CHECKER_TYPE,
78209  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_185_WIDTH },
78210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_186_CHECKER_TYPE,
78211  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_186_WIDTH },
78212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_187_CHECKER_TYPE,
78213  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_187_WIDTH },
78214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_188_CHECKER_TYPE,
78215  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_188_WIDTH },
78216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_189_CHECKER_TYPE,
78217  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_189_WIDTH },
78218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_190_CHECKER_TYPE,
78219  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_190_WIDTH },
78220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_191_CHECKER_TYPE,
78221  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_191_WIDTH },
78222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_192_CHECKER_TYPE,
78223  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_192_WIDTH },
78224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_193_CHECKER_TYPE,
78225  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_193_WIDTH },
78226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_194_CHECKER_TYPE,
78227  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_194_WIDTH },
78228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_195_CHECKER_TYPE,
78229  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_195_WIDTH },
78230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_196_CHECKER_TYPE,
78231  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_196_WIDTH },
78232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_197_CHECKER_TYPE,
78233  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_197_WIDTH },
78234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_198_CHECKER_TYPE,
78235  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_198_WIDTH },
78236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_199_CHECKER_TYPE,
78237  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_199_WIDTH },
78238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_200_CHECKER_TYPE,
78239  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_200_WIDTH },
78240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_201_CHECKER_TYPE,
78241  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_201_WIDTH },
78242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_202_CHECKER_TYPE,
78243  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_202_WIDTH },
78244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_203_CHECKER_TYPE,
78245  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_203_WIDTH },
78246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_204_CHECKER_TYPE,
78247  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_204_WIDTH },
78248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_205_CHECKER_TYPE,
78249  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_205_WIDTH },
78250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_206_CHECKER_TYPE,
78251  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_206_WIDTH },
78252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_207_CHECKER_TYPE,
78253  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_207_WIDTH },
78254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_208_CHECKER_TYPE,
78255  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_208_WIDTH },
78256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_209_CHECKER_TYPE,
78257  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_209_WIDTH },
78258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_210_CHECKER_TYPE,
78259  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_210_WIDTH },
78260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_211_CHECKER_TYPE,
78261  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_211_WIDTH },
78262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_212_CHECKER_TYPE,
78263  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_212_WIDTH },
78264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_213_CHECKER_TYPE,
78265  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_213_WIDTH },
78266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_214_CHECKER_TYPE,
78267  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_214_WIDTH },
78268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_215_CHECKER_TYPE,
78269  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_215_WIDTH },
78270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_216_CHECKER_TYPE,
78271  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_216_WIDTH },
78272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_217_CHECKER_TYPE,
78273  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_217_WIDTH },
78274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_218_CHECKER_TYPE,
78275  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_218_WIDTH },
78276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_219_CHECKER_TYPE,
78277  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_219_WIDTH },
78278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_220_CHECKER_TYPE,
78279  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_220_WIDTH },
78280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_221_CHECKER_TYPE,
78281  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_221_WIDTH },
78282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_222_CHECKER_TYPE,
78283  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_222_WIDTH },
78284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_223_CHECKER_TYPE,
78285  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_223_WIDTH },
78286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_224_CHECKER_TYPE,
78287  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_224_WIDTH },
78288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_225_CHECKER_TYPE,
78289  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_225_WIDTH },
78290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_226_CHECKER_TYPE,
78291  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_226_WIDTH },
78292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_227_CHECKER_TYPE,
78293  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_227_WIDTH },
78294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_228_CHECKER_TYPE,
78295  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_228_WIDTH },
78296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_229_CHECKER_TYPE,
78297  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_229_WIDTH },
78298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_230_CHECKER_TYPE,
78299  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_230_WIDTH },
78300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_231_CHECKER_TYPE,
78301  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_231_WIDTH },
78302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_232_CHECKER_TYPE,
78303  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_232_WIDTH },
78304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_233_CHECKER_TYPE,
78305  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_233_WIDTH },
78306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_234_CHECKER_TYPE,
78307  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_234_WIDTH },
78308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_235_CHECKER_TYPE,
78309  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_235_WIDTH },
78310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_236_CHECKER_TYPE,
78311  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_236_WIDTH },
78312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_237_CHECKER_TYPE,
78313  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_237_WIDTH },
78314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_238_CHECKER_TYPE,
78315  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_238_WIDTH },
78316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_239_CHECKER_TYPE,
78317  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_239_WIDTH },
78318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_240_CHECKER_TYPE,
78319  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_240_WIDTH },
78320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_241_CHECKER_TYPE,
78321  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_241_WIDTH },
78322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_242_CHECKER_TYPE,
78323  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_242_WIDTH },
78324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_243_CHECKER_TYPE,
78325  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_243_WIDTH },
78326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_244_CHECKER_TYPE,
78327  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_244_WIDTH },
78328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_245_CHECKER_TYPE,
78329  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_245_WIDTH },
78330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_246_CHECKER_TYPE,
78331  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_246_WIDTH },
78332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_247_CHECKER_TYPE,
78333  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_247_WIDTH },
78334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_248_CHECKER_TYPE,
78335  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_248_WIDTH },
78336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_249_CHECKER_TYPE,
78337  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_249_WIDTH },
78338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_250_CHECKER_TYPE,
78339  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_250_WIDTH },
78340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_251_CHECKER_TYPE,
78341  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_251_WIDTH },
78342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_252_CHECKER_TYPE,
78343  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_252_WIDTH },
78344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_253_CHECKER_TYPE,
78345  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_253_WIDTH },
78346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_254_CHECKER_TYPE,
78347  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_254_WIDTH },
78348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_255_CHECKER_TYPE,
78349  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_GROUP_255_WIDTH },
78350 };
78351 
78357 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS] =
78358 {
78359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_0_CHECKER_TYPE,
78360  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_0_WIDTH },
78361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_1_CHECKER_TYPE,
78362  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_1_WIDTH },
78363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_2_CHECKER_TYPE,
78364  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_2_WIDTH },
78365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_3_CHECKER_TYPE,
78366  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_3_WIDTH },
78367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_4_CHECKER_TYPE,
78368  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_4_WIDTH },
78369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_5_CHECKER_TYPE,
78370  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_5_WIDTH },
78371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_6_CHECKER_TYPE,
78372  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_6_WIDTH },
78373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_7_CHECKER_TYPE,
78374  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_7_WIDTH },
78375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_8_CHECKER_TYPE,
78376  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_8_WIDTH },
78377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_9_CHECKER_TYPE,
78378  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_9_WIDTH },
78379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_10_CHECKER_TYPE,
78380  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_10_WIDTH },
78381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_11_CHECKER_TYPE,
78382  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_11_WIDTH },
78383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_12_CHECKER_TYPE,
78384  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_12_WIDTH },
78385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_13_CHECKER_TYPE,
78386  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_13_WIDTH },
78387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_14_CHECKER_TYPE,
78388  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_14_WIDTH },
78389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_15_CHECKER_TYPE,
78390  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_15_WIDTH },
78391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_16_CHECKER_TYPE,
78392  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_16_WIDTH },
78393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_17_CHECKER_TYPE,
78394  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_17_WIDTH },
78395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_18_CHECKER_TYPE,
78396  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_18_WIDTH },
78397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_19_CHECKER_TYPE,
78398  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_19_WIDTH },
78399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_20_CHECKER_TYPE,
78400  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_20_WIDTH },
78401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_21_CHECKER_TYPE,
78402  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_21_WIDTH },
78403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_22_CHECKER_TYPE,
78404  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_22_WIDTH },
78405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_23_CHECKER_TYPE,
78406  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_23_WIDTH },
78407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_24_CHECKER_TYPE,
78408  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_24_WIDTH },
78409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_25_CHECKER_TYPE,
78410  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_25_WIDTH },
78411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_26_CHECKER_TYPE,
78412  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_26_WIDTH },
78413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_27_CHECKER_TYPE,
78414  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_27_WIDTH },
78415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_28_CHECKER_TYPE,
78416  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_28_WIDTH },
78417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_29_CHECKER_TYPE,
78418  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_29_WIDTH },
78419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_30_CHECKER_TYPE,
78420  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_30_WIDTH },
78421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_31_CHECKER_TYPE,
78422  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_31_WIDTH },
78423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_32_CHECKER_TYPE,
78424  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_32_WIDTH },
78425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_33_CHECKER_TYPE,
78426  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_33_WIDTH },
78427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_34_CHECKER_TYPE,
78428  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_34_WIDTH },
78429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_35_CHECKER_TYPE,
78430  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_35_WIDTH },
78431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_36_CHECKER_TYPE,
78432  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_36_WIDTH },
78433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_37_CHECKER_TYPE,
78434  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_37_WIDTH },
78435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_38_CHECKER_TYPE,
78436  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_38_WIDTH },
78437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_39_CHECKER_TYPE,
78438  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_39_WIDTH },
78439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_40_CHECKER_TYPE,
78440  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_40_WIDTH },
78441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_41_CHECKER_TYPE,
78442  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_41_WIDTH },
78443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_42_CHECKER_TYPE,
78444  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_42_WIDTH },
78445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_43_CHECKER_TYPE,
78446  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_43_WIDTH },
78447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_44_CHECKER_TYPE,
78448  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_44_WIDTH },
78449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_45_CHECKER_TYPE,
78450  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_45_WIDTH },
78451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_46_CHECKER_TYPE,
78452  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_46_WIDTH },
78453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_47_CHECKER_TYPE,
78454  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_47_WIDTH },
78455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_48_CHECKER_TYPE,
78456  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_48_WIDTH },
78457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_49_CHECKER_TYPE,
78458  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_49_WIDTH },
78459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_50_CHECKER_TYPE,
78460  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_50_WIDTH },
78461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_51_CHECKER_TYPE,
78462  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_51_WIDTH },
78463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_52_CHECKER_TYPE,
78464  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_52_WIDTH },
78465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_53_CHECKER_TYPE,
78466  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_53_WIDTH },
78467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_54_CHECKER_TYPE,
78468  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_54_WIDTH },
78469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_55_CHECKER_TYPE,
78470  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_55_WIDTH },
78471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_56_CHECKER_TYPE,
78472  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_56_WIDTH },
78473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_57_CHECKER_TYPE,
78474  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_57_WIDTH },
78475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_58_CHECKER_TYPE,
78476  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_58_WIDTH },
78477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_59_CHECKER_TYPE,
78478  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_59_WIDTH },
78479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_60_CHECKER_TYPE,
78480  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_60_WIDTH },
78481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_61_CHECKER_TYPE,
78482  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_61_WIDTH },
78483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_62_CHECKER_TYPE,
78484  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_62_WIDTH },
78485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_63_CHECKER_TYPE,
78486  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_63_WIDTH },
78487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_64_CHECKER_TYPE,
78488  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_64_WIDTH },
78489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_65_CHECKER_TYPE,
78490  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_65_WIDTH },
78491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_66_CHECKER_TYPE,
78492  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_66_WIDTH },
78493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_67_CHECKER_TYPE,
78494  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_67_WIDTH },
78495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_68_CHECKER_TYPE,
78496  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_68_WIDTH },
78497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_69_CHECKER_TYPE,
78498  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_69_WIDTH },
78499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_70_CHECKER_TYPE,
78500  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_70_WIDTH },
78501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_71_CHECKER_TYPE,
78502  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_71_WIDTH },
78503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_72_CHECKER_TYPE,
78504  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_72_WIDTH },
78505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_73_CHECKER_TYPE,
78506  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_73_WIDTH },
78507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_74_CHECKER_TYPE,
78508  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_74_WIDTH },
78509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_75_CHECKER_TYPE,
78510  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_75_WIDTH },
78511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_76_CHECKER_TYPE,
78512  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_76_WIDTH },
78513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_77_CHECKER_TYPE,
78514  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_77_WIDTH },
78515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_78_CHECKER_TYPE,
78516  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_78_WIDTH },
78517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_79_CHECKER_TYPE,
78518  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_79_WIDTH },
78519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_80_CHECKER_TYPE,
78520  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_80_WIDTH },
78521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_81_CHECKER_TYPE,
78522  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_81_WIDTH },
78523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_82_CHECKER_TYPE,
78524  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_82_WIDTH },
78525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_83_CHECKER_TYPE,
78526  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_83_WIDTH },
78527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_84_CHECKER_TYPE,
78528  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_84_WIDTH },
78529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_85_CHECKER_TYPE,
78530  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_85_WIDTH },
78531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_86_CHECKER_TYPE,
78532  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_86_WIDTH },
78533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_87_CHECKER_TYPE,
78534  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_87_WIDTH },
78535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_88_CHECKER_TYPE,
78536  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_88_WIDTH },
78537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_89_CHECKER_TYPE,
78538  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_89_WIDTH },
78539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_90_CHECKER_TYPE,
78540  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_90_WIDTH },
78541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_91_CHECKER_TYPE,
78542  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_91_WIDTH },
78543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_92_CHECKER_TYPE,
78544  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_92_WIDTH },
78545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_93_CHECKER_TYPE,
78546  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_93_WIDTH },
78547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_94_CHECKER_TYPE,
78548  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_94_WIDTH },
78549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_95_CHECKER_TYPE,
78550  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_95_WIDTH },
78551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_96_CHECKER_TYPE,
78552  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_96_WIDTH },
78553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_97_CHECKER_TYPE,
78554  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_97_WIDTH },
78555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_98_CHECKER_TYPE,
78556  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_98_WIDTH },
78557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_99_CHECKER_TYPE,
78558  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_99_WIDTH },
78559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_100_CHECKER_TYPE,
78560  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_100_WIDTH },
78561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_101_CHECKER_TYPE,
78562  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_101_WIDTH },
78563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_102_CHECKER_TYPE,
78564  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_102_WIDTH },
78565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_103_CHECKER_TYPE,
78566  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_103_WIDTH },
78567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_104_CHECKER_TYPE,
78568  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_104_WIDTH },
78569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_105_CHECKER_TYPE,
78570  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_105_WIDTH },
78571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_106_CHECKER_TYPE,
78572  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_106_WIDTH },
78573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_107_CHECKER_TYPE,
78574  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_107_WIDTH },
78575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_108_CHECKER_TYPE,
78576  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_108_WIDTH },
78577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_109_CHECKER_TYPE,
78578  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_109_WIDTH },
78579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_110_CHECKER_TYPE,
78580  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_110_WIDTH },
78581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_111_CHECKER_TYPE,
78582  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_111_WIDTH },
78583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_112_CHECKER_TYPE,
78584  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_112_WIDTH },
78585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_113_CHECKER_TYPE,
78586  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_113_WIDTH },
78587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_114_CHECKER_TYPE,
78588  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_114_WIDTH },
78589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_115_CHECKER_TYPE,
78590  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_115_WIDTH },
78591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_116_CHECKER_TYPE,
78592  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_116_WIDTH },
78593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_117_CHECKER_TYPE,
78594  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_117_WIDTH },
78595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_118_CHECKER_TYPE,
78596  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_118_WIDTH },
78597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_119_CHECKER_TYPE,
78598  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_119_WIDTH },
78599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_120_CHECKER_TYPE,
78600  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_120_WIDTH },
78601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_121_CHECKER_TYPE,
78602  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_121_WIDTH },
78603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_122_CHECKER_TYPE,
78604  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_122_WIDTH },
78605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_123_CHECKER_TYPE,
78606  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_123_WIDTH },
78607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_124_CHECKER_TYPE,
78608  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_124_WIDTH },
78609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_125_CHECKER_TYPE,
78610  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_125_WIDTH },
78611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_126_CHECKER_TYPE,
78612  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_126_WIDTH },
78613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_127_CHECKER_TYPE,
78614  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_127_WIDTH },
78615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_128_CHECKER_TYPE,
78616  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_128_WIDTH },
78617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_129_CHECKER_TYPE,
78618  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_129_WIDTH },
78619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_130_CHECKER_TYPE,
78620  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_130_WIDTH },
78621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_131_CHECKER_TYPE,
78622  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_131_WIDTH },
78623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_132_CHECKER_TYPE,
78624  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_132_WIDTH },
78625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_133_CHECKER_TYPE,
78626  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_133_WIDTH },
78627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_134_CHECKER_TYPE,
78628  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_134_WIDTH },
78629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_135_CHECKER_TYPE,
78630  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_135_WIDTH },
78631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_136_CHECKER_TYPE,
78632  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_136_WIDTH },
78633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_137_CHECKER_TYPE,
78634  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_137_WIDTH },
78635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_138_CHECKER_TYPE,
78636  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_138_WIDTH },
78637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_139_CHECKER_TYPE,
78638  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_139_WIDTH },
78639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_140_CHECKER_TYPE,
78640  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_140_WIDTH },
78641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_141_CHECKER_TYPE,
78642  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_141_WIDTH },
78643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_142_CHECKER_TYPE,
78644  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_142_WIDTH },
78645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_143_CHECKER_TYPE,
78646  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_143_WIDTH },
78647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_144_CHECKER_TYPE,
78648  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_144_WIDTH },
78649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_145_CHECKER_TYPE,
78650  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_145_WIDTH },
78651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_146_CHECKER_TYPE,
78652  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_146_WIDTH },
78653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_147_CHECKER_TYPE,
78654  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_147_WIDTH },
78655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_148_CHECKER_TYPE,
78656  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_148_WIDTH },
78657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_149_CHECKER_TYPE,
78658  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_149_WIDTH },
78659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_150_CHECKER_TYPE,
78660  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_150_WIDTH },
78661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_151_CHECKER_TYPE,
78662  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_151_WIDTH },
78663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_152_CHECKER_TYPE,
78664  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_152_WIDTH },
78665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_153_CHECKER_TYPE,
78666  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_153_WIDTH },
78667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_154_CHECKER_TYPE,
78668  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_154_WIDTH },
78669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_155_CHECKER_TYPE,
78670  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_155_WIDTH },
78671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_156_CHECKER_TYPE,
78672  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_156_WIDTH },
78673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_157_CHECKER_TYPE,
78674  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_157_WIDTH },
78675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_158_CHECKER_TYPE,
78676  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_158_WIDTH },
78677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_159_CHECKER_TYPE,
78678  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_159_WIDTH },
78679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_160_CHECKER_TYPE,
78680  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_160_WIDTH },
78681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_161_CHECKER_TYPE,
78682  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_161_WIDTH },
78683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_162_CHECKER_TYPE,
78684  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_162_WIDTH },
78685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_163_CHECKER_TYPE,
78686  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_163_WIDTH },
78687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_164_CHECKER_TYPE,
78688  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_164_WIDTH },
78689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_165_CHECKER_TYPE,
78690  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_165_WIDTH },
78691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_166_CHECKER_TYPE,
78692  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_166_WIDTH },
78693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_167_CHECKER_TYPE,
78694  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_167_WIDTH },
78695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_168_CHECKER_TYPE,
78696  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_168_WIDTH },
78697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_169_CHECKER_TYPE,
78698  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_169_WIDTH },
78699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_170_CHECKER_TYPE,
78700  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_170_WIDTH },
78701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_171_CHECKER_TYPE,
78702  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_171_WIDTH },
78703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_172_CHECKER_TYPE,
78704  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_172_WIDTH },
78705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_173_CHECKER_TYPE,
78706  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_173_WIDTH },
78707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_174_CHECKER_TYPE,
78708  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_174_WIDTH },
78709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_175_CHECKER_TYPE,
78710  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_175_WIDTH },
78711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_176_CHECKER_TYPE,
78712  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_176_WIDTH },
78713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_177_CHECKER_TYPE,
78714  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_177_WIDTH },
78715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_178_CHECKER_TYPE,
78716  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_178_WIDTH },
78717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_179_CHECKER_TYPE,
78718  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_179_WIDTH },
78719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_180_CHECKER_TYPE,
78720  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_180_WIDTH },
78721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_181_CHECKER_TYPE,
78722  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_181_WIDTH },
78723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_182_CHECKER_TYPE,
78724  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_182_WIDTH },
78725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_183_CHECKER_TYPE,
78726  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_183_WIDTH },
78727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_184_CHECKER_TYPE,
78728  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_184_WIDTH },
78729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_185_CHECKER_TYPE,
78730  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_185_WIDTH },
78731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_186_CHECKER_TYPE,
78732  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_186_WIDTH },
78733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_187_CHECKER_TYPE,
78734  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_187_WIDTH },
78735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_188_CHECKER_TYPE,
78736  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_188_WIDTH },
78737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_189_CHECKER_TYPE,
78738  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_189_WIDTH },
78739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_190_CHECKER_TYPE,
78740  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_190_WIDTH },
78741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_191_CHECKER_TYPE,
78742  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_191_WIDTH },
78743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_192_CHECKER_TYPE,
78744  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_192_WIDTH },
78745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_193_CHECKER_TYPE,
78746  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_193_WIDTH },
78747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_194_CHECKER_TYPE,
78748  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_194_WIDTH },
78749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_195_CHECKER_TYPE,
78750  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_195_WIDTH },
78751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_196_CHECKER_TYPE,
78752  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_196_WIDTH },
78753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_197_CHECKER_TYPE,
78754  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_197_WIDTH },
78755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_198_CHECKER_TYPE,
78756  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_198_WIDTH },
78757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_199_CHECKER_TYPE,
78758  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_199_WIDTH },
78759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_200_CHECKER_TYPE,
78760  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_200_WIDTH },
78761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_201_CHECKER_TYPE,
78762  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_201_WIDTH },
78763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_202_CHECKER_TYPE,
78764  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_202_WIDTH },
78765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_203_CHECKER_TYPE,
78766  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_203_WIDTH },
78767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_204_CHECKER_TYPE,
78768  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_204_WIDTH },
78769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_205_CHECKER_TYPE,
78770  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_205_WIDTH },
78771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_206_CHECKER_TYPE,
78772  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_206_WIDTH },
78773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_207_CHECKER_TYPE,
78774  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_207_WIDTH },
78775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_208_CHECKER_TYPE,
78776  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_208_WIDTH },
78777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_209_CHECKER_TYPE,
78778  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_209_WIDTH },
78779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_210_CHECKER_TYPE,
78780  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_210_WIDTH },
78781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_211_CHECKER_TYPE,
78782  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_211_WIDTH },
78783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_212_CHECKER_TYPE,
78784  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_212_WIDTH },
78785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_213_CHECKER_TYPE,
78786  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_213_WIDTH },
78787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_214_CHECKER_TYPE,
78788  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_214_WIDTH },
78789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_215_CHECKER_TYPE,
78790  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_215_WIDTH },
78791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_216_CHECKER_TYPE,
78792  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_216_WIDTH },
78793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_217_CHECKER_TYPE,
78794  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_217_WIDTH },
78795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_218_CHECKER_TYPE,
78796  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_218_WIDTH },
78797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_219_CHECKER_TYPE,
78798  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_219_WIDTH },
78799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_220_CHECKER_TYPE,
78800  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_220_WIDTH },
78801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_221_CHECKER_TYPE,
78802  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_221_WIDTH },
78803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_222_CHECKER_TYPE,
78804  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_222_WIDTH },
78805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_223_CHECKER_TYPE,
78806  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_223_WIDTH },
78807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_224_CHECKER_TYPE,
78808  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_224_WIDTH },
78809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_225_CHECKER_TYPE,
78810  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_225_WIDTH },
78811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_226_CHECKER_TYPE,
78812  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_226_WIDTH },
78813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_227_CHECKER_TYPE,
78814  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_227_WIDTH },
78815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_228_CHECKER_TYPE,
78816  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_228_WIDTH },
78817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_229_CHECKER_TYPE,
78818  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_229_WIDTH },
78819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_230_CHECKER_TYPE,
78820  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_230_WIDTH },
78821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_231_CHECKER_TYPE,
78822  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_231_WIDTH },
78823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_232_CHECKER_TYPE,
78824  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_232_WIDTH },
78825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_233_CHECKER_TYPE,
78826  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_233_WIDTH },
78827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_234_CHECKER_TYPE,
78828  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_234_WIDTH },
78829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_235_CHECKER_TYPE,
78830  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_235_WIDTH },
78831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_236_CHECKER_TYPE,
78832  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_236_WIDTH },
78833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_237_CHECKER_TYPE,
78834  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_237_WIDTH },
78835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_238_CHECKER_TYPE,
78836  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_238_WIDTH },
78837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_239_CHECKER_TYPE,
78838  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_239_WIDTH },
78839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_240_CHECKER_TYPE,
78840  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_240_WIDTH },
78841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_241_CHECKER_TYPE,
78842  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_241_WIDTH },
78843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_242_CHECKER_TYPE,
78844  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_242_WIDTH },
78845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_243_CHECKER_TYPE,
78846  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_243_WIDTH },
78847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_244_CHECKER_TYPE,
78848  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_244_WIDTH },
78849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_245_CHECKER_TYPE,
78850  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_245_WIDTH },
78851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_246_CHECKER_TYPE,
78852  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_246_WIDTH },
78853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_247_CHECKER_TYPE,
78854  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_247_WIDTH },
78855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_248_CHECKER_TYPE,
78856  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_248_WIDTH },
78857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_249_CHECKER_TYPE,
78858  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_249_WIDTH },
78859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_250_CHECKER_TYPE,
78860  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_250_WIDTH },
78861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_251_CHECKER_TYPE,
78862  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_251_WIDTH },
78863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_252_CHECKER_TYPE,
78864  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_252_WIDTH },
78865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_253_CHECKER_TYPE,
78866  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_253_WIDTH },
78867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_254_CHECKER_TYPE,
78868  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_254_WIDTH },
78869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_255_CHECKER_TYPE,
78870  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_GROUP_255_WIDTH },
78871 };
78872 
78878 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS] =
78879 {
78880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_0_CHECKER_TYPE,
78881  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_0_WIDTH },
78882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_1_CHECKER_TYPE,
78883  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_1_WIDTH },
78884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_2_CHECKER_TYPE,
78885  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_2_WIDTH },
78886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_3_CHECKER_TYPE,
78887  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_3_WIDTH },
78888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_4_CHECKER_TYPE,
78889  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_4_WIDTH },
78890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_5_CHECKER_TYPE,
78891  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_5_WIDTH },
78892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_6_CHECKER_TYPE,
78893  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_6_WIDTH },
78894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_7_CHECKER_TYPE,
78895  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_7_WIDTH },
78896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_8_CHECKER_TYPE,
78897  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_8_WIDTH },
78898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_9_CHECKER_TYPE,
78899  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_9_WIDTH },
78900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_10_CHECKER_TYPE,
78901  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_10_WIDTH },
78902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_11_CHECKER_TYPE,
78903  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_11_WIDTH },
78904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_12_CHECKER_TYPE,
78905  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_12_WIDTH },
78906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_13_CHECKER_TYPE,
78907  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_13_WIDTH },
78908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_14_CHECKER_TYPE,
78909  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_14_WIDTH },
78910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_15_CHECKER_TYPE,
78911  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_15_WIDTH },
78912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_16_CHECKER_TYPE,
78913  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_16_WIDTH },
78914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_17_CHECKER_TYPE,
78915  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_17_WIDTH },
78916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_18_CHECKER_TYPE,
78917  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_18_WIDTH },
78918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_19_CHECKER_TYPE,
78919  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_19_WIDTH },
78920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_20_CHECKER_TYPE,
78921  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_20_WIDTH },
78922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_21_CHECKER_TYPE,
78923  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_21_WIDTH },
78924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_22_CHECKER_TYPE,
78925  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_22_WIDTH },
78926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_23_CHECKER_TYPE,
78927  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_23_WIDTH },
78928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_24_CHECKER_TYPE,
78929  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_24_WIDTH },
78930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_25_CHECKER_TYPE,
78931  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_25_WIDTH },
78932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_26_CHECKER_TYPE,
78933  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_26_WIDTH },
78934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_27_CHECKER_TYPE,
78935  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_27_WIDTH },
78936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_28_CHECKER_TYPE,
78937  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_28_WIDTH },
78938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_29_CHECKER_TYPE,
78939  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_29_WIDTH },
78940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_30_CHECKER_TYPE,
78941  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_30_WIDTH },
78942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_31_CHECKER_TYPE,
78943  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_31_WIDTH },
78944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_32_CHECKER_TYPE,
78945  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_32_WIDTH },
78946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_33_CHECKER_TYPE,
78947  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_33_WIDTH },
78948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_34_CHECKER_TYPE,
78949  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_34_WIDTH },
78950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_35_CHECKER_TYPE,
78951  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_35_WIDTH },
78952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_36_CHECKER_TYPE,
78953  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_36_WIDTH },
78954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_37_CHECKER_TYPE,
78955  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_37_WIDTH },
78956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_38_CHECKER_TYPE,
78957  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_38_WIDTH },
78958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_39_CHECKER_TYPE,
78959  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_39_WIDTH },
78960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_40_CHECKER_TYPE,
78961  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_40_WIDTH },
78962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_41_CHECKER_TYPE,
78963  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_41_WIDTH },
78964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_42_CHECKER_TYPE,
78965  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_42_WIDTH },
78966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_43_CHECKER_TYPE,
78967  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_43_WIDTH },
78968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_44_CHECKER_TYPE,
78969  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_44_WIDTH },
78970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_45_CHECKER_TYPE,
78971  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_45_WIDTH },
78972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_46_CHECKER_TYPE,
78973  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_46_WIDTH },
78974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_47_CHECKER_TYPE,
78975  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_47_WIDTH },
78976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_48_CHECKER_TYPE,
78977  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_48_WIDTH },
78978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_49_CHECKER_TYPE,
78979  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_49_WIDTH },
78980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_50_CHECKER_TYPE,
78981  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_50_WIDTH },
78982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_51_CHECKER_TYPE,
78983  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_51_WIDTH },
78984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_52_CHECKER_TYPE,
78985  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_52_WIDTH },
78986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_53_CHECKER_TYPE,
78987  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_53_WIDTH },
78988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_54_CHECKER_TYPE,
78989  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_54_WIDTH },
78990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_55_CHECKER_TYPE,
78991  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_55_WIDTH },
78992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_56_CHECKER_TYPE,
78993  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_56_WIDTH },
78994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_57_CHECKER_TYPE,
78995  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_57_WIDTH },
78996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_58_CHECKER_TYPE,
78997  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_58_WIDTH },
78998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_59_CHECKER_TYPE,
78999  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_59_WIDTH },
79000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_60_CHECKER_TYPE,
79001  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_60_WIDTH },
79002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_61_CHECKER_TYPE,
79003  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_61_WIDTH },
79004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_62_CHECKER_TYPE,
79005  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_62_WIDTH },
79006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_63_CHECKER_TYPE,
79007  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_63_WIDTH },
79008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_64_CHECKER_TYPE,
79009  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_64_WIDTH },
79010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_65_CHECKER_TYPE,
79011  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_65_WIDTH },
79012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_66_CHECKER_TYPE,
79013  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_66_WIDTH },
79014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_67_CHECKER_TYPE,
79015  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_67_WIDTH },
79016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_68_CHECKER_TYPE,
79017  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_68_WIDTH },
79018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_69_CHECKER_TYPE,
79019  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_69_WIDTH },
79020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_70_CHECKER_TYPE,
79021  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_70_WIDTH },
79022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_71_CHECKER_TYPE,
79023  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_71_WIDTH },
79024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_72_CHECKER_TYPE,
79025  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_72_WIDTH },
79026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_73_CHECKER_TYPE,
79027  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_73_WIDTH },
79028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_74_CHECKER_TYPE,
79029  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_74_WIDTH },
79030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_75_CHECKER_TYPE,
79031  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_75_WIDTH },
79032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_76_CHECKER_TYPE,
79033  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_76_WIDTH },
79034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_77_CHECKER_TYPE,
79035  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_77_WIDTH },
79036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_78_CHECKER_TYPE,
79037  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_78_WIDTH },
79038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_79_CHECKER_TYPE,
79039  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_79_WIDTH },
79040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_80_CHECKER_TYPE,
79041  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_80_WIDTH },
79042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_81_CHECKER_TYPE,
79043  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_81_WIDTH },
79044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_82_CHECKER_TYPE,
79045  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_82_WIDTH },
79046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_83_CHECKER_TYPE,
79047  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_83_WIDTH },
79048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_84_CHECKER_TYPE,
79049  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_84_WIDTH },
79050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_85_CHECKER_TYPE,
79051  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_85_WIDTH },
79052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_86_CHECKER_TYPE,
79053  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_86_WIDTH },
79054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_87_CHECKER_TYPE,
79055  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_87_WIDTH },
79056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_88_CHECKER_TYPE,
79057  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_88_WIDTH },
79058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_89_CHECKER_TYPE,
79059  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_89_WIDTH },
79060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_90_CHECKER_TYPE,
79061  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_90_WIDTH },
79062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_91_CHECKER_TYPE,
79063  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_91_WIDTH },
79064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_92_CHECKER_TYPE,
79065  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_92_WIDTH },
79066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_93_CHECKER_TYPE,
79067  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_93_WIDTH },
79068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_94_CHECKER_TYPE,
79069  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_94_WIDTH },
79070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_95_CHECKER_TYPE,
79071  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_95_WIDTH },
79072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_96_CHECKER_TYPE,
79073  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_96_WIDTH },
79074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_97_CHECKER_TYPE,
79075  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_97_WIDTH },
79076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_98_CHECKER_TYPE,
79077  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_98_WIDTH },
79078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_99_CHECKER_TYPE,
79079  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_99_WIDTH },
79080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_100_CHECKER_TYPE,
79081  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_100_WIDTH },
79082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_101_CHECKER_TYPE,
79083  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_101_WIDTH },
79084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_102_CHECKER_TYPE,
79085  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_102_WIDTH },
79086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_103_CHECKER_TYPE,
79087  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_103_WIDTH },
79088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_104_CHECKER_TYPE,
79089  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_104_WIDTH },
79090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_105_CHECKER_TYPE,
79091  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_105_WIDTH },
79092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_106_CHECKER_TYPE,
79093  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_106_WIDTH },
79094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_107_CHECKER_TYPE,
79095  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_107_WIDTH },
79096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_108_CHECKER_TYPE,
79097  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_108_WIDTH },
79098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_109_CHECKER_TYPE,
79099  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_109_WIDTH },
79100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_110_CHECKER_TYPE,
79101  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_110_WIDTH },
79102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_111_CHECKER_TYPE,
79103  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_111_WIDTH },
79104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_112_CHECKER_TYPE,
79105  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_112_WIDTH },
79106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_113_CHECKER_TYPE,
79107  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_113_WIDTH },
79108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_114_CHECKER_TYPE,
79109  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_114_WIDTH },
79110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_115_CHECKER_TYPE,
79111  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_115_WIDTH },
79112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_116_CHECKER_TYPE,
79113  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_116_WIDTH },
79114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_117_CHECKER_TYPE,
79115  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_117_WIDTH },
79116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_118_CHECKER_TYPE,
79117  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_118_WIDTH },
79118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_119_CHECKER_TYPE,
79119  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_119_WIDTH },
79120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_120_CHECKER_TYPE,
79121  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_120_WIDTH },
79122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_121_CHECKER_TYPE,
79123  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_121_WIDTH },
79124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_122_CHECKER_TYPE,
79125  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_122_WIDTH },
79126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_123_CHECKER_TYPE,
79127  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_123_WIDTH },
79128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_124_CHECKER_TYPE,
79129  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_124_WIDTH },
79130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_125_CHECKER_TYPE,
79131  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_125_WIDTH },
79132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_126_CHECKER_TYPE,
79133  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_126_WIDTH },
79134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_127_CHECKER_TYPE,
79135  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_127_WIDTH },
79136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_128_CHECKER_TYPE,
79137  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_128_WIDTH },
79138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_129_CHECKER_TYPE,
79139  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_129_WIDTH },
79140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_130_CHECKER_TYPE,
79141  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_130_WIDTH },
79142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_131_CHECKER_TYPE,
79143  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_131_WIDTH },
79144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_132_CHECKER_TYPE,
79145  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_132_WIDTH },
79146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_133_CHECKER_TYPE,
79147  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_133_WIDTH },
79148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_134_CHECKER_TYPE,
79149  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_134_WIDTH },
79150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_135_CHECKER_TYPE,
79151  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_135_WIDTH },
79152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_136_CHECKER_TYPE,
79153  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_136_WIDTH },
79154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_137_CHECKER_TYPE,
79155  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_137_WIDTH },
79156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_138_CHECKER_TYPE,
79157  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_138_WIDTH },
79158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_139_CHECKER_TYPE,
79159  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_139_WIDTH },
79160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_140_CHECKER_TYPE,
79161  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_140_WIDTH },
79162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_141_CHECKER_TYPE,
79163  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_141_WIDTH },
79164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_142_CHECKER_TYPE,
79165  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_142_WIDTH },
79166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_143_CHECKER_TYPE,
79167  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_143_WIDTH },
79168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_144_CHECKER_TYPE,
79169  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_144_WIDTH },
79170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_145_CHECKER_TYPE,
79171  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_145_WIDTH },
79172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_146_CHECKER_TYPE,
79173  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_146_WIDTH },
79174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_147_CHECKER_TYPE,
79175  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_147_WIDTH },
79176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_148_CHECKER_TYPE,
79177  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_148_WIDTH },
79178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_149_CHECKER_TYPE,
79179  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_149_WIDTH },
79180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_150_CHECKER_TYPE,
79181  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_150_WIDTH },
79182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_151_CHECKER_TYPE,
79183  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_151_WIDTH },
79184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_152_CHECKER_TYPE,
79185  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_152_WIDTH },
79186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_153_CHECKER_TYPE,
79187  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_153_WIDTH },
79188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_154_CHECKER_TYPE,
79189  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_154_WIDTH },
79190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_155_CHECKER_TYPE,
79191  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_155_WIDTH },
79192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_156_CHECKER_TYPE,
79193  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_156_WIDTH },
79194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_157_CHECKER_TYPE,
79195  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_157_WIDTH },
79196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_158_CHECKER_TYPE,
79197  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_158_WIDTH },
79198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_159_CHECKER_TYPE,
79199  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_159_WIDTH },
79200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_160_CHECKER_TYPE,
79201  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_160_WIDTH },
79202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_161_CHECKER_TYPE,
79203  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_161_WIDTH },
79204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_162_CHECKER_TYPE,
79205  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_162_WIDTH },
79206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_163_CHECKER_TYPE,
79207  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_163_WIDTH },
79208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_164_CHECKER_TYPE,
79209  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_164_WIDTH },
79210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_165_CHECKER_TYPE,
79211  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_165_WIDTH },
79212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_166_CHECKER_TYPE,
79213  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_166_WIDTH },
79214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_167_CHECKER_TYPE,
79215  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_167_WIDTH },
79216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_168_CHECKER_TYPE,
79217  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_168_WIDTH },
79218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_169_CHECKER_TYPE,
79219  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_169_WIDTH },
79220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_170_CHECKER_TYPE,
79221  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_170_WIDTH },
79222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_171_CHECKER_TYPE,
79223  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_171_WIDTH },
79224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_172_CHECKER_TYPE,
79225  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_172_WIDTH },
79226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_173_CHECKER_TYPE,
79227  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_173_WIDTH },
79228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_174_CHECKER_TYPE,
79229  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_174_WIDTH },
79230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_175_CHECKER_TYPE,
79231  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_175_WIDTH },
79232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_176_CHECKER_TYPE,
79233  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_176_WIDTH },
79234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_177_CHECKER_TYPE,
79235  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_177_WIDTH },
79236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_178_CHECKER_TYPE,
79237  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_178_WIDTH },
79238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_179_CHECKER_TYPE,
79239  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_179_WIDTH },
79240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_180_CHECKER_TYPE,
79241  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_180_WIDTH },
79242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_181_CHECKER_TYPE,
79243  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_181_WIDTH },
79244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_182_CHECKER_TYPE,
79245  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_182_WIDTH },
79246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_183_CHECKER_TYPE,
79247  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_183_WIDTH },
79248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_184_CHECKER_TYPE,
79249  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_184_WIDTH },
79250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_185_CHECKER_TYPE,
79251  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_185_WIDTH },
79252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_186_CHECKER_TYPE,
79253  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_186_WIDTH },
79254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_187_CHECKER_TYPE,
79255  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_187_WIDTH },
79256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_188_CHECKER_TYPE,
79257  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_188_WIDTH },
79258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_189_CHECKER_TYPE,
79259  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_189_WIDTH },
79260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_190_CHECKER_TYPE,
79261  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_190_WIDTH },
79262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_191_CHECKER_TYPE,
79263  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_191_WIDTH },
79264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_192_CHECKER_TYPE,
79265  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_192_WIDTH },
79266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_193_CHECKER_TYPE,
79267  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_193_WIDTH },
79268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_194_CHECKER_TYPE,
79269  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_194_WIDTH },
79270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_195_CHECKER_TYPE,
79271  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_195_WIDTH },
79272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_196_CHECKER_TYPE,
79273  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_196_WIDTH },
79274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_197_CHECKER_TYPE,
79275  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_197_WIDTH },
79276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_198_CHECKER_TYPE,
79277  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_198_WIDTH },
79278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_199_CHECKER_TYPE,
79279  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_199_WIDTH },
79280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_200_CHECKER_TYPE,
79281  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_200_WIDTH },
79282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_201_CHECKER_TYPE,
79283  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_201_WIDTH },
79284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_202_CHECKER_TYPE,
79285  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_202_WIDTH },
79286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_203_CHECKER_TYPE,
79287  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_203_WIDTH },
79288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_204_CHECKER_TYPE,
79289  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_204_WIDTH },
79290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_205_CHECKER_TYPE,
79291  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_205_WIDTH },
79292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_206_CHECKER_TYPE,
79293  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_206_WIDTH },
79294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_207_CHECKER_TYPE,
79295  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_207_WIDTH },
79296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_208_CHECKER_TYPE,
79297  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_208_WIDTH },
79298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_209_CHECKER_TYPE,
79299  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_209_WIDTH },
79300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_210_CHECKER_TYPE,
79301  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_210_WIDTH },
79302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_211_CHECKER_TYPE,
79303  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_211_WIDTH },
79304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_212_CHECKER_TYPE,
79305  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_212_WIDTH },
79306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_213_CHECKER_TYPE,
79307  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_213_WIDTH },
79308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_214_CHECKER_TYPE,
79309  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_214_WIDTH },
79310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_215_CHECKER_TYPE,
79311  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_215_WIDTH },
79312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_216_CHECKER_TYPE,
79313  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_216_WIDTH },
79314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_217_CHECKER_TYPE,
79315  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_217_WIDTH },
79316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_218_CHECKER_TYPE,
79317  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_218_WIDTH },
79318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_219_CHECKER_TYPE,
79319  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_219_WIDTH },
79320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_220_CHECKER_TYPE,
79321  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_220_WIDTH },
79322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_221_CHECKER_TYPE,
79323  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_221_WIDTH },
79324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_222_CHECKER_TYPE,
79325  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_222_WIDTH },
79326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_223_CHECKER_TYPE,
79327  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_223_WIDTH },
79328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_224_CHECKER_TYPE,
79329  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_224_WIDTH },
79330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_225_CHECKER_TYPE,
79331  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_225_WIDTH },
79332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_226_CHECKER_TYPE,
79333  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_226_WIDTH },
79334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_227_CHECKER_TYPE,
79335  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_227_WIDTH },
79336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_228_CHECKER_TYPE,
79337  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_228_WIDTH },
79338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_229_CHECKER_TYPE,
79339  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_229_WIDTH },
79340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_230_CHECKER_TYPE,
79341  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_230_WIDTH },
79342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_231_CHECKER_TYPE,
79343  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_231_WIDTH },
79344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_232_CHECKER_TYPE,
79345  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_232_WIDTH },
79346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_233_CHECKER_TYPE,
79347  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_233_WIDTH },
79348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_234_CHECKER_TYPE,
79349  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_234_WIDTH },
79350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_235_CHECKER_TYPE,
79351  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_235_WIDTH },
79352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_236_CHECKER_TYPE,
79353  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_236_WIDTH },
79354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_237_CHECKER_TYPE,
79355  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_237_WIDTH },
79356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_238_CHECKER_TYPE,
79357  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_238_WIDTH },
79358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_239_CHECKER_TYPE,
79359  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_239_WIDTH },
79360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_240_CHECKER_TYPE,
79361  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_240_WIDTH },
79362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_241_CHECKER_TYPE,
79363  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_241_WIDTH },
79364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_242_CHECKER_TYPE,
79365  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_242_WIDTH },
79366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_243_CHECKER_TYPE,
79367  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_243_WIDTH },
79368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_244_CHECKER_TYPE,
79369  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_244_WIDTH },
79370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_245_CHECKER_TYPE,
79371  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_245_WIDTH },
79372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_246_CHECKER_TYPE,
79373  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_246_WIDTH },
79374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_247_CHECKER_TYPE,
79375  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_247_WIDTH },
79376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_248_CHECKER_TYPE,
79377  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_248_WIDTH },
79378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_249_CHECKER_TYPE,
79379  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_249_WIDTH },
79380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_250_CHECKER_TYPE,
79381  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_250_WIDTH },
79382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_251_CHECKER_TYPE,
79383  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_251_WIDTH },
79384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_252_CHECKER_TYPE,
79385  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_252_WIDTH },
79386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_253_CHECKER_TYPE,
79387  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_253_WIDTH },
79388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_254_CHECKER_TYPE,
79389  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_254_WIDTH },
79390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_255_CHECKER_TYPE,
79391  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_GROUP_255_WIDTH },
79392 };
79393 
79399 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
79400 {
79401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
79402  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
79403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
79404  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
79405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
79406  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
79407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
79408  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
79409 };
79410 
79416 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
79417 {
79418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
79419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
79420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
79421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
79422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
79423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
79424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
79425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
79426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
79427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
79428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
79429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
79430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
79431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
79432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
79433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
79434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
79435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
79436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
79437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
79438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
79439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
79440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
79441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
79442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
79443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
79444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
79445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
79446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
79447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
79448 };
79449 
79455 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
79456 {
79457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
79458  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
79459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
79460  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
79461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
79462  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
79463 };
79464 
79470 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
79471 {
79472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
79473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
79474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
79475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
79476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
79477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
79478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
79479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
79480 };
79481 
79487 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
79488 {
79489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
79490  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
79491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
79492  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
79493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
79494  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
79495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
79496  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
79497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
79498  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
79499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
79500  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
79501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
79502  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
79503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
79504  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
79505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
79506  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
79507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
79508  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
79509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
79510  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
79511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
79512  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
79513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
79514  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
79515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
79516  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
79517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
79518  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
79519 };
79520 
79526 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
79527 {
79528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
79529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
79530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
79531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
79532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
79533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
79534 };
79535 
79541 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
79542 {
79543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
79544  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
79545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
79546  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
79547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
79548  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
79549 };
79550 
79556 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
79557 {
79558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
79559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
79560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
79561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
79562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
79563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
79564 };
79565 
79571 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
79572 {
79573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
79574  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_0_WIDTH },
79575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
79576  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_1_WIDTH },
79577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
79578  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_GROUP_2_WIDTH },
79579 };
79580 
79586 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
79587 {
79588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
79589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
79590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
79591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
79592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
79593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
79594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
79595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
79596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
79597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
79598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
79599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
79600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
79601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
79602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
79603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
79604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
79605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
79606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
79607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
79608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
79609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
79610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
79611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
79612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
79613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
79614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
79615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
79616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
79617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
79618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
79619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
79620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
79621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
79622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
79623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
79624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
79625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
79626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
79627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
79628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
79629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
79630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
79631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
79632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
79633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
79634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
79635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
79636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
79637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
79638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
79639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
79640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
79641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
79642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
79643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
79644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
79645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
79646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
79647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
79648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
79649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
79650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
79651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
79652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
79653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
79654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
79655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
79656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
79657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
79658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
79659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
79660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
79661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
79662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
79663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
79664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
79665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
79666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
79667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
79668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
79669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
79670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
79671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
79672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
79673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
79674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
79675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
79676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
79677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
79678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
79679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
79680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
79681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
79682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
79683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
79684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
79685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
79686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
79687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
79688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
79689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
79690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
79691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
79692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
79693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
79694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
79695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
79696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
79697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
79698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
79699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
79700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
79701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
79702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
79703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
79704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
79705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
79706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
79707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
79708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
79709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
79710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
79711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
79712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
79713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
79714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
79715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
79716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
79717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
79718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
79719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
79720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
79721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
79722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
79723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
79724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
79725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
79726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
79727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
79728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
79729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
79730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
79731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
79732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
79733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
79734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
79735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
79736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
79737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
79738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
79739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
79740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
79741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
79742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
79743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
79744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
79745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
79746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
79747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
79748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
79749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
79750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
79751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
79752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
79753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
79754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
79755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
79756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
79757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
79758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
79759  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
79760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
79761  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
79762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
79763  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
79764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
79765  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
79766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
79767  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
79768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
79769  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
79770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
79771  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
79772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
79773  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
79774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
79775  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
79776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
79777  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
79778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
79779  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
79780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
79781  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
79782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
79783  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
79784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
79785  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
79786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
79787  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
79788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
79789  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
79790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
79791  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
79792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
79793  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
79794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
79795  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
79796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
79797  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
79798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
79799  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
79800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
79801  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
79802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
79803  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
79804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
79805  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
79806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
79807  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
79808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
79809  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
79810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
79811  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
79812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
79813  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
79814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
79815  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
79816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
79817  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
79818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
79819  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
79820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
79821  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
79822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
79823  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
79824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
79825  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
79826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
79827  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
79828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
79829  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
79830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
79831  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
79832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
79833  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
79834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
79835  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
79836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
79837  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
79838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
79839  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
79840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
79841  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
79842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
79843  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
79844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
79845  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
79846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
79847  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
79848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
79849  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
79850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
79851  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
79852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
79853  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
79854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
79855  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
79856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
79857  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
79858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
79859  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
79860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
79861  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
79862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
79863  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
79864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
79865  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
79866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
79867  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
79868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
79869  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
79870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
79871  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
79872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
79873  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
79874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
79875  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
79876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
79877  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
79878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
79879  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
79880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
79881  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
79882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
79883  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
79884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
79885  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
79886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
79887  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
79888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
79889  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
79890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
79891  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
79892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
79893  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
79894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
79895  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
79896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
79897  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
79898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
79899  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
79900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
79901  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
79902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
79903  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
79904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
79905  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
79906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
79907  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
79908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
79909  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
79910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
79911  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
79912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
79913  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
79914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
79915  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
79916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
79917  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
79918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
79919  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
79920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
79921  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
79922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
79923  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
79924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
79925  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
79926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
79927  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
79928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
79929  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
79930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
79931  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
79932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
79933  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
79934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
79935  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
79936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
79937  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
79938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
79939  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
79940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
79941  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
79942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
79943  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
79944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
79945  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
79946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
79947  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
79948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
79949  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
79950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
79951  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
79952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
79953  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
79954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
79955  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
79956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
79957  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
79958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
79959  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
79960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
79961  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
79962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
79963  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
79964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
79965  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
79966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
79967  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
79968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
79969  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
79970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
79971  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
79972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
79973  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
79974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
79975  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
79976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
79977  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
79978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
79979  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
79980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
79981  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
79982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
79983  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
79984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
79985  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
79986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
79987  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
79988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
79989  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
79990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
79991  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
79992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
79993  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
79994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
79995  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
79996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
79997  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
79998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
79999  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
80000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
80001  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
80002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
80003  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
80004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
80005  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
80006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
80007  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
80008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
80009  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
80010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
80011  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
80012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
80013  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
80014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
80015  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
80016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
80017  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
80018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
80019  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
80020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
80021  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
80022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
80023  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
80024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
80025  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
80026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
80027  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
80028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
80029  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
80030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
80031  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
80032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
80033  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
80034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
80035  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
80036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
80037  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
80038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
80039  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
80040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
80041  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
80042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
80043  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
80044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
80045  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
80046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
80047  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
80048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
80049  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
80050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
80051  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
80052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
80053  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
80054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
80055  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
80056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
80057  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
80058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
80059  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
80060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
80061  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
80062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
80063  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
80064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
80065  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
80066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
80067  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
80068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
80069  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
80070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
80071  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
80072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
80073  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
80074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
80075  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
80076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
80077  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
80078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
80079  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
80080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
80081  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
80082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
80083  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
80084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
80085  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
80086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
80087  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
80088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
80089  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
80090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
80091  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
80092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
80093  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
80094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
80095  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
80096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
80097  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
80098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
80099  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
80100 };
80101 
80107 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
80108 {
80109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
80110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
80111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
80112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
80113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
80114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
80115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
80116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
80117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
80118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
80119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
80120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
80121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
80122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
80123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
80124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
80125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
80126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
80127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
80128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
80129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
80130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
80131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
80132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
80133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
80134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
80135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
80136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
80137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
80138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
80139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
80140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
80141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
80142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
80143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
80144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
80145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
80146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
80147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
80148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
80149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
80150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
80151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
80152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
80153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
80154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
80155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
80156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
80157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
80158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
80159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
80160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
80161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
80162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
80163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
80164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
80165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
80166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
80167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
80168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
80169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
80170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
80171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
80172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
80173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
80174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
80175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
80176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
80177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
80178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
80179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
80180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
80181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
80182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
80183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
80184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
80185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
80186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
80187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
80188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
80189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
80190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
80191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
80192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
80193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
80194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
80195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
80196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
80197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
80198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
80199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
80200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
80201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
80202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
80203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
80204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
80205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
80206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
80207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
80208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
80209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
80210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
80211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
80212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
80213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
80214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
80215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
80216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
80217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
80218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
80219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
80220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
80221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
80222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
80223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
80224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
80225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
80226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
80227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
80228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
80229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
80230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
80231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
80232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
80233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
80234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
80235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
80236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
80237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
80238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
80239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
80240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
80241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
80242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
80243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
80244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
80245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
80246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
80247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
80248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
80249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
80250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
80251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
80252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
80253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
80254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
80255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
80256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
80257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
80258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
80259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
80260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
80261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
80262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
80263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
80264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
80265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
80266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
80267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
80268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
80269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
80270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
80271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
80272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
80273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
80274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
80275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
80276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
80277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
80278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
80279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
80280  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
80281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
80282  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
80283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
80284  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
80285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
80286  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
80287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
80288  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
80289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
80290  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
80291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
80292  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
80293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
80294  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
80295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
80296  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
80297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
80298  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
80299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
80300  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
80301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
80302  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
80303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
80304  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
80305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
80306  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
80307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
80308  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
80309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
80310  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
80311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
80312  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
80313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
80314  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
80315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
80316  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
80317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
80318  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
80319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
80320  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
80321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
80322  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
80323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
80324  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
80325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
80326  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
80327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
80328  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
80329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
80330  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
80331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
80332  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
80333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
80334  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
80335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
80336  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
80337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
80338  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
80339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
80340  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
80341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
80342  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
80343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
80344  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
80345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
80346  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
80347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
80348  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
80349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
80350  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
80351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
80352  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
80353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
80354  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
80355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
80356  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
80357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
80358  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
80359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
80360  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
80361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
80362  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
80363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
80364  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
80365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
80366  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
80367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
80368  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
80369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
80370  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
80371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
80372  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
80373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
80374  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
80375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
80376  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
80377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
80378  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
80379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
80380  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
80381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
80382  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
80383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
80384  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
80385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
80386  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
80387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
80388  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
80389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
80390  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
80391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
80392  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
80393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
80394  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
80395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
80396  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
80397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
80398  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
80399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
80400  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
80401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
80402  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
80403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
80404  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
80405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
80406  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
80407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
80408  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
80409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
80410  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
80411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
80412  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
80413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
80414  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
80415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
80416  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
80417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
80418  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
80419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
80420  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
80421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
80422  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
80423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
80424  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
80425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
80426  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
80427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
80428  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
80429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
80430  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
80431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
80432  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
80433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
80434  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
80435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
80436  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
80437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
80438  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
80439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
80440  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
80441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
80442  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
80443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
80444  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
80445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
80446  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
80447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
80448  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
80449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
80450  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
80451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
80452  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
80453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
80454  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
80455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
80456  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
80457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
80458  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
80459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
80460  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
80461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
80462  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
80463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
80464  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
80465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
80466  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
80467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
80468  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
80469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
80470  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
80471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
80472  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
80473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
80474  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
80475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
80476  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
80477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
80478  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
80479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
80480  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
80481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
80482  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
80483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
80484  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
80485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
80486  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
80487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
80488  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
80489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
80490  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
80491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
80492  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
80493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
80494  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
80495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
80496  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
80497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
80498  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
80499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
80500  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
80501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
80502  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
80503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
80504  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
80505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
80506  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
80507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
80508  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
80509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
80510  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
80511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
80512  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
80513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
80514  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
80515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
80516  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
80517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
80518  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
80519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
80520  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
80521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
80522  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
80523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
80524  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
80525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
80526  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
80527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
80528  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
80529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
80530  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
80531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
80532  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
80533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
80534  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
80535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
80536  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
80537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
80538  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
80539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
80540  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
80541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
80542  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
80543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
80544  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
80545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
80546  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
80547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
80548  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
80549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
80550  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
80551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
80552  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
80553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
80554  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
80555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
80556  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
80557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
80558  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
80559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
80560  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
80561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
80562  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
80563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
80564  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
80565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
80566  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
80567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
80568  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
80569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
80570  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
80571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
80572  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
80573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
80574  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
80575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
80576  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
80577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
80578  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
80579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
80580  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
80581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
80582  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
80583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
80584  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
80585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
80586  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
80587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
80588  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
80589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
80590  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
80591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
80592  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
80593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
80594  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
80595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
80596  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
80597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
80598  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
80599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
80600  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
80601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
80602  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
80603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
80604  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
80605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
80606  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
80607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
80608  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
80609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
80610  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
80611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
80612  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
80613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
80614  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
80615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
80616  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
80617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
80618  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
80619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
80620  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
80621 };
80622 
80628 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
80629 {
80630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
80631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
80632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
80633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
80634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
80635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
80636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
80637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
80638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
80639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
80640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
80641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
80642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
80643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
80644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
80645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
80646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
80647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
80648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
80649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
80650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
80651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
80652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
80653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
80654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
80655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
80656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
80657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
80658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
80659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
80660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
80661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
80662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
80663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
80664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
80665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
80666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
80667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
80668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
80669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
80670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
80671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
80672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
80673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
80674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
80675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
80676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
80677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
80678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
80679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
80680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
80681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
80682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
80683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
80684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
80685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
80686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
80687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
80688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
80689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
80690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
80691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
80692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
80693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
80694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
80695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
80696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
80697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
80698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
80699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
80700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
80701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
80702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
80703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
80704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
80705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
80706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
80707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
80708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
80709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
80710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
80711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
80712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
80713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
80714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
80715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
80716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
80717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
80718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
80719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
80720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
80721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
80722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
80723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
80724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
80725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
80726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
80727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
80728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
80729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
80730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
80731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
80732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
80733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
80734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
80735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
80736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
80737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
80738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
80739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
80740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
80741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
80742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
80743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
80744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
80745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
80746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
80747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
80748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
80749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
80750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
80751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
80752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
80753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
80754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
80755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
80756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
80757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
80758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
80759  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
80760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
80761  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
80762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
80763  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
80764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
80765  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
80766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
80767  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
80768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
80769  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
80770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
80771  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
80772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
80773  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
80774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
80775  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
80776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
80777  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
80778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
80779  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
80780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
80781  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
80782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
80783  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
80784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
80785  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
80786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
80787  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
80788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
80789  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
80790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
80791  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
80792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
80793  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
80794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
80795  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
80796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
80797  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
80798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
80799  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
80800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
80801  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
80802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
80803  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
80804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
80805  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
80806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
80807  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
80808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
80809  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
80810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
80811  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
80812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
80813  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
80814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
80815  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
80816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
80817  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
80818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
80819  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
80820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
80821  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
80822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
80823  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
80824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
80825  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
80826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
80827  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
80828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
80829  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
80830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
80831  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
80832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
80833  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
80834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
80835  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
80836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
80837  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
80838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
80839  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
80840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
80841  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
80842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
80843  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
80844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
80845  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
80846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
80847  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
80848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
80849  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
80850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
80851  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
80852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
80853  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
80854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
80855  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
80856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
80857  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
80858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
80859  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
80860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
80861  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
80862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
80863  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
80864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
80865  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
80866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
80867  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
80868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
80869  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
80870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
80871  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
80872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
80873  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
80874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
80875  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
80876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
80877  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
80878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
80879  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
80880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
80881  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
80882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
80883  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
80884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
80885  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
80886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
80887  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
80888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
80889  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
80890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
80891  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
80892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
80893  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
80894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
80895  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
80896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
80897  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
80898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
80899  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
80900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
80901  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
80902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
80903  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
80904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
80905  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
80906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
80907  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
80908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
80909  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
80910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
80911  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
80912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
80913  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
80914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
80915  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
80916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
80917  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
80918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
80919  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
80920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
80921  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
80922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
80923  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
80924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
80925  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
80926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
80927  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
80928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
80929  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
80930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
80931  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
80932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
80933  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
80934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
80935  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
80936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
80937  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
80938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
80939  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
80940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
80941  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
80942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
80943  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
80944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
80945  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
80946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
80947  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
80948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
80949  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
80950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
80951  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
80952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
80953  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
80954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
80955  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
80956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
80957  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
80958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
80959  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
80960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
80961  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
80962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
80963  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
80964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
80965  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
80966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
80967  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
80968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
80969  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
80970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
80971  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
80972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
80973  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
80974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
80975  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
80976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
80977  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
80978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
80979  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
80980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
80981  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
80982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
80983  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
80984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
80985  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
80986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
80987  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
80988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
80989  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
80990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
80991  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
80992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
80993  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
80994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
80995  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
80996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
80997  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
80998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
80999  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
81000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
81001  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
81002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
81003  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
81004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
81005  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
81006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
81007  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
81008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
81009  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
81010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
81011  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
81012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
81013  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
81014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
81015  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
81016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
81017  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
81018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
81019  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
81020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
81021  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
81022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
81023  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
81024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
81025  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
81026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
81027  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
81028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
81029  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
81030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
81031  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
81032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
81033  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
81034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
81035  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
81036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
81037  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
81038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
81039  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
81040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
81041  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
81042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
81043  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
81044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
81045  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
81046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
81047  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
81048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
81049  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
81050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
81051  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
81052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
81053  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
81054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
81055  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
81056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
81057  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
81058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
81059  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
81060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
81061  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
81062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
81063  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
81064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
81065  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
81066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
81067  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
81068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
81069  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
81070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
81071  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
81072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
81073  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
81074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
81075  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
81076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
81077  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
81078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
81079  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
81080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
81081  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
81082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
81083  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
81084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
81085  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
81086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
81087  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
81088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
81089  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
81090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
81091  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
81092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
81093  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
81094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
81095  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
81096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
81097  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
81098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
81099  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
81100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
81101  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
81102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
81103  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
81104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
81105  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
81106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
81107  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
81108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
81109  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
81110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
81111  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
81112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
81113  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
81114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
81115  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
81116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
81117  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
81118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
81119  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
81120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
81121  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
81122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
81123  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
81124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
81125  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
81126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
81127  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
81128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
81129  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
81130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
81131  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
81132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
81133  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
81134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
81135  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
81136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
81137  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
81138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
81139  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
81140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
81141  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
81142 };
81143 
81149 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
81150 {
81151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
81152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
81153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
81154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
81155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
81156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
81157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
81158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
81159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
81160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
81161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
81162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
81163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
81164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
81165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
81166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
81167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
81168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
81169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
81170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
81171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
81172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
81173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
81174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
81175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
81176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
81177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
81178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
81179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
81180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
81181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
81182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
81183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
81184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
81185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
81186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
81187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
81188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
81189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
81190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
81191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
81192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
81193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
81194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
81195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
81196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
81197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
81198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
81199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
81200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
81201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
81202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
81203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
81204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
81205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
81206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
81207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
81208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
81209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
81210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
81211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
81212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
81213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
81214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
81215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
81216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
81217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
81218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
81219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
81220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
81221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
81222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
81223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
81224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
81225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
81226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
81227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
81228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
81229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
81230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
81231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
81232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
81233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
81234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
81235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
81236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
81237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
81238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
81239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
81240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
81241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
81242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
81243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
81244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
81245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
81246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
81247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
81248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
81249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
81250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
81251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
81252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
81253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
81254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
81255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
81256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
81257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
81258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
81259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
81260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
81261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
81262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
81263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
81264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
81265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
81266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
81267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
81268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
81269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
81270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
81271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
81272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
81273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
81274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
81275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
81276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
81277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
81278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
81279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
81280  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
81281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
81282  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
81283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
81284  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
81285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
81286  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
81287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
81288  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
81289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
81290  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
81291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
81292  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
81293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
81294  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
81295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
81296  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
81297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
81298  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
81299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
81300  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
81301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
81302  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
81303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
81304  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
81305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
81306  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
81307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
81308  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
81309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
81310  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
81311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
81312  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
81313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
81314  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
81315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
81316  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
81317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
81318  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
81319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
81320  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
81321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
81322  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
81323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
81324  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
81325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
81326  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
81327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
81328  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
81329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
81330  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
81331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
81332  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
81333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
81334  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
81335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
81336  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
81337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
81338  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
81339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
81340  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
81341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
81342  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
81343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
81344  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
81345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
81346  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
81347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
81348  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
81349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
81350  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
81351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
81352  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
81353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
81354  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
81355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
81356  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
81357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
81358  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
81359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
81360  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
81361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
81362  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
81363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
81364  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
81365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
81366  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
81367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
81368  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
81369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
81370  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
81371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
81372  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
81373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
81374  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
81375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
81376  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
81377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
81378  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
81379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
81380  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
81381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
81382  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
81383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
81384  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
81385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
81386  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
81387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
81388  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
81389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
81390  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
81391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
81392  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
81393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
81394  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
81395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
81396  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
81397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
81398  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
81399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
81400  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
81401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
81402  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
81403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
81404  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
81405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
81406  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
81407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
81408  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
81409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
81410  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
81411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
81412  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
81413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
81414  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
81415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
81416  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
81417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
81418  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
81419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
81420  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
81421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
81422  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
81423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
81424  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
81425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
81426  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
81427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
81428  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
81429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
81430  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
81431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
81432  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
81433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
81434  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
81435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
81436  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
81437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
81438  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
81439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
81440  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
81441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
81442  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
81443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
81444  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
81445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
81446  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
81447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
81448  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
81449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
81450  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
81451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
81452  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
81453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
81454  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
81455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
81456  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
81457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
81458  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
81459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
81460  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
81461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
81462  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
81463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
81464  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
81465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
81466  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
81467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
81468  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
81469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
81470  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
81471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
81472  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
81473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
81474  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
81475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
81476  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
81477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
81478  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
81479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
81480  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
81481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
81482  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
81483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
81484  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
81485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
81486  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
81487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
81488  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
81489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
81490  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
81491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
81492  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
81493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
81494  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
81495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
81496  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
81497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
81498  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
81499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
81500  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
81501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
81502  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
81503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
81504  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
81505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
81506  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
81507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
81508  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
81509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
81510  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
81511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
81512  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
81513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
81514  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
81515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
81516  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
81517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
81518  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
81519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
81520  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
81521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
81522  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
81523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
81524  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
81525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
81526  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
81527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
81528  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
81529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
81530  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
81531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
81532  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
81533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
81534  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
81535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
81536  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
81537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
81538  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
81539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
81540  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
81541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
81542  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
81543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
81544  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
81545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
81546  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
81547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
81548  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
81549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
81550  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
81551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
81552  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
81553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
81554  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
81555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
81556  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
81557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
81558  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
81559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
81560  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
81561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
81562  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
81563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
81564  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
81565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
81566  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
81567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
81568  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
81569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
81570  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
81571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
81572  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
81573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
81574  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
81575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
81576  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
81577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
81578  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
81579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
81580  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
81581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
81582  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
81583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
81584  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
81585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
81586  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
81587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
81588  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
81589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
81590  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
81591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
81592  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
81593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
81594  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
81595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
81596  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
81597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
81598  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
81599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
81600  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
81601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
81602  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
81603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
81604  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
81605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
81606  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
81607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
81608  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
81609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
81610  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
81611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
81612  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
81613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
81614  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
81615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
81616  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
81617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
81618  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
81619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
81620  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
81621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
81622  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
81623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
81624  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
81625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
81626  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
81627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
81628  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
81629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
81630  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
81631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
81632  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
81633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
81634  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
81635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
81636  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
81637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
81638  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
81639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
81640  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
81641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
81642  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
81643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
81644  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
81645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
81646  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
81647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
81648  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
81649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
81650  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
81651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
81652  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
81653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
81654  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
81655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
81656  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
81657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
81658  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
81659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
81660  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
81661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
81662  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
81663 };
81664 
81670 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
81671 {
81672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
81673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
81674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
81675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
81676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
81677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
81678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
81679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
81680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
81681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
81682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
81683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
81684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
81685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
81686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
81687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
81688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
81689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
81690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
81691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
81692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
81693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
81694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
81695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
81696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
81697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
81698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
81699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
81700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
81701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
81702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
81703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
81704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
81705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
81706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
81707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
81708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
81709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
81710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
81711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
81712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
81713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
81714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
81715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
81716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
81717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
81718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
81719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
81720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
81721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
81722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
81723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
81724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
81725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
81726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
81727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
81728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
81729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
81730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
81731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
81732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
81733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
81734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
81735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
81736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
81737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
81738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
81739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
81740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
81741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
81742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
81743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
81744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
81745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
81746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
81747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
81748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
81749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
81750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
81751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
81752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
81753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
81754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
81755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
81756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
81757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
81758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
81759  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
81760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
81761  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
81762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
81763  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
81764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
81765  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
81766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
81767  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
81768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
81769  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
81770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
81771  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
81772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
81773  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
81774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
81775  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
81776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
81777  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
81778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
81779  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
81780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
81781  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
81782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
81783  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
81784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
81785  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
81786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
81787  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
81788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
81789  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
81790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
81791  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
81792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
81793  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
81794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
81795  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
81796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
81797  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
81798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
81799  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
81800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
81801  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
81802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
81803  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
81804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
81805  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
81806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
81807  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
81808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
81809  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
81810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
81811  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
81812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
81813  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
81814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
81815  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
81816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
81817  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
81818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
81819  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
81820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
81821  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
81822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
81823  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
81824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
81825  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
81826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
81827  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
81828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
81829  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
81830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
81831  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
81832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
81833  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
81834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
81835  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
81836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
81837  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
81838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
81839  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
81840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
81841  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
81842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
81843  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
81844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
81845  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
81846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
81847  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
81848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
81849  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
81850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
81851  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
81852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
81853  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
81854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
81855  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
81856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
81857  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
81858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
81859  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
81860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
81861  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
81862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
81863  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
81864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
81865  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
81866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
81867  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
81868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
81869  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
81870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
81871  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
81872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
81873  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
81874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
81875  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
81876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
81877  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
81878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
81879  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
81880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
81881  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
81882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
81883  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
81884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
81885  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
81886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
81887  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
81888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
81889  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
81890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
81891  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
81892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
81893  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
81894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
81895  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
81896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
81897  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
81898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
81899  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
81900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
81901  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
81902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
81903  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
81904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
81905  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
81906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
81907  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
81908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
81909  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
81910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
81911  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
81912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
81913  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
81914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
81915  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
81916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
81917  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
81918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
81919  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
81920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
81921  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
81922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
81923  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
81924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
81925  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
81926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
81927  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
81928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
81929  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
81930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
81931  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
81932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
81933  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
81934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
81935  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
81936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
81937  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
81938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
81939  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
81940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
81941  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
81942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
81943  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
81944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
81945  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
81946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
81947  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
81948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
81949  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
81950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
81951  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
81952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
81953  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
81954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
81955  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
81956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
81957  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
81958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
81959  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
81960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
81961  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
81962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
81963  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
81964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
81965  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
81966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
81967  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
81968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
81969  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
81970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
81971  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
81972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
81973  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
81974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
81975  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
81976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
81977  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
81978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
81979  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
81980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
81981  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
81982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
81983  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
81984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
81985  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
81986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
81987  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
81988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
81989  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
81990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
81991  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
81992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
81993  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
81994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
81995  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
81996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
81997  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
81998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
81999  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
82000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
82001  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
82002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
82003  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
82004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
82005  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
82006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
82007  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
82008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
82009  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
82010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
82011  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
82012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
82013  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
82014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
82015  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
82016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
82017  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
82018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
82019  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
82020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
82021  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
82022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
82023  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
82024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
82025  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
82026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
82027  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
82028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
82029  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
82030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
82031  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
82032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
82033  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
82034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
82035  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
82036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
82037  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
82038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
82039  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
82040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
82041  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
82042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
82043  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
82044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
82045  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
82046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
82047  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
82048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
82049  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
82050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
82051  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
82052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
82053  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
82054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
82055  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
82056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
82057  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
82058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
82059  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
82060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
82061  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
82062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
82063  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
82064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
82065  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
82066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
82067  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
82068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
82069  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
82070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
82071  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
82072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
82073  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
82074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
82075  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
82076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
82077  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
82078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
82079  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
82080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
82081  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
82082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
82083  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
82084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
82085  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
82086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
82087  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
82088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
82089  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
82090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
82091  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
82092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
82093  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
82094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
82095  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
82096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
82097  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
82098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
82099  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
82100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
82101  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
82102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
82103  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
82104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
82105  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
82106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
82107  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
82108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
82109  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
82110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
82111  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
82112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
82113  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
82114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
82115  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
82116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
82117  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
82118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
82119  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
82120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
82121  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
82122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
82123  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
82124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
82125  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
82126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
82127  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
82128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
82129  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
82130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
82131  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
82132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
82133  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
82134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
82135  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
82136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
82137  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
82138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
82139  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
82140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
82141  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
82142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
82143  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
82144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
82145  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
82146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
82147  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
82148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
82149  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
82150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
82151  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
82152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
82153  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
82154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
82155  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
82156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
82157  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
82158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
82159  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
82160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
82161  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
82162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
82163  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
82164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
82165  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
82166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
82167  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
82168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
82169  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
82170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
82171  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
82172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
82173  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
82174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
82175  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
82176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
82177  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
82178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
82179  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
82180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
82181  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
82182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
82183  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
82184 };
82185 
82191 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
82192 {
82193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
82194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
82195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
82196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
82197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
82198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
82199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
82200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
82201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
82202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
82203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
82204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
82205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
82206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
82207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
82208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
82209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
82210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
82211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
82212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
82213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
82214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
82215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
82216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
82217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
82218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
82219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
82220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
82221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
82222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
82223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
82224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
82225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
82226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
82227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
82228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
82229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
82230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
82231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
82232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
82233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
82234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
82235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
82236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
82237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
82238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
82239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
82240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
82241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
82242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
82243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
82244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
82245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
82246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
82247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
82248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
82249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
82250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
82251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
82252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
82253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
82254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
82255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
82256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
82257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
82258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
82259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
82260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
82261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
82262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
82263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
82264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
82265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
82266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
82267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
82268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
82269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
82270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
82271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
82272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
82273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
82274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
82275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
82276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
82277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
82278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
82279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
82280  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
82281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
82282  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
82283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
82284  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
82285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
82286  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
82287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
82288  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
82289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
82290  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
82291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
82292  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
82293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
82294  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
82295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
82296  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
82297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
82298  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
82299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
82300  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
82301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
82302  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
82303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
82304  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
82305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
82306  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
82307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
82308  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
82309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
82310  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
82311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
82312  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
82313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
82314  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
82315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
82316  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
82317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
82318  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
82319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
82320  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
82321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
82322  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
82323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
82324  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
82325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
82326  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
82327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
82328  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
82329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
82330  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
82331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
82332  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
82333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
82334  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
82335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
82336  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
82337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
82338  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
82339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
82340  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
82341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
82342  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
82343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
82344  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
82345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
82346  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
82347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
82348  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
82349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
82350  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
82351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
82352  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
82353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
82354  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
82355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
82356  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
82357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
82358  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
82359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
82360  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
82361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
82362  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
82363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
82364  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
82365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
82366  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
82367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
82368  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
82369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
82370  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
82371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
82372  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
82373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
82374  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
82375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
82376  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
82377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
82378  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
82379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
82380  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
82381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
82382  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
82383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
82384  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
82385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
82386  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
82387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
82388  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
82389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
82390  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
82391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
82392  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
82393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
82394  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
82395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
82396  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
82397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
82398  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
82399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
82400  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
82401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
82402  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
82403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
82404  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
82405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
82406  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
82407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
82408  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
82409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
82410  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
82411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
82412  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
82413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
82414  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
82415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
82416  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
82417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
82418  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
82419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
82420  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
82421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
82422  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
82423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
82424  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
82425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
82426  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
82427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
82428  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
82429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
82430  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
82431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
82432  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
82433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
82434  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
82435  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
82436  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
82437  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
82438  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
82439  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
82440  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
82441  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
82442  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
82443  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
82444  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
82445  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
82446  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
82447  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
82448  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
82449  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
82450  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
82451  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
82452  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
82453  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
82454  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
82455  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
82456  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
82457  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
82458  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
82459  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
82460  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
82461  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
82462  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
82463  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
82464  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
82465  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
82466  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
82467  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
82468  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
82469  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
82470  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
82471  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
82472  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
82473  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
82474  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
82475  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
82476  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
82477  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
82478  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
82479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
82480  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
82481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
82482  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
82483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
82484  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
82485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
82486  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
82487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
82488  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
82489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
82490  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
82491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
82492  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
82493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
82494  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
82495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
82496  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
82497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
82498  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
82499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
82500  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
82501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
82502  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
82503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
82504  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
82505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
82506  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
82507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
82508  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
82509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
82510  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
82511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
82512  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
82513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
82514  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
82515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
82516  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
82517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
82518  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
82519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
82520  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
82521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
82522  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
82523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
82524  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
82525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
82526  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
82527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
82528  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
82529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
82530  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
82531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
82532  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
82533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
82534  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
82535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
82536  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
82537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
82538  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
82539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
82540  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
82541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
82542  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
82543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
82544  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
82545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
82546  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
82547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
82548  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
82549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
82550  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
82551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
82552  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
82553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
82554  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
82555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
82556  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
82557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
82558  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
82559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
82560  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
82561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
82562  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
82563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
82564  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
82565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
82566  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
82567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
82568  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
82569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
82570  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
82571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
82572  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
82573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
82574  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
82575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
82576  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
82577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
82578  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
82579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
82580  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
82581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
82582  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
82583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
82584  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
82585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
82586  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
82587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
82588  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
82589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
82590  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
82591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
82592  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
82593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
82594  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
82595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
82596  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
82597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
82598  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
82599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
82600  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
82601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
82602  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
82603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
82604  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
82605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
82606  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
82607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
82608  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
82609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
82610  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
82611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
82612  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
82613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
82614  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
82615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
82616  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
82617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
82618  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
82619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
82620  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
82621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
82622  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
82623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
82624  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
82625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
82626  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
82627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
82628  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
82629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
82630  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
82631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
82632  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
82633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
82634  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
82635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
82636  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
82637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
82638  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
82639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
82640  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
82641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
82642  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
82643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
82644  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
82645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
82646  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
82647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
82648  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
82649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
82650  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
82651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
82652  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
82653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
82654  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
82655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
82656  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
82657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
82658  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
82659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
82660  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
82661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
82662  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
82663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
82664  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
82665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
82666  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
82667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
82668  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
82669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
82670  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
82671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
82672  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
82673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
82674  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
82675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
82676  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
82677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
82678  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
82679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
82680  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
82681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
82682  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
82683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
82684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
82685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
82686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
82687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
82688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
82689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
82690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
82691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
82692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
82693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
82694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
82695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
82696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
82697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
82698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
82699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
82700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
82701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
82702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
82703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
82704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
82705 };
82706 
82712 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
82713 {
82714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
82715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
82716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
82717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
82718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
82719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
82720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
82721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
82722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
82723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
82724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
82725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
82726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
82727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
82728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
82729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
82730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
82731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
82732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
82733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
82734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
82735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
82736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
82737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
82738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
82739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
82740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
82741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
82742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
82743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
82744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
82745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
82746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
82747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
82748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
82749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
82750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
82751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
82752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
82753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
82754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
82755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
82756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
82757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
82758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
82759  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
82760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
82761  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
82762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
82763  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
82764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
82765  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
82766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
82767  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
82768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
82769  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
82770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
82771  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
82772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
82773  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
82774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
82775  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
82776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
82777  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
82778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
82779  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
82780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
82781  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
82782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
82783  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
82784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
82785  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
82786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
82787  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
82788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
82789  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
82790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
82791  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
82792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
82793  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
82794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
82795  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
82796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
82797  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
82798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
82799  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
82800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
82801  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
82802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
82803  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
82804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
82805  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
82806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
82807  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
82808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
82809  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
82810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
82811  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
82812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
82813  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
82814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
82815  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
82816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
82817  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
82818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
82819  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
82820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
82821  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
82822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
82823  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
82824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
82825  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
82826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
82827  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
82828  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
82829  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
82830  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
82831  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
82832  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
82833  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
82834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
82835  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
82836  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
82837  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
82838  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
82839  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
82840  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
82841  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
82842  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
82843  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
82844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
82845  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
82846  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
82847  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
82848  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
82849  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
82850  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
82851  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
82852  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
82853  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
82854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
82855  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
82856  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
82857  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
82858  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
82859  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
82860  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
82861  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
82862  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
82863  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
82864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
82865  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
82866  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
82867  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
82868  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
82869  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
82870  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
82871  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
82872  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
82873  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
82874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
82875  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
82876  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
82877  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
82878  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
82879  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
82880  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
82881  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
82882  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
82883  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
82884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
82885  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
82886  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
82887  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
82888  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
82889  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
82890  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
82891  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
82892  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
82893  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
82894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
82895  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
82896  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
82897  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
82898  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
82899  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
82900  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
82901  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
82902  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
82903  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
82904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
82905  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
82906  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
82907  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
82908  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
82909  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
82910  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
82911  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
82912  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
82913  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
82914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
82915  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
82916  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
82917  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
82918  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
82919  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
82920  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
82921  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
82922  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
82923  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
82924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
82925  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
82926  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
82927  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
82928  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
82929  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
82930  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
82931  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
82932  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
82933  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
82934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
82935  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
82936  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
82937  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
82938  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
82939  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
82940  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
82941  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
82942  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
82943  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
82944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
82945  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
82946  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
82947  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
82948  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
82949  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
82950  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
82951  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
82952  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
82953  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
82954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
82955  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
82956  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
82957  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
82958  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
82959  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
82960  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
82961  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
82962  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
82963  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
82964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
82965  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
82966  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
82967  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
82968  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
82969  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
82970  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
82971  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
82972  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
82973  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
82974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
82975  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
82976  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
82977  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
82978  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
82979  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
82980  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
82981  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
82982  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
82983  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
82984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
82985  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
82986  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
82987  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
82988  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
82989  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
82990  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
82991  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
82992  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
82993  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
82994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
82995  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
82996  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
82997  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
82998  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
82999  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
83000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
83001  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
83002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
83003  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
83004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
83005  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
83006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
83007  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
83008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
83009  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
83010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
83011  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
83012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
83013  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
83014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
83015  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
83016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
83017  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
83018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
83019  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
83020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
83021  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
83022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
83023  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
83024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
83025  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
83026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
83027  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
83028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
83029  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
83030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
83031  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
83032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
83033  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
83034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
83035  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
83036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
83037  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
83038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
83039  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
83040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
83041  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
83042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
83043  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
83044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
83045  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
83046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
83047  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
83048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
83049  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
83050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
83051  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
83052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
83053  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
83054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
83055  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
83056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
83057  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
83058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
83059  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
83060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
83061  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
83062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
83063  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
83064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
83065  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
83066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
83067  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
83068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
83069  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
83070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
83071  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
83072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
83073  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
83074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
83075  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
83076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
83077  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
83078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
83079  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
83080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
83081  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
83082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
83083  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
83084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
83085  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
83086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
83087  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
83088 };
83089 
83095 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
83096 {
83097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
83098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
83099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
83100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
83101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
83102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
83103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
83104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
83105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
83106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
83107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
83108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
83109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
83110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
83111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
83112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
83113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
83114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
83115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
83116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
83117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
83118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
83119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
83120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
83121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
83122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
83123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
83124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
83125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
83126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
83127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
83128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
83129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
83130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
83131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
83132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
83133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
83134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
83135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
83136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
83137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
83138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
83139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
83140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
83141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
83142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
83143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
83144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
83145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
83146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
83147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
83148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
83149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
83150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
83151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
83152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
83153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
83154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
83155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
83156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
83157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
83158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
83159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
83160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
83161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
83162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
83163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
83164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
83165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
83166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
83167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
83168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
83169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
83170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
83171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
83172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
83173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
83174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
83175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
83176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
83177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
83178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
83179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
83180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
83181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
83182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
83183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
83184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
83185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
83186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
83187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
83188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
83189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
83190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
83191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
83192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
83193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
83194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
83195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
83196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
83197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
83198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
83199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
83200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
83201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
83202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
83203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
83204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
83205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
83206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
83207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
83208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
83209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
83210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
83211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
83212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
83213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
83214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
83215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
83216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
83217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
83218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
83219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
83220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
83221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
83222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
83223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
83224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
83225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
83226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
83227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
83228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
83229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
83230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
83231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
83232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
83233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
83234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
83235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
83236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
83237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
83238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
83239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
83240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
83241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
83242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
83243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
83244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
83245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
83246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
83247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
83248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
83249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
83250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
83251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
83252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
83253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
83254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
83255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
83256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
83257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
83258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
83259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
83260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
83261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
83262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
83263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
83264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
83265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
83266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
83267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
83268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
83269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
83270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
83271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
83272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
83273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
83274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
83275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
83276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
83277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
83278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
83279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
83280  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
83281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
83282  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
83283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
83284  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
83285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
83286  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
83287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
83288  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
83289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
83290  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
83291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
83292  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
83293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
83294  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
83295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
83296  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
83297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
83298  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
83299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
83300  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
83301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
83302  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
83303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
83304  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
83305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
83306  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
83307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
83308  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
83309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
83310  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
83311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
83312  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
83313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
83314  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
83315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
83316  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
83317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
83318  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
83319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
83320  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
83321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
83322  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
83323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
83324  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
83325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
83326  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
83327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
83328  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
83329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
83330  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
83331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
83332  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
83333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
83334  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
83335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
83336  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
83337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
83338  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
83339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
83340  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
83341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
83342  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
83343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
83344  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
83345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
83346  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
83347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
83348  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
83349  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
83350  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
83351  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
83352  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
83353  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
83354  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
83355  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
83356  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
83357  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
83358  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
83359  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
83360  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
83361  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
83362  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
83363  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_133_CHECKER_TYPE,
83364  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
83365  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_134_CHECKER_TYPE,
83366  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
83367  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_135_CHECKER_TYPE,
83368  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
83369  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_136_CHECKER_TYPE,
83370  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
83371  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_137_CHECKER_TYPE,
83372  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
83373  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_138_CHECKER_TYPE,
83374  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
83375  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_139_CHECKER_TYPE,
83376  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
83377  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_140_CHECKER_TYPE,
83378  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
83379  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_141_CHECKER_TYPE,
83380  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
83381  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_142_CHECKER_TYPE,
83382  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
83383  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_143_CHECKER_TYPE,
83384  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
83385  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_144_CHECKER_TYPE,
83386  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
83387  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_145_CHECKER_TYPE,
83388  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
83389  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_146_CHECKER_TYPE,
83390  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
83391  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_147_CHECKER_TYPE,
83392  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
83393  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_148_CHECKER_TYPE,
83394  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
83395  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_149_CHECKER_TYPE,
83396  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
83397  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_150_CHECKER_TYPE,
83398  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
83399  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_151_CHECKER_TYPE,
83400  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
83401  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_152_CHECKER_TYPE,
83402  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
83403  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_153_CHECKER_TYPE,
83404  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
83405  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_154_CHECKER_TYPE,
83406  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
83407  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_155_CHECKER_TYPE,
83408  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
83409  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_156_CHECKER_TYPE,
83410  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
83411  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_157_CHECKER_TYPE,
83412  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
83413  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_158_CHECKER_TYPE,
83414  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
83415  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_159_CHECKER_TYPE,
83416  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
83417  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_160_CHECKER_TYPE,
83418  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
83419  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_161_CHECKER_TYPE,
83420  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
83421  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_162_CHECKER_TYPE,
83422  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
83423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_163_CHECKER_TYPE,
83424  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
83425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_164_CHECKER_TYPE,
83426  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
83427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_165_CHECKER_TYPE,
83428  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
83429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_166_CHECKER_TYPE,
83430  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_166_WIDTH },
83431  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_167_CHECKER_TYPE,
83432  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_167_WIDTH },
83433  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_168_CHECKER_TYPE,
83434  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_GROUP_168_WIDTH },
83435 };
83436 
83442 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
83443 {
83444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
83445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
83446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
83447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
83448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
83449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
83450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
83451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
83452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
83453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
83454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
83455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
83456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
83457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
83458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
83459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
83460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
83461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
83462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
83463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
83464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
83465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
83466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
83467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
83468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
83469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
83470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
83471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
83472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
83473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
83474 };
83475 
83481 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
83482 {
83483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
83484  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
83485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
83486  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
83487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
83488  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
83489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
83490  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
83491 };
83492 
83498 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
83499 {
83500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
83501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
83502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
83503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
83504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
83505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
83506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
83507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
83508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
83509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
83510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
83511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
83512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
83513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
83514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
83515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
83516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
83517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
83518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
83519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
83520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
83521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
83522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
83523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
83524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
83525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
83526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
83527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
83528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
83529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
83530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
83531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
83532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
83533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
83534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
83535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
83536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
83537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
83538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
83539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
83540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
83541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
83542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
83543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
83544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
83545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
83546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
83547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
83548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
83549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
83550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
83551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
83552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
83553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
83554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
83555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
83556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
83557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
83558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
83559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
83560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
83561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
83562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
83563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
83564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
83565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
83566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
83567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
83568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
83569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
83570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
83571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
83572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
83573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
83574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
83575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
83576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
83577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
83578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
83579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
83580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
83581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
83582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
83583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
83584 };
83585 
83591 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
83592 {
83593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
83594  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
83595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
83596  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
83597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
83598  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
83599 };
83600 
83606 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
83607 {
83608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
83609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
83610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
83611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
83612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
83613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
83614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
83615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
83616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
83617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
83618 };
83619 
83625 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
83626 {
83627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
83628  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
83629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
83630  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
83631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
83632  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
83633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
83634  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
83635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
83636  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
83637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
83638  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
83639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
83640  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
83641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
83642  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
83643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
83644  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
83645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
83646  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
83647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
83648  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
83649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
83650  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
83651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
83652  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
83653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
83654  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
83655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
83656  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
83657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
83658  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
83659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
83660  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
83661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
83662  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
83663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
83664  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
83665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
83666  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
83667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
83668  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
83669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
83670  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
83671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
83672  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
83673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
83674  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
83675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
83676  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
83677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
83678  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
83679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
83680  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
83681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
83682  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
83683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
83684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
83685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
83686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
83687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
83688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
83689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
83690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
83691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
83692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
83693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
83694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
83695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
83696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
83697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
83698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
83699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
83700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
83701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
83702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
83703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
83704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
83705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
83706  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
83707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
83708  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
83709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
83710  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
83711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
83712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
83713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
83714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
83715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
83716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
83717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
83718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
83719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
83720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
83721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
83722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
83723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
83724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
83725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
83726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
83727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
83728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
83729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
83730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
83731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
83732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
83733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
83734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
83735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
83736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
83737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
83738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
83739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
83740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
83741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
83742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
83743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
83744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
83745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
83746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
83747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
83748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
83749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
83750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
83751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
83752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
83753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
83754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
83755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
83756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
83757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
83758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
83759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
83760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
83761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
83762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
83763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
83764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
83765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
83766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
83767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
83768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
83769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
83770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
83771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
83772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
83773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
83774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
83775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
83776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
83777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
83778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
83779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
83780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
83781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
83782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
83783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
83784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
83785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
83786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
83787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
83788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
83789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
83790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
83791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
83792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
83793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
83794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
83795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
83796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
83797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
83798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
83799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
83800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
83801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
83802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
83803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
83804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
83805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
83806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
83807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
83808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
83809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
83810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
83811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
83812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
83813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
83814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
83815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
83816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
83817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
83818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
83819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
83820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
83821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
83822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
83823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
83824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
83825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
83826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
83827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
83828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
83829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
83830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
83831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
83832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
83833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
83834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
83835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
83836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
83837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
83838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
83839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
83840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
83841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
83842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
83843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
83844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
83845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
83846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
83847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
83848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
83849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
83850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
83851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
83852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
83853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
83854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
83855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
83856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
83857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
83858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
83859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
83860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
83861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
83862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
83863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
83864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
83865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
83866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
83867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
83868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
83869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
83870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
83871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
83872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
83873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
83874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
83875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
83876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
83877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
83878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
83879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
83880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
83881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
83882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
83883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
83884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
83885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
83886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
83887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
83888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
83889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
83890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
83891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
83892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
83893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
83894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
83895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
83896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
83897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
83898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
83899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
83900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
83901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
83902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
83903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
83904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
83905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
83906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
83907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
83908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
83909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
83910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
83911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
83912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
83913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
83914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
83915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
83916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
83917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
83918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
83919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
83920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
83921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
83922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
83923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
83924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
83925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
83926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
83927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
83928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
83929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
83930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
83931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
83932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
83933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
83934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
83935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
83936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
83937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
83938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
83939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
83940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
83941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
83942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
83943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
83944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
83945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
83946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
83947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
83948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
83949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
83950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
83951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
83952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
83953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
83954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
83955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
83956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
83957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
83958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
83959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
83960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
83961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
83962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
83963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
83964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
83965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
83966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
83967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
83968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
83969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
83970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
83971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
83972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
83973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
83974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
83975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
83976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
83977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
83978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
83979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
83980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
83981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
83982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
83983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
83984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
83985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
83986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
83987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
83988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
83989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
83990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
83991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
83992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
83993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
83994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
83995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
83996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
83997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
83998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
83999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
84000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
84001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
84002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
84003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
84004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
84005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
84006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
84007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
84008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
84009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
84010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
84011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
84012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
84013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
84014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
84015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
84016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
84017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
84018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
84019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
84020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
84021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
84022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
84023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
84024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
84025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
84026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
84027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
84028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
84029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
84030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
84031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
84032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
84033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
84034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
84035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
84036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
84037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
84038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
84039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
84040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
84041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
84042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
84043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
84044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
84045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
84046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
84047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
84048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
84049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
84050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
84051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
84052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
84053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
84054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
84055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
84056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
84057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
84058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
84059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
84060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
84061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
84062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
84063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
84064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
84065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
84066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
84067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
84068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
84069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
84070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
84071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
84072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
84073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
84074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
84075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
84076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
84077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
84078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
84079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
84080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
84081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
84082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
84083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
84084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
84085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
84086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
84087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
84088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
84089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
84090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
84091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
84092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
84093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
84094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
84095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
84096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
84097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
84098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
84099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
84100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
84101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
84102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
84103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
84104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
84105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
84106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
84107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
84108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
84109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
84110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
84111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
84112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
84113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
84114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
84115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
84116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
84117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
84118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
84119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
84120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
84121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
84122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
84123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
84124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
84125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
84126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
84127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
84128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
84129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
84130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
84131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
84132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
84133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
84134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
84135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
84136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
84137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
84138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
84139 };
84140 
84146 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS] =
84147 {
84148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_0_CHECKER_TYPE,
84149  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_0_WIDTH },
84150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_1_CHECKER_TYPE,
84151  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_1_WIDTH },
84152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_2_CHECKER_TYPE,
84153  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_2_WIDTH },
84154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_3_CHECKER_TYPE,
84155  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_3_WIDTH },
84156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_4_CHECKER_TYPE,
84157  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_4_WIDTH },
84158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_5_CHECKER_TYPE,
84159  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_5_WIDTH },
84160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_6_CHECKER_TYPE,
84161  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_6_WIDTH },
84162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_7_CHECKER_TYPE,
84163  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_7_WIDTH },
84164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_8_CHECKER_TYPE,
84165  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_8_WIDTH },
84166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_9_CHECKER_TYPE,
84167  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_9_WIDTH },
84168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_10_CHECKER_TYPE,
84169  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_10_WIDTH },
84170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_11_CHECKER_TYPE,
84171  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_11_WIDTH },
84172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_12_CHECKER_TYPE,
84173  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_12_WIDTH },
84174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_13_CHECKER_TYPE,
84175  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_13_WIDTH },
84176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_14_CHECKER_TYPE,
84177  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_14_WIDTH },
84178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_15_CHECKER_TYPE,
84179  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_15_WIDTH },
84180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_16_CHECKER_TYPE,
84181  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_16_WIDTH },
84182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_17_CHECKER_TYPE,
84183  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_17_WIDTH },
84184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_18_CHECKER_TYPE,
84185  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_18_WIDTH },
84186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_19_CHECKER_TYPE,
84187  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_19_WIDTH },
84188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_20_CHECKER_TYPE,
84189  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_20_WIDTH },
84190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_21_CHECKER_TYPE,
84191  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_21_WIDTH },
84192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_22_CHECKER_TYPE,
84193  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_22_WIDTH },
84194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_23_CHECKER_TYPE,
84195  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_23_WIDTH },
84196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_24_CHECKER_TYPE,
84197  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_24_WIDTH },
84198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_25_CHECKER_TYPE,
84199  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_25_WIDTH },
84200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_26_CHECKER_TYPE,
84201  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_26_WIDTH },
84202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_27_CHECKER_TYPE,
84203  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_27_WIDTH },
84204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_28_CHECKER_TYPE,
84205  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_28_WIDTH },
84206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_29_CHECKER_TYPE,
84207  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_29_WIDTH },
84208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_30_CHECKER_TYPE,
84209  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_30_WIDTH },
84210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_31_CHECKER_TYPE,
84211  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_31_WIDTH },
84212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_32_CHECKER_TYPE,
84213  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_32_WIDTH },
84214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_33_CHECKER_TYPE,
84215  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_33_WIDTH },
84216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_34_CHECKER_TYPE,
84217  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_34_WIDTH },
84218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_35_CHECKER_TYPE,
84219  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_35_WIDTH },
84220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_36_CHECKER_TYPE,
84221  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_36_WIDTH },
84222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_37_CHECKER_TYPE,
84223  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_37_WIDTH },
84224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_38_CHECKER_TYPE,
84225  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_38_WIDTH },
84226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_39_CHECKER_TYPE,
84227  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_39_WIDTH },
84228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_40_CHECKER_TYPE,
84229  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_40_WIDTH },
84230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_41_CHECKER_TYPE,
84231  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_41_WIDTH },
84232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_42_CHECKER_TYPE,
84233  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_42_WIDTH },
84234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_43_CHECKER_TYPE,
84235  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_43_WIDTH },
84236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_44_CHECKER_TYPE,
84237  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_44_WIDTH },
84238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_45_CHECKER_TYPE,
84239  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_45_WIDTH },
84240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_46_CHECKER_TYPE,
84241  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_46_WIDTH },
84242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_47_CHECKER_TYPE,
84243  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_47_WIDTH },
84244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_48_CHECKER_TYPE,
84245  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_48_WIDTH },
84246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_49_CHECKER_TYPE,
84247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_49_WIDTH },
84248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_50_CHECKER_TYPE,
84249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_50_WIDTH },
84250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_51_CHECKER_TYPE,
84251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_51_WIDTH },
84252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_52_CHECKER_TYPE,
84253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_52_WIDTH },
84254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_53_CHECKER_TYPE,
84255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_53_WIDTH },
84256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_54_CHECKER_TYPE,
84257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_54_WIDTH },
84258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_55_CHECKER_TYPE,
84259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_55_WIDTH },
84260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_56_CHECKER_TYPE,
84261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_56_WIDTH },
84262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_57_CHECKER_TYPE,
84263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_57_WIDTH },
84264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_58_CHECKER_TYPE,
84265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_58_WIDTH },
84266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_59_CHECKER_TYPE,
84267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_59_WIDTH },
84268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_60_CHECKER_TYPE,
84269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_60_WIDTH },
84270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_61_CHECKER_TYPE,
84271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_61_WIDTH },
84272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_62_CHECKER_TYPE,
84273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_62_WIDTH },
84274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_63_CHECKER_TYPE,
84275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_63_WIDTH },
84276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_64_CHECKER_TYPE,
84277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_64_WIDTH },
84278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_65_CHECKER_TYPE,
84279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_65_WIDTH },
84280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_66_CHECKER_TYPE,
84281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_66_WIDTH },
84282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_67_CHECKER_TYPE,
84283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_67_WIDTH },
84284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_68_CHECKER_TYPE,
84285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_68_WIDTH },
84286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_69_CHECKER_TYPE,
84287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_69_WIDTH },
84288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_70_CHECKER_TYPE,
84289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_70_WIDTH },
84290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_71_CHECKER_TYPE,
84291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_71_WIDTH },
84292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_72_CHECKER_TYPE,
84293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_72_WIDTH },
84294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_73_CHECKER_TYPE,
84295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_73_WIDTH },
84296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_74_CHECKER_TYPE,
84297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_74_WIDTH },
84298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_75_CHECKER_TYPE,
84299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_75_WIDTH },
84300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_76_CHECKER_TYPE,
84301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_76_WIDTH },
84302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_77_CHECKER_TYPE,
84303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_77_WIDTH },
84304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_78_CHECKER_TYPE,
84305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_78_WIDTH },
84306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_79_CHECKER_TYPE,
84307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_79_WIDTH },
84308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_80_CHECKER_TYPE,
84309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_80_WIDTH },
84310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_81_CHECKER_TYPE,
84311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_81_WIDTH },
84312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_82_CHECKER_TYPE,
84313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_82_WIDTH },
84314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_83_CHECKER_TYPE,
84315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_83_WIDTH },
84316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_84_CHECKER_TYPE,
84317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_84_WIDTH },
84318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_85_CHECKER_TYPE,
84319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_85_WIDTH },
84320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_86_CHECKER_TYPE,
84321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_86_WIDTH },
84322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_87_CHECKER_TYPE,
84323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_87_WIDTH },
84324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_88_CHECKER_TYPE,
84325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_88_WIDTH },
84326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_89_CHECKER_TYPE,
84327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_89_WIDTH },
84328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_90_CHECKER_TYPE,
84329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_90_WIDTH },
84330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_91_CHECKER_TYPE,
84331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_91_WIDTH },
84332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_92_CHECKER_TYPE,
84333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_92_WIDTH },
84334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_93_CHECKER_TYPE,
84335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_93_WIDTH },
84336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_94_CHECKER_TYPE,
84337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_94_WIDTH },
84338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_95_CHECKER_TYPE,
84339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_95_WIDTH },
84340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_96_CHECKER_TYPE,
84341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_96_WIDTH },
84342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_97_CHECKER_TYPE,
84343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_97_WIDTH },
84344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_98_CHECKER_TYPE,
84345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_98_WIDTH },
84346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_99_CHECKER_TYPE,
84347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_99_WIDTH },
84348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_100_CHECKER_TYPE,
84349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_100_WIDTH },
84350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_101_CHECKER_TYPE,
84351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_101_WIDTH },
84352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_102_CHECKER_TYPE,
84353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_102_WIDTH },
84354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_103_CHECKER_TYPE,
84355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_103_WIDTH },
84356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_104_CHECKER_TYPE,
84357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_104_WIDTH },
84358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_105_CHECKER_TYPE,
84359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_105_WIDTH },
84360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_106_CHECKER_TYPE,
84361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_106_WIDTH },
84362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_107_CHECKER_TYPE,
84363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_107_WIDTH },
84364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_108_CHECKER_TYPE,
84365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_108_WIDTH },
84366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_109_CHECKER_TYPE,
84367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_109_WIDTH },
84368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_110_CHECKER_TYPE,
84369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_110_WIDTH },
84370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_111_CHECKER_TYPE,
84371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_111_WIDTH },
84372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_112_CHECKER_TYPE,
84373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_112_WIDTH },
84374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_113_CHECKER_TYPE,
84375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_113_WIDTH },
84376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_114_CHECKER_TYPE,
84377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_114_WIDTH },
84378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_115_CHECKER_TYPE,
84379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_115_WIDTH },
84380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_116_CHECKER_TYPE,
84381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_116_WIDTH },
84382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_117_CHECKER_TYPE,
84383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_117_WIDTH },
84384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_118_CHECKER_TYPE,
84385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_118_WIDTH },
84386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_119_CHECKER_TYPE,
84387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_119_WIDTH },
84388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_120_CHECKER_TYPE,
84389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_120_WIDTH },
84390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_121_CHECKER_TYPE,
84391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_121_WIDTH },
84392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_122_CHECKER_TYPE,
84393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_122_WIDTH },
84394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_123_CHECKER_TYPE,
84395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_123_WIDTH },
84396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_124_CHECKER_TYPE,
84397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_124_WIDTH },
84398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_125_CHECKER_TYPE,
84399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_125_WIDTH },
84400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_126_CHECKER_TYPE,
84401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_126_WIDTH },
84402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_127_CHECKER_TYPE,
84403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_127_WIDTH },
84404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_128_CHECKER_TYPE,
84405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_128_WIDTH },
84406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_129_CHECKER_TYPE,
84407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_129_WIDTH },
84408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_130_CHECKER_TYPE,
84409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_130_WIDTH },
84410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_131_CHECKER_TYPE,
84411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_131_WIDTH },
84412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_132_CHECKER_TYPE,
84413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_132_WIDTH },
84414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_133_CHECKER_TYPE,
84415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_133_WIDTH },
84416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_134_CHECKER_TYPE,
84417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_134_WIDTH },
84418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_135_CHECKER_TYPE,
84419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_135_WIDTH },
84420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_136_CHECKER_TYPE,
84421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_136_WIDTH },
84422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_137_CHECKER_TYPE,
84423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_137_WIDTH },
84424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_138_CHECKER_TYPE,
84425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_138_WIDTH },
84426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_139_CHECKER_TYPE,
84427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_139_WIDTH },
84428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_140_CHECKER_TYPE,
84429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_140_WIDTH },
84430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_141_CHECKER_TYPE,
84431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_141_WIDTH },
84432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_142_CHECKER_TYPE,
84433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_142_WIDTH },
84434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_143_CHECKER_TYPE,
84435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_143_WIDTH },
84436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_144_CHECKER_TYPE,
84437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_144_WIDTH },
84438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_145_CHECKER_TYPE,
84439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_145_WIDTH },
84440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_146_CHECKER_TYPE,
84441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_146_WIDTH },
84442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_147_CHECKER_TYPE,
84443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_147_WIDTH },
84444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_148_CHECKER_TYPE,
84445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_148_WIDTH },
84446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_149_CHECKER_TYPE,
84447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_149_WIDTH },
84448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_150_CHECKER_TYPE,
84449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_150_WIDTH },
84450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_151_CHECKER_TYPE,
84451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_151_WIDTH },
84452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_152_CHECKER_TYPE,
84453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_152_WIDTH },
84454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_153_CHECKER_TYPE,
84455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_153_WIDTH },
84456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_154_CHECKER_TYPE,
84457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_154_WIDTH },
84458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_155_CHECKER_TYPE,
84459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_155_WIDTH },
84460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_156_CHECKER_TYPE,
84461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_156_WIDTH },
84462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_157_CHECKER_TYPE,
84463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_157_WIDTH },
84464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_158_CHECKER_TYPE,
84465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_158_WIDTH },
84466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_159_CHECKER_TYPE,
84467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_159_WIDTH },
84468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_160_CHECKER_TYPE,
84469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_160_WIDTH },
84470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_161_CHECKER_TYPE,
84471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_161_WIDTH },
84472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_162_CHECKER_TYPE,
84473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_162_WIDTH },
84474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_163_CHECKER_TYPE,
84475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_163_WIDTH },
84476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_164_CHECKER_TYPE,
84477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_164_WIDTH },
84478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_165_CHECKER_TYPE,
84479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_165_WIDTH },
84480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_166_CHECKER_TYPE,
84481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_166_WIDTH },
84482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_167_CHECKER_TYPE,
84483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_167_WIDTH },
84484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_168_CHECKER_TYPE,
84485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_168_WIDTH },
84486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_169_CHECKER_TYPE,
84487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_169_WIDTH },
84488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_170_CHECKER_TYPE,
84489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_170_WIDTH },
84490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_171_CHECKER_TYPE,
84491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_171_WIDTH },
84492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_172_CHECKER_TYPE,
84493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_172_WIDTH },
84494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_173_CHECKER_TYPE,
84495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_173_WIDTH },
84496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_174_CHECKER_TYPE,
84497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_174_WIDTH },
84498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_175_CHECKER_TYPE,
84499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_175_WIDTH },
84500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_176_CHECKER_TYPE,
84501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_176_WIDTH },
84502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_177_CHECKER_TYPE,
84503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_177_WIDTH },
84504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_178_CHECKER_TYPE,
84505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_178_WIDTH },
84506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_179_CHECKER_TYPE,
84507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_179_WIDTH },
84508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_180_CHECKER_TYPE,
84509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_180_WIDTH },
84510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_181_CHECKER_TYPE,
84511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_181_WIDTH },
84512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_182_CHECKER_TYPE,
84513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_182_WIDTH },
84514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_183_CHECKER_TYPE,
84515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_183_WIDTH },
84516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_184_CHECKER_TYPE,
84517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_184_WIDTH },
84518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_185_CHECKER_TYPE,
84519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_185_WIDTH },
84520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_186_CHECKER_TYPE,
84521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_186_WIDTH },
84522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_187_CHECKER_TYPE,
84523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_187_WIDTH },
84524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_188_CHECKER_TYPE,
84525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_188_WIDTH },
84526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_189_CHECKER_TYPE,
84527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_189_WIDTH },
84528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_190_CHECKER_TYPE,
84529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_190_WIDTH },
84530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_191_CHECKER_TYPE,
84531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_191_WIDTH },
84532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_192_CHECKER_TYPE,
84533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_192_WIDTH },
84534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_193_CHECKER_TYPE,
84535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_193_WIDTH },
84536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_194_CHECKER_TYPE,
84537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_194_WIDTH },
84538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_195_CHECKER_TYPE,
84539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_195_WIDTH },
84540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_196_CHECKER_TYPE,
84541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_196_WIDTH },
84542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_197_CHECKER_TYPE,
84543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_197_WIDTH },
84544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_198_CHECKER_TYPE,
84545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_198_WIDTH },
84546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_199_CHECKER_TYPE,
84547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_199_WIDTH },
84548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_200_CHECKER_TYPE,
84549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_200_WIDTH },
84550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_201_CHECKER_TYPE,
84551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_201_WIDTH },
84552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_202_CHECKER_TYPE,
84553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_202_WIDTH },
84554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_203_CHECKER_TYPE,
84555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_203_WIDTH },
84556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_204_CHECKER_TYPE,
84557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_204_WIDTH },
84558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_205_CHECKER_TYPE,
84559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_205_WIDTH },
84560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_206_CHECKER_TYPE,
84561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_206_WIDTH },
84562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_207_CHECKER_TYPE,
84563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_207_WIDTH },
84564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_208_CHECKER_TYPE,
84565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_208_WIDTH },
84566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_209_CHECKER_TYPE,
84567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_209_WIDTH },
84568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_210_CHECKER_TYPE,
84569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_210_WIDTH },
84570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_211_CHECKER_TYPE,
84571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_211_WIDTH },
84572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_212_CHECKER_TYPE,
84573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_212_WIDTH },
84574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_213_CHECKER_TYPE,
84575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_213_WIDTH },
84576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_214_CHECKER_TYPE,
84577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_214_WIDTH },
84578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_215_CHECKER_TYPE,
84579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_215_WIDTH },
84580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_216_CHECKER_TYPE,
84581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_216_WIDTH },
84582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_217_CHECKER_TYPE,
84583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_217_WIDTH },
84584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_218_CHECKER_TYPE,
84585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_218_WIDTH },
84586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_219_CHECKER_TYPE,
84587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_219_WIDTH },
84588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_220_CHECKER_TYPE,
84589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_220_WIDTH },
84590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_221_CHECKER_TYPE,
84591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_221_WIDTH },
84592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_222_CHECKER_TYPE,
84593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_222_WIDTH },
84594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_223_CHECKER_TYPE,
84595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_223_WIDTH },
84596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_224_CHECKER_TYPE,
84597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_224_WIDTH },
84598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_225_CHECKER_TYPE,
84599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_225_WIDTH },
84600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_226_CHECKER_TYPE,
84601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_226_WIDTH },
84602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_227_CHECKER_TYPE,
84603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_227_WIDTH },
84604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_228_CHECKER_TYPE,
84605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_228_WIDTH },
84606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_229_CHECKER_TYPE,
84607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_229_WIDTH },
84608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_230_CHECKER_TYPE,
84609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_230_WIDTH },
84610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_231_CHECKER_TYPE,
84611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_231_WIDTH },
84612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_232_CHECKER_TYPE,
84613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_232_WIDTH },
84614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_233_CHECKER_TYPE,
84615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_233_WIDTH },
84616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_234_CHECKER_TYPE,
84617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_234_WIDTH },
84618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_235_CHECKER_TYPE,
84619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_235_WIDTH },
84620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_236_CHECKER_TYPE,
84621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_236_WIDTH },
84622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_237_CHECKER_TYPE,
84623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_237_WIDTH },
84624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_238_CHECKER_TYPE,
84625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_238_WIDTH },
84626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_239_CHECKER_TYPE,
84627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_239_WIDTH },
84628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_240_CHECKER_TYPE,
84629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_240_WIDTH },
84630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_241_CHECKER_TYPE,
84631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_241_WIDTH },
84632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_242_CHECKER_TYPE,
84633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_242_WIDTH },
84634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_243_CHECKER_TYPE,
84635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_243_WIDTH },
84636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_244_CHECKER_TYPE,
84637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_244_WIDTH },
84638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_245_CHECKER_TYPE,
84639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_245_WIDTH },
84640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_246_CHECKER_TYPE,
84641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_246_WIDTH },
84642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_247_CHECKER_TYPE,
84643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_247_WIDTH },
84644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_248_CHECKER_TYPE,
84645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_248_WIDTH },
84646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_249_CHECKER_TYPE,
84647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_249_WIDTH },
84648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_250_CHECKER_TYPE,
84649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_250_WIDTH },
84650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_251_CHECKER_TYPE,
84651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_251_WIDTH },
84652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_252_CHECKER_TYPE,
84653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_252_WIDTH },
84654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_253_CHECKER_TYPE,
84655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_253_WIDTH },
84656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_254_CHECKER_TYPE,
84657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_254_WIDTH },
84658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_255_CHECKER_TYPE,
84659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_255_WIDTH },
84660 };
84661 
84667 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS] =
84668 {
84669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_0_CHECKER_TYPE,
84670  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_0_WIDTH },
84671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_1_CHECKER_TYPE,
84672  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_1_WIDTH },
84673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_2_CHECKER_TYPE,
84674  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_2_WIDTH },
84675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_3_CHECKER_TYPE,
84676  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_3_WIDTH },
84677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_4_CHECKER_TYPE,
84678  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_4_WIDTH },
84679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_5_CHECKER_TYPE,
84680  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_5_WIDTH },
84681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_6_CHECKER_TYPE,
84682  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_6_WIDTH },
84683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_7_CHECKER_TYPE,
84684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_7_WIDTH },
84685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_8_CHECKER_TYPE,
84686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_8_WIDTH },
84687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_9_CHECKER_TYPE,
84688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_9_WIDTH },
84689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_10_CHECKER_TYPE,
84690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_10_WIDTH },
84691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_11_CHECKER_TYPE,
84692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_11_WIDTH },
84693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_12_CHECKER_TYPE,
84694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_12_WIDTH },
84695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_13_CHECKER_TYPE,
84696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_13_WIDTH },
84697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_14_CHECKER_TYPE,
84698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_14_WIDTH },
84699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_15_CHECKER_TYPE,
84700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_15_WIDTH },
84701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_16_CHECKER_TYPE,
84702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_16_WIDTH },
84703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_17_CHECKER_TYPE,
84704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_17_WIDTH },
84705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_18_CHECKER_TYPE,
84706  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_18_WIDTH },
84707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_19_CHECKER_TYPE,
84708  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_19_WIDTH },
84709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_20_CHECKER_TYPE,
84710  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_20_WIDTH },
84711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_21_CHECKER_TYPE,
84712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_21_WIDTH },
84713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_22_CHECKER_TYPE,
84714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_22_WIDTH },
84715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_23_CHECKER_TYPE,
84716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_23_WIDTH },
84717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_24_CHECKER_TYPE,
84718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_24_WIDTH },
84719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_25_CHECKER_TYPE,
84720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_25_WIDTH },
84721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_26_CHECKER_TYPE,
84722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_26_WIDTH },
84723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_27_CHECKER_TYPE,
84724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_27_WIDTH },
84725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_28_CHECKER_TYPE,
84726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_28_WIDTH },
84727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_29_CHECKER_TYPE,
84728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_29_WIDTH },
84729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_30_CHECKER_TYPE,
84730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_30_WIDTH },
84731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_31_CHECKER_TYPE,
84732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_31_WIDTH },
84733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_32_CHECKER_TYPE,
84734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_32_WIDTH },
84735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_33_CHECKER_TYPE,
84736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_33_WIDTH },
84737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_34_CHECKER_TYPE,
84738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_34_WIDTH },
84739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_35_CHECKER_TYPE,
84740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_35_WIDTH },
84741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_36_CHECKER_TYPE,
84742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_36_WIDTH },
84743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_37_CHECKER_TYPE,
84744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_37_WIDTH },
84745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_38_CHECKER_TYPE,
84746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_38_WIDTH },
84747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_39_CHECKER_TYPE,
84748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_39_WIDTH },
84749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_40_CHECKER_TYPE,
84750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_40_WIDTH },
84751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_41_CHECKER_TYPE,
84752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_41_WIDTH },
84753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_42_CHECKER_TYPE,
84754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_42_WIDTH },
84755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_43_CHECKER_TYPE,
84756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_43_WIDTH },
84757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_44_CHECKER_TYPE,
84758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_44_WIDTH },
84759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_45_CHECKER_TYPE,
84760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_45_WIDTH },
84761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_46_CHECKER_TYPE,
84762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_46_WIDTH },
84763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_47_CHECKER_TYPE,
84764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_47_WIDTH },
84765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_48_CHECKER_TYPE,
84766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_48_WIDTH },
84767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_49_CHECKER_TYPE,
84768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_49_WIDTH },
84769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_50_CHECKER_TYPE,
84770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_50_WIDTH },
84771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_51_CHECKER_TYPE,
84772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_51_WIDTH },
84773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_52_CHECKER_TYPE,
84774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_52_WIDTH },
84775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_53_CHECKER_TYPE,
84776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_53_WIDTH },
84777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_54_CHECKER_TYPE,
84778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_54_WIDTH },
84779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_55_CHECKER_TYPE,
84780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_55_WIDTH },
84781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_56_CHECKER_TYPE,
84782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_56_WIDTH },
84783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_57_CHECKER_TYPE,
84784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_57_WIDTH },
84785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_58_CHECKER_TYPE,
84786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_58_WIDTH },
84787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_59_CHECKER_TYPE,
84788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_59_WIDTH },
84789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_60_CHECKER_TYPE,
84790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_60_WIDTH },
84791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_61_CHECKER_TYPE,
84792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_61_WIDTH },
84793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_62_CHECKER_TYPE,
84794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_62_WIDTH },
84795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_63_CHECKER_TYPE,
84796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_63_WIDTH },
84797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_64_CHECKER_TYPE,
84798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_64_WIDTH },
84799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_65_CHECKER_TYPE,
84800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_65_WIDTH },
84801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_66_CHECKER_TYPE,
84802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_66_WIDTH },
84803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_67_CHECKER_TYPE,
84804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_67_WIDTH },
84805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_68_CHECKER_TYPE,
84806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_68_WIDTH },
84807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_69_CHECKER_TYPE,
84808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_69_WIDTH },
84809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_70_CHECKER_TYPE,
84810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_70_WIDTH },
84811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_71_CHECKER_TYPE,
84812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_71_WIDTH },
84813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_72_CHECKER_TYPE,
84814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_72_WIDTH },
84815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_73_CHECKER_TYPE,
84816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_73_WIDTH },
84817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_74_CHECKER_TYPE,
84818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_74_WIDTH },
84819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_75_CHECKER_TYPE,
84820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_75_WIDTH },
84821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_76_CHECKER_TYPE,
84822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_76_WIDTH },
84823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_77_CHECKER_TYPE,
84824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_77_WIDTH },
84825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_78_CHECKER_TYPE,
84826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_78_WIDTH },
84827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_79_CHECKER_TYPE,
84828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_79_WIDTH },
84829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_80_CHECKER_TYPE,
84830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_80_WIDTH },
84831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_81_CHECKER_TYPE,
84832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_81_WIDTH },
84833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_82_CHECKER_TYPE,
84834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_82_WIDTH },
84835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_83_CHECKER_TYPE,
84836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_83_WIDTH },
84837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_84_CHECKER_TYPE,
84838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_84_WIDTH },
84839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_85_CHECKER_TYPE,
84840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_85_WIDTH },
84841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_86_CHECKER_TYPE,
84842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_86_WIDTH },
84843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_87_CHECKER_TYPE,
84844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_87_WIDTH },
84845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_88_CHECKER_TYPE,
84846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_88_WIDTH },
84847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_89_CHECKER_TYPE,
84848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_89_WIDTH },
84849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_90_CHECKER_TYPE,
84850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_90_WIDTH },
84851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_91_CHECKER_TYPE,
84852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_91_WIDTH },
84853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_92_CHECKER_TYPE,
84854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_92_WIDTH },
84855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_93_CHECKER_TYPE,
84856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_93_WIDTH },
84857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_94_CHECKER_TYPE,
84858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_94_WIDTH },
84859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_95_CHECKER_TYPE,
84860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_95_WIDTH },
84861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_96_CHECKER_TYPE,
84862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_96_WIDTH },
84863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_97_CHECKER_TYPE,
84864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_97_WIDTH },
84865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_98_CHECKER_TYPE,
84866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_98_WIDTH },
84867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_99_CHECKER_TYPE,
84868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_99_WIDTH },
84869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_100_CHECKER_TYPE,
84870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_100_WIDTH },
84871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_101_CHECKER_TYPE,
84872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_101_WIDTH },
84873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_102_CHECKER_TYPE,
84874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_102_WIDTH },
84875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_103_CHECKER_TYPE,
84876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_103_WIDTH },
84877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_104_CHECKER_TYPE,
84878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_104_WIDTH },
84879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_105_CHECKER_TYPE,
84880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_105_WIDTH },
84881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_106_CHECKER_TYPE,
84882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_106_WIDTH },
84883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_107_CHECKER_TYPE,
84884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_107_WIDTH },
84885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_108_CHECKER_TYPE,
84886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_108_WIDTH },
84887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_109_CHECKER_TYPE,
84888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_109_WIDTH },
84889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_110_CHECKER_TYPE,
84890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_110_WIDTH },
84891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_111_CHECKER_TYPE,
84892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_111_WIDTH },
84893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_112_CHECKER_TYPE,
84894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_112_WIDTH },
84895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_113_CHECKER_TYPE,
84896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_113_WIDTH },
84897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_114_CHECKER_TYPE,
84898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_114_WIDTH },
84899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_115_CHECKER_TYPE,
84900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_115_WIDTH },
84901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_116_CHECKER_TYPE,
84902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_116_WIDTH },
84903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_117_CHECKER_TYPE,
84904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_117_WIDTH },
84905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_118_CHECKER_TYPE,
84906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_118_WIDTH },
84907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_119_CHECKER_TYPE,
84908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_119_WIDTH },
84909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_120_CHECKER_TYPE,
84910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_120_WIDTH },
84911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_121_CHECKER_TYPE,
84912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_121_WIDTH },
84913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_122_CHECKER_TYPE,
84914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_122_WIDTH },
84915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_123_CHECKER_TYPE,
84916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_123_WIDTH },
84917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_124_CHECKER_TYPE,
84918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_124_WIDTH },
84919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_125_CHECKER_TYPE,
84920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_125_WIDTH },
84921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_126_CHECKER_TYPE,
84922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_126_WIDTH },
84923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_127_CHECKER_TYPE,
84924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_127_WIDTH },
84925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_128_CHECKER_TYPE,
84926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_128_WIDTH },
84927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_129_CHECKER_TYPE,
84928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_129_WIDTH },
84929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_130_CHECKER_TYPE,
84930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_130_WIDTH },
84931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_131_CHECKER_TYPE,
84932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_131_WIDTH },
84933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_132_CHECKER_TYPE,
84934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_132_WIDTH },
84935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_133_CHECKER_TYPE,
84936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_133_WIDTH },
84937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_134_CHECKER_TYPE,
84938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_134_WIDTH },
84939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_135_CHECKER_TYPE,
84940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_135_WIDTH },
84941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_136_CHECKER_TYPE,
84942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_136_WIDTH },
84943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_137_CHECKER_TYPE,
84944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_137_WIDTH },
84945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_138_CHECKER_TYPE,
84946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_138_WIDTH },
84947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_139_CHECKER_TYPE,
84948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_139_WIDTH },
84949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_140_CHECKER_TYPE,
84950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_140_WIDTH },
84951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_141_CHECKER_TYPE,
84952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_141_WIDTH },
84953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_142_CHECKER_TYPE,
84954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_142_WIDTH },
84955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_143_CHECKER_TYPE,
84956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_143_WIDTH },
84957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_144_CHECKER_TYPE,
84958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_144_WIDTH },
84959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_145_CHECKER_TYPE,
84960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_145_WIDTH },
84961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_146_CHECKER_TYPE,
84962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_146_WIDTH },
84963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_147_CHECKER_TYPE,
84964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_147_WIDTH },
84965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_148_CHECKER_TYPE,
84966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_148_WIDTH },
84967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_149_CHECKER_TYPE,
84968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_149_WIDTH },
84969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_150_CHECKER_TYPE,
84970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_150_WIDTH },
84971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_151_CHECKER_TYPE,
84972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_151_WIDTH },
84973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_152_CHECKER_TYPE,
84974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_152_WIDTH },
84975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_153_CHECKER_TYPE,
84976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_153_WIDTH },
84977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_154_CHECKER_TYPE,
84978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_154_WIDTH },
84979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_155_CHECKER_TYPE,
84980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_155_WIDTH },
84981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_156_CHECKER_TYPE,
84982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_156_WIDTH },
84983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_157_CHECKER_TYPE,
84984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_157_WIDTH },
84985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_158_CHECKER_TYPE,
84986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_158_WIDTH },
84987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_159_CHECKER_TYPE,
84988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_159_WIDTH },
84989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_160_CHECKER_TYPE,
84990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_160_WIDTH },
84991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_161_CHECKER_TYPE,
84992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_161_WIDTH },
84993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_162_CHECKER_TYPE,
84994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_162_WIDTH },
84995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_163_CHECKER_TYPE,
84996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_163_WIDTH },
84997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_164_CHECKER_TYPE,
84998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_164_WIDTH },
84999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_165_CHECKER_TYPE,
85000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_165_WIDTH },
85001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_166_CHECKER_TYPE,
85002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_166_WIDTH },
85003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_167_CHECKER_TYPE,
85004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_167_WIDTH },
85005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_168_CHECKER_TYPE,
85006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_168_WIDTH },
85007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_169_CHECKER_TYPE,
85008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_169_WIDTH },
85009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_170_CHECKER_TYPE,
85010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_170_WIDTH },
85011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_171_CHECKER_TYPE,
85012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_171_WIDTH },
85013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_172_CHECKER_TYPE,
85014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_172_WIDTH },
85015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_173_CHECKER_TYPE,
85016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_173_WIDTH },
85017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_174_CHECKER_TYPE,
85018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_174_WIDTH },
85019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_175_CHECKER_TYPE,
85020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_175_WIDTH },
85021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_176_CHECKER_TYPE,
85022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_176_WIDTH },
85023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_177_CHECKER_TYPE,
85024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_177_WIDTH },
85025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_178_CHECKER_TYPE,
85026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_178_WIDTH },
85027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_179_CHECKER_TYPE,
85028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_179_WIDTH },
85029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_180_CHECKER_TYPE,
85030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_180_WIDTH },
85031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_181_CHECKER_TYPE,
85032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_181_WIDTH },
85033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_182_CHECKER_TYPE,
85034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_182_WIDTH },
85035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_183_CHECKER_TYPE,
85036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_183_WIDTH },
85037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_184_CHECKER_TYPE,
85038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_184_WIDTH },
85039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_185_CHECKER_TYPE,
85040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_185_WIDTH },
85041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_186_CHECKER_TYPE,
85042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_186_WIDTH },
85043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_187_CHECKER_TYPE,
85044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_187_WIDTH },
85045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_188_CHECKER_TYPE,
85046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_188_WIDTH },
85047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_189_CHECKER_TYPE,
85048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_189_WIDTH },
85049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_190_CHECKER_TYPE,
85050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_190_WIDTH },
85051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_191_CHECKER_TYPE,
85052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_191_WIDTH },
85053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_192_CHECKER_TYPE,
85054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_192_WIDTH },
85055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_193_CHECKER_TYPE,
85056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_193_WIDTH },
85057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_194_CHECKER_TYPE,
85058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_194_WIDTH },
85059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_195_CHECKER_TYPE,
85060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_195_WIDTH },
85061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_196_CHECKER_TYPE,
85062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_196_WIDTH },
85063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_197_CHECKER_TYPE,
85064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_197_WIDTH },
85065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_198_CHECKER_TYPE,
85066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_198_WIDTH },
85067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_199_CHECKER_TYPE,
85068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_199_WIDTH },
85069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_200_CHECKER_TYPE,
85070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_200_WIDTH },
85071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_201_CHECKER_TYPE,
85072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_201_WIDTH },
85073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_202_CHECKER_TYPE,
85074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_202_WIDTH },
85075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_203_CHECKER_TYPE,
85076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_203_WIDTH },
85077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_204_CHECKER_TYPE,
85078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_204_WIDTH },
85079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_205_CHECKER_TYPE,
85080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_205_WIDTH },
85081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_206_CHECKER_TYPE,
85082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_206_WIDTH },
85083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_207_CHECKER_TYPE,
85084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_207_WIDTH },
85085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_208_CHECKER_TYPE,
85086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_208_WIDTH },
85087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_209_CHECKER_TYPE,
85088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_209_WIDTH },
85089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_210_CHECKER_TYPE,
85090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_210_WIDTH },
85091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_211_CHECKER_TYPE,
85092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_211_WIDTH },
85093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_212_CHECKER_TYPE,
85094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_212_WIDTH },
85095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_213_CHECKER_TYPE,
85096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_213_WIDTH },
85097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_214_CHECKER_TYPE,
85098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_214_WIDTH },
85099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_215_CHECKER_TYPE,
85100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_215_WIDTH },
85101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_216_CHECKER_TYPE,
85102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_216_WIDTH },
85103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_217_CHECKER_TYPE,
85104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_217_WIDTH },
85105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_218_CHECKER_TYPE,
85106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_218_WIDTH },
85107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_219_CHECKER_TYPE,
85108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_219_WIDTH },
85109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_220_CHECKER_TYPE,
85110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_220_WIDTH },
85111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_221_CHECKER_TYPE,
85112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_221_WIDTH },
85113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_222_CHECKER_TYPE,
85114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_222_WIDTH },
85115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_223_CHECKER_TYPE,
85116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_223_WIDTH },
85117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_224_CHECKER_TYPE,
85118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_224_WIDTH },
85119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_225_CHECKER_TYPE,
85120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_225_WIDTH },
85121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_226_CHECKER_TYPE,
85122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_226_WIDTH },
85123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_227_CHECKER_TYPE,
85124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_227_WIDTH },
85125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_228_CHECKER_TYPE,
85126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_228_WIDTH },
85127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_229_CHECKER_TYPE,
85128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_229_WIDTH },
85129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_230_CHECKER_TYPE,
85130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_230_WIDTH },
85131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_231_CHECKER_TYPE,
85132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_231_WIDTH },
85133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_232_CHECKER_TYPE,
85134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_232_WIDTH },
85135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_233_CHECKER_TYPE,
85136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_233_WIDTH },
85137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_234_CHECKER_TYPE,
85138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_234_WIDTH },
85139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_235_CHECKER_TYPE,
85140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_235_WIDTH },
85141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_236_CHECKER_TYPE,
85142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_236_WIDTH },
85143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_237_CHECKER_TYPE,
85144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_237_WIDTH },
85145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_238_CHECKER_TYPE,
85146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_238_WIDTH },
85147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_239_CHECKER_TYPE,
85148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_239_WIDTH },
85149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_240_CHECKER_TYPE,
85150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_240_WIDTH },
85151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_241_CHECKER_TYPE,
85152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_241_WIDTH },
85153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_242_CHECKER_TYPE,
85154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_242_WIDTH },
85155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_243_CHECKER_TYPE,
85156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_243_WIDTH },
85157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_244_CHECKER_TYPE,
85158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_244_WIDTH },
85159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_245_CHECKER_TYPE,
85160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_245_WIDTH },
85161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_246_CHECKER_TYPE,
85162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_246_WIDTH },
85163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_247_CHECKER_TYPE,
85164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_247_WIDTH },
85165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_248_CHECKER_TYPE,
85166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_248_WIDTH },
85167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_249_CHECKER_TYPE,
85168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_249_WIDTH },
85169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_250_CHECKER_TYPE,
85170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_250_WIDTH },
85171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_251_CHECKER_TYPE,
85172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_251_WIDTH },
85173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_252_CHECKER_TYPE,
85174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_252_WIDTH },
85175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_253_CHECKER_TYPE,
85176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_253_WIDTH },
85177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_254_CHECKER_TYPE,
85178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_254_WIDTH },
85179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_255_CHECKER_TYPE,
85180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_255_WIDTH },
85181 };
85182 
85188 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS] =
85189 {
85190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_0_CHECKER_TYPE,
85191  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_0_WIDTH },
85192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_1_CHECKER_TYPE,
85193  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_1_WIDTH },
85194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_2_CHECKER_TYPE,
85195  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_2_WIDTH },
85196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_3_CHECKER_TYPE,
85197  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_3_WIDTH },
85198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_4_CHECKER_TYPE,
85199  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_4_WIDTH },
85200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_5_CHECKER_TYPE,
85201  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_5_WIDTH },
85202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_6_CHECKER_TYPE,
85203  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_6_WIDTH },
85204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_7_CHECKER_TYPE,
85205  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_7_WIDTH },
85206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_8_CHECKER_TYPE,
85207  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_8_WIDTH },
85208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_9_CHECKER_TYPE,
85209  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_9_WIDTH },
85210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_10_CHECKER_TYPE,
85211  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_10_WIDTH },
85212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_11_CHECKER_TYPE,
85213  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_11_WIDTH },
85214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_12_CHECKER_TYPE,
85215  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_12_WIDTH },
85216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_13_CHECKER_TYPE,
85217  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_13_WIDTH },
85218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_14_CHECKER_TYPE,
85219  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_14_WIDTH },
85220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_15_CHECKER_TYPE,
85221  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_15_WIDTH },
85222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_16_CHECKER_TYPE,
85223  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_16_WIDTH },
85224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_17_CHECKER_TYPE,
85225  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_17_WIDTH },
85226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_18_CHECKER_TYPE,
85227  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_18_WIDTH },
85228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_19_CHECKER_TYPE,
85229  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_19_WIDTH },
85230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_20_CHECKER_TYPE,
85231  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_20_WIDTH },
85232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_21_CHECKER_TYPE,
85233  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_21_WIDTH },
85234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_22_CHECKER_TYPE,
85235  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_22_WIDTH },
85236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_23_CHECKER_TYPE,
85237  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_23_WIDTH },
85238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_24_CHECKER_TYPE,
85239  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_24_WIDTH },
85240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_25_CHECKER_TYPE,
85241  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_25_WIDTH },
85242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_26_CHECKER_TYPE,
85243  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_26_WIDTH },
85244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_27_CHECKER_TYPE,
85245  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_27_WIDTH },
85246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_28_CHECKER_TYPE,
85247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_28_WIDTH },
85248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_29_CHECKER_TYPE,
85249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_29_WIDTH },
85250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_30_CHECKER_TYPE,
85251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_30_WIDTH },
85252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_31_CHECKER_TYPE,
85253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_31_WIDTH },
85254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_32_CHECKER_TYPE,
85255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_32_WIDTH },
85256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_33_CHECKER_TYPE,
85257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_33_WIDTH },
85258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_34_CHECKER_TYPE,
85259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_34_WIDTH },
85260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_35_CHECKER_TYPE,
85261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_35_WIDTH },
85262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_36_CHECKER_TYPE,
85263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_36_WIDTH },
85264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_37_CHECKER_TYPE,
85265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_37_WIDTH },
85266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_38_CHECKER_TYPE,
85267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_38_WIDTH },
85268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_39_CHECKER_TYPE,
85269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_39_WIDTH },
85270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_40_CHECKER_TYPE,
85271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_40_WIDTH },
85272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_41_CHECKER_TYPE,
85273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_41_WIDTH },
85274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_42_CHECKER_TYPE,
85275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_42_WIDTH },
85276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_43_CHECKER_TYPE,
85277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_43_WIDTH },
85278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_44_CHECKER_TYPE,
85279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_44_WIDTH },
85280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_45_CHECKER_TYPE,
85281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_45_WIDTH },
85282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_46_CHECKER_TYPE,
85283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_46_WIDTH },
85284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_47_CHECKER_TYPE,
85285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_47_WIDTH },
85286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_48_CHECKER_TYPE,
85287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_48_WIDTH },
85288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_49_CHECKER_TYPE,
85289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_49_WIDTH },
85290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_50_CHECKER_TYPE,
85291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_50_WIDTH },
85292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_51_CHECKER_TYPE,
85293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_51_WIDTH },
85294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_52_CHECKER_TYPE,
85295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_52_WIDTH },
85296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_53_CHECKER_TYPE,
85297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_53_WIDTH },
85298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_54_CHECKER_TYPE,
85299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_54_WIDTH },
85300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_55_CHECKER_TYPE,
85301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_55_WIDTH },
85302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_56_CHECKER_TYPE,
85303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_56_WIDTH },
85304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_57_CHECKER_TYPE,
85305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_57_WIDTH },
85306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_58_CHECKER_TYPE,
85307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_58_WIDTH },
85308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_59_CHECKER_TYPE,
85309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_59_WIDTH },
85310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_60_CHECKER_TYPE,
85311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_60_WIDTH },
85312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_61_CHECKER_TYPE,
85313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_61_WIDTH },
85314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_62_CHECKER_TYPE,
85315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_62_WIDTH },
85316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_63_CHECKER_TYPE,
85317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_63_WIDTH },
85318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_64_CHECKER_TYPE,
85319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_64_WIDTH },
85320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_65_CHECKER_TYPE,
85321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_65_WIDTH },
85322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_66_CHECKER_TYPE,
85323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_66_WIDTH },
85324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_67_CHECKER_TYPE,
85325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_67_WIDTH },
85326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_68_CHECKER_TYPE,
85327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_68_WIDTH },
85328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_69_CHECKER_TYPE,
85329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_69_WIDTH },
85330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_70_CHECKER_TYPE,
85331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_70_WIDTH },
85332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_71_CHECKER_TYPE,
85333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_71_WIDTH },
85334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_72_CHECKER_TYPE,
85335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_72_WIDTH },
85336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_73_CHECKER_TYPE,
85337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_73_WIDTH },
85338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_74_CHECKER_TYPE,
85339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_74_WIDTH },
85340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_75_CHECKER_TYPE,
85341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_75_WIDTH },
85342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_76_CHECKER_TYPE,
85343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_76_WIDTH },
85344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_77_CHECKER_TYPE,
85345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_77_WIDTH },
85346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_78_CHECKER_TYPE,
85347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_78_WIDTH },
85348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_79_CHECKER_TYPE,
85349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_79_WIDTH },
85350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_80_CHECKER_TYPE,
85351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_80_WIDTH },
85352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_81_CHECKER_TYPE,
85353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_81_WIDTH },
85354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_82_CHECKER_TYPE,
85355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_82_WIDTH },
85356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_83_CHECKER_TYPE,
85357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_83_WIDTH },
85358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_84_CHECKER_TYPE,
85359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_84_WIDTH },
85360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_85_CHECKER_TYPE,
85361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_85_WIDTH },
85362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_86_CHECKER_TYPE,
85363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_86_WIDTH },
85364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_87_CHECKER_TYPE,
85365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_87_WIDTH },
85366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_88_CHECKER_TYPE,
85367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_88_WIDTH },
85368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_89_CHECKER_TYPE,
85369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_89_WIDTH },
85370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_90_CHECKER_TYPE,
85371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_90_WIDTH },
85372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_91_CHECKER_TYPE,
85373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_91_WIDTH },
85374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_92_CHECKER_TYPE,
85375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_92_WIDTH },
85376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_93_CHECKER_TYPE,
85377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_93_WIDTH },
85378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_94_CHECKER_TYPE,
85379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_94_WIDTH },
85380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_95_CHECKER_TYPE,
85381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_95_WIDTH },
85382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_96_CHECKER_TYPE,
85383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_96_WIDTH },
85384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_97_CHECKER_TYPE,
85385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_97_WIDTH },
85386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_98_CHECKER_TYPE,
85387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_98_WIDTH },
85388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_99_CHECKER_TYPE,
85389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_99_WIDTH },
85390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_100_CHECKER_TYPE,
85391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_100_WIDTH },
85392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_101_CHECKER_TYPE,
85393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_101_WIDTH },
85394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_102_CHECKER_TYPE,
85395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_102_WIDTH },
85396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_103_CHECKER_TYPE,
85397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_103_WIDTH },
85398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_104_CHECKER_TYPE,
85399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_104_WIDTH },
85400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_105_CHECKER_TYPE,
85401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_105_WIDTH },
85402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_106_CHECKER_TYPE,
85403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_106_WIDTH },
85404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_107_CHECKER_TYPE,
85405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_107_WIDTH },
85406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_108_CHECKER_TYPE,
85407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_108_WIDTH },
85408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_109_CHECKER_TYPE,
85409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_109_WIDTH },
85410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_110_CHECKER_TYPE,
85411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_110_WIDTH },
85412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_111_CHECKER_TYPE,
85413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_111_WIDTH },
85414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_112_CHECKER_TYPE,
85415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_112_WIDTH },
85416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_113_CHECKER_TYPE,
85417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_113_WIDTH },
85418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_114_CHECKER_TYPE,
85419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_114_WIDTH },
85420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_115_CHECKER_TYPE,
85421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_115_WIDTH },
85422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_116_CHECKER_TYPE,
85423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_116_WIDTH },
85424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_117_CHECKER_TYPE,
85425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_117_WIDTH },
85426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_118_CHECKER_TYPE,
85427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_118_WIDTH },
85428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_119_CHECKER_TYPE,
85429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_119_WIDTH },
85430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_120_CHECKER_TYPE,
85431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_120_WIDTH },
85432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_121_CHECKER_TYPE,
85433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_121_WIDTH },
85434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_122_CHECKER_TYPE,
85435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_122_WIDTH },
85436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_123_CHECKER_TYPE,
85437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_123_WIDTH },
85438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_124_CHECKER_TYPE,
85439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_124_WIDTH },
85440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_125_CHECKER_TYPE,
85441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_125_WIDTH },
85442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_126_CHECKER_TYPE,
85443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_126_WIDTH },
85444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_127_CHECKER_TYPE,
85445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_127_WIDTH },
85446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_128_CHECKER_TYPE,
85447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_128_WIDTH },
85448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_129_CHECKER_TYPE,
85449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_129_WIDTH },
85450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_130_CHECKER_TYPE,
85451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_130_WIDTH },
85452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_131_CHECKER_TYPE,
85453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_131_WIDTH },
85454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_132_CHECKER_TYPE,
85455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_132_WIDTH },
85456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_133_CHECKER_TYPE,
85457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_133_WIDTH },
85458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_134_CHECKER_TYPE,
85459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_134_WIDTH },
85460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_135_CHECKER_TYPE,
85461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_135_WIDTH },
85462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_136_CHECKER_TYPE,
85463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_136_WIDTH },
85464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_137_CHECKER_TYPE,
85465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_137_WIDTH },
85466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_138_CHECKER_TYPE,
85467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_138_WIDTH },
85468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_139_CHECKER_TYPE,
85469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_139_WIDTH },
85470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_140_CHECKER_TYPE,
85471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_140_WIDTH },
85472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_141_CHECKER_TYPE,
85473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_141_WIDTH },
85474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_142_CHECKER_TYPE,
85475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_142_WIDTH },
85476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_143_CHECKER_TYPE,
85477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_143_WIDTH },
85478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_144_CHECKER_TYPE,
85479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_144_WIDTH },
85480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_145_CHECKER_TYPE,
85481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_145_WIDTH },
85482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_146_CHECKER_TYPE,
85483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_146_WIDTH },
85484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_147_CHECKER_TYPE,
85485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_147_WIDTH },
85486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_148_CHECKER_TYPE,
85487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_148_WIDTH },
85488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_149_CHECKER_TYPE,
85489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_149_WIDTH },
85490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_150_CHECKER_TYPE,
85491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_150_WIDTH },
85492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_151_CHECKER_TYPE,
85493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_151_WIDTH },
85494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_152_CHECKER_TYPE,
85495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_152_WIDTH },
85496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_153_CHECKER_TYPE,
85497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_153_WIDTH },
85498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_154_CHECKER_TYPE,
85499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_154_WIDTH },
85500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_155_CHECKER_TYPE,
85501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_155_WIDTH },
85502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_156_CHECKER_TYPE,
85503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_156_WIDTH },
85504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_157_CHECKER_TYPE,
85505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_157_WIDTH },
85506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_158_CHECKER_TYPE,
85507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_158_WIDTH },
85508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_159_CHECKER_TYPE,
85509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_159_WIDTH },
85510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_160_CHECKER_TYPE,
85511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_160_WIDTH },
85512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_161_CHECKER_TYPE,
85513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_161_WIDTH },
85514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_162_CHECKER_TYPE,
85515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_162_WIDTH },
85516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_163_CHECKER_TYPE,
85517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_163_WIDTH },
85518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_164_CHECKER_TYPE,
85519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_164_WIDTH },
85520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_165_CHECKER_TYPE,
85521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_165_WIDTH },
85522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_166_CHECKER_TYPE,
85523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_166_WIDTH },
85524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_167_CHECKER_TYPE,
85525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_167_WIDTH },
85526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_168_CHECKER_TYPE,
85527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_168_WIDTH },
85528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_169_CHECKER_TYPE,
85529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_169_WIDTH },
85530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_170_CHECKER_TYPE,
85531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_170_WIDTH },
85532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_171_CHECKER_TYPE,
85533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_171_WIDTH },
85534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_172_CHECKER_TYPE,
85535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_172_WIDTH },
85536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_173_CHECKER_TYPE,
85537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_173_WIDTH },
85538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_174_CHECKER_TYPE,
85539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_174_WIDTH },
85540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_175_CHECKER_TYPE,
85541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_175_WIDTH },
85542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_176_CHECKER_TYPE,
85543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_176_WIDTH },
85544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_177_CHECKER_TYPE,
85545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_177_WIDTH },
85546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_178_CHECKER_TYPE,
85547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_178_WIDTH },
85548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_179_CHECKER_TYPE,
85549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_179_WIDTH },
85550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_180_CHECKER_TYPE,
85551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_180_WIDTH },
85552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_181_CHECKER_TYPE,
85553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_181_WIDTH },
85554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_182_CHECKER_TYPE,
85555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_182_WIDTH },
85556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_183_CHECKER_TYPE,
85557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_183_WIDTH },
85558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_184_CHECKER_TYPE,
85559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_184_WIDTH },
85560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_185_CHECKER_TYPE,
85561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_185_WIDTH },
85562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_186_CHECKER_TYPE,
85563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_186_WIDTH },
85564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_187_CHECKER_TYPE,
85565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_187_WIDTH },
85566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_188_CHECKER_TYPE,
85567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_188_WIDTH },
85568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_189_CHECKER_TYPE,
85569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_189_WIDTH },
85570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_190_CHECKER_TYPE,
85571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_190_WIDTH },
85572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_191_CHECKER_TYPE,
85573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_191_WIDTH },
85574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_192_CHECKER_TYPE,
85575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_192_WIDTH },
85576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_193_CHECKER_TYPE,
85577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_193_WIDTH },
85578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_194_CHECKER_TYPE,
85579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_194_WIDTH },
85580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_195_CHECKER_TYPE,
85581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_195_WIDTH },
85582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_196_CHECKER_TYPE,
85583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_196_WIDTH },
85584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_197_CHECKER_TYPE,
85585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_197_WIDTH },
85586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_198_CHECKER_TYPE,
85587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_198_WIDTH },
85588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_199_CHECKER_TYPE,
85589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_199_WIDTH },
85590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_200_CHECKER_TYPE,
85591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_200_WIDTH },
85592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_201_CHECKER_TYPE,
85593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_201_WIDTH },
85594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_202_CHECKER_TYPE,
85595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_202_WIDTH },
85596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_203_CHECKER_TYPE,
85597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_203_WIDTH },
85598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_204_CHECKER_TYPE,
85599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_204_WIDTH },
85600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_205_CHECKER_TYPE,
85601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_205_WIDTH },
85602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_206_CHECKER_TYPE,
85603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_206_WIDTH },
85604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_207_CHECKER_TYPE,
85605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_207_WIDTH },
85606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_208_CHECKER_TYPE,
85607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_208_WIDTH },
85608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_209_CHECKER_TYPE,
85609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_209_WIDTH },
85610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_210_CHECKER_TYPE,
85611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_210_WIDTH },
85612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_211_CHECKER_TYPE,
85613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_211_WIDTH },
85614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_212_CHECKER_TYPE,
85615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_212_WIDTH },
85616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_213_CHECKER_TYPE,
85617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_213_WIDTH },
85618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_214_CHECKER_TYPE,
85619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_214_WIDTH },
85620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_215_CHECKER_TYPE,
85621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_215_WIDTH },
85622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_216_CHECKER_TYPE,
85623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_216_WIDTH },
85624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_217_CHECKER_TYPE,
85625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_217_WIDTH },
85626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_218_CHECKER_TYPE,
85627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_218_WIDTH },
85628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_219_CHECKER_TYPE,
85629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_219_WIDTH },
85630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_220_CHECKER_TYPE,
85631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_220_WIDTH },
85632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_221_CHECKER_TYPE,
85633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_221_WIDTH },
85634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_222_CHECKER_TYPE,
85635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_222_WIDTH },
85636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_223_CHECKER_TYPE,
85637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_223_WIDTH },
85638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_224_CHECKER_TYPE,
85639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_224_WIDTH },
85640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_225_CHECKER_TYPE,
85641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_225_WIDTH },
85642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_226_CHECKER_TYPE,
85643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_226_WIDTH },
85644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_227_CHECKER_TYPE,
85645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_227_WIDTH },
85646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_228_CHECKER_TYPE,
85647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_228_WIDTH },
85648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_229_CHECKER_TYPE,
85649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_229_WIDTH },
85650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_230_CHECKER_TYPE,
85651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_230_WIDTH },
85652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_231_CHECKER_TYPE,
85653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_231_WIDTH },
85654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_232_CHECKER_TYPE,
85655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_232_WIDTH },
85656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_233_CHECKER_TYPE,
85657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_233_WIDTH },
85658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_234_CHECKER_TYPE,
85659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_234_WIDTH },
85660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_235_CHECKER_TYPE,
85661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_235_WIDTH },
85662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_236_CHECKER_TYPE,
85663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_236_WIDTH },
85664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_237_CHECKER_TYPE,
85665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_237_WIDTH },
85666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_238_CHECKER_TYPE,
85667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_238_WIDTH },
85668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_239_CHECKER_TYPE,
85669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_239_WIDTH },
85670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_240_CHECKER_TYPE,
85671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_240_WIDTH },
85672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_241_CHECKER_TYPE,
85673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_241_WIDTH },
85674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_242_CHECKER_TYPE,
85675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_242_WIDTH },
85676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_243_CHECKER_TYPE,
85677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_243_WIDTH },
85678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_244_CHECKER_TYPE,
85679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_244_WIDTH },
85680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_245_CHECKER_TYPE,
85681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_245_WIDTH },
85682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_246_CHECKER_TYPE,
85683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_246_WIDTH },
85684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_247_CHECKER_TYPE,
85685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_247_WIDTH },
85686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_248_CHECKER_TYPE,
85687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_248_WIDTH },
85688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_249_CHECKER_TYPE,
85689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_249_WIDTH },
85690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_250_CHECKER_TYPE,
85691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_250_WIDTH },
85692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_251_CHECKER_TYPE,
85693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_251_WIDTH },
85694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_252_CHECKER_TYPE,
85695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_252_WIDTH },
85696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_253_CHECKER_TYPE,
85697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_253_WIDTH },
85698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_254_CHECKER_TYPE,
85699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_254_WIDTH },
85700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_255_CHECKER_TYPE,
85701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_GROUP_255_WIDTH },
85702 };
85703 
85709 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS] =
85710 {
85711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_0_CHECKER_TYPE,
85712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_0_WIDTH },
85713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_1_CHECKER_TYPE,
85714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_1_WIDTH },
85715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_2_CHECKER_TYPE,
85716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_2_WIDTH },
85717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_3_CHECKER_TYPE,
85718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_3_WIDTH },
85719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_4_CHECKER_TYPE,
85720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_4_WIDTH },
85721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_5_CHECKER_TYPE,
85722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_5_WIDTH },
85723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_6_CHECKER_TYPE,
85724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_6_WIDTH },
85725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_7_CHECKER_TYPE,
85726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_7_WIDTH },
85727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_8_CHECKER_TYPE,
85728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_8_WIDTH },
85729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_9_CHECKER_TYPE,
85730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_9_WIDTH },
85731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_10_CHECKER_TYPE,
85732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_10_WIDTH },
85733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_11_CHECKER_TYPE,
85734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_11_WIDTH },
85735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_12_CHECKER_TYPE,
85736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_12_WIDTH },
85737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_13_CHECKER_TYPE,
85738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_13_WIDTH },
85739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_14_CHECKER_TYPE,
85740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_14_WIDTH },
85741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_15_CHECKER_TYPE,
85742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_15_WIDTH },
85743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_16_CHECKER_TYPE,
85744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_16_WIDTH },
85745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_17_CHECKER_TYPE,
85746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_17_WIDTH },
85747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_18_CHECKER_TYPE,
85748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_18_WIDTH },
85749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_19_CHECKER_TYPE,
85750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_19_WIDTH },
85751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_20_CHECKER_TYPE,
85752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_20_WIDTH },
85753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_21_CHECKER_TYPE,
85754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_21_WIDTH },
85755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_22_CHECKER_TYPE,
85756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_22_WIDTH },
85757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_23_CHECKER_TYPE,
85758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_23_WIDTH },
85759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_24_CHECKER_TYPE,
85760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_24_WIDTH },
85761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_25_CHECKER_TYPE,
85762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_25_WIDTH },
85763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_26_CHECKER_TYPE,
85764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_26_WIDTH },
85765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_27_CHECKER_TYPE,
85766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_27_WIDTH },
85767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_28_CHECKER_TYPE,
85768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_28_WIDTH },
85769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_29_CHECKER_TYPE,
85770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_29_WIDTH },
85771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_30_CHECKER_TYPE,
85772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_30_WIDTH },
85773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_31_CHECKER_TYPE,
85774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_31_WIDTH },
85775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_32_CHECKER_TYPE,
85776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_32_WIDTH },
85777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_33_CHECKER_TYPE,
85778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_33_WIDTH },
85779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_34_CHECKER_TYPE,
85780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_34_WIDTH },
85781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_35_CHECKER_TYPE,
85782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_35_WIDTH },
85783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_36_CHECKER_TYPE,
85784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_36_WIDTH },
85785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_37_CHECKER_TYPE,
85786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_37_WIDTH },
85787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_38_CHECKER_TYPE,
85788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_38_WIDTH },
85789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_39_CHECKER_TYPE,
85790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_39_WIDTH },
85791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_40_CHECKER_TYPE,
85792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_40_WIDTH },
85793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_41_CHECKER_TYPE,
85794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_41_WIDTH },
85795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_42_CHECKER_TYPE,
85796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_42_WIDTH },
85797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_43_CHECKER_TYPE,
85798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_43_WIDTH },
85799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_44_CHECKER_TYPE,
85800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_44_WIDTH },
85801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_45_CHECKER_TYPE,
85802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_45_WIDTH },
85803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_46_CHECKER_TYPE,
85804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_46_WIDTH },
85805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_47_CHECKER_TYPE,
85806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_47_WIDTH },
85807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_48_CHECKER_TYPE,
85808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_48_WIDTH },
85809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_49_CHECKER_TYPE,
85810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_49_WIDTH },
85811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_50_CHECKER_TYPE,
85812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_50_WIDTH },
85813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_51_CHECKER_TYPE,
85814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_51_WIDTH },
85815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_52_CHECKER_TYPE,
85816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_52_WIDTH },
85817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_53_CHECKER_TYPE,
85818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_53_WIDTH },
85819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_54_CHECKER_TYPE,
85820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_54_WIDTH },
85821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_55_CHECKER_TYPE,
85822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_55_WIDTH },
85823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_56_CHECKER_TYPE,
85824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_56_WIDTH },
85825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_57_CHECKER_TYPE,
85826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_57_WIDTH },
85827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_58_CHECKER_TYPE,
85828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_58_WIDTH },
85829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_59_CHECKER_TYPE,
85830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_59_WIDTH },
85831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_60_CHECKER_TYPE,
85832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_60_WIDTH },
85833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_61_CHECKER_TYPE,
85834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_61_WIDTH },
85835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_62_CHECKER_TYPE,
85836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_62_WIDTH },
85837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_63_CHECKER_TYPE,
85838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_63_WIDTH },
85839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_64_CHECKER_TYPE,
85840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_64_WIDTH },
85841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_65_CHECKER_TYPE,
85842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_65_WIDTH },
85843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_66_CHECKER_TYPE,
85844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_66_WIDTH },
85845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_67_CHECKER_TYPE,
85846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_67_WIDTH },
85847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_68_CHECKER_TYPE,
85848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_68_WIDTH },
85849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_69_CHECKER_TYPE,
85850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_69_WIDTH },
85851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_70_CHECKER_TYPE,
85852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_70_WIDTH },
85853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_71_CHECKER_TYPE,
85854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_71_WIDTH },
85855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_72_CHECKER_TYPE,
85856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_72_WIDTH },
85857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_73_CHECKER_TYPE,
85858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_73_WIDTH },
85859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_74_CHECKER_TYPE,
85860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_74_WIDTH },
85861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_75_CHECKER_TYPE,
85862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_75_WIDTH },
85863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_76_CHECKER_TYPE,
85864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_76_WIDTH },
85865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_77_CHECKER_TYPE,
85866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_77_WIDTH },
85867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_78_CHECKER_TYPE,
85868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_78_WIDTH },
85869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_79_CHECKER_TYPE,
85870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_79_WIDTH },
85871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_80_CHECKER_TYPE,
85872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_80_WIDTH },
85873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_81_CHECKER_TYPE,
85874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_81_WIDTH },
85875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_82_CHECKER_TYPE,
85876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_82_WIDTH },
85877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_83_CHECKER_TYPE,
85878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_83_WIDTH },
85879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_84_CHECKER_TYPE,
85880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_84_WIDTH },
85881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_85_CHECKER_TYPE,
85882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_85_WIDTH },
85883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_86_CHECKER_TYPE,
85884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_86_WIDTH },
85885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_87_CHECKER_TYPE,
85886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_87_WIDTH },
85887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_88_CHECKER_TYPE,
85888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_88_WIDTH },
85889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_89_CHECKER_TYPE,
85890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_89_WIDTH },
85891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_90_CHECKER_TYPE,
85892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_90_WIDTH },
85893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_91_CHECKER_TYPE,
85894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_91_WIDTH },
85895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_92_CHECKER_TYPE,
85896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_92_WIDTH },
85897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_93_CHECKER_TYPE,
85898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_93_WIDTH },
85899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_94_CHECKER_TYPE,
85900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_94_WIDTH },
85901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_95_CHECKER_TYPE,
85902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_95_WIDTH },
85903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_96_CHECKER_TYPE,
85904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_96_WIDTH },
85905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_97_CHECKER_TYPE,
85906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_97_WIDTH },
85907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_98_CHECKER_TYPE,
85908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_98_WIDTH },
85909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_99_CHECKER_TYPE,
85910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_99_WIDTH },
85911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_100_CHECKER_TYPE,
85912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_100_WIDTH },
85913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_101_CHECKER_TYPE,
85914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_101_WIDTH },
85915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_102_CHECKER_TYPE,
85916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_102_WIDTH },
85917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_103_CHECKER_TYPE,
85918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_103_WIDTH },
85919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_104_CHECKER_TYPE,
85920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_104_WIDTH },
85921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_105_CHECKER_TYPE,
85922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_105_WIDTH },
85923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_106_CHECKER_TYPE,
85924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_106_WIDTH },
85925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_107_CHECKER_TYPE,
85926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_107_WIDTH },
85927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_108_CHECKER_TYPE,
85928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_108_WIDTH },
85929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_109_CHECKER_TYPE,
85930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_109_WIDTH },
85931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_110_CHECKER_TYPE,
85932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_110_WIDTH },
85933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_111_CHECKER_TYPE,
85934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_111_WIDTH },
85935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_112_CHECKER_TYPE,
85936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_112_WIDTH },
85937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_113_CHECKER_TYPE,
85938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_113_WIDTH },
85939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_114_CHECKER_TYPE,
85940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_114_WIDTH },
85941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_115_CHECKER_TYPE,
85942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_115_WIDTH },
85943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_116_CHECKER_TYPE,
85944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_116_WIDTH },
85945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_117_CHECKER_TYPE,
85946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_117_WIDTH },
85947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_118_CHECKER_TYPE,
85948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_118_WIDTH },
85949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_119_CHECKER_TYPE,
85950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_119_WIDTH },
85951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_120_CHECKER_TYPE,
85952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_120_WIDTH },
85953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_121_CHECKER_TYPE,
85954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_121_WIDTH },
85955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_122_CHECKER_TYPE,
85956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_122_WIDTH },
85957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_123_CHECKER_TYPE,
85958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_123_WIDTH },
85959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_124_CHECKER_TYPE,
85960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_124_WIDTH },
85961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_125_CHECKER_TYPE,
85962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_125_WIDTH },
85963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_126_CHECKER_TYPE,
85964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_126_WIDTH },
85965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_127_CHECKER_TYPE,
85966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_127_WIDTH },
85967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_128_CHECKER_TYPE,
85968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_128_WIDTH },
85969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_129_CHECKER_TYPE,
85970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_129_WIDTH },
85971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_130_CHECKER_TYPE,
85972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_130_WIDTH },
85973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_131_CHECKER_TYPE,
85974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_131_WIDTH },
85975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_132_CHECKER_TYPE,
85976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_132_WIDTH },
85977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_133_CHECKER_TYPE,
85978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_133_WIDTH },
85979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_134_CHECKER_TYPE,
85980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_134_WIDTH },
85981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_135_CHECKER_TYPE,
85982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_135_WIDTH },
85983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_136_CHECKER_TYPE,
85984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_136_WIDTH },
85985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_137_CHECKER_TYPE,
85986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_137_WIDTH },
85987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_138_CHECKER_TYPE,
85988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_138_WIDTH },
85989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_139_CHECKER_TYPE,
85990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_139_WIDTH },
85991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_140_CHECKER_TYPE,
85992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_140_WIDTH },
85993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_141_CHECKER_TYPE,
85994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_141_WIDTH },
85995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_142_CHECKER_TYPE,
85996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_142_WIDTH },
85997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_143_CHECKER_TYPE,
85998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_143_WIDTH },
85999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_144_CHECKER_TYPE,
86000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_144_WIDTH },
86001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_145_CHECKER_TYPE,
86002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_145_WIDTH },
86003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_146_CHECKER_TYPE,
86004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_146_WIDTH },
86005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_147_CHECKER_TYPE,
86006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_147_WIDTH },
86007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_148_CHECKER_TYPE,
86008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_148_WIDTH },
86009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_149_CHECKER_TYPE,
86010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_149_WIDTH },
86011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_150_CHECKER_TYPE,
86012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_150_WIDTH },
86013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_151_CHECKER_TYPE,
86014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_151_WIDTH },
86015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_152_CHECKER_TYPE,
86016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_152_WIDTH },
86017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_153_CHECKER_TYPE,
86018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_153_WIDTH },
86019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_154_CHECKER_TYPE,
86020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_154_WIDTH },
86021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_155_CHECKER_TYPE,
86022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_155_WIDTH },
86023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_156_CHECKER_TYPE,
86024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_156_WIDTH },
86025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_157_CHECKER_TYPE,
86026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_157_WIDTH },
86027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_158_CHECKER_TYPE,
86028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_158_WIDTH },
86029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_159_CHECKER_TYPE,
86030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_159_WIDTH },
86031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_160_CHECKER_TYPE,
86032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_160_WIDTH },
86033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_161_CHECKER_TYPE,
86034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_161_WIDTH },
86035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_162_CHECKER_TYPE,
86036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_162_WIDTH },
86037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_163_CHECKER_TYPE,
86038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_163_WIDTH },
86039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_164_CHECKER_TYPE,
86040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_164_WIDTH },
86041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_165_CHECKER_TYPE,
86042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_165_WIDTH },
86043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_166_CHECKER_TYPE,
86044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_166_WIDTH },
86045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_167_CHECKER_TYPE,
86046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_167_WIDTH },
86047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_168_CHECKER_TYPE,
86048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_168_WIDTH },
86049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_169_CHECKER_TYPE,
86050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_169_WIDTH },
86051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_170_CHECKER_TYPE,
86052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_170_WIDTH },
86053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_171_CHECKER_TYPE,
86054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_171_WIDTH },
86055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_172_CHECKER_TYPE,
86056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_172_WIDTH },
86057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_173_CHECKER_TYPE,
86058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_173_WIDTH },
86059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_174_CHECKER_TYPE,
86060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_174_WIDTH },
86061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_175_CHECKER_TYPE,
86062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_175_WIDTH },
86063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_176_CHECKER_TYPE,
86064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_176_WIDTH },
86065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_177_CHECKER_TYPE,
86066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_177_WIDTH },
86067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_178_CHECKER_TYPE,
86068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_178_WIDTH },
86069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_179_CHECKER_TYPE,
86070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_179_WIDTH },
86071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_180_CHECKER_TYPE,
86072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_180_WIDTH },
86073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_181_CHECKER_TYPE,
86074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_181_WIDTH },
86075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_182_CHECKER_TYPE,
86076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_182_WIDTH },
86077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_183_CHECKER_TYPE,
86078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_183_WIDTH },
86079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_184_CHECKER_TYPE,
86080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_184_WIDTH },
86081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_185_CHECKER_TYPE,
86082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_185_WIDTH },
86083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_186_CHECKER_TYPE,
86084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_186_WIDTH },
86085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_187_CHECKER_TYPE,
86086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_187_WIDTH },
86087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_188_CHECKER_TYPE,
86088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_188_WIDTH },
86089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_189_CHECKER_TYPE,
86090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_189_WIDTH },
86091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_190_CHECKER_TYPE,
86092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_190_WIDTH },
86093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_191_CHECKER_TYPE,
86094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_191_WIDTH },
86095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_192_CHECKER_TYPE,
86096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_192_WIDTH },
86097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_193_CHECKER_TYPE,
86098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_193_WIDTH },
86099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_194_CHECKER_TYPE,
86100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_194_WIDTH },
86101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_195_CHECKER_TYPE,
86102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_195_WIDTH },
86103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_196_CHECKER_TYPE,
86104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_196_WIDTH },
86105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_197_CHECKER_TYPE,
86106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_197_WIDTH },
86107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_198_CHECKER_TYPE,
86108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_198_WIDTH },
86109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_199_CHECKER_TYPE,
86110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_199_WIDTH },
86111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_200_CHECKER_TYPE,
86112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_200_WIDTH },
86113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_201_CHECKER_TYPE,
86114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_201_WIDTH },
86115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_202_CHECKER_TYPE,
86116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_202_WIDTH },
86117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_203_CHECKER_TYPE,
86118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_203_WIDTH },
86119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_204_CHECKER_TYPE,
86120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_204_WIDTH },
86121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_205_CHECKER_TYPE,
86122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_205_WIDTH },
86123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_206_CHECKER_TYPE,
86124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_206_WIDTH },
86125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_207_CHECKER_TYPE,
86126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_207_WIDTH },
86127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_208_CHECKER_TYPE,
86128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_208_WIDTH },
86129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_209_CHECKER_TYPE,
86130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_209_WIDTH },
86131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_210_CHECKER_TYPE,
86132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_210_WIDTH },
86133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_211_CHECKER_TYPE,
86134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_211_WIDTH },
86135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_212_CHECKER_TYPE,
86136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_212_WIDTH },
86137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_213_CHECKER_TYPE,
86138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_213_WIDTH },
86139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_214_CHECKER_TYPE,
86140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_214_WIDTH },
86141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_215_CHECKER_TYPE,
86142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_215_WIDTH },
86143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_216_CHECKER_TYPE,
86144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_216_WIDTH },
86145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_217_CHECKER_TYPE,
86146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_217_WIDTH },
86147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_218_CHECKER_TYPE,
86148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_218_WIDTH },
86149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_219_CHECKER_TYPE,
86150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_219_WIDTH },
86151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_220_CHECKER_TYPE,
86152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_220_WIDTH },
86153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_221_CHECKER_TYPE,
86154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_221_WIDTH },
86155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_222_CHECKER_TYPE,
86156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_222_WIDTH },
86157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_223_CHECKER_TYPE,
86158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_223_WIDTH },
86159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_224_CHECKER_TYPE,
86160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_224_WIDTH },
86161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_225_CHECKER_TYPE,
86162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_225_WIDTH },
86163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_226_CHECKER_TYPE,
86164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_226_WIDTH },
86165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_227_CHECKER_TYPE,
86166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_227_WIDTH },
86167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_228_CHECKER_TYPE,
86168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_228_WIDTH },
86169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_229_CHECKER_TYPE,
86170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_229_WIDTH },
86171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_230_CHECKER_TYPE,
86172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_230_WIDTH },
86173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_231_CHECKER_TYPE,
86174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_231_WIDTH },
86175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_232_CHECKER_TYPE,
86176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_232_WIDTH },
86177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_233_CHECKER_TYPE,
86178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_233_WIDTH },
86179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_234_CHECKER_TYPE,
86180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_234_WIDTH },
86181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_235_CHECKER_TYPE,
86182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_235_WIDTH },
86183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_236_CHECKER_TYPE,
86184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_236_WIDTH },
86185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_237_CHECKER_TYPE,
86186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_237_WIDTH },
86187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_238_CHECKER_TYPE,
86188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_238_WIDTH },
86189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_239_CHECKER_TYPE,
86190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_239_WIDTH },
86191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_240_CHECKER_TYPE,
86192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_240_WIDTH },
86193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_241_CHECKER_TYPE,
86194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_241_WIDTH },
86195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_242_CHECKER_TYPE,
86196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_242_WIDTH },
86197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_243_CHECKER_TYPE,
86198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_243_WIDTH },
86199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_244_CHECKER_TYPE,
86200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_244_WIDTH },
86201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_245_CHECKER_TYPE,
86202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_245_WIDTH },
86203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_246_CHECKER_TYPE,
86204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_246_WIDTH },
86205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_247_CHECKER_TYPE,
86206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_247_WIDTH },
86207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_248_CHECKER_TYPE,
86208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_248_WIDTH },
86209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_249_CHECKER_TYPE,
86210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_249_WIDTH },
86211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_250_CHECKER_TYPE,
86212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_250_WIDTH },
86213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_251_CHECKER_TYPE,
86214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_251_WIDTH },
86215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_252_CHECKER_TYPE,
86216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_252_WIDTH },
86217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_253_CHECKER_TYPE,
86218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_253_WIDTH },
86219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_254_CHECKER_TYPE,
86220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_254_WIDTH },
86221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_255_CHECKER_TYPE,
86222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_GROUP_255_WIDTH },
86223 };
86224 
86230 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS] =
86231 {
86232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_0_CHECKER_TYPE,
86233  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_0_WIDTH },
86234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_1_CHECKER_TYPE,
86235  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_1_WIDTH },
86236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_2_CHECKER_TYPE,
86237  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_2_WIDTH },
86238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_3_CHECKER_TYPE,
86239  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_3_WIDTH },
86240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_4_CHECKER_TYPE,
86241  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_4_WIDTH },
86242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_5_CHECKER_TYPE,
86243  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_5_WIDTH },
86244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_6_CHECKER_TYPE,
86245  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_6_WIDTH },
86246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_7_CHECKER_TYPE,
86247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_7_WIDTH },
86248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_8_CHECKER_TYPE,
86249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_8_WIDTH },
86250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_9_CHECKER_TYPE,
86251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_9_WIDTH },
86252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_10_CHECKER_TYPE,
86253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_10_WIDTH },
86254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_11_CHECKER_TYPE,
86255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_11_WIDTH },
86256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_12_CHECKER_TYPE,
86257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_12_WIDTH },
86258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_13_CHECKER_TYPE,
86259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_13_WIDTH },
86260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_14_CHECKER_TYPE,
86261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_14_WIDTH },
86262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_15_CHECKER_TYPE,
86263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_15_WIDTH },
86264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_16_CHECKER_TYPE,
86265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_16_WIDTH },
86266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_17_CHECKER_TYPE,
86267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_17_WIDTH },
86268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_18_CHECKER_TYPE,
86269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_18_WIDTH },
86270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_19_CHECKER_TYPE,
86271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_19_WIDTH },
86272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_20_CHECKER_TYPE,
86273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_20_WIDTH },
86274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_21_CHECKER_TYPE,
86275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_21_WIDTH },
86276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_22_CHECKER_TYPE,
86277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_22_WIDTH },
86278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_23_CHECKER_TYPE,
86279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_23_WIDTH },
86280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_24_CHECKER_TYPE,
86281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_24_WIDTH },
86282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_25_CHECKER_TYPE,
86283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_25_WIDTH },
86284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_26_CHECKER_TYPE,
86285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_26_WIDTH },
86286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_27_CHECKER_TYPE,
86287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_27_WIDTH },
86288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_28_CHECKER_TYPE,
86289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_28_WIDTH },
86290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_29_CHECKER_TYPE,
86291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_29_WIDTH },
86292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_30_CHECKER_TYPE,
86293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_30_WIDTH },
86294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_31_CHECKER_TYPE,
86295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_31_WIDTH },
86296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_32_CHECKER_TYPE,
86297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_32_WIDTH },
86298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_33_CHECKER_TYPE,
86299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_33_WIDTH },
86300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_34_CHECKER_TYPE,
86301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_34_WIDTH },
86302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_35_CHECKER_TYPE,
86303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_35_WIDTH },
86304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_36_CHECKER_TYPE,
86305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_36_WIDTH },
86306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_37_CHECKER_TYPE,
86307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_37_WIDTH },
86308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_38_CHECKER_TYPE,
86309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_38_WIDTH },
86310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_39_CHECKER_TYPE,
86311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_39_WIDTH },
86312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_40_CHECKER_TYPE,
86313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_40_WIDTH },
86314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_41_CHECKER_TYPE,
86315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_41_WIDTH },
86316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_42_CHECKER_TYPE,
86317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_42_WIDTH },
86318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_43_CHECKER_TYPE,
86319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_43_WIDTH },
86320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_44_CHECKER_TYPE,
86321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_44_WIDTH },
86322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_45_CHECKER_TYPE,
86323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_45_WIDTH },
86324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_46_CHECKER_TYPE,
86325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_46_WIDTH },
86326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_47_CHECKER_TYPE,
86327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_47_WIDTH },
86328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_48_CHECKER_TYPE,
86329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_48_WIDTH },
86330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_49_CHECKER_TYPE,
86331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_49_WIDTH },
86332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_50_CHECKER_TYPE,
86333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_50_WIDTH },
86334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_51_CHECKER_TYPE,
86335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_51_WIDTH },
86336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_52_CHECKER_TYPE,
86337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_52_WIDTH },
86338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_53_CHECKER_TYPE,
86339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_53_WIDTH },
86340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_54_CHECKER_TYPE,
86341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_54_WIDTH },
86342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_55_CHECKER_TYPE,
86343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_55_WIDTH },
86344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_56_CHECKER_TYPE,
86345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_56_WIDTH },
86346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_57_CHECKER_TYPE,
86347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_57_WIDTH },
86348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_58_CHECKER_TYPE,
86349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_58_WIDTH },
86350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_59_CHECKER_TYPE,
86351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_59_WIDTH },
86352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_60_CHECKER_TYPE,
86353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_60_WIDTH },
86354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_61_CHECKER_TYPE,
86355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_61_WIDTH },
86356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_62_CHECKER_TYPE,
86357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_62_WIDTH },
86358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_63_CHECKER_TYPE,
86359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_63_WIDTH },
86360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_64_CHECKER_TYPE,
86361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_64_WIDTH },
86362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_65_CHECKER_TYPE,
86363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_65_WIDTH },
86364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_66_CHECKER_TYPE,
86365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_66_WIDTH },
86366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_67_CHECKER_TYPE,
86367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_67_WIDTH },
86368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_68_CHECKER_TYPE,
86369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_68_WIDTH },
86370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_69_CHECKER_TYPE,
86371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_69_WIDTH },
86372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_70_CHECKER_TYPE,
86373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_70_WIDTH },
86374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_71_CHECKER_TYPE,
86375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_71_WIDTH },
86376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_72_CHECKER_TYPE,
86377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_72_WIDTH },
86378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_73_CHECKER_TYPE,
86379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_73_WIDTH },
86380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_74_CHECKER_TYPE,
86381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_74_WIDTH },
86382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_75_CHECKER_TYPE,
86383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_75_WIDTH },
86384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_76_CHECKER_TYPE,
86385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_76_WIDTH },
86386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_77_CHECKER_TYPE,
86387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_77_WIDTH },
86388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_78_CHECKER_TYPE,
86389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_78_WIDTH },
86390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_79_CHECKER_TYPE,
86391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_79_WIDTH },
86392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_80_CHECKER_TYPE,
86393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_80_WIDTH },
86394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_81_CHECKER_TYPE,
86395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_81_WIDTH },
86396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_82_CHECKER_TYPE,
86397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_82_WIDTH },
86398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_83_CHECKER_TYPE,
86399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_83_WIDTH },
86400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_84_CHECKER_TYPE,
86401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_84_WIDTH },
86402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_85_CHECKER_TYPE,
86403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_85_WIDTH },
86404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_86_CHECKER_TYPE,
86405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_86_WIDTH },
86406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_87_CHECKER_TYPE,
86407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_87_WIDTH },
86408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_88_CHECKER_TYPE,
86409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_88_WIDTH },
86410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_89_CHECKER_TYPE,
86411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_89_WIDTH },
86412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_90_CHECKER_TYPE,
86413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_90_WIDTH },
86414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_91_CHECKER_TYPE,
86415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_91_WIDTH },
86416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_92_CHECKER_TYPE,
86417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_92_WIDTH },
86418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_93_CHECKER_TYPE,
86419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_93_WIDTH },
86420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_94_CHECKER_TYPE,
86421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_94_WIDTH },
86422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_95_CHECKER_TYPE,
86423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_95_WIDTH },
86424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_96_CHECKER_TYPE,
86425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_96_WIDTH },
86426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_97_CHECKER_TYPE,
86427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_97_WIDTH },
86428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_98_CHECKER_TYPE,
86429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_98_WIDTH },
86430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_99_CHECKER_TYPE,
86431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_99_WIDTH },
86432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_100_CHECKER_TYPE,
86433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_100_WIDTH },
86434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_101_CHECKER_TYPE,
86435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_101_WIDTH },
86436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_102_CHECKER_TYPE,
86437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_102_WIDTH },
86438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_103_CHECKER_TYPE,
86439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_103_WIDTH },
86440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_104_CHECKER_TYPE,
86441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_104_WIDTH },
86442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_105_CHECKER_TYPE,
86443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_105_WIDTH },
86444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_106_CHECKER_TYPE,
86445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_106_WIDTH },
86446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_107_CHECKER_TYPE,
86447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_107_WIDTH },
86448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_108_CHECKER_TYPE,
86449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_108_WIDTH },
86450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_109_CHECKER_TYPE,
86451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_109_WIDTH },
86452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_110_CHECKER_TYPE,
86453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_110_WIDTH },
86454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_111_CHECKER_TYPE,
86455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_111_WIDTH },
86456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_112_CHECKER_TYPE,
86457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_112_WIDTH },
86458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_113_CHECKER_TYPE,
86459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_113_WIDTH },
86460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_114_CHECKER_TYPE,
86461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_114_WIDTH },
86462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_115_CHECKER_TYPE,
86463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_115_WIDTH },
86464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_116_CHECKER_TYPE,
86465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_116_WIDTH },
86466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_117_CHECKER_TYPE,
86467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_117_WIDTH },
86468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_118_CHECKER_TYPE,
86469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_118_WIDTH },
86470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_119_CHECKER_TYPE,
86471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_119_WIDTH },
86472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_120_CHECKER_TYPE,
86473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_120_WIDTH },
86474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_121_CHECKER_TYPE,
86475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_121_WIDTH },
86476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_122_CHECKER_TYPE,
86477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_122_WIDTH },
86478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_123_CHECKER_TYPE,
86479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_123_WIDTH },
86480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_124_CHECKER_TYPE,
86481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_124_WIDTH },
86482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_125_CHECKER_TYPE,
86483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_125_WIDTH },
86484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_126_CHECKER_TYPE,
86485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_126_WIDTH },
86486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_127_CHECKER_TYPE,
86487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_127_WIDTH },
86488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_128_CHECKER_TYPE,
86489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_128_WIDTH },
86490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_129_CHECKER_TYPE,
86491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_129_WIDTH },
86492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_130_CHECKER_TYPE,
86493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_130_WIDTH },
86494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_131_CHECKER_TYPE,
86495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_131_WIDTH },
86496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_132_CHECKER_TYPE,
86497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_132_WIDTH },
86498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_133_CHECKER_TYPE,
86499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_133_WIDTH },
86500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_134_CHECKER_TYPE,
86501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_134_WIDTH },
86502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_135_CHECKER_TYPE,
86503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_135_WIDTH },
86504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_136_CHECKER_TYPE,
86505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_136_WIDTH },
86506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_137_CHECKER_TYPE,
86507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_137_WIDTH },
86508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_138_CHECKER_TYPE,
86509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_138_WIDTH },
86510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_139_CHECKER_TYPE,
86511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_139_WIDTH },
86512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_140_CHECKER_TYPE,
86513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_140_WIDTH },
86514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_141_CHECKER_TYPE,
86515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_141_WIDTH },
86516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_142_CHECKER_TYPE,
86517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_142_WIDTH },
86518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_143_CHECKER_TYPE,
86519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_143_WIDTH },
86520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_144_CHECKER_TYPE,
86521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_144_WIDTH },
86522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_145_CHECKER_TYPE,
86523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_145_WIDTH },
86524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_146_CHECKER_TYPE,
86525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_146_WIDTH },
86526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_147_CHECKER_TYPE,
86527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_147_WIDTH },
86528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_148_CHECKER_TYPE,
86529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_148_WIDTH },
86530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_149_CHECKER_TYPE,
86531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_149_WIDTH },
86532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_150_CHECKER_TYPE,
86533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_150_WIDTH },
86534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_151_CHECKER_TYPE,
86535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_151_WIDTH },
86536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_152_CHECKER_TYPE,
86537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_152_WIDTH },
86538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_153_CHECKER_TYPE,
86539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_153_WIDTH },
86540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_154_CHECKER_TYPE,
86541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_154_WIDTH },
86542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_155_CHECKER_TYPE,
86543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_155_WIDTH },
86544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_156_CHECKER_TYPE,
86545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_156_WIDTH },
86546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_157_CHECKER_TYPE,
86547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_157_WIDTH },
86548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_158_CHECKER_TYPE,
86549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_158_WIDTH },
86550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_159_CHECKER_TYPE,
86551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_159_WIDTH },
86552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_160_CHECKER_TYPE,
86553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_160_WIDTH },
86554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_161_CHECKER_TYPE,
86555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_161_WIDTH },
86556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_162_CHECKER_TYPE,
86557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_162_WIDTH },
86558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_163_CHECKER_TYPE,
86559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_163_WIDTH },
86560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_164_CHECKER_TYPE,
86561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_164_WIDTH },
86562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_165_CHECKER_TYPE,
86563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_165_WIDTH },
86564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_166_CHECKER_TYPE,
86565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_166_WIDTH },
86566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_167_CHECKER_TYPE,
86567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_167_WIDTH },
86568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_168_CHECKER_TYPE,
86569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_168_WIDTH },
86570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_169_CHECKER_TYPE,
86571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_169_WIDTH },
86572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_170_CHECKER_TYPE,
86573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_170_WIDTH },
86574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_171_CHECKER_TYPE,
86575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_171_WIDTH },
86576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_172_CHECKER_TYPE,
86577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_172_WIDTH },
86578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_173_CHECKER_TYPE,
86579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_173_WIDTH },
86580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_174_CHECKER_TYPE,
86581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_174_WIDTH },
86582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_175_CHECKER_TYPE,
86583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_175_WIDTH },
86584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_176_CHECKER_TYPE,
86585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_176_WIDTH },
86586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_177_CHECKER_TYPE,
86587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_177_WIDTH },
86588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_178_CHECKER_TYPE,
86589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_178_WIDTH },
86590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_179_CHECKER_TYPE,
86591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_179_WIDTH },
86592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_180_CHECKER_TYPE,
86593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_180_WIDTH },
86594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_181_CHECKER_TYPE,
86595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_181_WIDTH },
86596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_182_CHECKER_TYPE,
86597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_182_WIDTH },
86598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_183_CHECKER_TYPE,
86599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_183_WIDTH },
86600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_184_CHECKER_TYPE,
86601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_184_WIDTH },
86602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_185_CHECKER_TYPE,
86603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_185_WIDTH },
86604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_186_CHECKER_TYPE,
86605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_186_WIDTH },
86606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_187_CHECKER_TYPE,
86607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_187_WIDTH },
86608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_188_CHECKER_TYPE,
86609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_188_WIDTH },
86610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_189_CHECKER_TYPE,
86611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_189_WIDTH },
86612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_190_CHECKER_TYPE,
86613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_190_WIDTH },
86614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_191_CHECKER_TYPE,
86615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_191_WIDTH },
86616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_192_CHECKER_TYPE,
86617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_192_WIDTH },
86618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_193_CHECKER_TYPE,
86619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_193_WIDTH },
86620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_194_CHECKER_TYPE,
86621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_194_WIDTH },
86622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_195_CHECKER_TYPE,
86623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_195_WIDTH },
86624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_196_CHECKER_TYPE,
86625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_196_WIDTH },
86626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_197_CHECKER_TYPE,
86627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_197_WIDTH },
86628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_198_CHECKER_TYPE,
86629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_198_WIDTH },
86630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_199_CHECKER_TYPE,
86631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_199_WIDTH },
86632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_200_CHECKER_TYPE,
86633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_200_WIDTH },
86634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_201_CHECKER_TYPE,
86635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_201_WIDTH },
86636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_202_CHECKER_TYPE,
86637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_202_WIDTH },
86638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_203_CHECKER_TYPE,
86639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_203_WIDTH },
86640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_204_CHECKER_TYPE,
86641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_204_WIDTH },
86642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_205_CHECKER_TYPE,
86643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_205_WIDTH },
86644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_206_CHECKER_TYPE,
86645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_206_WIDTH },
86646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_207_CHECKER_TYPE,
86647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_207_WIDTH },
86648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_208_CHECKER_TYPE,
86649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_208_WIDTH },
86650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_209_CHECKER_TYPE,
86651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_209_WIDTH },
86652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_210_CHECKER_TYPE,
86653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_210_WIDTH },
86654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_211_CHECKER_TYPE,
86655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_211_WIDTH },
86656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_212_CHECKER_TYPE,
86657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_212_WIDTH },
86658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_213_CHECKER_TYPE,
86659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_213_WIDTH },
86660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_214_CHECKER_TYPE,
86661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_214_WIDTH },
86662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_215_CHECKER_TYPE,
86663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_215_WIDTH },
86664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_216_CHECKER_TYPE,
86665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_216_WIDTH },
86666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_217_CHECKER_TYPE,
86667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_217_WIDTH },
86668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_218_CHECKER_TYPE,
86669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_218_WIDTH },
86670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_219_CHECKER_TYPE,
86671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_219_WIDTH },
86672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_220_CHECKER_TYPE,
86673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_220_WIDTH },
86674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_221_CHECKER_TYPE,
86675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_221_WIDTH },
86676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_222_CHECKER_TYPE,
86677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_222_WIDTH },
86678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_223_CHECKER_TYPE,
86679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_223_WIDTH },
86680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_224_CHECKER_TYPE,
86681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_224_WIDTH },
86682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_225_CHECKER_TYPE,
86683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_225_WIDTH },
86684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_226_CHECKER_TYPE,
86685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_226_WIDTH },
86686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_227_CHECKER_TYPE,
86687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_227_WIDTH },
86688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_228_CHECKER_TYPE,
86689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_228_WIDTH },
86690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_229_CHECKER_TYPE,
86691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_229_WIDTH },
86692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_230_CHECKER_TYPE,
86693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_230_WIDTH },
86694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_231_CHECKER_TYPE,
86695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_231_WIDTH },
86696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_232_CHECKER_TYPE,
86697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_232_WIDTH },
86698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_233_CHECKER_TYPE,
86699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_233_WIDTH },
86700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_234_CHECKER_TYPE,
86701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_234_WIDTH },
86702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_235_CHECKER_TYPE,
86703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_235_WIDTH },
86704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_236_CHECKER_TYPE,
86705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_236_WIDTH },
86706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_237_CHECKER_TYPE,
86707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_237_WIDTH },
86708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_238_CHECKER_TYPE,
86709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_238_WIDTH },
86710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_239_CHECKER_TYPE,
86711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_239_WIDTH },
86712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_240_CHECKER_TYPE,
86713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_240_WIDTH },
86714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_241_CHECKER_TYPE,
86715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_241_WIDTH },
86716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_242_CHECKER_TYPE,
86717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_242_WIDTH },
86718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_243_CHECKER_TYPE,
86719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_243_WIDTH },
86720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_244_CHECKER_TYPE,
86721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_244_WIDTH },
86722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_245_CHECKER_TYPE,
86723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_245_WIDTH },
86724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_246_CHECKER_TYPE,
86725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_246_WIDTH },
86726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_247_CHECKER_TYPE,
86727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_247_WIDTH },
86728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_248_CHECKER_TYPE,
86729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_248_WIDTH },
86730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_249_CHECKER_TYPE,
86731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_249_WIDTH },
86732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_250_CHECKER_TYPE,
86733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_250_WIDTH },
86734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_251_CHECKER_TYPE,
86735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_251_WIDTH },
86736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_252_CHECKER_TYPE,
86737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_252_WIDTH },
86738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_253_CHECKER_TYPE,
86739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_253_WIDTH },
86740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_254_CHECKER_TYPE,
86741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_254_WIDTH },
86742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_255_CHECKER_TYPE,
86743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_GROUP_255_WIDTH },
86744 };
86745 
86751 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS] =
86752 {
86753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_0_CHECKER_TYPE,
86754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_0_WIDTH },
86755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_1_CHECKER_TYPE,
86756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_1_WIDTH },
86757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_2_CHECKER_TYPE,
86758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_2_WIDTH },
86759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_3_CHECKER_TYPE,
86760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_3_WIDTH },
86761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_4_CHECKER_TYPE,
86762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_4_WIDTH },
86763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_5_CHECKER_TYPE,
86764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_5_WIDTH },
86765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_6_CHECKER_TYPE,
86766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_6_WIDTH },
86767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_7_CHECKER_TYPE,
86768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_7_WIDTH },
86769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_8_CHECKER_TYPE,
86770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_8_WIDTH },
86771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_9_CHECKER_TYPE,
86772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_9_WIDTH },
86773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_10_CHECKER_TYPE,
86774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_10_WIDTH },
86775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_11_CHECKER_TYPE,
86776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_11_WIDTH },
86777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_12_CHECKER_TYPE,
86778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_12_WIDTH },
86779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_13_CHECKER_TYPE,
86780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_13_WIDTH },
86781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_14_CHECKER_TYPE,
86782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_14_WIDTH },
86783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_15_CHECKER_TYPE,
86784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_15_WIDTH },
86785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_16_CHECKER_TYPE,
86786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_16_WIDTH },
86787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_17_CHECKER_TYPE,
86788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_17_WIDTH },
86789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_18_CHECKER_TYPE,
86790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_18_WIDTH },
86791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_19_CHECKER_TYPE,
86792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_19_WIDTH },
86793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_20_CHECKER_TYPE,
86794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_20_WIDTH },
86795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_21_CHECKER_TYPE,
86796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_21_WIDTH },
86797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_22_CHECKER_TYPE,
86798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_22_WIDTH },
86799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_23_CHECKER_TYPE,
86800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_23_WIDTH },
86801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_24_CHECKER_TYPE,
86802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_24_WIDTH },
86803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_25_CHECKER_TYPE,
86804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_25_WIDTH },
86805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_26_CHECKER_TYPE,
86806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_26_WIDTH },
86807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_27_CHECKER_TYPE,
86808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_27_WIDTH },
86809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_28_CHECKER_TYPE,
86810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_28_WIDTH },
86811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_29_CHECKER_TYPE,
86812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_29_WIDTH },
86813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_30_CHECKER_TYPE,
86814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_30_WIDTH },
86815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_31_CHECKER_TYPE,
86816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_31_WIDTH },
86817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_32_CHECKER_TYPE,
86818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_32_WIDTH },
86819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_33_CHECKER_TYPE,
86820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_33_WIDTH },
86821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_34_CHECKER_TYPE,
86822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_34_WIDTH },
86823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_35_CHECKER_TYPE,
86824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_35_WIDTH },
86825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_36_CHECKER_TYPE,
86826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_36_WIDTH },
86827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_37_CHECKER_TYPE,
86828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_37_WIDTH },
86829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_38_CHECKER_TYPE,
86830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_38_WIDTH },
86831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_39_CHECKER_TYPE,
86832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_39_WIDTH },
86833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_40_CHECKER_TYPE,
86834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_40_WIDTH },
86835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_41_CHECKER_TYPE,
86836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_41_WIDTH },
86837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_42_CHECKER_TYPE,
86838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_42_WIDTH },
86839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_43_CHECKER_TYPE,
86840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_43_WIDTH },
86841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_44_CHECKER_TYPE,
86842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_44_WIDTH },
86843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_45_CHECKER_TYPE,
86844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_45_WIDTH },
86845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_46_CHECKER_TYPE,
86846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_46_WIDTH },
86847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_47_CHECKER_TYPE,
86848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_47_WIDTH },
86849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_48_CHECKER_TYPE,
86850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_48_WIDTH },
86851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_49_CHECKER_TYPE,
86852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_49_WIDTH },
86853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_50_CHECKER_TYPE,
86854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_50_WIDTH },
86855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_51_CHECKER_TYPE,
86856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_51_WIDTH },
86857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_52_CHECKER_TYPE,
86858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_52_WIDTH },
86859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_53_CHECKER_TYPE,
86860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_53_WIDTH },
86861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_54_CHECKER_TYPE,
86862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_54_WIDTH },
86863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_55_CHECKER_TYPE,
86864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_55_WIDTH },
86865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_56_CHECKER_TYPE,
86866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_56_WIDTH },
86867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_57_CHECKER_TYPE,
86868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_57_WIDTH },
86869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_58_CHECKER_TYPE,
86870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_58_WIDTH },
86871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_59_CHECKER_TYPE,
86872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_59_WIDTH },
86873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_60_CHECKER_TYPE,
86874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_60_WIDTH },
86875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_61_CHECKER_TYPE,
86876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_61_WIDTH },
86877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_62_CHECKER_TYPE,
86878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_62_WIDTH },
86879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_63_CHECKER_TYPE,
86880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_63_WIDTH },
86881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_64_CHECKER_TYPE,
86882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_64_WIDTH },
86883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_65_CHECKER_TYPE,
86884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_65_WIDTH },
86885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_66_CHECKER_TYPE,
86886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_66_WIDTH },
86887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_67_CHECKER_TYPE,
86888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_67_WIDTH },
86889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_68_CHECKER_TYPE,
86890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_68_WIDTH },
86891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_69_CHECKER_TYPE,
86892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_69_WIDTH },
86893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_70_CHECKER_TYPE,
86894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_70_WIDTH },
86895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_71_CHECKER_TYPE,
86896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_71_WIDTH },
86897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_72_CHECKER_TYPE,
86898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_72_WIDTH },
86899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_73_CHECKER_TYPE,
86900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_73_WIDTH },
86901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_74_CHECKER_TYPE,
86902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_74_WIDTH },
86903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_75_CHECKER_TYPE,
86904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_75_WIDTH },
86905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_76_CHECKER_TYPE,
86906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_76_WIDTH },
86907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_77_CHECKER_TYPE,
86908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_77_WIDTH },
86909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_78_CHECKER_TYPE,
86910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_78_WIDTH },
86911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_79_CHECKER_TYPE,
86912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_79_WIDTH },
86913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_80_CHECKER_TYPE,
86914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_80_WIDTH },
86915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_81_CHECKER_TYPE,
86916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_81_WIDTH },
86917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_82_CHECKER_TYPE,
86918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_82_WIDTH },
86919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_83_CHECKER_TYPE,
86920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_83_WIDTH },
86921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_84_CHECKER_TYPE,
86922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_84_WIDTH },
86923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_85_CHECKER_TYPE,
86924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_85_WIDTH },
86925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_86_CHECKER_TYPE,
86926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_86_WIDTH },
86927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_87_CHECKER_TYPE,
86928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_87_WIDTH },
86929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_88_CHECKER_TYPE,
86930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_88_WIDTH },
86931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_89_CHECKER_TYPE,
86932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_89_WIDTH },
86933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_90_CHECKER_TYPE,
86934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_90_WIDTH },
86935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_91_CHECKER_TYPE,
86936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_91_WIDTH },
86937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_92_CHECKER_TYPE,
86938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_92_WIDTH },
86939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_93_CHECKER_TYPE,
86940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_93_WIDTH },
86941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_94_CHECKER_TYPE,
86942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_94_WIDTH },
86943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_95_CHECKER_TYPE,
86944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_95_WIDTH },
86945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_96_CHECKER_TYPE,
86946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_96_WIDTH },
86947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_97_CHECKER_TYPE,
86948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_97_WIDTH },
86949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_98_CHECKER_TYPE,
86950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_98_WIDTH },
86951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_99_CHECKER_TYPE,
86952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_99_WIDTH },
86953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_100_CHECKER_TYPE,
86954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_100_WIDTH },
86955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_101_CHECKER_TYPE,
86956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_101_WIDTH },
86957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_102_CHECKER_TYPE,
86958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_102_WIDTH },
86959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_103_CHECKER_TYPE,
86960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_103_WIDTH },
86961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_104_CHECKER_TYPE,
86962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_104_WIDTH },
86963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_105_CHECKER_TYPE,
86964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_105_WIDTH },
86965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_106_CHECKER_TYPE,
86966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_106_WIDTH },
86967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_107_CHECKER_TYPE,
86968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_107_WIDTH },
86969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_108_CHECKER_TYPE,
86970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_108_WIDTH },
86971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_109_CHECKER_TYPE,
86972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_109_WIDTH },
86973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_110_CHECKER_TYPE,
86974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_110_WIDTH },
86975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_111_CHECKER_TYPE,
86976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_111_WIDTH },
86977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_112_CHECKER_TYPE,
86978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_112_WIDTH },
86979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_113_CHECKER_TYPE,
86980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_113_WIDTH },
86981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_114_CHECKER_TYPE,
86982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_114_WIDTH },
86983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_115_CHECKER_TYPE,
86984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_115_WIDTH },
86985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_116_CHECKER_TYPE,
86986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_116_WIDTH },
86987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_117_CHECKER_TYPE,
86988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_117_WIDTH },
86989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_118_CHECKER_TYPE,
86990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_118_WIDTH },
86991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_119_CHECKER_TYPE,
86992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_119_WIDTH },
86993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_120_CHECKER_TYPE,
86994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_120_WIDTH },
86995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_121_CHECKER_TYPE,
86996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_121_WIDTH },
86997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_122_CHECKER_TYPE,
86998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_122_WIDTH },
86999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_123_CHECKER_TYPE,
87000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_123_WIDTH },
87001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_124_CHECKER_TYPE,
87002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_124_WIDTH },
87003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_125_CHECKER_TYPE,
87004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_125_WIDTH },
87005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_126_CHECKER_TYPE,
87006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_126_WIDTH },
87007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_127_CHECKER_TYPE,
87008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_127_WIDTH },
87009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_128_CHECKER_TYPE,
87010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_128_WIDTH },
87011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_129_CHECKER_TYPE,
87012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_129_WIDTH },
87013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_130_CHECKER_TYPE,
87014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_130_WIDTH },
87015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_131_CHECKER_TYPE,
87016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_131_WIDTH },
87017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_132_CHECKER_TYPE,
87018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_132_WIDTH },
87019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_133_CHECKER_TYPE,
87020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_133_WIDTH },
87021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_134_CHECKER_TYPE,
87022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_134_WIDTH },
87023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_135_CHECKER_TYPE,
87024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_135_WIDTH },
87025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_136_CHECKER_TYPE,
87026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_136_WIDTH },
87027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_137_CHECKER_TYPE,
87028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_137_WIDTH },
87029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_138_CHECKER_TYPE,
87030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_138_WIDTH },
87031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_139_CHECKER_TYPE,
87032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_139_WIDTH },
87033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_140_CHECKER_TYPE,
87034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_140_WIDTH },
87035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_141_CHECKER_TYPE,
87036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_141_WIDTH },
87037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_142_CHECKER_TYPE,
87038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_142_WIDTH },
87039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_143_CHECKER_TYPE,
87040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_143_WIDTH },
87041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_144_CHECKER_TYPE,
87042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_144_WIDTH },
87043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_145_CHECKER_TYPE,
87044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_145_WIDTH },
87045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_146_CHECKER_TYPE,
87046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_146_WIDTH },
87047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_147_CHECKER_TYPE,
87048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_147_WIDTH },
87049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_148_CHECKER_TYPE,
87050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_148_WIDTH },
87051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_149_CHECKER_TYPE,
87052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_149_WIDTH },
87053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_150_CHECKER_TYPE,
87054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_150_WIDTH },
87055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_151_CHECKER_TYPE,
87056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_151_WIDTH },
87057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_152_CHECKER_TYPE,
87058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_152_WIDTH },
87059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_153_CHECKER_TYPE,
87060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_153_WIDTH },
87061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_154_CHECKER_TYPE,
87062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_154_WIDTH },
87063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_155_CHECKER_TYPE,
87064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_155_WIDTH },
87065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_156_CHECKER_TYPE,
87066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_156_WIDTH },
87067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_157_CHECKER_TYPE,
87068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_157_WIDTH },
87069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_158_CHECKER_TYPE,
87070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_158_WIDTH },
87071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_159_CHECKER_TYPE,
87072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_159_WIDTH },
87073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_160_CHECKER_TYPE,
87074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_160_WIDTH },
87075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_161_CHECKER_TYPE,
87076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_161_WIDTH },
87077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_162_CHECKER_TYPE,
87078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_162_WIDTH },
87079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_163_CHECKER_TYPE,
87080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_163_WIDTH },
87081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_164_CHECKER_TYPE,
87082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_164_WIDTH },
87083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_165_CHECKER_TYPE,
87084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_165_WIDTH },
87085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_166_CHECKER_TYPE,
87086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_166_WIDTH },
87087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_167_CHECKER_TYPE,
87088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_167_WIDTH },
87089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_168_CHECKER_TYPE,
87090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_168_WIDTH },
87091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_169_CHECKER_TYPE,
87092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_169_WIDTH },
87093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_170_CHECKER_TYPE,
87094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_170_WIDTH },
87095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_171_CHECKER_TYPE,
87096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_171_WIDTH },
87097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_172_CHECKER_TYPE,
87098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_172_WIDTH },
87099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_173_CHECKER_TYPE,
87100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_173_WIDTH },
87101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_174_CHECKER_TYPE,
87102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_174_WIDTH },
87103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_175_CHECKER_TYPE,
87104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_175_WIDTH },
87105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_176_CHECKER_TYPE,
87106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_176_WIDTH },
87107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_177_CHECKER_TYPE,
87108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_177_WIDTH },
87109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_178_CHECKER_TYPE,
87110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_178_WIDTH },
87111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_179_CHECKER_TYPE,
87112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_179_WIDTH },
87113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_180_CHECKER_TYPE,
87114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_180_WIDTH },
87115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_181_CHECKER_TYPE,
87116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_181_WIDTH },
87117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_182_CHECKER_TYPE,
87118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_182_WIDTH },
87119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_183_CHECKER_TYPE,
87120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_183_WIDTH },
87121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_184_CHECKER_TYPE,
87122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_184_WIDTH },
87123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_185_CHECKER_TYPE,
87124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_185_WIDTH },
87125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_186_CHECKER_TYPE,
87126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_186_WIDTH },
87127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_187_CHECKER_TYPE,
87128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_187_WIDTH },
87129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_188_CHECKER_TYPE,
87130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_188_WIDTH },
87131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_189_CHECKER_TYPE,
87132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_189_WIDTH },
87133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_190_CHECKER_TYPE,
87134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_190_WIDTH },
87135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_191_CHECKER_TYPE,
87136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_191_WIDTH },
87137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_192_CHECKER_TYPE,
87138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_192_WIDTH },
87139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_193_CHECKER_TYPE,
87140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_193_WIDTH },
87141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_194_CHECKER_TYPE,
87142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_194_WIDTH },
87143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_195_CHECKER_TYPE,
87144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_195_WIDTH },
87145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_196_CHECKER_TYPE,
87146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_196_WIDTH },
87147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_197_CHECKER_TYPE,
87148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_197_WIDTH },
87149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_198_CHECKER_TYPE,
87150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_198_WIDTH },
87151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_199_CHECKER_TYPE,
87152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_199_WIDTH },
87153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_200_CHECKER_TYPE,
87154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_200_WIDTH },
87155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_201_CHECKER_TYPE,
87156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_201_WIDTH },
87157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_202_CHECKER_TYPE,
87158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_202_WIDTH },
87159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_203_CHECKER_TYPE,
87160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_203_WIDTH },
87161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_204_CHECKER_TYPE,
87162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_204_WIDTH },
87163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_205_CHECKER_TYPE,
87164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_205_WIDTH },
87165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_206_CHECKER_TYPE,
87166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_206_WIDTH },
87167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_207_CHECKER_TYPE,
87168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_207_WIDTH },
87169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_208_CHECKER_TYPE,
87170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_208_WIDTH },
87171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_209_CHECKER_TYPE,
87172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_209_WIDTH },
87173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_210_CHECKER_TYPE,
87174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_210_WIDTH },
87175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_211_CHECKER_TYPE,
87176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_211_WIDTH },
87177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_212_CHECKER_TYPE,
87178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_212_WIDTH },
87179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_213_CHECKER_TYPE,
87180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_213_WIDTH },
87181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_214_CHECKER_TYPE,
87182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_214_WIDTH },
87183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_215_CHECKER_TYPE,
87184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_215_WIDTH },
87185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_216_CHECKER_TYPE,
87186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_216_WIDTH },
87187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_217_CHECKER_TYPE,
87188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_217_WIDTH },
87189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_218_CHECKER_TYPE,
87190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_218_WIDTH },
87191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_219_CHECKER_TYPE,
87192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_219_WIDTH },
87193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_220_CHECKER_TYPE,
87194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_220_WIDTH },
87195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_221_CHECKER_TYPE,
87196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_221_WIDTH },
87197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_222_CHECKER_TYPE,
87198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_222_WIDTH },
87199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_223_CHECKER_TYPE,
87200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_223_WIDTH },
87201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_224_CHECKER_TYPE,
87202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_224_WIDTH },
87203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_225_CHECKER_TYPE,
87204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_225_WIDTH },
87205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_226_CHECKER_TYPE,
87206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_226_WIDTH },
87207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_227_CHECKER_TYPE,
87208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_227_WIDTH },
87209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_228_CHECKER_TYPE,
87210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_228_WIDTH },
87211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_229_CHECKER_TYPE,
87212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_229_WIDTH },
87213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_230_CHECKER_TYPE,
87214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_230_WIDTH },
87215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_231_CHECKER_TYPE,
87216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_231_WIDTH },
87217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_232_CHECKER_TYPE,
87218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_232_WIDTH },
87219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_233_CHECKER_TYPE,
87220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_233_WIDTH },
87221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_234_CHECKER_TYPE,
87222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_234_WIDTH },
87223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_235_CHECKER_TYPE,
87224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_235_WIDTH },
87225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_236_CHECKER_TYPE,
87226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_236_WIDTH },
87227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_237_CHECKER_TYPE,
87228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_237_WIDTH },
87229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_238_CHECKER_TYPE,
87230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_238_WIDTH },
87231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_239_CHECKER_TYPE,
87232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_239_WIDTH },
87233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_240_CHECKER_TYPE,
87234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_240_WIDTH },
87235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_241_CHECKER_TYPE,
87236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_241_WIDTH },
87237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_242_CHECKER_TYPE,
87238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_242_WIDTH },
87239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_243_CHECKER_TYPE,
87240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_243_WIDTH },
87241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_244_CHECKER_TYPE,
87242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_244_WIDTH },
87243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_245_CHECKER_TYPE,
87244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_245_WIDTH },
87245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_246_CHECKER_TYPE,
87246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_246_WIDTH },
87247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_247_CHECKER_TYPE,
87248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_247_WIDTH },
87249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_248_CHECKER_TYPE,
87250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_248_WIDTH },
87251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_249_CHECKER_TYPE,
87252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_249_WIDTH },
87253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_250_CHECKER_TYPE,
87254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_250_WIDTH },
87255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_251_CHECKER_TYPE,
87256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_251_WIDTH },
87257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_252_CHECKER_TYPE,
87258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_252_WIDTH },
87259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_253_CHECKER_TYPE,
87260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_253_WIDTH },
87261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_254_CHECKER_TYPE,
87262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_254_WIDTH },
87263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_255_CHECKER_TYPE,
87264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_GROUP_255_WIDTH },
87265 };
87266 
87272 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS] =
87273 {
87274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_0_CHECKER_TYPE,
87275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_0_WIDTH },
87276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_1_CHECKER_TYPE,
87277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_1_WIDTH },
87278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_2_CHECKER_TYPE,
87279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_2_WIDTH },
87280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_3_CHECKER_TYPE,
87281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_3_WIDTH },
87282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_4_CHECKER_TYPE,
87283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_4_WIDTH },
87284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_5_CHECKER_TYPE,
87285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_5_WIDTH },
87286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_6_CHECKER_TYPE,
87287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_6_WIDTH },
87288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_7_CHECKER_TYPE,
87289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_7_WIDTH },
87290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_8_CHECKER_TYPE,
87291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_8_WIDTH },
87292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_9_CHECKER_TYPE,
87293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_9_WIDTH },
87294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_10_CHECKER_TYPE,
87295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_10_WIDTH },
87296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_11_CHECKER_TYPE,
87297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_11_WIDTH },
87298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_12_CHECKER_TYPE,
87299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_12_WIDTH },
87300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_13_CHECKER_TYPE,
87301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_13_WIDTH },
87302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_14_CHECKER_TYPE,
87303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_14_WIDTH },
87304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_15_CHECKER_TYPE,
87305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_15_WIDTH },
87306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_16_CHECKER_TYPE,
87307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_16_WIDTH },
87308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_17_CHECKER_TYPE,
87309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_17_WIDTH },
87310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_18_CHECKER_TYPE,
87311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_18_WIDTH },
87312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_19_CHECKER_TYPE,
87313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_19_WIDTH },
87314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_20_CHECKER_TYPE,
87315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_20_WIDTH },
87316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_21_CHECKER_TYPE,
87317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_21_WIDTH },
87318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_22_CHECKER_TYPE,
87319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_22_WIDTH },
87320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_23_CHECKER_TYPE,
87321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_23_WIDTH },
87322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_24_CHECKER_TYPE,
87323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_24_WIDTH },
87324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_25_CHECKER_TYPE,
87325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_25_WIDTH },
87326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_26_CHECKER_TYPE,
87327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_26_WIDTH },
87328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_27_CHECKER_TYPE,
87329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_27_WIDTH },
87330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_28_CHECKER_TYPE,
87331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_28_WIDTH },
87332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_29_CHECKER_TYPE,
87333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_29_WIDTH },
87334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_30_CHECKER_TYPE,
87335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_30_WIDTH },
87336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_31_CHECKER_TYPE,
87337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_31_WIDTH },
87338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_32_CHECKER_TYPE,
87339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_32_WIDTH },
87340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_33_CHECKER_TYPE,
87341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_33_WIDTH },
87342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_34_CHECKER_TYPE,
87343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_34_WIDTH },
87344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_35_CHECKER_TYPE,
87345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_35_WIDTH },
87346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_36_CHECKER_TYPE,
87347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_36_WIDTH },
87348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_37_CHECKER_TYPE,
87349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_37_WIDTH },
87350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_38_CHECKER_TYPE,
87351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_38_WIDTH },
87352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_39_CHECKER_TYPE,
87353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_39_WIDTH },
87354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_40_CHECKER_TYPE,
87355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_40_WIDTH },
87356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_41_CHECKER_TYPE,
87357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_41_WIDTH },
87358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_42_CHECKER_TYPE,
87359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_42_WIDTH },
87360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_43_CHECKER_TYPE,
87361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_43_WIDTH },
87362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_44_CHECKER_TYPE,
87363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_44_WIDTH },
87364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_45_CHECKER_TYPE,
87365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_45_WIDTH },
87366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_46_CHECKER_TYPE,
87367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_46_WIDTH },
87368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_47_CHECKER_TYPE,
87369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_47_WIDTH },
87370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_48_CHECKER_TYPE,
87371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_48_WIDTH },
87372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_49_CHECKER_TYPE,
87373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_49_WIDTH },
87374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_50_CHECKER_TYPE,
87375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_50_WIDTH },
87376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_51_CHECKER_TYPE,
87377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_51_WIDTH },
87378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_52_CHECKER_TYPE,
87379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_52_WIDTH },
87380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_53_CHECKER_TYPE,
87381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_53_WIDTH },
87382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_54_CHECKER_TYPE,
87383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_54_WIDTH },
87384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_55_CHECKER_TYPE,
87385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_55_WIDTH },
87386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_56_CHECKER_TYPE,
87387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_56_WIDTH },
87388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_57_CHECKER_TYPE,
87389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_57_WIDTH },
87390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_58_CHECKER_TYPE,
87391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_58_WIDTH },
87392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_59_CHECKER_TYPE,
87393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_59_WIDTH },
87394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_60_CHECKER_TYPE,
87395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_60_WIDTH },
87396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_61_CHECKER_TYPE,
87397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_61_WIDTH },
87398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_62_CHECKER_TYPE,
87399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_62_WIDTH },
87400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_63_CHECKER_TYPE,
87401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_63_WIDTH },
87402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_64_CHECKER_TYPE,
87403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_64_WIDTH },
87404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_65_CHECKER_TYPE,
87405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_65_WIDTH },
87406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_66_CHECKER_TYPE,
87407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_66_WIDTH },
87408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_67_CHECKER_TYPE,
87409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_67_WIDTH },
87410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_68_CHECKER_TYPE,
87411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_68_WIDTH },
87412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_69_CHECKER_TYPE,
87413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_69_WIDTH },
87414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_70_CHECKER_TYPE,
87415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_70_WIDTH },
87416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_71_CHECKER_TYPE,
87417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_71_WIDTH },
87418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_72_CHECKER_TYPE,
87419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_72_WIDTH },
87420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_73_CHECKER_TYPE,
87421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_73_WIDTH },
87422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_74_CHECKER_TYPE,
87423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_74_WIDTH },
87424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_75_CHECKER_TYPE,
87425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_75_WIDTH },
87426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_76_CHECKER_TYPE,
87427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_76_WIDTH },
87428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_77_CHECKER_TYPE,
87429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_77_WIDTH },
87430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_78_CHECKER_TYPE,
87431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_78_WIDTH },
87432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_79_CHECKER_TYPE,
87433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_79_WIDTH },
87434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_80_CHECKER_TYPE,
87435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_80_WIDTH },
87436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_81_CHECKER_TYPE,
87437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_81_WIDTH },
87438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_82_CHECKER_TYPE,
87439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_82_WIDTH },
87440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_83_CHECKER_TYPE,
87441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_83_WIDTH },
87442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_84_CHECKER_TYPE,
87443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_84_WIDTH },
87444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_85_CHECKER_TYPE,
87445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_85_WIDTH },
87446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_86_CHECKER_TYPE,
87447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_86_WIDTH },
87448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_87_CHECKER_TYPE,
87449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_87_WIDTH },
87450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_88_CHECKER_TYPE,
87451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_88_WIDTH },
87452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_89_CHECKER_TYPE,
87453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_89_WIDTH },
87454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_90_CHECKER_TYPE,
87455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_90_WIDTH },
87456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_91_CHECKER_TYPE,
87457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_91_WIDTH },
87458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_92_CHECKER_TYPE,
87459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_92_WIDTH },
87460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_93_CHECKER_TYPE,
87461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_93_WIDTH },
87462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_94_CHECKER_TYPE,
87463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_94_WIDTH },
87464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_95_CHECKER_TYPE,
87465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_95_WIDTH },
87466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_96_CHECKER_TYPE,
87467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_96_WIDTH },
87468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_97_CHECKER_TYPE,
87469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_97_WIDTH },
87470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_98_CHECKER_TYPE,
87471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_98_WIDTH },
87472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_99_CHECKER_TYPE,
87473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_99_WIDTH },
87474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_100_CHECKER_TYPE,
87475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_100_WIDTH },
87476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_101_CHECKER_TYPE,
87477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_101_WIDTH },
87478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_102_CHECKER_TYPE,
87479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_102_WIDTH },
87480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_103_CHECKER_TYPE,
87481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_103_WIDTH },
87482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_104_CHECKER_TYPE,
87483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_104_WIDTH },
87484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_105_CHECKER_TYPE,
87485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_105_WIDTH },
87486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_106_CHECKER_TYPE,
87487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_106_WIDTH },
87488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_107_CHECKER_TYPE,
87489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_107_WIDTH },
87490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_108_CHECKER_TYPE,
87491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_108_WIDTH },
87492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_109_CHECKER_TYPE,
87493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_109_WIDTH },
87494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_110_CHECKER_TYPE,
87495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_110_WIDTH },
87496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_111_CHECKER_TYPE,
87497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_111_WIDTH },
87498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_112_CHECKER_TYPE,
87499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_112_WIDTH },
87500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_113_CHECKER_TYPE,
87501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_113_WIDTH },
87502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_114_CHECKER_TYPE,
87503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_114_WIDTH },
87504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_115_CHECKER_TYPE,
87505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_115_WIDTH },
87506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_116_CHECKER_TYPE,
87507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_116_WIDTH },
87508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_117_CHECKER_TYPE,
87509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_117_WIDTH },
87510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_118_CHECKER_TYPE,
87511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_118_WIDTH },
87512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_119_CHECKER_TYPE,
87513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_119_WIDTH },
87514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_120_CHECKER_TYPE,
87515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_120_WIDTH },
87516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_121_CHECKER_TYPE,
87517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_121_WIDTH },
87518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_122_CHECKER_TYPE,
87519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_122_WIDTH },
87520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_123_CHECKER_TYPE,
87521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_123_WIDTH },
87522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_124_CHECKER_TYPE,
87523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_124_WIDTH },
87524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_125_CHECKER_TYPE,
87525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_125_WIDTH },
87526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_126_CHECKER_TYPE,
87527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_126_WIDTH },
87528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_127_CHECKER_TYPE,
87529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_127_WIDTH },
87530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_128_CHECKER_TYPE,
87531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_128_WIDTH },
87532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_129_CHECKER_TYPE,
87533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_129_WIDTH },
87534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_130_CHECKER_TYPE,
87535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_130_WIDTH },
87536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_131_CHECKER_TYPE,
87537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_131_WIDTH },
87538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_132_CHECKER_TYPE,
87539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_132_WIDTH },
87540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_133_CHECKER_TYPE,
87541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_133_WIDTH },
87542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_134_CHECKER_TYPE,
87543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_134_WIDTH },
87544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_135_CHECKER_TYPE,
87545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_135_WIDTH },
87546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_136_CHECKER_TYPE,
87547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_136_WIDTH },
87548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_137_CHECKER_TYPE,
87549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_137_WIDTH },
87550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_138_CHECKER_TYPE,
87551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_138_WIDTH },
87552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_139_CHECKER_TYPE,
87553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_139_WIDTH },
87554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_140_CHECKER_TYPE,
87555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_140_WIDTH },
87556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_141_CHECKER_TYPE,
87557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_141_WIDTH },
87558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_142_CHECKER_TYPE,
87559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_142_WIDTH },
87560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_143_CHECKER_TYPE,
87561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_143_WIDTH },
87562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_144_CHECKER_TYPE,
87563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_144_WIDTH },
87564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_145_CHECKER_TYPE,
87565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_145_WIDTH },
87566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_146_CHECKER_TYPE,
87567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_146_WIDTH },
87568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_147_CHECKER_TYPE,
87569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_147_WIDTH },
87570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_148_CHECKER_TYPE,
87571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_148_WIDTH },
87572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_149_CHECKER_TYPE,
87573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_149_WIDTH },
87574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_150_CHECKER_TYPE,
87575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_150_WIDTH },
87576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_151_CHECKER_TYPE,
87577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_151_WIDTH },
87578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_152_CHECKER_TYPE,
87579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_152_WIDTH },
87580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_153_CHECKER_TYPE,
87581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_153_WIDTH },
87582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_154_CHECKER_TYPE,
87583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_154_WIDTH },
87584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_155_CHECKER_TYPE,
87585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_155_WIDTH },
87586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_156_CHECKER_TYPE,
87587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_156_WIDTH },
87588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_157_CHECKER_TYPE,
87589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_157_WIDTH },
87590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_158_CHECKER_TYPE,
87591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_158_WIDTH },
87592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_159_CHECKER_TYPE,
87593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_159_WIDTH },
87594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_160_CHECKER_TYPE,
87595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_160_WIDTH },
87596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_161_CHECKER_TYPE,
87597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_161_WIDTH },
87598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_162_CHECKER_TYPE,
87599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_162_WIDTH },
87600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_163_CHECKER_TYPE,
87601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_163_WIDTH },
87602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_164_CHECKER_TYPE,
87603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_164_WIDTH },
87604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_165_CHECKER_TYPE,
87605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_165_WIDTH },
87606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_166_CHECKER_TYPE,
87607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_166_WIDTH },
87608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_167_CHECKER_TYPE,
87609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_167_WIDTH },
87610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_168_CHECKER_TYPE,
87611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_168_WIDTH },
87612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_169_CHECKER_TYPE,
87613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_169_WIDTH },
87614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_170_CHECKER_TYPE,
87615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_170_WIDTH },
87616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_171_CHECKER_TYPE,
87617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_171_WIDTH },
87618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_172_CHECKER_TYPE,
87619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_172_WIDTH },
87620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_173_CHECKER_TYPE,
87621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_173_WIDTH },
87622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_174_CHECKER_TYPE,
87623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_174_WIDTH },
87624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_175_CHECKER_TYPE,
87625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_175_WIDTH },
87626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_176_CHECKER_TYPE,
87627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_176_WIDTH },
87628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_177_CHECKER_TYPE,
87629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_177_WIDTH },
87630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_178_CHECKER_TYPE,
87631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_178_WIDTH },
87632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_179_CHECKER_TYPE,
87633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_179_WIDTH },
87634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_180_CHECKER_TYPE,
87635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_180_WIDTH },
87636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_181_CHECKER_TYPE,
87637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_181_WIDTH },
87638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_182_CHECKER_TYPE,
87639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_182_WIDTH },
87640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_183_CHECKER_TYPE,
87641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_183_WIDTH },
87642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_184_CHECKER_TYPE,
87643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_184_WIDTH },
87644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_185_CHECKER_TYPE,
87645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_185_WIDTH },
87646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_186_CHECKER_TYPE,
87647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_186_WIDTH },
87648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_187_CHECKER_TYPE,
87649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_187_WIDTH },
87650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_188_CHECKER_TYPE,
87651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_188_WIDTH },
87652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_189_CHECKER_TYPE,
87653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_189_WIDTH },
87654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_190_CHECKER_TYPE,
87655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_190_WIDTH },
87656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_191_CHECKER_TYPE,
87657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_191_WIDTH },
87658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_192_CHECKER_TYPE,
87659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_192_WIDTH },
87660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_193_CHECKER_TYPE,
87661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_193_WIDTH },
87662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_194_CHECKER_TYPE,
87663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_194_WIDTH },
87664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_195_CHECKER_TYPE,
87665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_195_WIDTH },
87666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_196_CHECKER_TYPE,
87667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_196_WIDTH },
87668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_197_CHECKER_TYPE,
87669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_197_WIDTH },
87670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_198_CHECKER_TYPE,
87671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_198_WIDTH },
87672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_199_CHECKER_TYPE,
87673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_199_WIDTH },
87674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_200_CHECKER_TYPE,
87675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_200_WIDTH },
87676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_201_CHECKER_TYPE,
87677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_201_WIDTH },
87678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_202_CHECKER_TYPE,
87679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_202_WIDTH },
87680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_203_CHECKER_TYPE,
87681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_203_WIDTH },
87682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_204_CHECKER_TYPE,
87683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_204_WIDTH },
87684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_205_CHECKER_TYPE,
87685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_205_WIDTH },
87686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_206_CHECKER_TYPE,
87687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_206_WIDTH },
87688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_207_CHECKER_TYPE,
87689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_207_WIDTH },
87690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_208_CHECKER_TYPE,
87691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_208_WIDTH },
87692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_209_CHECKER_TYPE,
87693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_209_WIDTH },
87694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_210_CHECKER_TYPE,
87695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_210_WIDTH },
87696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_211_CHECKER_TYPE,
87697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_211_WIDTH },
87698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_212_CHECKER_TYPE,
87699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_212_WIDTH },
87700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_213_CHECKER_TYPE,
87701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_213_WIDTH },
87702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_214_CHECKER_TYPE,
87703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_214_WIDTH },
87704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_215_CHECKER_TYPE,
87705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_215_WIDTH },
87706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_216_CHECKER_TYPE,
87707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_216_WIDTH },
87708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_217_CHECKER_TYPE,
87709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_217_WIDTH },
87710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_218_CHECKER_TYPE,
87711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_218_WIDTH },
87712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_219_CHECKER_TYPE,
87713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_219_WIDTH },
87714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_220_CHECKER_TYPE,
87715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_220_WIDTH },
87716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_221_CHECKER_TYPE,
87717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_221_WIDTH },
87718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_222_CHECKER_TYPE,
87719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_222_WIDTH },
87720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_223_CHECKER_TYPE,
87721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_223_WIDTH },
87722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_224_CHECKER_TYPE,
87723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_224_WIDTH },
87724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_225_CHECKER_TYPE,
87725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_225_WIDTH },
87726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_226_CHECKER_TYPE,
87727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_226_WIDTH },
87728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_227_CHECKER_TYPE,
87729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_227_WIDTH },
87730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_228_CHECKER_TYPE,
87731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_228_WIDTH },
87732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_229_CHECKER_TYPE,
87733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_229_WIDTH },
87734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_230_CHECKER_TYPE,
87735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_230_WIDTH },
87736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_231_CHECKER_TYPE,
87737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_231_WIDTH },
87738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_232_CHECKER_TYPE,
87739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_232_WIDTH },
87740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_233_CHECKER_TYPE,
87741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_233_WIDTH },
87742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_234_CHECKER_TYPE,
87743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_234_WIDTH },
87744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_235_CHECKER_TYPE,
87745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_235_WIDTH },
87746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_236_CHECKER_TYPE,
87747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_236_WIDTH },
87748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_237_CHECKER_TYPE,
87749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_237_WIDTH },
87750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_238_CHECKER_TYPE,
87751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_238_WIDTH },
87752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_239_CHECKER_TYPE,
87753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_239_WIDTH },
87754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_240_CHECKER_TYPE,
87755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_240_WIDTH },
87756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_241_CHECKER_TYPE,
87757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_241_WIDTH },
87758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_242_CHECKER_TYPE,
87759  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_242_WIDTH },
87760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_243_CHECKER_TYPE,
87761  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_243_WIDTH },
87762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_244_CHECKER_TYPE,
87763  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_244_WIDTH },
87764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_245_CHECKER_TYPE,
87765  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_245_WIDTH },
87766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_246_CHECKER_TYPE,
87767  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_246_WIDTH },
87768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_247_CHECKER_TYPE,
87769  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_247_WIDTH },
87770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_248_CHECKER_TYPE,
87771  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_248_WIDTH },
87772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_249_CHECKER_TYPE,
87773  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_249_WIDTH },
87774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_250_CHECKER_TYPE,
87775  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_250_WIDTH },
87776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_251_CHECKER_TYPE,
87777  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_251_WIDTH },
87778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_252_CHECKER_TYPE,
87779  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_252_WIDTH },
87780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_253_CHECKER_TYPE,
87781  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_253_WIDTH },
87782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_254_CHECKER_TYPE,
87783  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_254_WIDTH },
87784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_255_CHECKER_TYPE,
87785  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_GROUP_255_WIDTH },
87786 };
87787 
87793 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS] =
87794 {
87795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_0_CHECKER_TYPE,
87796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_0_WIDTH },
87797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_1_CHECKER_TYPE,
87798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_1_WIDTH },
87799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_2_CHECKER_TYPE,
87800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_2_WIDTH },
87801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_3_CHECKER_TYPE,
87802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_3_WIDTH },
87803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_4_CHECKER_TYPE,
87804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_4_WIDTH },
87805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_5_CHECKER_TYPE,
87806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_5_WIDTH },
87807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_6_CHECKER_TYPE,
87808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_6_WIDTH },
87809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_7_CHECKER_TYPE,
87810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_7_WIDTH },
87811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_8_CHECKER_TYPE,
87812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_8_WIDTH },
87813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_9_CHECKER_TYPE,
87814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_9_WIDTH },
87815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_10_CHECKER_TYPE,
87816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_10_WIDTH },
87817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_11_CHECKER_TYPE,
87818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_11_WIDTH },
87819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_12_CHECKER_TYPE,
87820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_12_WIDTH },
87821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_13_CHECKER_TYPE,
87822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_13_WIDTH },
87823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_14_CHECKER_TYPE,
87824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_14_WIDTH },
87825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_15_CHECKER_TYPE,
87826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_15_WIDTH },
87827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_16_CHECKER_TYPE,
87828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_16_WIDTH },
87829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_17_CHECKER_TYPE,
87830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_17_WIDTH },
87831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_18_CHECKER_TYPE,
87832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_18_WIDTH },
87833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_19_CHECKER_TYPE,
87834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_19_WIDTH },
87835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_20_CHECKER_TYPE,
87836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_20_WIDTH },
87837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_21_CHECKER_TYPE,
87838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_21_WIDTH },
87839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_22_CHECKER_TYPE,
87840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_22_WIDTH },
87841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_23_CHECKER_TYPE,
87842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_23_WIDTH },
87843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_24_CHECKER_TYPE,
87844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_24_WIDTH },
87845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_25_CHECKER_TYPE,
87846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_25_WIDTH },
87847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_26_CHECKER_TYPE,
87848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_26_WIDTH },
87849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_27_CHECKER_TYPE,
87850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_27_WIDTH },
87851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_28_CHECKER_TYPE,
87852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_28_WIDTH },
87853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_29_CHECKER_TYPE,
87854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_29_WIDTH },
87855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_30_CHECKER_TYPE,
87856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_30_WIDTH },
87857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_31_CHECKER_TYPE,
87858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_31_WIDTH },
87859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_32_CHECKER_TYPE,
87860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_32_WIDTH },
87861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_33_CHECKER_TYPE,
87862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_33_WIDTH },
87863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_34_CHECKER_TYPE,
87864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_34_WIDTH },
87865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_35_CHECKER_TYPE,
87866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_35_WIDTH },
87867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_36_CHECKER_TYPE,
87868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_36_WIDTH },
87869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_37_CHECKER_TYPE,
87870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_37_WIDTH },
87871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_38_CHECKER_TYPE,
87872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_38_WIDTH },
87873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_39_CHECKER_TYPE,
87874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_39_WIDTH },
87875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_40_CHECKER_TYPE,
87876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_40_WIDTH },
87877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_41_CHECKER_TYPE,
87878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_41_WIDTH },
87879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_42_CHECKER_TYPE,
87880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_42_WIDTH },
87881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_43_CHECKER_TYPE,
87882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_43_WIDTH },
87883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_44_CHECKER_TYPE,
87884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_44_WIDTH },
87885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_45_CHECKER_TYPE,
87886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_45_WIDTH },
87887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_46_CHECKER_TYPE,
87888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_46_WIDTH },
87889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_47_CHECKER_TYPE,
87890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_47_WIDTH },
87891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_48_CHECKER_TYPE,
87892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_48_WIDTH },
87893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_49_CHECKER_TYPE,
87894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_49_WIDTH },
87895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_50_CHECKER_TYPE,
87896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_50_WIDTH },
87897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_51_CHECKER_TYPE,
87898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_51_WIDTH },
87899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_52_CHECKER_TYPE,
87900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_52_WIDTH },
87901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_53_CHECKER_TYPE,
87902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_53_WIDTH },
87903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_54_CHECKER_TYPE,
87904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_54_WIDTH },
87905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_55_CHECKER_TYPE,
87906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_55_WIDTH },
87907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_56_CHECKER_TYPE,
87908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_56_WIDTH },
87909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_57_CHECKER_TYPE,
87910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_57_WIDTH },
87911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_58_CHECKER_TYPE,
87912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_58_WIDTH },
87913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_59_CHECKER_TYPE,
87914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_59_WIDTH },
87915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_60_CHECKER_TYPE,
87916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_60_WIDTH },
87917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_61_CHECKER_TYPE,
87918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_61_WIDTH },
87919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_62_CHECKER_TYPE,
87920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_62_WIDTH },
87921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_63_CHECKER_TYPE,
87922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_63_WIDTH },
87923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_64_CHECKER_TYPE,
87924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_64_WIDTH },
87925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_65_CHECKER_TYPE,
87926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_65_WIDTH },
87927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_66_CHECKER_TYPE,
87928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_66_WIDTH },
87929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_67_CHECKER_TYPE,
87930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_67_WIDTH },
87931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_68_CHECKER_TYPE,
87932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_68_WIDTH },
87933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_69_CHECKER_TYPE,
87934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_69_WIDTH },
87935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_70_CHECKER_TYPE,
87936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_70_WIDTH },
87937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_71_CHECKER_TYPE,
87938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_71_WIDTH },
87939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_72_CHECKER_TYPE,
87940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_72_WIDTH },
87941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_73_CHECKER_TYPE,
87942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_73_WIDTH },
87943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_74_CHECKER_TYPE,
87944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_74_WIDTH },
87945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_75_CHECKER_TYPE,
87946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_75_WIDTH },
87947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_76_CHECKER_TYPE,
87948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_76_WIDTH },
87949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_77_CHECKER_TYPE,
87950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_77_WIDTH },
87951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_78_CHECKER_TYPE,
87952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_78_WIDTH },
87953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_79_CHECKER_TYPE,
87954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_79_WIDTH },
87955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_80_CHECKER_TYPE,
87956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_80_WIDTH },
87957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_81_CHECKER_TYPE,
87958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_81_WIDTH },
87959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_82_CHECKER_TYPE,
87960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_82_WIDTH },
87961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_83_CHECKER_TYPE,
87962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_83_WIDTH },
87963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_84_CHECKER_TYPE,
87964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_84_WIDTH },
87965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_85_CHECKER_TYPE,
87966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_85_WIDTH },
87967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_86_CHECKER_TYPE,
87968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_86_WIDTH },
87969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_87_CHECKER_TYPE,
87970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_87_WIDTH },
87971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_88_CHECKER_TYPE,
87972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_88_WIDTH },
87973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_89_CHECKER_TYPE,
87974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_89_WIDTH },
87975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_90_CHECKER_TYPE,
87976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_90_WIDTH },
87977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_91_CHECKER_TYPE,
87978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_91_WIDTH },
87979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_92_CHECKER_TYPE,
87980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_92_WIDTH },
87981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_93_CHECKER_TYPE,
87982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_93_WIDTH },
87983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_94_CHECKER_TYPE,
87984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_94_WIDTH },
87985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_95_CHECKER_TYPE,
87986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_95_WIDTH },
87987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_96_CHECKER_TYPE,
87988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_96_WIDTH },
87989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_97_CHECKER_TYPE,
87990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_97_WIDTH },
87991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_98_CHECKER_TYPE,
87992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_98_WIDTH },
87993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_99_CHECKER_TYPE,
87994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_99_WIDTH },
87995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_100_CHECKER_TYPE,
87996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_100_WIDTH },
87997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_101_CHECKER_TYPE,
87998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_101_WIDTH },
87999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_102_CHECKER_TYPE,
88000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_102_WIDTH },
88001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_103_CHECKER_TYPE,
88002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_103_WIDTH },
88003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_104_CHECKER_TYPE,
88004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_104_WIDTH },
88005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_105_CHECKER_TYPE,
88006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_105_WIDTH },
88007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_106_CHECKER_TYPE,
88008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_106_WIDTH },
88009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_107_CHECKER_TYPE,
88010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_107_WIDTH },
88011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_108_CHECKER_TYPE,
88012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_108_WIDTH },
88013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_109_CHECKER_TYPE,
88014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_109_WIDTH },
88015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_110_CHECKER_TYPE,
88016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_110_WIDTH },
88017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_111_CHECKER_TYPE,
88018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_111_WIDTH },
88019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_112_CHECKER_TYPE,
88020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_112_WIDTH },
88021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_113_CHECKER_TYPE,
88022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_113_WIDTH },
88023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_114_CHECKER_TYPE,
88024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_114_WIDTH },
88025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_115_CHECKER_TYPE,
88026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_115_WIDTH },
88027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_116_CHECKER_TYPE,
88028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_116_WIDTH },
88029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_117_CHECKER_TYPE,
88030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_117_WIDTH },
88031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_118_CHECKER_TYPE,
88032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_118_WIDTH },
88033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_119_CHECKER_TYPE,
88034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_119_WIDTH },
88035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_120_CHECKER_TYPE,
88036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_120_WIDTH },
88037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_121_CHECKER_TYPE,
88038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_121_WIDTH },
88039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_122_CHECKER_TYPE,
88040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_122_WIDTH },
88041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_123_CHECKER_TYPE,
88042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_123_WIDTH },
88043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_124_CHECKER_TYPE,
88044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_124_WIDTH },
88045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_125_CHECKER_TYPE,
88046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_125_WIDTH },
88047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_126_CHECKER_TYPE,
88048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_126_WIDTH },
88049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_127_CHECKER_TYPE,
88050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_127_WIDTH },
88051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_128_CHECKER_TYPE,
88052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_128_WIDTH },
88053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_129_CHECKER_TYPE,
88054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_129_WIDTH },
88055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_130_CHECKER_TYPE,
88056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_130_WIDTH },
88057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_131_CHECKER_TYPE,
88058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_131_WIDTH },
88059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_132_CHECKER_TYPE,
88060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_132_WIDTH },
88061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_133_CHECKER_TYPE,
88062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_133_WIDTH },
88063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_134_CHECKER_TYPE,
88064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_134_WIDTH },
88065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_135_CHECKER_TYPE,
88066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_135_WIDTH },
88067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_136_CHECKER_TYPE,
88068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_136_WIDTH },
88069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_137_CHECKER_TYPE,
88070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_137_WIDTH },
88071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_138_CHECKER_TYPE,
88072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_138_WIDTH },
88073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_139_CHECKER_TYPE,
88074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_139_WIDTH },
88075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_140_CHECKER_TYPE,
88076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_140_WIDTH },
88077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_141_CHECKER_TYPE,
88078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_141_WIDTH },
88079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_142_CHECKER_TYPE,
88080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_142_WIDTH },
88081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_143_CHECKER_TYPE,
88082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_143_WIDTH },
88083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_144_CHECKER_TYPE,
88084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_144_WIDTH },
88085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_145_CHECKER_TYPE,
88086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_145_WIDTH },
88087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_146_CHECKER_TYPE,
88088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_146_WIDTH },
88089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_147_CHECKER_TYPE,
88090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_147_WIDTH },
88091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_148_CHECKER_TYPE,
88092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_148_WIDTH },
88093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_149_CHECKER_TYPE,
88094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_149_WIDTH },
88095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_150_CHECKER_TYPE,
88096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_150_WIDTH },
88097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_151_CHECKER_TYPE,
88098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_151_WIDTH },
88099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_152_CHECKER_TYPE,
88100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_152_WIDTH },
88101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_153_CHECKER_TYPE,
88102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_153_WIDTH },
88103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_154_CHECKER_TYPE,
88104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_154_WIDTH },
88105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_155_CHECKER_TYPE,
88106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_155_WIDTH },
88107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_156_CHECKER_TYPE,
88108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_156_WIDTH },
88109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_157_CHECKER_TYPE,
88110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_157_WIDTH },
88111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_158_CHECKER_TYPE,
88112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_158_WIDTH },
88113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_159_CHECKER_TYPE,
88114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_159_WIDTH },
88115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_160_CHECKER_TYPE,
88116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_160_WIDTH },
88117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_161_CHECKER_TYPE,
88118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_161_WIDTH },
88119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_162_CHECKER_TYPE,
88120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_162_WIDTH },
88121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_163_CHECKER_TYPE,
88122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_163_WIDTH },
88123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_164_CHECKER_TYPE,
88124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_164_WIDTH },
88125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_165_CHECKER_TYPE,
88126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_165_WIDTH },
88127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_166_CHECKER_TYPE,
88128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_166_WIDTH },
88129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_167_CHECKER_TYPE,
88130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_167_WIDTH },
88131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_168_CHECKER_TYPE,
88132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_168_WIDTH },
88133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_169_CHECKER_TYPE,
88134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_169_WIDTH },
88135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_170_CHECKER_TYPE,
88136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_170_WIDTH },
88137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_171_CHECKER_TYPE,
88138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_171_WIDTH },
88139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_172_CHECKER_TYPE,
88140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_172_WIDTH },
88141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_173_CHECKER_TYPE,
88142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_173_WIDTH },
88143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_174_CHECKER_TYPE,
88144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_174_WIDTH },
88145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_175_CHECKER_TYPE,
88146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_175_WIDTH },
88147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_176_CHECKER_TYPE,
88148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_176_WIDTH },
88149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_177_CHECKER_TYPE,
88150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_177_WIDTH },
88151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_178_CHECKER_TYPE,
88152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_178_WIDTH },
88153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_179_CHECKER_TYPE,
88154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_179_WIDTH },
88155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_180_CHECKER_TYPE,
88156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_180_WIDTH },
88157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_181_CHECKER_TYPE,
88158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_181_WIDTH },
88159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_182_CHECKER_TYPE,
88160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_182_WIDTH },
88161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_183_CHECKER_TYPE,
88162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_183_WIDTH },
88163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_184_CHECKER_TYPE,
88164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_184_WIDTH },
88165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_185_CHECKER_TYPE,
88166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_185_WIDTH },
88167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_186_CHECKER_TYPE,
88168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_186_WIDTH },
88169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_187_CHECKER_TYPE,
88170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_187_WIDTH },
88171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_188_CHECKER_TYPE,
88172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_188_WIDTH },
88173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_189_CHECKER_TYPE,
88174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_189_WIDTH },
88175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_190_CHECKER_TYPE,
88176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_190_WIDTH },
88177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_191_CHECKER_TYPE,
88178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_191_WIDTH },
88179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_192_CHECKER_TYPE,
88180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_192_WIDTH },
88181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_193_CHECKER_TYPE,
88182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_193_WIDTH },
88183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_194_CHECKER_TYPE,
88184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_194_WIDTH },
88185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_195_CHECKER_TYPE,
88186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_195_WIDTH },
88187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_196_CHECKER_TYPE,
88188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_196_WIDTH },
88189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_197_CHECKER_TYPE,
88190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_197_WIDTH },
88191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_198_CHECKER_TYPE,
88192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_198_WIDTH },
88193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_199_CHECKER_TYPE,
88194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_199_WIDTH },
88195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_200_CHECKER_TYPE,
88196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_200_WIDTH },
88197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_201_CHECKER_TYPE,
88198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_201_WIDTH },
88199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_202_CHECKER_TYPE,
88200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_202_WIDTH },
88201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_203_CHECKER_TYPE,
88202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_203_WIDTH },
88203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_204_CHECKER_TYPE,
88204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_204_WIDTH },
88205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_205_CHECKER_TYPE,
88206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_205_WIDTH },
88207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_206_CHECKER_TYPE,
88208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_206_WIDTH },
88209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_207_CHECKER_TYPE,
88210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_207_WIDTH },
88211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_208_CHECKER_TYPE,
88212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_208_WIDTH },
88213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_209_CHECKER_TYPE,
88214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_209_WIDTH },
88215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_210_CHECKER_TYPE,
88216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_210_WIDTH },
88217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_211_CHECKER_TYPE,
88218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_211_WIDTH },
88219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_212_CHECKER_TYPE,
88220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_212_WIDTH },
88221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_213_CHECKER_TYPE,
88222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_213_WIDTH },
88223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_214_CHECKER_TYPE,
88224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_214_WIDTH },
88225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_215_CHECKER_TYPE,
88226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_215_WIDTH },
88227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_216_CHECKER_TYPE,
88228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_216_WIDTH },
88229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_217_CHECKER_TYPE,
88230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_217_WIDTH },
88231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_218_CHECKER_TYPE,
88232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_218_WIDTH },
88233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_219_CHECKER_TYPE,
88234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_219_WIDTH },
88235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_220_CHECKER_TYPE,
88236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_220_WIDTH },
88237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_221_CHECKER_TYPE,
88238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_221_WIDTH },
88239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_222_CHECKER_TYPE,
88240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_222_WIDTH },
88241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_223_CHECKER_TYPE,
88242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_223_WIDTH },
88243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_224_CHECKER_TYPE,
88244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_224_WIDTH },
88245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_225_CHECKER_TYPE,
88246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_225_WIDTH },
88247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_226_CHECKER_TYPE,
88248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_226_WIDTH },
88249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_227_CHECKER_TYPE,
88250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_227_WIDTH },
88251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_228_CHECKER_TYPE,
88252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_228_WIDTH },
88253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_229_CHECKER_TYPE,
88254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_229_WIDTH },
88255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_230_CHECKER_TYPE,
88256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_230_WIDTH },
88257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_231_CHECKER_TYPE,
88258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_231_WIDTH },
88259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_232_CHECKER_TYPE,
88260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_232_WIDTH },
88261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_233_CHECKER_TYPE,
88262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_233_WIDTH },
88263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_234_CHECKER_TYPE,
88264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_234_WIDTH },
88265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_235_CHECKER_TYPE,
88266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_235_WIDTH },
88267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_236_CHECKER_TYPE,
88268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_236_WIDTH },
88269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_237_CHECKER_TYPE,
88270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_237_WIDTH },
88271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_238_CHECKER_TYPE,
88272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_238_WIDTH },
88273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_239_CHECKER_TYPE,
88274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_239_WIDTH },
88275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_240_CHECKER_TYPE,
88276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_240_WIDTH },
88277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_241_CHECKER_TYPE,
88278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_241_WIDTH },
88279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_242_CHECKER_TYPE,
88280  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_242_WIDTH },
88281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_243_CHECKER_TYPE,
88282  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_243_WIDTH },
88283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_244_CHECKER_TYPE,
88284  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_244_WIDTH },
88285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_245_CHECKER_TYPE,
88286  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_245_WIDTH },
88287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_246_CHECKER_TYPE,
88288  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_246_WIDTH },
88289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_247_CHECKER_TYPE,
88290  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_247_WIDTH },
88291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_248_CHECKER_TYPE,
88292  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_248_WIDTH },
88293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_249_CHECKER_TYPE,
88294  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_249_WIDTH },
88295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_250_CHECKER_TYPE,
88296  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_250_WIDTH },
88297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_251_CHECKER_TYPE,
88298  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_251_WIDTH },
88299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_252_CHECKER_TYPE,
88300  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_252_WIDTH },
88301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_253_CHECKER_TYPE,
88302  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_253_WIDTH },
88303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_254_CHECKER_TYPE,
88304  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_254_WIDTH },
88305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_255_CHECKER_TYPE,
88306  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_GROUP_255_WIDTH },
88307 };
88308 
88314 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS] =
88315 {
88316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_0_CHECKER_TYPE,
88317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_0_WIDTH },
88318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_1_CHECKER_TYPE,
88319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_1_WIDTH },
88320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_2_CHECKER_TYPE,
88321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_2_WIDTH },
88322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_3_CHECKER_TYPE,
88323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_3_WIDTH },
88324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_4_CHECKER_TYPE,
88325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_4_WIDTH },
88326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_5_CHECKER_TYPE,
88327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_5_WIDTH },
88328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_6_CHECKER_TYPE,
88329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_6_WIDTH },
88330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_7_CHECKER_TYPE,
88331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_7_WIDTH },
88332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_8_CHECKER_TYPE,
88333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_8_WIDTH },
88334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_9_CHECKER_TYPE,
88335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_9_WIDTH },
88336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_10_CHECKER_TYPE,
88337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_10_WIDTH },
88338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_11_CHECKER_TYPE,
88339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_11_WIDTH },
88340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_12_CHECKER_TYPE,
88341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_12_WIDTH },
88342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_13_CHECKER_TYPE,
88343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_13_WIDTH },
88344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_14_CHECKER_TYPE,
88345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_14_WIDTH },
88346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_15_CHECKER_TYPE,
88347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_15_WIDTH },
88348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_16_CHECKER_TYPE,
88349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_16_WIDTH },
88350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_17_CHECKER_TYPE,
88351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_17_WIDTH },
88352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_18_CHECKER_TYPE,
88353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_18_WIDTH },
88354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_19_CHECKER_TYPE,
88355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_19_WIDTH },
88356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_20_CHECKER_TYPE,
88357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_20_WIDTH },
88358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_21_CHECKER_TYPE,
88359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_21_WIDTH },
88360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_22_CHECKER_TYPE,
88361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_22_WIDTH },
88362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_23_CHECKER_TYPE,
88363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_23_WIDTH },
88364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_24_CHECKER_TYPE,
88365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_24_WIDTH },
88366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_25_CHECKER_TYPE,
88367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_25_WIDTH },
88368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_26_CHECKER_TYPE,
88369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_26_WIDTH },
88370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_27_CHECKER_TYPE,
88371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_27_WIDTH },
88372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_28_CHECKER_TYPE,
88373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_28_WIDTH },
88374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_29_CHECKER_TYPE,
88375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_29_WIDTH },
88376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_30_CHECKER_TYPE,
88377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_30_WIDTH },
88378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_31_CHECKER_TYPE,
88379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_31_WIDTH },
88380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_32_CHECKER_TYPE,
88381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_32_WIDTH },
88382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_33_CHECKER_TYPE,
88383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_33_WIDTH },
88384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_34_CHECKER_TYPE,
88385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_34_WIDTH },
88386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_35_CHECKER_TYPE,
88387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_35_WIDTH },
88388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_36_CHECKER_TYPE,
88389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_36_WIDTH },
88390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_37_CHECKER_TYPE,
88391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_37_WIDTH },
88392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_38_CHECKER_TYPE,
88393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_38_WIDTH },
88394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_39_CHECKER_TYPE,
88395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_39_WIDTH },
88396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_40_CHECKER_TYPE,
88397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_40_WIDTH },
88398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_41_CHECKER_TYPE,
88399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_41_WIDTH },
88400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_42_CHECKER_TYPE,
88401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_42_WIDTH },
88402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_43_CHECKER_TYPE,
88403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_43_WIDTH },
88404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_44_CHECKER_TYPE,
88405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_44_WIDTH },
88406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_45_CHECKER_TYPE,
88407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_45_WIDTH },
88408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_46_CHECKER_TYPE,
88409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_46_WIDTH },
88410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_47_CHECKER_TYPE,
88411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_47_WIDTH },
88412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_48_CHECKER_TYPE,
88413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_48_WIDTH },
88414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_49_CHECKER_TYPE,
88415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_49_WIDTH },
88416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_50_CHECKER_TYPE,
88417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_50_WIDTH },
88418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_51_CHECKER_TYPE,
88419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_51_WIDTH },
88420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_52_CHECKER_TYPE,
88421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_52_WIDTH },
88422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_53_CHECKER_TYPE,
88423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_53_WIDTH },
88424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_54_CHECKER_TYPE,
88425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_54_WIDTH },
88426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_55_CHECKER_TYPE,
88427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_55_WIDTH },
88428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_56_CHECKER_TYPE,
88429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_56_WIDTH },
88430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_57_CHECKER_TYPE,
88431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_57_WIDTH },
88432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_58_CHECKER_TYPE,
88433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_58_WIDTH },
88434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_59_CHECKER_TYPE,
88435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_59_WIDTH },
88436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_60_CHECKER_TYPE,
88437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_60_WIDTH },
88438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_61_CHECKER_TYPE,
88439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_61_WIDTH },
88440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_62_CHECKER_TYPE,
88441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_62_WIDTH },
88442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_63_CHECKER_TYPE,
88443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_63_WIDTH },
88444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_64_CHECKER_TYPE,
88445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_64_WIDTH },
88446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_65_CHECKER_TYPE,
88447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_65_WIDTH },
88448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_66_CHECKER_TYPE,
88449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_66_WIDTH },
88450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_67_CHECKER_TYPE,
88451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_67_WIDTH },
88452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_68_CHECKER_TYPE,
88453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_68_WIDTH },
88454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_69_CHECKER_TYPE,
88455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_69_WIDTH },
88456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_70_CHECKER_TYPE,
88457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_70_WIDTH },
88458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_71_CHECKER_TYPE,
88459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_71_WIDTH },
88460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_72_CHECKER_TYPE,
88461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_72_WIDTH },
88462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_73_CHECKER_TYPE,
88463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_73_WIDTH },
88464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_74_CHECKER_TYPE,
88465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_74_WIDTH },
88466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_75_CHECKER_TYPE,
88467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_75_WIDTH },
88468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_76_CHECKER_TYPE,
88469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_76_WIDTH },
88470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_77_CHECKER_TYPE,
88471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_77_WIDTH },
88472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_78_CHECKER_TYPE,
88473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_78_WIDTH },
88474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_79_CHECKER_TYPE,
88475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_79_WIDTH },
88476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_80_CHECKER_TYPE,
88477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_80_WIDTH },
88478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_81_CHECKER_TYPE,
88479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_81_WIDTH },
88480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_82_CHECKER_TYPE,
88481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_82_WIDTH },
88482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_83_CHECKER_TYPE,
88483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_83_WIDTH },
88484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_84_CHECKER_TYPE,
88485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_84_WIDTH },
88486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_85_CHECKER_TYPE,
88487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_85_WIDTH },
88488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_86_CHECKER_TYPE,
88489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_86_WIDTH },
88490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_87_CHECKER_TYPE,
88491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_87_WIDTH },
88492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_88_CHECKER_TYPE,
88493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_88_WIDTH },
88494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_89_CHECKER_TYPE,
88495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_89_WIDTH },
88496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_90_CHECKER_TYPE,
88497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_90_WIDTH },
88498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_91_CHECKER_TYPE,
88499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_91_WIDTH },
88500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_92_CHECKER_TYPE,
88501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_92_WIDTH },
88502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_93_CHECKER_TYPE,
88503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_93_WIDTH },
88504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_94_CHECKER_TYPE,
88505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_94_WIDTH },
88506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_95_CHECKER_TYPE,
88507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_95_WIDTH },
88508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_96_CHECKER_TYPE,
88509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_96_WIDTH },
88510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_97_CHECKER_TYPE,
88511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_97_WIDTH },
88512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_98_CHECKER_TYPE,
88513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_98_WIDTH },
88514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_99_CHECKER_TYPE,
88515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_99_WIDTH },
88516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_100_CHECKER_TYPE,
88517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_100_WIDTH },
88518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_101_CHECKER_TYPE,
88519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_101_WIDTH },
88520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_102_CHECKER_TYPE,
88521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_102_WIDTH },
88522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_103_CHECKER_TYPE,
88523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_103_WIDTH },
88524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_104_CHECKER_TYPE,
88525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_104_WIDTH },
88526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_105_CHECKER_TYPE,
88527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_105_WIDTH },
88528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_106_CHECKER_TYPE,
88529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_106_WIDTH },
88530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_107_CHECKER_TYPE,
88531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_107_WIDTH },
88532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_108_CHECKER_TYPE,
88533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_108_WIDTH },
88534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_109_CHECKER_TYPE,
88535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_109_WIDTH },
88536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_110_CHECKER_TYPE,
88537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_110_WIDTH },
88538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_111_CHECKER_TYPE,
88539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_111_WIDTH },
88540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_112_CHECKER_TYPE,
88541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_112_WIDTH },
88542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_113_CHECKER_TYPE,
88543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_113_WIDTH },
88544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_114_CHECKER_TYPE,
88545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_114_WIDTH },
88546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_115_CHECKER_TYPE,
88547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_115_WIDTH },
88548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_116_CHECKER_TYPE,
88549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_116_WIDTH },
88550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_117_CHECKER_TYPE,
88551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_117_WIDTH },
88552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_118_CHECKER_TYPE,
88553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_118_WIDTH },
88554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_119_CHECKER_TYPE,
88555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_119_WIDTH },
88556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_120_CHECKER_TYPE,
88557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_120_WIDTH },
88558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_121_CHECKER_TYPE,
88559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_121_WIDTH },
88560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_122_CHECKER_TYPE,
88561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_122_WIDTH },
88562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_123_CHECKER_TYPE,
88563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_123_WIDTH },
88564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_124_CHECKER_TYPE,
88565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_124_WIDTH },
88566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_125_CHECKER_TYPE,
88567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_125_WIDTH },
88568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_126_CHECKER_TYPE,
88569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_126_WIDTH },
88570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_127_CHECKER_TYPE,
88571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_127_WIDTH },
88572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_128_CHECKER_TYPE,
88573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_128_WIDTH },
88574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_129_CHECKER_TYPE,
88575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_129_WIDTH },
88576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_130_CHECKER_TYPE,
88577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_130_WIDTH },
88578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_131_CHECKER_TYPE,
88579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_131_WIDTH },
88580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_132_CHECKER_TYPE,
88581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_132_WIDTH },
88582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_133_CHECKER_TYPE,
88583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_133_WIDTH },
88584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_134_CHECKER_TYPE,
88585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_134_WIDTH },
88586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_135_CHECKER_TYPE,
88587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_135_WIDTH },
88588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_136_CHECKER_TYPE,
88589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_136_WIDTH },
88590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_137_CHECKER_TYPE,
88591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_137_WIDTH },
88592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_138_CHECKER_TYPE,
88593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_138_WIDTH },
88594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_139_CHECKER_TYPE,
88595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_139_WIDTH },
88596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_140_CHECKER_TYPE,
88597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_140_WIDTH },
88598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_141_CHECKER_TYPE,
88599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_141_WIDTH },
88600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_142_CHECKER_TYPE,
88601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_142_WIDTH },
88602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_143_CHECKER_TYPE,
88603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_143_WIDTH },
88604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_144_CHECKER_TYPE,
88605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_144_WIDTH },
88606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_145_CHECKER_TYPE,
88607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_145_WIDTH },
88608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_146_CHECKER_TYPE,
88609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_146_WIDTH },
88610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_147_CHECKER_TYPE,
88611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_147_WIDTH },
88612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_148_CHECKER_TYPE,
88613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_148_WIDTH },
88614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_149_CHECKER_TYPE,
88615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_149_WIDTH },
88616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_150_CHECKER_TYPE,
88617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_150_WIDTH },
88618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_151_CHECKER_TYPE,
88619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_151_WIDTH },
88620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_152_CHECKER_TYPE,
88621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_152_WIDTH },
88622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_153_CHECKER_TYPE,
88623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_153_WIDTH },
88624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_154_CHECKER_TYPE,
88625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_154_WIDTH },
88626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_155_CHECKER_TYPE,
88627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_155_WIDTH },
88628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_156_CHECKER_TYPE,
88629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_156_WIDTH },
88630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_157_CHECKER_TYPE,
88631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_157_WIDTH },
88632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_158_CHECKER_TYPE,
88633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_158_WIDTH },
88634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_159_CHECKER_TYPE,
88635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_159_WIDTH },
88636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_160_CHECKER_TYPE,
88637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_160_WIDTH },
88638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_161_CHECKER_TYPE,
88639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_161_WIDTH },
88640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_162_CHECKER_TYPE,
88641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_162_WIDTH },
88642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_163_CHECKER_TYPE,
88643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_163_WIDTH },
88644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_164_CHECKER_TYPE,
88645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_164_WIDTH },
88646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_165_CHECKER_TYPE,
88647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_165_WIDTH },
88648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_166_CHECKER_TYPE,
88649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_166_WIDTH },
88650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_167_CHECKER_TYPE,
88651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_167_WIDTH },
88652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_168_CHECKER_TYPE,
88653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_168_WIDTH },
88654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_169_CHECKER_TYPE,
88655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_169_WIDTH },
88656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_170_CHECKER_TYPE,
88657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_170_WIDTH },
88658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_171_CHECKER_TYPE,
88659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_171_WIDTH },
88660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_172_CHECKER_TYPE,
88661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_172_WIDTH },
88662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_173_CHECKER_TYPE,
88663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_173_WIDTH },
88664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_174_CHECKER_TYPE,
88665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_174_WIDTH },
88666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_175_CHECKER_TYPE,
88667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_175_WIDTH },
88668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_176_CHECKER_TYPE,
88669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_176_WIDTH },
88670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_177_CHECKER_TYPE,
88671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_177_WIDTH },
88672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_178_CHECKER_TYPE,
88673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_178_WIDTH },
88674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_179_CHECKER_TYPE,
88675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_179_WIDTH },
88676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_180_CHECKER_TYPE,
88677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_180_WIDTH },
88678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_181_CHECKER_TYPE,
88679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_181_WIDTH },
88680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_182_CHECKER_TYPE,
88681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_182_WIDTH },
88682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_183_CHECKER_TYPE,
88683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_183_WIDTH },
88684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_184_CHECKER_TYPE,
88685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_184_WIDTH },
88686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_185_CHECKER_TYPE,
88687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_185_WIDTH },
88688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_186_CHECKER_TYPE,
88689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_186_WIDTH },
88690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_187_CHECKER_TYPE,
88691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_187_WIDTH },
88692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_188_CHECKER_TYPE,
88693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_188_WIDTH },
88694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_189_CHECKER_TYPE,
88695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_189_WIDTH },
88696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_190_CHECKER_TYPE,
88697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_190_WIDTH },
88698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_191_CHECKER_TYPE,
88699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_191_WIDTH },
88700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_192_CHECKER_TYPE,
88701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_192_WIDTH },
88702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_193_CHECKER_TYPE,
88703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_193_WIDTH },
88704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_194_CHECKER_TYPE,
88705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_194_WIDTH },
88706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_195_CHECKER_TYPE,
88707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_195_WIDTH },
88708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_196_CHECKER_TYPE,
88709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_196_WIDTH },
88710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_197_CHECKER_TYPE,
88711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_197_WIDTH },
88712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_198_CHECKER_TYPE,
88713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_198_WIDTH },
88714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_199_CHECKER_TYPE,
88715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_199_WIDTH },
88716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_200_CHECKER_TYPE,
88717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_200_WIDTH },
88718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_201_CHECKER_TYPE,
88719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_201_WIDTH },
88720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_202_CHECKER_TYPE,
88721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_202_WIDTH },
88722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_203_CHECKER_TYPE,
88723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_203_WIDTH },
88724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_204_CHECKER_TYPE,
88725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_204_WIDTH },
88726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_205_CHECKER_TYPE,
88727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_205_WIDTH },
88728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_206_CHECKER_TYPE,
88729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_206_WIDTH },
88730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_207_CHECKER_TYPE,
88731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_207_WIDTH },
88732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_208_CHECKER_TYPE,
88733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_208_WIDTH },
88734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_209_CHECKER_TYPE,
88735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_209_WIDTH },
88736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_210_CHECKER_TYPE,
88737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_210_WIDTH },
88738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_211_CHECKER_TYPE,
88739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_211_WIDTH },
88740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_212_CHECKER_TYPE,
88741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_212_WIDTH },
88742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_213_CHECKER_TYPE,
88743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_213_WIDTH },
88744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_214_CHECKER_TYPE,
88745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_214_WIDTH },
88746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_215_CHECKER_TYPE,
88747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_215_WIDTH },
88748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_216_CHECKER_TYPE,
88749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_216_WIDTH },
88750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_217_CHECKER_TYPE,
88751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_217_WIDTH },
88752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_218_CHECKER_TYPE,
88753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_218_WIDTH },
88754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_219_CHECKER_TYPE,
88755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_219_WIDTH },
88756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_220_CHECKER_TYPE,
88757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_220_WIDTH },
88758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_221_CHECKER_TYPE,
88759  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_221_WIDTH },
88760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_222_CHECKER_TYPE,
88761  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_222_WIDTH },
88762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_223_CHECKER_TYPE,
88763  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_223_WIDTH },
88764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_224_CHECKER_TYPE,
88765  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_224_WIDTH },
88766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_225_CHECKER_TYPE,
88767  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_225_WIDTH },
88768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_226_CHECKER_TYPE,
88769  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_226_WIDTH },
88770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_227_CHECKER_TYPE,
88771  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_227_WIDTH },
88772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_228_CHECKER_TYPE,
88773  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_228_WIDTH },
88774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_229_CHECKER_TYPE,
88775  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_229_WIDTH },
88776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_230_CHECKER_TYPE,
88777  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_230_WIDTH },
88778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_231_CHECKER_TYPE,
88779  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_231_WIDTH },
88780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_232_CHECKER_TYPE,
88781  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_232_WIDTH },
88782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_233_CHECKER_TYPE,
88783  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_233_WIDTH },
88784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_234_CHECKER_TYPE,
88785  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_234_WIDTH },
88786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_235_CHECKER_TYPE,
88787  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_235_WIDTH },
88788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_236_CHECKER_TYPE,
88789  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_236_WIDTH },
88790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_237_CHECKER_TYPE,
88791  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_237_WIDTH },
88792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_238_CHECKER_TYPE,
88793  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_238_WIDTH },
88794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_239_CHECKER_TYPE,
88795  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_239_WIDTH },
88796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_240_CHECKER_TYPE,
88797  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_240_WIDTH },
88798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_241_CHECKER_TYPE,
88799  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_241_WIDTH },
88800  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_242_CHECKER_TYPE,
88801  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_242_WIDTH },
88802  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_243_CHECKER_TYPE,
88803  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_243_WIDTH },
88804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_244_CHECKER_TYPE,
88805  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_244_WIDTH },
88806  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_245_CHECKER_TYPE,
88807  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_245_WIDTH },
88808  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_246_CHECKER_TYPE,
88809  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_246_WIDTH },
88810  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_247_CHECKER_TYPE,
88811  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_247_WIDTH },
88812  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_248_CHECKER_TYPE,
88813  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_248_WIDTH },
88814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_249_CHECKER_TYPE,
88815  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_249_WIDTH },
88816  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_250_CHECKER_TYPE,
88817  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_250_WIDTH },
88818  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_251_CHECKER_TYPE,
88819  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_251_WIDTH },
88820  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_252_CHECKER_TYPE,
88821  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_252_WIDTH },
88822  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_253_CHECKER_TYPE,
88823  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_253_WIDTH },
88824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_254_CHECKER_TYPE,
88825  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_254_WIDTH },
88826  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_255_CHECKER_TYPE,
88827  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_GROUP_255_WIDTH },
88828 };
88829 
88835 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS] =
88836 {
88837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_0_CHECKER_TYPE,
88838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_0_WIDTH },
88839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_1_CHECKER_TYPE,
88840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_1_WIDTH },
88841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_2_CHECKER_TYPE,
88842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_2_WIDTH },
88843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_3_CHECKER_TYPE,
88844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_3_WIDTH },
88845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_4_CHECKER_TYPE,
88846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_4_WIDTH },
88847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_5_CHECKER_TYPE,
88848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_5_WIDTH },
88849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_6_CHECKER_TYPE,
88850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_6_WIDTH },
88851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_7_CHECKER_TYPE,
88852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_7_WIDTH },
88853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_8_CHECKER_TYPE,
88854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_8_WIDTH },
88855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_9_CHECKER_TYPE,
88856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_9_WIDTH },
88857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_10_CHECKER_TYPE,
88858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_10_WIDTH },
88859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_11_CHECKER_TYPE,
88860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_11_WIDTH },
88861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_12_CHECKER_TYPE,
88862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_12_WIDTH },
88863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_13_CHECKER_TYPE,
88864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_13_WIDTH },
88865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_14_CHECKER_TYPE,
88866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_14_WIDTH },
88867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_15_CHECKER_TYPE,
88868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_15_WIDTH },
88869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_16_CHECKER_TYPE,
88870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_16_WIDTH },
88871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_17_CHECKER_TYPE,
88872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_17_WIDTH },
88873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_18_CHECKER_TYPE,
88874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_18_WIDTH },
88875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_19_CHECKER_TYPE,
88876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_19_WIDTH },
88877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_20_CHECKER_TYPE,
88878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_20_WIDTH },
88879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_21_CHECKER_TYPE,
88880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_21_WIDTH },
88881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_22_CHECKER_TYPE,
88882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_22_WIDTH },
88883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_23_CHECKER_TYPE,
88884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_23_WIDTH },
88885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_24_CHECKER_TYPE,
88886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_24_WIDTH },
88887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_25_CHECKER_TYPE,
88888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_25_WIDTH },
88889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_26_CHECKER_TYPE,
88890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_26_WIDTH },
88891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_27_CHECKER_TYPE,
88892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_27_WIDTH },
88893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_28_CHECKER_TYPE,
88894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_28_WIDTH },
88895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_29_CHECKER_TYPE,
88896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_29_WIDTH },
88897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_30_CHECKER_TYPE,
88898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_30_WIDTH },
88899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_31_CHECKER_TYPE,
88900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_31_WIDTH },
88901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_32_CHECKER_TYPE,
88902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_32_WIDTH },
88903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_33_CHECKER_TYPE,
88904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_33_WIDTH },
88905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_34_CHECKER_TYPE,
88906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_34_WIDTH },
88907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_35_CHECKER_TYPE,
88908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_35_WIDTH },
88909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_36_CHECKER_TYPE,
88910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_36_WIDTH },
88911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_37_CHECKER_TYPE,
88912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_37_WIDTH },
88913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_38_CHECKER_TYPE,
88914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_38_WIDTH },
88915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_39_CHECKER_TYPE,
88916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_39_WIDTH },
88917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_40_CHECKER_TYPE,
88918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_40_WIDTH },
88919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_41_CHECKER_TYPE,
88920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_41_WIDTH },
88921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_42_CHECKER_TYPE,
88922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_42_WIDTH },
88923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_43_CHECKER_TYPE,
88924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_43_WIDTH },
88925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_44_CHECKER_TYPE,
88926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_44_WIDTH },
88927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_45_CHECKER_TYPE,
88928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_45_WIDTH },
88929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_46_CHECKER_TYPE,
88930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_46_WIDTH },
88931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_47_CHECKER_TYPE,
88932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_47_WIDTH },
88933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_48_CHECKER_TYPE,
88934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_48_WIDTH },
88935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_49_CHECKER_TYPE,
88936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_49_WIDTH },
88937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_50_CHECKER_TYPE,
88938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_50_WIDTH },
88939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_51_CHECKER_TYPE,
88940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_51_WIDTH },
88941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_52_CHECKER_TYPE,
88942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_52_WIDTH },
88943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_53_CHECKER_TYPE,
88944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_53_WIDTH },
88945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_54_CHECKER_TYPE,
88946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_54_WIDTH },
88947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_55_CHECKER_TYPE,
88948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_55_WIDTH },
88949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_56_CHECKER_TYPE,
88950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_56_WIDTH },
88951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_57_CHECKER_TYPE,
88952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_57_WIDTH },
88953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_58_CHECKER_TYPE,
88954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_58_WIDTH },
88955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_59_CHECKER_TYPE,
88956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_59_WIDTH },
88957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_60_CHECKER_TYPE,
88958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_60_WIDTH },
88959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_61_CHECKER_TYPE,
88960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_61_WIDTH },
88961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_62_CHECKER_TYPE,
88962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_62_WIDTH },
88963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_63_CHECKER_TYPE,
88964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_63_WIDTH },
88965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_64_CHECKER_TYPE,
88966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_64_WIDTH },
88967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_65_CHECKER_TYPE,
88968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_65_WIDTH },
88969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_66_CHECKER_TYPE,
88970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_66_WIDTH },
88971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_67_CHECKER_TYPE,
88972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_67_WIDTH },
88973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_68_CHECKER_TYPE,
88974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_68_WIDTH },
88975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_69_CHECKER_TYPE,
88976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_69_WIDTH },
88977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_70_CHECKER_TYPE,
88978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_70_WIDTH },
88979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_71_CHECKER_TYPE,
88980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_71_WIDTH },
88981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_72_CHECKER_TYPE,
88982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_72_WIDTH },
88983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_73_CHECKER_TYPE,
88984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_73_WIDTH },
88985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_74_CHECKER_TYPE,
88986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_74_WIDTH },
88987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_75_CHECKER_TYPE,
88988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_75_WIDTH },
88989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_76_CHECKER_TYPE,
88990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_76_WIDTH },
88991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_77_CHECKER_TYPE,
88992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_77_WIDTH },
88993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_78_CHECKER_TYPE,
88994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_78_WIDTH },
88995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_79_CHECKER_TYPE,
88996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_79_WIDTH },
88997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_80_CHECKER_TYPE,
88998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_80_WIDTH },
88999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_81_CHECKER_TYPE,
89000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_81_WIDTH },
89001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_82_CHECKER_TYPE,
89002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_82_WIDTH },
89003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_83_CHECKER_TYPE,
89004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_83_WIDTH },
89005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_84_CHECKER_TYPE,
89006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_84_WIDTH },
89007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_85_CHECKER_TYPE,
89008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_85_WIDTH },
89009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_86_CHECKER_TYPE,
89010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_86_WIDTH },
89011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_87_CHECKER_TYPE,
89012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_87_WIDTH },
89013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_88_CHECKER_TYPE,
89014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_88_WIDTH },
89015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_89_CHECKER_TYPE,
89016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_89_WIDTH },
89017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_90_CHECKER_TYPE,
89018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_90_WIDTH },
89019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_91_CHECKER_TYPE,
89020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_91_WIDTH },
89021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_92_CHECKER_TYPE,
89022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_92_WIDTH },
89023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_93_CHECKER_TYPE,
89024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_93_WIDTH },
89025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_94_CHECKER_TYPE,
89026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_94_WIDTH },
89027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_95_CHECKER_TYPE,
89028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_95_WIDTH },
89029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_96_CHECKER_TYPE,
89030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_96_WIDTH },
89031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_97_CHECKER_TYPE,
89032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_97_WIDTH },
89033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_98_CHECKER_TYPE,
89034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_98_WIDTH },
89035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_99_CHECKER_TYPE,
89036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_99_WIDTH },
89037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_100_CHECKER_TYPE,
89038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_100_WIDTH },
89039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_101_CHECKER_TYPE,
89040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_101_WIDTH },
89041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_102_CHECKER_TYPE,
89042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_102_WIDTH },
89043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_103_CHECKER_TYPE,
89044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_103_WIDTH },
89045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_104_CHECKER_TYPE,
89046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_104_WIDTH },
89047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_105_CHECKER_TYPE,
89048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_105_WIDTH },
89049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_106_CHECKER_TYPE,
89050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_106_WIDTH },
89051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_107_CHECKER_TYPE,
89052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_107_WIDTH },
89053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_108_CHECKER_TYPE,
89054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_108_WIDTH },
89055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_109_CHECKER_TYPE,
89056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_109_WIDTH },
89057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_110_CHECKER_TYPE,
89058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_110_WIDTH },
89059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_111_CHECKER_TYPE,
89060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_111_WIDTH },
89061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_112_CHECKER_TYPE,
89062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_112_WIDTH },
89063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_113_CHECKER_TYPE,
89064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_113_WIDTH },
89065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_114_CHECKER_TYPE,
89066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_114_WIDTH },
89067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_115_CHECKER_TYPE,
89068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_115_WIDTH },
89069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_116_CHECKER_TYPE,
89070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_116_WIDTH },
89071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_117_CHECKER_TYPE,
89072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_117_WIDTH },
89073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_118_CHECKER_TYPE,
89074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_118_WIDTH },
89075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_119_CHECKER_TYPE,
89076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_119_WIDTH },
89077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_120_CHECKER_TYPE,
89078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_120_WIDTH },
89079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_121_CHECKER_TYPE,
89080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_121_WIDTH },
89081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_122_CHECKER_TYPE,
89082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_122_WIDTH },
89083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_123_CHECKER_TYPE,
89084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_123_WIDTH },
89085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_124_CHECKER_TYPE,
89086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_124_WIDTH },
89087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_125_CHECKER_TYPE,
89088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_125_WIDTH },
89089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_126_CHECKER_TYPE,
89090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_126_WIDTH },
89091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_127_CHECKER_TYPE,
89092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_127_WIDTH },
89093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_128_CHECKER_TYPE,
89094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_128_WIDTH },
89095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_129_CHECKER_TYPE,
89096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_129_WIDTH },
89097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_130_CHECKER_TYPE,
89098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_130_WIDTH },
89099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_131_CHECKER_TYPE,
89100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_131_WIDTH },
89101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_132_CHECKER_TYPE,
89102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_132_WIDTH },
89103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_133_CHECKER_TYPE,
89104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_133_WIDTH },
89105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_134_CHECKER_TYPE,
89106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_134_WIDTH },
89107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_135_CHECKER_TYPE,
89108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_135_WIDTH },
89109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_136_CHECKER_TYPE,
89110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_136_WIDTH },
89111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_137_CHECKER_TYPE,
89112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_137_WIDTH },
89113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_138_CHECKER_TYPE,
89114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_138_WIDTH },
89115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_139_CHECKER_TYPE,
89116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_139_WIDTH },
89117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_140_CHECKER_TYPE,
89118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_140_WIDTH },
89119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_141_CHECKER_TYPE,
89120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_141_WIDTH },
89121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_142_CHECKER_TYPE,
89122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_142_WIDTH },
89123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_143_CHECKER_TYPE,
89124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_143_WIDTH },
89125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_144_CHECKER_TYPE,
89126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_144_WIDTH },
89127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_145_CHECKER_TYPE,
89128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_145_WIDTH },
89129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_146_CHECKER_TYPE,
89130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_146_WIDTH },
89131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_147_CHECKER_TYPE,
89132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_147_WIDTH },
89133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_148_CHECKER_TYPE,
89134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_148_WIDTH },
89135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_149_CHECKER_TYPE,
89136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_149_WIDTH },
89137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_150_CHECKER_TYPE,
89138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_150_WIDTH },
89139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_151_CHECKER_TYPE,
89140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_151_WIDTH },
89141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_152_CHECKER_TYPE,
89142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_152_WIDTH },
89143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_153_CHECKER_TYPE,
89144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_153_WIDTH },
89145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_154_CHECKER_TYPE,
89146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_154_WIDTH },
89147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_155_CHECKER_TYPE,
89148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_155_WIDTH },
89149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_156_CHECKER_TYPE,
89150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_156_WIDTH },
89151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_157_CHECKER_TYPE,
89152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_157_WIDTH },
89153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_158_CHECKER_TYPE,
89154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_158_WIDTH },
89155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_159_CHECKER_TYPE,
89156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_159_WIDTH },
89157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_160_CHECKER_TYPE,
89158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_160_WIDTH },
89159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_161_CHECKER_TYPE,
89160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_161_WIDTH },
89161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_162_CHECKER_TYPE,
89162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_162_WIDTH },
89163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_163_CHECKER_TYPE,
89164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_163_WIDTH },
89165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_164_CHECKER_TYPE,
89166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_164_WIDTH },
89167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_165_CHECKER_TYPE,
89168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_165_WIDTH },
89169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_166_CHECKER_TYPE,
89170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_166_WIDTH },
89171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_167_CHECKER_TYPE,
89172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_167_WIDTH },
89173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_168_CHECKER_TYPE,
89174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_168_WIDTH },
89175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_169_CHECKER_TYPE,
89176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_169_WIDTH },
89177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_170_CHECKER_TYPE,
89178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_170_WIDTH },
89179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_171_CHECKER_TYPE,
89180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_171_WIDTH },
89181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_172_CHECKER_TYPE,
89182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_172_WIDTH },
89183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_173_CHECKER_TYPE,
89184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_173_WIDTH },
89185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_174_CHECKER_TYPE,
89186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_174_WIDTH },
89187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_175_CHECKER_TYPE,
89188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_175_WIDTH },
89189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_176_CHECKER_TYPE,
89190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_176_WIDTH },
89191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_177_CHECKER_TYPE,
89192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_177_WIDTH },
89193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_178_CHECKER_TYPE,
89194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_178_WIDTH },
89195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_179_CHECKER_TYPE,
89196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_179_WIDTH },
89197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_180_CHECKER_TYPE,
89198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_180_WIDTH },
89199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_181_CHECKER_TYPE,
89200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_181_WIDTH },
89201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_182_CHECKER_TYPE,
89202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_182_WIDTH },
89203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_183_CHECKER_TYPE,
89204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_183_WIDTH },
89205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_184_CHECKER_TYPE,
89206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_184_WIDTH },
89207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_185_CHECKER_TYPE,
89208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_185_WIDTH },
89209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_186_CHECKER_TYPE,
89210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_186_WIDTH },
89211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_187_CHECKER_TYPE,
89212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_187_WIDTH },
89213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_188_CHECKER_TYPE,
89214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_188_WIDTH },
89215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_189_CHECKER_TYPE,
89216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_189_WIDTH },
89217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_190_CHECKER_TYPE,
89218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_190_WIDTH },
89219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_191_CHECKER_TYPE,
89220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_191_WIDTH },
89221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_192_CHECKER_TYPE,
89222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_192_WIDTH },
89223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_193_CHECKER_TYPE,
89224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_193_WIDTH },
89225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_194_CHECKER_TYPE,
89226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_194_WIDTH },
89227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_195_CHECKER_TYPE,
89228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_195_WIDTH },
89229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_196_CHECKER_TYPE,
89230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_196_WIDTH },
89231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_197_CHECKER_TYPE,
89232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_197_WIDTH },
89233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_198_CHECKER_TYPE,
89234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_198_WIDTH },
89235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_199_CHECKER_TYPE,
89236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_199_WIDTH },
89237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_200_CHECKER_TYPE,
89238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_200_WIDTH },
89239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_201_CHECKER_TYPE,
89240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_201_WIDTH },
89241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_202_CHECKER_TYPE,
89242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_202_WIDTH },
89243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_203_CHECKER_TYPE,
89244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_203_WIDTH },
89245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_204_CHECKER_TYPE,
89246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_204_WIDTH },
89247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_205_CHECKER_TYPE,
89248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_205_WIDTH },
89249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_206_CHECKER_TYPE,
89250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_206_WIDTH },
89251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_207_CHECKER_TYPE,
89252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_207_WIDTH },
89253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_208_CHECKER_TYPE,
89254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_208_WIDTH },
89255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_209_CHECKER_TYPE,
89256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_209_WIDTH },
89257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_210_CHECKER_TYPE,
89258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_210_WIDTH },
89259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_211_CHECKER_TYPE,
89260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_211_WIDTH },
89261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_212_CHECKER_TYPE,
89262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_212_WIDTH },
89263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_213_CHECKER_TYPE,
89264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_213_WIDTH },
89265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_214_CHECKER_TYPE,
89266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_214_WIDTH },
89267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_215_CHECKER_TYPE,
89268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_215_WIDTH },
89269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_216_CHECKER_TYPE,
89270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_216_WIDTH },
89271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_217_CHECKER_TYPE,
89272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_217_WIDTH },
89273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_218_CHECKER_TYPE,
89274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_218_WIDTH },
89275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_219_CHECKER_TYPE,
89276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_219_WIDTH },
89277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_220_CHECKER_TYPE,
89278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_220_WIDTH },
89279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_221_CHECKER_TYPE,
89280  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_221_WIDTH },
89281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_222_CHECKER_TYPE,
89282  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_222_WIDTH },
89283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_223_CHECKER_TYPE,
89284  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_223_WIDTH },
89285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_224_CHECKER_TYPE,
89286  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_224_WIDTH },
89287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_225_CHECKER_TYPE,
89288  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_225_WIDTH },
89289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_226_CHECKER_TYPE,
89290  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_226_WIDTH },
89291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_227_CHECKER_TYPE,
89292  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_227_WIDTH },
89293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_228_CHECKER_TYPE,
89294  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_228_WIDTH },
89295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_229_CHECKER_TYPE,
89296  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_229_WIDTH },
89297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_230_CHECKER_TYPE,
89298  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_230_WIDTH },
89299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_231_CHECKER_TYPE,
89300  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_231_WIDTH },
89301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_232_CHECKER_TYPE,
89302  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_232_WIDTH },
89303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_233_CHECKER_TYPE,
89304  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_233_WIDTH },
89305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_234_CHECKER_TYPE,
89306  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_234_WIDTH },
89307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_235_CHECKER_TYPE,
89308  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_235_WIDTH },
89309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_236_CHECKER_TYPE,
89310  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_236_WIDTH },
89311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_237_CHECKER_TYPE,
89312  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_237_WIDTH },
89313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_238_CHECKER_TYPE,
89314  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_238_WIDTH },
89315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_239_CHECKER_TYPE,
89316  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_239_WIDTH },
89317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_240_CHECKER_TYPE,
89318  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_240_WIDTH },
89319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_241_CHECKER_TYPE,
89320  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_241_WIDTH },
89321  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_242_CHECKER_TYPE,
89322  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_242_WIDTH },
89323  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_243_CHECKER_TYPE,
89324  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_243_WIDTH },
89325  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_244_CHECKER_TYPE,
89326  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_244_WIDTH },
89327  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_245_CHECKER_TYPE,
89328  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_245_WIDTH },
89329  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_246_CHECKER_TYPE,
89330  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_246_WIDTH },
89331  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_247_CHECKER_TYPE,
89332  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_247_WIDTH },
89333  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_248_CHECKER_TYPE,
89334  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_248_WIDTH },
89335  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_249_CHECKER_TYPE,
89336  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_249_WIDTH },
89337  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_250_CHECKER_TYPE,
89338  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_250_WIDTH },
89339  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_251_CHECKER_TYPE,
89340  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_251_WIDTH },
89341  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_252_CHECKER_TYPE,
89342  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_252_WIDTH },
89343  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_253_CHECKER_TYPE,
89344  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_253_WIDTH },
89345  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_254_CHECKER_TYPE,
89346  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_254_WIDTH },
89347  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_255_CHECKER_TYPE,
89348  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_GROUP_255_WIDTH },
89349 };
89350 
89356 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS] =
89357 {
89358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_0_CHECKER_TYPE,
89359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_0_WIDTH },
89360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_1_CHECKER_TYPE,
89361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_1_WIDTH },
89362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_2_CHECKER_TYPE,
89363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_2_WIDTH },
89364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_3_CHECKER_TYPE,
89365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_3_WIDTH },
89366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_4_CHECKER_TYPE,
89367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_4_WIDTH },
89368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_5_CHECKER_TYPE,
89369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_5_WIDTH },
89370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_6_CHECKER_TYPE,
89371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_6_WIDTH },
89372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_7_CHECKER_TYPE,
89373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_7_WIDTH },
89374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_8_CHECKER_TYPE,
89375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_8_WIDTH },
89376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_9_CHECKER_TYPE,
89377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_9_WIDTH },
89378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_10_CHECKER_TYPE,
89379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_10_WIDTH },
89380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_11_CHECKER_TYPE,
89381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_11_WIDTH },
89382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_12_CHECKER_TYPE,
89383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_12_WIDTH },
89384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_13_CHECKER_TYPE,
89385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_13_WIDTH },
89386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_14_CHECKER_TYPE,
89387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_14_WIDTH },
89388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_15_CHECKER_TYPE,
89389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_15_WIDTH },
89390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_16_CHECKER_TYPE,
89391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_16_WIDTH },
89392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_17_CHECKER_TYPE,
89393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_17_WIDTH },
89394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_18_CHECKER_TYPE,
89395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_18_WIDTH },
89396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_19_CHECKER_TYPE,
89397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_19_WIDTH },
89398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_20_CHECKER_TYPE,
89399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_20_WIDTH },
89400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_21_CHECKER_TYPE,
89401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_21_WIDTH },
89402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_22_CHECKER_TYPE,
89403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_22_WIDTH },
89404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_23_CHECKER_TYPE,
89405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_23_WIDTH },
89406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_24_CHECKER_TYPE,
89407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_24_WIDTH },
89408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_25_CHECKER_TYPE,
89409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_25_WIDTH },
89410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_26_CHECKER_TYPE,
89411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_26_WIDTH },
89412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_27_CHECKER_TYPE,
89413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_27_WIDTH },
89414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_28_CHECKER_TYPE,
89415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_28_WIDTH },
89416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_29_CHECKER_TYPE,
89417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_29_WIDTH },
89418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_30_CHECKER_TYPE,
89419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_30_WIDTH },
89420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_31_CHECKER_TYPE,
89421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_31_WIDTH },
89422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_32_CHECKER_TYPE,
89423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_32_WIDTH },
89424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_33_CHECKER_TYPE,
89425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_33_WIDTH },
89426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_34_CHECKER_TYPE,
89427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_34_WIDTH },
89428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_35_CHECKER_TYPE,
89429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_35_WIDTH },
89430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_36_CHECKER_TYPE,
89431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_36_WIDTH },
89432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_37_CHECKER_TYPE,
89433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_37_WIDTH },
89434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_38_CHECKER_TYPE,
89435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_38_WIDTH },
89436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_39_CHECKER_TYPE,
89437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_39_WIDTH },
89438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_40_CHECKER_TYPE,
89439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_40_WIDTH },
89440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_41_CHECKER_TYPE,
89441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_41_WIDTH },
89442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_42_CHECKER_TYPE,
89443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_42_WIDTH },
89444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_43_CHECKER_TYPE,
89445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_43_WIDTH },
89446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_44_CHECKER_TYPE,
89447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_44_WIDTH },
89448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_45_CHECKER_TYPE,
89449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_45_WIDTH },
89450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_46_CHECKER_TYPE,
89451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_46_WIDTH },
89452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_47_CHECKER_TYPE,
89453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_47_WIDTH },
89454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_48_CHECKER_TYPE,
89455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_48_WIDTH },
89456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_49_CHECKER_TYPE,
89457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_49_WIDTH },
89458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_50_CHECKER_TYPE,
89459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_50_WIDTH },
89460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_51_CHECKER_TYPE,
89461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_51_WIDTH },
89462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_52_CHECKER_TYPE,
89463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_52_WIDTH },
89464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_53_CHECKER_TYPE,
89465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_53_WIDTH },
89466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_54_CHECKER_TYPE,
89467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_54_WIDTH },
89468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_55_CHECKER_TYPE,
89469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_55_WIDTH },
89470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_56_CHECKER_TYPE,
89471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_56_WIDTH },
89472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_57_CHECKER_TYPE,
89473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_57_WIDTH },
89474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_58_CHECKER_TYPE,
89475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_58_WIDTH },
89476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_59_CHECKER_TYPE,
89477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_59_WIDTH },
89478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_60_CHECKER_TYPE,
89479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_60_WIDTH },
89480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_61_CHECKER_TYPE,
89481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_61_WIDTH },
89482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_62_CHECKER_TYPE,
89483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_62_WIDTH },
89484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_63_CHECKER_TYPE,
89485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_63_WIDTH },
89486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_64_CHECKER_TYPE,
89487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_64_WIDTH },
89488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_65_CHECKER_TYPE,
89489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_65_WIDTH },
89490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_66_CHECKER_TYPE,
89491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_66_WIDTH },
89492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_67_CHECKER_TYPE,
89493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_67_WIDTH },
89494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_68_CHECKER_TYPE,
89495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_68_WIDTH },
89496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_69_CHECKER_TYPE,
89497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_69_WIDTH },
89498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_70_CHECKER_TYPE,
89499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_70_WIDTH },
89500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_71_CHECKER_TYPE,
89501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_71_WIDTH },
89502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_72_CHECKER_TYPE,
89503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_72_WIDTH },
89504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_73_CHECKER_TYPE,
89505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_73_WIDTH },
89506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_74_CHECKER_TYPE,
89507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_74_WIDTH },
89508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_75_CHECKER_TYPE,
89509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_75_WIDTH },
89510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_76_CHECKER_TYPE,
89511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_76_WIDTH },
89512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_77_CHECKER_TYPE,
89513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_77_WIDTH },
89514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_78_CHECKER_TYPE,
89515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_78_WIDTH },
89516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_79_CHECKER_TYPE,
89517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_79_WIDTH },
89518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_80_CHECKER_TYPE,
89519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_80_WIDTH },
89520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_81_CHECKER_TYPE,
89521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_81_WIDTH },
89522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_82_CHECKER_TYPE,
89523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_82_WIDTH },
89524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_83_CHECKER_TYPE,
89525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_83_WIDTH },
89526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_84_CHECKER_TYPE,
89527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_84_WIDTH },
89528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_85_CHECKER_TYPE,
89529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_85_WIDTH },
89530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_86_CHECKER_TYPE,
89531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_86_WIDTH },
89532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_87_CHECKER_TYPE,
89533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_87_WIDTH },
89534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_88_CHECKER_TYPE,
89535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_88_WIDTH },
89536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_89_CHECKER_TYPE,
89537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_89_WIDTH },
89538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_90_CHECKER_TYPE,
89539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_90_WIDTH },
89540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_91_CHECKER_TYPE,
89541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_91_WIDTH },
89542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_92_CHECKER_TYPE,
89543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_92_WIDTH },
89544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_93_CHECKER_TYPE,
89545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_93_WIDTH },
89546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_94_CHECKER_TYPE,
89547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_94_WIDTH },
89548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_95_CHECKER_TYPE,
89549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_95_WIDTH },
89550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_96_CHECKER_TYPE,
89551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_96_WIDTH },
89552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_97_CHECKER_TYPE,
89553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_97_WIDTH },
89554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_98_CHECKER_TYPE,
89555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_98_WIDTH },
89556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_99_CHECKER_TYPE,
89557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_99_WIDTH },
89558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_100_CHECKER_TYPE,
89559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_100_WIDTH },
89560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_101_CHECKER_TYPE,
89561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_101_WIDTH },
89562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_102_CHECKER_TYPE,
89563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_102_WIDTH },
89564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_103_CHECKER_TYPE,
89565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_103_WIDTH },
89566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_104_CHECKER_TYPE,
89567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_104_WIDTH },
89568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_105_CHECKER_TYPE,
89569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_105_WIDTH },
89570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_106_CHECKER_TYPE,
89571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_106_WIDTH },
89572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_107_CHECKER_TYPE,
89573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_107_WIDTH },
89574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_108_CHECKER_TYPE,
89575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_108_WIDTH },
89576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_109_CHECKER_TYPE,
89577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_109_WIDTH },
89578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_110_CHECKER_TYPE,
89579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_110_WIDTH },
89580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_111_CHECKER_TYPE,
89581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_111_WIDTH },
89582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_112_CHECKER_TYPE,
89583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_112_WIDTH },
89584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_113_CHECKER_TYPE,
89585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_113_WIDTH },
89586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_114_CHECKER_TYPE,
89587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_114_WIDTH },
89588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_115_CHECKER_TYPE,
89589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_115_WIDTH },
89590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_116_CHECKER_TYPE,
89591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_116_WIDTH },
89592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_117_CHECKER_TYPE,
89593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_117_WIDTH },
89594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_118_CHECKER_TYPE,
89595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_118_WIDTH },
89596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_119_CHECKER_TYPE,
89597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_119_WIDTH },
89598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_120_CHECKER_TYPE,
89599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_120_WIDTH },
89600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_121_CHECKER_TYPE,
89601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_121_WIDTH },
89602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_122_CHECKER_TYPE,
89603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_122_WIDTH },
89604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_123_CHECKER_TYPE,
89605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_123_WIDTH },
89606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_124_CHECKER_TYPE,
89607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_124_WIDTH },
89608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_125_CHECKER_TYPE,
89609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_125_WIDTH },
89610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_126_CHECKER_TYPE,
89611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_126_WIDTH },
89612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_127_CHECKER_TYPE,
89613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_127_WIDTH },
89614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_128_CHECKER_TYPE,
89615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_128_WIDTH },
89616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_129_CHECKER_TYPE,
89617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_129_WIDTH },
89618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_130_CHECKER_TYPE,
89619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_130_WIDTH },
89620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_131_CHECKER_TYPE,
89621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_131_WIDTH },
89622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_132_CHECKER_TYPE,
89623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_132_WIDTH },
89624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_133_CHECKER_TYPE,
89625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_133_WIDTH },
89626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_134_CHECKER_TYPE,
89627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_134_WIDTH },
89628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_135_CHECKER_TYPE,
89629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_135_WIDTH },
89630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_136_CHECKER_TYPE,
89631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_GROUP_136_WIDTH },
89632 };
89633 
89639 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
89640 {
89641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
89642  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
89643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
89644  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
89645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
89646  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
89647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
89648  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
89649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
89650  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
89651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
89652  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
89653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
89654  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
89655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
89656  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
89657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
89658  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
89659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
89660  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
89661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
89662  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
89663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
89664  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
89665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
89666  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
89667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
89668  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
89669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
89670  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
89671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
89672  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
89673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
89674  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
89675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
89676  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
89677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
89678  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
89679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
89680  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
89681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
89682  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
89683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
89684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
89685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
89686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
89687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
89688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
89689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
89690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
89691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
89692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
89693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
89694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
89695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
89696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
89697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
89698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
89699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
89700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
89701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
89702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
89703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
89704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
89705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
89706  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
89707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
89708  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
89709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
89710  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
89711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
89712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
89713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
89714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
89715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
89716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
89717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
89718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
89719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
89720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
89721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
89722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
89723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
89724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
89725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
89726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
89727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
89728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
89729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
89730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
89731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
89732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
89733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
89734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
89735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
89736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
89737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
89738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
89739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
89740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
89741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
89742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
89743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
89744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
89745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
89746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
89747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
89748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
89749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
89750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
89751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
89752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
89753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
89754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
89755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
89756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
89757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
89758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
89759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
89760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
89761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
89762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
89763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
89764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
89765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
89766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
89767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
89768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
89769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
89770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
89771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
89772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
89773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
89774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
89775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
89776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
89777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
89778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
89779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
89780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
89781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
89782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
89783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
89784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
89785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
89786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
89787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
89788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
89789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
89790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
89791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
89792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
89793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
89794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
89795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
89796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
89797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
89798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
89799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
89800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
89801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
89802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
89803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
89804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
89805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
89806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
89807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
89808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
89809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
89810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
89811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
89812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
89813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
89814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
89815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
89816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
89817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
89818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
89819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
89820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
89821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
89822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
89823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
89824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
89825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
89826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
89827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
89828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
89829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
89830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
89831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
89832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
89833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
89834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
89835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
89836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
89837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
89838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
89839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
89840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
89841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
89842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
89843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
89844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
89845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
89846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
89847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
89848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
89849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
89850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
89851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
89852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
89853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
89854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
89855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
89856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
89857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
89858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
89859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
89860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
89861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
89862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
89863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
89864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
89865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
89866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
89867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
89868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
89869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
89870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
89871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
89872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
89873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
89874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
89875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
89876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
89877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
89878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
89879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
89880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
89881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
89882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
89883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
89884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
89885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
89886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
89887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
89888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
89889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
89890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
89891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
89892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
89893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
89894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
89895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
89896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
89897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
89898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
89899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
89900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
89901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
89902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
89903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
89904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
89905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
89906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
89907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
89908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
89909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
89910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
89911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
89912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
89913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
89914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
89915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
89916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
89917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
89918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
89919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
89920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
89921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
89922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
89923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
89924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
89925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
89926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
89927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
89928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
89929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
89930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
89931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
89932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
89933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
89934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
89935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
89936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
89937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
89938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
89939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
89940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
89941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
89942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
89943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
89944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
89945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
89946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
89947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
89948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
89949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
89950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
89951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
89952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
89953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
89954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
89955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
89956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
89957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
89958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
89959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
89960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
89961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
89962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
89963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
89964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
89965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
89966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
89967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
89968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
89969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
89970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
89971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
89972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
89973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
89974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
89975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
89976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
89977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
89978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
89979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
89980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
89981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
89982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
89983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
89984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
89985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
89986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
89987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
89988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
89989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
89990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
89991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
89992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
89993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
89994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
89995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
89996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
89997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
89998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
89999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
90000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
90001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
90002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
90003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
90004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
90005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
90006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
90007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
90008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
90009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
90010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
90011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
90012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
90013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
90014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
90015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
90016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
90017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
90018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
90019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
90020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
90021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
90022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
90023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
90024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
90025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
90026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
90027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
90028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
90029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
90030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
90031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
90032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
90033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
90034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
90035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
90036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
90037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
90038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
90039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
90040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
90041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
90042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
90043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
90044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
90045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
90046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
90047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
90048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
90049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
90050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
90051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
90052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
90053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
90054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
90055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
90056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
90057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
90058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
90059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
90060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
90061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
90062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
90063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
90064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
90065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
90066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
90067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
90068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
90069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
90070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
90071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
90072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
90073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
90074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
90075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
90076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
90077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
90078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
90079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
90080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
90081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
90082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
90083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
90084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
90085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
90086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
90087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
90088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
90089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
90090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
90091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
90092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
90093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
90094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
90095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
90096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
90097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
90098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
90099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
90100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
90101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
90102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
90103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
90104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
90105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
90106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
90107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
90108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
90109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
90110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
90111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
90112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
90113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
90114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
90115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
90116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
90117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
90118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
90119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
90120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
90121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
90122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
90123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
90124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
90125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
90126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
90127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
90128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
90129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
90130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
90131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
90132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
90133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
90134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
90135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
90136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
90137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
90138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
90139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
90140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
90141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
90142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
90143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
90144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
90145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
90146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
90147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
90148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
90149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
90150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
90151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
90152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
90153 };
90154 
90160 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
90161 {
90162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
90163  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
90164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
90165  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
90166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
90167  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
90168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
90169  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
90170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
90171  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
90172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
90173  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
90174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
90175  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
90176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
90177  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
90178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
90179  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
90180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
90181  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
90182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
90183  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
90184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
90185  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
90186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
90187  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
90188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
90189  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
90190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
90191  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
90192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
90193  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
90194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
90195  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
90196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
90197  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
90198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
90199  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
90200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
90201  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
90202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
90203  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
90204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
90205  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
90206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
90207  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
90208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
90209  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
90210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
90211  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
90212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
90213  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
90214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
90215  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
90216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
90217  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
90218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
90219  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
90220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
90221  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
90222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
90223  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
90224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
90225  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
90226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
90227  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
90228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
90229  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
90230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
90231  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
90232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
90233  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
90234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
90235  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
90236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
90237  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
90238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
90239  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
90240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
90241  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
90242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
90243  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
90244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
90245  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
90246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
90247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
90248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
90249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
90250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
90251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
90252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
90253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
90254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
90255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
90256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
90257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
90258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
90259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
90260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
90261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
90262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
90263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
90264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
90265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
90266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
90267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
90268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
90269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
90270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
90271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
90272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
90273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
90274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
90275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
90276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
90277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
90278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
90279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
90280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
90281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
90282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
90283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
90284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
90285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
90286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
90287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
90288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
90289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
90290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
90291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
90292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
90293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
90294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
90295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
90296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
90297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
90298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
90299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
90300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
90301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
90302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
90303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
90304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
90305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
90306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
90307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
90308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
90309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
90310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
90311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
90312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
90313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
90314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
90315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
90316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
90317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
90318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
90319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
90320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
90321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
90322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
90323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
90324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
90325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
90326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
90327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
90328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
90329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
90330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
90331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
90332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
90333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
90334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
90335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
90336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
90337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
90338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
90339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
90340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
90341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
90342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
90343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
90344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
90345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
90346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
90347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
90348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
90349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
90350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
90351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
90352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
90353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
90354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
90355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
90356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
90357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
90358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
90359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
90360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
90361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
90362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
90363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
90364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
90365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
90366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
90367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
90368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
90369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
90370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
90371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
90372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
90373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
90374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
90375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
90376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
90377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
90378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
90379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
90380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
90381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
90382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
90383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
90384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
90385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
90386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
90387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
90388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
90389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
90390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
90391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
90392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
90393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
90394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
90395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
90396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
90397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
90398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
90399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
90400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
90401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
90402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
90403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
90404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
90405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
90406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
90407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
90408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
90409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
90410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
90411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
90412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
90413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
90414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
90415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
90416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
90417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
90418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
90419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
90420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
90421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
90422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
90423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
90424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
90425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
90426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
90427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
90428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
90429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
90430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
90431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
90432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
90433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
90434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
90435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
90436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
90437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
90438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
90439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
90440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
90441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
90442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
90443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
90444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
90445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
90446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
90447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
90448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
90449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
90450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
90451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
90452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
90453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
90454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
90455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
90456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
90457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
90458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
90459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
90460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
90461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
90462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
90463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
90464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
90465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
90466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
90467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
90468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
90469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
90470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
90471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
90472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
90473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
90474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
90475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
90476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
90477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
90478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
90479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
90480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
90481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
90482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
90483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
90484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
90485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
90486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
90487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
90488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
90489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
90490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
90491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
90492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
90493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
90494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
90495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
90496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
90497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
90498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
90499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
90500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
90501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
90502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
90503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
90504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
90505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
90506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
90507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
90508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
90509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
90510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
90511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
90512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
90513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
90514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
90515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
90516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
90517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
90518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
90519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
90520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
90521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
90522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
90523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
90524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
90525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
90526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
90527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
90528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
90529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
90530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
90531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
90532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
90533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
90534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
90535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
90536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
90537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
90538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
90539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
90540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
90541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
90542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
90543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
90544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
90545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
90546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
90547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
90548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
90549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
90550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
90551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
90552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
90553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
90554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
90555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
90556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
90557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
90558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
90559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
90560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
90561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
90562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
90563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
90564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
90565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
90566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
90567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
90568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
90569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
90570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
90571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
90572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
90573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
90574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
90575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
90576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
90577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
90578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
90579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
90580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
90581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
90582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
90583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
90584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
90585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
90586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
90587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
90588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
90589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
90590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
90591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
90592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
90593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
90594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
90595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
90596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
90597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
90598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
90599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
90600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
90601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
90602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
90603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
90604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
90605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
90606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
90607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
90608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
90609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
90610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
90611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
90612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
90613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
90614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
90615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
90616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
90617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
90618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
90619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
90620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
90621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
90622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
90623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
90624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
90625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
90626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
90627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
90628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
90629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
90630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
90631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
90632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
90633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
90634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
90635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
90636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
90637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
90638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
90639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
90640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
90641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
90642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
90643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
90644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
90645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
90646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
90647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
90648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
90649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
90650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
90651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
90652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
90653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
90654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
90655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
90656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
90657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
90658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
90659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
90660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
90661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
90662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
90663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
90664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
90665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
90666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
90667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
90668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
90669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
90670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
90671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
90672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
90673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
90674 };
90675 
90681 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
90682 {
90683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
90684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
90685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
90686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
90687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
90688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
90689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
90690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
90691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
90692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
90693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
90694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
90695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
90696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
90697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
90698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
90699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
90700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
90701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
90702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
90703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
90704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
90705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
90706  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
90707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
90708  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
90709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
90710  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
90711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
90712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
90713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
90714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
90715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
90716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
90717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
90718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
90719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
90720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
90721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
90722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
90723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
90724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
90725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
90726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
90727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
90728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
90729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
90730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
90731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
90732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
90733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
90734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
90735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
90736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
90737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
90738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
90739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
90740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
90741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
90742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
90743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
90744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
90745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
90746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
90747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
90748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
90749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
90750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
90751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
90752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
90753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
90754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
90755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
90756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
90757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
90758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
90759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
90760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
90761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
90762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
90763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
90764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
90765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
90766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
90767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
90768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
90769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
90770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
90771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
90772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
90773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
90774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
90775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
90776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
90777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
90778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
90779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
90780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
90781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
90782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
90783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
90784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
90785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
90786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
90787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
90788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
90789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
90790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
90791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
90792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
90793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
90794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
90795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
90796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
90797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
90798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
90799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
90800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
90801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
90802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
90803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
90804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
90805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
90806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
90807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
90808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
90809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
90810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
90811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
90812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
90813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
90814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
90815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
90816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
90817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
90818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
90819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
90820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
90821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
90822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
90823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
90824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
90825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
90826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
90827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
90828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
90829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
90830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
90831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
90832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
90833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
90834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
90835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
90836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
90837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
90838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
90839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
90840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
90841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
90842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
90843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
90844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
90845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
90846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
90847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
90848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
90849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
90850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
90851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
90852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
90853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
90854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
90855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
90856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
90857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
90858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
90859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
90860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
90861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
90862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
90863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
90864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
90865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
90866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
90867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
90868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
90869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
90870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
90871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
90872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
90873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
90874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
90875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
90876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
90877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
90878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
90879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
90880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
90881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
90882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
90883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
90884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
90885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
90886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
90887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
90888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
90889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
90890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
90891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
90892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
90893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
90894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
90895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
90896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
90897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
90898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
90899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
90900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
90901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
90902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
90903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
90904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
90905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
90906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
90907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
90908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
90909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
90910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
90911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
90912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
90913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
90914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
90915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
90916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
90917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
90918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
90919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
90920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
90921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
90922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
90923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
90924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
90925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
90926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
90927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
90928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
90929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
90930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
90931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
90932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
90933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
90934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
90935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
90936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
90937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
90938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
90939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
90940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
90941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
90942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
90943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
90944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
90945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
90946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
90947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
90948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
90949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
90950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
90951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
90952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
90953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
90954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
90955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
90956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
90957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
90958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
90959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
90960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
90961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
90962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
90963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
90964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
90965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
90966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
90967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
90968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
90969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
90970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
90971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
90972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
90973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
90974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
90975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
90976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
90977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
90978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
90979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
90980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
90981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
90982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
90983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
90984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
90985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
90986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
90987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
90988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
90989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
90990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
90991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
90992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
90993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
90994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
90995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
90996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
90997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
90998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
90999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
91000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
91001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
91002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
91003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
91004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
91005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
91006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
91007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
91008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
91009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
91010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
91011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
91012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
91013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
91014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
91015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
91016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
91017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
91018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
91019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
91020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
91021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
91022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
91023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
91024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
91025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
91026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
91027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
91028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
91029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
91030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
91031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
91032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
91033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
91034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
91035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
91036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
91037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
91038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
91039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
91040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
91041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
91042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
91043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
91044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
91045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
91046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
91047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
91048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
91049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
91050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
91051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
91052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
91053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
91054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
91055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
91056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
91057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
91058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
91059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
91060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
91061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
91062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
91063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
91064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
91065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
91066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
91067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
91068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
91069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
91070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
91071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
91072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
91073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
91074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
91075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
91076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
91077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
91078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
91079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
91080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
91081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
91082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
91083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
91084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
91085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
91086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
91087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
91088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
91089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
91090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
91091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
91092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
91093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
91094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
91095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
91096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
91097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
91098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
91099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
91100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
91101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
91102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
91103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
91104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
91105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
91106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
91107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
91108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
91109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
91110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
91111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
91112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
91113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
91114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
91115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
91116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
91117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
91118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
91119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
91120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
91121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
91122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
91123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
91124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
91125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
91126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
91127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
91128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
91129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
91130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
91131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
91132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
91133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
91134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
91135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
91136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
91137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
91138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
91139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
91140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
91141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
91142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
91143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
91144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
91145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
91146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
91147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
91148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
91149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
91150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
91151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
91152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
91153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
91154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
91155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
91156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
91157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
91158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
91159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
91160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
91161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
91162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
91163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
91164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
91165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
91166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
91167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
91168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
91169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
91170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
91171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
91172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
91173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
91174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
91175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
91176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
91177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
91178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
91179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
91180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
91181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
91182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
91183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
91184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
91185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
91186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
91187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
91188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
91189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
91190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
91191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
91192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
91193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
91194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
91195 };
91196 
91202 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
91203 {
91204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
91205  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
91206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
91207  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
91208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
91209  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
91210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
91211  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
91212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
91213  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
91214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
91215  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
91216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
91217  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
91218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
91219  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
91220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
91221  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
91222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
91223  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
91224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
91225  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
91226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
91227  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
91228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
91229  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
91230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
91231  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
91232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
91233  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
91234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
91235  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
91236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
91237  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
91238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
91239  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
91240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
91241  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
91242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
91243  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
91244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
91245  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
91246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
91247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
91248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
91249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
91250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
91251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
91252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
91253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
91254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
91255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
91256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
91257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
91258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
91259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
91260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
91261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
91262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
91263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
91264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
91265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
91266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
91267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
91268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
91269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
91270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
91271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
91272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
91273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
91274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
91275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
91276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
91277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
91278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
91279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
91280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
91281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
91282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
91283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
91284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
91285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
91286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
91287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
91288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
91289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
91290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
91291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
91292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
91293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
91294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
91295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
91296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
91297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
91298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
91299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
91300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
91301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
91302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
91303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
91304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
91305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
91306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
91307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
91308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
91309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
91310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
91311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
91312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
91313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
91314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
91315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
91316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
91317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
91318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
91319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
91320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
91321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
91322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
91323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
91324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
91325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
91326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
91327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
91328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
91329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
91330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
91331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
91332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
91333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
91334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
91335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
91336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
91337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
91338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
91339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
91340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
91341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
91342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
91343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
91344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
91345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
91346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
91347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
91348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
91349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
91350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
91351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
91352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
91353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
91354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
91355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
91356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
91357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
91358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
91359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
91360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
91361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
91362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
91363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
91364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
91365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
91366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
91367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
91368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
91369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
91370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
91371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
91372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
91373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
91374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
91375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
91376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
91377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
91378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
91379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
91380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
91381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
91382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
91383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
91384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
91385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
91386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
91387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
91388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
91389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
91390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
91391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
91392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
91393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
91394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
91395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
91396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
91397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
91398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
91399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
91400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
91401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
91402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
91403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
91404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
91405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
91406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
91407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
91408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
91409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
91410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
91411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
91412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
91413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
91414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
91415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
91416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
91417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
91418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
91419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
91420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
91421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
91422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
91423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
91424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
91425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
91426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
91427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
91428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
91429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
91430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
91431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
91432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
91433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
91434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
91435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
91436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
91437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
91438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
91439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
91440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
91441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
91442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
91443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
91444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
91445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
91446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
91447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
91448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
91449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
91450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
91451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
91452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
91453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
91454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
91455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
91456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
91457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
91458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
91459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
91460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
91461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
91462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
91463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
91464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
91465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
91466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
91467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
91468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
91469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
91470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
91471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
91472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
91473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
91474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
91475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
91476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
91477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
91478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
91479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
91480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
91481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
91482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
91483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
91484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
91485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
91486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
91487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
91488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
91489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
91490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
91491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
91492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
91493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
91494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
91495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
91496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
91497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
91498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
91499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
91500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
91501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
91502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
91503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
91504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
91505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
91506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
91507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
91508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
91509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
91510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
91511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
91512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
91513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
91514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
91515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
91516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
91517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
91518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
91519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
91520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
91521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
91522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
91523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
91524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
91525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
91526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
91527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
91528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
91529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
91530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
91531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
91532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
91533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
91534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
91535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
91536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
91537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
91538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
91539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
91540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
91541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
91542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
91543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
91544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
91545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
91546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
91547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
91548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
91549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
91550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
91551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
91552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
91553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
91554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
91555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
91556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
91557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
91558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
91559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
91560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
91561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
91562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
91563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
91564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
91565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
91566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
91567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
91568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
91569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
91570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
91571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
91572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
91573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
91574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
91575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
91576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
91577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
91578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
91579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
91580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
91581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
91582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
91583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
91584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
91585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
91586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
91587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
91588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
91589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
91590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
91591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
91592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
91593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
91594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
91595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
91596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
91597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
91598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
91599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
91600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
91601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
91602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
91603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
91604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
91605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
91606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
91607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
91608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
91609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
91610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
91611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
91612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
91613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
91614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
91615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
91616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
91617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
91618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
91619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
91620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
91621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
91622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
91623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
91624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
91625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
91626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
91627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
91628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
91629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
91630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
91631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
91632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
91633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
91634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
91635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
91636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
91637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
91638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
91639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
91640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
91641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
91642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
91643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
91644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
91645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
91646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
91647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
91648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
91649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
91650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
91651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
91652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
91653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
91654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
91655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
91656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
91657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
91658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
91659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
91660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
91661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
91662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
91663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
91664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
91665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
91666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
91667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
91668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
91669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
91670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
91671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
91672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
91673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
91674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
91675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
91676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
91677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
91678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
91679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
91680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
91681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
91682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
91683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
91684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
91685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
91686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
91687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
91688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
91689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
91690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
91691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
91692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
91693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
91694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
91695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
91696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
91697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
91698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
91699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
91700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
91701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
91702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
91703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
91704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
91705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
91706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
91707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
91708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
91709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
91710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
91711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
91712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
91713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
91714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
91715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
91716 };
91717 
91723 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
91724 {
91725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
91726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
91727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
91728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
91729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
91730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
91731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
91732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
91733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
91734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
91735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
91736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
91737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
91738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
91739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
91740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
91741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
91742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
91743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
91744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
91745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
91746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
91747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
91748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
91749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
91750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
91751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
91752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
91753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
91754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
91755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
91756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
91757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
91758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
91759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
91760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
91761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
91762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
91763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
91764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
91765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
91766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
91767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
91768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
91769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
91770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
91771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
91772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
91773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
91774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
91775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
91776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
91777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
91778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
91779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
91780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
91781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
91782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
91783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
91784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
91785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
91786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
91787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
91788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
91789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
91790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
91791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
91792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
91793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
91794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
91795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
91796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
91797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
91798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
91799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
91800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
91801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
91802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
91803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
91804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
91805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
91806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
91807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
91808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
91809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
91810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
91811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
91812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
91813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
91814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
91815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
91816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
91817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
91818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
91819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
91820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
91821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
91822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
91823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
91824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
91825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
91826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
91827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
91828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
91829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
91830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
91831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
91832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
91833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
91834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
91835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
91836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
91837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
91838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
91839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
91840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
91841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
91842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
91843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
91844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
91845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
91846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
91847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
91848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
91849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
91850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
91851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
91852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
91853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
91854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
91855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
91856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
91857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
91858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
91859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
91860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
91861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
91862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
91863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
91864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
91865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
91866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
91867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
91868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
91869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
91870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
91871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
91872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
91873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
91874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
91875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
91876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
91877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
91878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
91879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
91880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
91881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
91882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
91883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
91884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
91885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
91886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
91887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
91888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
91889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
91890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
91891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
91892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
91893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
91894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
91895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
91896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
91897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
91898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
91899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
91900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
91901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
91902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
91903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
91904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
91905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
91906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
91907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
91908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
91909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
91910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
91911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
91912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
91913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
91914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
91915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
91916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
91917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
91918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
91919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
91920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
91921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
91922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
91923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
91924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
91925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
91926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
91927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
91928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
91929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
91930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
91931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
91932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
91933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
91934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
91935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
91936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
91937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
91938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
91939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
91940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
91941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
91942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
91943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
91944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
91945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
91946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
91947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
91948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
91949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
91950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
91951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
91952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
91953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
91954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
91955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
91956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
91957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
91958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
91959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
91960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
91961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
91962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
91963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
91964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
91965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
91966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
91967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
91968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
91969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
91970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
91971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
91972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
91973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
91974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
91975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
91976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
91977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
91978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
91979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
91980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
91981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
91982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
91983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
91984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
91985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
91986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
91987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
91988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
91989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
91990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
91991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
91992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
91993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
91994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
91995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
91996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
91997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
91998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
91999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
92000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
92001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
92002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
92003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
92004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
92005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
92006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
92007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
92008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
92009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
92010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
92011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
92012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
92013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
92014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
92015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
92016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
92017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
92018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
92019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
92020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
92021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
92022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
92023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
92024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
92025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
92026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
92027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
92028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
92029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
92030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
92031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
92032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
92033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
92034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
92035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
92036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
92037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
92038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
92039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
92040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
92041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
92042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
92043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
92044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
92045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
92046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
92047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
92048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
92049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
92050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
92051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
92052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
92053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
92054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
92055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
92056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
92057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
92058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
92059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
92060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
92061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
92062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
92063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
92064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
92065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
92066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
92067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
92068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
92069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
92070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
92071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
92072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
92073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
92074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
92075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
92076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
92077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
92078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
92079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
92080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
92081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
92082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
92083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
92084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
92085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
92086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
92087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
92088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
92089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
92090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
92091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
92092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
92093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
92094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
92095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
92096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
92097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
92098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
92099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
92100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
92101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
92102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
92103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
92104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
92105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
92106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
92107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
92108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
92109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
92110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
92111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
92112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
92113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
92114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
92115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
92116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
92117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
92118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
92119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
92120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
92121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
92122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
92123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
92124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
92125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
92126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
92127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
92128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
92129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
92130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
92131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
92132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
92133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
92134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
92135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
92136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
92137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
92138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
92139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
92140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
92141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
92142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
92143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
92144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
92145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
92146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
92147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
92148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
92149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
92150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
92151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
92152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
92153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
92154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
92155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
92156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
92157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
92158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
92159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
92160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
92161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
92162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
92163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
92164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
92165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
92166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
92167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
92168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
92169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
92170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
92171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
92172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
92173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
92174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
92175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
92176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
92177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
92178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
92179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
92180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
92181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
92182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
92183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
92184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
92185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
92186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
92187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
92188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
92189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
92190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
92191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
92192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
92193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
92194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
92195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
92196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
92197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
92198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
92199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
92200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
92201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
92202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
92203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
92204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
92205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
92206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
92207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
92208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
92209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
92210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
92211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
92212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
92213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
92214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
92215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
92216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
92217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
92218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
92219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
92220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
92221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
92222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
92223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
92224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
92225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
92226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
92227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
92228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
92229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
92230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
92231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
92232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
92233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
92234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
92235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
92236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
92237 };
92238 
92244 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
92245 {
92246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
92247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
92248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
92249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
92250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
92251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
92252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
92253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
92254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
92255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
92256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
92257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
92258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
92259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
92260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
92261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
92262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
92263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
92264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
92265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
92266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
92267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
92268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
92269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
92270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
92271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
92272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
92273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
92274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
92275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
92276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
92277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
92278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
92279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
92280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
92281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
92282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
92283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
92284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
92285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
92286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
92287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
92288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
92289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
92290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
92291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
92292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
92293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
92294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
92295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
92296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
92297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
92298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
92299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
92300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
92301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
92302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
92303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
92304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
92305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
92306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
92307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
92308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
92309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
92310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
92311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
92312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
92313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
92314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
92315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
92316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
92317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
92318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
92319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
92320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
92321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
92322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
92323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
92324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
92325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
92326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
92327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
92328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
92329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
92330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
92331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
92332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
92333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
92334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
92335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
92336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
92337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
92338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
92339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
92340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
92341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
92342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
92343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
92344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
92345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
92346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
92347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
92348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
92349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
92350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
92351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
92352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
92353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
92354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
92355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
92356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
92357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
92358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
92359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
92360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
92361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
92362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
92363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
92364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
92365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
92366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
92367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
92368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
92369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
92370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
92371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
92372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
92373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
92374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
92375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
92376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
92377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
92378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
92379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
92380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
92381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
92382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
92383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
92384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
92385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
92386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
92387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
92388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
92389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
92390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
92391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
92392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
92393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
92394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
92395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
92396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
92397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
92398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
92399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
92400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
92401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
92402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
92403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
92404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
92405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
92406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
92407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
92408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
92409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
92410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
92411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
92412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
92413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
92414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
92415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
92416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
92417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
92418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
92419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
92420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
92421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
92422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
92423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
92424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
92425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
92426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
92427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
92428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
92429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
92430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
92431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
92432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
92433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
92434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
92435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
92436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
92437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
92438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
92439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
92440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
92441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
92442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
92443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
92444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
92445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
92446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
92447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
92448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
92449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
92450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
92451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
92452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
92453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
92454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
92455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
92456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
92457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
92458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
92459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
92460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
92461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
92462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
92463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
92464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
92465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
92466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
92467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
92468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
92469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
92470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
92471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
92472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
92473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
92474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
92475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
92476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
92477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
92478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
92479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
92480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
92481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
92482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
92483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
92484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
92485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
92486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
92487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
92488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
92489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
92490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
92491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
92492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
92493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
92494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
92495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
92496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
92497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
92498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
92499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
92500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
92501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
92502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
92503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
92504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
92505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
92506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
92507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
92508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
92509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
92510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
92511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
92512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
92513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
92514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
92515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
92516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
92517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
92518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
92519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
92520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
92521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
92522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
92523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
92524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
92525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
92526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
92527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
92528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
92529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
92530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
92531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
92532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
92533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
92534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
92535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
92536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
92537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
92538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
92539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
92540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
92541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
92542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
92543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
92544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
92545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
92546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
92547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
92548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
92549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
92550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
92551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
92552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
92553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
92554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
92555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
92556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
92557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
92558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
92559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
92560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
92561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
92562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
92563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
92564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
92565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
92566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
92567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
92568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
92569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
92570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
92571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
92572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
92573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
92574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
92575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
92576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
92577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
92578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
92579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
92580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
92581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
92582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
92583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
92584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
92585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
92586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
92587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
92588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
92589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
92590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
92591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
92592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
92593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
92594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
92595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
92596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
92597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
92598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
92599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
92600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
92601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
92602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
92603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
92604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
92605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
92606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
92607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
92608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
92609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
92610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
92611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
92612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
92613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
92614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
92615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
92616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
92617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
92618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
92619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
92620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_CHECKER_TYPE,
92621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_WIDTH },
92622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_CHECKER_TYPE,
92623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_WIDTH },
92624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_CHECKER_TYPE,
92625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_WIDTH },
92626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_CHECKER_TYPE,
92627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_WIDTH },
92628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_CHECKER_TYPE,
92629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_WIDTH },
92630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_CHECKER_TYPE,
92631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_WIDTH },
92632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_CHECKER_TYPE,
92633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_WIDTH },
92634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_CHECKER_TYPE,
92635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_WIDTH },
92636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_CHECKER_TYPE,
92637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_WIDTH },
92638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_CHECKER_TYPE,
92639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_WIDTH },
92640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_CHECKER_TYPE,
92641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_WIDTH },
92642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_CHECKER_TYPE,
92643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_WIDTH },
92644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_CHECKER_TYPE,
92645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_WIDTH },
92646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_CHECKER_TYPE,
92647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_WIDTH },
92648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_CHECKER_TYPE,
92649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_WIDTH },
92650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_CHECKER_TYPE,
92651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_WIDTH },
92652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_CHECKER_TYPE,
92653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_WIDTH },
92654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_CHECKER_TYPE,
92655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_WIDTH },
92656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_CHECKER_TYPE,
92657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_WIDTH },
92658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_CHECKER_TYPE,
92659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_WIDTH },
92660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_CHECKER_TYPE,
92661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_WIDTH },
92662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_CHECKER_TYPE,
92663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_WIDTH },
92664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_CHECKER_TYPE,
92665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_WIDTH },
92666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_CHECKER_TYPE,
92667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_WIDTH },
92668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_CHECKER_TYPE,
92669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_WIDTH },
92670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_CHECKER_TYPE,
92671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_WIDTH },
92672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_CHECKER_TYPE,
92673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_WIDTH },
92674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_CHECKER_TYPE,
92675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_WIDTH },
92676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_CHECKER_TYPE,
92677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_WIDTH },
92678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_CHECKER_TYPE,
92679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_WIDTH },
92680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_CHECKER_TYPE,
92681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_WIDTH },
92682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_CHECKER_TYPE,
92683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_WIDTH },
92684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_CHECKER_TYPE,
92685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_WIDTH },
92686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_CHECKER_TYPE,
92687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_WIDTH },
92688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_CHECKER_TYPE,
92689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_WIDTH },
92690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_CHECKER_TYPE,
92691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_WIDTH },
92692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_CHECKER_TYPE,
92693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_WIDTH },
92694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_CHECKER_TYPE,
92695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_WIDTH },
92696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_CHECKER_TYPE,
92697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_WIDTH },
92698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_CHECKER_TYPE,
92699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_WIDTH },
92700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_CHECKER_TYPE,
92701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_WIDTH },
92702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_CHECKER_TYPE,
92703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_WIDTH },
92704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_CHECKER_TYPE,
92705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_WIDTH },
92706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_CHECKER_TYPE,
92707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_WIDTH },
92708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_CHECKER_TYPE,
92709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_WIDTH },
92710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_CHECKER_TYPE,
92711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_WIDTH },
92712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_CHECKER_TYPE,
92713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_WIDTH },
92714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_CHECKER_TYPE,
92715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_WIDTH },
92716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_CHECKER_TYPE,
92717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_WIDTH },
92718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_CHECKER_TYPE,
92719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_WIDTH },
92720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_CHECKER_TYPE,
92721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_WIDTH },
92722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_CHECKER_TYPE,
92723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_WIDTH },
92724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_CHECKER_TYPE,
92725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_WIDTH },
92726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_CHECKER_TYPE,
92727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_WIDTH },
92728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_CHECKER_TYPE,
92729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_WIDTH },
92730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_CHECKER_TYPE,
92731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_WIDTH },
92732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_CHECKER_TYPE,
92733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_WIDTH },
92734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_CHECKER_TYPE,
92735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_WIDTH },
92736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_CHECKER_TYPE,
92737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_WIDTH },
92738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_CHECKER_TYPE,
92739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_WIDTH },
92740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_CHECKER_TYPE,
92741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_WIDTH },
92742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_CHECKER_TYPE,
92743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_WIDTH },
92744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_CHECKER_TYPE,
92745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_WIDTH },
92746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_CHECKER_TYPE,
92747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_WIDTH },
92748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_CHECKER_TYPE,
92749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_WIDTH },
92750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_CHECKER_TYPE,
92751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_WIDTH },
92752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_CHECKER_TYPE,
92753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_WIDTH },
92754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_CHECKER_TYPE,
92755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_WIDTH },
92756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_CHECKER_TYPE,
92757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_WIDTH },
92758 };
92759 
92765 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS] =
92766 {
92767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_CHECKER_TYPE,
92768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_WIDTH },
92769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_CHECKER_TYPE,
92770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_WIDTH },
92771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_CHECKER_TYPE,
92772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_WIDTH },
92773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_CHECKER_TYPE,
92774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_WIDTH },
92775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_CHECKER_TYPE,
92776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_WIDTH },
92777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_CHECKER_TYPE,
92778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_WIDTH },
92779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_CHECKER_TYPE,
92780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_WIDTH },
92781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_CHECKER_TYPE,
92782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_WIDTH },
92783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_CHECKER_TYPE,
92784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_WIDTH },
92785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_CHECKER_TYPE,
92786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_WIDTH },
92787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_CHECKER_TYPE,
92788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_WIDTH },
92789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_CHECKER_TYPE,
92790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_WIDTH },
92791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_CHECKER_TYPE,
92792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_WIDTH },
92793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_CHECKER_TYPE,
92794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_WIDTH },
92795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_CHECKER_TYPE,
92796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_WIDTH },
92797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_CHECKER_TYPE,
92798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_WIDTH },
92799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_CHECKER_TYPE,
92800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_WIDTH },
92801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_CHECKER_TYPE,
92802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_WIDTH },
92803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_CHECKER_TYPE,
92804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_WIDTH },
92805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_CHECKER_TYPE,
92806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_WIDTH },
92807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_CHECKER_TYPE,
92808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_WIDTH },
92809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_CHECKER_TYPE,
92810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_WIDTH },
92811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_CHECKER_TYPE,
92812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_WIDTH },
92813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_CHECKER_TYPE,
92814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_WIDTH },
92815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_CHECKER_TYPE,
92816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_WIDTH },
92817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_CHECKER_TYPE,
92818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_WIDTH },
92819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_CHECKER_TYPE,
92820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_WIDTH },
92821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_CHECKER_TYPE,
92822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_WIDTH },
92823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_CHECKER_TYPE,
92824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_WIDTH },
92825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_CHECKER_TYPE,
92826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_WIDTH },
92827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_CHECKER_TYPE,
92828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_WIDTH },
92829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_CHECKER_TYPE,
92830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_WIDTH },
92831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_CHECKER_TYPE,
92832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_WIDTH },
92833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_CHECKER_TYPE,
92834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_WIDTH },
92835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_CHECKER_TYPE,
92836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_WIDTH },
92837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_CHECKER_TYPE,
92838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_WIDTH },
92839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_CHECKER_TYPE,
92840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_WIDTH },
92841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_CHECKER_TYPE,
92842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_WIDTH },
92843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_CHECKER_TYPE,
92844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_WIDTH },
92845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_CHECKER_TYPE,
92846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_WIDTH },
92847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_CHECKER_TYPE,
92848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_WIDTH },
92849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_CHECKER_TYPE,
92850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_WIDTH },
92851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_CHECKER_TYPE,
92852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_WIDTH },
92853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_CHECKER_TYPE,
92854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_WIDTH },
92855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_CHECKER_TYPE,
92856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_WIDTH },
92857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_CHECKER_TYPE,
92858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_WIDTH },
92859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_CHECKER_TYPE,
92860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_WIDTH },
92861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_CHECKER_TYPE,
92862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_WIDTH },
92863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_CHECKER_TYPE,
92864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_WIDTH },
92865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_CHECKER_TYPE,
92866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_WIDTH },
92867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_CHECKER_TYPE,
92868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_WIDTH },
92869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_CHECKER_TYPE,
92870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_WIDTH },
92871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_CHECKER_TYPE,
92872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_WIDTH },
92873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_CHECKER_TYPE,
92874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_WIDTH },
92875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_CHECKER_TYPE,
92876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_WIDTH },
92877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_CHECKER_TYPE,
92878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_WIDTH },
92879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_CHECKER_TYPE,
92880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_WIDTH },
92881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_CHECKER_TYPE,
92882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_WIDTH },
92883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_CHECKER_TYPE,
92884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_WIDTH },
92885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_CHECKER_TYPE,
92886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_WIDTH },
92887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_CHECKER_TYPE,
92888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_WIDTH },
92889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_CHECKER_TYPE,
92890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_WIDTH },
92891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_CHECKER_TYPE,
92892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_WIDTH },
92893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_CHECKER_TYPE,
92894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_WIDTH },
92895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_CHECKER_TYPE,
92896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_WIDTH },
92897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_CHECKER_TYPE,
92898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_WIDTH },
92899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_CHECKER_TYPE,
92900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_WIDTH },
92901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_CHECKER_TYPE,
92902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_WIDTH },
92903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_CHECKER_TYPE,
92904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_WIDTH },
92905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_CHECKER_TYPE,
92906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_WIDTH },
92907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_CHECKER_TYPE,
92908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_WIDTH },
92909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_CHECKER_TYPE,
92910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_WIDTH },
92911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_CHECKER_TYPE,
92912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_WIDTH },
92913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_CHECKER_TYPE,
92914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_WIDTH },
92915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_CHECKER_TYPE,
92916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_WIDTH },
92917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_CHECKER_TYPE,
92918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_WIDTH },
92919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_CHECKER_TYPE,
92920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_WIDTH },
92921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_CHECKER_TYPE,
92922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_WIDTH },
92923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_CHECKER_TYPE,
92924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_WIDTH },
92925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_CHECKER_TYPE,
92926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_WIDTH },
92927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_CHECKER_TYPE,
92928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_WIDTH },
92929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_CHECKER_TYPE,
92930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_WIDTH },
92931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_CHECKER_TYPE,
92932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_WIDTH },
92933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_CHECKER_TYPE,
92934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_WIDTH },
92935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_CHECKER_TYPE,
92936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_WIDTH },
92937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_CHECKER_TYPE,
92938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_WIDTH },
92939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_CHECKER_TYPE,
92940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_WIDTH },
92941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_CHECKER_TYPE,
92942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_WIDTH },
92943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_CHECKER_TYPE,
92944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_WIDTH },
92945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_CHECKER_TYPE,
92946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_WIDTH },
92947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_CHECKER_TYPE,
92948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_WIDTH },
92949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_CHECKER_TYPE,
92950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_WIDTH },
92951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_CHECKER_TYPE,
92952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_WIDTH },
92953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_CHECKER_TYPE,
92954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_WIDTH },
92955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_CHECKER_TYPE,
92956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_WIDTH },
92957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_CHECKER_TYPE,
92958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_WIDTH },
92959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_CHECKER_TYPE,
92960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_WIDTH },
92961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_CHECKER_TYPE,
92962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_WIDTH },
92963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_CHECKER_TYPE,
92964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_WIDTH },
92965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_CHECKER_TYPE,
92966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_WIDTH },
92967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_CHECKER_TYPE,
92968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_WIDTH },
92969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_CHECKER_TYPE,
92970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_WIDTH },
92971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_102_CHECKER_TYPE,
92972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_102_WIDTH },
92973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_103_CHECKER_TYPE,
92974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_103_WIDTH },
92975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_104_CHECKER_TYPE,
92976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_104_WIDTH },
92977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_105_CHECKER_TYPE,
92978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_105_WIDTH },
92979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_106_CHECKER_TYPE,
92980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_106_WIDTH },
92981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_107_CHECKER_TYPE,
92982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_107_WIDTH },
92983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_108_CHECKER_TYPE,
92984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_108_WIDTH },
92985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_109_CHECKER_TYPE,
92986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_109_WIDTH },
92987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_110_CHECKER_TYPE,
92988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_110_WIDTH },
92989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_111_CHECKER_TYPE,
92990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_111_WIDTH },
92991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_112_CHECKER_TYPE,
92992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_112_WIDTH },
92993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_113_CHECKER_TYPE,
92994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_113_WIDTH },
92995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_114_CHECKER_TYPE,
92996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_114_WIDTH },
92997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_115_CHECKER_TYPE,
92998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_115_WIDTH },
92999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_116_CHECKER_TYPE,
93000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_116_WIDTH },
93001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_117_CHECKER_TYPE,
93002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_117_WIDTH },
93003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_118_CHECKER_TYPE,
93004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_118_WIDTH },
93005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_119_CHECKER_TYPE,
93006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_119_WIDTH },
93007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_120_CHECKER_TYPE,
93008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_120_WIDTH },
93009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_121_CHECKER_TYPE,
93010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_121_WIDTH },
93011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_122_CHECKER_TYPE,
93012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_122_WIDTH },
93013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_123_CHECKER_TYPE,
93014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_123_WIDTH },
93015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_124_CHECKER_TYPE,
93016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_124_WIDTH },
93017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_125_CHECKER_TYPE,
93018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_125_WIDTH },
93019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_126_CHECKER_TYPE,
93020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_126_WIDTH },
93021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_127_CHECKER_TYPE,
93022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_127_WIDTH },
93023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_128_CHECKER_TYPE,
93024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_128_WIDTH },
93025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_129_CHECKER_TYPE,
93026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_129_WIDTH },
93027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_130_CHECKER_TYPE,
93028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_130_WIDTH },
93029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_131_CHECKER_TYPE,
93030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_131_WIDTH },
93031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_132_CHECKER_TYPE,
93032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_132_WIDTH },
93033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_133_CHECKER_TYPE,
93034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_133_WIDTH },
93035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_134_CHECKER_TYPE,
93036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_134_WIDTH },
93037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_135_CHECKER_TYPE,
93038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_135_WIDTH },
93039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_136_CHECKER_TYPE,
93040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_136_WIDTH },
93041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_137_CHECKER_TYPE,
93042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_137_WIDTH },
93043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_138_CHECKER_TYPE,
93044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_138_WIDTH },
93045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_139_CHECKER_TYPE,
93046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_139_WIDTH },
93047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_140_CHECKER_TYPE,
93048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_140_WIDTH },
93049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_141_CHECKER_TYPE,
93050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_141_WIDTH },
93051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_142_CHECKER_TYPE,
93052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_142_WIDTH },
93053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_143_CHECKER_TYPE,
93054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_143_WIDTH },
93055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_144_CHECKER_TYPE,
93056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_144_WIDTH },
93057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_145_CHECKER_TYPE,
93058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_145_WIDTH },
93059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_146_CHECKER_TYPE,
93060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_146_WIDTH },
93061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_147_CHECKER_TYPE,
93062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_147_WIDTH },
93063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_148_CHECKER_TYPE,
93064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_148_WIDTH },
93065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_149_CHECKER_TYPE,
93066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_149_WIDTH },
93067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_150_CHECKER_TYPE,
93068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_150_WIDTH },
93069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_151_CHECKER_TYPE,
93070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_151_WIDTH },
93071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_152_CHECKER_TYPE,
93072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_152_WIDTH },
93073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_153_CHECKER_TYPE,
93074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_153_WIDTH },
93075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_154_CHECKER_TYPE,
93076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_154_WIDTH },
93077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_155_CHECKER_TYPE,
93078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_155_WIDTH },
93079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_156_CHECKER_TYPE,
93080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_156_WIDTH },
93081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_157_CHECKER_TYPE,
93082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_157_WIDTH },
93083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_158_CHECKER_TYPE,
93084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_158_WIDTH },
93085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_159_CHECKER_TYPE,
93086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_159_WIDTH },
93087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_160_CHECKER_TYPE,
93088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_160_WIDTH },
93089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_161_CHECKER_TYPE,
93090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_161_WIDTH },
93091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_162_CHECKER_TYPE,
93092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_162_WIDTH },
93093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_163_CHECKER_TYPE,
93094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_163_WIDTH },
93095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_164_CHECKER_TYPE,
93096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_164_WIDTH },
93097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_165_CHECKER_TYPE,
93098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_165_WIDTH },
93099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_166_CHECKER_TYPE,
93100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_166_WIDTH },
93101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_167_CHECKER_TYPE,
93102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_167_WIDTH },
93103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_168_CHECKER_TYPE,
93104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_168_WIDTH },
93105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_169_CHECKER_TYPE,
93106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_169_WIDTH },
93107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_170_CHECKER_TYPE,
93108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_170_WIDTH },
93109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_171_CHECKER_TYPE,
93110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_171_WIDTH },
93111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_172_CHECKER_TYPE,
93112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_172_WIDTH },
93113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_173_CHECKER_TYPE,
93114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_173_WIDTH },
93115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_174_CHECKER_TYPE,
93116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_174_WIDTH },
93117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_175_CHECKER_TYPE,
93118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_175_WIDTH },
93119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_176_CHECKER_TYPE,
93120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_176_WIDTH },
93121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_177_CHECKER_TYPE,
93122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_177_WIDTH },
93123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_178_CHECKER_TYPE,
93124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_178_WIDTH },
93125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_179_CHECKER_TYPE,
93126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_179_WIDTH },
93127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_180_CHECKER_TYPE,
93128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_180_WIDTH },
93129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_181_CHECKER_TYPE,
93130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_181_WIDTH },
93131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_182_CHECKER_TYPE,
93132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_182_WIDTH },
93133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_183_CHECKER_TYPE,
93134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_183_WIDTH },
93135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_184_CHECKER_TYPE,
93136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_184_WIDTH },
93137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_185_CHECKER_TYPE,
93138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_185_WIDTH },
93139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_186_CHECKER_TYPE,
93140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_186_WIDTH },
93141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_187_CHECKER_TYPE,
93142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_187_WIDTH },
93143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_188_CHECKER_TYPE,
93144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_188_WIDTH },
93145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_189_CHECKER_TYPE,
93146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_189_WIDTH },
93147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_190_CHECKER_TYPE,
93148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_190_WIDTH },
93149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_191_CHECKER_TYPE,
93150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_191_WIDTH },
93151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_192_CHECKER_TYPE,
93152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_192_WIDTH },
93153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_193_CHECKER_TYPE,
93154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_193_WIDTH },
93155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_194_CHECKER_TYPE,
93156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_194_WIDTH },
93157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_195_CHECKER_TYPE,
93158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_195_WIDTH },
93159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_196_CHECKER_TYPE,
93160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_196_WIDTH },
93161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_197_CHECKER_TYPE,
93162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_197_WIDTH },
93163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_198_CHECKER_TYPE,
93164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_198_WIDTH },
93165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_199_CHECKER_TYPE,
93166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_199_WIDTH },
93167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_200_CHECKER_TYPE,
93168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_200_WIDTH },
93169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_201_CHECKER_TYPE,
93170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_201_WIDTH },
93171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_202_CHECKER_TYPE,
93172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_202_WIDTH },
93173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_203_CHECKER_TYPE,
93174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_203_WIDTH },
93175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_204_CHECKER_TYPE,
93176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_204_WIDTH },
93177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_205_CHECKER_TYPE,
93178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_205_WIDTH },
93179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_206_CHECKER_TYPE,
93180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_206_WIDTH },
93181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_207_CHECKER_TYPE,
93182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_207_WIDTH },
93183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_208_CHECKER_TYPE,
93184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_208_WIDTH },
93185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_209_CHECKER_TYPE,
93186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_209_WIDTH },
93187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_210_CHECKER_TYPE,
93188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_210_WIDTH },
93189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_211_CHECKER_TYPE,
93190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_211_WIDTH },
93191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_212_CHECKER_TYPE,
93192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_212_WIDTH },
93193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_213_CHECKER_TYPE,
93194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_213_WIDTH },
93195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_214_CHECKER_TYPE,
93196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_214_WIDTH },
93197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_215_CHECKER_TYPE,
93198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_215_WIDTH },
93199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_216_CHECKER_TYPE,
93200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_216_WIDTH },
93201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_217_CHECKER_TYPE,
93202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_217_WIDTH },
93203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_218_CHECKER_TYPE,
93204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_218_WIDTH },
93205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_219_CHECKER_TYPE,
93206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_219_WIDTH },
93207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_220_CHECKER_TYPE,
93208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_220_WIDTH },
93209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_221_CHECKER_TYPE,
93210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_221_WIDTH },
93211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_222_CHECKER_TYPE,
93212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_222_WIDTH },
93213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_223_CHECKER_TYPE,
93214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_223_WIDTH },
93215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_224_CHECKER_TYPE,
93216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_224_WIDTH },
93217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_225_CHECKER_TYPE,
93218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_225_WIDTH },
93219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_226_CHECKER_TYPE,
93220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_226_WIDTH },
93221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_227_CHECKER_TYPE,
93222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_227_WIDTH },
93223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_228_CHECKER_TYPE,
93224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_228_WIDTH },
93225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_229_CHECKER_TYPE,
93226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_229_WIDTH },
93227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_230_CHECKER_TYPE,
93228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_230_WIDTH },
93229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_231_CHECKER_TYPE,
93230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_231_WIDTH },
93231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_232_CHECKER_TYPE,
93232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_232_WIDTH },
93233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_233_CHECKER_TYPE,
93234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_233_WIDTH },
93235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_234_CHECKER_TYPE,
93236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_234_WIDTH },
93237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_235_CHECKER_TYPE,
93238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_235_WIDTH },
93239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_236_CHECKER_TYPE,
93240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_236_WIDTH },
93241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_237_CHECKER_TYPE,
93242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_237_WIDTH },
93243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_238_CHECKER_TYPE,
93244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_238_WIDTH },
93245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_239_CHECKER_TYPE,
93246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_239_WIDTH },
93247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_240_CHECKER_TYPE,
93248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_240_WIDTH },
93249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_241_CHECKER_TYPE,
93250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_241_WIDTH },
93251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_242_CHECKER_TYPE,
93252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_242_WIDTH },
93253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_243_CHECKER_TYPE,
93254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_243_WIDTH },
93255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_244_CHECKER_TYPE,
93256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_244_WIDTH },
93257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_245_CHECKER_TYPE,
93258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_245_WIDTH },
93259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_246_CHECKER_TYPE,
93260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_246_WIDTH },
93261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_247_CHECKER_TYPE,
93262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_247_WIDTH },
93263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_248_CHECKER_TYPE,
93264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_248_WIDTH },
93265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_249_CHECKER_TYPE,
93266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_249_WIDTH },
93267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_250_CHECKER_TYPE,
93268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_250_WIDTH },
93269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_251_CHECKER_TYPE,
93270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_251_WIDTH },
93271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_252_CHECKER_TYPE,
93272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_252_WIDTH },
93273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_253_CHECKER_TYPE,
93274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_253_WIDTH },
93275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_254_CHECKER_TYPE,
93276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_254_WIDTH },
93277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_255_CHECKER_TYPE,
93278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_255_WIDTH },
93279 };
93280 
93286 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS] =
93287 {
93288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_0_CHECKER_TYPE,
93289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_0_WIDTH },
93290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_1_CHECKER_TYPE,
93291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_1_WIDTH },
93292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_2_CHECKER_TYPE,
93293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_2_WIDTH },
93294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_3_CHECKER_TYPE,
93295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_3_WIDTH },
93296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_4_CHECKER_TYPE,
93297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_4_WIDTH },
93298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_5_CHECKER_TYPE,
93299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_5_WIDTH },
93300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_6_CHECKER_TYPE,
93301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_6_WIDTH },
93302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_7_CHECKER_TYPE,
93303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_7_WIDTH },
93304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_8_CHECKER_TYPE,
93305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_8_WIDTH },
93306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_9_CHECKER_TYPE,
93307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_9_WIDTH },
93308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_10_CHECKER_TYPE,
93309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_10_WIDTH },
93310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_11_CHECKER_TYPE,
93311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_11_WIDTH },
93312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_12_CHECKER_TYPE,
93313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_12_WIDTH },
93314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_13_CHECKER_TYPE,
93315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_13_WIDTH },
93316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_14_CHECKER_TYPE,
93317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_14_WIDTH },
93318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_15_CHECKER_TYPE,
93319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_15_WIDTH },
93320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_16_CHECKER_TYPE,
93321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_16_WIDTH },
93322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_17_CHECKER_TYPE,
93323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_17_WIDTH },
93324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_18_CHECKER_TYPE,
93325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_18_WIDTH },
93326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_19_CHECKER_TYPE,
93327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_19_WIDTH },
93328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_20_CHECKER_TYPE,
93329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_20_WIDTH },
93330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_21_CHECKER_TYPE,
93331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_21_WIDTH },
93332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_22_CHECKER_TYPE,
93333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_22_WIDTH },
93334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_23_CHECKER_TYPE,
93335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_23_WIDTH },
93336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_24_CHECKER_TYPE,
93337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_24_WIDTH },
93338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_25_CHECKER_TYPE,
93339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_25_WIDTH },
93340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_26_CHECKER_TYPE,
93341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_26_WIDTH },
93342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_27_CHECKER_TYPE,
93343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_27_WIDTH },
93344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_28_CHECKER_TYPE,
93345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_28_WIDTH },
93346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_29_CHECKER_TYPE,
93347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_29_WIDTH },
93348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_30_CHECKER_TYPE,
93349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_30_WIDTH },
93350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_31_CHECKER_TYPE,
93351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_31_WIDTH },
93352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_32_CHECKER_TYPE,
93353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_32_WIDTH },
93354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_33_CHECKER_TYPE,
93355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_33_WIDTH },
93356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_34_CHECKER_TYPE,
93357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_34_WIDTH },
93358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_35_CHECKER_TYPE,
93359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_35_WIDTH },
93360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_36_CHECKER_TYPE,
93361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_36_WIDTH },
93362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_37_CHECKER_TYPE,
93363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_37_WIDTH },
93364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_38_CHECKER_TYPE,
93365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_38_WIDTH },
93366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_39_CHECKER_TYPE,
93367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_39_WIDTH },
93368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_40_CHECKER_TYPE,
93369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_40_WIDTH },
93370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_41_CHECKER_TYPE,
93371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_41_WIDTH },
93372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_42_CHECKER_TYPE,
93373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_42_WIDTH },
93374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_43_CHECKER_TYPE,
93375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_43_WIDTH },
93376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_44_CHECKER_TYPE,
93377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_44_WIDTH },
93378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_45_CHECKER_TYPE,
93379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_45_WIDTH },
93380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_46_CHECKER_TYPE,
93381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_46_WIDTH },
93382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_47_CHECKER_TYPE,
93383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_47_WIDTH },
93384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_48_CHECKER_TYPE,
93385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_48_WIDTH },
93386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_49_CHECKER_TYPE,
93387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_49_WIDTH },
93388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_50_CHECKER_TYPE,
93389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_50_WIDTH },
93390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_51_CHECKER_TYPE,
93391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_51_WIDTH },
93392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_52_CHECKER_TYPE,
93393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_52_WIDTH },
93394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_53_CHECKER_TYPE,
93395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_53_WIDTH },
93396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_54_CHECKER_TYPE,
93397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_54_WIDTH },
93398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_55_CHECKER_TYPE,
93399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_55_WIDTH },
93400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_56_CHECKER_TYPE,
93401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_56_WIDTH },
93402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_57_CHECKER_TYPE,
93403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_57_WIDTH },
93404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_58_CHECKER_TYPE,
93405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_58_WIDTH },
93406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_59_CHECKER_TYPE,
93407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_59_WIDTH },
93408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_60_CHECKER_TYPE,
93409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_60_WIDTH },
93410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_61_CHECKER_TYPE,
93411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_61_WIDTH },
93412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_62_CHECKER_TYPE,
93413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_62_WIDTH },
93414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_63_CHECKER_TYPE,
93415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_63_WIDTH },
93416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_64_CHECKER_TYPE,
93417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_64_WIDTH },
93418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_65_CHECKER_TYPE,
93419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_65_WIDTH },
93420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_66_CHECKER_TYPE,
93421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_66_WIDTH },
93422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_67_CHECKER_TYPE,
93423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_67_WIDTH },
93424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_68_CHECKER_TYPE,
93425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_68_WIDTH },
93426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_69_CHECKER_TYPE,
93427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_69_WIDTH },
93428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_70_CHECKER_TYPE,
93429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_70_WIDTH },
93430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_71_CHECKER_TYPE,
93431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_71_WIDTH },
93432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_72_CHECKER_TYPE,
93433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_72_WIDTH },
93434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_73_CHECKER_TYPE,
93435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_73_WIDTH },
93436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_74_CHECKER_TYPE,
93437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_74_WIDTH },
93438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_75_CHECKER_TYPE,
93439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_75_WIDTH },
93440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_76_CHECKER_TYPE,
93441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_76_WIDTH },
93442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_77_CHECKER_TYPE,
93443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_77_WIDTH },
93444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_78_CHECKER_TYPE,
93445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_78_WIDTH },
93446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_79_CHECKER_TYPE,
93447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_79_WIDTH },
93448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_80_CHECKER_TYPE,
93449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_80_WIDTH },
93450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_81_CHECKER_TYPE,
93451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_81_WIDTH },
93452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_82_CHECKER_TYPE,
93453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_82_WIDTH },
93454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_83_CHECKER_TYPE,
93455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_83_WIDTH },
93456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_84_CHECKER_TYPE,
93457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_84_WIDTH },
93458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_85_CHECKER_TYPE,
93459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_85_WIDTH },
93460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_86_CHECKER_TYPE,
93461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_86_WIDTH },
93462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_87_CHECKER_TYPE,
93463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_87_WIDTH },
93464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_88_CHECKER_TYPE,
93465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_88_WIDTH },
93466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_89_CHECKER_TYPE,
93467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_89_WIDTH },
93468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_90_CHECKER_TYPE,
93469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_90_WIDTH },
93470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_91_CHECKER_TYPE,
93471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_91_WIDTH },
93472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_92_CHECKER_TYPE,
93473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_92_WIDTH },
93474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_93_CHECKER_TYPE,
93475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_93_WIDTH },
93476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_94_CHECKER_TYPE,
93477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_94_WIDTH },
93478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_95_CHECKER_TYPE,
93479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_95_WIDTH },
93480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_96_CHECKER_TYPE,
93481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_96_WIDTH },
93482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_97_CHECKER_TYPE,
93483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_97_WIDTH },
93484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_98_CHECKER_TYPE,
93485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_98_WIDTH },
93486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_99_CHECKER_TYPE,
93487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_99_WIDTH },
93488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_100_CHECKER_TYPE,
93489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_100_WIDTH },
93490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_101_CHECKER_TYPE,
93491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_101_WIDTH },
93492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_102_CHECKER_TYPE,
93493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_102_WIDTH },
93494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_103_CHECKER_TYPE,
93495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_103_WIDTH },
93496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_104_CHECKER_TYPE,
93497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_104_WIDTH },
93498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_105_CHECKER_TYPE,
93499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_105_WIDTH },
93500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_106_CHECKER_TYPE,
93501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_106_WIDTH },
93502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_107_CHECKER_TYPE,
93503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_107_WIDTH },
93504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_108_CHECKER_TYPE,
93505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_108_WIDTH },
93506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_109_CHECKER_TYPE,
93507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_109_WIDTH },
93508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_110_CHECKER_TYPE,
93509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_110_WIDTH },
93510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_111_CHECKER_TYPE,
93511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_111_WIDTH },
93512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_112_CHECKER_TYPE,
93513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_112_WIDTH },
93514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_113_CHECKER_TYPE,
93515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_113_WIDTH },
93516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_114_CHECKER_TYPE,
93517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_114_WIDTH },
93518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_115_CHECKER_TYPE,
93519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_115_WIDTH },
93520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_116_CHECKER_TYPE,
93521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_116_WIDTH },
93522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_117_CHECKER_TYPE,
93523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_117_WIDTH },
93524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_118_CHECKER_TYPE,
93525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_118_WIDTH },
93526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_119_CHECKER_TYPE,
93527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_119_WIDTH },
93528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_120_CHECKER_TYPE,
93529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_120_WIDTH },
93530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_121_CHECKER_TYPE,
93531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_121_WIDTH },
93532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_122_CHECKER_TYPE,
93533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_122_WIDTH },
93534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_123_CHECKER_TYPE,
93535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_123_WIDTH },
93536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_124_CHECKER_TYPE,
93537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_124_WIDTH },
93538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_125_CHECKER_TYPE,
93539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_125_WIDTH },
93540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_126_CHECKER_TYPE,
93541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_126_WIDTH },
93542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_127_CHECKER_TYPE,
93543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_127_WIDTH },
93544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_128_CHECKER_TYPE,
93545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_128_WIDTH },
93546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_129_CHECKER_TYPE,
93547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_129_WIDTH },
93548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_130_CHECKER_TYPE,
93549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_130_WIDTH },
93550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_131_CHECKER_TYPE,
93551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_131_WIDTH },
93552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_132_CHECKER_TYPE,
93553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_132_WIDTH },
93554  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_133_CHECKER_TYPE,
93555  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_133_WIDTH },
93556  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_134_CHECKER_TYPE,
93557  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_134_WIDTH },
93558  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_135_CHECKER_TYPE,
93559  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_135_WIDTH },
93560  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_136_CHECKER_TYPE,
93561  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_136_WIDTH },
93562  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_137_CHECKER_TYPE,
93563  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_137_WIDTH },
93564  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_138_CHECKER_TYPE,
93565  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_138_WIDTH },
93566  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_139_CHECKER_TYPE,
93567  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_139_WIDTH },
93568  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_140_CHECKER_TYPE,
93569  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_140_WIDTH },
93570  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_141_CHECKER_TYPE,
93571  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_141_WIDTH },
93572  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_142_CHECKER_TYPE,
93573  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_142_WIDTH },
93574  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_143_CHECKER_TYPE,
93575  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_143_WIDTH },
93576  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_144_CHECKER_TYPE,
93577  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_144_WIDTH },
93578  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_145_CHECKER_TYPE,
93579  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_145_WIDTH },
93580  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_146_CHECKER_TYPE,
93581  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_146_WIDTH },
93582  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_147_CHECKER_TYPE,
93583  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_147_WIDTH },
93584  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_148_CHECKER_TYPE,
93585  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_148_WIDTH },
93586  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_149_CHECKER_TYPE,
93587  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_149_WIDTH },
93588  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_150_CHECKER_TYPE,
93589  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_150_WIDTH },
93590  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_151_CHECKER_TYPE,
93591  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_151_WIDTH },
93592  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_152_CHECKER_TYPE,
93593  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_152_WIDTH },
93594  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_153_CHECKER_TYPE,
93595  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_153_WIDTH },
93596  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_154_CHECKER_TYPE,
93597  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_154_WIDTH },
93598  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_155_CHECKER_TYPE,
93599  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_155_WIDTH },
93600  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_156_CHECKER_TYPE,
93601  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_156_WIDTH },
93602  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_157_CHECKER_TYPE,
93603  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_157_WIDTH },
93604  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_158_CHECKER_TYPE,
93605  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_158_WIDTH },
93606  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_159_CHECKER_TYPE,
93607  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_159_WIDTH },
93608  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_160_CHECKER_TYPE,
93609  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_160_WIDTH },
93610  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_161_CHECKER_TYPE,
93611  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_161_WIDTH },
93612  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_162_CHECKER_TYPE,
93613  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_162_WIDTH },
93614  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_163_CHECKER_TYPE,
93615  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_163_WIDTH },
93616  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_164_CHECKER_TYPE,
93617  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_164_WIDTH },
93618  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_165_CHECKER_TYPE,
93619  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_165_WIDTH },
93620  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_166_CHECKER_TYPE,
93621  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_166_WIDTH },
93622  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_167_CHECKER_TYPE,
93623  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_167_WIDTH },
93624  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_168_CHECKER_TYPE,
93625  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_168_WIDTH },
93626  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_169_CHECKER_TYPE,
93627  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_169_WIDTH },
93628  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_170_CHECKER_TYPE,
93629  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_170_WIDTH },
93630  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_171_CHECKER_TYPE,
93631  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_171_WIDTH },
93632  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_172_CHECKER_TYPE,
93633  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_172_WIDTH },
93634  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_173_CHECKER_TYPE,
93635  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_173_WIDTH },
93636  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_174_CHECKER_TYPE,
93637  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_174_WIDTH },
93638  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_175_CHECKER_TYPE,
93639  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_175_WIDTH },
93640  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_176_CHECKER_TYPE,
93641  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_176_WIDTH },
93642  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_177_CHECKER_TYPE,
93643  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_177_WIDTH },
93644  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_178_CHECKER_TYPE,
93645  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_178_WIDTH },
93646  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_179_CHECKER_TYPE,
93647  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_179_WIDTH },
93648  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_180_CHECKER_TYPE,
93649  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_180_WIDTH },
93650  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_181_CHECKER_TYPE,
93651  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_181_WIDTH },
93652  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_182_CHECKER_TYPE,
93653  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_182_WIDTH },
93654  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_183_CHECKER_TYPE,
93655  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_183_WIDTH },
93656  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_184_CHECKER_TYPE,
93657  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_184_WIDTH },
93658  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_185_CHECKER_TYPE,
93659  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_185_WIDTH },
93660  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_186_CHECKER_TYPE,
93661  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_186_WIDTH },
93662  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_187_CHECKER_TYPE,
93663  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_187_WIDTH },
93664  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_188_CHECKER_TYPE,
93665  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_188_WIDTH },
93666  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_189_CHECKER_TYPE,
93667  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_189_WIDTH },
93668  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_190_CHECKER_TYPE,
93669  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_190_WIDTH },
93670  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_191_CHECKER_TYPE,
93671  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_191_WIDTH },
93672  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_192_CHECKER_TYPE,
93673  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_192_WIDTH },
93674  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_193_CHECKER_TYPE,
93675  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_193_WIDTH },
93676  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_194_CHECKER_TYPE,
93677  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_194_WIDTH },
93678  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_195_CHECKER_TYPE,
93679  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_195_WIDTH },
93680  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_196_CHECKER_TYPE,
93681  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_196_WIDTH },
93682  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_197_CHECKER_TYPE,
93683  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_197_WIDTH },
93684  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_198_CHECKER_TYPE,
93685  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_198_WIDTH },
93686  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_199_CHECKER_TYPE,
93687  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_199_WIDTH },
93688  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_200_CHECKER_TYPE,
93689  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_200_WIDTH },
93690  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_201_CHECKER_TYPE,
93691  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_201_WIDTH },
93692  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_202_CHECKER_TYPE,
93693  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_202_WIDTH },
93694  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_203_CHECKER_TYPE,
93695  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_203_WIDTH },
93696  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_204_CHECKER_TYPE,
93697  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_204_WIDTH },
93698  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_205_CHECKER_TYPE,
93699  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_205_WIDTH },
93700  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_206_CHECKER_TYPE,
93701  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_206_WIDTH },
93702  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_207_CHECKER_TYPE,
93703  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_207_WIDTH },
93704  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_208_CHECKER_TYPE,
93705  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_208_WIDTH },
93706  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_209_CHECKER_TYPE,
93707  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_209_WIDTH },
93708  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_210_CHECKER_TYPE,
93709  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_210_WIDTH },
93710  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_211_CHECKER_TYPE,
93711  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_211_WIDTH },
93712  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_212_CHECKER_TYPE,
93713  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_212_WIDTH },
93714  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_213_CHECKER_TYPE,
93715  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_213_WIDTH },
93716  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_214_CHECKER_TYPE,
93717  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_214_WIDTH },
93718  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_215_CHECKER_TYPE,
93719  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_215_WIDTH },
93720  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_216_CHECKER_TYPE,
93721  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_216_WIDTH },
93722  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_217_CHECKER_TYPE,
93723  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_217_WIDTH },
93724  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_218_CHECKER_TYPE,
93725  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_218_WIDTH },
93726  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_219_CHECKER_TYPE,
93727  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_219_WIDTH },
93728  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_220_CHECKER_TYPE,
93729  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_220_WIDTH },
93730  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_221_CHECKER_TYPE,
93731  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_221_WIDTH },
93732  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_222_CHECKER_TYPE,
93733  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_222_WIDTH },
93734  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_223_CHECKER_TYPE,
93735  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_223_WIDTH },
93736  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_224_CHECKER_TYPE,
93737  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_224_WIDTH },
93738  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_225_CHECKER_TYPE,
93739  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_225_WIDTH },
93740  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_226_CHECKER_TYPE,
93741  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_226_WIDTH },
93742  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_227_CHECKER_TYPE,
93743  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_227_WIDTH },
93744  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_228_CHECKER_TYPE,
93745  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_228_WIDTH },
93746  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_229_CHECKER_TYPE,
93747  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_229_WIDTH },
93748  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_230_CHECKER_TYPE,
93749  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_230_WIDTH },
93750  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_231_CHECKER_TYPE,
93751  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_231_WIDTH },
93752  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_232_CHECKER_TYPE,
93753  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_232_WIDTH },
93754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_233_CHECKER_TYPE,
93755  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_233_WIDTH },
93756  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_234_CHECKER_TYPE,
93757  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_234_WIDTH },
93758  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_235_CHECKER_TYPE,
93759  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_235_WIDTH },
93760  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_236_CHECKER_TYPE,
93761  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_236_WIDTH },
93762  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_237_CHECKER_TYPE,
93763  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_237_WIDTH },
93764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_238_CHECKER_TYPE,
93765  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_238_WIDTH },
93766  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_239_CHECKER_TYPE,
93767  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_239_WIDTH },
93768  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_240_CHECKER_TYPE,
93769  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_240_WIDTH },
93770  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_241_CHECKER_TYPE,
93771  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_241_WIDTH },
93772  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_242_CHECKER_TYPE,
93773  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_242_WIDTH },
93774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_243_CHECKER_TYPE,
93775  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_243_WIDTH },
93776  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_244_CHECKER_TYPE,
93777  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_244_WIDTH },
93778  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_245_CHECKER_TYPE,
93779  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_245_WIDTH },
93780  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_246_CHECKER_TYPE,
93781  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_246_WIDTH },
93782  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_247_CHECKER_TYPE,
93783  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_247_WIDTH },
93784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_248_CHECKER_TYPE,
93785  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_248_WIDTH },
93786  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_249_CHECKER_TYPE,
93787  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_249_WIDTH },
93788  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_250_CHECKER_TYPE,
93789  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_250_WIDTH },
93790  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_251_CHECKER_TYPE,
93791  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_251_WIDTH },
93792  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_252_CHECKER_TYPE,
93793  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_252_WIDTH },
93794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_253_CHECKER_TYPE,
93795  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_253_WIDTH },
93796  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_254_CHECKER_TYPE,
93797  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_254_WIDTH },
93798  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_255_CHECKER_TYPE,
93799  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_255_WIDTH },
93800 };
93801 
93807 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS] =
93808 {
93809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_0_CHECKER_TYPE,
93810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_0_WIDTH },
93811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_1_CHECKER_TYPE,
93812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_1_WIDTH },
93813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_2_CHECKER_TYPE,
93814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_2_WIDTH },
93815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_3_CHECKER_TYPE,
93816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_3_WIDTH },
93817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_4_CHECKER_TYPE,
93818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_4_WIDTH },
93819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_5_CHECKER_TYPE,
93820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_5_WIDTH },
93821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_6_CHECKER_TYPE,
93822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_6_WIDTH },
93823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_7_CHECKER_TYPE,
93824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_7_WIDTH },
93825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_8_CHECKER_TYPE,
93826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_8_WIDTH },
93827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_9_CHECKER_TYPE,
93828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_9_WIDTH },
93829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_10_CHECKER_TYPE,
93830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_10_WIDTH },
93831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_11_CHECKER_TYPE,
93832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_11_WIDTH },
93833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_12_CHECKER_TYPE,
93834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_12_WIDTH },
93835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_13_CHECKER_TYPE,
93836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_13_WIDTH },
93837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_14_CHECKER_TYPE,
93838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_14_WIDTH },
93839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_15_CHECKER_TYPE,
93840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_15_WIDTH },
93841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_16_CHECKER_TYPE,
93842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_16_WIDTH },
93843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_17_CHECKER_TYPE,
93844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_17_WIDTH },
93845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_18_CHECKER_TYPE,
93846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_18_WIDTH },
93847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_19_CHECKER_TYPE,
93848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_19_WIDTH },
93849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_20_CHECKER_TYPE,
93850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_20_WIDTH },
93851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_21_CHECKER_TYPE,
93852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_21_WIDTH },
93853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_22_CHECKER_TYPE,
93854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_22_WIDTH },
93855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_23_CHECKER_TYPE,
93856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_23_WIDTH },
93857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_24_CHECKER_TYPE,
93858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_24_WIDTH },
93859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_25_CHECKER_TYPE,
93860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_25_WIDTH },
93861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_26_CHECKER_TYPE,
93862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_26_WIDTH },
93863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_27_CHECKER_TYPE,
93864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_27_WIDTH },
93865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_28_CHECKER_TYPE,
93866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_28_WIDTH },
93867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_29_CHECKER_TYPE,
93868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_29_WIDTH },
93869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_30_CHECKER_TYPE,
93870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_30_WIDTH },
93871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_31_CHECKER_TYPE,
93872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_31_WIDTH },
93873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_32_CHECKER_TYPE,
93874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_32_WIDTH },
93875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_33_CHECKER_TYPE,
93876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_33_WIDTH },
93877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_34_CHECKER_TYPE,
93878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_34_WIDTH },
93879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_35_CHECKER_TYPE,
93880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_35_WIDTH },
93881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_36_CHECKER_TYPE,
93882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_36_WIDTH },
93883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_37_CHECKER_TYPE,
93884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_37_WIDTH },
93885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_38_CHECKER_TYPE,
93886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_38_WIDTH },
93887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_39_CHECKER_TYPE,
93888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_39_WIDTH },
93889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_40_CHECKER_TYPE,
93890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_40_WIDTH },
93891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_41_CHECKER_TYPE,
93892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_41_WIDTH },
93893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_42_CHECKER_TYPE,
93894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_42_WIDTH },
93895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_43_CHECKER_TYPE,
93896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_43_WIDTH },
93897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_44_CHECKER_TYPE,
93898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_44_WIDTH },
93899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_45_CHECKER_TYPE,
93900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_45_WIDTH },
93901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_46_CHECKER_TYPE,
93902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_46_WIDTH },
93903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_47_CHECKER_TYPE,
93904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_47_WIDTH },
93905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_48_CHECKER_TYPE,
93906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_48_WIDTH },
93907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_49_CHECKER_TYPE,
93908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_49_WIDTH },
93909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_50_CHECKER_TYPE,
93910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_50_WIDTH },
93911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_51_CHECKER_TYPE,
93912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_51_WIDTH },
93913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_52_CHECKER_TYPE,
93914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_52_WIDTH },
93915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_53_CHECKER_TYPE,
93916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_53_WIDTH },
93917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_54_CHECKER_TYPE,
93918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_54_WIDTH },
93919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_55_CHECKER_TYPE,
93920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_55_WIDTH },
93921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_56_CHECKER_TYPE,
93922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_56_WIDTH },
93923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_57_CHECKER_TYPE,
93924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_57_WIDTH },
93925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_58_CHECKER_TYPE,
93926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_58_WIDTH },
93927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_59_CHECKER_TYPE,
93928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_59_WIDTH },
93929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_60_CHECKER_TYPE,
93930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_60_WIDTH },
93931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_61_CHECKER_TYPE,
93932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_61_WIDTH },
93933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_62_CHECKER_TYPE,
93934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_62_WIDTH },
93935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_63_CHECKER_TYPE,
93936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_63_WIDTH },
93937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_64_CHECKER_TYPE,
93938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_64_WIDTH },
93939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_65_CHECKER_TYPE,
93940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_65_WIDTH },
93941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_66_CHECKER_TYPE,
93942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_66_WIDTH },
93943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_67_CHECKER_TYPE,
93944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_67_WIDTH },
93945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_68_CHECKER_TYPE,
93946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_68_WIDTH },
93947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_69_CHECKER_TYPE,
93948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_69_WIDTH },
93949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_70_CHECKER_TYPE,
93950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_70_WIDTH },
93951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_71_CHECKER_TYPE,
93952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_71_WIDTH },
93953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_72_CHECKER_TYPE,
93954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_72_WIDTH },
93955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_73_CHECKER_TYPE,
93956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_73_WIDTH },
93957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_74_CHECKER_TYPE,
93958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_74_WIDTH },
93959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_75_CHECKER_TYPE,
93960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_75_WIDTH },
93961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_76_CHECKER_TYPE,
93962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_76_WIDTH },
93963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_77_CHECKER_TYPE,
93964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_77_WIDTH },
93965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_78_CHECKER_TYPE,
93966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_78_WIDTH },
93967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_79_CHECKER_TYPE,
93968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_79_WIDTH },
93969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_80_CHECKER_TYPE,
93970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_80_WIDTH },
93971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_81_CHECKER_TYPE,
93972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_81_WIDTH },
93973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_82_CHECKER_TYPE,
93974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_82_WIDTH },
93975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_83_CHECKER_TYPE,
93976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_83_WIDTH },
93977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_84_CHECKER_TYPE,
93978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_84_WIDTH },
93979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_85_CHECKER_TYPE,
93980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_85_WIDTH },
93981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_86_CHECKER_TYPE,
93982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_86_WIDTH },
93983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_87_CHECKER_TYPE,
93984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_87_WIDTH },
93985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_88_CHECKER_TYPE,
93986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_88_WIDTH },
93987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_89_CHECKER_TYPE,
93988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_89_WIDTH },
93989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_90_CHECKER_TYPE,
93990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_90_WIDTH },
93991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_91_CHECKER_TYPE,
93992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_91_WIDTH },
93993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_92_CHECKER_TYPE,
93994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_92_WIDTH },
93995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_93_CHECKER_TYPE,
93996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_93_WIDTH },
93997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_94_CHECKER_TYPE,
93998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_94_WIDTH },
93999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_95_CHECKER_TYPE,
94000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_95_WIDTH },
94001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_96_CHECKER_TYPE,
94002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_96_WIDTH },
94003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_97_CHECKER_TYPE,
94004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_97_WIDTH },
94005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_98_CHECKER_TYPE,
94006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_98_WIDTH },
94007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_99_CHECKER_TYPE,
94008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_99_WIDTH },
94009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_100_CHECKER_TYPE,
94010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_100_WIDTH },
94011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_101_CHECKER_TYPE,
94012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_101_WIDTH },
94013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_102_CHECKER_TYPE,
94014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_102_WIDTH },
94015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_103_CHECKER_TYPE,
94016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_103_WIDTH },
94017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_104_CHECKER_TYPE,
94018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_104_WIDTH },
94019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_105_CHECKER_TYPE,
94020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_105_WIDTH },
94021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_106_CHECKER_TYPE,
94022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_106_WIDTH },
94023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_107_CHECKER_TYPE,
94024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_107_WIDTH },
94025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_108_CHECKER_TYPE,
94026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_108_WIDTH },
94027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_109_CHECKER_TYPE,
94028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_109_WIDTH },
94029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_110_CHECKER_TYPE,
94030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_110_WIDTH },
94031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_111_CHECKER_TYPE,
94032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_111_WIDTH },
94033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_112_CHECKER_TYPE,
94034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_112_WIDTH },
94035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_113_CHECKER_TYPE,
94036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_113_WIDTH },
94037  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_114_CHECKER_TYPE,
94038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_114_WIDTH },
94039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_115_CHECKER_TYPE,
94040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_115_WIDTH },
94041  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_116_CHECKER_TYPE,
94042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_116_WIDTH },
94043  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_117_CHECKER_TYPE,
94044  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_117_WIDTH },
94045  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_118_CHECKER_TYPE,
94046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_118_WIDTH },
94047  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_119_CHECKER_TYPE,
94048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_119_WIDTH },
94049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_120_CHECKER_TYPE,
94050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_120_WIDTH },
94051  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_121_CHECKER_TYPE,
94052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_121_WIDTH },
94053  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_122_CHECKER_TYPE,
94054  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_122_WIDTH },
94055  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_123_CHECKER_TYPE,
94056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_123_WIDTH },
94057  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_124_CHECKER_TYPE,
94058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_124_WIDTH },
94059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_125_CHECKER_TYPE,
94060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_125_WIDTH },
94061  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_126_CHECKER_TYPE,
94062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_126_WIDTH },
94063  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_127_CHECKER_TYPE,
94064  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_127_WIDTH },
94065  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_128_CHECKER_TYPE,
94066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_128_WIDTH },
94067  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_129_CHECKER_TYPE,
94068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_129_WIDTH },
94069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_130_CHECKER_TYPE,
94070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_130_WIDTH },
94071  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_131_CHECKER_TYPE,
94072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_131_WIDTH },
94073  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_132_CHECKER_TYPE,
94074  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_132_WIDTH },
94075  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_133_CHECKER_TYPE,
94076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_133_WIDTH },
94077  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_134_CHECKER_TYPE,
94078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_134_WIDTH },
94079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_135_CHECKER_TYPE,
94080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_135_WIDTH },
94081  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_136_CHECKER_TYPE,
94082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_136_WIDTH },
94083  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_137_CHECKER_TYPE,
94084  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_137_WIDTH },
94085  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_138_CHECKER_TYPE,
94086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_138_WIDTH },
94087  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_139_CHECKER_TYPE,
94088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_139_WIDTH },
94089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_140_CHECKER_TYPE,
94090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_140_WIDTH },
94091  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_141_CHECKER_TYPE,
94092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_141_WIDTH },
94093  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_142_CHECKER_TYPE,
94094  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_142_WIDTH },
94095  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_143_CHECKER_TYPE,
94096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_143_WIDTH },
94097  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_144_CHECKER_TYPE,
94098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_144_WIDTH },
94099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_145_CHECKER_TYPE,
94100  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_145_WIDTH },
94101  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_146_CHECKER_TYPE,
94102  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_146_WIDTH },
94103  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_147_CHECKER_TYPE,
94104  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_147_WIDTH },
94105  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_148_CHECKER_TYPE,
94106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_148_WIDTH },
94107  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_149_CHECKER_TYPE,
94108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_149_WIDTH },
94109  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_150_CHECKER_TYPE,
94110  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_150_WIDTH },
94111  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_151_CHECKER_TYPE,
94112  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_151_WIDTH },
94113  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_152_CHECKER_TYPE,
94114  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_152_WIDTH },
94115  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_153_CHECKER_TYPE,
94116  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_153_WIDTH },
94117  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_154_CHECKER_TYPE,
94118  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_154_WIDTH },
94119  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_155_CHECKER_TYPE,
94120  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_155_WIDTH },
94121  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_156_CHECKER_TYPE,
94122  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_156_WIDTH },
94123  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_157_CHECKER_TYPE,
94124  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_157_WIDTH },
94125  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_158_CHECKER_TYPE,
94126  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_158_WIDTH },
94127  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_159_CHECKER_TYPE,
94128  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_159_WIDTH },
94129  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_160_CHECKER_TYPE,
94130  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_160_WIDTH },
94131  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_161_CHECKER_TYPE,
94132  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_161_WIDTH },
94133  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_162_CHECKER_TYPE,
94134  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_162_WIDTH },
94135  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_163_CHECKER_TYPE,
94136  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_163_WIDTH },
94137  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_164_CHECKER_TYPE,
94138  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_164_WIDTH },
94139  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_165_CHECKER_TYPE,
94140  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_165_WIDTH },
94141  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_166_CHECKER_TYPE,
94142  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_166_WIDTH },
94143  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_167_CHECKER_TYPE,
94144  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_167_WIDTH },
94145  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_168_CHECKER_TYPE,
94146  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_168_WIDTH },
94147  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_169_CHECKER_TYPE,
94148  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_169_WIDTH },
94149  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_170_CHECKER_TYPE,
94150  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_170_WIDTH },
94151  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_171_CHECKER_TYPE,
94152  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_171_WIDTH },
94153  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_172_CHECKER_TYPE,
94154  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_172_WIDTH },
94155  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_173_CHECKER_TYPE,
94156  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_173_WIDTH },
94157  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_174_CHECKER_TYPE,
94158  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_174_WIDTH },
94159  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_175_CHECKER_TYPE,
94160  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_175_WIDTH },
94161  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_176_CHECKER_TYPE,
94162  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_176_WIDTH },
94163  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_177_CHECKER_TYPE,
94164  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_177_WIDTH },
94165  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_178_CHECKER_TYPE,
94166  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_178_WIDTH },
94167  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_179_CHECKER_TYPE,
94168  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_179_WIDTH },
94169  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_180_CHECKER_TYPE,
94170  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_180_WIDTH },
94171  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_181_CHECKER_TYPE,
94172  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_181_WIDTH },
94173  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_182_CHECKER_TYPE,
94174  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_182_WIDTH },
94175  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_183_CHECKER_TYPE,
94176  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_183_WIDTH },
94177  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_184_CHECKER_TYPE,
94178  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_184_WIDTH },
94179  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_185_CHECKER_TYPE,
94180  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_185_WIDTH },
94181  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_186_CHECKER_TYPE,
94182  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_186_WIDTH },
94183  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_187_CHECKER_TYPE,
94184  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_187_WIDTH },
94185  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_188_CHECKER_TYPE,
94186  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_188_WIDTH },
94187  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_189_CHECKER_TYPE,
94188  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_189_WIDTH },
94189  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_190_CHECKER_TYPE,
94190  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_190_WIDTH },
94191  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_191_CHECKER_TYPE,
94192  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_191_WIDTH },
94193  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_192_CHECKER_TYPE,
94194  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_192_WIDTH },
94195  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_193_CHECKER_TYPE,
94196  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_193_WIDTH },
94197  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_194_CHECKER_TYPE,
94198  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_194_WIDTH },
94199  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_195_CHECKER_TYPE,
94200  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_195_WIDTH },
94201  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_196_CHECKER_TYPE,
94202  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_196_WIDTH },
94203  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_197_CHECKER_TYPE,
94204  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_197_WIDTH },
94205  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_198_CHECKER_TYPE,
94206  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_198_WIDTH },
94207  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_199_CHECKER_TYPE,
94208  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_199_WIDTH },
94209  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_200_CHECKER_TYPE,
94210  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_200_WIDTH },
94211  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_201_CHECKER_TYPE,
94212  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_201_WIDTH },
94213  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_202_CHECKER_TYPE,
94214  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_202_WIDTH },
94215  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_203_CHECKER_TYPE,
94216  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_203_WIDTH },
94217  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_204_CHECKER_TYPE,
94218  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_204_WIDTH },
94219  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_205_CHECKER_TYPE,
94220  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_205_WIDTH },
94221  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_206_CHECKER_TYPE,
94222  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_206_WIDTH },
94223  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_207_CHECKER_TYPE,
94224  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_207_WIDTH },
94225  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_208_CHECKER_TYPE,
94226  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_208_WIDTH },
94227  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_209_CHECKER_TYPE,
94228  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_209_WIDTH },
94229  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_210_CHECKER_TYPE,
94230  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_210_WIDTH },
94231  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_211_CHECKER_TYPE,
94232  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_211_WIDTH },
94233  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_212_CHECKER_TYPE,
94234  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_212_WIDTH },
94235  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_213_CHECKER_TYPE,
94236  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_213_WIDTH },
94237  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_214_CHECKER_TYPE,
94238  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_214_WIDTH },
94239  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_215_CHECKER_TYPE,
94240  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_215_WIDTH },
94241  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_216_CHECKER_TYPE,
94242  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_216_WIDTH },
94243  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_217_CHECKER_TYPE,
94244  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_217_WIDTH },
94245  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_218_CHECKER_TYPE,
94246  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_218_WIDTH },
94247  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_219_CHECKER_TYPE,
94248  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_219_WIDTH },
94249  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_220_CHECKER_TYPE,
94250  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_220_WIDTH },
94251  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_221_CHECKER_TYPE,
94252  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_221_WIDTH },
94253  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_222_CHECKER_TYPE,
94254  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_222_WIDTH },
94255  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_223_CHECKER_TYPE,
94256  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_223_WIDTH },
94257  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_224_CHECKER_TYPE,
94258  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_224_WIDTH },
94259  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_225_CHECKER_TYPE,
94260  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_225_WIDTH },
94261  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_226_CHECKER_TYPE,
94262  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_226_WIDTH },
94263  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_227_CHECKER_TYPE,
94264  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_227_WIDTH },
94265  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_228_CHECKER_TYPE,
94266  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_228_WIDTH },
94267  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_229_CHECKER_TYPE,
94268  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_229_WIDTH },
94269  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_230_CHECKER_TYPE,
94270  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_230_WIDTH },
94271  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_231_CHECKER_TYPE,
94272  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_231_WIDTH },
94273  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_232_CHECKER_TYPE,
94274  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_232_WIDTH },
94275  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_233_CHECKER_TYPE,
94276  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_233_WIDTH },
94277  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_234_CHECKER_TYPE,
94278  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_234_WIDTH },
94279  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_235_CHECKER_TYPE,
94280  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_235_WIDTH },
94281  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_236_CHECKER_TYPE,
94282  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_236_WIDTH },
94283  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_237_CHECKER_TYPE,
94284  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_237_WIDTH },
94285  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_238_CHECKER_TYPE,
94286  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_238_WIDTH },
94287  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_239_CHECKER_TYPE,
94288  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_239_WIDTH },
94289  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_240_CHECKER_TYPE,
94290  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_240_WIDTH },
94291  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_241_CHECKER_TYPE,
94292  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_241_WIDTH },
94293  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_242_CHECKER_TYPE,
94294  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_242_WIDTH },
94295  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_243_CHECKER_TYPE,
94296  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_243_WIDTH },
94297  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_244_CHECKER_TYPE,
94298  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_244_WIDTH },
94299  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_245_CHECKER_TYPE,
94300  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_245_WIDTH },
94301  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_246_CHECKER_TYPE,
94302  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_246_WIDTH },
94303  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_247_CHECKER_TYPE,
94304  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_247_WIDTH },
94305  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_248_CHECKER_TYPE,
94306  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_248_WIDTH },
94307  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_249_CHECKER_TYPE,
94308  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_249_WIDTH },
94309  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_250_CHECKER_TYPE,
94310  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_250_WIDTH },
94311  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_251_CHECKER_TYPE,
94312  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_251_WIDTH },
94313  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_252_CHECKER_TYPE,
94314  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_252_WIDTH },
94315  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_253_CHECKER_TYPE,
94316  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_253_WIDTH },
94317  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_254_CHECKER_TYPE,
94318  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_254_WIDTH },
94319  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_255_CHECKER_TYPE,
94320  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_255_WIDTH },
94321 };
94322 
94328 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
94329 {
94330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
94331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
94332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
94333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
94334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
94335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
94336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
94337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
94338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
94339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
94340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
94341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
94342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
94343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
94344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
94345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
94346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
94347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
94348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
94349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
94350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
94351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
94352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
94353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
94354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
94355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
94356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
94357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
94358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
94359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
94360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
94361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
94362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
94363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
94364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
94365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
94366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
94367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
94368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
94369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
94370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
94371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
94372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
94373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
94374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
94375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
94376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
94377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
94378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
94379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
94380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
94381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
94382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
94383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
94384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
94385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
94386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
94387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
94388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
94389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
94390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
94391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
94392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
94393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
94394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
94395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
94396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
94397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
94398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
94399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
94400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
94401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
94402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
94403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
94404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
94405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
94406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
94407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
94408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
94409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
94410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
94411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
94412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
94413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
94414 };
94415 
94421 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
94422 {
94423  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
94424  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
94425  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
94426  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
94427  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
94428  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
94429  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
94430  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
94431 };
94432 
94438 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
94439 {
94440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
94441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
94442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
94443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
94444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
94445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
94446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
94447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
94448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
94449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
94450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
94451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
94452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
94453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
94454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
94455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
94456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
94457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
94458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
94459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
94460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
94461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
94462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
94463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
94464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
94465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
94466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
94467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
94468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
94469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
94470 };
94471 
94477 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_MAX_NUM_CHECKERS] =
94478 {
94479  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_0_CHECKER_TYPE,
94480  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_0_WIDTH },
94481  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_1_CHECKER_TYPE,
94482  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_1_WIDTH },
94483  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_2_CHECKER_TYPE,
94484  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_2_WIDTH },
94485  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_3_CHECKER_TYPE,
94486  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_3_WIDTH },
94487  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_4_CHECKER_TYPE,
94488  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_4_WIDTH },
94489  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_5_CHECKER_TYPE,
94490  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_5_WIDTH },
94491  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_6_CHECKER_TYPE,
94492  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_6_WIDTH },
94493  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_7_CHECKER_TYPE,
94494  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_7_WIDTH },
94495  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_8_CHECKER_TYPE,
94496  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_8_WIDTH },
94497  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_9_CHECKER_TYPE,
94498  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_9_WIDTH },
94499  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_10_CHECKER_TYPE,
94500  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_10_WIDTH },
94501  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_11_CHECKER_TYPE,
94502  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_11_WIDTH },
94503  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_12_CHECKER_TYPE,
94504  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_12_WIDTH },
94505  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_13_CHECKER_TYPE,
94506  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_13_WIDTH },
94507  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_14_CHECKER_TYPE,
94508  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_14_WIDTH },
94509  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_15_CHECKER_TYPE,
94510  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_15_WIDTH },
94511  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_16_CHECKER_TYPE,
94512  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_16_WIDTH },
94513  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_17_CHECKER_TYPE,
94514  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_17_WIDTH },
94515  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_18_CHECKER_TYPE,
94516  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_18_WIDTH },
94517  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_19_CHECKER_TYPE,
94518  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_19_WIDTH },
94519  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_20_CHECKER_TYPE,
94520  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_20_WIDTH },
94521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_21_CHECKER_TYPE,
94522  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_21_WIDTH },
94523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_22_CHECKER_TYPE,
94524  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_22_WIDTH },
94525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_23_CHECKER_TYPE,
94526  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_23_WIDTH },
94527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_24_CHECKER_TYPE,
94528  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_24_WIDTH },
94529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_25_CHECKER_TYPE,
94530  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_25_WIDTH },
94531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_26_CHECKER_TYPE,
94532  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_26_WIDTH },
94533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_27_CHECKER_TYPE,
94534  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_27_WIDTH },
94535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_28_CHECKER_TYPE,
94536  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_28_WIDTH },
94537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_29_CHECKER_TYPE,
94538  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_29_WIDTH },
94539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_30_CHECKER_TYPE,
94540  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_30_WIDTH },
94541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_31_CHECKER_TYPE,
94542  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_31_WIDTH },
94543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_32_CHECKER_TYPE,
94544  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_32_WIDTH },
94545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_33_CHECKER_TYPE,
94546  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_33_WIDTH },
94547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_34_CHECKER_TYPE,
94548  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_34_WIDTH },
94549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_35_CHECKER_TYPE,
94550  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_35_WIDTH },
94551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_36_CHECKER_TYPE,
94552  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_36_WIDTH },
94553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_37_CHECKER_TYPE,
94554  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_37_WIDTH },
94555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_38_CHECKER_TYPE,
94556  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_38_WIDTH },
94557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_39_CHECKER_TYPE,
94558  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_39_WIDTH },
94559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_40_CHECKER_TYPE,
94560  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_40_WIDTH },
94561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_41_CHECKER_TYPE,
94562  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_41_WIDTH },
94563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_42_CHECKER_TYPE,
94564  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_42_WIDTH },
94565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_43_CHECKER_TYPE,
94566  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_43_WIDTH },
94567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_44_CHECKER_TYPE,
94568  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_44_WIDTH },
94569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_45_CHECKER_TYPE,
94570  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_45_WIDTH },
94571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_46_CHECKER_TYPE,
94572  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_46_WIDTH },
94573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_47_CHECKER_TYPE,
94574  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_47_WIDTH },
94575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_48_CHECKER_TYPE,
94576  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_48_WIDTH },
94577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_49_CHECKER_TYPE,
94578  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_49_WIDTH },
94579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_50_CHECKER_TYPE,
94580  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_50_WIDTH },
94581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_51_CHECKER_TYPE,
94582  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_51_WIDTH },
94583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_52_CHECKER_TYPE,
94584  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_52_WIDTH },
94585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_53_CHECKER_TYPE,
94586  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_53_WIDTH },
94587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_54_CHECKER_TYPE,
94588  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_54_WIDTH },
94589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_55_CHECKER_TYPE,
94590  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_55_WIDTH },
94591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_56_CHECKER_TYPE,
94592  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_56_WIDTH },
94593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_57_CHECKER_TYPE,
94594  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_57_WIDTH },
94595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_58_CHECKER_TYPE,
94596  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_58_WIDTH },
94597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_59_CHECKER_TYPE,
94598  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_59_WIDTH },
94599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_60_CHECKER_TYPE,
94600  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_60_WIDTH },
94601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_61_CHECKER_TYPE,
94602  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_61_WIDTH },
94603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_62_CHECKER_TYPE,
94604  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_62_WIDTH },
94605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_63_CHECKER_TYPE,
94606  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_63_WIDTH },
94607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_64_CHECKER_TYPE,
94608  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_64_WIDTH },
94609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_65_CHECKER_TYPE,
94610  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_65_WIDTH },
94611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_66_CHECKER_TYPE,
94612  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_66_WIDTH },
94613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_67_CHECKER_TYPE,
94614  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_67_WIDTH },
94615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_68_CHECKER_TYPE,
94616  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_68_WIDTH },
94617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_69_CHECKER_TYPE,
94618  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_69_WIDTH },
94619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_70_CHECKER_TYPE,
94620  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_70_WIDTH },
94621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_71_CHECKER_TYPE,
94622  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_71_WIDTH },
94623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_72_CHECKER_TYPE,
94624  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_72_WIDTH },
94625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_73_CHECKER_TYPE,
94626  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_73_WIDTH },
94627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_74_CHECKER_TYPE,
94628  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_74_WIDTH },
94629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_75_CHECKER_TYPE,
94630  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_75_WIDTH },
94631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_76_CHECKER_TYPE,
94632  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_76_WIDTH },
94633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_77_CHECKER_TYPE,
94634  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_77_WIDTH },
94635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_78_CHECKER_TYPE,
94636  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_78_WIDTH },
94637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_79_CHECKER_TYPE,
94638  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_79_WIDTH },
94639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_80_CHECKER_TYPE,
94640  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_80_WIDTH },
94641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_81_CHECKER_TYPE,
94642  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_81_WIDTH },
94643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_82_CHECKER_TYPE,
94644  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_82_WIDTH },
94645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_83_CHECKER_TYPE,
94646  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_83_WIDTH },
94647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_84_CHECKER_TYPE,
94648  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_84_WIDTH },
94649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_85_CHECKER_TYPE,
94650  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_85_WIDTH },
94651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_86_CHECKER_TYPE,
94652  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_86_WIDTH },
94653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_87_CHECKER_TYPE,
94654  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_87_WIDTH },
94655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_88_CHECKER_TYPE,
94656  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_88_WIDTH },
94657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_89_CHECKER_TYPE,
94658  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_89_WIDTH },
94659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_90_CHECKER_TYPE,
94660  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_90_WIDTH },
94661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_91_CHECKER_TYPE,
94662  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_91_WIDTH },
94663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_92_CHECKER_TYPE,
94664  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_92_WIDTH },
94665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_93_CHECKER_TYPE,
94666  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_93_WIDTH },
94667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_94_CHECKER_TYPE,
94668  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_94_WIDTH },
94669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_95_CHECKER_TYPE,
94670  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_95_WIDTH },
94671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_96_CHECKER_TYPE,
94672  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_96_WIDTH },
94673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_97_CHECKER_TYPE,
94674  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_97_WIDTH },
94675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_98_CHECKER_TYPE,
94676  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_98_WIDTH },
94677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_99_CHECKER_TYPE,
94678  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_99_WIDTH },
94679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_100_CHECKER_TYPE,
94680  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_100_WIDTH },
94681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_101_CHECKER_TYPE,
94682  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_101_WIDTH },
94683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_102_CHECKER_TYPE,
94684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_102_WIDTH },
94685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_103_CHECKER_TYPE,
94686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_103_WIDTH },
94687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_104_CHECKER_TYPE,
94688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_104_WIDTH },
94689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_105_CHECKER_TYPE,
94690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_105_WIDTH },
94691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_106_CHECKER_TYPE,
94692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_106_WIDTH },
94693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_107_CHECKER_TYPE,
94694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_107_WIDTH },
94695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_108_CHECKER_TYPE,
94696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_108_WIDTH },
94697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_109_CHECKER_TYPE,
94698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_109_WIDTH },
94699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_110_CHECKER_TYPE,
94700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_110_WIDTH },
94701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_111_CHECKER_TYPE,
94702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_111_WIDTH },
94703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_112_CHECKER_TYPE,
94704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_112_WIDTH },
94705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_113_CHECKER_TYPE,
94706  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_113_WIDTH },
94707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_114_CHECKER_TYPE,
94708  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_114_WIDTH },
94709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_115_CHECKER_TYPE,
94710  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_115_WIDTH },
94711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_116_CHECKER_TYPE,
94712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_116_WIDTH },
94713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_117_CHECKER_TYPE,
94714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_117_WIDTH },
94715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_118_CHECKER_TYPE,
94716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_118_WIDTH },
94717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_119_CHECKER_TYPE,
94718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_119_WIDTH },
94719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_120_CHECKER_TYPE,
94720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_120_WIDTH },
94721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_121_CHECKER_TYPE,
94722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_121_WIDTH },
94723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_122_CHECKER_TYPE,
94724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_122_WIDTH },
94725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_123_CHECKER_TYPE,
94726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_123_WIDTH },
94727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_124_CHECKER_TYPE,
94728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_124_WIDTH },
94729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_125_CHECKER_TYPE,
94730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_125_WIDTH },
94731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_126_CHECKER_TYPE,
94732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_126_WIDTH },
94733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_127_CHECKER_TYPE,
94734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_127_WIDTH },
94735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_128_CHECKER_TYPE,
94736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_128_WIDTH },
94737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_129_CHECKER_TYPE,
94738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_129_WIDTH },
94739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_130_CHECKER_TYPE,
94740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_130_WIDTH },
94741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_131_CHECKER_TYPE,
94742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_131_WIDTH },
94743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_132_CHECKER_TYPE,
94744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_132_WIDTH },
94745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_133_CHECKER_TYPE,
94746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_133_WIDTH },
94747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_134_CHECKER_TYPE,
94748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_134_WIDTH },
94749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_135_CHECKER_TYPE,
94750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_135_WIDTH },
94751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_136_CHECKER_TYPE,
94752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_136_WIDTH },
94753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_137_CHECKER_TYPE,
94754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_137_WIDTH },
94755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_138_CHECKER_TYPE,
94756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_138_WIDTH },
94757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_139_CHECKER_TYPE,
94758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_139_WIDTH },
94759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_140_CHECKER_TYPE,
94760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_140_WIDTH },
94761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_141_CHECKER_TYPE,
94762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_141_WIDTH },
94763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_142_CHECKER_TYPE,
94764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_142_WIDTH },
94765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_143_CHECKER_TYPE,
94766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_143_WIDTH },
94767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_144_CHECKER_TYPE,
94768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_144_WIDTH },
94769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_145_CHECKER_TYPE,
94770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_145_WIDTH },
94771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_146_CHECKER_TYPE,
94772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_146_WIDTH },
94773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_147_CHECKER_TYPE,
94774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_147_WIDTH },
94775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_148_CHECKER_TYPE,
94776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_148_WIDTH },
94777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_149_CHECKER_TYPE,
94778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_149_WIDTH },
94779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_150_CHECKER_TYPE,
94780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_150_WIDTH },
94781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_151_CHECKER_TYPE,
94782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_151_WIDTH },
94783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_152_CHECKER_TYPE,
94784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_152_WIDTH },
94785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_153_CHECKER_TYPE,
94786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_153_WIDTH },
94787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_154_CHECKER_TYPE,
94788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_154_WIDTH },
94789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_155_CHECKER_TYPE,
94790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_155_WIDTH },
94791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_156_CHECKER_TYPE,
94792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_156_WIDTH },
94793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_157_CHECKER_TYPE,
94794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_157_WIDTH },
94795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_158_CHECKER_TYPE,
94796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_158_WIDTH },
94797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_159_CHECKER_TYPE,
94798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_159_WIDTH },
94799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_160_CHECKER_TYPE,
94800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_160_WIDTH },
94801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_161_CHECKER_TYPE,
94802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_161_WIDTH },
94803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_162_CHECKER_TYPE,
94804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_162_WIDTH },
94805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_163_CHECKER_TYPE,
94806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_163_WIDTH },
94807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_164_CHECKER_TYPE,
94808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_164_WIDTH },
94809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_165_CHECKER_TYPE,
94810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_165_WIDTH },
94811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_166_CHECKER_TYPE,
94812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_166_WIDTH },
94813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_167_CHECKER_TYPE,
94814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_167_WIDTH },
94815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_168_CHECKER_TYPE,
94816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_168_WIDTH },
94817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_169_CHECKER_TYPE,
94818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_169_WIDTH },
94819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_170_CHECKER_TYPE,
94820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_170_WIDTH },
94821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_171_CHECKER_TYPE,
94822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_171_WIDTH },
94823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_172_CHECKER_TYPE,
94824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_172_WIDTH },
94825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_173_CHECKER_TYPE,
94826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_173_WIDTH },
94827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_174_CHECKER_TYPE,
94828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_174_WIDTH },
94829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_175_CHECKER_TYPE,
94830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_175_WIDTH },
94831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_176_CHECKER_TYPE,
94832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_176_WIDTH },
94833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_177_CHECKER_TYPE,
94834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_177_WIDTH },
94835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_178_CHECKER_TYPE,
94836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_178_WIDTH },
94837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_179_CHECKER_TYPE,
94838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_179_WIDTH },
94839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_180_CHECKER_TYPE,
94840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_180_WIDTH },
94841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_181_CHECKER_TYPE,
94842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_181_WIDTH },
94843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_182_CHECKER_TYPE,
94844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_182_WIDTH },
94845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_183_CHECKER_TYPE,
94846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_183_WIDTH },
94847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_184_CHECKER_TYPE,
94848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_184_WIDTH },
94849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_185_CHECKER_TYPE,
94850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_185_WIDTH },
94851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_186_CHECKER_TYPE,
94852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_186_WIDTH },
94853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_187_CHECKER_TYPE,
94854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_187_WIDTH },
94855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_188_CHECKER_TYPE,
94856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_188_WIDTH },
94857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_189_CHECKER_TYPE,
94858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_189_WIDTH },
94859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_190_CHECKER_TYPE,
94860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_190_WIDTH },
94861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_191_CHECKER_TYPE,
94862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_191_WIDTH },
94863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_192_CHECKER_TYPE,
94864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_192_WIDTH },
94865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_193_CHECKER_TYPE,
94866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_193_WIDTH },
94867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_194_CHECKER_TYPE,
94868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_194_WIDTH },
94869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_195_CHECKER_TYPE,
94870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_195_WIDTH },
94871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_196_CHECKER_TYPE,
94872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_196_WIDTH },
94873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_197_CHECKER_TYPE,
94874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_197_WIDTH },
94875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_198_CHECKER_TYPE,
94876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_198_WIDTH },
94877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_199_CHECKER_TYPE,
94878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_199_WIDTH },
94879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_200_CHECKER_TYPE,
94880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_200_WIDTH },
94881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_201_CHECKER_TYPE,
94882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_201_WIDTH },
94883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_202_CHECKER_TYPE,
94884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_202_WIDTH },
94885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_203_CHECKER_TYPE,
94886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_203_WIDTH },
94887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_204_CHECKER_TYPE,
94888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_204_WIDTH },
94889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_205_CHECKER_TYPE,
94890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_205_WIDTH },
94891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_206_CHECKER_TYPE,
94892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_206_WIDTH },
94893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_207_CHECKER_TYPE,
94894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_207_WIDTH },
94895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_208_CHECKER_TYPE,
94896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_208_WIDTH },
94897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_209_CHECKER_TYPE,
94898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_209_WIDTH },
94899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_210_CHECKER_TYPE,
94900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_210_WIDTH },
94901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_211_CHECKER_TYPE,
94902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_211_WIDTH },
94903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_212_CHECKER_TYPE,
94904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_212_WIDTH },
94905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_213_CHECKER_TYPE,
94906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_213_WIDTH },
94907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_214_CHECKER_TYPE,
94908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_214_WIDTH },
94909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_215_CHECKER_TYPE,
94910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_215_WIDTH },
94911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_216_CHECKER_TYPE,
94912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_216_WIDTH },
94913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_217_CHECKER_TYPE,
94914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_217_WIDTH },
94915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_218_CHECKER_TYPE,
94916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_218_WIDTH },
94917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_219_CHECKER_TYPE,
94918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_219_WIDTH },
94919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_220_CHECKER_TYPE,
94920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_220_WIDTH },
94921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_221_CHECKER_TYPE,
94922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_221_WIDTH },
94923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_222_CHECKER_TYPE,
94924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_222_WIDTH },
94925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_223_CHECKER_TYPE,
94926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_223_WIDTH },
94927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_224_CHECKER_TYPE,
94928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_224_WIDTH },
94929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_225_CHECKER_TYPE,
94930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_225_WIDTH },
94931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_226_CHECKER_TYPE,
94932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_226_WIDTH },
94933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_227_CHECKER_TYPE,
94934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_227_WIDTH },
94935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_228_CHECKER_TYPE,
94936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_228_WIDTH },
94937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_229_CHECKER_TYPE,
94938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_229_WIDTH },
94939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_230_CHECKER_TYPE,
94940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_230_WIDTH },
94941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_231_CHECKER_TYPE,
94942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_231_WIDTH },
94943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_232_CHECKER_TYPE,
94944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_232_WIDTH },
94945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_233_CHECKER_TYPE,
94946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_233_WIDTH },
94947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_234_CHECKER_TYPE,
94948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_234_WIDTH },
94949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_235_CHECKER_TYPE,
94950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_235_WIDTH },
94951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_236_CHECKER_TYPE,
94952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_236_WIDTH },
94953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_237_CHECKER_TYPE,
94954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_237_WIDTH },
94955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_238_CHECKER_TYPE,
94956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_238_WIDTH },
94957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_239_CHECKER_TYPE,
94958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_239_WIDTH },
94959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_240_CHECKER_TYPE,
94960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_240_WIDTH },
94961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_241_CHECKER_TYPE,
94962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_241_WIDTH },
94963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_242_CHECKER_TYPE,
94964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_242_WIDTH },
94965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_243_CHECKER_TYPE,
94966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_243_WIDTH },
94967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_244_CHECKER_TYPE,
94968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_244_WIDTH },
94969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_245_CHECKER_TYPE,
94970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_245_WIDTH },
94971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_246_CHECKER_TYPE,
94972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_246_WIDTH },
94973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_247_CHECKER_TYPE,
94974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_247_WIDTH },
94975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_248_CHECKER_TYPE,
94976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_248_WIDTH },
94977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_249_CHECKER_TYPE,
94978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_249_WIDTH },
94979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_250_CHECKER_TYPE,
94980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_250_WIDTH },
94981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_251_CHECKER_TYPE,
94982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_251_WIDTH },
94983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_252_CHECKER_TYPE,
94984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_252_WIDTH },
94985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_253_CHECKER_TYPE,
94986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_253_WIDTH },
94987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_254_CHECKER_TYPE,
94988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_254_WIDTH },
94989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_255_CHECKER_TYPE,
94990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_GROUP_255_WIDTH },
94991 };
94992 
94998 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_MAX_NUM_CHECKERS] =
94999 {
95000  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_0_CHECKER_TYPE,
95001  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_0_WIDTH },
95002  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_1_CHECKER_TYPE,
95003  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_1_WIDTH },
95004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_2_CHECKER_TYPE,
95005  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_2_WIDTH },
95006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_3_CHECKER_TYPE,
95007  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_3_WIDTH },
95008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_4_CHECKER_TYPE,
95009  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_4_WIDTH },
95010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_5_CHECKER_TYPE,
95011  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_5_WIDTH },
95012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_6_CHECKER_TYPE,
95013  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_6_WIDTH },
95014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_7_CHECKER_TYPE,
95015  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_7_WIDTH },
95016  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_8_CHECKER_TYPE,
95017  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_8_WIDTH },
95018  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_9_CHECKER_TYPE,
95019  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_9_WIDTH },
95020  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_10_CHECKER_TYPE,
95021  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_10_WIDTH },
95022  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_11_CHECKER_TYPE,
95023  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_11_WIDTH },
95024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_12_CHECKER_TYPE,
95025  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_12_WIDTH },
95026  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_13_CHECKER_TYPE,
95027  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_13_WIDTH },
95028  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_14_CHECKER_TYPE,
95029  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_14_WIDTH },
95030  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_15_CHECKER_TYPE,
95031  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_15_WIDTH },
95032  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_16_CHECKER_TYPE,
95033  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_16_WIDTH },
95034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_17_CHECKER_TYPE,
95035  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_17_WIDTH },
95036  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_18_CHECKER_TYPE,
95037  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_18_WIDTH },
95038  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_19_CHECKER_TYPE,
95039  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_19_WIDTH },
95040  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_20_CHECKER_TYPE,
95041  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_20_WIDTH },
95042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_21_CHECKER_TYPE,
95043  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_21_WIDTH },
95044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_22_CHECKER_TYPE,
95045  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_22_WIDTH },
95046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_23_CHECKER_TYPE,
95047  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_23_WIDTH },
95048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_24_CHECKER_TYPE,
95049  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_24_WIDTH },
95050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_25_CHECKER_TYPE,
95051  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_25_WIDTH },
95052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_26_CHECKER_TYPE,
95053  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_26_WIDTH },
95054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_27_CHECKER_TYPE,
95055  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_27_WIDTH },
95056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_28_CHECKER_TYPE,
95057  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_28_WIDTH },
95058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_29_CHECKER_TYPE,
95059  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_29_WIDTH },
95060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_30_CHECKER_TYPE,
95061  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_30_WIDTH },
95062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_31_CHECKER_TYPE,
95063  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_31_WIDTH },
95064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_32_CHECKER_TYPE,
95065  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_32_WIDTH },
95066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_33_CHECKER_TYPE,
95067  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_33_WIDTH },
95068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_34_CHECKER_TYPE,
95069  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_34_WIDTH },
95070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_35_CHECKER_TYPE,
95071  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_35_WIDTH },
95072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_36_CHECKER_TYPE,
95073  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_36_WIDTH },
95074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_37_CHECKER_TYPE,
95075  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_37_WIDTH },
95076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_38_CHECKER_TYPE,
95077  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_38_WIDTH },
95078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_39_CHECKER_TYPE,
95079  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_39_WIDTH },
95080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_40_CHECKER_TYPE,
95081  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_40_WIDTH },
95082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_41_CHECKER_TYPE,
95083  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_41_WIDTH },
95084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_42_CHECKER_TYPE,
95085  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_42_WIDTH },
95086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_43_CHECKER_TYPE,
95087  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_43_WIDTH },
95088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_44_CHECKER_TYPE,
95089  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_44_WIDTH },
95090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_45_CHECKER_TYPE,
95091  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_45_WIDTH },
95092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_46_CHECKER_TYPE,
95093  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_46_WIDTH },
95094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_47_CHECKER_TYPE,
95095  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_47_WIDTH },
95096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_48_CHECKER_TYPE,
95097  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_48_WIDTH },
95098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_49_CHECKER_TYPE,
95099  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_49_WIDTH },
95100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_50_CHECKER_TYPE,
95101  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_50_WIDTH },
95102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_51_CHECKER_TYPE,
95103  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_51_WIDTH },
95104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_52_CHECKER_TYPE,
95105  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_52_WIDTH },
95106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_53_CHECKER_TYPE,
95107  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_53_WIDTH },
95108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_54_CHECKER_TYPE,
95109  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_54_WIDTH },
95110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_55_CHECKER_TYPE,
95111  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_55_WIDTH },
95112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_56_CHECKER_TYPE,
95113  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_56_WIDTH },
95114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_57_CHECKER_TYPE,
95115  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_57_WIDTH },
95116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_58_CHECKER_TYPE,
95117  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_58_WIDTH },
95118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_59_CHECKER_TYPE,
95119  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_59_WIDTH },
95120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_60_CHECKER_TYPE,
95121  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_60_WIDTH },
95122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_61_CHECKER_TYPE,
95123  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_61_WIDTH },
95124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_62_CHECKER_TYPE,
95125  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_62_WIDTH },
95126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_63_CHECKER_TYPE,
95127  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_63_WIDTH },
95128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_64_CHECKER_TYPE,
95129  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_64_WIDTH },
95130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_65_CHECKER_TYPE,
95131  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_65_WIDTH },
95132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_66_CHECKER_TYPE,
95133  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_66_WIDTH },
95134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_67_CHECKER_TYPE,
95135  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_67_WIDTH },
95136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_68_CHECKER_TYPE,
95137  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_68_WIDTH },
95138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_69_CHECKER_TYPE,
95139  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_69_WIDTH },
95140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_70_CHECKER_TYPE,
95141  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_70_WIDTH },
95142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_71_CHECKER_TYPE,
95143  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_71_WIDTH },
95144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_72_CHECKER_TYPE,
95145  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_72_WIDTH },
95146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_73_CHECKER_TYPE,
95147  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_73_WIDTH },
95148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_74_CHECKER_TYPE,
95149  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_74_WIDTH },
95150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_75_CHECKER_TYPE,
95151  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_75_WIDTH },
95152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_76_CHECKER_TYPE,
95153  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_76_WIDTH },
95154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_77_CHECKER_TYPE,
95155  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_77_WIDTH },
95156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_78_CHECKER_TYPE,
95157  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_78_WIDTH },
95158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_79_CHECKER_TYPE,
95159  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_79_WIDTH },
95160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_80_CHECKER_TYPE,
95161  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_80_WIDTH },
95162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_81_CHECKER_TYPE,
95163  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_81_WIDTH },
95164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_82_CHECKER_TYPE,
95165  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_82_WIDTH },
95166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_83_CHECKER_TYPE,
95167  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_83_WIDTH },
95168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_84_CHECKER_TYPE,
95169  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_84_WIDTH },
95170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_85_CHECKER_TYPE,
95171  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_85_WIDTH },
95172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_86_CHECKER_TYPE,
95173  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_86_WIDTH },
95174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_87_CHECKER_TYPE,
95175  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_87_WIDTH },
95176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_88_CHECKER_TYPE,
95177  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_88_WIDTH },
95178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_89_CHECKER_TYPE,
95179  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_89_WIDTH },
95180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_90_CHECKER_TYPE,
95181  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_90_WIDTH },
95182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_91_CHECKER_TYPE,
95183  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_91_WIDTH },
95184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_92_CHECKER_TYPE,
95185  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_92_WIDTH },
95186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_93_CHECKER_TYPE,
95187  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_93_WIDTH },
95188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_94_CHECKER_TYPE,
95189  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_94_WIDTH },
95190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_95_CHECKER_TYPE,
95191  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_95_WIDTH },
95192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_96_CHECKER_TYPE,
95193  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_96_WIDTH },
95194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_97_CHECKER_TYPE,
95195  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_97_WIDTH },
95196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_98_CHECKER_TYPE,
95197  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_98_WIDTH },
95198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_99_CHECKER_TYPE,
95199  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_99_WIDTH },
95200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_100_CHECKER_TYPE,
95201  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_100_WIDTH },
95202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_101_CHECKER_TYPE,
95203  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_101_WIDTH },
95204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_102_CHECKER_TYPE,
95205  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_102_WIDTH },
95206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_103_CHECKER_TYPE,
95207  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_103_WIDTH },
95208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_104_CHECKER_TYPE,
95209  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_104_WIDTH },
95210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_105_CHECKER_TYPE,
95211  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_105_WIDTH },
95212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_106_CHECKER_TYPE,
95213  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_106_WIDTH },
95214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_107_CHECKER_TYPE,
95215  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_107_WIDTH },
95216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_108_CHECKER_TYPE,
95217  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_108_WIDTH },
95218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_109_CHECKER_TYPE,
95219  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_109_WIDTH },
95220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_110_CHECKER_TYPE,
95221  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_110_WIDTH },
95222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_111_CHECKER_TYPE,
95223  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_111_WIDTH },
95224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_112_CHECKER_TYPE,
95225  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_112_WIDTH },
95226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_113_CHECKER_TYPE,
95227  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_113_WIDTH },
95228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_114_CHECKER_TYPE,
95229  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_114_WIDTH },
95230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_115_CHECKER_TYPE,
95231  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_115_WIDTH },
95232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_116_CHECKER_TYPE,
95233  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_116_WIDTH },
95234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_117_CHECKER_TYPE,
95235  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_117_WIDTH },
95236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_118_CHECKER_TYPE,
95237  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_118_WIDTH },
95238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_119_CHECKER_TYPE,
95239  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_119_WIDTH },
95240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_120_CHECKER_TYPE,
95241  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_120_WIDTH },
95242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_121_CHECKER_TYPE,
95243  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_121_WIDTH },
95244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_122_CHECKER_TYPE,
95245  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_122_WIDTH },
95246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_123_CHECKER_TYPE,
95247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_123_WIDTH },
95248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_124_CHECKER_TYPE,
95249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_124_WIDTH },
95250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_125_CHECKER_TYPE,
95251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_125_WIDTH },
95252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_126_CHECKER_TYPE,
95253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_126_WIDTH },
95254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_127_CHECKER_TYPE,
95255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_127_WIDTH },
95256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_128_CHECKER_TYPE,
95257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_128_WIDTH },
95258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_129_CHECKER_TYPE,
95259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_129_WIDTH },
95260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_130_CHECKER_TYPE,
95261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_130_WIDTH },
95262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_131_CHECKER_TYPE,
95263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_131_WIDTH },
95264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_132_CHECKER_TYPE,
95265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_132_WIDTH },
95266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_133_CHECKER_TYPE,
95267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_133_WIDTH },
95268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_134_CHECKER_TYPE,
95269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_134_WIDTH },
95270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_135_CHECKER_TYPE,
95271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_135_WIDTH },
95272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_136_CHECKER_TYPE,
95273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_136_WIDTH },
95274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_137_CHECKER_TYPE,
95275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_137_WIDTH },
95276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_138_CHECKER_TYPE,
95277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_138_WIDTH },
95278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_139_CHECKER_TYPE,
95279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_139_WIDTH },
95280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_140_CHECKER_TYPE,
95281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_140_WIDTH },
95282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_141_CHECKER_TYPE,
95283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_141_WIDTH },
95284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_142_CHECKER_TYPE,
95285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_142_WIDTH },
95286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_143_CHECKER_TYPE,
95287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_143_WIDTH },
95288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_144_CHECKER_TYPE,
95289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_144_WIDTH },
95290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_145_CHECKER_TYPE,
95291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_145_WIDTH },
95292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_146_CHECKER_TYPE,
95293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_146_WIDTH },
95294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_147_CHECKER_TYPE,
95295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_147_WIDTH },
95296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_148_CHECKER_TYPE,
95297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_148_WIDTH },
95298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_149_CHECKER_TYPE,
95299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_149_WIDTH },
95300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_150_CHECKER_TYPE,
95301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_150_WIDTH },
95302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_151_CHECKER_TYPE,
95303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_151_WIDTH },
95304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_152_CHECKER_TYPE,
95305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_152_WIDTH },
95306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_153_CHECKER_TYPE,
95307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_153_WIDTH },
95308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_154_CHECKER_TYPE,
95309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_154_WIDTH },
95310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_155_CHECKER_TYPE,
95311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_155_WIDTH },
95312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_156_CHECKER_TYPE,
95313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_156_WIDTH },
95314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_157_CHECKER_TYPE,
95315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_157_WIDTH },
95316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_158_CHECKER_TYPE,
95317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_158_WIDTH },
95318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_159_CHECKER_TYPE,
95319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_159_WIDTH },
95320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_160_CHECKER_TYPE,
95321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_160_WIDTH },
95322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_161_CHECKER_TYPE,
95323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_161_WIDTH },
95324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_162_CHECKER_TYPE,
95325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_162_WIDTH },
95326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_163_CHECKER_TYPE,
95327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_163_WIDTH },
95328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_164_CHECKER_TYPE,
95329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_164_WIDTH },
95330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_165_CHECKER_TYPE,
95331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_165_WIDTH },
95332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_166_CHECKER_TYPE,
95333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_166_WIDTH },
95334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_167_CHECKER_TYPE,
95335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_167_WIDTH },
95336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_168_CHECKER_TYPE,
95337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_168_WIDTH },
95338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_169_CHECKER_TYPE,
95339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_169_WIDTH },
95340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_170_CHECKER_TYPE,
95341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_170_WIDTH },
95342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_171_CHECKER_TYPE,
95343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_171_WIDTH },
95344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_172_CHECKER_TYPE,
95345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_172_WIDTH },
95346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_173_CHECKER_TYPE,
95347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_173_WIDTH },
95348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_174_CHECKER_TYPE,
95349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_174_WIDTH },
95350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_175_CHECKER_TYPE,
95351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_175_WIDTH },
95352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_176_CHECKER_TYPE,
95353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_176_WIDTH },
95354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_177_CHECKER_TYPE,
95355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_177_WIDTH },
95356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_178_CHECKER_TYPE,
95357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_178_WIDTH },
95358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_179_CHECKER_TYPE,
95359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_179_WIDTH },
95360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_180_CHECKER_TYPE,
95361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_180_WIDTH },
95362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_181_CHECKER_TYPE,
95363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_181_WIDTH },
95364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_182_CHECKER_TYPE,
95365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_182_WIDTH },
95366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_183_CHECKER_TYPE,
95367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_183_WIDTH },
95368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_184_CHECKER_TYPE,
95369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_184_WIDTH },
95370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_185_CHECKER_TYPE,
95371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_185_WIDTH },
95372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_186_CHECKER_TYPE,
95373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_186_WIDTH },
95374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_187_CHECKER_TYPE,
95375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_187_WIDTH },
95376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_188_CHECKER_TYPE,
95377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_188_WIDTH },
95378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_189_CHECKER_TYPE,
95379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_189_WIDTH },
95380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_190_CHECKER_TYPE,
95381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_190_WIDTH },
95382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_191_CHECKER_TYPE,
95383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_191_WIDTH },
95384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_192_CHECKER_TYPE,
95385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_192_WIDTH },
95386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_193_CHECKER_TYPE,
95387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_193_WIDTH },
95388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_194_CHECKER_TYPE,
95389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_194_WIDTH },
95390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_195_CHECKER_TYPE,
95391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_195_WIDTH },
95392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_196_CHECKER_TYPE,
95393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_196_WIDTH },
95394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_197_CHECKER_TYPE,
95395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_197_WIDTH },
95396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_198_CHECKER_TYPE,
95397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_198_WIDTH },
95398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_199_CHECKER_TYPE,
95399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_199_WIDTH },
95400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_200_CHECKER_TYPE,
95401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_200_WIDTH },
95402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_201_CHECKER_TYPE,
95403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_201_WIDTH },
95404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_202_CHECKER_TYPE,
95405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_202_WIDTH },
95406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_203_CHECKER_TYPE,
95407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_203_WIDTH },
95408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_204_CHECKER_TYPE,
95409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_204_WIDTH },
95410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_205_CHECKER_TYPE,
95411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_205_WIDTH },
95412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_206_CHECKER_TYPE,
95413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_206_WIDTH },
95414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_207_CHECKER_TYPE,
95415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_207_WIDTH },
95416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_208_CHECKER_TYPE,
95417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_208_WIDTH },
95418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_209_CHECKER_TYPE,
95419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_209_WIDTH },
95420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_210_CHECKER_TYPE,
95421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_210_WIDTH },
95422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_211_CHECKER_TYPE,
95423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_211_WIDTH },
95424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_212_CHECKER_TYPE,
95425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_212_WIDTH },
95426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_213_CHECKER_TYPE,
95427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_213_WIDTH },
95428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_214_CHECKER_TYPE,
95429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_214_WIDTH },
95430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_215_CHECKER_TYPE,
95431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_215_WIDTH },
95432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_216_CHECKER_TYPE,
95433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_216_WIDTH },
95434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_217_CHECKER_TYPE,
95435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_217_WIDTH },
95436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_218_CHECKER_TYPE,
95437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_218_WIDTH },
95438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_219_CHECKER_TYPE,
95439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_219_WIDTH },
95440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_220_CHECKER_TYPE,
95441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_220_WIDTH },
95442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_221_CHECKER_TYPE,
95443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_221_WIDTH },
95444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_222_CHECKER_TYPE,
95445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_222_WIDTH },
95446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_223_CHECKER_TYPE,
95447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_223_WIDTH },
95448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_224_CHECKER_TYPE,
95449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_224_WIDTH },
95450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_225_CHECKER_TYPE,
95451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_225_WIDTH },
95452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_226_CHECKER_TYPE,
95453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_226_WIDTH },
95454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_227_CHECKER_TYPE,
95455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_227_WIDTH },
95456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_228_CHECKER_TYPE,
95457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_228_WIDTH },
95458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_229_CHECKER_TYPE,
95459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_229_WIDTH },
95460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_230_CHECKER_TYPE,
95461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_230_WIDTH },
95462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_231_CHECKER_TYPE,
95463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_231_WIDTH },
95464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_232_CHECKER_TYPE,
95465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_232_WIDTH },
95466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_233_CHECKER_TYPE,
95467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_233_WIDTH },
95468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_234_CHECKER_TYPE,
95469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_234_WIDTH },
95470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_235_CHECKER_TYPE,
95471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_235_WIDTH },
95472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_236_CHECKER_TYPE,
95473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_236_WIDTH },
95474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_237_CHECKER_TYPE,
95475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_237_WIDTH },
95476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_238_CHECKER_TYPE,
95477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_238_WIDTH },
95478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_239_CHECKER_TYPE,
95479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_239_WIDTH },
95480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_240_CHECKER_TYPE,
95481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_240_WIDTH },
95482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_241_CHECKER_TYPE,
95483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_241_WIDTH },
95484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_242_CHECKER_TYPE,
95485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_242_WIDTH },
95486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_243_CHECKER_TYPE,
95487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_243_WIDTH },
95488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_244_CHECKER_TYPE,
95489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_244_WIDTH },
95490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_245_CHECKER_TYPE,
95491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_245_WIDTH },
95492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_246_CHECKER_TYPE,
95493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_246_WIDTH },
95494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_247_CHECKER_TYPE,
95495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_247_WIDTH },
95496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_248_CHECKER_TYPE,
95497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_248_WIDTH },
95498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_249_CHECKER_TYPE,
95499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_249_WIDTH },
95500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_250_CHECKER_TYPE,
95501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_250_WIDTH },
95502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_251_CHECKER_TYPE,
95503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_251_WIDTH },
95504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_252_CHECKER_TYPE,
95505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_252_WIDTH },
95506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_253_CHECKER_TYPE,
95507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_253_WIDTH },
95508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_254_CHECKER_TYPE,
95509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_254_WIDTH },
95510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_255_CHECKER_TYPE,
95511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_GROUP_255_WIDTH },
95512 };
95513 
95519 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_MAX_NUM_CHECKERS] =
95520 {
95521  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_0_CHECKER_TYPE,
95522  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_0_WIDTH },
95523  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_1_CHECKER_TYPE,
95524  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_1_WIDTH },
95525  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_2_CHECKER_TYPE,
95526  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_2_WIDTH },
95527  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_3_CHECKER_TYPE,
95528  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_3_WIDTH },
95529  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_4_CHECKER_TYPE,
95530  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_4_WIDTH },
95531  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_5_CHECKER_TYPE,
95532  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_5_WIDTH },
95533  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_6_CHECKER_TYPE,
95534  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_6_WIDTH },
95535  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_7_CHECKER_TYPE,
95536  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_7_WIDTH },
95537  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_8_CHECKER_TYPE,
95538  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_8_WIDTH },
95539  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_9_CHECKER_TYPE,
95540  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_9_WIDTH },
95541  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_10_CHECKER_TYPE,
95542  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_10_WIDTH },
95543  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_11_CHECKER_TYPE,
95544  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_11_WIDTH },
95545  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_12_CHECKER_TYPE,
95546  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_12_WIDTH },
95547  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_13_CHECKER_TYPE,
95548  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_13_WIDTH },
95549  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_14_CHECKER_TYPE,
95550  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_14_WIDTH },
95551  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_15_CHECKER_TYPE,
95552  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_15_WIDTH },
95553  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_16_CHECKER_TYPE,
95554  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_16_WIDTH },
95555  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_17_CHECKER_TYPE,
95556  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_17_WIDTH },
95557  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_18_CHECKER_TYPE,
95558  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_18_WIDTH },
95559  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_19_CHECKER_TYPE,
95560  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_19_WIDTH },
95561  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_20_CHECKER_TYPE,
95562  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_20_WIDTH },
95563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_21_CHECKER_TYPE,
95564  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_21_WIDTH },
95565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_22_CHECKER_TYPE,
95566  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_22_WIDTH },
95567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_23_CHECKER_TYPE,
95568  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_23_WIDTH },
95569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_24_CHECKER_TYPE,
95570  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_24_WIDTH },
95571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_25_CHECKER_TYPE,
95572  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_25_WIDTH },
95573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_26_CHECKER_TYPE,
95574  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_26_WIDTH },
95575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_27_CHECKER_TYPE,
95576  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_27_WIDTH },
95577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_28_CHECKER_TYPE,
95578  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_28_WIDTH },
95579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_29_CHECKER_TYPE,
95580  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_29_WIDTH },
95581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_30_CHECKER_TYPE,
95582  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_30_WIDTH },
95583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_31_CHECKER_TYPE,
95584  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_31_WIDTH },
95585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_32_CHECKER_TYPE,
95586  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_32_WIDTH },
95587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_33_CHECKER_TYPE,
95588  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_33_WIDTH },
95589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_34_CHECKER_TYPE,
95590  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_34_WIDTH },
95591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_35_CHECKER_TYPE,
95592  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_35_WIDTH },
95593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_36_CHECKER_TYPE,
95594  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_36_WIDTH },
95595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_37_CHECKER_TYPE,
95596  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_37_WIDTH },
95597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_38_CHECKER_TYPE,
95598  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_38_WIDTH },
95599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_39_CHECKER_TYPE,
95600  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_39_WIDTH },
95601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_40_CHECKER_TYPE,
95602  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_40_WIDTH },
95603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_41_CHECKER_TYPE,
95604  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_41_WIDTH },
95605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_42_CHECKER_TYPE,
95606  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_42_WIDTH },
95607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_43_CHECKER_TYPE,
95608  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_43_WIDTH },
95609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_44_CHECKER_TYPE,
95610  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_44_WIDTH },
95611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_45_CHECKER_TYPE,
95612  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_45_WIDTH },
95613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_46_CHECKER_TYPE,
95614  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_46_WIDTH },
95615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_47_CHECKER_TYPE,
95616  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_47_WIDTH },
95617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_48_CHECKER_TYPE,
95618  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_48_WIDTH },
95619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_49_CHECKER_TYPE,
95620  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_49_WIDTH },
95621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_50_CHECKER_TYPE,
95622  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_50_WIDTH },
95623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_51_CHECKER_TYPE,
95624  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_51_WIDTH },
95625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_52_CHECKER_TYPE,
95626  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_52_WIDTH },
95627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_53_CHECKER_TYPE,
95628  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_53_WIDTH },
95629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_54_CHECKER_TYPE,
95630  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_54_WIDTH },
95631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_55_CHECKER_TYPE,
95632  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_55_WIDTH },
95633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_56_CHECKER_TYPE,
95634  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_56_WIDTH },
95635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_57_CHECKER_TYPE,
95636  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_57_WIDTH },
95637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_58_CHECKER_TYPE,
95638  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_58_WIDTH },
95639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_59_CHECKER_TYPE,
95640  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_59_WIDTH },
95641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_60_CHECKER_TYPE,
95642  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_60_WIDTH },
95643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_61_CHECKER_TYPE,
95644  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_61_WIDTH },
95645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_62_CHECKER_TYPE,
95646  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_62_WIDTH },
95647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_63_CHECKER_TYPE,
95648  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_63_WIDTH },
95649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_64_CHECKER_TYPE,
95650  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_64_WIDTH },
95651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_65_CHECKER_TYPE,
95652  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_65_WIDTH },
95653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_66_CHECKER_TYPE,
95654  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_66_WIDTH },
95655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_67_CHECKER_TYPE,
95656  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_67_WIDTH },
95657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_68_CHECKER_TYPE,
95658  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_68_WIDTH },
95659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_69_CHECKER_TYPE,
95660  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_69_WIDTH },
95661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_70_CHECKER_TYPE,
95662  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_70_WIDTH },
95663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_71_CHECKER_TYPE,
95664  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_71_WIDTH },
95665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_72_CHECKER_TYPE,
95666  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_72_WIDTH },
95667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_73_CHECKER_TYPE,
95668  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_73_WIDTH },
95669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_74_CHECKER_TYPE,
95670  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_74_WIDTH },
95671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_75_CHECKER_TYPE,
95672  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_75_WIDTH },
95673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_76_CHECKER_TYPE,
95674  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_76_WIDTH },
95675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_77_CHECKER_TYPE,
95676  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_77_WIDTH },
95677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_78_CHECKER_TYPE,
95678  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_78_WIDTH },
95679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_79_CHECKER_TYPE,
95680  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_79_WIDTH },
95681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_80_CHECKER_TYPE,
95682  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_80_WIDTH },
95683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_81_CHECKER_TYPE,
95684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_81_WIDTH },
95685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_82_CHECKER_TYPE,
95686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_82_WIDTH },
95687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_83_CHECKER_TYPE,
95688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_83_WIDTH },
95689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_84_CHECKER_TYPE,
95690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_84_WIDTH },
95691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_85_CHECKER_TYPE,
95692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_85_WIDTH },
95693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_86_CHECKER_TYPE,
95694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_86_WIDTH },
95695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_87_CHECKER_TYPE,
95696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_87_WIDTH },
95697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_88_CHECKER_TYPE,
95698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_88_WIDTH },
95699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_89_CHECKER_TYPE,
95700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_89_WIDTH },
95701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_90_CHECKER_TYPE,
95702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_90_WIDTH },
95703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_91_CHECKER_TYPE,
95704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_91_WIDTH },
95705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_92_CHECKER_TYPE,
95706  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_92_WIDTH },
95707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_93_CHECKER_TYPE,
95708  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_93_WIDTH },
95709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_94_CHECKER_TYPE,
95710  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_94_WIDTH },
95711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_95_CHECKER_TYPE,
95712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_95_WIDTH },
95713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_96_CHECKER_TYPE,
95714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_96_WIDTH },
95715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_97_CHECKER_TYPE,
95716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_97_WIDTH },
95717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_98_CHECKER_TYPE,
95718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_98_WIDTH },
95719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_99_CHECKER_TYPE,
95720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_99_WIDTH },
95721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_100_CHECKER_TYPE,
95722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_100_WIDTH },
95723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_101_CHECKER_TYPE,
95724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_101_WIDTH },
95725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_102_CHECKER_TYPE,
95726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_102_WIDTH },
95727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_103_CHECKER_TYPE,
95728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_103_WIDTH },
95729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_104_CHECKER_TYPE,
95730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_104_WIDTH },
95731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_105_CHECKER_TYPE,
95732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_105_WIDTH },
95733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_106_CHECKER_TYPE,
95734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_106_WIDTH },
95735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_107_CHECKER_TYPE,
95736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_107_WIDTH },
95737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_108_CHECKER_TYPE,
95738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_108_WIDTH },
95739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_109_CHECKER_TYPE,
95740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_109_WIDTH },
95741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_110_CHECKER_TYPE,
95742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_110_WIDTH },
95743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_111_CHECKER_TYPE,
95744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_111_WIDTH },
95745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_112_CHECKER_TYPE,
95746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_112_WIDTH },
95747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_113_CHECKER_TYPE,
95748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_113_WIDTH },
95749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_114_CHECKER_TYPE,
95750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_114_WIDTH },
95751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_115_CHECKER_TYPE,
95752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_115_WIDTH },
95753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_116_CHECKER_TYPE,
95754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_116_WIDTH },
95755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_117_CHECKER_TYPE,
95756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_117_WIDTH },
95757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_118_CHECKER_TYPE,
95758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_118_WIDTH },
95759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_119_CHECKER_TYPE,
95760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_119_WIDTH },
95761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_120_CHECKER_TYPE,
95762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_120_WIDTH },
95763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_121_CHECKER_TYPE,
95764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_121_WIDTH },
95765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_122_CHECKER_TYPE,
95766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_122_WIDTH },
95767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_123_CHECKER_TYPE,
95768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_123_WIDTH },
95769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_124_CHECKER_TYPE,
95770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_124_WIDTH },
95771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_125_CHECKER_TYPE,
95772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_125_WIDTH },
95773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_126_CHECKER_TYPE,
95774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_126_WIDTH },
95775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_127_CHECKER_TYPE,
95776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_127_WIDTH },
95777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_128_CHECKER_TYPE,
95778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_128_WIDTH },
95779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_129_CHECKER_TYPE,
95780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_129_WIDTH },
95781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_130_CHECKER_TYPE,
95782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_130_WIDTH },
95783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_131_CHECKER_TYPE,
95784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_131_WIDTH },
95785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_132_CHECKER_TYPE,
95786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_132_WIDTH },
95787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_133_CHECKER_TYPE,
95788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_133_WIDTH },
95789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_134_CHECKER_TYPE,
95790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_134_WIDTH },
95791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_135_CHECKER_TYPE,
95792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_135_WIDTH },
95793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_136_CHECKER_TYPE,
95794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_136_WIDTH },
95795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_137_CHECKER_TYPE,
95796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_137_WIDTH },
95797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_138_CHECKER_TYPE,
95798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_138_WIDTH },
95799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_139_CHECKER_TYPE,
95800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_139_WIDTH },
95801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_140_CHECKER_TYPE,
95802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_140_WIDTH },
95803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_141_CHECKER_TYPE,
95804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_141_WIDTH },
95805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_142_CHECKER_TYPE,
95806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_142_WIDTH },
95807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_143_CHECKER_TYPE,
95808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_143_WIDTH },
95809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_144_CHECKER_TYPE,
95810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_144_WIDTH },
95811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_145_CHECKER_TYPE,
95812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_145_WIDTH },
95813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_146_CHECKER_TYPE,
95814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_146_WIDTH },
95815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_147_CHECKER_TYPE,
95816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_147_WIDTH },
95817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_148_CHECKER_TYPE,
95818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_148_WIDTH },
95819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_149_CHECKER_TYPE,
95820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_149_WIDTH },
95821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_150_CHECKER_TYPE,
95822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_150_WIDTH },
95823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_151_CHECKER_TYPE,
95824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_151_WIDTH },
95825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_152_CHECKER_TYPE,
95826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_152_WIDTH },
95827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_153_CHECKER_TYPE,
95828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_153_WIDTH },
95829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_154_CHECKER_TYPE,
95830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_154_WIDTH },
95831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_155_CHECKER_TYPE,
95832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_155_WIDTH },
95833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_156_CHECKER_TYPE,
95834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_156_WIDTH },
95835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_157_CHECKER_TYPE,
95836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_157_WIDTH },
95837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_158_CHECKER_TYPE,
95838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_158_WIDTH },
95839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_159_CHECKER_TYPE,
95840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_159_WIDTH },
95841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_160_CHECKER_TYPE,
95842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_160_WIDTH },
95843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_161_CHECKER_TYPE,
95844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_161_WIDTH },
95845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_162_CHECKER_TYPE,
95846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_162_WIDTH },
95847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_163_CHECKER_TYPE,
95848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_163_WIDTH },
95849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_164_CHECKER_TYPE,
95850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_164_WIDTH },
95851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_165_CHECKER_TYPE,
95852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_165_WIDTH },
95853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_166_CHECKER_TYPE,
95854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_166_WIDTH },
95855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_167_CHECKER_TYPE,
95856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_167_WIDTH },
95857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_168_CHECKER_TYPE,
95858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_168_WIDTH },
95859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_169_CHECKER_TYPE,
95860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_169_WIDTH },
95861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_170_CHECKER_TYPE,
95862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_170_WIDTH },
95863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_171_CHECKER_TYPE,
95864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_171_WIDTH },
95865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_172_CHECKER_TYPE,
95866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_172_WIDTH },
95867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_173_CHECKER_TYPE,
95868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_173_WIDTH },
95869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_174_CHECKER_TYPE,
95870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_174_WIDTH },
95871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_175_CHECKER_TYPE,
95872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_175_WIDTH },
95873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_176_CHECKER_TYPE,
95874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_176_WIDTH },
95875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_177_CHECKER_TYPE,
95876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_177_WIDTH },
95877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_178_CHECKER_TYPE,
95878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_178_WIDTH },
95879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_179_CHECKER_TYPE,
95880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_179_WIDTH },
95881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_180_CHECKER_TYPE,
95882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_180_WIDTH },
95883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_181_CHECKER_TYPE,
95884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_181_WIDTH },
95885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_182_CHECKER_TYPE,
95886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_182_WIDTH },
95887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_183_CHECKER_TYPE,
95888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_183_WIDTH },
95889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_184_CHECKER_TYPE,
95890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_184_WIDTH },
95891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_185_CHECKER_TYPE,
95892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_185_WIDTH },
95893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_186_CHECKER_TYPE,
95894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_186_WIDTH },
95895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_187_CHECKER_TYPE,
95896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_187_WIDTH },
95897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_188_CHECKER_TYPE,
95898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_188_WIDTH },
95899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_189_CHECKER_TYPE,
95900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_189_WIDTH },
95901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_190_CHECKER_TYPE,
95902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_190_WIDTH },
95903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_191_CHECKER_TYPE,
95904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_191_WIDTH },
95905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_192_CHECKER_TYPE,
95906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_192_WIDTH },
95907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_193_CHECKER_TYPE,
95908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_193_WIDTH },
95909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_194_CHECKER_TYPE,
95910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_194_WIDTH },
95911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_195_CHECKER_TYPE,
95912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_195_WIDTH },
95913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_196_CHECKER_TYPE,
95914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_196_WIDTH },
95915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_197_CHECKER_TYPE,
95916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_197_WIDTH },
95917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_198_CHECKER_TYPE,
95918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_198_WIDTH },
95919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_199_CHECKER_TYPE,
95920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_199_WIDTH },
95921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_200_CHECKER_TYPE,
95922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_200_WIDTH },
95923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_201_CHECKER_TYPE,
95924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_201_WIDTH },
95925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_202_CHECKER_TYPE,
95926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_202_WIDTH },
95927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_203_CHECKER_TYPE,
95928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_203_WIDTH },
95929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_204_CHECKER_TYPE,
95930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_204_WIDTH },
95931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_205_CHECKER_TYPE,
95932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_205_WIDTH },
95933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_206_CHECKER_TYPE,
95934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_206_WIDTH },
95935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_207_CHECKER_TYPE,
95936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_207_WIDTH },
95937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_208_CHECKER_TYPE,
95938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_208_WIDTH },
95939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_209_CHECKER_TYPE,
95940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_209_WIDTH },
95941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_210_CHECKER_TYPE,
95942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_210_WIDTH },
95943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_211_CHECKER_TYPE,
95944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_211_WIDTH },
95945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_212_CHECKER_TYPE,
95946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_212_WIDTH },
95947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_213_CHECKER_TYPE,
95948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_213_WIDTH },
95949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_214_CHECKER_TYPE,
95950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_214_WIDTH },
95951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_215_CHECKER_TYPE,
95952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_215_WIDTH },
95953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_216_CHECKER_TYPE,
95954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_216_WIDTH },
95955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_217_CHECKER_TYPE,
95956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_217_WIDTH },
95957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_218_CHECKER_TYPE,
95958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_218_WIDTH },
95959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_219_CHECKER_TYPE,
95960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_219_WIDTH },
95961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_220_CHECKER_TYPE,
95962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_220_WIDTH },
95963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_221_CHECKER_TYPE,
95964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_221_WIDTH },
95965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_222_CHECKER_TYPE,
95966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_222_WIDTH },
95967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_223_CHECKER_TYPE,
95968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_223_WIDTH },
95969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_224_CHECKER_TYPE,
95970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_224_WIDTH },
95971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_225_CHECKER_TYPE,
95972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_225_WIDTH },
95973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_226_CHECKER_TYPE,
95974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_226_WIDTH },
95975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_227_CHECKER_TYPE,
95976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_227_WIDTH },
95977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_228_CHECKER_TYPE,
95978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_228_WIDTH },
95979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_229_CHECKER_TYPE,
95980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_229_WIDTH },
95981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_230_CHECKER_TYPE,
95982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_230_WIDTH },
95983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_231_CHECKER_TYPE,
95984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_231_WIDTH },
95985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_232_CHECKER_TYPE,
95986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_232_WIDTH },
95987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_233_CHECKER_TYPE,
95988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_233_WIDTH },
95989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_234_CHECKER_TYPE,
95990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_234_WIDTH },
95991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_235_CHECKER_TYPE,
95992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_235_WIDTH },
95993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_236_CHECKER_TYPE,
95994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_236_WIDTH },
95995  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_237_CHECKER_TYPE,
95996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_237_WIDTH },
95997  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_238_CHECKER_TYPE,
95998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_238_WIDTH },
95999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_239_CHECKER_TYPE,
96000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_239_WIDTH },
96001  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_240_CHECKER_TYPE,
96002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_240_WIDTH },
96003  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_241_CHECKER_TYPE,
96004  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_241_WIDTH },
96005  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_242_CHECKER_TYPE,
96006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_242_WIDTH },
96007  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_243_CHECKER_TYPE,
96008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_243_WIDTH },
96009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_244_CHECKER_TYPE,
96010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_244_WIDTH },
96011  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_245_CHECKER_TYPE,
96012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_245_WIDTH },
96013  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_246_CHECKER_TYPE,
96014  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_246_WIDTH },
96015  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_247_CHECKER_TYPE,
96016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_247_WIDTH },
96017  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_248_CHECKER_TYPE,
96018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_248_WIDTH },
96019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_249_CHECKER_TYPE,
96020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_249_WIDTH },
96021  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_250_CHECKER_TYPE,
96022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_250_WIDTH },
96023  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_251_CHECKER_TYPE,
96024  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_251_WIDTH },
96025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_252_CHECKER_TYPE,
96026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_252_WIDTH },
96027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_253_CHECKER_TYPE,
96028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_253_WIDTH },
96029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_254_CHECKER_TYPE,
96030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_254_WIDTH },
96031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_255_CHECKER_TYPE,
96032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_GROUP_255_WIDTH },
96033 };
96034 
96040 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_MAX_NUM_CHECKERS] =
96041 {
96042  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_0_CHECKER_TYPE,
96043  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_0_WIDTH },
96044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_1_CHECKER_TYPE,
96045  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_1_WIDTH },
96046  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_2_CHECKER_TYPE,
96047  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_2_WIDTH },
96048  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_3_CHECKER_TYPE,
96049  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_3_WIDTH },
96050  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_4_CHECKER_TYPE,
96051  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_4_WIDTH },
96052  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_5_CHECKER_TYPE,
96053  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_5_WIDTH },
96054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_6_CHECKER_TYPE,
96055  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_6_WIDTH },
96056  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_7_CHECKER_TYPE,
96057  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_7_WIDTH },
96058  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_8_CHECKER_TYPE,
96059  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_8_WIDTH },
96060  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_9_CHECKER_TYPE,
96061  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_9_WIDTH },
96062  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_10_CHECKER_TYPE,
96063  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_10_WIDTH },
96064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_11_CHECKER_TYPE,
96065  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_11_WIDTH },
96066  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_12_CHECKER_TYPE,
96067  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_12_WIDTH },
96068  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_13_CHECKER_TYPE,
96069  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_13_WIDTH },
96070  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_14_CHECKER_TYPE,
96071  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_14_WIDTH },
96072  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_15_CHECKER_TYPE,
96073  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_15_WIDTH },
96074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_16_CHECKER_TYPE,
96075  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_16_WIDTH },
96076  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_17_CHECKER_TYPE,
96077  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_17_WIDTH },
96078  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_18_CHECKER_TYPE,
96079  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_18_WIDTH },
96080  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_19_CHECKER_TYPE,
96081  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_19_WIDTH },
96082  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_20_CHECKER_TYPE,
96083  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_20_WIDTH },
96084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_21_CHECKER_TYPE,
96085  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_21_WIDTH },
96086  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_22_CHECKER_TYPE,
96087  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_22_WIDTH },
96088  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_23_CHECKER_TYPE,
96089  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_23_WIDTH },
96090  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_24_CHECKER_TYPE,
96091  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_24_WIDTH },
96092  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_25_CHECKER_TYPE,
96093  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_25_WIDTH },
96094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_26_CHECKER_TYPE,
96095  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_26_WIDTH },
96096  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_27_CHECKER_TYPE,
96097  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_27_WIDTH },
96098  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_28_CHECKER_TYPE,
96099  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_28_WIDTH },
96100  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_29_CHECKER_TYPE,
96101  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_29_WIDTH },
96102  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_30_CHECKER_TYPE,
96103  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_30_WIDTH },
96104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_31_CHECKER_TYPE,
96105  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_31_WIDTH },
96106  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_32_CHECKER_TYPE,
96107  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_32_WIDTH },
96108  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_33_CHECKER_TYPE,
96109  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_33_WIDTH },
96110  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_34_CHECKER_TYPE,
96111  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_34_WIDTH },
96112  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_35_CHECKER_TYPE,
96113  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_35_WIDTH },
96114  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_36_CHECKER_TYPE,
96115  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_36_WIDTH },
96116  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_37_CHECKER_TYPE,
96117  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_37_WIDTH },
96118  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_38_CHECKER_TYPE,
96119  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_38_WIDTH },
96120  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_39_CHECKER_TYPE,
96121  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_39_WIDTH },
96122  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_40_CHECKER_TYPE,
96123  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_40_WIDTH },
96124  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_41_CHECKER_TYPE,
96125  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_41_WIDTH },
96126  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_42_CHECKER_TYPE,
96127  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_42_WIDTH },
96128  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_43_CHECKER_TYPE,
96129  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_43_WIDTH },
96130  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_44_CHECKER_TYPE,
96131  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_44_WIDTH },
96132  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_45_CHECKER_TYPE,
96133  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_45_WIDTH },
96134  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_46_CHECKER_TYPE,
96135  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_46_WIDTH },
96136  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_47_CHECKER_TYPE,
96137  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_47_WIDTH },
96138  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_48_CHECKER_TYPE,
96139  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_48_WIDTH },
96140  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_49_CHECKER_TYPE,
96141  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_49_WIDTH },
96142  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_50_CHECKER_TYPE,
96143  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_50_WIDTH },
96144  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_51_CHECKER_TYPE,
96145  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_51_WIDTH },
96146  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_52_CHECKER_TYPE,
96147  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_52_WIDTH },
96148  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_53_CHECKER_TYPE,
96149  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_53_WIDTH },
96150  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_54_CHECKER_TYPE,
96151  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_54_WIDTH },
96152  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_55_CHECKER_TYPE,
96153  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_55_WIDTH },
96154  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_56_CHECKER_TYPE,
96155  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_56_WIDTH },
96156  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_57_CHECKER_TYPE,
96157  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_57_WIDTH },
96158  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_58_CHECKER_TYPE,
96159  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_58_WIDTH },
96160  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_59_CHECKER_TYPE,
96161  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_59_WIDTH },
96162  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_60_CHECKER_TYPE,
96163  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_60_WIDTH },
96164  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_61_CHECKER_TYPE,
96165  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_61_WIDTH },
96166  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_62_CHECKER_TYPE,
96167  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_62_WIDTH },
96168  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_63_CHECKER_TYPE,
96169  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_63_WIDTH },
96170  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_64_CHECKER_TYPE,
96171  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_64_WIDTH },
96172  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_65_CHECKER_TYPE,
96173  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_65_WIDTH },
96174  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_66_CHECKER_TYPE,
96175  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_66_WIDTH },
96176  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_67_CHECKER_TYPE,
96177  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_67_WIDTH },
96178  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_68_CHECKER_TYPE,
96179  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_68_WIDTH },
96180  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_69_CHECKER_TYPE,
96181  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_69_WIDTH },
96182  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_70_CHECKER_TYPE,
96183  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_70_WIDTH },
96184  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_71_CHECKER_TYPE,
96185  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_71_WIDTH },
96186  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_72_CHECKER_TYPE,
96187  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_72_WIDTH },
96188  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_73_CHECKER_TYPE,
96189  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_73_WIDTH },
96190  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_74_CHECKER_TYPE,
96191  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_74_WIDTH },
96192  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_75_CHECKER_TYPE,
96193  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_75_WIDTH },
96194  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_76_CHECKER_TYPE,
96195  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_76_WIDTH },
96196  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_77_CHECKER_TYPE,
96197  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_77_WIDTH },
96198  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_78_CHECKER_TYPE,
96199  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_78_WIDTH },
96200  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_79_CHECKER_TYPE,
96201  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_79_WIDTH },
96202  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_80_CHECKER_TYPE,
96203  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_80_WIDTH },
96204  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_81_CHECKER_TYPE,
96205  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_81_WIDTH },
96206  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_82_CHECKER_TYPE,
96207  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_82_WIDTH },
96208  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_83_CHECKER_TYPE,
96209  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_83_WIDTH },
96210  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_84_CHECKER_TYPE,
96211  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_84_WIDTH },
96212  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_85_CHECKER_TYPE,
96213  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_85_WIDTH },
96214  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_86_CHECKER_TYPE,
96215  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_86_WIDTH },
96216  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_87_CHECKER_TYPE,
96217  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_87_WIDTH },
96218  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_88_CHECKER_TYPE,
96219  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_88_WIDTH },
96220  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_89_CHECKER_TYPE,
96221  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_89_WIDTH },
96222  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_90_CHECKER_TYPE,
96223  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_90_WIDTH },
96224  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_91_CHECKER_TYPE,
96225  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_91_WIDTH },
96226  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_92_CHECKER_TYPE,
96227  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_92_WIDTH },
96228  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_93_CHECKER_TYPE,
96229  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_93_WIDTH },
96230  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_94_CHECKER_TYPE,
96231  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_94_WIDTH },
96232  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_95_CHECKER_TYPE,
96233  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_95_WIDTH },
96234  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_96_CHECKER_TYPE,
96235  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_96_WIDTH },
96236  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_97_CHECKER_TYPE,
96237  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_97_WIDTH },
96238  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_98_CHECKER_TYPE,
96239  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_98_WIDTH },
96240  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_99_CHECKER_TYPE,
96241  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_99_WIDTH },
96242  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_100_CHECKER_TYPE,
96243  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_100_WIDTH },
96244  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_101_CHECKER_TYPE,
96245  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_101_WIDTH },
96246  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_102_CHECKER_TYPE,
96247  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_102_WIDTH },
96248  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_103_CHECKER_TYPE,
96249  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_103_WIDTH },
96250  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_104_CHECKER_TYPE,
96251  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_104_WIDTH },
96252  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_105_CHECKER_TYPE,
96253  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_105_WIDTH },
96254  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_106_CHECKER_TYPE,
96255  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_106_WIDTH },
96256  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_107_CHECKER_TYPE,
96257  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_107_WIDTH },
96258  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_108_CHECKER_TYPE,
96259  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_108_WIDTH },
96260  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_109_CHECKER_TYPE,
96261  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_109_WIDTH },
96262  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_110_CHECKER_TYPE,
96263  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_110_WIDTH },
96264  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_111_CHECKER_TYPE,
96265  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_111_WIDTH },
96266  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_112_CHECKER_TYPE,
96267  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_112_WIDTH },
96268  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_113_CHECKER_TYPE,
96269  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_113_WIDTH },
96270  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_114_CHECKER_TYPE,
96271  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_114_WIDTH },
96272  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_115_CHECKER_TYPE,
96273  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_115_WIDTH },
96274  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_116_CHECKER_TYPE,
96275  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_116_WIDTH },
96276  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_117_CHECKER_TYPE,
96277  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_117_WIDTH },
96278  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_118_CHECKER_TYPE,
96279  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_118_WIDTH },
96280  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_119_CHECKER_TYPE,
96281  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_119_WIDTH },
96282  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_120_CHECKER_TYPE,
96283  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_120_WIDTH },
96284  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_121_CHECKER_TYPE,
96285  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_121_WIDTH },
96286  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_122_CHECKER_TYPE,
96287  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_122_WIDTH },
96288  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_123_CHECKER_TYPE,
96289  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_123_WIDTH },
96290  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_124_CHECKER_TYPE,
96291  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_124_WIDTH },
96292  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_125_CHECKER_TYPE,
96293  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_125_WIDTH },
96294  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_126_CHECKER_TYPE,
96295  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_126_WIDTH },
96296  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_127_CHECKER_TYPE,
96297  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_127_WIDTH },
96298  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_128_CHECKER_TYPE,
96299  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_128_WIDTH },
96300  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_129_CHECKER_TYPE,
96301  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_129_WIDTH },
96302  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_130_CHECKER_TYPE,
96303  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_130_WIDTH },
96304  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_131_CHECKER_TYPE,
96305  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_131_WIDTH },
96306  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_132_CHECKER_TYPE,
96307  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_132_WIDTH },
96308  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_133_CHECKER_TYPE,
96309  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_133_WIDTH },
96310  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_134_CHECKER_TYPE,
96311  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_134_WIDTH },
96312  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_135_CHECKER_TYPE,
96313  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_135_WIDTH },
96314  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_136_CHECKER_TYPE,
96315  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_136_WIDTH },
96316  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_137_CHECKER_TYPE,
96317  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_137_WIDTH },
96318  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_138_CHECKER_TYPE,
96319  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_138_WIDTH },
96320  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_139_CHECKER_TYPE,
96321  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_139_WIDTH },
96322  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_140_CHECKER_TYPE,
96323  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_140_WIDTH },
96324  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_141_CHECKER_TYPE,
96325  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_141_WIDTH },
96326  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_142_CHECKER_TYPE,
96327  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_142_WIDTH },
96328  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_143_CHECKER_TYPE,
96329  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_143_WIDTH },
96330  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_144_CHECKER_TYPE,
96331  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_144_WIDTH },
96332  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_145_CHECKER_TYPE,
96333  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_145_WIDTH },
96334  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_146_CHECKER_TYPE,
96335  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_146_WIDTH },
96336  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_147_CHECKER_TYPE,
96337  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_147_WIDTH },
96338  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_148_CHECKER_TYPE,
96339  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_148_WIDTH },
96340  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_149_CHECKER_TYPE,
96341  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_149_WIDTH },
96342  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_150_CHECKER_TYPE,
96343  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_150_WIDTH },
96344  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_151_CHECKER_TYPE,
96345  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_151_WIDTH },
96346  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_152_CHECKER_TYPE,
96347  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_152_WIDTH },
96348  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_153_CHECKER_TYPE,
96349  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_153_WIDTH },
96350  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_154_CHECKER_TYPE,
96351  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_154_WIDTH },
96352  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_155_CHECKER_TYPE,
96353  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_155_WIDTH },
96354  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_156_CHECKER_TYPE,
96355  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_156_WIDTH },
96356  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_157_CHECKER_TYPE,
96357  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_157_WIDTH },
96358  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_158_CHECKER_TYPE,
96359  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_158_WIDTH },
96360  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_159_CHECKER_TYPE,
96361  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_159_WIDTH },
96362  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_160_CHECKER_TYPE,
96363  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_160_WIDTH },
96364  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_161_CHECKER_TYPE,
96365  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_161_WIDTH },
96366  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_162_CHECKER_TYPE,
96367  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_162_WIDTH },
96368  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_163_CHECKER_TYPE,
96369  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_163_WIDTH },
96370  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_164_CHECKER_TYPE,
96371  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_164_WIDTH },
96372  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_165_CHECKER_TYPE,
96373  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_165_WIDTH },
96374  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_166_CHECKER_TYPE,
96375  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_166_WIDTH },
96376  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_167_CHECKER_TYPE,
96377  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_167_WIDTH },
96378  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_168_CHECKER_TYPE,
96379  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_168_WIDTH },
96380  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_169_CHECKER_TYPE,
96381  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_169_WIDTH },
96382  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_170_CHECKER_TYPE,
96383  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_170_WIDTH },
96384  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_171_CHECKER_TYPE,
96385  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_171_WIDTH },
96386  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_172_CHECKER_TYPE,
96387  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_172_WIDTH },
96388  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_173_CHECKER_TYPE,
96389  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_173_WIDTH },
96390  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_174_CHECKER_TYPE,
96391  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_174_WIDTH },
96392  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_175_CHECKER_TYPE,
96393  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_175_WIDTH },
96394  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_176_CHECKER_TYPE,
96395  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_176_WIDTH },
96396  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_177_CHECKER_TYPE,
96397  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_177_WIDTH },
96398  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_178_CHECKER_TYPE,
96399  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_178_WIDTH },
96400  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_179_CHECKER_TYPE,
96401  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_179_WIDTH },
96402  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_180_CHECKER_TYPE,
96403  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_180_WIDTH },
96404  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_181_CHECKER_TYPE,
96405  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_181_WIDTH },
96406  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_182_CHECKER_TYPE,
96407  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_182_WIDTH },
96408  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_183_CHECKER_TYPE,
96409  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_183_WIDTH },
96410  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_184_CHECKER_TYPE,
96411  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_184_WIDTH },
96412  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_185_CHECKER_TYPE,
96413  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_185_WIDTH },
96414  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_186_CHECKER_TYPE,
96415  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_186_WIDTH },
96416  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_187_CHECKER_TYPE,
96417  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_187_WIDTH },
96418  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_188_CHECKER_TYPE,
96419  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_188_WIDTH },
96420  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_189_CHECKER_TYPE,
96421  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_189_WIDTH },
96422  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_190_CHECKER_TYPE,
96423  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_190_WIDTH },
96424  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_191_CHECKER_TYPE,
96425  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_191_WIDTH },
96426  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_192_CHECKER_TYPE,
96427  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_192_WIDTH },
96428  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_193_CHECKER_TYPE,
96429  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_193_WIDTH },
96430  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_194_CHECKER_TYPE,
96431  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_194_WIDTH },
96432  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_195_CHECKER_TYPE,
96433  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_195_WIDTH },
96434  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_196_CHECKER_TYPE,
96435  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_196_WIDTH },
96436  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_197_CHECKER_TYPE,
96437  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_197_WIDTH },
96438  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_198_CHECKER_TYPE,
96439  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_198_WIDTH },
96440  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_199_CHECKER_TYPE,
96441  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_199_WIDTH },
96442  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_200_CHECKER_TYPE,
96443  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_200_WIDTH },
96444  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_201_CHECKER_TYPE,
96445  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_201_WIDTH },
96446  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_202_CHECKER_TYPE,
96447  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_202_WIDTH },
96448  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_203_CHECKER_TYPE,
96449  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_203_WIDTH },
96450  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_204_CHECKER_TYPE,
96451  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_204_WIDTH },
96452  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_205_CHECKER_TYPE,
96453  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_205_WIDTH },
96454  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_206_CHECKER_TYPE,
96455  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_206_WIDTH },
96456  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_207_CHECKER_TYPE,
96457  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_207_WIDTH },
96458  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_208_CHECKER_TYPE,
96459  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_208_WIDTH },
96460  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_209_CHECKER_TYPE,
96461  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_209_WIDTH },
96462  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_210_CHECKER_TYPE,
96463  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_210_WIDTH },
96464  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_211_CHECKER_TYPE,
96465  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_211_WIDTH },
96466  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_212_CHECKER_TYPE,
96467  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_212_WIDTH },
96468  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_213_CHECKER_TYPE,
96469  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_213_WIDTH },
96470  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_214_CHECKER_TYPE,
96471  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_214_WIDTH },
96472  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_215_CHECKER_TYPE,
96473  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_215_WIDTH },
96474  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_216_CHECKER_TYPE,
96475  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_216_WIDTH },
96476  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_217_CHECKER_TYPE,
96477  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_217_WIDTH },
96478  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_218_CHECKER_TYPE,
96479  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_218_WIDTH },
96480  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_219_CHECKER_TYPE,
96481  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_219_WIDTH },
96482  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_220_CHECKER_TYPE,
96483  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_220_WIDTH },
96484  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_221_CHECKER_TYPE,
96485  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_221_WIDTH },
96486  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_222_CHECKER_TYPE,
96487  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_222_WIDTH },
96488  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_223_CHECKER_TYPE,
96489  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_223_WIDTH },
96490  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_224_CHECKER_TYPE,
96491  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_224_WIDTH },
96492  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_225_CHECKER_TYPE,
96493  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_225_WIDTH },
96494  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_226_CHECKER_TYPE,
96495  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_226_WIDTH },
96496  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_227_CHECKER_TYPE,
96497  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_227_WIDTH },
96498  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_228_CHECKER_TYPE,
96499  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_228_WIDTH },
96500  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_229_CHECKER_TYPE,
96501  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_229_WIDTH },
96502  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_230_CHECKER_TYPE,
96503  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_230_WIDTH },
96504  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_231_CHECKER_TYPE,
96505  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_231_WIDTH },
96506  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_232_CHECKER_TYPE,
96507  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_232_WIDTH },
96508  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_233_CHECKER_TYPE,
96509  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_233_WIDTH },
96510  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_234_CHECKER_TYPE,
96511  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_234_WIDTH },
96512  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_235_CHECKER_TYPE,
96513  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_235_WIDTH },
96514  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_236_CHECKER_TYPE,
96515  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_236_WIDTH },
96516  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_237_CHECKER_TYPE,
96517  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_237_WIDTH },
96518  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_238_CHECKER_TYPE,
96519  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_238_WIDTH },
96520  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_239_CHECKER_TYPE,
96521  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_239_WIDTH },
96522  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_240_CHECKER_TYPE,
96523  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_240_WIDTH },
96524  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_241_CHECKER_TYPE,
96525  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_241_WIDTH },
96526  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_242_CHECKER_TYPE,
96527  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_242_WIDTH },
96528  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_243_CHECKER_TYPE,
96529  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_243_WIDTH },
96530  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_244_CHECKER_TYPE,
96531  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_244_WIDTH },
96532  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_245_CHECKER_TYPE,
96533  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_245_WIDTH },
96534  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_246_CHECKER_TYPE,
96535  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_246_WIDTH },
96536  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_247_CHECKER_TYPE,
96537  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_247_WIDTH },
96538  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_248_CHECKER_TYPE,
96539  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_248_WIDTH },
96540  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_249_CHECKER_TYPE,
96541  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_249_WIDTH },
96542  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_250_CHECKER_TYPE,
96543  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_250_WIDTH },
96544  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_251_CHECKER_TYPE,
96545  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_251_WIDTH },
96546  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_252_CHECKER_TYPE,
96547  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_252_WIDTH },
96548  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_253_CHECKER_TYPE,
96549  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_253_WIDTH },
96550  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_254_CHECKER_TYPE,
96551  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_254_WIDTH },
96552  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_255_CHECKER_TYPE,
96553  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_GROUP_255_WIDTH },
96554 };
96555 
96561 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_MAX_NUM_CHECKERS] =
96562 {
96563  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_0_CHECKER_TYPE,
96564  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_0_WIDTH },
96565  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_1_CHECKER_TYPE,
96566  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_1_WIDTH },
96567  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_2_CHECKER_TYPE,
96568  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_2_WIDTH },
96569  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_3_CHECKER_TYPE,
96570  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_3_WIDTH },
96571  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_4_CHECKER_TYPE,
96572  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_4_WIDTH },
96573  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_5_CHECKER_TYPE,
96574  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_5_WIDTH },
96575  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_6_CHECKER_TYPE,
96576  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_6_WIDTH },
96577  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_7_CHECKER_TYPE,
96578  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_7_WIDTH },
96579  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_8_CHECKER_TYPE,
96580  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_8_WIDTH },
96581  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_9_CHECKER_TYPE,
96582  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_9_WIDTH },
96583  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_10_CHECKER_TYPE,
96584  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_10_WIDTH },
96585  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_11_CHECKER_TYPE,
96586  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_11_WIDTH },
96587  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_12_CHECKER_TYPE,
96588  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_12_WIDTH },
96589  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_13_CHECKER_TYPE,
96590  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_13_WIDTH },
96591  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_14_CHECKER_TYPE,
96592  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_14_WIDTH },
96593  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_15_CHECKER_TYPE,
96594  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_15_WIDTH },
96595  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_16_CHECKER_TYPE,
96596  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_16_WIDTH },
96597  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_17_CHECKER_TYPE,
96598  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_17_WIDTH },
96599  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_18_CHECKER_TYPE,
96600  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_18_WIDTH },
96601  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_19_CHECKER_TYPE,
96602  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_19_WIDTH },
96603  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_20_CHECKER_TYPE,
96604  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_20_WIDTH },
96605  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_21_CHECKER_TYPE,
96606  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_21_WIDTH },
96607  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_22_CHECKER_TYPE,
96608  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_22_WIDTH },
96609  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_23_CHECKER_TYPE,
96610  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_23_WIDTH },
96611  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_24_CHECKER_TYPE,
96612  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_24_WIDTH },
96613  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_25_CHECKER_TYPE,
96614  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_25_WIDTH },
96615  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_26_CHECKER_TYPE,
96616  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_26_WIDTH },
96617  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_27_CHECKER_TYPE,
96618  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_27_WIDTH },
96619  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_28_CHECKER_TYPE,
96620  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_28_WIDTH },
96621  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_29_CHECKER_TYPE,
96622  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_29_WIDTH },
96623  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_30_CHECKER_TYPE,
96624  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_30_WIDTH },
96625  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_31_CHECKER_TYPE,
96626  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_31_WIDTH },
96627  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_32_CHECKER_TYPE,
96628  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_32_WIDTH },
96629  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_33_CHECKER_TYPE,
96630  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_33_WIDTH },
96631  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_34_CHECKER_TYPE,
96632  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_34_WIDTH },
96633  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_35_CHECKER_TYPE,
96634  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_35_WIDTH },
96635  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_36_CHECKER_TYPE,
96636  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_36_WIDTH },
96637  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_37_CHECKER_TYPE,
96638  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_37_WIDTH },
96639  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_38_CHECKER_TYPE,
96640  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_38_WIDTH },
96641  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_39_CHECKER_TYPE,
96642  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_39_WIDTH },
96643  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_40_CHECKER_TYPE,
96644  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_40_WIDTH },
96645  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_41_CHECKER_TYPE,
96646  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_41_WIDTH },
96647  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_42_CHECKER_TYPE,
96648  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_42_WIDTH },
96649  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_43_CHECKER_TYPE,
96650  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_43_WIDTH },
96651  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_44_CHECKER_TYPE,
96652  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_44_WIDTH },
96653  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_45_CHECKER_TYPE,
96654  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_45_WIDTH },
96655  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_46_CHECKER_TYPE,
96656  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_46_WIDTH },
96657  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_47_CHECKER_TYPE,
96658  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_47_WIDTH },
96659  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_48_CHECKER_TYPE,
96660  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_48_WIDTH },
96661  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_49_CHECKER_TYPE,
96662  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_49_WIDTH },
96663  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_50_CHECKER_TYPE,
96664  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_50_WIDTH },
96665  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_51_CHECKER_TYPE,
96666  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_51_WIDTH },
96667  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_52_CHECKER_TYPE,
96668  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_52_WIDTH },
96669  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_53_CHECKER_TYPE,
96670  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_53_WIDTH },
96671  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_54_CHECKER_TYPE,
96672  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_54_WIDTH },
96673  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_55_CHECKER_TYPE,
96674  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_55_WIDTH },
96675  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_56_CHECKER_TYPE,
96676  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_56_WIDTH },
96677  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_57_CHECKER_TYPE,
96678  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_57_WIDTH },
96679  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_58_CHECKER_TYPE,
96680  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_58_WIDTH },
96681  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_59_CHECKER_TYPE,
96682  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_59_WIDTH },
96683  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_60_CHECKER_TYPE,
96684  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_60_WIDTH },
96685  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_61_CHECKER_TYPE,
96686  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_61_WIDTH },
96687  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_62_CHECKER_TYPE,
96688  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_62_WIDTH },
96689  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_63_CHECKER_TYPE,
96690  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_63_WIDTH },
96691  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_64_CHECKER_TYPE,
96692  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_64_WIDTH },
96693  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_65_CHECKER_TYPE,
96694  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_65_WIDTH },
96695  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_66_CHECKER_TYPE,
96696  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_66_WIDTH },
96697  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_67_CHECKER_TYPE,
96698  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_67_WIDTH },
96699  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_68_CHECKER_TYPE,
96700  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_68_WIDTH },
96701  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_69_CHECKER_TYPE,
96702  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_69_WIDTH },
96703  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_70_CHECKER_TYPE,
96704  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_70_WIDTH },
96705  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_71_CHECKER_TYPE,
96706  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_71_WIDTH },
96707  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_72_CHECKER_TYPE,
96708  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_72_WIDTH },
96709  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_73_CHECKER_TYPE,
96710  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_73_WIDTH },
96711  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_74_CHECKER_TYPE,
96712  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_74_WIDTH },
96713  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_75_CHECKER_TYPE,
96714  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_75_WIDTH },
96715  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_76_CHECKER_TYPE,
96716  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_76_WIDTH },
96717  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_77_CHECKER_TYPE,
96718  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_77_WIDTH },
96719  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_78_CHECKER_TYPE,
96720  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_78_WIDTH },
96721  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_79_CHECKER_TYPE,
96722  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_79_WIDTH },
96723  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_80_CHECKER_TYPE,
96724  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_80_WIDTH },
96725  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_81_CHECKER_TYPE,
96726  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_81_WIDTH },
96727  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_82_CHECKER_TYPE,
96728  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_82_WIDTH },
96729  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_83_CHECKER_TYPE,
96730  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_83_WIDTH },
96731  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_84_CHECKER_TYPE,
96732  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_84_WIDTH },
96733  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_85_CHECKER_TYPE,
96734  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_85_WIDTH },
96735  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_86_CHECKER_TYPE,
96736  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_86_WIDTH },
96737  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_87_CHECKER_TYPE,
96738  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_87_WIDTH },
96739  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_88_CHECKER_TYPE,
96740  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_88_WIDTH },
96741  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_89_CHECKER_TYPE,
96742  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_89_WIDTH },
96743  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_90_CHECKER_TYPE,
96744  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_90_WIDTH },
96745  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_91_CHECKER_TYPE,
96746  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_91_WIDTH },
96747  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_92_CHECKER_TYPE,
96748  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_92_WIDTH },
96749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_93_CHECKER_TYPE,
96750  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_93_WIDTH },
96751  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_94_CHECKER_TYPE,
96752  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_94_WIDTH },
96753  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_95_CHECKER_TYPE,
96754  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_95_WIDTH },
96755  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_96_CHECKER_TYPE,
96756  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_96_WIDTH },
96757  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_97_CHECKER_TYPE,
96758  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_97_WIDTH },
96759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_98_CHECKER_TYPE,
96760  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_98_WIDTH },
96761  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_99_CHECKER_TYPE,
96762  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_99_WIDTH },
96763  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_100_CHECKER_TYPE,
96764  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_100_WIDTH },
96765  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_101_CHECKER_TYPE,
96766  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_101_WIDTH },
96767  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_102_CHECKER_TYPE,
96768  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_102_WIDTH },
96769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_103_CHECKER_TYPE,
96770  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_103_WIDTH },
96771  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_104_CHECKER_TYPE,
96772  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_104_WIDTH },
96773  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_105_CHECKER_TYPE,
96774  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_105_WIDTH },
96775  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_106_CHECKER_TYPE,
96776  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_106_WIDTH },
96777  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_107_CHECKER_TYPE,
96778  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_107_WIDTH },
96779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_108_CHECKER_TYPE,
96780  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_108_WIDTH },
96781  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_109_CHECKER_TYPE,
96782  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_109_WIDTH },
96783  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_110_CHECKER_TYPE,
96784  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_110_WIDTH },
96785  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_111_CHECKER_TYPE,
96786  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_111_WIDTH },
96787  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_112_CHECKER_TYPE,
96788  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_112_WIDTH },
96789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_113_CHECKER_TYPE,
96790  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_113_WIDTH },
96791  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_114_CHECKER_TYPE,
96792  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_114_WIDTH },
96793  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_115_CHECKER_TYPE,
96794  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_115_WIDTH },
96795  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_116_CHECKER_TYPE,
96796  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_116_WIDTH },
96797  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_117_CHECKER_TYPE,
96798  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_117_WIDTH },
96799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_118_CHECKER_TYPE,
96800  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_118_WIDTH },
96801  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_119_CHECKER_TYPE,
96802  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_119_WIDTH },
96803  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_120_CHECKER_TYPE,
96804  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_120_WIDTH },
96805  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_121_CHECKER_TYPE,
96806  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_121_WIDTH },
96807  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_122_CHECKER_TYPE,
96808  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_122_WIDTH },
96809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_123_CHECKER_TYPE,
96810  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_123_WIDTH },
96811  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_124_CHECKER_TYPE,
96812  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_124_WIDTH },
96813  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_125_CHECKER_TYPE,
96814  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_125_WIDTH },
96815  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_126_CHECKER_TYPE,
96816  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_126_WIDTH },
96817  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_127_CHECKER_TYPE,
96818  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_127_WIDTH },
96819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_128_CHECKER_TYPE,
96820  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_128_WIDTH },
96821  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_129_CHECKER_TYPE,
96822  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_129_WIDTH },
96823  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_130_CHECKER_TYPE,
96824  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_130_WIDTH },
96825  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_131_CHECKER_TYPE,
96826  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_131_WIDTH },
96827  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_132_CHECKER_TYPE,
96828  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_132_WIDTH },
96829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_133_CHECKER_TYPE,
96830  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_133_WIDTH },
96831  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_134_CHECKER_TYPE,
96832  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_134_WIDTH },
96833  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_135_CHECKER_TYPE,
96834  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_135_WIDTH },
96835  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_136_CHECKER_TYPE,
96836  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_136_WIDTH },
96837  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_137_CHECKER_TYPE,
96838  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_137_WIDTH },
96839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_138_CHECKER_TYPE,
96840  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_138_WIDTH },
96841  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_139_CHECKER_TYPE,
96842  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_139_WIDTH },
96843  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_140_CHECKER_TYPE,
96844  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_140_WIDTH },
96845  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_141_CHECKER_TYPE,
96846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_141_WIDTH },
96847  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_142_CHECKER_TYPE,
96848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_142_WIDTH },
96849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_143_CHECKER_TYPE,
96850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_143_WIDTH },
96851  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_144_CHECKER_TYPE,
96852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_144_WIDTH },
96853  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_145_CHECKER_TYPE,
96854  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_145_WIDTH },
96855  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_146_CHECKER_TYPE,
96856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_146_WIDTH },
96857  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_147_CHECKER_TYPE,
96858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_147_WIDTH },
96859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_148_CHECKER_TYPE,
96860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_148_WIDTH },
96861  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_149_CHECKER_TYPE,
96862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_149_WIDTH },
96863  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_150_CHECKER_TYPE,
96864  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_150_WIDTH },
96865  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_151_CHECKER_TYPE,
96866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_151_WIDTH },
96867  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_152_CHECKER_TYPE,
96868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_152_WIDTH },
96869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_153_CHECKER_TYPE,
96870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_153_WIDTH },
96871  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_154_CHECKER_TYPE,
96872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_154_WIDTH },
96873  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_155_CHECKER_TYPE,
96874  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_155_WIDTH },
96875  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_156_CHECKER_TYPE,
96876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_156_WIDTH },
96877  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_157_CHECKER_TYPE,
96878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_157_WIDTH },
96879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_158_CHECKER_TYPE,
96880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_158_WIDTH },
96881  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_159_CHECKER_TYPE,
96882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_159_WIDTH },
96883  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_160_CHECKER_TYPE,
96884  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_160_WIDTH },
96885  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_161_CHECKER_TYPE,
96886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_161_WIDTH },
96887  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_162_CHECKER_TYPE,
96888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_162_WIDTH },
96889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_163_CHECKER_TYPE,
96890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_163_WIDTH },
96891  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_164_CHECKER_TYPE,
96892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_164_WIDTH },
96893  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_165_CHECKER_TYPE,
96894  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_165_WIDTH },
96895  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_166_CHECKER_TYPE,
96896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_166_WIDTH },
96897  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_167_CHECKER_TYPE,
96898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_167_WIDTH },
96899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_168_CHECKER_TYPE,
96900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_168_WIDTH },
96901  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_169_CHECKER_TYPE,
96902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_169_WIDTH },
96903  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_170_CHECKER_TYPE,
96904  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_170_WIDTH },
96905  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_171_CHECKER_TYPE,
96906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_171_WIDTH },
96907  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_172_CHECKER_TYPE,
96908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_172_WIDTH },
96909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_173_CHECKER_TYPE,
96910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_173_WIDTH },
96911  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_174_CHECKER_TYPE,
96912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_174_WIDTH },
96913  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_175_CHECKER_TYPE,
96914  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_175_WIDTH },
96915  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_176_CHECKER_TYPE,
96916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_176_WIDTH },
96917  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_177_CHECKER_TYPE,
96918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_177_WIDTH },
96919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_178_CHECKER_TYPE,
96920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_178_WIDTH },
96921  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_179_CHECKER_TYPE,
96922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_179_WIDTH },
96923  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_180_CHECKER_TYPE,
96924  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_180_WIDTH },
96925  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_181_CHECKER_TYPE,
96926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_181_WIDTH },
96927  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_182_CHECKER_TYPE,
96928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_182_WIDTH },
96929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_183_CHECKER_TYPE,
96930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_183_WIDTH },
96931  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_184_CHECKER_TYPE,
96932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_184_WIDTH },
96933  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_185_CHECKER_TYPE,
96934  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_185_WIDTH },
96935  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_186_CHECKER_TYPE,
96936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_186_WIDTH },
96937  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_187_CHECKER_TYPE,
96938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_187_WIDTH },
96939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_188_CHECKER_TYPE,
96940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_188_WIDTH },
96941  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_189_CHECKER_TYPE,
96942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_189_WIDTH },
96943  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_190_CHECKER_TYPE,
96944  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_190_WIDTH },
96945  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_191_CHECKER_TYPE,
96946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_191_WIDTH },
96947  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_192_CHECKER_TYPE,
96948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_192_WIDTH },
96949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_193_CHECKER_TYPE,
96950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_193_WIDTH },
96951  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_194_CHECKER_TYPE,
96952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_194_WIDTH },
96953  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_195_CHECKER_TYPE,
96954  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_195_WIDTH },
96955  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_196_CHECKER_TYPE,
96956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_196_WIDTH },
96957  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_197_CHECKER_TYPE,
96958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_197_WIDTH },
96959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_198_CHECKER_TYPE,
96960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_198_WIDTH },
96961  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_199_CHECKER_TYPE,
96962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_199_WIDTH },
96963  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_200_CHECKER_TYPE,
96964  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_200_WIDTH },
96965  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_201_CHECKER_TYPE,
96966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_201_WIDTH },
96967  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_202_CHECKER_TYPE,
96968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_202_WIDTH },
96969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_203_CHECKER_TYPE,
96970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_203_WIDTH },
96971  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_204_CHECKER_TYPE,
96972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_204_WIDTH },
96973  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_205_CHECKER_TYPE,
96974  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_205_WIDTH },
96975  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_206_CHECKER_TYPE,
96976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_206_WIDTH },
96977  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_207_CHECKER_TYPE,
96978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_207_WIDTH },
96979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_208_CHECKER_TYPE,
96980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_208_WIDTH },
96981  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_209_CHECKER_TYPE,
96982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_209_WIDTH },
96983  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_210_CHECKER_TYPE,
96984  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_210_WIDTH },
96985  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_211_CHECKER_TYPE,
96986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_211_WIDTH },
96987  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_212_CHECKER_TYPE,
96988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_212_WIDTH },
96989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_213_CHECKER_TYPE,
96990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_213_WIDTH },
96991  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_214_CHECKER_TYPE,
96992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_214_WIDTH },
96993  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_215_CHECKER_TYPE,
96994  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_GROUP_215_WIDTH },
96995 };
96996 
97002 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
97003 {
97004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
97005  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
97006  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
97007  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
97008  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
97009  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
97010  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
97011  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
97012  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
97013  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
97014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
97015  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
97016 };
97017 
97023 static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
97024 {
97025  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
97026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
97027  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
97028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
97029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
97030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
97031  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
97032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
97033  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
97034  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
97035  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
97036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
97037 };
97038 
97044 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97045 {
97046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97082 };
97083 
97089 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97090 {
97091  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97092  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97093  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97094  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97095  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97096  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97097  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97098  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97099  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97100  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97101  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97102  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97103  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97104  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97105  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97106  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97107  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97108  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97109  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97110  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97111  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97112  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97113  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97114  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97115  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97116  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97117  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97118  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97119  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97120  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97121  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97122  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97123  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97124  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97125  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97126  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97127  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97128  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97129  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97130  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97131  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97132  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97133  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97134  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97135  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97136  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97137 };
97138 
97144 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97145 {
97146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97182 };
97183 
97189 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97190 {
97191  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97192  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97193  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97194  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97195  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97196  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97197  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97198  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97199  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97200  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97201  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97202  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97203  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97204  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97205  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97206  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97207  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97208  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97209  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97210  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97211  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97212  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97213  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97214  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97215  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97216  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97217  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97218  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97219  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97220  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97221  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97222  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97223  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97224  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97225  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97226  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97227  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97228  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97229  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97230  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97231  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97232  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97233  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97234  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97235  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97236  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97237 };
97238 
97244 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97245 {
97246  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97247  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97248  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97249  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97250  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97251  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97252  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97253  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97254  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97255  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97256  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97257  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97258  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97259  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97260  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97261  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97262  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97263  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97264  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97265  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97266  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97267  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97268  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97269  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97270  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97271  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97272  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97273  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97274  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97275  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97276  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97277  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97278  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97279  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97280  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97281  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97282 };
97283 
97289 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97290 {
97291  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97292  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97293  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97294  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97295  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97296  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97297  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97298  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97299  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97300  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97301  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97302  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97303  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97304  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97305  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97306  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97307  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97308  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97337 };
97338 
97344 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97345 {
97346  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97347  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97348  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97349  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97350  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97351  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97352  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97353  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97354  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97355  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97356  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97357  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97358  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97359  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97360  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97361  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97362  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97363  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97364  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97365  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97366  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97367  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97368  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97369  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97370  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97371  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97372  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97373  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97374  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97375  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97376  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97377  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97378  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97379  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97380  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97381  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97382 };
97383 
97389 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97390 {
97391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97395  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97399  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97401  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97402  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97403  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97405  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97409  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97411  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97412  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97413  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97415  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97437 };
97438 
97444 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97445 {
97446  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97447  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97448  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97449  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97450  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97451  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97452  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97453  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97454  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97455  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97456  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97457  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97458  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97459  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97460  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97461  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97462  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97463  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97464  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97465  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97466  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97467  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97468  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97469  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97470  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97471  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97472  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97473  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97474  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97475  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97476  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97477  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97478  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97479  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97480  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97481  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97482  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97483  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97484  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97485  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97486  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97487  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97488  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97489  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97490  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97491  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97492  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
97493  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
97494  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
97495  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
97496  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
97497  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
97498  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
97499  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
97500  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
97501  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
97502  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
97503  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
97504  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
97505  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
97506  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
97507  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
97508  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
97509  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
97510  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
97511  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
97512  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
97513  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
97514  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
97515  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
97516  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
97517  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
97518  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
97519  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
97520  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
97521  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
97522  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
97523  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
97524  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
97525  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
97526  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
97527  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
97528 };
97529 
97535 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97536 {
97537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97541  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97542  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97543  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97545  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97549  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97551  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97552  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97553  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97554  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97555  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97559  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97561  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97562  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97569  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97571  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97572  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97573  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97574  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97575  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97576  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97577  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97578  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97579  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97580  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97581  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97582  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97583  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
97584  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
97585  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
97586  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
97587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
97588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
97589  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
97590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
97591  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
97592  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
97593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
97594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
97595  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
97596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
97597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
97598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
97599  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
97600  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
97601  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
97602  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
97603  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
97604  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
97605  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
97606  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
97607  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
97608  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
97609  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
97610  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
97611  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
97612  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
97613  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
97614  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
97615  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
97616  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
97617  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
97618  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
97619  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
97620  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
97621  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
97622  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
97623  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
97624  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
97625  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
97626  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
97627  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
97628  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
97629  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
97630  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
97631 };
97632 
97638 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97639 {
97640  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97641  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97642  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97643  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97644  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97645  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97646  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97647  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97648  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97649  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97650  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97651  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97652  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97653  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97654  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97655  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97656  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97657  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97658  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97659  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97660  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97661  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97662  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97663  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97664  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97665  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97666  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97667  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97668  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97669  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97670  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97671  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97672  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97673  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97674  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97675  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97676  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97677  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97678  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97679  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97680  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97681  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97682  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97683  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97684  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97685  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97686  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
97687  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
97688  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
97689  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
97690  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
97691  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
97692  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
97693  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
97694  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
97695  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
97696  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
97697  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
97698  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
97699  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
97700  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
97701  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
97702  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
97703  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
97704  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
97705  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
97706  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
97707  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
97708  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
97709  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
97710  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
97711  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
97712  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
97713  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
97714  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
97715  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
97716  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
97717  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
97718  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
97719  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
97720  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
97721  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
97722 };
97723 
97729 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97730 {
97731  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97732  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97733  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97734  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97735  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97736  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97737  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97738  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97739  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97740  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97741  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97742  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97743  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97744  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97745  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97746  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97747  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97748  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97749  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97750  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97751  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97752  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97753  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97754  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97755  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97756  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97757  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97758  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97759  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97760  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97761  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97762  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97763  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97764  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97765  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97766  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97767  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97768  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97769  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97770  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97771  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97772  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97773  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97774  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97775  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97776  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97777  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
97778  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
97779  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
97780  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
97781  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
97782  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
97783  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
97784  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
97785  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
97786  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
97787  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
97788  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
97789  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
97790  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
97791  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
97792  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
97793  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
97794  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
97795  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
97796  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
97797  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
97798  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
97799  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
97800  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
97801  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
97802  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
97803  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
97804  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
97805  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
97806  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
97807  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
97808  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
97809  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
97810  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
97811  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
97812  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
97813 };
97814 
97820 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97821 {
97822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97858  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97859  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97860  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97861  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97862  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97863  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97864  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97865  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97866  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97867  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97868  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
97869  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
97870  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
97871  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
97872  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
97873  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
97874  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
97875  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
97876  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
97877  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
97878  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
97879  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
97880  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
97881  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
97882  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
97883  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
97884  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
97885  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
97886  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
97887  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
97888  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
97889  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
97890  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
97891  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
97892  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
97893  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
97894  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
97895  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
97896  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
97897  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
97898  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
97899  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
97900  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
97901  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
97902  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
97903  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
97904 };
97905 
97911 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
97912 {
97913  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
97914  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
97915  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
97916  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
97917  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
97918  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
97919  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
97920  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
97921  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
97922  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
97923  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
97924  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
97925  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
97926  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
97927  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
97928  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
97929  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
97930  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
97931  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
97932  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
97933  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
97934  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
97935  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
97936  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
97937  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
97938  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
97939  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
97940  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
97941  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
97942  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
97943  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
97944  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
97945  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
97946  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
97947  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
97948  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
97949  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
97950  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
97951  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
97952  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
97953  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
97954  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
97955  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
97956  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
97957  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
97958  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
97959  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
97960  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
97961  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
97962  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
97963  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
97964  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
97965  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
97966  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
97967  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
97968  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
97969  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
97970  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
97971  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
97972  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
97973  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
97974  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
97975  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
97976  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
97977  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
97978  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
97979  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
97980  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
97981  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
97982  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
97983  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
97984  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
97985  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
97986  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
97987  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
97988  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
97989  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
97990  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
97991  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
97992  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
97993  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
97994  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
97995 };
97996 
98002 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98003 {
98004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98086 };
98087 
98093 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98094 {
98095  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98096  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98097  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98098  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98099  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98100  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98101  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98102  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98103  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98104  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98105  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98106  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98107  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98108  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98109  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98110  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98111  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98112  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98113  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98114  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98115  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98116  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98117  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98118  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98119  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98120  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98121  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98122  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98123  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98124  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98125  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98126  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98127  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98128  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98129  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98130  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98131  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98132  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98133  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98134  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98135  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98136  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98137  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98138  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98139  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98140  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98141  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98142  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98143  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98144  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98145  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98146  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98147  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98148  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98149  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98150  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98151  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98152  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98153  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98154  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98155  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98156  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98157  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98158  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98159  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98160  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98161  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98162  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98163  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98164  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98165  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98166  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98167  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98168  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98169  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98170  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98171  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98172  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98173  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98174  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98175  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98176  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98177 };
98178 
98184 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98185 {
98186  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98187  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98188  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98189  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98190  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98191  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98192  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98193  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98194  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98195  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98196  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98197  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98198  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98199  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98200  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98201  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98202  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98203  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98204  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98205  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98206  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98207  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98208  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98209  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98210  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98211  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98212  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98213  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98214  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98215  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98216  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98217  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98218  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98219  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98220  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98221  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98222  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98223  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98224  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98225  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98226  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98227  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98228  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98229  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98230  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98231  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98232  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98233  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98234  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98235  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98236  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98237  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98238  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98239  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98240  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98241  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98242  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98243  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98244  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98245  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98246  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98247  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98248  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98249  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98250  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98251  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98252  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98253  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98254  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98255  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98256  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98257  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98258  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98259  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98260  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98261  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98262  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98263  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98264  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98265  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98266  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98267  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98268 };
98269 
98275 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98276 {
98277  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98278  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98279  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98280  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98281  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98282  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98283  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98284  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98285  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98286  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98287  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98288  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98289  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98290  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98291  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98292  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98293  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98294  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98295  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98296  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98297  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98298  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98299  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98300  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98301  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98302  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98303  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98304  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98305  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98306  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98307  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98308  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98339  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98340  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98341  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98342  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98343  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98344  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98345  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98346  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98347  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98348  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98349  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98350  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98351  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98352  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98353  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98354  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98355  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98356  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98357  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98358  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98359 };
98360 
98366 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98367 {
98368  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98369  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98370  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98371  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98372  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98373  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98374  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98375  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98376  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98377  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98378  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98379  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98380  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98381  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98382  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98383  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98384  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98385  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98386  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98387  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98388  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98389  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98390  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98391  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98392  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98393  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98394  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98395  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98396  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98397  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98398  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98399  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98400  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98401  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98402  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98403  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98404  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98405  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98406  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98407  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98408  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98409  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98410  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98411  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98412  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98413  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98414  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98415  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98416  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98417  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98418  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98419  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98420  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98421  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98422  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98423  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98424  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98425  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98426  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98427  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98428  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98429  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98430  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98431  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98432  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98433  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98434  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98435  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98436  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98437  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98438  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98439  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98440  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98441  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98442  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98443  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98444  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98445  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98446  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98447  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98448  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98449  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98450 };
98451 
98457 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98458 {
98459  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98460  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98461  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98462  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98463  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98464  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98465  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98466  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98467  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98468  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98469  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98470  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98471  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98472  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98473  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98475  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98509  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98511  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98512  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98513  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98515  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98519  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98521  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98522  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98523  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98525  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98541 };
98542 
98548 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98549 {
98550  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98551  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98552  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98553  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98554  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98555  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98556  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98557  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98558  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98559  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98560  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98561  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98562  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98563  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98564  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98565  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98566  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98567  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98568  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98569  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98570  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98571  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98572  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98573  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98574  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98575  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98576  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98577  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98578  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98579  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98580  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98581  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98582  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98583  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98584  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98585  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98586  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98587  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98588  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98589  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98590  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98591  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98592  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98593  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98594  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98595  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98596  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98597  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98598  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98599  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98600  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98601  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98602  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98603  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98604  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98605  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98606  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98607  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98608  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98609  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98610  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98611  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98612  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98613  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98614  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98615  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98616  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98617  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98618  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98619  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98620  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98621  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98622  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98623  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98624  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98625  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98626  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98627  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98628  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98629  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98630  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98631  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98632 };
98633 
98639 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98640 {
98641  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98642  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98643  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98644  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98645  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98646  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98655  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98656  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98657  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98658  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98699  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98700  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98701  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98702  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98703  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98704  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98705  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98706  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98707  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98708  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98709  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98710  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98711  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98712  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98713  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98714  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98715  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98716  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98717  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98718  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98719  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98720  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98721  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98722  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98723 };
98724 
98730 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98731 {
98732  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98733  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98734  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98735  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98736  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98737  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98738  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98739  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98740  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98741  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98742  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98743  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98744  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98745  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98746  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98747  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98748  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98749  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98750  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98751  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98752  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98753  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98754  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98755  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98756  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98757  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98758  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98759  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98760  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98761  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98762  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98763  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98764  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98765  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98766  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98767  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98768  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98769  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98770  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98771  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98772  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98773  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98774  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98775  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98776  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98777  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98778  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98779  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98780  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98781  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98782  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98783  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98784  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98785  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98786  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98787  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98788  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98789  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98790  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98791  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98792  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98793  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98794  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98795  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98796  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98797  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98798  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98799  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98800  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98801  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98802  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98803  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98804  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98805  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98806  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98807  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98808  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98809  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98810  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98811  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
98815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
98816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
98817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
98818 };
98819 
98825 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98826 {
98827  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98828  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98829  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98830  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98831  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98832  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98833  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98834  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98835  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98836  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98837  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98838  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98839  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98840  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98841  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98842  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98843  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98844  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98845  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98846  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98847  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98848  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98849  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98850  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98851  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98852  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98853  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98854  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98855  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98856  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98857  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98858  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98859  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98860  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98861  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98862  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98863  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98864  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98865  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98866  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98867  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98868  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98869  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98870  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98871  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98872  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98873  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98874  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98875  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98876  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98877  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98878  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98879  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98880  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98881  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98882  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98883  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98884  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98885  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98886  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98887  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98888  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98889  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98890  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98891  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98892  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98893  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98894  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98895  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98896  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98897  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98898  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98899  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98900  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98901  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98902  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98903  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98904  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98905  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98906  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98907  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98908  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
98909 };
98910 
98916 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
98917 {
98918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
98919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
98920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
98921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
98922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
98923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
98924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
98925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
98926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
98927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
98928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
98929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
98930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
98931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
98932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
98933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
98934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
98935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
98936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
98937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
98938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
98939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
98940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
98941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
98942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
98943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
98944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
98945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
98946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
98947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
98948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
98949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
98950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
98951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
98952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
98953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
98954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
98955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
98956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
98957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
98958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
98959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
98960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
98961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
98962  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
98963  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
98964  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
98965  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
98966  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
98967  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
98968  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
98969  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
98970  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
98971  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
98972  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
98973  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
98974  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
98975  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
98976  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
98977  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
98978  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
98979  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
98980  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
98981  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
98982  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
98983  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
98984  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
98985  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
98986  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
98987  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
98988  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
98989  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
98990  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
98991  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
98992  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
98993  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
98994  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
98995  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
98996  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
98997  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
98998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
98999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
99000 };
99001 
99007 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99008 {
99009  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99010  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99011  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99012  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99013  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99014  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99015  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99016  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99017  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99018  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99019  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99020  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99021  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99022  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99023  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99024  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99025  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99026  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99027  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99028  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99029  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99030  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99031  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99032  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99033  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99034  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99035  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99036  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99037  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99038  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99039  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99040  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99041  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99042  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99043  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99044  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99045  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99046  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99047  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99048  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99049  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99050  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99051  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99052  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99053  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99054  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99055  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
99056  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
99057  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
99058  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
99059  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
99060  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
99061  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
99062  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
99063  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
99064  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
99065  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
99066  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
99067  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
99068  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
99069  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
99070  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
99071  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
99072  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
99073  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
99074  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
99075  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
99076  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
99077  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
99078  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
99079  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
99080  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
99081  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
99082  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
99083  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
99084  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
99085  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
99086  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
99087  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
99088  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
99089  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
99090  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
99091 };
99092 
99098 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99099 {
99100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
99147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
99148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
99149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
99150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
99151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
99152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
99153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
99154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
99155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
99156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
99157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
99158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
99159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
99160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
99161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
99162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
99163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
99164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
99165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
99166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
99167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
99168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
99169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
99170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
99171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
99172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
99173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
99174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
99175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
99176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
99177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
99178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
99179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
99180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
99181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
99182 };
99183 
99189 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99190 {
99191  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99192  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99193  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99194  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99195  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99196  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99197  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99198  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99199  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99200  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99201  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99202  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99203  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99204  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99205  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99206  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99207  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99208  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99209  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99210  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99211  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99212  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99213  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99214  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99215  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99216  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99217  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99218  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99219  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99220  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99221  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99222  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99223  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99224  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99225  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99226  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99227  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99228  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99229  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99230  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99231  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99232  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99233  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99234  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99235  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99236  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99237  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
99238  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
99239  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
99240  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
99241  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
99242  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
99243  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
99244  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
99245  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
99246  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
99247  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
99248  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
99249  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
99250  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
99251  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
99252  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
99253  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
99254  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
99255  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
99256  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
99257  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
99258  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
99259  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
99260  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
99261  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
99262  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
99263  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
99264  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
99265  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
99266  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
99267  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
99268  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
99269  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
99270  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
99271  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
99272  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
99273 };
99274 
99280 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99281 {
99282  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99283  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99284  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99285  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99286  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99287  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99288  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99289  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99290  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99291  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99292  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99293  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99294  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99295  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99296  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99297  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99298  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99299  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99300  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99301  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99302  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99303  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99304  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99305  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99306  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99307  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99308  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99309  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99310  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99311  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99312  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99313  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99314  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99315  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99316  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99317  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99318  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99319  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99320  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99321  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99322  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99323  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99324  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99325  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99326  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99327  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99328  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
99329  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
99330  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
99331  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
99332  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
99333  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
99334  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
99335  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
99336  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
99337  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
99338  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
99339  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
99340  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
99341  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
99342  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
99343  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
99344  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
99345  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
99346  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
99347  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
99348  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
99349  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
99350  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
99351  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
99352  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
99353  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
99354  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
99355  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
99356  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
99357  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
99358  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
99359  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
99360  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
99361  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
99362  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
99363  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
99364 };
99365 
99371 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99372 {
99373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99395  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99399  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99401  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99402  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99403  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99405  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99409  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99411  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99412  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99413  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99415  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
99420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
99421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
99422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
99423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
99424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
99425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
99426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
99427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
99428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
99429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
99430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
99431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
99432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
99433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
99434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
99435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
99436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
99437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
99438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
99439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
99440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
99441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
99442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
99443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
99444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
99445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
99446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
99447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
99448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
99449  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
99450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
99451  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
99452  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
99453  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
99454  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
99455 };
99456 
99462 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99463 {
99464  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99465  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99466  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99467  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99468  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99469  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99470  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99471  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99472  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99473  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99474  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99475  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99476  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99477  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99478  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99479  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99480  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99481  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99482  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99483  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99484  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99485  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99486  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99487  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99488  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99489  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99490  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99491  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99492  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99493  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99494  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99495  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99496  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99497  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99498  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99499  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99500  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99501  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99502  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99503  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99504  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99505  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99506  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99507  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99508  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99509  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99510  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
99511  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
99512  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
99513  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
99514  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
99515  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
99516  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
99517  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
99518  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
99519  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
99520  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
99521  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
99522  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
99523  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
99524  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
99525  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
99526  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
99527  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
99528  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
99529  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
99530  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
99531  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
99532  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
99533  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
99534  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
99535  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
99536  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
99537  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
99538  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
99539  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
99540  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
99541  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
99542  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
99543  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
99544  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
99545  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
99546 };
99547 
99553 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99554 {
99555  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99559  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99561  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99562  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99569  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99571  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99572  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99573  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99574  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99575  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99576  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99577  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99578  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99579  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99580  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99581  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99582  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99583  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99584  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99585  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99586  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99589  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99591  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99592  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99595 };
99596 
99602 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99603 {
99604  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99605  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99606  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99607  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99608  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99609  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99610  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99611  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99612  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99613  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99614  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99615  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99616  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99617  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99618  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99619  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99620  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99621  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99622  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99623  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99624  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99625  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99626  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99627  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99628  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99629  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99630  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99631  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99632  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99633  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99634  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99635  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99636  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99637  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99638  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99639  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99640  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99641  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99642  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99643  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99644  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99645  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99646  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99647  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99648  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99649  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99650 };
99651 
99657 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99658 {
99659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99699 };
99700 
99706 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99707 {
99708  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99709  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99710  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99711  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99712  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99713  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99714  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99715  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99716  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99717  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99718  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99719  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99720  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99721  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99722  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99723  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99724  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99725  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99726  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99727  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99728  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99729  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99730  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99731  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99732  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99733  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99734  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99735  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99736  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99737  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99738  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99739  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99740  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99741  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99742  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99743  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99744  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99745  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99746  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99747  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99748  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99749  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99750  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99751  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99752  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99753  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99754 };
99755 
99761 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99762 {
99763  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99764  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99765  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99766  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99767  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99768  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99769  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99770  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99771  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99772  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99773  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99774  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99775  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99776  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99777  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99778  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99779  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99780  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99781  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99782  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99783  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99784  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99785  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99786  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99787  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99788  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99789  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99790  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99791  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99792  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99793  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99794  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99795  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99796  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99797  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99798  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99799  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99800  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99801  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99802  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99803 };
99804 
99810 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99811 {
99812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99818  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99819  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99820  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99821  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99858 };
99859 
99865 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99866 {
99867  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99868  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99869  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99870  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99871  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99872  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99873  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99874  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99875  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99876  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99877  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99878  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99879  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99880  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99881  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99882  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99883  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99884  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99885  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99886  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99887  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99888  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99889  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99890  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99891  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99892  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99893  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99894  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99895  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99896  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99897  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99898  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99899  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99900  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99901  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99902  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99903  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99904  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99905  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99906  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99907 };
99908 
99914 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99915 {
99916  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99917  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
99945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
99946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
99947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
99948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
99949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
99950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
99951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
99952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
99953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
99954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
99955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
99956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
99957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
99958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
99959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
99960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
99961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
99962 };
99963 
99969 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
99970 {
99971  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
99972  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
99973  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
99974  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
99975  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
99976  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
99977  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
99978  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
99979  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
99980  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
99981  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
99982  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
99983  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
99984  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
99985  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
99986  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
99987  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
99988  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
99989  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
99990  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
99991  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
99992  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
99993  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
99994  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
99995  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
99996  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
99997  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
99998  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
99999  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100000  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100001  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100002  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100003  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100004  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100005  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100006  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100007  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100008  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100009  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100010  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100011 };
100012 
100018 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100019 {
100020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
100061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
100062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
100063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
100064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
100065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
100066 };
100067 
100073 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100074 {
100075  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100076  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100077  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100078  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100079  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100080  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100081  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100082  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100083  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100084  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100085  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100086  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100087  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100088  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100089  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100090  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100091  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100092  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100093  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100094  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100095  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100096  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100097  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100098  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100099  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100100  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100101  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100102  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100103  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100104  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100105  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100106  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100107  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100108  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100109  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100110  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100111  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100112  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100113  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100114  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100115 };
100116 
100122 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100123 {
100124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
100165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
100166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
100167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
100168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
100169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
100170 };
100171 
100177 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100178 {
100179  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100180  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100181  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100182  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100183  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100184  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100185  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100186  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100187  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100188  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100189  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100190  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100191  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100192  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100193  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100194  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100195  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100196  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100197  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100198  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100199  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100200  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100201  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100202  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100203  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100204  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100205  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100206  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100207  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100208  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100209  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100210  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100211  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100212  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100213  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100214  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100215  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100216  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100217  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100218  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100219  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
100220  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
100221  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
100222  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
100223  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
100224  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
100225  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
100226  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
100227  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
100228  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
100229  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
100230  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
100231  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
100232  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
100233  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
100234  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
100235  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
100236  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
100237  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
100238  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
100239  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
100240  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
100241  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
100242  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
100243  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
100244  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
100245  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
100246  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
100247  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
100248  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
100249  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
100250  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
100251  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
100252  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
100253  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
100254  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
100255  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
100256  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
100257  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
100258  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
100259  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
100260  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
100261 };
100262 
100268 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
100269 {
100270  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
100271  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
100272  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
100273  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
100274  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
100275  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
100276  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
100277  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
100278  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
100279  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
100280  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
100281  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
100282  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
100283  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
100284  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
100285  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
100286  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
100287  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
100288  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
100289  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
100290  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
100291  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
100292  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
100293  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
100294  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
100295  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
100296  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
100297  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
100298  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
100299  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
100300 };
100301 
100307 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
100308 {
100309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
100310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
100311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
100312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
100313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
100314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
100315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
100316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
100317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
100318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
100319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
100320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
100321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
100322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
100323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
100324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
100325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
100326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
100327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
100328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
100329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
100330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
100331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
100332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
100333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
100334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
100335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
100336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
100337 };
100338 
100344 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100345 {
100346  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100347  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100348  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100349  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100350  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100351  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100352  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100353  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100354  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100355  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100356  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100357  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100358  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100359  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100360  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100361  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100362  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100363  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100364  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100365  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100366  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100367  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100368  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100369  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100370  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100371  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100372  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100373  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100374  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100375  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100376  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100377  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100378  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100379  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100380  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100381  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100382  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100383  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100384  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100385  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100386  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
100387  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
100388  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
100389  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
100390  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
100391  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
100392  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
100393  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
100394  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
100395  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
100396  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
100397  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
100398  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
100399  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
100400  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
100401  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
100402  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
100403  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
100404  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
100405  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
100406  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
100407  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
100408  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
100409  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
100410  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
100411  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
100412  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
100413  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
100414  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
100415  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
100416  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
100417  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
100418  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
100419  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
100420  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
100421  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
100422  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
100423  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
100424  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
100425  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
100426  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
100427  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
100428 };
100429 
100435 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100436 {
100437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100449  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100451  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100452  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100453  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100454  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100455  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100456  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100457  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100458  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100459  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100460  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100461  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100462  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100463  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100464  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100465  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100466  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100467  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100468  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100469  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100470  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100471  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100472  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100473  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100475  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
100478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
100479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
100480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
100481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
100482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
100483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
100484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
100485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
100486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
100487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
100488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
100489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
100490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
100491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
100492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
100493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
100494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
100495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
100496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
100497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
100498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
100499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
100500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
100501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
100502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
100503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
100504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
100505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
100506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
100507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
100508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
100509  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
100510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
100511  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
100512  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
100513  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
100514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
100515  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
100516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
100517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
100518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
100519 };
100520 
100526 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100527 {
100528  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100529  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100530  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100531  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100532  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100533  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100534  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100535  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100536  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100537  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100538  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100539  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100540  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100541  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100542  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100543  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100544  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100545  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100546  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100547  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100548  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100549  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100550  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100551  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100552  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100553  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100554  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100555  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100556  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100557  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100558  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100559  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100560  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100561  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100562  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100563  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100564  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100565  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100566  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100567  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100568  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
100569  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
100570  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
100571  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
100572  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
100573  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
100574  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
100575  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
100576  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
100577  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
100578  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
100579  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
100580  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
100581  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
100582  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
100583  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
100584  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
100585  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
100586  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
100587  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
100588  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
100589  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
100590  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
100591  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
100592  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
100593  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
100594  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
100595  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
100596  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
100597  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
100598  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
100599  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
100600  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
100601  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
100602  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
100603  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
100604  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
100605  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
100606  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
100607  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
100608  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
100609  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
100610 };
100611 
100617 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
100618 {
100619  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
100620  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
100621  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
100622  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
100623  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
100624  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
100625  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
100626  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
100627  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
100628  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
100629  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
100630  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
100631  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
100632  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
100633  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
100634  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
100635  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
100636  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
100637  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
100638  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
100639  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
100640  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
100641  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
100642  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
100643  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
100644  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
100645  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
100646  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
100647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
100648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
100649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
100650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
100651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
100652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
100653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
100654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
100655  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
100656  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
100657  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
100658  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
100659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
100660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
100661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
100662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
100663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
100664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
100665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
100666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
100667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
100668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
100669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
100670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
100671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
100672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
100673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
100674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
100675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
100676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
100677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
100678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
100679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
100680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
100681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
100682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
100683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
100684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
100685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
100686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
100687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
100688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
100689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
100690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
100691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
100692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
100693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
100694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
100695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
100696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
100697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
100698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
100699  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
100700  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
100701 };
100702 
100708 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
100709 {
100710  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
100711  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
100712  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
100713  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
100714  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
100715  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
100716  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
100717  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
100718  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
100719  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
100720  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
100721  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
100722  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
100723  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
100724  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
100725  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
100726  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
100727  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
100728  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
100729  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
100730  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
100731  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
100732  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
100733  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
100734  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
100735  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
100736  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
100737  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
100738  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
100739  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
100740  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
100741  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
100742  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
100743  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
100744  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
100745  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
100746  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
100747  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
100748  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
100749  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
100750  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
100751  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
100752  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
100753  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
100754  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
100755  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
100756  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
100757  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
100758  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
100759  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
100760  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
100761  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
100762  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
100763  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
100764  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
100765  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
100766  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
100767  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
100768  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
100769  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
100770  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
100771  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
100772  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
100773  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
100774  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
100775  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
100776  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
100777  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
100778  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
100779  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
100780  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
100781  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
100782  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
100783  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
100784  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
100785  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
100786  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
100787  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
100788  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
100789  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
100790  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
100791  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
100792  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
100793  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
100794  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
100795  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
100796  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
100797  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
100798  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
100799  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
100800  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
100801  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
100802  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
100803  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
100804  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
100805  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
100806  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
100807  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
100808  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
100809  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
100810  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
100811  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
100812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
100813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
100814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
100815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
100816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
100817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
100818  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
100819  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
100820  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
100821  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
100822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
100823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
100824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
100825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
100826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
100827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
100828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
100829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
100830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
100831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
100832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
100833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
100834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
100835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
100836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
100837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
100838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
100839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
100840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
100841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
100842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
100843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
100844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
100845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
100846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
100847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
100848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
100849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
100850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
100851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
100852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
100853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
100854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
100855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
100856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
100857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
100858  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
100859  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
100860  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
100861  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
100862  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
100863  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
100864  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
100865  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
100866  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
100867  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
100868  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
100869  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
100870  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
100871  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
100872  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
100873  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
100874  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
100875  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
100876  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
100877  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
100878  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
100879  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
100880  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
100881  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
100882  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
100883  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
100884  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
100885  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
100886  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
100887  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
100888  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
100889  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
100890  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
100891  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
100892  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
100893  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
100894  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
100895  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
100896  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
100897  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
100898  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
100899  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
100900  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
100901  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
100902  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
100903  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
100904  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
100905  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
100906  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
100907  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
100908  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
100909  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
100910  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
100911  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
100912  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
100913  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
100914  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
100915  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
100916  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
100917  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
100918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
100919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
100920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
100921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
100922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
100923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
100924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
100925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
100926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
100927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
100928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
100929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
100930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
100931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
100932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
100933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
100934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
100935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
100936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
100937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
100938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
100939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
100940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
100941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
100942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
100943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
100944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
100945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
100946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
100947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
100948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
100949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
100950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
100951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
100952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
100953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
100954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
100955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
100956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
100957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
100958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
100959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
100960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
100961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
100962  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
100963  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
100964  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
100965  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
100966  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
100967  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
100968  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
100969  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
100970  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
100971  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
100972  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
100973  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
100974  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
100975  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
100976  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
100977  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
100978  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
100979  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
100980  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
100981  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
100982  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
100983  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
100984  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
100985  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
100986  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
100987  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
100988  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
100989  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
100990  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
100991  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
100992  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
100993  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
100994  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
100995  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
100996  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
100997  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
100998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
100999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
101000  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
101001  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
101002  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
101003  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
101004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
101005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
101006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
101007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
101008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
101009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
101010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
101011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
101012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
101013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
101014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
101015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
101016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
101017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
101018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
101019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
101020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
101021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
101022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
101023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
101024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
101025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
101026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
101027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
101028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
101029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
101030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
101031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
101032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
101033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
101034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
101035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
101036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
101037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
101038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
101039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
101040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
101041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
101042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
101043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
101044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
101045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
101046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
101047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
101048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
101049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
101050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
101051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
101052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
101053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
101054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
101055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
101056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
101057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
101058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
101059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
101060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
101061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
101062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
101063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
101064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
101065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
101066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
101067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
101068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
101069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
101070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
101071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
101072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
101073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
101074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
101075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
101076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
101077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
101078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
101079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
101080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
101081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
101082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
101083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
101084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
101085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
101086  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
101087  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
101088  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
101089  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
101090  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
101091  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
101092  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
101093  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
101094  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
101095  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
101096  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
101097  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
101098  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
101099  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
101100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
101101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
101102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
101103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
101104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
101105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
101106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
101107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
101108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
101109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
101110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
101111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
101112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
101113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
101114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
101115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
101116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
101117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
101118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
101119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
101120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
101121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
101122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
101123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
101124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
101125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
101126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
101127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
101128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
101129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
101130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
101131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
101132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
101133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
101134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
101135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
101136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
101137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
101138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
101139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
101140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
101141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
101142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
101143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
101144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
101145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
101146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
101147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
101148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
101149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
101150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
101151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
101152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
101153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
101154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
101155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
101156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
101157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
101158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
101159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
101160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
101161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
101162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
101163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
101164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
101165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
101166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
101167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
101168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
101169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
101170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
101171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
101172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
101173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
101174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
101175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
101176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
101177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
101178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
101179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
101180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
101181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
101182  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
101183  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
101184  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
101185  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
101186  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
101187  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
101188  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
101189  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
101190  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
101191  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
101192  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
101193  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
101194  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
101195  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
101196  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
101197  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
101198  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
101199  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
101200  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
101201  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
101202  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
101203  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
101204  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
101205  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
101206  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
101207  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
101208  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
101209  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
101210  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
101211  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
101212  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
101213  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
101214  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
101215  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
101216  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
101217  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
101218  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
101219  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
101220  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
101221  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
101222 };
101223 
101229 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
101230 {
101231  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
101232  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
101233  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
101234  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
101235  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
101236  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
101237  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
101238  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
101239  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
101240  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
101241  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
101242  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
101243  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
101244  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
101245  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
101246  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
101247  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
101248  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
101249  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
101250  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
101251  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
101252  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
101253  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
101254  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
101255  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
101256  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
101257  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
101258  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
101259  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
101260  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
101261  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
101262  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
101263  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
101264  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
101265  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
101266  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
101267  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
101268  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
101269  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
101270  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
101271  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
101272  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
101273  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
101274  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
101275  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
101276  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
101277  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
101278  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
101279  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
101280  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
101281  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
101282  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
101283  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
101284  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
101285  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
101286  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
101287  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
101288  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
101289  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
101290  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
101291  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
101292  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
101293  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
101294  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
101295  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
101296  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
101297  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
101298  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
101299  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
101300  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
101301  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
101302  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
101303  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
101304  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
101305  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
101306  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
101307  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
101308  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
101309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
101310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
101311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
101312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
101313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
101314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
101315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
101316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
101317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
101318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
101319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
101320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
101321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
101322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
101323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
101324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
101325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
101326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
101327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
101328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
101329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
101330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
101331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
101332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
101333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
101334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
101335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
101336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
101337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
101338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
101339  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
101340  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
101341  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
101342  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
101343  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
101344  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
101345  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
101346  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
101347  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
101348  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
101349  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
101350  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
101351  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
101352  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
101353  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
101354  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
101355  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
101356  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
101357  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
101358  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
101359  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
101360  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
101361  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
101362  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
101363  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
101364  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
101365  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
101366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
101367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
101368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
101369  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
101370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
101371  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
101372  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
101373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
101374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
101375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
101376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
101377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
101378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
101379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
101380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
101381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
101382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
101383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
101384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
101385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
101386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
101387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
101388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
101389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
101390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
101391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
101392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
101393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
101394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
101395  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
101396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
101397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
101398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
101399  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
101400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
101401  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
101402  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
101403  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
101404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
101405  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
101406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
101407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
101408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
101409  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
101410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
101411  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
101412  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
101413  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
101414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
101415  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
101416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
101417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
101418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
101419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
101420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
101421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
101422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
101423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
101424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
101425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
101426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
101427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
101428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
101429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
101430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
101431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
101432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
101433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
101434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
101435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
101436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
101437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
101438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
101439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
101440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
101441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
101442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
101443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
101444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
101445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
101446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
101447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
101448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
101449  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
101450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
101451  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
101452  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
101453  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
101454  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
101455  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
101456  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
101457  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
101458  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
101459  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
101460  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
101461  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
101462  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
101463  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
101464  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
101465  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
101466  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
101467  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
101468  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
101469  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
101470  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
101471  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
101472  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
101473  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
101474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
101475  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
101476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
101477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
101478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
101479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
101480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
101481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
101482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
101483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
101484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
101485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
101486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
101487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
101488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
101489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
101490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
101491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
101492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
101493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
101494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
101495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
101496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
101497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
101498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
101499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
101500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
101501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
101502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
101503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
101504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
101505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
101506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
101507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
101508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
101509  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
101510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
101511  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
101512  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
101513  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
101514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
101515  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
101516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
101517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
101518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
101519  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
101520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
101521  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
101522  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
101523  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
101524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
101525  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
101526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
101527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
101528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
101529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
101530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
101531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
101532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
101533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
101534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
101535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
101536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
101537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
101538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
101539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
101540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
101541  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
101542  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
101543  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
101544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
101545  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
101546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
101547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
101548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
101549  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
101550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
101551  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
101552  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
101553  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
101554  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
101555  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
101556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
101557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
101558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
101559  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
101560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
101561  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
101562  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
101563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
101564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
101565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
101566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
101567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
101568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
101569  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
101570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
101571  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
101572  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
101573  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
101574  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
101575  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
101576  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
101577  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
101578  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
101579  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
101580  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
101581  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
101582  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
101583  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
101584  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
101585  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
101586  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
101587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
101588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
101589  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
101590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
101591  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
101592  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
101593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
101594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
101595  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
101596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
101597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
101598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
101599  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
101600  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
101601  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
101602  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
101603  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
101604  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
101605  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
101606  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
101607  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
101608  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
101609  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
101610  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
101611  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
101612  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
101613  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
101614  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
101615  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
101616  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
101617  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
101618  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
101619  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
101620  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
101621  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
101622  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
101623  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
101624  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
101625  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
101626  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
101627  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
101628  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
101629  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
101630  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
101631  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
101632  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
101633  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
101634  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
101635  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
101636  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
101637  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
101638  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
101639  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
101640  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
101641  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
101642  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
101643  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
101644  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
101645  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
101646  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
101647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
101648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
101649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
101650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
101651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
101652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
101653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
101654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
101655  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
101656  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
101657  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
101658  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
101659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
101660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
101661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
101662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
101663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
101664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
101665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
101666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
101667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
101668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
101669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
101670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
101671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
101672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
101673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
101674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
101675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
101676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
101677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
101678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
101679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
101680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
101681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
101682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
101683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
101684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
101685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
101686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
101687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
101688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
101689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
101690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
101691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
101692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
101693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
101694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
101695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
101696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
101697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
101698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
101699  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
101700  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
101701  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
101702  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
101703  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
101704  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
101705  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
101706  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
101707  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
101708  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
101709  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
101710  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
101711  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
101712  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
101713  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
101714  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
101715  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
101716  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
101717  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
101718  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
101719  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
101720  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
101721  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
101722  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
101723  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
101724  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
101725  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
101726  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
101727  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
101728  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
101729  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
101730  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
101731  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
101732  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
101733  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
101734  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
101735  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
101736  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
101737  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
101738  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
101739  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
101740  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
101741  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
101742  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
101743 };
101744 
101750 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
101751 {
101752  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
101753  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
101754  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
101755  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
101756  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
101757  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
101758  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
101759  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
101760  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
101761  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
101762  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
101763  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
101764  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
101765  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
101766  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
101767  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
101768  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
101769  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
101770  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
101771  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
101772  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
101773  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
101774  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
101775  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
101776  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
101777  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
101778  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
101779  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
101780  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
101781  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
101782  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
101783  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
101784  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
101785  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
101786  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
101787  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
101788  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
101789  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
101790  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
101791  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
101792  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
101793  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
101794  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
101795  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
101796  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
101797  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
101798  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
101799  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
101800  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
101801  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
101802  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
101803  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
101804  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
101805  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
101806  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
101807  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
101808  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
101809  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
101810  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
101811  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
101812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
101813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
101814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
101815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
101816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
101817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
101818  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
101819  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
101820  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
101821  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
101822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
101823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
101824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
101825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
101826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
101827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
101828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
101829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
101830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
101831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
101832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
101833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
101834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
101835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
101836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
101837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
101838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
101839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
101840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
101841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
101842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
101843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
101844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
101845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
101846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
101847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
101848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
101849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
101850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
101851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
101852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
101853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
101854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
101855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
101856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
101857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
101858  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
101859  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
101860  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
101861  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
101862  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
101863  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
101864  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
101865  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
101866  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
101867  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
101868  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
101869  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
101870  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
101871  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
101872  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
101873  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
101874  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
101875  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
101876  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
101877  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
101878  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
101879  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
101880  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
101881  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
101882  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
101883  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
101884  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
101885  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
101886  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
101887  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
101888  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
101889  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
101890  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
101891  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
101892  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
101893  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
101894  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
101895  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
101896  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
101897  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
101898  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
101899  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
101900  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
101901  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
101902  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
101903  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
101904  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
101905  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
101906  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
101907  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
101908  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
101909  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
101910  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
101911  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
101912  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
101913  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
101914  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
101915  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
101916  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
101917  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
101918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
101919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
101920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
101921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
101922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
101923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
101924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
101925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
101926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
101927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
101928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
101929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
101930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
101931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
101932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
101933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
101934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
101935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
101936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
101937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
101938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
101939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
101940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
101941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
101942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
101943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
101944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
101945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
101946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
101947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
101948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
101949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
101950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
101951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
101952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
101953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
101954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
101955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
101956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
101957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
101958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
101959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
101960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
101961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
101962  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
101963  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
101964  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
101965  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
101966  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
101967  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
101968  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
101969  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
101970  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
101971  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
101972  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
101973  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
101974  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
101975  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
101976  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
101977  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
101978  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
101979  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
101980  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
101981  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
101982  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
101983  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
101984  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
101985  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
101986  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
101987  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
101988  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
101989  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
101990  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
101991  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
101992  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
101993  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
101994  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
101995  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
101996  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
101997  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
101998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
101999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
102000  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
102001  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
102002  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
102003  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
102004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
102005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
102006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
102007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
102008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
102009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
102010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
102011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
102012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
102013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
102014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
102015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
102016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
102017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
102018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
102019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
102020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
102021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
102022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
102023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
102024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
102025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
102026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
102027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
102028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
102029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
102030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
102031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
102032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
102033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
102034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
102035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
102036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
102037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
102038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
102039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
102040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
102041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
102042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
102043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
102044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
102045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
102046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
102047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
102048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
102049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
102050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
102051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
102052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
102053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
102054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
102055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
102056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
102057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
102058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
102059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
102060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
102061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
102062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
102063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
102064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
102065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
102066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
102067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
102068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
102069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
102070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
102071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
102072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
102073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
102074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
102075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
102076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
102077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
102078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
102079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
102080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
102081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
102082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
102083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
102084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
102085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
102086  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
102087  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
102088  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
102089  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
102090  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
102091  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
102092  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
102093  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
102094  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
102095  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
102096  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
102097  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
102098  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
102099  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
102100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
102101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
102102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
102103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
102104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
102105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
102106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
102107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
102108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
102109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
102110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
102111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
102112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
102113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
102114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
102115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
102116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
102117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
102118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
102119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
102120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
102121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
102122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
102123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
102124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
102125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
102126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
102127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
102128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
102129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
102130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
102131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
102132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
102133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
102134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
102135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
102136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
102137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
102138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
102139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
102140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
102141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
102142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
102143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
102144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
102145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
102146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
102147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
102148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
102149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
102150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
102151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
102152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
102153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
102154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
102155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
102156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
102157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
102158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
102159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
102160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
102161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
102162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
102163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
102164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
102165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
102166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
102167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
102168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
102169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
102170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
102171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
102172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
102173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
102174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
102175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
102176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
102177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
102178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
102179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
102180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
102181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
102182  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
102183  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
102184  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
102185  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
102186  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
102187  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
102188  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
102189  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
102190  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
102191  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
102192  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
102193  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
102194  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
102195  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
102196  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
102197  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
102198  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
102199  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
102200  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
102201  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
102202  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
102203  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
102204  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
102205  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
102206  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
102207  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
102208  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
102209  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
102210  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
102211  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
102212  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
102213  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
102214  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
102215  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
102216  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
102217  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
102218  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
102219  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
102220  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
102221  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
102222  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
102223  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
102224  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
102225  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
102226  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
102227  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
102228  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
102229  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
102230  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
102231  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
102232  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
102233  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
102234  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
102235  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
102236  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
102237  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
102238  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
102239  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
102240  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
102241  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
102242  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
102243  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
102244  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
102245  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
102246  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
102247  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
102248  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
102249  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
102250  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
102251  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
102252  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
102253  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
102254  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
102255  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
102256  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
102257  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
102258  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
102259  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
102260  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
102261  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
102262  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
102263  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
102264 };
102265 
102271 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
102272 {
102273  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
102274  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
102275  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
102276  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
102277  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
102278  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
102279  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
102280  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
102281  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
102282  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
102283  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
102284  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
102285  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
102286  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
102287  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
102288  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
102289  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
102290  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
102291  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
102292  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
102293  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
102294  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
102295  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
102296  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
102297  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
102298  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
102299  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
102300  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
102301  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
102302  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
102303  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
102304  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
102305  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
102306  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
102307  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
102308  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
102309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
102310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
102311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
102312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
102313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
102314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
102315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
102316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
102317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
102318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
102319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
102320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
102321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
102322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
102323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
102324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
102325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
102326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
102327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
102328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
102329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
102330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
102331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
102332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
102333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
102334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
102335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
102336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
102337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
102338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
102339  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
102340  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
102341  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
102342  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
102343  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
102344  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
102345  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
102346  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
102347  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
102348  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
102349  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
102350  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
102351  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
102352  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
102353  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
102354  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
102355  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
102356  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
102357  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
102358  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
102359  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
102360  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
102361  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
102362  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
102363  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
102364  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
102365  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
102366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
102367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
102368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
102369  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
102370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
102371  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
102372  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
102373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
102374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
102375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
102376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
102377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
102378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
102379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
102380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
102381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
102382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
102383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
102384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
102385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
102386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
102387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
102388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
102389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
102390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
102391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
102392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
102393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
102394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
102395  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
102396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
102397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
102398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
102399  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
102400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
102401  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
102402  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
102403  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
102404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
102405  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
102406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
102407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
102408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
102409  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
102410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
102411  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
102412  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
102413  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
102414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
102415  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
102416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
102417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
102418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
102419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
102420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
102421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
102422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
102423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
102424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
102425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
102426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
102427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
102428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
102429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
102430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
102431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
102432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
102433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
102434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
102435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
102436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
102437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
102438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
102439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
102440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
102441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
102442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
102443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
102444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
102445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
102446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
102447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
102448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
102449  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
102450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
102451  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
102452  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
102453  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
102454  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
102455  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
102456  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
102457  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
102458  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
102459  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
102460  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
102461  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
102462  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
102463  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
102464  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
102465  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
102466  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
102467  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
102468  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
102469  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
102470  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
102471  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
102472  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
102473  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
102474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
102475  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
102476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
102477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
102478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
102479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
102480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
102481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
102482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
102483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
102484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
102485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
102486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
102487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
102488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
102489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
102490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
102491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
102492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
102493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
102494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
102495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
102496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
102497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
102498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
102499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
102500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
102501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
102502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
102503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
102504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
102505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
102506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
102507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
102508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
102509  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
102510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
102511  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
102512  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
102513  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
102514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
102515  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
102516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
102517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
102518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
102519  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
102520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
102521  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
102522  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
102523  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
102524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
102525  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
102526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
102527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
102528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
102529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
102530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
102531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
102532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
102533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
102534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
102535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
102536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
102537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
102538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
102539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
102540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
102541  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
102542  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
102543  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
102544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
102545  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
102546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
102547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
102548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
102549  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
102550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
102551  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
102552  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
102553  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
102554  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
102555  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
102556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
102557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
102558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
102559  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
102560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
102561  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
102562  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
102563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
102564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
102565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
102566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
102567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
102568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
102569  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
102570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
102571  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
102572  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
102573  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
102574  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
102575  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
102576  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
102577  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
102578  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
102579  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
102580  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
102581  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
102582  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
102583  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
102584  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
102585  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
102586  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
102587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
102588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
102589  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
102590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
102591  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
102592  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
102593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
102594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
102595  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
102596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
102597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
102598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
102599  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
102600  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
102601  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
102602  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
102603  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
102604  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
102605  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
102606  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
102607  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
102608  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
102609  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
102610  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
102611  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
102612  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
102613  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
102614  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
102615  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
102616  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
102617  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
102618  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
102619  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
102620  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
102621  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
102622  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
102623  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
102624  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
102625  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
102626  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
102627  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
102628  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
102629  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
102630  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
102631  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
102632  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
102633  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
102634  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
102635  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
102636  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
102637  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
102638  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
102639  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
102640  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
102641  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
102642  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
102643  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
102644  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
102645  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
102646  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
102647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
102648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
102649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
102650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
102651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
102652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
102653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
102654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
102655  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
102656  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
102657  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
102658  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
102659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
102660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
102661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
102662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
102663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
102664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
102665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
102666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
102667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
102668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
102669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
102670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
102671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
102672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
102673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
102674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
102675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
102676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
102677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
102678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
102679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
102680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
102681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
102682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
102683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
102684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
102685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
102686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
102687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
102688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
102689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
102690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
102691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
102692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
102693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
102694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
102695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
102696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
102697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
102698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
102699  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
102700  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
102701  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
102702  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
102703  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
102704  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
102705  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
102706  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
102707  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
102708  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
102709  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
102710  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
102711  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
102712  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
102713  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
102714  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
102715  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
102716  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
102717  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
102718  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
102719  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
102720  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
102721  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
102722  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
102723  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
102724  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
102725  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
102726  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
102727 };
102728 
102734 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
102735 {
102736  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
102737  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
102738  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
102739  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
102740  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
102741  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
102742  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
102743  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
102744  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
102745  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
102746  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
102747  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
102748  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
102749  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
102750  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
102751  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
102752  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
102753  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
102754  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
102755  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
102756  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
102757  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
102758  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
102759  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
102760  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
102761  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
102762  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
102763  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
102764  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
102765  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
102766  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
102767  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
102768  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
102769  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
102770  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
102771  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
102772  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
102773  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
102774  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
102775  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
102776  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
102777  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
102778  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
102779  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
102780  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
102781  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
102782  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
102783  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
102784  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
102785  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
102786  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
102787  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
102788  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
102789  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
102790  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
102791  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
102792  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
102793  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
102794  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
102795  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
102796  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
102797  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
102798  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
102799  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
102800  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
102801  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
102802  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
102803  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
102804  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
102805  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
102806  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
102807  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
102808  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
102809  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
102810  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
102811  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
102812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
102813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
102814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
102815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
102816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
102817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
102818  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
102819  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
102820  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
102821  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
102822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
102823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
102824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
102825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
102826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
102827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
102828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
102829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
102830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
102831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
102832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
102833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
102834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
102835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
102836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
102837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
102838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
102839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
102840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
102841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
102842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
102843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
102844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
102845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
102846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
102847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
102848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
102849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
102850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
102851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
102852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
102853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
102854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
102855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
102856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
102857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
102858  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
102859  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
102860  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
102861  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
102862  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
102863  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
102864  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
102865  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
102866  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
102867  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
102868  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
102869  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
102870  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
102871  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
102872  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
102873  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
102874  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
102875  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
102876  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
102877  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
102878  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
102879  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
102880  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
102881  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
102882  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
102883  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
102884  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
102885  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
102886  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
102887  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
102888  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
102889  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
102890  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
102891  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
102892  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
102893  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
102894  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
102895  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
102896  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
102897  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
102898  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
102899  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
102900  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
102901  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
102902  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
102903  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
102904  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
102905  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
102906  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
102907  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
102908  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
102909  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
102910  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
102911  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
102912  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
102913  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
102914  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
102915  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
102916  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
102917  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
102918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
102919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
102920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
102921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
102922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
102923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
102924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
102925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
102926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
102927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
102928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
102929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
102930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
102931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
102932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
102933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
102934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
102935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
102936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
102937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
102938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
102939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
102940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
102941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
102942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
102943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
102944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
102945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
102946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
102947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
102948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
102949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
102950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
102951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
102952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
102953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
102954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
102955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
102956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
102957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
102958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
102959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
102960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
102961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
102962  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
102963  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
102964  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
102965  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
102966  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
102967  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
102968  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
102969  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
102970  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
102971  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
102972  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
102973  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
102974  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
102975  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
102976  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
102977  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
102978  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
102979  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
102980  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
102981  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
102982  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
102983  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
102984  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
102985  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
102986  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
102987  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
102988  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
102989  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
102990  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
102991  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
102992  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
102993  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
102994  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
102995  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
102996  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
102997  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
102998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
102999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
103000  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
103001  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
103002  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
103003  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
103004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
103005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
103006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
103007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
103008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
103009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
103010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
103011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
103012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
103013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
103014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
103015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
103016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
103017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
103018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
103019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
103020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
103021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
103022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
103023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
103024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
103025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
103026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
103027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
103028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
103029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
103030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
103031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
103032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
103033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
103034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
103035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
103036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
103037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
103038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
103039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
103040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
103041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
103042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
103043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
103044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
103045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
103046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
103047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
103048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
103049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
103050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
103051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
103052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
103053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
103054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
103055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
103056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
103057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
103058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
103059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
103060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
103061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
103062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
103063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
103064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
103065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
103066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
103067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
103068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
103069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
103070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
103071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
103072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
103073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
103074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
103075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
103076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
103077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
103078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
103079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
103080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
103081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
103082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
103083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
103084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
103085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
103086  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
103087  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
103088  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
103089  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
103090  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
103091  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
103092  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
103093  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
103094  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
103095  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
103096  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
103097  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
103098  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
103099  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
103100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
103101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
103102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
103103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
103104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
103105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
103106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
103107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
103108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
103109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
103110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
103111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
103112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
103113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
103114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
103115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
103116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
103117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
103118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
103119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
103120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
103121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
103122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
103123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
103124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
103125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
103126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
103127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
103128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
103129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
103130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
103131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
103132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
103133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
103134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
103135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
103136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
103137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
103138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
103139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
103140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
103141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
103142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
103143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
103144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
103145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
103146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
103147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
103148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
103149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
103150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
103151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
103152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
103153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
103154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
103155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
103156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
103157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
103158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
103159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
103160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
103161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
103162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
103163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
103164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
103165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
103166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
103167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
103168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
103169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
103170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
103171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
103172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
103173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
103174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
103175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
103176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
103177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
103178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
103179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
103180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
103181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
103182  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
103183  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
103184  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
103185  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
103186  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
103187  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
103188  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
103189  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
103190  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
103191  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
103192  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
103193  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
103194  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
103195  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
103196  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
103197  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
103198  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
103199  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
103200  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
103201  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
103202  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
103203  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
103204  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
103205  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
103206  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
103207  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
103208  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
103209  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
103210  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
103211  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
103212  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
103213  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
103214  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
103215  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
103216  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
103217  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
103218  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
103219  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
103220  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
103221  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
103222  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
103223  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
103224  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
103225  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
103226  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
103227  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
103228  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
103229  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
103230  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
103231  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
103232  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
103233  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
103234  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
103235  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
103236  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
103237  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
103238  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
103239  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
103240  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
103241  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
103242  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
103243  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
103244  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
103245  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
103246  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
103247  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
103248 };
103249 
103255 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
103256 {
103257  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
103258  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
103259  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
103260  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
103261  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
103262  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
103263  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
103264  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
103265  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
103266  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
103267  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
103268  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
103269  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
103270  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
103271  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
103272  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
103273  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
103274  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
103275  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
103276  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
103277  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
103278  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
103279  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
103280  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
103281  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
103282  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
103283  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
103284  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
103285  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
103286  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
103287  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
103288  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
103289  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
103290  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
103291  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
103292  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
103293  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
103294  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
103295  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
103296  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
103297  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
103298  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
103299  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
103300  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
103301  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
103302  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
103303  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
103304  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
103305  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
103306  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
103307  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
103308  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
103309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
103310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
103311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
103312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
103313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
103314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
103315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
103316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
103317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
103318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
103319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
103320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
103321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
103322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
103323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
103324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
103325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
103326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
103327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
103328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
103329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
103330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
103331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
103332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
103333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
103334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
103335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
103336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
103337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
103338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
103339  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
103340  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
103341  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
103342  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
103343  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
103344  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
103345  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
103346  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
103347  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
103348  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
103349  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
103350  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
103351  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
103352  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
103353  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
103354  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
103355  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
103356  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
103357  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
103358  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
103359  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
103360  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
103361  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
103362  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
103363  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
103364  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
103365  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
103366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
103367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
103368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
103369  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
103370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
103371  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
103372  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
103373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
103374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
103375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
103376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
103377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
103378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
103379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
103380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
103381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
103382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
103383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
103384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
103385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
103386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
103387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
103388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
103389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
103390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
103391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
103392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
103393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
103394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
103395  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
103396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
103397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
103398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
103399  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
103400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
103401  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
103402  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
103403  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
103404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
103405  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
103406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
103407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
103408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
103409  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
103410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
103411  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
103412  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
103413  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
103414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
103415  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
103416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
103417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
103418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
103419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
103420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
103421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
103422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
103423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
103424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
103425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
103426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
103427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
103428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
103429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
103430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
103431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
103432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
103433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
103434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
103435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
103436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
103437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
103438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
103439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
103440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
103441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
103442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
103443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
103444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
103445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
103446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
103447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
103448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
103449  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
103450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
103451  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
103452  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
103453  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
103454  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
103455  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
103456  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
103457  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
103458  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
103459  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
103460  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
103461  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
103462  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
103463  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
103464  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
103465  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
103466  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
103467  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
103468  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
103469  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
103470  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
103471  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
103472  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
103473  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
103474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
103475  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
103476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
103477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
103478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
103479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
103480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
103481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
103482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
103483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
103484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
103485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
103486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
103487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
103488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
103489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
103490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
103491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
103492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
103493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
103494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
103495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
103496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
103497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
103498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
103499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
103500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
103501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
103502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
103503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
103504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
103505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
103506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
103507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
103508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
103509  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
103510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
103511  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
103512  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
103513  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
103514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
103515  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
103516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
103517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
103518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
103519  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
103520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
103521  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
103522  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
103523  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
103524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
103525  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
103526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
103527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
103528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
103529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
103530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
103531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
103532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
103533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
103534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
103535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
103536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
103537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
103538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
103539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
103540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
103541  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
103542  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
103543  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
103544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
103545  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
103546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
103547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
103548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
103549  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
103550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
103551  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
103552  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
103553  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
103554  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
103555  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
103556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
103557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
103558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
103559  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
103560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
103561  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
103562  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
103563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
103564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
103565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
103566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
103567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
103568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
103569  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
103570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
103571  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
103572  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
103573  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
103574  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
103575  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
103576  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
103577  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
103578  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
103579  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
103580  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
103581  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
103582  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
103583  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
103584  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
103585  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
103586  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
103587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
103588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
103589  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
103590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
103591  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
103592  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
103593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
103594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
103595  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
103596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
103597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
103598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
103599  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
103600  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
103601  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
103602  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
103603  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
103604  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
103605  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
103606  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
103607  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
103608  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
103609  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
103610  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
103611  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
103612  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
103613  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
103614  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
103615  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
103616  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
103617  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
103618  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
103619  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
103620  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
103621  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
103622  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
103623  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
103624  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
103625  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
103626  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
103627  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
103628  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
103629  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
103630  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
103631  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
103632  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
103633  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
103634  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
103635  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
103636  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
103637  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
103638  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
103639  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
103640  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
103641  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
103642  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
103643  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
103644  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
103645  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
103646  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
103647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
103648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
103649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
103650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
103651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
103652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
103653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
103654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
103655  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
103656  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
103657  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
103658  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
103659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
103660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
103661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
103662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
103663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
103664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
103665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
103666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
103667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
103668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
103669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
103670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
103671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
103672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
103673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
103674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
103675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
103676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
103677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
103678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
103679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
103680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
103681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
103682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
103683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
103684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
103685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
103686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
103687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
103688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
103689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
103690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
103691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
103692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
103693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
103694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
103695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
103696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
103697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
103698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
103699  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
103700  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
103701  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
103702  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
103703  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
103704  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
103705  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
103706  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
103707  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
103708  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
103709  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
103710  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
103711  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
103712  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
103713  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
103714  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
103715  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
103716  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
103717  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
103718  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
103719  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
103720  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
103721  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
103722  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
103723  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
103724  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
103725  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
103726  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
103727  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
103728  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
103729  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
103730  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
103731  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
103732  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
103733  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
103734  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
103735  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
103736  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
103737  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
103738  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
103739  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
103740  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
103741  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
103742  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
103743  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
103744  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
103745  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
103746  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
103747  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
103748  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
103749  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
103750  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
103751  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
103752  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
103753  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
103754  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
103755  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
103756  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
103757  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
103758  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
103759  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
103760  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
103761  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
103762  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
103763  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
103764  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
103765  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
103766  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
103767  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
103768  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
103769 };
103770 
103776 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
103777 {
103778  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
103779  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
103780  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
103781  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
103782  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
103783  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
103784  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
103785  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
103786  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
103787  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
103788  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
103789  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
103790  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
103791  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
103792  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
103793  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
103794  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
103795  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
103796  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
103797  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
103798  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
103799  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
103800  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
103801  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
103802  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
103803  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
103804  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
103805  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
103806  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
103807  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
103808  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
103809  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
103810  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
103811  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
103812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
103813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
103814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
103815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
103816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
103817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
103818  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
103819  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
103820  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
103821  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
103822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
103823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
103824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
103825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
103826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
103827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
103828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
103829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
103830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
103831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
103832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
103833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
103834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
103835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
103836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
103837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
103838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
103839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
103840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
103841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
103842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
103843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
103844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
103845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
103846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
103847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
103848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
103849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
103850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
103851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
103852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
103853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
103854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
103855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
103856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
103857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
103858  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
103859  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
103860  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
103861  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
103862  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
103863  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
103864  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
103865  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
103866  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
103867  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
103868  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
103869  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
103870  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
103871  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
103872  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
103873  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
103874  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
103875  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
103876  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
103877  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
103878  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
103879  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
103880  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
103881  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
103882  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
103883  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
103884  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
103885  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
103886  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
103887  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
103888  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
103889  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
103890  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
103891  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
103892  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
103893  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
103894  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
103895  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
103896  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
103897  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
103898  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
103899  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
103900  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
103901  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
103902  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
103903  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
103904  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
103905  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
103906  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
103907  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
103908  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
103909  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
103910  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
103911  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
103912  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
103913  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
103914  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
103915  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
103916  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
103917  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
103918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
103919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
103920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
103921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
103922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
103923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
103924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
103925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
103926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
103927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
103928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
103929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
103930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
103931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
103932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
103933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
103934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
103935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
103936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
103937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
103938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
103939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
103940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
103941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
103942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
103943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
103944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
103945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
103946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
103947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
103948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
103949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
103950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
103951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
103952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
103953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
103954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
103955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
103956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
103957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
103958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
103959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
103960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
103961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
103962  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
103963  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
103964  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
103965  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
103966  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
103967  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
103968  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
103969  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
103970  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
103971  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
103972  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
103973  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
103974  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
103975  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
103976  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
103977  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
103978  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
103979  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
103980  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
103981  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
103982  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
103983  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
103984  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
103985  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
103986  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
103987  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
103988  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
103989  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
103990  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
103991  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
103992  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
103993  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
103994  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
103995  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
103996  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
103997  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
103998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
103999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
104000  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
104001  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
104002  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
104003  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
104004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
104005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
104006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
104007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
104008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
104009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
104010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
104011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
104012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
104013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
104014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
104015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
104016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
104017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
104018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
104019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
104020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
104021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
104022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
104023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
104024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
104025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
104026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
104027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
104028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
104029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
104030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
104031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
104032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
104033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
104034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
104035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
104036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
104037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
104038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
104039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
104040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
104041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
104042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
104043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
104044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
104045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
104046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
104047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
104048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
104049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
104050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
104051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
104052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
104053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
104054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
104055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
104056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
104057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
104058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
104059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
104060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
104061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
104062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
104063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
104064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
104065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
104066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
104067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
104068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
104069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
104070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
104071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
104072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
104073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
104074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
104075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
104076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
104077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
104078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
104079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
104080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
104081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
104082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
104083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
104084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
104085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
104086  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
104087  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
104088  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
104089  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
104090  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
104091  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
104092  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
104093  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
104094  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
104095  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
104096  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
104097  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
104098  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
104099  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
104100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
104101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
104102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
104103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
104104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
104105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
104106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
104107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
104108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
104109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
104110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
104111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
104112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
104113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
104114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
104115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
104116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
104117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
104118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
104119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
104120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
104121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
104122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
104123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
104124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
104125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
104126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
104127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
104128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
104129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
104130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
104131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
104132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
104133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
104134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
104135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
104136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
104137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
104138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
104139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
104140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
104141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
104142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
104143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
104144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
104145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
104146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
104147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
104148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
104149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
104150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
104151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
104152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
104153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
104154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
104155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
104156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
104157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
104158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
104159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
104160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
104161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
104162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
104163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
104164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
104165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
104166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
104167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
104168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
104169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
104170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
104171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
104172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
104173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
104174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
104175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
104176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
104177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
104178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
104179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
104180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
104181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
104182  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
104183  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
104184  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
104185  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
104186  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
104187  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
104188  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
104189  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
104190  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
104191  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
104192  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
104193  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
104194  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
104195  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
104196  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
104197  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
104198  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
104199  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
104200  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
104201  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
104202  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
104203  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
104204  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
104205  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
104206  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
104207  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
104208  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
104209  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
104210  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
104211  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
104212  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
104213  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
104214  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
104215  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
104216  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
104217  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
104218  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
104219  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
104220  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
104221  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
104222  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
104223  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
104224  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
104225  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
104226  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
104227  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
104228  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
104229  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
104230  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
104231  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
104232  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
104233  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
104234  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
104235  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
104236  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
104237  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
104238  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
104239  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
104240  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
104241  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
104242  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
104243  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
104244  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
104245  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
104246  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
104247  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
104248  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
104249  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
104250  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
104251  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
104252  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
104253  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
104254  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
104255  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
104256  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
104257  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
104258  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
104259  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
104260  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
104261  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
104262  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
104263  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
104264  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
104265  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
104266  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
104267  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
104268  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
104269  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
104270  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
104271  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
104272  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
104273  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
104274  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
104275  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
104276  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
104277  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
104278  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
104279  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
104280  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
104281  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
104282  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
104283  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
104284  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
104285  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
104286  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
104287  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
104288  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
104289  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
104290 };
104291 
104297 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
104298 {
104299  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
104300  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
104301  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
104302  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
104303  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
104304  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
104305  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
104306  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
104307  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
104308  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
104309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
104310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
104311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
104312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
104313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
104314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
104315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
104316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
104317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
104318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
104319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
104320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
104321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
104322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
104323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
104324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
104325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
104326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
104327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
104328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
104329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
104330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
104331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
104332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
104333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
104334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
104335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
104336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
104337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
104338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
104339  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
104340  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
104341  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
104342  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
104343  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
104344  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
104345  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
104346  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
104347  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
104348  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
104349  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
104350  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
104351  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
104352  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
104353  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
104354  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
104355  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
104356  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
104357  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
104358  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
104359  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
104360  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
104361  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
104362  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
104363  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
104364  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
104365  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
104366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
104367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
104368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
104369  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
104370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
104371  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
104372  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
104373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
104374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
104375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
104376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
104377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
104378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
104379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
104380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
104381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
104382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
104383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
104384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
104385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
104386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
104387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
104388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
104389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
104390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
104391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
104392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
104393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
104394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
104395  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
104396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
104397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
104398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
104399  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
104400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
104401  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
104402  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
104403  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
104404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
104405  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
104406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
104407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
104408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
104409  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
104410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
104411  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
104412  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
104413  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
104414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
104415  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
104416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
104417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
104418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
104419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
104420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
104421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
104422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
104423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
104424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
104425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
104426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
104427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
104428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
104429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
104430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
104431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
104432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
104433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
104434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
104435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
104436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
104437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
104438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
104439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
104440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
104441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
104442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
104443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
104444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
104445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
104446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
104447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
104448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
104449  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
104450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
104451  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
104452  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
104453  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
104454  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
104455  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
104456  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
104457  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
104458  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
104459  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
104460  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
104461  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
104462  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
104463  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
104464  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
104465  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
104466  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
104467  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
104468  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
104469  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
104470  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
104471  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
104472  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
104473  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
104474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
104475  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
104476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
104477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
104478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
104479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
104480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
104481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
104482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
104483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
104484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
104485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
104486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
104487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
104488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
104489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
104490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
104491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
104492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
104493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
104494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
104495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
104496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
104497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
104498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
104499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
104500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
104501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
104502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
104503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
104504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
104505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
104506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
104507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
104508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
104509  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
104510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
104511  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
104512  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
104513  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
104514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
104515  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
104516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
104517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
104518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
104519  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
104520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
104521  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
104522  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
104523  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
104524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
104525  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
104526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
104527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
104528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
104529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
104530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
104531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
104532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
104533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
104534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
104535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
104536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
104537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
104538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
104539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
104540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
104541  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
104542  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
104543  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
104544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
104545  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
104546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
104547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
104548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
104549  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
104550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
104551  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
104552  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
104553 };
104554 
104560 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
104561 {
104562  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
104563  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
104564  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
104565  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
104566  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
104567  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
104568  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
104569  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
104570  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
104571  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
104572  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
104573  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
104574  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
104575  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
104576  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
104577  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
104578  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
104579  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
104580  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
104581  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
104582  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
104583  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
104584  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
104585  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
104586  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
104587  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
104588  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
104589  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
104590  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
104591  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
104592  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
104593  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
104594  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
104595  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
104596  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
104597  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
104598  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
104599  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
104600  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
104601  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
104602  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
104603  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
104604  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
104605  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
104606  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
104607  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
104608  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
104609  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
104610  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
104611  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
104612  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
104613  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
104614  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
104615  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
104616  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
104617  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
104618  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
104619  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
104620  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
104621  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
104622  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
104623  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
104624  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
104625  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
104626  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
104627  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
104628  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
104629  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
104630  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
104631  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
104632  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
104633  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
104634  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
104635  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
104636  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
104637  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
104638  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
104639  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
104640  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
104641  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
104642  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
104643  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
104644  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
104645  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
104646  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
104647  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
104648  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
104649  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
104650  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
104651  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
104652  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
104653  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
104654  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
104655  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
104656  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
104657  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
104658  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
104659  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
104660  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
104661  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
104662  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
104663  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
104664  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
104665  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
104666  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
104667  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
104668  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
104669  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
104670  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
104671  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
104672  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
104673  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
104674  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
104675  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
104676  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
104677  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
104678  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
104679  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
104680  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
104681  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
104682  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
104683  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
104684  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
104685  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
104686  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
104687  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
104688  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
104689  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
104690  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
104691  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
104692  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
104693  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
104694  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
104695  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
104696  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
104697  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
104698  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
104699  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
104700  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
104701  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
104702  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
104703  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
104704  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
104705  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
104706  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
104707  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
104708  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
104709  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
104710  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
104711  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
104712  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
104713  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
104714  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
104715  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
104716  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
104717  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
104718  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
104719  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
104720  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
104721  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
104722  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
104723  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
104724  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
104725  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
104726  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
104727  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
104728  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
104729  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
104730  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
104731  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
104732  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
104733  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
104734  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
104735  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
104736  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
104737  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
104738  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
104739  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
104740  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
104741  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
104742  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
104743  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
104744  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
104745  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
104746  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
104747  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
104748  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
104749  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
104750  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
104751  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
104752  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
104753  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
104754  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
104755  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
104756  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
104757  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
104758  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
104759  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
104760  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
104761  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
104762  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
104763  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
104764  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
104765  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
104766  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
104767  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
104768  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
104769  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
104770  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
104771  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
104772  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
104773  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
104774  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
104775  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
104776  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
104777  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
104778  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
104779  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
104780  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
104781  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
104782  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
104783  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
104784  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
104785  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
104786  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
104787  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
104788  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
104789  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
104790  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
104791  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
104792  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
104793  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
104794  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
104795  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
104796  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
104797  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
104798  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
104799  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
104800  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
104801  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
104802  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
104803  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
104804  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
104805  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
104806  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
104807  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
104808  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
104809  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
104810  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
104811  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
104812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
104813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
104814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
104815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
104816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
104817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
104818  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
104819  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
104820  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
104821  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
104822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
104823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
104824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
104825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
104826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
104827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
104828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
104829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
104830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
104831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
104832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
104833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
104834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
104835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
104836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
104837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
104838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
104839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
104840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
104841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
104842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
104843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
104844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
104845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
104846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
104847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
104848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
104849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
104850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
104851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
104852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
104853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
104854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
104855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
104856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
104857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
104858  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
104859  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
104860  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
104861  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
104862  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
104863  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
104864  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
104865  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
104866  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
104867  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
104868  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
104869  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
104870  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
104871  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
104872  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
104873  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
104874  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
104875  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
104876  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
104877  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
104878  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
104879  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
104880  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
104881  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
104882  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
104883  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
104884  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
104885  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
104886  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
104887  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
104888  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
104889  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
104890  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
104891  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
104892  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
104893  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
104894  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
104895  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
104896  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
104897  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
104898  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
104899  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
104900  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
104901  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
104902  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
104903  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
104904  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
104905  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
104906  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
104907  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
104908  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
104909  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
104910  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
104911  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
104912  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
104913  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
104914  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
104915  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
104916  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
104917  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
104918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
104919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
104920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
104921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
104922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
104923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
104924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
104925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
104926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
104927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
104928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
104929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
104930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
104931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
104932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
104933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
104934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
104935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
104936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
104937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
104938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
104939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
104940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
104941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
104942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
104943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
104944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
104945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
104946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
104947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
104948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
104949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
104950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
104951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
104952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
104953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
104954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
104955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
104956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
104957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
104958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
104959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
104960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
104961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
104962  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
104963  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
104964  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
104965  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
104966  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
104967  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
104968  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
104969  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
104970  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
104971  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
104972  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
104973  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
104974  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
104975  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
104976  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
104977  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
104978  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
104979  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
104980  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
104981  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
104982  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
104983  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
104984  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
104985  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
104986  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
104987  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
104988  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
104989  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
104990  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
104991  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
104992  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
104993  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
104994  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
104995  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
104996  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
104997  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
104998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
104999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
105000  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
105001  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
105002  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
105003  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
105004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
105005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
105006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
105007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
105008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
105009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
105010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
105011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
105012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
105013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
105014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
105015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
105016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
105017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
105018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
105019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
105020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
105021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
105022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
105023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
105024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
105025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
105026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
105027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
105028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
105029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
105030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
105031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
105032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
105033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
105034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
105035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
105036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
105037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
105038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
105039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
105040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
105041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
105042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
105043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
105044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
105045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
105046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
105047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
105048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
105049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
105050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
105051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
105052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
105053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
105054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
105055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
105056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
105057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
105058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
105059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
105060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
105061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
105062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
105063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
105064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
105065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
105066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
105067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
105068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
105069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
105070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
105071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
105072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
105073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
105074 };
105075 
105081 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
105082 {
105083  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
105084  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
105085  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
105086  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
105087  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
105088  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
105089  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
105090  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
105091  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
105092  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
105093  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
105094  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
105095  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
105096  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
105097  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
105098  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
105099  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
105100  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
105101  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
105102  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
105103  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
105104  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
105105  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
105106  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
105107  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
105108  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
105109  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
105110  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
105111  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
105112  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
105113  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
105114  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
105115  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
105116  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
105117  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
105118  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
105119  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
105120  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
105121  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
105122  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
105123  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
105124  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
105125  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
105126  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
105127  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
105128  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
105129  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
105130  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
105131  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
105132  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
105133  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
105134  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
105135  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
105136  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
105137  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
105138  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
105139  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
105140  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
105141  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
105142  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
105143  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
105144  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
105145  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
105146  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
105147  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
105148  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
105149  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
105150  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
105151  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
105152  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
105153  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
105154  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
105155  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
105156  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
105157  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
105158  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
105159  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
105160  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
105161  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
105162  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
105163  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
105164  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
105165  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
105166  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
105167  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
105168  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
105169  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
105170  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
105171  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
105172  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
105173  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
105174  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
105175  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
105176  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
105177  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
105178  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
105179  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
105180  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
105181  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
105182  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
105183  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
105184  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
105185  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
105186  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
105187  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
105188  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
105189  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
105190  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
105191  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
105192  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
105193  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
105194  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
105195  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
105196  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
105197  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
105198  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
105199  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
105200  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
105201  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
105202  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
105203  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
105204  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
105205  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
105206  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
105207  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
105208  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
105209  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
105210  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
105211  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
105212  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
105213  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
105214  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
105215  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
105216  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
105217  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
105218  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
105219  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
105220  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
105221  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
105222  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
105223  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
105224  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
105225  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
105226  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
105227  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
105228  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
105229  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
105230  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
105231  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
105232  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
105233  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
105234  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
105235  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
105236  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
105237  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
105238  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
105239  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
105240  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
105241  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
105242  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
105243  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
105244  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
105245  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
105246  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
105247  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
105248  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
105249  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
105250  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
105251  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
105252  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
105253  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
105254  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
105255  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
105256  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
105257  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
105258  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
105259  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
105260  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
105261  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
105262  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
105263  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
105264  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
105265  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
105266  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
105267  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
105268  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
105269  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
105270  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
105271  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
105272  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
105273 };
105274 
105280 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
105281 {
105282  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
105283  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
105284  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
105285  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
105286  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
105287  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
105288  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
105289  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
105290  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
105291  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
105292  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
105293  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
105294  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
105295  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
105296  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
105297  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
105298  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
105299  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
105300 };
105301 
105307 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
105308 {
105309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
105310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
105311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
105312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
105313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
105314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
105315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
105316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
105317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
105318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
105319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
105320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
105321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
105322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
105323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
105324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
105325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
105326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
105327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
105328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
105329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
105330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
105331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
105332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
105333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
105334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
105335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
105336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
105337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
105338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
105339 };
105340 
105346 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
105347 {
105348  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
105349  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
105350  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
105351  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
105352  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
105353  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
105354  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
105355  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
105356 };
105357 
105363 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
105364 {
105365  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
105366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
105367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
105368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
105369  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
105370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
105371  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
105372  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
105373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
105374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
105375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
105376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
105377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
105378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
105379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
105380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
105381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
105382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
105383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
105384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
105385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
105386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
105387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
105388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
105389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
105390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
105391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
105392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
105393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
105394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
105395  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
105396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
105397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
105398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
105399  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
105400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
105401  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
105402  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
105403  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
105404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
105405  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
105406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
105407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
105408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
105409  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
105410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
105411  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
105412  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
105413  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
105414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
105415  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
105416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
105417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
105418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
105419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
105420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
105421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
105422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
105423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
105424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
105425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
105426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
105427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
105428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
105429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
105430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
105431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
105432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
105433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
105434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
105435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
105436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
105437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
105438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
105439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
105440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
105441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
105442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
105443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
105444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
105445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
105446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
105447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
105448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
105449 };
105450 
105456 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
105457 {
105458  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
105459  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
105460  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
105461  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
105462  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
105463  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
105464  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
105465  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
105466  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
105467  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
105468 };
105469 
105475 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_MAX_NUM_CHECKERS] =
105476 {
105477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_0_CHECKER_TYPE,
105478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_0_WIDTH },
105479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_1_CHECKER_TYPE,
105480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_1_WIDTH },
105481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_2_CHECKER_TYPE,
105482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_2_WIDTH },
105483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_3_CHECKER_TYPE,
105484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_3_WIDTH },
105485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_4_CHECKER_TYPE,
105486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_4_WIDTH },
105487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_5_CHECKER_TYPE,
105488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_5_WIDTH },
105489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_6_CHECKER_TYPE,
105490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_6_WIDTH },
105491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_7_CHECKER_TYPE,
105492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_7_WIDTH },
105493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_8_CHECKER_TYPE,
105494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_8_WIDTH },
105495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_9_CHECKER_TYPE,
105496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_9_WIDTH },
105497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_10_CHECKER_TYPE,
105498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_10_WIDTH },
105499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_11_CHECKER_TYPE,
105500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_11_WIDTH },
105501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_12_CHECKER_TYPE,
105502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_12_WIDTH },
105503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_13_CHECKER_TYPE,
105504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_13_WIDTH },
105505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_14_CHECKER_TYPE,
105506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_14_WIDTH },
105507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_15_CHECKER_TYPE,
105508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_15_WIDTH },
105509  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_16_CHECKER_TYPE,
105510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_16_WIDTH },
105511  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_17_CHECKER_TYPE,
105512  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_17_WIDTH },
105513  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_18_CHECKER_TYPE,
105514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_18_WIDTH },
105515  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_19_CHECKER_TYPE,
105516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_19_WIDTH },
105517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_20_CHECKER_TYPE,
105518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_20_WIDTH },
105519  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_21_CHECKER_TYPE,
105520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_21_WIDTH },
105521  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_22_CHECKER_TYPE,
105522  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_22_WIDTH },
105523  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_23_CHECKER_TYPE,
105524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_23_WIDTH },
105525  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_24_CHECKER_TYPE,
105526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_24_WIDTH },
105527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_25_CHECKER_TYPE,
105528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_25_WIDTH },
105529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_26_CHECKER_TYPE,
105530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_26_WIDTH },
105531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_27_CHECKER_TYPE,
105532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_27_WIDTH },
105533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_28_CHECKER_TYPE,
105534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_28_WIDTH },
105535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_29_CHECKER_TYPE,
105536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_29_WIDTH },
105537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_30_CHECKER_TYPE,
105538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_30_WIDTH },
105539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_31_CHECKER_TYPE,
105540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_31_WIDTH },
105541  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_32_CHECKER_TYPE,
105542  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_32_WIDTH },
105543  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_33_CHECKER_TYPE,
105544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_33_WIDTH },
105545  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_34_CHECKER_TYPE,
105546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_34_WIDTH },
105547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_35_CHECKER_TYPE,
105548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_35_WIDTH },
105549  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_36_CHECKER_TYPE,
105550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_36_WIDTH },
105551  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_37_CHECKER_TYPE,
105552  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_37_WIDTH },
105553  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_38_CHECKER_TYPE,
105554  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_38_WIDTH },
105555  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_39_CHECKER_TYPE,
105556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_39_WIDTH },
105557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_40_CHECKER_TYPE,
105558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_40_WIDTH },
105559  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_41_CHECKER_TYPE,
105560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_41_WIDTH },
105561  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_42_CHECKER_TYPE,
105562  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_42_WIDTH },
105563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_43_CHECKER_TYPE,
105564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_43_WIDTH },
105565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_44_CHECKER_TYPE,
105566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_44_WIDTH },
105567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_45_CHECKER_TYPE,
105568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_45_WIDTH },
105569  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_46_CHECKER_TYPE,
105570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_46_WIDTH },
105571  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_47_CHECKER_TYPE,
105572  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_47_WIDTH },
105573  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_48_CHECKER_TYPE,
105574  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_48_WIDTH },
105575  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_49_CHECKER_TYPE,
105576  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_49_WIDTH },
105577  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_50_CHECKER_TYPE,
105578  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_50_WIDTH },
105579  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_51_CHECKER_TYPE,
105580  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_51_WIDTH },
105581  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_52_CHECKER_TYPE,
105582  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_52_WIDTH },
105583  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_53_CHECKER_TYPE,
105584  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_53_WIDTH },
105585  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_54_CHECKER_TYPE,
105586  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_54_WIDTH },
105587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_55_CHECKER_TYPE,
105588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_55_WIDTH },
105589  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_56_CHECKER_TYPE,
105590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_56_WIDTH },
105591  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_57_CHECKER_TYPE,
105592  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_57_WIDTH },
105593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_58_CHECKER_TYPE,
105594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_58_WIDTH },
105595  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_59_CHECKER_TYPE,
105596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_59_WIDTH },
105597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_60_CHECKER_TYPE,
105598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_60_WIDTH },
105599  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_61_CHECKER_TYPE,
105600  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_61_WIDTH },
105601  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_62_CHECKER_TYPE,
105602  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_62_WIDTH },
105603  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_63_CHECKER_TYPE,
105604  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_63_WIDTH },
105605  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_64_CHECKER_TYPE,
105606  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_64_WIDTH },
105607  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_65_CHECKER_TYPE,
105608  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_65_WIDTH },
105609  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_66_CHECKER_TYPE,
105610  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_66_WIDTH },
105611  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_67_CHECKER_TYPE,
105612  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_67_WIDTH },
105613  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_68_CHECKER_TYPE,
105614  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_68_WIDTH },
105615  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_69_CHECKER_TYPE,
105616  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_69_WIDTH },
105617  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_70_CHECKER_TYPE,
105618  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_70_WIDTH },
105619  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_71_CHECKER_TYPE,
105620  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_71_WIDTH },
105621  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_72_CHECKER_TYPE,
105622  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_72_WIDTH },
105623  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_73_CHECKER_TYPE,
105624  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_73_WIDTH },
105625  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_74_CHECKER_TYPE,
105626  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_74_WIDTH },
105627  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_75_CHECKER_TYPE,
105628  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_75_WIDTH },
105629  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_76_CHECKER_TYPE,
105630  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_76_WIDTH },
105631  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_77_CHECKER_TYPE,
105632  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_77_WIDTH },
105633  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_78_CHECKER_TYPE,
105634  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_78_WIDTH },
105635  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_79_CHECKER_TYPE,
105636  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_79_WIDTH },
105637  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_80_CHECKER_TYPE,
105638  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_80_WIDTH },
105639  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_81_CHECKER_TYPE,
105640  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_81_WIDTH },
105641  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_82_CHECKER_TYPE,
105642  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_82_WIDTH },
105643  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_83_CHECKER_TYPE,
105644  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_83_WIDTH },
105645  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_84_CHECKER_TYPE,
105646  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_84_WIDTH },
105647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_85_CHECKER_TYPE,
105648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_85_WIDTH },
105649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_86_CHECKER_TYPE,
105650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_86_WIDTH },
105651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_87_CHECKER_TYPE,
105652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_87_WIDTH },
105653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_88_CHECKER_TYPE,
105654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_88_WIDTH },
105655  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_89_CHECKER_TYPE,
105656  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_89_WIDTH },
105657  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_90_CHECKER_TYPE,
105658  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_90_WIDTH },
105659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_91_CHECKER_TYPE,
105660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_91_WIDTH },
105661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_92_CHECKER_TYPE,
105662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_92_WIDTH },
105663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_93_CHECKER_TYPE,
105664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_93_WIDTH },
105665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_94_CHECKER_TYPE,
105666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_94_WIDTH },
105667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_95_CHECKER_TYPE,
105668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_95_WIDTH },
105669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_96_CHECKER_TYPE,
105670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_96_WIDTH },
105671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_97_CHECKER_TYPE,
105672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_97_WIDTH },
105673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_98_CHECKER_TYPE,
105674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_98_WIDTH },
105675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_99_CHECKER_TYPE,
105676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_99_WIDTH },
105677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_100_CHECKER_TYPE,
105678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_100_WIDTH },
105679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_101_CHECKER_TYPE,
105680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_101_WIDTH },
105681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_102_CHECKER_TYPE,
105682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_102_WIDTH },
105683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_103_CHECKER_TYPE,
105684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_103_WIDTH },
105685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_104_CHECKER_TYPE,
105686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_104_WIDTH },
105687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_105_CHECKER_TYPE,
105688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_105_WIDTH },
105689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_106_CHECKER_TYPE,
105690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_106_WIDTH },
105691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_107_CHECKER_TYPE,
105692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_107_WIDTH },
105693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_108_CHECKER_TYPE,
105694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_108_WIDTH },
105695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_109_CHECKER_TYPE,
105696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_109_WIDTH },
105697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_110_CHECKER_TYPE,
105698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_110_WIDTH },
105699  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_111_CHECKER_TYPE,
105700  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_111_WIDTH },
105701  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_112_CHECKER_TYPE,
105702  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_112_WIDTH },
105703  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_113_CHECKER_TYPE,
105704  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_113_WIDTH },
105705  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_114_CHECKER_TYPE,
105706  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_114_WIDTH },
105707  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_115_CHECKER_TYPE,
105708  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_115_WIDTH },
105709  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_116_CHECKER_TYPE,
105710  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_116_WIDTH },
105711  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_117_CHECKER_TYPE,
105712  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_117_WIDTH },
105713  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_118_CHECKER_TYPE,
105714  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_118_WIDTH },
105715  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_119_CHECKER_TYPE,
105716  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_119_WIDTH },
105717  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_120_CHECKER_TYPE,
105718  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_120_WIDTH },
105719  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_121_CHECKER_TYPE,
105720  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_121_WIDTH },
105721  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_122_CHECKER_TYPE,
105722  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_122_WIDTH },
105723  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_123_CHECKER_TYPE,
105724  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_123_WIDTH },
105725  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_124_CHECKER_TYPE,
105726  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_124_WIDTH },
105727  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_125_CHECKER_TYPE,
105728  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_125_WIDTH },
105729  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_126_CHECKER_TYPE,
105730  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_126_WIDTH },
105731  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_127_CHECKER_TYPE,
105732  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_127_WIDTH },
105733  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_128_CHECKER_TYPE,
105734  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_128_WIDTH },
105735  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_129_CHECKER_TYPE,
105736  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_129_WIDTH },
105737  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_130_CHECKER_TYPE,
105738  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_130_WIDTH },
105739  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_131_CHECKER_TYPE,
105740  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_131_WIDTH },
105741  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_132_CHECKER_TYPE,
105742  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_132_WIDTH },
105743  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_133_CHECKER_TYPE,
105744  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_133_WIDTH },
105745  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_134_CHECKER_TYPE,
105746  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_134_WIDTH },
105747  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_135_CHECKER_TYPE,
105748  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_135_WIDTH },
105749  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_136_CHECKER_TYPE,
105750  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_136_WIDTH },
105751  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_137_CHECKER_TYPE,
105752  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_137_WIDTH },
105753  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_138_CHECKER_TYPE,
105754  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_138_WIDTH },
105755  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_139_CHECKER_TYPE,
105756  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_139_WIDTH },
105757  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_140_CHECKER_TYPE,
105758  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_140_WIDTH },
105759  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_141_CHECKER_TYPE,
105760  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_141_WIDTH },
105761  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_142_CHECKER_TYPE,
105762  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_142_WIDTH },
105763  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_143_CHECKER_TYPE,
105764  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_143_WIDTH },
105765  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_144_CHECKER_TYPE,
105766  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_144_WIDTH },
105767  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_145_CHECKER_TYPE,
105768  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_145_WIDTH },
105769  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_146_CHECKER_TYPE,
105770  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_146_WIDTH },
105771  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_147_CHECKER_TYPE,
105772  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_147_WIDTH },
105773  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_148_CHECKER_TYPE,
105774  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_148_WIDTH },
105775  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_149_CHECKER_TYPE,
105776  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_149_WIDTH },
105777  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_150_CHECKER_TYPE,
105778  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_150_WIDTH },
105779  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_151_CHECKER_TYPE,
105780  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_151_WIDTH },
105781  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_152_CHECKER_TYPE,
105782  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_152_WIDTH },
105783  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_153_CHECKER_TYPE,
105784  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_153_WIDTH },
105785  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_154_CHECKER_TYPE,
105786  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_154_WIDTH },
105787  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_155_CHECKER_TYPE,
105788  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_155_WIDTH },
105789  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_156_CHECKER_TYPE,
105790  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_156_WIDTH },
105791  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_157_CHECKER_TYPE,
105792  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_157_WIDTH },
105793  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_158_CHECKER_TYPE,
105794  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_158_WIDTH },
105795  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_159_CHECKER_TYPE,
105796  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_159_WIDTH },
105797  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_160_CHECKER_TYPE,
105798  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_160_WIDTH },
105799  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_161_CHECKER_TYPE,
105800  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_161_WIDTH },
105801  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_162_CHECKER_TYPE,
105802  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_162_WIDTH },
105803  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_163_CHECKER_TYPE,
105804  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_163_WIDTH },
105805  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_164_CHECKER_TYPE,
105806  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_164_WIDTH },
105807  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_165_CHECKER_TYPE,
105808  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_165_WIDTH },
105809  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_166_CHECKER_TYPE,
105810  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_166_WIDTH },
105811  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_167_CHECKER_TYPE,
105812  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_167_WIDTH },
105813  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_168_CHECKER_TYPE,
105814  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_168_WIDTH },
105815  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_169_CHECKER_TYPE,
105816  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_169_WIDTH },
105817  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_170_CHECKER_TYPE,
105818  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_170_WIDTH },
105819  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_171_CHECKER_TYPE,
105820  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_171_WIDTH },
105821  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_172_CHECKER_TYPE,
105822  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_172_WIDTH },
105823  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_173_CHECKER_TYPE,
105824  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_173_WIDTH },
105825  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_174_CHECKER_TYPE,
105826  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_174_WIDTH },
105827  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_175_CHECKER_TYPE,
105828  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_175_WIDTH },
105829  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_176_CHECKER_TYPE,
105830  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_176_WIDTH },
105831  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_177_CHECKER_TYPE,
105832  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_177_WIDTH },
105833  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_178_CHECKER_TYPE,
105834  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_178_WIDTH },
105835  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_179_CHECKER_TYPE,
105836  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_179_WIDTH },
105837  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_180_CHECKER_TYPE,
105838  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_180_WIDTH },
105839  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_181_CHECKER_TYPE,
105840  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_181_WIDTH },
105841  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_182_CHECKER_TYPE,
105842  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_182_WIDTH },
105843  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_183_CHECKER_TYPE,
105844  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_183_WIDTH },
105845  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_184_CHECKER_TYPE,
105846  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_184_WIDTH },
105847  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_185_CHECKER_TYPE,
105848  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_185_WIDTH },
105849  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_186_CHECKER_TYPE,
105850  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_186_WIDTH },
105851  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_187_CHECKER_TYPE,
105852  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_187_WIDTH },
105853  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_188_CHECKER_TYPE,
105854  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_188_WIDTH },
105855  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_189_CHECKER_TYPE,
105856  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_189_WIDTH },
105857  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_190_CHECKER_TYPE,
105858  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_190_WIDTH },
105859  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_191_CHECKER_TYPE,
105860  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_191_WIDTH },
105861  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_192_CHECKER_TYPE,
105862  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_192_WIDTH },
105863  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_193_CHECKER_TYPE,
105864  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_193_WIDTH },
105865  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_194_CHECKER_TYPE,
105866  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_194_WIDTH },
105867  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_195_CHECKER_TYPE,
105868  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_195_WIDTH },
105869  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_196_CHECKER_TYPE,
105870  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_196_WIDTH },
105871  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_197_CHECKER_TYPE,
105872  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_197_WIDTH },
105873  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_198_CHECKER_TYPE,
105874  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_198_WIDTH },
105875  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_199_CHECKER_TYPE,
105876  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_199_WIDTH },
105877  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_200_CHECKER_TYPE,
105878  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_200_WIDTH },
105879  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_201_CHECKER_TYPE,
105880  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_201_WIDTH },
105881  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_202_CHECKER_TYPE,
105882  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_202_WIDTH },
105883  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_203_CHECKER_TYPE,
105884  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_203_WIDTH },
105885  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_204_CHECKER_TYPE,
105886  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_204_WIDTH },
105887  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_205_CHECKER_TYPE,
105888  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_205_WIDTH },
105889  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_206_CHECKER_TYPE,
105890  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_206_WIDTH },
105891  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_207_CHECKER_TYPE,
105892  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_207_WIDTH },
105893  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_208_CHECKER_TYPE,
105894  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_208_WIDTH },
105895  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_209_CHECKER_TYPE,
105896  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_209_WIDTH },
105897  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_210_CHECKER_TYPE,
105898  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_210_WIDTH },
105899  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_211_CHECKER_TYPE,
105900  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_211_WIDTH },
105901  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_212_CHECKER_TYPE,
105902  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_212_WIDTH },
105903  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_213_CHECKER_TYPE,
105904  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_213_WIDTH },
105905  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_214_CHECKER_TYPE,
105906  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_214_WIDTH },
105907  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_215_CHECKER_TYPE,
105908  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_215_WIDTH },
105909  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_216_CHECKER_TYPE,
105910  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_216_WIDTH },
105911  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_217_CHECKER_TYPE,
105912  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_217_WIDTH },
105913  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_218_CHECKER_TYPE,
105914  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_218_WIDTH },
105915  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_219_CHECKER_TYPE,
105916  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_219_WIDTH },
105917  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_220_CHECKER_TYPE,
105918  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_220_WIDTH },
105919  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_221_CHECKER_TYPE,
105920  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_221_WIDTH },
105921  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_222_CHECKER_TYPE,
105922  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_222_WIDTH },
105923  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_223_CHECKER_TYPE,
105924  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_223_WIDTH },
105925  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_224_CHECKER_TYPE,
105926  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_224_WIDTH },
105927  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_225_CHECKER_TYPE,
105928  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_225_WIDTH },
105929  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_226_CHECKER_TYPE,
105930  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_226_WIDTH },
105931  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_227_CHECKER_TYPE,
105932  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_227_WIDTH },
105933  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_228_CHECKER_TYPE,
105934  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_228_WIDTH },
105935  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_229_CHECKER_TYPE,
105936  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_229_WIDTH },
105937  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_230_CHECKER_TYPE,
105938  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_230_WIDTH },
105939  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_231_CHECKER_TYPE,
105940  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_231_WIDTH },
105941  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_232_CHECKER_TYPE,
105942  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_232_WIDTH },
105943  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_233_CHECKER_TYPE,
105944  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_233_WIDTH },
105945  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_234_CHECKER_TYPE,
105946  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_234_WIDTH },
105947  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_235_CHECKER_TYPE,
105948  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_235_WIDTH },
105949  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_236_CHECKER_TYPE,
105950  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_236_WIDTH },
105951  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_237_CHECKER_TYPE,
105952  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_237_WIDTH },
105953  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_238_CHECKER_TYPE,
105954  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_238_WIDTH },
105955  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_239_CHECKER_TYPE,
105956  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_239_WIDTH },
105957  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_240_CHECKER_TYPE,
105958  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_240_WIDTH },
105959  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_241_CHECKER_TYPE,
105960  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_241_WIDTH },
105961  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_242_CHECKER_TYPE,
105962  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_242_WIDTH },
105963  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_243_CHECKER_TYPE,
105964  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_243_WIDTH },
105965  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_244_CHECKER_TYPE,
105966  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_244_WIDTH },
105967  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_245_CHECKER_TYPE,
105968  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_245_WIDTH },
105969  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_246_CHECKER_TYPE,
105970  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_246_WIDTH },
105971  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_247_CHECKER_TYPE,
105972  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_247_WIDTH },
105973  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_248_CHECKER_TYPE,
105974  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_248_WIDTH },
105975  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_249_CHECKER_TYPE,
105976  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_249_WIDTH },
105977  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_250_CHECKER_TYPE,
105978  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_250_WIDTH },
105979  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_251_CHECKER_TYPE,
105980  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_251_WIDTH },
105981  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_252_CHECKER_TYPE,
105982  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_252_WIDTH },
105983  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_253_CHECKER_TYPE,
105984  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_253_WIDTH },
105985  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_254_CHECKER_TYPE,
105986  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_254_WIDTH },
105987  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_255_CHECKER_TYPE,
105988  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_GROUP_255_WIDTH },
105989 };
105990 
105996 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_MAX_NUM_CHECKERS] =
105997 {
105998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_0_CHECKER_TYPE,
105999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_0_WIDTH },
106000  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_1_CHECKER_TYPE,
106001  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_1_WIDTH },
106002  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_2_CHECKER_TYPE,
106003  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_2_WIDTH },
106004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_3_CHECKER_TYPE,
106005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_3_WIDTH },
106006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_4_CHECKER_TYPE,
106007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_4_WIDTH },
106008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_5_CHECKER_TYPE,
106009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_5_WIDTH },
106010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_6_CHECKER_TYPE,
106011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_6_WIDTH },
106012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_7_CHECKER_TYPE,
106013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_7_WIDTH },
106014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_8_CHECKER_TYPE,
106015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_8_WIDTH },
106016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_9_CHECKER_TYPE,
106017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_9_WIDTH },
106018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_10_CHECKER_TYPE,
106019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_10_WIDTH },
106020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_11_CHECKER_TYPE,
106021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_11_WIDTH },
106022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_12_CHECKER_TYPE,
106023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_12_WIDTH },
106024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_13_CHECKER_TYPE,
106025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_13_WIDTH },
106026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_14_CHECKER_TYPE,
106027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_14_WIDTH },
106028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_15_CHECKER_TYPE,
106029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_15_WIDTH },
106030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_16_CHECKER_TYPE,
106031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_16_WIDTH },
106032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_17_CHECKER_TYPE,
106033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_17_WIDTH },
106034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_18_CHECKER_TYPE,
106035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_18_WIDTH },
106036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_19_CHECKER_TYPE,
106037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_19_WIDTH },
106038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_20_CHECKER_TYPE,
106039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_20_WIDTH },
106040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_21_CHECKER_TYPE,
106041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_21_WIDTH },
106042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_22_CHECKER_TYPE,
106043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_22_WIDTH },
106044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_23_CHECKER_TYPE,
106045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_23_WIDTH },
106046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_24_CHECKER_TYPE,
106047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_24_WIDTH },
106048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_25_CHECKER_TYPE,
106049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_25_WIDTH },
106050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_26_CHECKER_TYPE,
106051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_26_WIDTH },
106052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_27_CHECKER_TYPE,
106053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_27_WIDTH },
106054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_28_CHECKER_TYPE,
106055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_28_WIDTH },
106056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_29_CHECKER_TYPE,
106057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_29_WIDTH },
106058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_30_CHECKER_TYPE,
106059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_30_WIDTH },
106060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_31_CHECKER_TYPE,
106061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_31_WIDTH },
106062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_32_CHECKER_TYPE,
106063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_32_WIDTH },
106064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_33_CHECKER_TYPE,
106065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_33_WIDTH },
106066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_34_CHECKER_TYPE,
106067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_34_WIDTH },
106068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_35_CHECKER_TYPE,
106069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_35_WIDTH },
106070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_36_CHECKER_TYPE,
106071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_36_WIDTH },
106072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_37_CHECKER_TYPE,
106073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_37_WIDTH },
106074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_38_CHECKER_TYPE,
106075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_38_WIDTH },
106076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_39_CHECKER_TYPE,
106077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_39_WIDTH },
106078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_40_CHECKER_TYPE,
106079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_40_WIDTH },
106080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_41_CHECKER_TYPE,
106081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_41_WIDTH },
106082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_42_CHECKER_TYPE,
106083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_42_WIDTH },
106084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_43_CHECKER_TYPE,
106085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_43_WIDTH },
106086  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_44_CHECKER_TYPE,
106087  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_44_WIDTH },
106088  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_45_CHECKER_TYPE,
106089  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_45_WIDTH },
106090  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_46_CHECKER_TYPE,
106091  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_46_WIDTH },
106092  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_47_CHECKER_TYPE,
106093  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_47_WIDTH },
106094  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_48_CHECKER_TYPE,
106095  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_48_WIDTH },
106096  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_49_CHECKER_TYPE,
106097  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_49_WIDTH },
106098  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_50_CHECKER_TYPE,
106099  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_50_WIDTH },
106100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_51_CHECKER_TYPE,
106101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_51_WIDTH },
106102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_52_CHECKER_TYPE,
106103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_52_WIDTH },
106104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_53_CHECKER_TYPE,
106105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_53_WIDTH },
106106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_54_CHECKER_TYPE,
106107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_54_WIDTH },
106108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_55_CHECKER_TYPE,
106109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_55_WIDTH },
106110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_56_CHECKER_TYPE,
106111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_56_WIDTH },
106112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_57_CHECKER_TYPE,
106113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_57_WIDTH },
106114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_58_CHECKER_TYPE,
106115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_58_WIDTH },
106116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_59_CHECKER_TYPE,
106117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_59_WIDTH },
106118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_60_CHECKER_TYPE,
106119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_60_WIDTH },
106120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_61_CHECKER_TYPE,
106121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_61_WIDTH },
106122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_62_CHECKER_TYPE,
106123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_62_WIDTH },
106124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_63_CHECKER_TYPE,
106125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_63_WIDTH },
106126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_64_CHECKER_TYPE,
106127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_64_WIDTH },
106128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_65_CHECKER_TYPE,
106129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_65_WIDTH },
106130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_66_CHECKER_TYPE,
106131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_66_WIDTH },
106132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_67_CHECKER_TYPE,
106133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_67_WIDTH },
106134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_68_CHECKER_TYPE,
106135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_68_WIDTH },
106136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_69_CHECKER_TYPE,
106137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_69_WIDTH },
106138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_70_CHECKER_TYPE,
106139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_70_WIDTH },
106140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_71_CHECKER_TYPE,
106141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_71_WIDTH },
106142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_72_CHECKER_TYPE,
106143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_72_WIDTH },
106144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_73_CHECKER_TYPE,
106145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_73_WIDTH },
106146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_74_CHECKER_TYPE,
106147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_74_WIDTH },
106148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_75_CHECKER_TYPE,
106149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_75_WIDTH },
106150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_76_CHECKER_TYPE,
106151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_76_WIDTH },
106152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_77_CHECKER_TYPE,
106153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_77_WIDTH },
106154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_78_CHECKER_TYPE,
106155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_78_WIDTH },
106156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_79_CHECKER_TYPE,
106157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_79_WIDTH },
106158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_80_CHECKER_TYPE,
106159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_80_WIDTH },
106160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_81_CHECKER_TYPE,
106161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_81_WIDTH },
106162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_82_CHECKER_TYPE,
106163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_82_WIDTH },
106164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_83_CHECKER_TYPE,
106165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_83_WIDTH },
106166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_84_CHECKER_TYPE,
106167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_84_WIDTH },
106168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_85_CHECKER_TYPE,
106169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_85_WIDTH },
106170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_86_CHECKER_TYPE,
106171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_86_WIDTH },
106172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_87_CHECKER_TYPE,
106173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_87_WIDTH },
106174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_88_CHECKER_TYPE,
106175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_88_WIDTH },
106176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_89_CHECKER_TYPE,
106177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_89_WIDTH },
106178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_90_CHECKER_TYPE,
106179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_90_WIDTH },
106180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_91_CHECKER_TYPE,
106181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_91_WIDTH },
106182  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_92_CHECKER_TYPE,
106183  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_92_WIDTH },
106184  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_93_CHECKER_TYPE,
106185  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_93_WIDTH },
106186  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_94_CHECKER_TYPE,
106187  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_94_WIDTH },
106188  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_95_CHECKER_TYPE,
106189  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_95_WIDTH },
106190  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_96_CHECKER_TYPE,
106191  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_96_WIDTH },
106192  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_97_CHECKER_TYPE,
106193  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_97_WIDTH },
106194  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_98_CHECKER_TYPE,
106195  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_98_WIDTH },
106196  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_99_CHECKER_TYPE,
106197  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_99_WIDTH },
106198  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_100_CHECKER_TYPE,
106199  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_100_WIDTH },
106200  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_101_CHECKER_TYPE,
106201  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_101_WIDTH },
106202  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_102_CHECKER_TYPE,
106203  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_102_WIDTH },
106204  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_103_CHECKER_TYPE,
106205  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_103_WIDTH },
106206  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_104_CHECKER_TYPE,
106207  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_104_WIDTH },
106208  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_105_CHECKER_TYPE,
106209  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_105_WIDTH },
106210  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_106_CHECKER_TYPE,
106211  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_106_WIDTH },
106212  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_107_CHECKER_TYPE,
106213  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_107_WIDTH },
106214  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_108_CHECKER_TYPE,
106215  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_108_WIDTH },
106216  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_109_CHECKER_TYPE,
106217  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_109_WIDTH },
106218  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_110_CHECKER_TYPE,
106219  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_110_WIDTH },
106220  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_111_CHECKER_TYPE,
106221  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_111_WIDTH },
106222  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_112_CHECKER_TYPE,
106223  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_112_WIDTH },
106224  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_113_CHECKER_TYPE,
106225  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_113_WIDTH },
106226  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_114_CHECKER_TYPE,
106227  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_114_WIDTH },
106228  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_115_CHECKER_TYPE,
106229  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_115_WIDTH },
106230  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_116_CHECKER_TYPE,
106231  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_116_WIDTH },
106232  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_117_CHECKER_TYPE,
106233  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_117_WIDTH },
106234  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_118_CHECKER_TYPE,
106235  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_118_WIDTH },
106236  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_119_CHECKER_TYPE,
106237  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_119_WIDTH },
106238  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_120_CHECKER_TYPE,
106239  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_120_WIDTH },
106240  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_121_CHECKER_TYPE,
106241  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_121_WIDTH },
106242  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_122_CHECKER_TYPE,
106243  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_122_WIDTH },
106244  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_123_CHECKER_TYPE,
106245  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_123_WIDTH },
106246  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_124_CHECKER_TYPE,
106247  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_124_WIDTH },
106248  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_125_CHECKER_TYPE,
106249  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_125_WIDTH },
106250  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_126_CHECKER_TYPE,
106251  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_126_WIDTH },
106252  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_127_CHECKER_TYPE,
106253  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_127_WIDTH },
106254  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_128_CHECKER_TYPE,
106255  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_128_WIDTH },
106256  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_129_CHECKER_TYPE,
106257  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_129_WIDTH },
106258  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_130_CHECKER_TYPE,
106259  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_130_WIDTH },
106260  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_131_CHECKER_TYPE,
106261  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_131_WIDTH },
106262  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_132_CHECKER_TYPE,
106263  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_132_WIDTH },
106264  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_133_CHECKER_TYPE,
106265  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_133_WIDTH },
106266  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_134_CHECKER_TYPE,
106267  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_134_WIDTH },
106268  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_135_CHECKER_TYPE,
106269  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_135_WIDTH },
106270  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_136_CHECKER_TYPE,
106271  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_136_WIDTH },
106272  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_137_CHECKER_TYPE,
106273  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_137_WIDTH },
106274  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_138_CHECKER_TYPE,
106275  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_138_WIDTH },
106276  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_139_CHECKER_TYPE,
106277  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_139_WIDTH },
106278  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_140_CHECKER_TYPE,
106279  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_140_WIDTH },
106280  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_141_CHECKER_TYPE,
106281  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_141_WIDTH },
106282  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_142_CHECKER_TYPE,
106283  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_142_WIDTH },
106284  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_143_CHECKER_TYPE,
106285  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_143_WIDTH },
106286  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_144_CHECKER_TYPE,
106287  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_144_WIDTH },
106288  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_145_CHECKER_TYPE,
106289  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_145_WIDTH },
106290  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_146_CHECKER_TYPE,
106291  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_146_WIDTH },
106292  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_147_CHECKER_TYPE,
106293  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_147_WIDTH },
106294  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_148_CHECKER_TYPE,
106295  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_148_WIDTH },
106296  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_149_CHECKER_TYPE,
106297  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_149_WIDTH },
106298  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_150_CHECKER_TYPE,
106299  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_150_WIDTH },
106300  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_151_CHECKER_TYPE,
106301  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_151_WIDTH },
106302  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_152_CHECKER_TYPE,
106303  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_152_WIDTH },
106304  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_153_CHECKER_TYPE,
106305  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_153_WIDTH },
106306  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_154_CHECKER_TYPE,
106307  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_154_WIDTH },
106308  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_155_CHECKER_TYPE,
106309  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_155_WIDTH },
106310  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_156_CHECKER_TYPE,
106311  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_156_WIDTH },
106312  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_157_CHECKER_TYPE,
106313  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_157_WIDTH },
106314  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_158_CHECKER_TYPE,
106315  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_158_WIDTH },
106316  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_159_CHECKER_TYPE,
106317  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_159_WIDTH },
106318  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_160_CHECKER_TYPE,
106319  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_160_WIDTH },
106320  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_161_CHECKER_TYPE,
106321  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_161_WIDTH },
106322  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_162_CHECKER_TYPE,
106323  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_162_WIDTH },
106324  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_163_CHECKER_TYPE,
106325  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_163_WIDTH },
106326  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_164_CHECKER_TYPE,
106327  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_164_WIDTH },
106328  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_165_CHECKER_TYPE,
106329  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_165_WIDTH },
106330  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_166_CHECKER_TYPE,
106331  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_166_WIDTH },
106332  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_167_CHECKER_TYPE,
106333  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_167_WIDTH },
106334  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_168_CHECKER_TYPE,
106335  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_168_WIDTH },
106336  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_169_CHECKER_TYPE,
106337  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_169_WIDTH },
106338  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_170_CHECKER_TYPE,
106339  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_170_WIDTH },
106340  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_171_CHECKER_TYPE,
106341  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_171_WIDTH },
106342  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_172_CHECKER_TYPE,
106343  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_172_WIDTH },
106344  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_173_CHECKER_TYPE,
106345  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_173_WIDTH },
106346  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_174_CHECKER_TYPE,
106347  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_174_WIDTH },
106348  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_175_CHECKER_TYPE,
106349  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_175_WIDTH },
106350  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_176_CHECKER_TYPE,
106351  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_176_WIDTH },
106352  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_177_CHECKER_TYPE,
106353  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_177_WIDTH },
106354  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_178_CHECKER_TYPE,
106355  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_178_WIDTH },
106356  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_179_CHECKER_TYPE,
106357  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_179_WIDTH },
106358  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_180_CHECKER_TYPE,
106359  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_180_WIDTH },
106360  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_181_CHECKER_TYPE,
106361  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_181_WIDTH },
106362  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_182_CHECKER_TYPE,
106363  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_182_WIDTH },
106364  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_183_CHECKER_TYPE,
106365  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_183_WIDTH },
106366  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_184_CHECKER_TYPE,
106367  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_184_WIDTH },
106368  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_185_CHECKER_TYPE,
106369  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_185_WIDTH },
106370  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_186_CHECKER_TYPE,
106371  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_186_WIDTH },
106372  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_187_CHECKER_TYPE,
106373  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_187_WIDTH },
106374  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_188_CHECKER_TYPE,
106375  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_188_WIDTH },
106376  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_189_CHECKER_TYPE,
106377  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_189_WIDTH },
106378  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_190_CHECKER_TYPE,
106379  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_190_WIDTH },
106380  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_191_CHECKER_TYPE,
106381  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_191_WIDTH },
106382  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_192_CHECKER_TYPE,
106383  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_192_WIDTH },
106384  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_193_CHECKER_TYPE,
106385  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_193_WIDTH },
106386  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_194_CHECKER_TYPE,
106387  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_194_WIDTH },
106388  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_195_CHECKER_TYPE,
106389  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_195_WIDTH },
106390  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_196_CHECKER_TYPE,
106391  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_196_WIDTH },
106392  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_197_CHECKER_TYPE,
106393  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_197_WIDTH },
106394  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_198_CHECKER_TYPE,
106395  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_198_WIDTH },
106396  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_199_CHECKER_TYPE,
106397  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_199_WIDTH },
106398  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_200_CHECKER_TYPE,
106399  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_200_WIDTH },
106400  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_201_CHECKER_TYPE,
106401  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_201_WIDTH },
106402  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_202_CHECKER_TYPE,
106403  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_202_WIDTH },
106404  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_203_CHECKER_TYPE,
106405  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_203_WIDTH },
106406  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_204_CHECKER_TYPE,
106407  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_204_WIDTH },
106408  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_205_CHECKER_TYPE,
106409  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_205_WIDTH },
106410  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_206_CHECKER_TYPE,
106411  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_206_WIDTH },
106412  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_207_CHECKER_TYPE,
106413  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_207_WIDTH },
106414  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_208_CHECKER_TYPE,
106415  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_208_WIDTH },
106416  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_209_CHECKER_TYPE,
106417  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_209_WIDTH },
106418  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_210_CHECKER_TYPE,
106419  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_210_WIDTH },
106420  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_211_CHECKER_TYPE,
106421  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_211_WIDTH },
106422  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_212_CHECKER_TYPE,
106423  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_212_WIDTH },
106424  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_213_CHECKER_TYPE,
106425  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_213_WIDTH },
106426  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_214_CHECKER_TYPE,
106427  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_214_WIDTH },
106428  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_215_CHECKER_TYPE,
106429  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_215_WIDTH },
106430  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_216_CHECKER_TYPE,
106431  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_216_WIDTH },
106432  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_217_CHECKER_TYPE,
106433  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_217_WIDTH },
106434  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_218_CHECKER_TYPE,
106435  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_218_WIDTH },
106436  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_219_CHECKER_TYPE,
106437  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_219_WIDTH },
106438  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_220_CHECKER_TYPE,
106439  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_220_WIDTH },
106440  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_221_CHECKER_TYPE,
106441  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_221_WIDTH },
106442  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_222_CHECKER_TYPE,
106443  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_222_WIDTH },
106444  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_223_CHECKER_TYPE,
106445  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_223_WIDTH },
106446  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_224_CHECKER_TYPE,
106447  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_224_WIDTH },
106448  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_225_CHECKER_TYPE,
106449  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_225_WIDTH },
106450  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_226_CHECKER_TYPE,
106451  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_226_WIDTH },
106452  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_227_CHECKER_TYPE,
106453  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_227_WIDTH },
106454  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_228_CHECKER_TYPE,
106455  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_228_WIDTH },
106456  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_229_CHECKER_TYPE,
106457  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_229_WIDTH },
106458  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_230_CHECKER_TYPE,
106459  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_230_WIDTH },
106460  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_231_CHECKER_TYPE,
106461  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_231_WIDTH },
106462  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_232_CHECKER_TYPE,
106463  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_232_WIDTH },
106464  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_233_CHECKER_TYPE,
106465  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_233_WIDTH },
106466  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_234_CHECKER_TYPE,
106467  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_234_WIDTH },
106468  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_235_CHECKER_TYPE,
106469  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_235_WIDTH },
106470  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_236_CHECKER_TYPE,
106471  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_236_WIDTH },
106472  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_237_CHECKER_TYPE,
106473  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_237_WIDTH },
106474  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_238_CHECKER_TYPE,
106475  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_238_WIDTH },
106476  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_239_CHECKER_TYPE,
106477  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_239_WIDTH },
106478  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_240_CHECKER_TYPE,
106479  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_240_WIDTH },
106480  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_241_CHECKER_TYPE,
106481  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_241_WIDTH },
106482  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_242_CHECKER_TYPE,
106483  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_242_WIDTH },
106484  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_243_CHECKER_TYPE,
106485  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_243_WIDTH },
106486  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_244_CHECKER_TYPE,
106487  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_244_WIDTH },
106488  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_245_CHECKER_TYPE,
106489  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_245_WIDTH },
106490  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_246_CHECKER_TYPE,
106491  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_246_WIDTH },
106492  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_247_CHECKER_TYPE,
106493  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_247_WIDTH },
106494  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_248_CHECKER_TYPE,
106495  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_248_WIDTH },
106496  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_249_CHECKER_TYPE,
106497  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_249_WIDTH },
106498  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_250_CHECKER_TYPE,
106499  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_250_WIDTH },
106500  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_251_CHECKER_TYPE,
106501  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_251_WIDTH },
106502  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_252_CHECKER_TYPE,
106503  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_252_WIDTH },
106504  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_253_CHECKER_TYPE,
106505  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_253_WIDTH },
106506  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_254_CHECKER_TYPE,
106507  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_254_WIDTH },
106508  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_255_CHECKER_TYPE,
106509  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_GROUP_255_WIDTH },
106510 };
106511 
106517 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_MAX_NUM_CHECKERS] =
106518 {
106519  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_0_CHECKER_TYPE,
106520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_0_WIDTH },
106521  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_1_CHECKER_TYPE,
106522  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_1_WIDTH },
106523  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_2_CHECKER_TYPE,
106524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_2_WIDTH },
106525  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_3_CHECKER_TYPE,
106526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_3_WIDTH },
106527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_4_CHECKER_TYPE,
106528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_4_WIDTH },
106529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_5_CHECKER_TYPE,
106530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_5_WIDTH },
106531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_6_CHECKER_TYPE,
106532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_6_WIDTH },
106533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_7_CHECKER_TYPE,
106534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_7_WIDTH },
106535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_8_CHECKER_TYPE,
106536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_8_WIDTH },
106537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_9_CHECKER_TYPE,
106538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_9_WIDTH },
106539  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_10_CHECKER_TYPE,
106540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_10_WIDTH },
106541  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_11_CHECKER_TYPE,
106542  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_11_WIDTH },
106543  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_12_CHECKER_TYPE,
106544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_12_WIDTH },
106545  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_13_CHECKER_TYPE,
106546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_13_WIDTH },
106547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_14_CHECKER_TYPE,
106548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_14_WIDTH },
106549  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_15_CHECKER_TYPE,
106550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_15_WIDTH },
106551  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_16_CHECKER_TYPE,
106552  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_16_WIDTH },
106553  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_17_CHECKER_TYPE,
106554  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_17_WIDTH },
106555  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_18_CHECKER_TYPE,
106556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_18_WIDTH },
106557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_19_CHECKER_TYPE,
106558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_19_WIDTH },
106559  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_20_CHECKER_TYPE,
106560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_20_WIDTH },
106561  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_21_CHECKER_TYPE,
106562  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_21_WIDTH },
106563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_22_CHECKER_TYPE,
106564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_22_WIDTH },
106565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_23_CHECKER_TYPE,
106566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_23_WIDTH },
106567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_24_CHECKER_TYPE,
106568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_24_WIDTH },
106569  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_25_CHECKER_TYPE,
106570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_25_WIDTH },
106571  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_26_CHECKER_TYPE,
106572  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_26_WIDTH },
106573  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_27_CHECKER_TYPE,
106574  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_27_WIDTH },
106575  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_28_CHECKER_TYPE,
106576  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_28_WIDTH },
106577  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_29_CHECKER_TYPE,
106578  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_29_WIDTH },
106579  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_30_CHECKER_TYPE,
106580  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_30_WIDTH },
106581  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_31_CHECKER_TYPE,
106582  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_31_WIDTH },
106583  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_32_CHECKER_TYPE,
106584  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_32_WIDTH },
106585  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_33_CHECKER_TYPE,
106586  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_33_WIDTH },
106587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_34_CHECKER_TYPE,
106588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_34_WIDTH },
106589  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_35_CHECKER_TYPE,
106590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_35_WIDTH },
106591  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_36_CHECKER_TYPE,
106592  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_36_WIDTH },
106593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_37_CHECKER_TYPE,
106594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_37_WIDTH },
106595  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_38_CHECKER_TYPE,
106596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_38_WIDTH },
106597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_39_CHECKER_TYPE,
106598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_39_WIDTH },
106599  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_40_CHECKER_TYPE,
106600  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_40_WIDTH },
106601  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_41_CHECKER_TYPE,
106602  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_41_WIDTH },
106603  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_42_CHECKER_TYPE,
106604  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_42_WIDTH },
106605  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_43_CHECKER_TYPE,
106606  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_43_WIDTH },
106607  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_44_CHECKER_TYPE,
106608  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_44_WIDTH },
106609  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_45_CHECKER_TYPE,
106610  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_45_WIDTH },
106611  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_46_CHECKER_TYPE,
106612  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_46_WIDTH },
106613  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_47_CHECKER_TYPE,
106614  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_47_WIDTH },
106615  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_48_CHECKER_TYPE,
106616  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_48_WIDTH },
106617  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_49_CHECKER_TYPE,
106618  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_49_WIDTH },
106619  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_50_CHECKER_TYPE,
106620  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_50_WIDTH },
106621  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_51_CHECKER_TYPE,
106622  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_51_WIDTH },
106623  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_52_CHECKER_TYPE,
106624  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_52_WIDTH },
106625  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_53_CHECKER_TYPE,
106626  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_53_WIDTH },
106627  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_54_CHECKER_TYPE,
106628  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_54_WIDTH },
106629  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_55_CHECKER_TYPE,
106630  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_55_WIDTH },
106631  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_56_CHECKER_TYPE,
106632  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_56_WIDTH },
106633  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_57_CHECKER_TYPE,
106634  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_57_WIDTH },
106635  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_58_CHECKER_TYPE,
106636  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_58_WIDTH },
106637  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_59_CHECKER_TYPE,
106638  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_59_WIDTH },
106639  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_60_CHECKER_TYPE,
106640  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_60_WIDTH },
106641  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_61_CHECKER_TYPE,
106642  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_61_WIDTH },
106643  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_62_CHECKER_TYPE,
106644  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_62_WIDTH },
106645  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_63_CHECKER_TYPE,
106646  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_63_WIDTH },
106647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_64_CHECKER_TYPE,
106648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_64_WIDTH },
106649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_65_CHECKER_TYPE,
106650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_65_WIDTH },
106651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_66_CHECKER_TYPE,
106652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_66_WIDTH },
106653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_67_CHECKER_TYPE,
106654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_67_WIDTH },
106655  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_68_CHECKER_TYPE,
106656  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_68_WIDTH },
106657  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_69_CHECKER_TYPE,
106658  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_69_WIDTH },
106659  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_70_CHECKER_TYPE,
106660  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_70_WIDTH },
106661  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_71_CHECKER_TYPE,
106662  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_71_WIDTH },
106663  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_72_CHECKER_TYPE,
106664  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_72_WIDTH },
106665  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_73_CHECKER_TYPE,
106666  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_73_WIDTH },
106667  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_74_CHECKER_TYPE,
106668  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_74_WIDTH },
106669  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_75_CHECKER_TYPE,
106670  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_75_WIDTH },
106671  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_76_CHECKER_TYPE,
106672  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_76_WIDTH },
106673  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_77_CHECKER_TYPE,
106674  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_77_WIDTH },
106675  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_78_CHECKER_TYPE,
106676  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_78_WIDTH },
106677  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_79_CHECKER_TYPE,
106678  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_79_WIDTH },
106679  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_80_CHECKER_TYPE,
106680  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_80_WIDTH },
106681  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_81_CHECKER_TYPE,
106682  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_81_WIDTH },
106683  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_82_CHECKER_TYPE,
106684  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_82_WIDTH },
106685  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_83_CHECKER_TYPE,
106686  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_83_WIDTH },
106687  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_84_CHECKER_TYPE,
106688  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_84_WIDTH },
106689  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_85_CHECKER_TYPE,
106690  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_85_WIDTH },
106691  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_86_CHECKER_TYPE,
106692  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_86_WIDTH },
106693  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_87_CHECKER_TYPE,
106694  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_87_WIDTH },
106695  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_88_CHECKER_TYPE,
106696  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_88_WIDTH },
106697  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_89_CHECKER_TYPE,
106698  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_89_WIDTH },
106699  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_90_CHECKER_TYPE,
106700  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_90_WIDTH },
106701  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_91_CHECKER_TYPE,
106702  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_91_WIDTH },
106703  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_92_CHECKER_TYPE,
106704  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_92_WIDTH },
106705  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_93_CHECKER_TYPE,
106706  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_93_WIDTH },
106707  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_94_CHECKER_TYPE,
106708  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_94_WIDTH },
106709  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_95_CHECKER_TYPE,
106710  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_95_WIDTH },
106711  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_96_CHECKER_TYPE,
106712  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_96_WIDTH },
106713  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_97_CHECKER_TYPE,
106714  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_97_WIDTH },
106715  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_98_CHECKER_TYPE,
106716  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_98_WIDTH },
106717  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_99_CHECKER_TYPE,
106718  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_99_WIDTH },
106719  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_100_CHECKER_TYPE,
106720  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_100_WIDTH },
106721  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_101_CHECKER_TYPE,
106722  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_101_WIDTH },
106723  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_102_CHECKER_TYPE,
106724  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_102_WIDTH },
106725  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_103_CHECKER_TYPE,
106726  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_103_WIDTH },
106727  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_104_CHECKER_TYPE,
106728  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_104_WIDTH },
106729  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_105_CHECKER_TYPE,
106730  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_105_WIDTH },
106731  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_106_CHECKER_TYPE,
106732  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_106_WIDTH },
106733  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_107_CHECKER_TYPE,
106734  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_107_WIDTH },
106735  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_108_CHECKER_TYPE,
106736  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_108_WIDTH },
106737  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_109_CHECKER_TYPE,
106738  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_109_WIDTH },
106739  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_110_CHECKER_TYPE,
106740  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_110_WIDTH },
106741  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_111_CHECKER_TYPE,
106742  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_111_WIDTH },
106743  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_112_CHECKER_TYPE,
106744  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_112_WIDTH },
106745  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_113_CHECKER_TYPE,
106746  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_113_WIDTH },
106747  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_114_CHECKER_TYPE,
106748  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_114_WIDTH },
106749  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_115_CHECKER_TYPE,
106750  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_115_WIDTH },
106751  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_116_CHECKER_TYPE,
106752  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_116_WIDTH },
106753  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_117_CHECKER_TYPE,
106754  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_117_WIDTH },
106755  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_118_CHECKER_TYPE,
106756  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_118_WIDTH },
106757  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_119_CHECKER_TYPE,
106758  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_119_WIDTH },
106759  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_120_CHECKER_TYPE,
106760  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_120_WIDTH },
106761  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_121_CHECKER_TYPE,
106762  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_121_WIDTH },
106763  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_122_CHECKER_TYPE,
106764  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_122_WIDTH },
106765  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_123_CHECKER_TYPE,
106766  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_123_WIDTH },
106767  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_124_CHECKER_TYPE,
106768  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_124_WIDTH },
106769  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_125_CHECKER_TYPE,
106770  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_125_WIDTH },
106771  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_126_CHECKER_TYPE,
106772  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_126_WIDTH },
106773  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_127_CHECKER_TYPE,
106774  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_127_WIDTH },
106775  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_128_CHECKER_TYPE,
106776  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_128_WIDTH },
106777  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_129_CHECKER_TYPE,
106778  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_129_WIDTH },
106779  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_130_CHECKER_TYPE,
106780  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_130_WIDTH },
106781  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_131_CHECKER_TYPE,
106782  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_131_WIDTH },
106783  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_132_CHECKER_TYPE,
106784  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_132_WIDTH },
106785  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_133_CHECKER_TYPE,
106786  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_133_WIDTH },
106787  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_134_CHECKER_TYPE,
106788  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_134_WIDTH },
106789  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_135_CHECKER_TYPE,
106790  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_135_WIDTH },
106791  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_136_CHECKER_TYPE,
106792  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_136_WIDTH },
106793  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_137_CHECKER_TYPE,
106794  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_137_WIDTH },
106795  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_138_CHECKER_TYPE,
106796  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_138_WIDTH },
106797  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_139_CHECKER_TYPE,
106798  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_139_WIDTH },
106799  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_140_CHECKER_TYPE,
106800  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_140_WIDTH },
106801  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_141_CHECKER_TYPE,
106802  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_141_WIDTH },
106803  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_142_CHECKER_TYPE,
106804  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_142_WIDTH },
106805  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_143_CHECKER_TYPE,
106806  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_143_WIDTH },
106807  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_144_CHECKER_TYPE,
106808  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_144_WIDTH },
106809  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_145_CHECKER_TYPE,
106810  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_145_WIDTH },
106811  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_146_CHECKER_TYPE,
106812  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_146_WIDTH },
106813  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_147_CHECKER_TYPE,
106814  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_147_WIDTH },
106815  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_148_CHECKER_TYPE,
106816  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_148_WIDTH },
106817  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_149_CHECKER_TYPE,
106818  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_149_WIDTH },
106819  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_150_CHECKER_TYPE,
106820  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_150_WIDTH },
106821  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_151_CHECKER_TYPE,
106822  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_151_WIDTH },
106823  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_152_CHECKER_TYPE,
106824  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_152_WIDTH },
106825  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_153_CHECKER_TYPE,
106826  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_153_WIDTH },
106827  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_154_CHECKER_TYPE,
106828  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_154_WIDTH },
106829  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_155_CHECKER_TYPE,
106830  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_155_WIDTH },
106831  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_156_CHECKER_TYPE,
106832  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_156_WIDTH },
106833  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_157_CHECKER_TYPE,
106834  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_157_WIDTH },
106835  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_158_CHECKER_TYPE,
106836  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_158_WIDTH },
106837  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_159_CHECKER_TYPE,
106838  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_159_WIDTH },
106839  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_160_CHECKER_TYPE,
106840  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_160_WIDTH },
106841  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_161_CHECKER_TYPE,
106842  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_161_WIDTH },
106843  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_162_CHECKER_TYPE,
106844  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_162_WIDTH },
106845  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_163_CHECKER_TYPE,
106846  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_163_WIDTH },
106847  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_164_CHECKER_TYPE,
106848  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_164_WIDTH },
106849  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_165_CHECKER_TYPE,
106850  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_165_WIDTH },
106851  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_166_CHECKER_TYPE,
106852  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_166_WIDTH },
106853  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_167_CHECKER_TYPE,
106854  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_167_WIDTH },
106855  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_168_CHECKER_TYPE,
106856  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_168_WIDTH },
106857  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_169_CHECKER_TYPE,
106858  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_169_WIDTH },
106859  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_170_CHECKER_TYPE,
106860  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_170_WIDTH },
106861  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_171_CHECKER_TYPE,
106862  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_171_WIDTH },
106863  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_172_CHECKER_TYPE,
106864  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_172_WIDTH },
106865  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_173_CHECKER_TYPE,
106866  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_173_WIDTH },
106867  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_174_CHECKER_TYPE,
106868  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_174_WIDTH },
106869  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_175_CHECKER_TYPE,
106870  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_175_WIDTH },
106871  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_176_CHECKER_TYPE,
106872  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_176_WIDTH },
106873  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_177_CHECKER_TYPE,
106874  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_177_WIDTH },
106875  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_178_CHECKER_TYPE,
106876  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_178_WIDTH },
106877  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_179_CHECKER_TYPE,
106878  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_179_WIDTH },
106879  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_180_CHECKER_TYPE,
106880  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_180_WIDTH },
106881  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_181_CHECKER_TYPE,
106882  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_181_WIDTH },
106883  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_182_CHECKER_TYPE,
106884  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_182_WIDTH },
106885  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_183_CHECKER_TYPE,
106886  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_183_WIDTH },
106887  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_184_CHECKER_TYPE,
106888  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_184_WIDTH },
106889  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_185_CHECKER_TYPE,
106890  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_185_WIDTH },
106891  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_186_CHECKER_TYPE,
106892  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_186_WIDTH },
106893  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_187_CHECKER_TYPE,
106894  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_187_WIDTH },
106895  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_188_CHECKER_TYPE,
106896  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_188_WIDTH },
106897  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_189_CHECKER_TYPE,
106898  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_189_WIDTH },
106899  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_190_CHECKER_TYPE,
106900  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_190_WIDTH },
106901  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_191_CHECKER_TYPE,
106902  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_191_WIDTH },
106903  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_192_CHECKER_TYPE,
106904  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_192_WIDTH },
106905  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_193_CHECKER_TYPE,
106906  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_193_WIDTH },
106907  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_194_CHECKER_TYPE,
106908  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_194_WIDTH },
106909  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_195_CHECKER_TYPE,
106910  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_195_WIDTH },
106911  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_196_CHECKER_TYPE,
106912  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_196_WIDTH },
106913  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_197_CHECKER_TYPE,
106914  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_197_WIDTH },
106915  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_198_CHECKER_TYPE,
106916  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_198_WIDTH },
106917  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_199_CHECKER_TYPE,
106918  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_199_WIDTH },
106919  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_200_CHECKER_TYPE,
106920  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_200_WIDTH },
106921  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_201_CHECKER_TYPE,
106922  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_201_WIDTH },
106923  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_202_CHECKER_TYPE,
106924  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_202_WIDTH },
106925  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_203_CHECKER_TYPE,
106926  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_203_WIDTH },
106927  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_204_CHECKER_TYPE,
106928  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_204_WIDTH },
106929  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_205_CHECKER_TYPE,
106930  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_205_WIDTH },
106931  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_206_CHECKER_TYPE,
106932  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_206_WIDTH },
106933  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_207_CHECKER_TYPE,
106934  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_207_WIDTH },
106935  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_208_CHECKER_TYPE,
106936  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_208_WIDTH },
106937  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_209_CHECKER_TYPE,
106938  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_209_WIDTH },
106939  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_210_CHECKER_TYPE,
106940  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_210_WIDTH },
106941  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_211_CHECKER_TYPE,
106942  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_211_WIDTH },
106943  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_212_CHECKER_TYPE,
106944  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_212_WIDTH },
106945  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_213_CHECKER_TYPE,
106946  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_213_WIDTH },
106947  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_214_CHECKER_TYPE,
106948  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_214_WIDTH },
106949  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_215_CHECKER_TYPE,
106950  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_215_WIDTH },
106951  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_216_CHECKER_TYPE,
106952  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_216_WIDTH },
106953  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_217_CHECKER_TYPE,
106954  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_217_WIDTH },
106955  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_218_CHECKER_TYPE,
106956  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_218_WIDTH },
106957  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_219_CHECKER_TYPE,
106958  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_219_WIDTH },
106959  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_220_CHECKER_TYPE,
106960  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_220_WIDTH },
106961  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_221_CHECKER_TYPE,
106962  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_221_WIDTH },
106963  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_222_CHECKER_TYPE,
106964  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_222_WIDTH },
106965  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_223_CHECKER_TYPE,
106966  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_223_WIDTH },
106967  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_224_CHECKER_TYPE,
106968  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_224_WIDTH },
106969  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_225_CHECKER_TYPE,
106970  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_225_WIDTH },
106971  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_226_CHECKER_TYPE,
106972  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_226_WIDTH },
106973  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_227_CHECKER_TYPE,
106974  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_227_WIDTH },
106975  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_228_CHECKER_TYPE,
106976  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_228_WIDTH },
106977  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_229_CHECKER_TYPE,
106978  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_229_WIDTH },
106979  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_230_CHECKER_TYPE,
106980  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_230_WIDTH },
106981  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_231_CHECKER_TYPE,
106982  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_231_WIDTH },
106983  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_232_CHECKER_TYPE,
106984  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_232_WIDTH },
106985  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_233_CHECKER_TYPE,
106986  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_233_WIDTH },
106987  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_234_CHECKER_TYPE,
106988  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_234_WIDTH },
106989  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_235_CHECKER_TYPE,
106990  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_235_WIDTH },
106991  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_236_CHECKER_TYPE,
106992  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_236_WIDTH },
106993  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_237_CHECKER_TYPE,
106994  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_237_WIDTH },
106995  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_238_CHECKER_TYPE,
106996  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_238_WIDTH },
106997  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_239_CHECKER_TYPE,
106998  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_239_WIDTH },
106999  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_240_CHECKER_TYPE,
107000  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_240_WIDTH },
107001  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_241_CHECKER_TYPE,
107002  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_241_WIDTH },
107003  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_242_CHECKER_TYPE,
107004  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_242_WIDTH },
107005  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_243_CHECKER_TYPE,
107006  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_243_WIDTH },
107007  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_244_CHECKER_TYPE,
107008  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_244_WIDTH },
107009  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_245_CHECKER_TYPE,
107010  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_245_WIDTH },
107011  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_246_CHECKER_TYPE,
107012  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_246_WIDTH },
107013  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_247_CHECKER_TYPE,
107014  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_247_WIDTH },
107015  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_248_CHECKER_TYPE,
107016  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_248_WIDTH },
107017  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_249_CHECKER_TYPE,
107018  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_249_WIDTH },
107019  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_250_CHECKER_TYPE,
107020  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_250_WIDTH },
107021  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_251_CHECKER_TYPE,
107022  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_251_WIDTH },
107023  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_252_CHECKER_TYPE,
107024  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_252_WIDTH },
107025  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_253_CHECKER_TYPE,
107026  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_253_WIDTH },
107027  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_254_CHECKER_TYPE,
107028  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_254_WIDTH },
107029  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_255_CHECKER_TYPE,
107030  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_GROUP_255_WIDTH },
107031 };
107032 
107038 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_MAX_NUM_CHECKERS] =
107039 {
107040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_0_CHECKER_TYPE,
107041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_0_WIDTH },
107042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_1_CHECKER_TYPE,
107043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_1_WIDTH },
107044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_2_CHECKER_TYPE,
107045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_2_WIDTH },
107046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_3_CHECKER_TYPE,
107047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_3_WIDTH },
107048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_4_CHECKER_TYPE,
107049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_4_WIDTH },
107050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_5_CHECKER_TYPE,
107051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_5_WIDTH },
107052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_6_CHECKER_TYPE,
107053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_6_WIDTH },
107054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_7_CHECKER_TYPE,
107055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_7_WIDTH },
107056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_8_CHECKER_TYPE,
107057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_8_WIDTH },
107058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_9_CHECKER_TYPE,
107059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_9_WIDTH },
107060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_10_CHECKER_TYPE,
107061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_10_WIDTH },
107062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_11_CHECKER_TYPE,
107063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_11_WIDTH },
107064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_12_CHECKER_TYPE,
107065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_12_WIDTH },
107066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_13_CHECKER_TYPE,
107067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_13_WIDTH },
107068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_14_CHECKER_TYPE,
107069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_14_WIDTH },
107070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_15_CHECKER_TYPE,
107071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_15_WIDTH },
107072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_16_CHECKER_TYPE,
107073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_16_WIDTH },
107074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_17_CHECKER_TYPE,
107075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_17_WIDTH },
107076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_18_CHECKER_TYPE,
107077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_18_WIDTH },
107078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_19_CHECKER_TYPE,
107079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_19_WIDTH },
107080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_20_CHECKER_TYPE,
107081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_20_WIDTH },
107082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_21_CHECKER_TYPE,
107083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_21_WIDTH },
107084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_22_CHECKER_TYPE,
107085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_22_WIDTH },
107086  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_23_CHECKER_TYPE,
107087  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_23_WIDTH },
107088  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_24_CHECKER_TYPE,
107089  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_24_WIDTH },
107090  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_25_CHECKER_TYPE,
107091  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_25_WIDTH },
107092  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_26_CHECKER_TYPE,
107093  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_26_WIDTH },
107094  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_27_CHECKER_TYPE,
107095  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_27_WIDTH },
107096  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_28_CHECKER_TYPE,
107097  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_28_WIDTH },
107098  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_29_CHECKER_TYPE,
107099  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_29_WIDTH },
107100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_30_CHECKER_TYPE,
107101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_30_WIDTH },
107102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_31_CHECKER_TYPE,
107103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_31_WIDTH },
107104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_32_CHECKER_TYPE,
107105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_32_WIDTH },
107106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_33_CHECKER_TYPE,
107107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_33_WIDTH },
107108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_34_CHECKER_TYPE,
107109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_34_WIDTH },
107110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_35_CHECKER_TYPE,
107111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_35_WIDTH },
107112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_36_CHECKER_TYPE,
107113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_36_WIDTH },
107114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_37_CHECKER_TYPE,
107115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_37_WIDTH },
107116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_38_CHECKER_TYPE,
107117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_38_WIDTH },
107118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_39_CHECKER_TYPE,
107119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_39_WIDTH },
107120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_40_CHECKER_TYPE,
107121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_40_WIDTH },
107122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_41_CHECKER_TYPE,
107123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_41_WIDTH },
107124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_42_CHECKER_TYPE,
107125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_42_WIDTH },
107126  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_43_CHECKER_TYPE,
107127  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_43_WIDTH },
107128  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_44_CHECKER_TYPE,
107129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_44_WIDTH },
107130  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_45_CHECKER_TYPE,
107131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_45_WIDTH },
107132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_46_CHECKER_TYPE,
107133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_46_WIDTH },
107134  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_47_CHECKER_TYPE,
107135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_47_WIDTH },
107136  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_48_CHECKER_TYPE,
107137  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_48_WIDTH },
107138  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_49_CHECKER_TYPE,
107139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_49_WIDTH },
107140  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_50_CHECKER_TYPE,
107141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_50_WIDTH },
107142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_51_CHECKER_TYPE,
107143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_51_WIDTH },
107144  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_52_CHECKER_TYPE,
107145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_52_WIDTH },
107146  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_53_CHECKER_TYPE,
107147  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_53_WIDTH },
107148  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_54_CHECKER_TYPE,
107149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_54_WIDTH },
107150  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_55_CHECKER_TYPE,
107151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_55_WIDTH },
107152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_56_CHECKER_TYPE,
107153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_56_WIDTH },
107154  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_57_CHECKER_TYPE,
107155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_57_WIDTH },
107156  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_58_CHECKER_TYPE,
107157  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_58_WIDTH },
107158  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_59_CHECKER_TYPE,
107159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_59_WIDTH },
107160  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_60_CHECKER_TYPE,
107161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_60_WIDTH },
107162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_61_CHECKER_TYPE,
107163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_61_WIDTH },
107164  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_62_CHECKER_TYPE,
107165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_62_WIDTH },
107166  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_63_CHECKER_TYPE,
107167  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_63_WIDTH },
107168  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_64_CHECKER_TYPE,
107169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_64_WIDTH },
107170  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_65_CHECKER_TYPE,
107171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_65_WIDTH },
107172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_66_CHECKER_TYPE,
107173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_66_WIDTH },
107174  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_67_CHECKER_TYPE,
107175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_67_WIDTH },
107176  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_68_CHECKER_TYPE,
107177  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_68_WIDTH },
107178  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_69_CHECKER_TYPE,
107179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_69_WIDTH },
107180  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_70_CHECKER_TYPE,
107181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_70_WIDTH },
107182  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_71_CHECKER_TYPE,
107183  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_71_WIDTH },
107184  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_72_CHECKER_TYPE,
107185  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_72_WIDTH },
107186  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_73_CHECKER_TYPE,
107187  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_GROUP_73_WIDTH },
107188 };
107189 
107195 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107196 {
107197  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107198  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107199  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107200  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107201  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107202  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107203  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107204  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107205  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107206  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107207  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107208  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107209  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107210  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107211  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107212  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107213  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107214  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107215  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107216  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107217  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107218  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107219  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107220  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107221  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107222  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107223  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107224  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107225  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107226  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107227 };
107228 
107234 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107235 {
107236  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107237  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107238  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107239  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107240  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107241  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107242  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107243  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107244 };
107245 
107251 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107252 {
107253  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107254  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107255  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107256  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107257  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107258  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107259  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107260  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107261  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107262  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107263  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107264  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107265  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107266  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107267  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107268  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107269  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107270  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107271  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107272  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107273  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107274  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107275  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107276  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107277  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107278  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107279  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107280  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107281  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107282  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107283 };
107284 
107290 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107291 {
107292  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107293  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107294  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107295  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107296  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107297  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107298  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107299  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107300 };
107301 
107307 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107308 {
107309  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107311  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107312  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107313  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107315  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107319  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107321  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107322  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107323  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107325  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107329  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107331  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107332  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107333  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107335  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107339 };
107340 
107346 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107347 {
107348  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107349  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107350  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107351  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107352  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107353  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107354  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107355  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107356 };
107357 
107363 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107364 {
107365  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107369  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107371  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107372  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107391  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107392  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107393  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107395 };
107396 
107402 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107403 {
107404  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107405  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107406  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107407  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107408  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107409  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107410  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107411  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107412 };
107413 
107419 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107420 {
107421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107449  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107451 };
107452 
107458 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107459 {
107460  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107461  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107462  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107463  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107464  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107465  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107466  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107467  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107468 };
107469 
107475 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107476 {
107477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107503  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107505  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107507 };
107508 
107514 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107515 {
107516  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107517  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107518  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107519  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107520  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107521  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107522  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107523  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107524 };
107525 
107531 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
107532 {
107533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
107534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
107535  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
107536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
107537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
107538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
107539 };
107540 
107546 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
107547 {
107548  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
107549  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
107550  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
107551  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
107552  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
107553  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
107554 };
107555 
107561 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
107562 {
107563  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
107564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
107565  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
107566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
107567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
107568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
107569 };
107570 
107576 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
107577 {
107578  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
107579  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
107580  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
107581  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
107582  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
107583  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
107584 };
107585 
107591 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
107592 {
107593  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
107594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
107595  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
107596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
107597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
107598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
107599 };
107600 
107606 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107607 {
107608  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107609  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107610  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107611  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107612  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107613  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107614  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107615  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107616  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107617  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107618  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107619  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107620  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107621  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107622  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107623  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107624  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107625  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107626  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107627  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107628  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107629  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107630  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107631  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107632  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107633  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107634  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107635  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107636  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107637  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107638 };
107639 
107645 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107646 {
107647  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107648  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107649  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107650  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107651  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107652  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107653  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107654  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107655 };
107656 
107662 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
107663 {
107664  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
107665  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
107666  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
107667  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
107668  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
107669  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
107670  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
107671  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
107672  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
107673  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
107674  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
107675  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
107676  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
107677  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
107678  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
107679  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
107680  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
107681  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
107682  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
107683  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
107684  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
107685  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
107686  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
107687  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
107688  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
107689  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
107690  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
107691  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
107692  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
107693  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
107694 };
107695 
107701 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
107702 {
107703  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
107704  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
107705  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
107706  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
107707  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
107708  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
107709  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
107710  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
107711 };
107712 
107718 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
107719 {
107720  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
107721  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
107722  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
107723  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
107724  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
107725  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
107726  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
107727  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
107728  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
107729  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
107730  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
107731  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
107732  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
107733  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
107734  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
107735  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
107736  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
107737  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
107738  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
107739  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
107740  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
107741  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
107742  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
107743  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
107744  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
107745  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
107746  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
107747  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
107748  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
107749  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
107750  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
107751  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
107752  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
107753  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
107754  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
107755  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
107756  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
107757  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
107758  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
107759  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
107760  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
107761  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
107762  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
107763  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
107764  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
107765  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
107766  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
107767  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
107768  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
107769  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
107770  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
107771  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
107772  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
107773  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
107774  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
107775  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
107776  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
107777  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
107778  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
107779  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
107780  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
107781  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
107782  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
107783  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
107784  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
107785  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
107786  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
107787  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
107788  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
107789  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
107790  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
107791  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
107792  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
107793  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
107794  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
107795  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
107796  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
107797  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
107798  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
107799  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
107800  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
107801  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
107802  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
107803  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
107804  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
107805  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
107806  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
107807  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
107808  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
107809  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
107810  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
107811  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
107812  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
107813  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
107814  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
107815  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
107816  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
107817  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
107818  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
107819  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
107820  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
107821  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
107822  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
107823  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
107824  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
107825  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
107826  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
107827  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
107828  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
107829  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
107830  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
107831  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
107832  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
107833  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
107834  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
107835  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
107836  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
107837  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
107838  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
107839  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
107840  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
107841  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
107842  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
107843  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
107844  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
107845  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
107846  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
107847  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
107848  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
107849  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
107850  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
107851  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
107852  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
107853  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
107854  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
107855  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
107856  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
107857  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
107858  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
107859  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
107860  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
107861  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
107862  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
107863  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
107864  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
107865  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
107866  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
107867  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
107868  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
107869  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
107870  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
107871  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
107872  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
107873  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
107874  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
107875  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
107876  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
107877  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
107878  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
107879  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
107880  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
107881  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
107882  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
107883  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
107884  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
107885  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
107886  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
107887  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
107888  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
107889  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
107890  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
107891  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
107892  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
107893  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
107894  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
107895  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
107896  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
107897  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
107898  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
107899  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
107900  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
107901  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
107902  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
107903  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
107904  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
107905  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
107906  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
107907  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
107908  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
107909  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
107910  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
107911  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
107912  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
107913  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
107914  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
107915  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
107916  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
107917  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
107918  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
107919  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
107920  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
107921  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
107922  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
107923  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
107924  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
107925  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
107926  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
107927  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
107928  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
107929  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
107930  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
107931  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
107932  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
107933  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
107934  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
107935  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
107936  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
107937  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
107938  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
107939  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
107940  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
107941  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
107942  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
107943  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
107944  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
107945  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
107946  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
107947  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
107948  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
107949  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
107950  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
107951  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
107952  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
107953  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
107954  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
107955  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
107956  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
107957  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
107958  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
107959  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
107960  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
107961  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
107962  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_121_CHECKER_TYPE,
107963  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_121_WIDTH },
107964  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_122_CHECKER_TYPE,
107965  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_122_WIDTH },
107966  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_123_CHECKER_TYPE,
107967  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_123_WIDTH },
107968  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_124_CHECKER_TYPE,
107969  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_124_WIDTH },
107970  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_125_CHECKER_TYPE,
107971  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_125_WIDTH },
107972  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_126_CHECKER_TYPE,
107973  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_126_WIDTH },
107974  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_127_CHECKER_TYPE,
107975  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_127_WIDTH },
107976  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_128_CHECKER_TYPE,
107977  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_128_WIDTH },
107978  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_129_CHECKER_TYPE,
107979  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_129_WIDTH },
107980  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_130_CHECKER_TYPE,
107981  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_130_WIDTH },
107982  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_131_CHECKER_TYPE,
107983  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_131_WIDTH },
107984  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_132_CHECKER_TYPE,
107985  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_132_WIDTH },
107986  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_133_CHECKER_TYPE,
107987  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_133_WIDTH },
107988  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_134_CHECKER_TYPE,
107989  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_134_WIDTH },
107990  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_135_CHECKER_TYPE,
107991  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_135_WIDTH },
107992  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_136_CHECKER_TYPE,
107993  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_136_WIDTH },
107994  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_137_CHECKER_TYPE,
107995  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_137_WIDTH },
107996  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_138_CHECKER_TYPE,
107997  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_138_WIDTH },
107998  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_139_CHECKER_TYPE,
107999  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_139_WIDTH },
108000  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_140_CHECKER_TYPE,
108001  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_140_WIDTH },
108002  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_141_CHECKER_TYPE,
108003  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_141_WIDTH },
108004  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_142_CHECKER_TYPE,
108005  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_142_WIDTH },
108006  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_143_CHECKER_TYPE,
108007  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_143_WIDTH },
108008  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_144_CHECKER_TYPE,
108009  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_144_WIDTH },
108010  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_145_CHECKER_TYPE,
108011  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_145_WIDTH },
108012  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_146_CHECKER_TYPE,
108013  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_146_WIDTH },
108014  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_147_CHECKER_TYPE,
108015  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_147_WIDTH },
108016  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_148_CHECKER_TYPE,
108017  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_148_WIDTH },
108018  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_149_CHECKER_TYPE,
108019  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_149_WIDTH },
108020  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_150_CHECKER_TYPE,
108021  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_150_WIDTH },
108022  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_151_CHECKER_TYPE,
108023  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_151_WIDTH },
108024  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_152_CHECKER_TYPE,
108025  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_152_WIDTH },
108026  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_153_CHECKER_TYPE,
108027  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_153_WIDTH },
108028  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_154_CHECKER_TYPE,
108029  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_154_WIDTH },
108030  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_155_CHECKER_TYPE,
108031  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_155_WIDTH },
108032  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_156_CHECKER_TYPE,
108033  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_156_WIDTH },
108034  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_157_CHECKER_TYPE,
108035  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_157_WIDTH },
108036  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_158_CHECKER_TYPE,
108037  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_158_WIDTH },
108038  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_159_CHECKER_TYPE,
108039  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_159_WIDTH },
108040  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_160_CHECKER_TYPE,
108041  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_160_WIDTH },
108042  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_161_CHECKER_TYPE,
108043  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_161_WIDTH },
108044  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_162_CHECKER_TYPE,
108045  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_162_WIDTH },
108046  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_163_CHECKER_TYPE,
108047  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_163_WIDTH },
108048  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_164_CHECKER_TYPE,
108049  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_164_WIDTH },
108050  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_165_CHECKER_TYPE,
108051  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_165_WIDTH },
108052  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_166_CHECKER_TYPE,
108053  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_166_WIDTH },
108054  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_167_CHECKER_TYPE,
108055  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_167_WIDTH },
108056  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_168_CHECKER_TYPE,
108057  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_168_WIDTH },
108058  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_169_CHECKER_TYPE,
108059  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_169_WIDTH },
108060  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_170_CHECKER_TYPE,
108061  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_170_WIDTH },
108062  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_171_CHECKER_TYPE,
108063  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_171_WIDTH },
108064  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_172_CHECKER_TYPE,
108065  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_172_WIDTH },
108066  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_173_CHECKER_TYPE,
108067  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_173_WIDTH },
108068  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_174_CHECKER_TYPE,
108069  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_174_WIDTH },
108070  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_175_CHECKER_TYPE,
108071  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_175_WIDTH },
108072  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_176_CHECKER_TYPE,
108073  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_176_WIDTH },
108074  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_177_CHECKER_TYPE,
108075  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_177_WIDTH },
108076  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_178_CHECKER_TYPE,
108077  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_178_WIDTH },
108078  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_179_CHECKER_TYPE,
108079  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_179_WIDTH },
108080  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_180_CHECKER_TYPE,
108081  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_180_WIDTH },
108082  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_181_CHECKER_TYPE,
108083  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_181_WIDTH },
108084  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_182_CHECKER_TYPE,
108085  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_182_WIDTH },
108086  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_183_CHECKER_TYPE,
108087  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_183_WIDTH },
108088  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_184_CHECKER_TYPE,
108089  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_184_WIDTH },
108090  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_185_CHECKER_TYPE,
108091  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_185_WIDTH },
108092  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_186_CHECKER_TYPE,
108093  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_186_WIDTH },
108094  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_187_CHECKER_TYPE,
108095  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_187_WIDTH },
108096  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_188_CHECKER_TYPE,
108097  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_188_WIDTH },
108098  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_189_CHECKER_TYPE,
108099  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_189_WIDTH },
108100  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_190_CHECKER_TYPE,
108101  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_190_WIDTH },
108102  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_191_CHECKER_TYPE,
108103  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_191_WIDTH },
108104  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_192_CHECKER_TYPE,
108105  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_192_WIDTH },
108106  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_193_CHECKER_TYPE,
108107  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_193_WIDTH },
108108  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_194_CHECKER_TYPE,
108109  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_194_WIDTH },
108110  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_195_CHECKER_TYPE,
108111  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_195_WIDTH },
108112  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_196_CHECKER_TYPE,
108113  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_196_WIDTH },
108114  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_197_CHECKER_TYPE,
108115  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_197_WIDTH },
108116  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_198_CHECKER_TYPE,
108117  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_198_WIDTH },
108118  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_199_CHECKER_TYPE,
108119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_199_WIDTH },
108120  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_200_CHECKER_TYPE,
108121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_200_WIDTH },
108122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_201_CHECKER_TYPE,
108123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_201_WIDTH },
108124  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_202_CHECKER_TYPE,
108125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_202_WIDTH },
108126 };
108127 
108133 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
108134 {
108135  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
108136  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
108137  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
108138  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
108139  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
108140  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
108141  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
108142  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
108143  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
108144  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
108145  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
108146  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
108147  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
108148  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
108149  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
108150  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
108151  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
108152  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
108153  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
108154  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
108155  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
108156  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
108157  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
108158  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
108159  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
108160  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
108161  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
108162  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
108163  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
108164  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
108165 };
108166 
108172 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
108173 {
108174  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
108175  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
108176  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
108177  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
108178  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
108179  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
108180  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
108181  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
108182 };
108183 
108189 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
108190 {
108191  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
108192  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
108193  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
108194  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
108195  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
108196  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
108197  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
108198  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
108199  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
108200  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
108201  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
108202  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
108203  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
108204  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
108205  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
108206  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
108207  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
108208  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
108209  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
108210  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
108211  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
108212  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
108213  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
108214  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
108215  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
108216  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
108217  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
108218  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
108219  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
108220  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
108221  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
108222  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
108223  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
108224  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
108225  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
108226  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
108227  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
108228  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
108229  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
108230  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
108231  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
108232  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
108233  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
108234  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
108235  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
108236  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
108237  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
108238  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
108239  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
108240  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
108241 };
108242 
108248 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
108249 {
108250  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
108251  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
108252  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
108253  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
108254  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
108255  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
108256  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
108257  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
108258  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
108259  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
108260  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
108261  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
108262  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
108263  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
108264  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
108265  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
108266  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
108267  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
108268  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
108269  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
108270  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
108271  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
108272  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
108273  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
108274  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
108275  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
108276  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
108277  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
108278  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
108279  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
108280  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
108281  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
108282  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
108283  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
108284  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
108285  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
108286  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
108287  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
108288  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
108289  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
108290  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
108291  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
108292  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
108293  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
108294  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
108295  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
108296  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
108297  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
108298  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
108299  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
108300  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
108301  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
108302  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
108303  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
108304  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
108305  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
108306  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
108307  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
108308  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
108309  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
108310  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
108311  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
108312  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
108313  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
108314  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
108315  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
108316  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
108317  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
108318  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
108319  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
108320  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
108321  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
108322  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
108323  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
108324  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
108325  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
108326  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
108327  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
108328  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
108329  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
108330  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
108331  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
108332  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
108333  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
108334 };
108335 
108341 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
108342 {
108343  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
108344  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
108345  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
108346  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
108347  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
108348  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
108349  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
108350  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
108351 };
108352 
108358 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
108359 {
108360  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
108361  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
108362  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
108363  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
108364  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
108365  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
108366  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
108367  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
108368  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
108369  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
108370  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
108371  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
108372  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
108373  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
108374  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
108375  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
108376  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
108377  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
108378  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
108379  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
108380  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
108381  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
108382  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
108383  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
108384  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
108385  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
108386  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
108387  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
108388  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
108389  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
108390 };
108391 
108397 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS] =
108398 {
108399  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
108400  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_0_WIDTH },
108401  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
108402  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_1_WIDTH },
108403  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
108404  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_2_WIDTH },
108405  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
108406  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_3_WIDTH },
108407  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_4_CHECKER_TYPE,
108408  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_4_WIDTH },
108409  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_5_CHECKER_TYPE,
108410  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_5_WIDTH },
108411  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_6_CHECKER_TYPE,
108412  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_6_WIDTH },
108413  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_7_CHECKER_TYPE,
108414  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_7_WIDTH },
108415  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_8_CHECKER_TYPE,
108416  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_8_WIDTH },
108417  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_9_CHECKER_TYPE,
108418  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_9_WIDTH },
108419  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_10_CHECKER_TYPE,
108420  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_10_WIDTH },
108421  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_11_CHECKER_TYPE,
108422  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_11_WIDTH },
108423  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_12_CHECKER_TYPE,
108424  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_12_WIDTH },
108425  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_13_CHECKER_TYPE,
108426  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_13_WIDTH },
108427 };
108428 
108434 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
108435 {
108436  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
108437  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_0_WIDTH },
108438  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
108439  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_1_WIDTH },
108440  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
108441  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_2_WIDTH },
108442  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
108443  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_3_WIDTH },
108444  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
108445  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_4_WIDTH },
108446  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
108447  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_5_WIDTH },
108448  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
108449  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_6_WIDTH },
108450  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
108451  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_7_WIDTH },
108452  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
108453  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_8_WIDTH },
108454  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
108455  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_9_WIDTH },
108456  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
108457  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_10_WIDTH },
108458  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
108459  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_11_WIDTH },
108460  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
108461  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_12_WIDTH },
108462  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
108463  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_13_WIDTH },
108464  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
108465  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_14_WIDTH },
108466 };
108467 
108473 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS] =
108474 {
108475  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
108476  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_WIDTH },
108477  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
108478  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_WIDTH },
108479  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
108480  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_WIDTH },
108481  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
108482  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_WIDTH },
108483 };
108484 
108490 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS] =
108491 {
108492  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
108493  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_0_WIDTH },
108494  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
108495  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_1_WIDTH },
108496  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
108497  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_2_WIDTH },
108498  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
108499  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_3_WIDTH },
108500  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
108501  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_4_WIDTH },
108502  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
108503  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_5_WIDTH },
108504  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
108505  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_6_WIDTH },
108506  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
108507  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_7_WIDTH },
108508  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
108509  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_8_WIDTH },
108510  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
108511  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_9_WIDTH },
108512  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
108513  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_10_WIDTH },
108514  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
108515  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_11_WIDTH },
108516  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
108517  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_12_WIDTH },
108518  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
108519  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_13_WIDTH },
108520  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
108521  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_14_WIDTH },
108522  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
108523  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_15_WIDTH },
108524  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
108525  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_16_WIDTH },
108526  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
108527  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_17_WIDTH },
108528  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
108529  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_18_WIDTH },
108530  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
108531  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_19_WIDTH },
108532  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
108533  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_20_WIDTH },
108534  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
108535  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_21_WIDTH },
108536  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
108537  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_22_WIDTH },
108538  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
108539  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_23_WIDTH },
108540  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
108541  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_24_WIDTH },
108542  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
108543  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_25_WIDTH },
108544  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
108545  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_26_WIDTH },
108546  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
108547  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_27_WIDTH },
108548  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
108549  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_28_WIDTH },
108550  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
108551  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_29_WIDTH },
108552  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
108553  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_30_WIDTH },
108554  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
108555  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_31_WIDTH },
108556  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
108557  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_32_WIDTH },
108558  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
108559  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_33_WIDTH },
108560  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
108561  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_34_WIDTH },
108562  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
108563  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_35_WIDTH },
108564  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
108565  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_36_WIDTH },
108566  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
108567  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_37_WIDTH },
108568  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
108569  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_38_WIDTH },
108570  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
108571  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_39_WIDTH },
108572  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
108573  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_GROUP_40_WIDTH },
108574 };
108575 
108581 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS] =
108582 {
108583  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
108584  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_0_WIDTH },
108585  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
108586  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_1_WIDTH },
108587  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
108588  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_2_WIDTH },
108589  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
108590  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_3_WIDTH },
108591  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_4_CHECKER_TYPE,
108592  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_4_WIDTH },
108593  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_5_CHECKER_TYPE,
108594  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_5_WIDTH },
108595  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_6_CHECKER_TYPE,
108596  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_6_WIDTH },
108597  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_7_CHECKER_TYPE,
108598  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_7_WIDTH },
108599  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_8_CHECKER_TYPE,
108600  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_8_WIDTH },
108601  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_9_CHECKER_TYPE,
108602  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_9_WIDTH },
108603  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_10_CHECKER_TYPE,
108604  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_10_WIDTH },
108605  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_11_CHECKER_TYPE,
108606  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_11_WIDTH },
108607  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_12_CHECKER_TYPE,
108608  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_12_WIDTH },
108609  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_13_CHECKER_TYPE,
108610  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_13_WIDTH },
108611 };
108612 
108618 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
108619 {
108620  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
108621  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_0_WIDTH },
108622  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
108623  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_1_WIDTH },
108624  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
108625  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_2_WIDTH },
108626  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
108627  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_3_WIDTH },
108628  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
108629  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_4_WIDTH },
108630  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
108631  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_5_WIDTH },
108632  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
108633  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_6_WIDTH },
108634  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
108635  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_7_WIDTH },
108636  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
108637  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_8_WIDTH },
108638  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
108639  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_9_WIDTH },
108640  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
108641  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_10_WIDTH },
108642  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
108643  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_11_WIDTH },
108644  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
108645  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_12_WIDTH },
108646  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
108647  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_13_WIDTH },
108648  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
108649  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_14_WIDTH },
108650 };
108651 
108657 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS] =
108658 {
108659  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
108660  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_WIDTH },
108661  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
108662  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_WIDTH },
108663  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
108664  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_WIDTH },
108665  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
108666  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_WIDTH },
108667 };
108668 
108674 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS] =
108675 {
108676  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
108677  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_0_WIDTH },
108678  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
108679  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_1_WIDTH },
108680  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
108681  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_2_WIDTH },
108682  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
108683  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_3_WIDTH },
108684  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
108685  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_4_WIDTH },
108686  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
108687  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_5_WIDTH },
108688  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
108689  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_6_WIDTH },
108690  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
108691  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_7_WIDTH },
108692  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
108693  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_8_WIDTH },
108694  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
108695  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_9_WIDTH },
108696  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
108697  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_10_WIDTH },
108698  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
108699  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_11_WIDTH },
108700  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
108701  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_12_WIDTH },
108702  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
108703  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_13_WIDTH },
108704  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
108705  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_14_WIDTH },
108706  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
108707  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_15_WIDTH },
108708  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
108709  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_16_WIDTH },
108710  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
108711  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_17_WIDTH },
108712  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
108713  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_18_WIDTH },
108714  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
108715  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_19_WIDTH },
108716  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
108717  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_20_WIDTH },
108718  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
108719  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_21_WIDTH },
108720  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
108721  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_22_WIDTH },
108722  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
108723  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_23_WIDTH },
108724  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
108725  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_24_WIDTH },
108726  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
108727  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_25_WIDTH },
108728  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
108729  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_26_WIDTH },
108730  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
108731  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_27_WIDTH },
108732  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
108733  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_28_WIDTH },
108734  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
108735  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_29_WIDTH },
108736  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
108737  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_30_WIDTH },
108738  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
108739  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_31_WIDTH },
108740  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
108741  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_32_WIDTH },
108742  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
108743  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_33_WIDTH },
108744  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
108745  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_34_WIDTH },
108746  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
108747  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_35_WIDTH },
108748  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
108749  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_36_WIDTH },
108750  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
108751  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_37_WIDTH },
108752  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
108753  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_38_WIDTH },
108754  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
108755  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_39_WIDTH },
108756  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
108757  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_40_WIDTH },
108758 };
108759 
108765 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS] =
108766 {
108767  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
108768  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_0_WIDTH },
108769  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
108770  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_1_WIDTH },
108771  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
108772  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_2_WIDTH },
108773  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
108774  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_3_WIDTH },
108775  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_4_CHECKER_TYPE,
108776  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_4_WIDTH },
108777  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_5_CHECKER_TYPE,
108778  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_5_WIDTH },
108779  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_6_CHECKER_TYPE,
108780  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_6_WIDTH },
108781  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_7_CHECKER_TYPE,
108782  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_7_WIDTH },
108783  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_8_CHECKER_TYPE,
108784  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_8_WIDTH },
108785  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_9_CHECKER_TYPE,
108786  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_9_WIDTH },
108787  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_10_CHECKER_TYPE,
108788  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_10_WIDTH },
108789  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_11_CHECKER_TYPE,
108790  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_11_WIDTH },
108791  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_12_CHECKER_TYPE,
108792  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_12_WIDTH },
108793  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_13_CHECKER_TYPE,
108794  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_GROUP_13_WIDTH },
108795 };
108796 
108802 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
108803 {
108804  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
108805  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_0_WIDTH },
108806  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
108807  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_1_WIDTH },
108808  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
108809  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_2_WIDTH },
108810  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
108811  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_3_WIDTH },
108812  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
108813  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_4_WIDTH },
108814  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
108815  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_5_WIDTH },
108816  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
108817  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_6_WIDTH },
108818  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
108819  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_7_WIDTH },
108820  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
108821  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_8_WIDTH },
108822  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
108823  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_9_WIDTH },
108824  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
108825  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_10_WIDTH },
108826  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
108827  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_11_WIDTH },
108828  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
108829  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_12_WIDTH },
108830  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
108831  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_13_WIDTH },
108832  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
108833  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_GROUP_14_WIDTH },
108834 };
108835 
108841 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS] =
108842 {
108843  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
108844  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_0_WIDTH },
108845  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
108846  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_1_WIDTH },
108847  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
108848  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_2_WIDTH },
108849  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
108850  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_GROUP_3_WIDTH },
108851 };
108852 
108858 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS] =
108859 {
108860  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
108861  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_0_WIDTH },
108862  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
108863  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_1_WIDTH },
108864  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
108865  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_2_WIDTH },
108866  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
108867  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_3_WIDTH },
108868  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
108869  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_4_WIDTH },
108870  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
108871  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_5_WIDTH },
108872  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
108873  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_6_WIDTH },
108874  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
108875  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_7_WIDTH },
108876  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
108877  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_8_WIDTH },
108878  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
108879  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_9_WIDTH },
108880  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
108881  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_10_WIDTH },
108882  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
108883  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_11_WIDTH },
108884  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
108885  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_12_WIDTH },
108886  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
108887  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_13_WIDTH },
108888  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
108889  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_14_WIDTH },
108890  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
108891  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_15_WIDTH },
108892  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
108893  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_16_WIDTH },
108894  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
108895  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_17_WIDTH },
108896  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
108897  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_18_WIDTH },
108898  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
108899  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_19_WIDTH },
108900  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
108901  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_20_WIDTH },
108902  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
108903  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_21_WIDTH },
108904  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
108905  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_22_WIDTH },
108906  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
108907  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_23_WIDTH },
108908  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
108909  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_24_WIDTH },
108910  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
108911  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_25_WIDTH },
108912  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
108913  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_26_WIDTH },
108914  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
108915  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_27_WIDTH },
108916  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
108917  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_28_WIDTH },
108918  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
108919  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_29_WIDTH },
108920  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
108921  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_30_WIDTH },
108922  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
108923  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_31_WIDTH },
108924  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
108925  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_32_WIDTH },
108926  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
108927  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_33_WIDTH },
108928  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
108929  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_34_WIDTH },
108930  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
108931  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_35_WIDTH },
108932  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
108933  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_36_WIDTH },
108934  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
108935  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_37_WIDTH },
108936  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
108937  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_38_WIDTH },
108938  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
108939  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_39_WIDTH },
108940  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
108941  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_GROUP_40_WIDTH },
108942 };
108943 
108949 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
108950 {
108951  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
108952  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
108953  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
108954  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
108955  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
108956  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
108957  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
108958  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
108959  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
108960  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
108961  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
108962  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
108963  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
108964  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
108965  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
108966  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
108967  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
108968  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
108969  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
108970  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
108971  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
108972  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
108973  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
108974  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
108975  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
108976  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
108977  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
108978  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
108979  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
108980  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
108981  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
108982  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
108983  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
108984  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
108985  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
108986  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
108987  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
108988  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
108989  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
108990  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
108991  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
108992  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
108993  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
108994  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
108995 };
108996 
109002 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
109003 {
109004  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
109005  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
109006  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
109007  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
109008  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
109009  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
109010  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
109011  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
109012  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
109013  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
109014  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
109015  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
109016  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
109017  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
109018  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
109019  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
109020  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
109021  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
109022  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
109023  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
109024  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
109025  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
109026  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
109027  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
109028  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
109029  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
109030  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
109031  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
109032  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
109033  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
109034  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
109035  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
109036  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
109037  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
109038  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
109039  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
109040  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
109041  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
109042  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
109043  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
109044  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
109045  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
109046  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
109047  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
109048 };
109049 
109055 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
109056 {
109057  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
109058  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
109059  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
109060  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
109061  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
109062  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
109063  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
109064  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
109065  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
109066  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
109067  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
109068  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
109069  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
109070  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
109071  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
109072  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
109073  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
109074  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
109075  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
109076  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
109077  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
109078  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
109079  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
109080  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
109081  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
109082  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
109083  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
109084  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
109085  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
109086  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
109087 };
109088 
109094 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
109095 {
109096  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
109097  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
109098  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
109099  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
109100  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
109101  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
109102  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
109103  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
109104 };
109105 
109111 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
109112 {
109113  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
109114  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
109115  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
109116  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
109117  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
109118  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
109119 };
109120 
109126 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
109127 {
109128  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
109129  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
109130  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
109131  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_1_WIDTH },
109132  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
109133  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_GROUP_2_WIDTH },
109134 };
109135 
109141 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
109142 {
109143  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
109144  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
109145  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
109146  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
109147  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
109148  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
109149  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
109150  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
109151  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
109152  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
109153  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
109154  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
109155  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
109156  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
109157  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
109158  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
109159  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
109160  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
109161  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
109162  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
109163  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
109164  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
109165  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
109166  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
109167  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
109168  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
109169  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
109170  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
109171  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
109172  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
109173  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
109174  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
109175  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
109176  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
109177  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
109178  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
109179  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
109180  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
109181  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
109182  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
109183  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
109184  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
109185  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
109186  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
109187  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
109188  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
109189  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
109190  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
109191  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
109192  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
109193  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
109194  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
109195  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
109196  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
109197  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
109198  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
109199  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
109200  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
109201  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
109202  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
109203  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
109204  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
109205  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
109206  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
109207  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
109208  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
109209  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
109210  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
109211  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
109212  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
109213  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
109214  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
109215  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
109216  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
109217  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
109218  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
109219  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
109220  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
109221  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
109222  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
109223  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
109224  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
109225  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
109226  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
109227 };
109228 
109234 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS] =
109235 {
109236  { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
109237  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_WIDTH },
109238  { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
109239  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_WIDTH },
109240  { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
109241  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_WIDTH },
109242  { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
109243  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_WIDTH },
109244 };
109245 
109251 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS] =
109252 {
109253  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_CHECKER_TYPE,
109254  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_WIDTH },
109255  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_CHECKER_TYPE,
109256  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_WIDTH },
109257  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_CHECKER_TYPE,
109258  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_WIDTH },
109259  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_CHECKER_TYPE,
109260  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_WIDTH },
109261 };
109262 
109268 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS] =
109269 {
109270  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
109271  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_0_WIDTH },
109272  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
109273  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_1_WIDTH },
109274  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
109275  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_2_WIDTH },
109276  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
109277  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_3_WIDTH },
109278  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
109279  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_4_WIDTH },
109280  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
109281  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_5_WIDTH },
109282  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
109283  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_6_WIDTH },
109284  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
109285  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_7_WIDTH },
109286  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
109287  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_8_WIDTH },
109288  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
109289  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_9_WIDTH },
109290  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
109291  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_10_WIDTH },
109292  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
109293  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_11_WIDTH },
109294  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
109295  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_12_WIDTH },
109296  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
109297  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_13_WIDTH },
109298  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
109299  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_14_WIDTH },
109300  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
109301  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_15_WIDTH },
109302  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
109303  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_16_WIDTH },
109304  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
109305  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_17_WIDTH },
109306  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
109307  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_18_WIDTH },
109308  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
109309  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_19_WIDTH },
109310  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
109311  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_20_WIDTH },
109312  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
109313  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_21_WIDTH },
109314  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
109315  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_22_WIDTH },
109316  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
109317  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_23_WIDTH },
109318  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
109319  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_24_WIDTH },
109320  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
109321  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_25_WIDTH },
109322  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
109323  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_26_WIDTH },
109324  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
109325  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_27_WIDTH },
109326  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
109327  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_28_WIDTH },
109328  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
109329  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_29_WIDTH },
109330  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
109331  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_30_WIDTH },
109332  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
109333  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_31_WIDTH },
109334  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
109335  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_32_WIDTH },
109336  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
109337  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_33_WIDTH },
109338  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
109339  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_34_WIDTH },
109340  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
109341  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_35_WIDTH },
109342  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
109343  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_36_WIDTH },
109344  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
109345  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_37_WIDTH },
109346  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
109347  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_38_WIDTH },
109348  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
109349  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_39_WIDTH },
109350  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
109351  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_GROUP_40_WIDTH },
109352 };
109353 
109359 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
109360 {
109361  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
109362  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
109363  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
109364  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
109365  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
109366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
109367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
109368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
109369  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
109370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
109371  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
109372  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
109373  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
109374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
109375  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
109376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
109377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
109378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
109379  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
109380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
109381  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
109382  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
109383  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
109384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
109385  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
109386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
109387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
109388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
109389  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
109390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
109391 };
109392 
109398 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
109399 {
109400  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
109401  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
109402  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
109403  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
109404  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
109405  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
109406  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
109407  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
109408 };
109409 
109415 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
109416 {
109417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
109418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
109419  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
109420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
109421  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
109422  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
109423  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
109424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
109425  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
109426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
109427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
109428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
109429  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
109430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
109431  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
109432  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
109433  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
109434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
109435  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
109436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
109437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
109438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
109439  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
109440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
109441  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
109442  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
109443  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
109444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
109445  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
109446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
109447 };
109448 
109454 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
109455 {
109456  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
109457  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
109458  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
109459  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
109460  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
109461  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
109462  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
109463  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
109464 };
109465 
109471 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
109472 {
109473  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
109474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
109475  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
109476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
109477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
109478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
109479  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
109480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
109481  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
109482  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
109483  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
109484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
109485  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
109486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
109487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
109488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
109489  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
109490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
109491  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
109492  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
109493  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
109494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
109495  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
109496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
109497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
109498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
109499  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
109500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
109501  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
109502  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
109503 };
109504 
109510 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
109511 {
109512  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
109513  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
109514  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
109515  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
109516  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
109517  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
109518  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
109519  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
109520 };
109521 
109527 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
109528 {
109529  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
109530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
109531  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
109532  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
109533  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
109534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
109535 };
109536 
109542 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
109543 {
109544  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
109545  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
109546  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
109547  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
109548  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
109549  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
109550  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
109551  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
109552  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
109553  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
109554  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
109555  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
109556  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
109557  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
109558  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
109559  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
109560  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
109561  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
109562  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
109563  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
109564  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
109565  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
109566  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
109567  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
109568  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
109569  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
109570  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
109571  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
109572  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
109573  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
109574  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
109575  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
109576  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
109577  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
109578  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
109579  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
109580  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
109581  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
109582  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
109583  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
109584  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
109585  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
109586  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
109587  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
109588  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
109589  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
109590  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
109591  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
109592  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
109593  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
109594  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
109595  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
109596  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
109597  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
109598  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
109599  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
109600  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
109601  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
109602  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
109603  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
109604  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
109605  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
109606  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
109607  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
109608  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
109609  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
109610  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
109611  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
109612  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
109613  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
109614  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
109615  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
109616  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
109617  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
109618  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
109619  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
109620  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
109621  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
109622  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
109623  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
109624  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
109625  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
109626 };
109627 
109633 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
109634 {
109635  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
109636  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_GROUP_0_WIDTH },
109637 };
109638 
109644 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
109645 {
109646  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
109647  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
109648 };
109649 
109655 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
109656 {
109657  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
109658  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
109659 };
109660 
109666 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
109667 {
109668  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
109669  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
109670  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
109671  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
109672  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
109673  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
109674  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
109675  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
109676  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
109677  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
109678  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
109679  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
109680  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
109681  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
109682  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
109683  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
109684  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
109685  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
109686  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
109687  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
109688  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
109689  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
109690  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
109691  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
109692  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
109693  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
109694  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
109695  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
109696  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
109697  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
109698  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
109699  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
109700  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
109701  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
109702  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
109703  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
109704  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
109705  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
109706  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
109707  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
109708  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
109709  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
109710  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
109711  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
109712 };
109713 
109719 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
109720 {
109721  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
109722  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
109723 };
109724 
109730 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
109731 {
109732  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
109733  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
109734  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
109735  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
109736  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
109737  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
109738  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
109739  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
109740  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
109741  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
109742  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
109743  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
109744  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
109745  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
109746  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
109747  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
109748  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
109749  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
109750  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
109751  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
109752  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
109753  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
109754  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
109755  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
109756  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
109757  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
109758  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
109759  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
109760  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
109761  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
109762  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
109763  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
109764  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
109765  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
109766  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
109767  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
109768  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
109769  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
109770  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
109771  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
109772  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
109773  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
109774  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
109775  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
109776  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
109777  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
109778  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
109779  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
109780  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
109781  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
109782  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
109783  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
109784  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
109785  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
109786  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
109787  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
109788  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
109789  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
109790  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
109791  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
109792  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
109793  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
109794  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
109795  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
109796  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
109797  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
109798  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
109799  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
109800  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
109801  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
109802  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
109803  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
109804  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
109805  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
109806  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
109807  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
109808  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
109809  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
109810  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
109811  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
109812  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
109813  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
109814  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
109815  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
109816  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
109817  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
109818  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
109819  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
109820  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
109821  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
109822  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
109823  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
109824  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
109825  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
109826  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
109827  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
109828 };
109829 
109835 static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
109836 {
109837  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
109838  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
109839  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
109840  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
109841  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
109842  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
109843  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
109844  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
109845  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
109846  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
109847  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
109848  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
109849 };
109850 
109856 static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS] =
109857 {
109858  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_0_CHECKER_TYPE,
109859  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_0_WIDTH },
109860  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_1_CHECKER_TYPE,
109861  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_1_WIDTH },
109862  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_2_CHECKER_TYPE,
109863  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_2_WIDTH },
109864  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_3_CHECKER_TYPE,
109865  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_3_WIDTH },
109866  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_4_CHECKER_TYPE,
109867  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_4_WIDTH },
109868  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_5_CHECKER_TYPE,
109869  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_5_WIDTH },
109870  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_6_CHECKER_TYPE,
109871  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_6_WIDTH },
109872  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_7_CHECKER_TYPE,
109873  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_7_WIDTH },
109874  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_8_CHECKER_TYPE,
109875  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_8_WIDTH },
109876  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_9_CHECKER_TYPE,
109877  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_9_WIDTH },
109878  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_10_CHECKER_TYPE,
109879  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_10_WIDTH },
109880  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_11_CHECKER_TYPE,
109881  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_11_WIDTH },
109882  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_12_CHECKER_TYPE,
109883  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_12_WIDTH },
109884  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_13_CHECKER_TYPE,
109885  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_13_WIDTH },
109886  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_14_CHECKER_TYPE,
109887  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_14_WIDTH },
109888  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_15_CHECKER_TYPE,
109889  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_15_WIDTH },
109890  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_16_CHECKER_TYPE,
109891  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_16_WIDTH },
109892  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_17_CHECKER_TYPE,
109893  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_17_WIDTH },
109894  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_18_CHECKER_TYPE,
109895  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_18_WIDTH },
109896  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_19_CHECKER_TYPE,
109897  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_19_WIDTH },
109898  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_20_CHECKER_TYPE,
109899  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_20_WIDTH },
109900  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_21_CHECKER_TYPE,
109901  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_21_WIDTH },
109902  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_22_CHECKER_TYPE,
109903  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_22_WIDTH },
109904  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_23_CHECKER_TYPE,
109905  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_23_WIDTH },
109906  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_24_CHECKER_TYPE,
109907  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_24_WIDTH },
109908  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_25_CHECKER_TYPE,
109909  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_25_WIDTH },
109910  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_26_CHECKER_TYPE,
109911  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_26_WIDTH },
109912  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_27_CHECKER_TYPE,
109913  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_27_WIDTH },
109914  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_28_CHECKER_TYPE,
109915  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_28_WIDTH },
109916  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_29_CHECKER_TYPE,
109917  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_29_WIDTH },
109918  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_30_CHECKER_TYPE,
109919  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_30_WIDTH },
109920  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_31_CHECKER_TYPE,
109921  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_31_WIDTH },
109922  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_32_CHECKER_TYPE,
109923  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_32_WIDTH },
109924  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_33_CHECKER_TYPE,
109925  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_33_WIDTH },
109926  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_34_CHECKER_TYPE,
109927  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_GROUP_34_WIDTH },
109928 };
109929 
109935 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_MAX_NUM_CHECKERS] =
109936 {
109937  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
109938  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_0_WIDTH },
109939  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
109940  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_1_WIDTH },
109941  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
109942  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_2_WIDTH },
109943  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
109944  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_GROUP_3_WIDTH },
109945 };
109946 
109952 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS] =
109953 {
109954  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
109955  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_0_WIDTH },
109956  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
109957  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_1_WIDTH },
109958  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
109959  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_2_WIDTH },
109960  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
109961  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_3_WIDTH },
109962  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
109963  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_4_WIDTH },
109964  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
109965  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_5_WIDTH },
109966  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
109967  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_6_WIDTH },
109968  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
109969  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_7_WIDTH },
109970  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
109971  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_8_WIDTH },
109972  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
109973  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_9_WIDTH },
109974  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
109975  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_10_WIDTH },
109976  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
109977  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_11_WIDTH },
109978  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
109979  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_12_WIDTH },
109980  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
109981  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_13_WIDTH },
109982  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
109983  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_14_WIDTH },
109984  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
109985  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_15_WIDTH },
109986  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
109987  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_16_WIDTH },
109988  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
109989  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_17_WIDTH },
109990  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
109991  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_18_WIDTH },
109992  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
109993  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_19_WIDTH },
109994  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
109995  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_20_WIDTH },
109996  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
109997  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_21_WIDTH },
109998  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
109999  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_22_WIDTH },
110000  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
110001  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_23_WIDTH },
110002  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
110003  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_24_WIDTH },
110004  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
110005  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_25_WIDTH },
110006  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
110007  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_26_WIDTH },
110008  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
110009  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_27_WIDTH },
110010  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
110011  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_28_WIDTH },
110012  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
110013  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_29_WIDTH },
110014  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
110015  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_30_WIDTH },
110016  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
110017  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_31_WIDTH },
110018  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
110019  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_32_WIDTH },
110020  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
110021  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_33_WIDTH },
110022  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
110023  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_34_WIDTH },
110024  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
110025  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_35_WIDTH },
110026  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
110027  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_36_WIDTH },
110028  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
110029  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_37_WIDTH },
110030  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
110031  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_38_WIDTH },
110032  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
110033  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_39_WIDTH },
110034  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
110035  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_GROUP_40_WIDTH },
110036 };
110037 
110043 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_MAX_NUM_CHECKERS] =
110044 {
110045  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
110046  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_0_WIDTH },
110047  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
110048  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_1_WIDTH },
110049  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
110050  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_2_WIDTH },
110051  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
110052  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_3_WIDTH },
110053  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
110054  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_4_WIDTH },
110055  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
110056  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_5_WIDTH },
110057  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
110058  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_6_WIDTH },
110059  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
110060  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_7_WIDTH },
110061  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
110062  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_8_WIDTH },
110063  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
110064  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_9_WIDTH },
110065  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
110066  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_10_WIDTH },
110067  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
110068  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_11_WIDTH },
110069  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
110070  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_12_WIDTH },
110071  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
110072  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_13_WIDTH },
110073  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
110074  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_14_WIDTH },
110075  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
110076  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_15_WIDTH },
110077  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
110078  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_16_WIDTH },
110079  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
110080  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_17_WIDTH },
110081  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
110082  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_18_WIDTH },
110083  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
110084  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_19_WIDTH },
110085  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
110086  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_20_WIDTH },
110087  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
110088  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_21_WIDTH },
110089  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
110090  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_22_WIDTH },
110091  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
110092  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_23_WIDTH },
110093  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
110094  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_24_WIDTH },
110095  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
110096  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_25_WIDTH },
110097  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
110098  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_26_WIDTH },
110099  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
110100  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_27_WIDTH },
110101  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
110102  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_28_WIDTH },
110103  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
110104  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_29_WIDTH },
110105  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
110106  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_30_WIDTH },
110107  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
110108  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_31_WIDTH },
110109  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
110110  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_32_WIDTH },
110111  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
110112  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_33_WIDTH },
110113  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
110114  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_34_WIDTH },
110115  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
110116  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_35_WIDTH },
110117  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
110118  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_36_WIDTH },
110119  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
110120  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_37_WIDTH },
110121  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
110122  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_38_WIDTH },
110123  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
110124  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_39_WIDTH },
110125  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
110126  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_GROUP_40_WIDTH },
110127 };
110128 
110134 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS] =
110135 {
110136  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
110137  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_0_WIDTH },
110138  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
110139  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_1_WIDTH },
110140  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
110141  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_2_WIDTH },
110142  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
110143  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_3_WIDTH },
110144  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_4_CHECKER_TYPE,
110145  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_4_WIDTH },
110146  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_5_CHECKER_TYPE,
110147  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_5_WIDTH },
110148  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_6_CHECKER_TYPE,
110149  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_6_WIDTH },
110150  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_7_CHECKER_TYPE,
110151  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_7_WIDTH },
110152  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_8_CHECKER_TYPE,
110153  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_8_WIDTH },
110154  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_9_CHECKER_TYPE,
110155  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_9_WIDTH },
110156  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_10_CHECKER_TYPE,
110157  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_10_WIDTH },
110158  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_11_CHECKER_TYPE,
110159  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_11_WIDTH },
110160  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_12_CHECKER_TYPE,
110161  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_12_WIDTH },
110162  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_13_CHECKER_TYPE,
110163  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_GROUP_13_WIDTH },
110164 };
110165 
110171 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
110172 {
110173  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
110174  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_0_WIDTH },
110175  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
110176  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_1_WIDTH },
110177  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
110178  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_2_WIDTH },
110179  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
110180  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_3_WIDTH },
110181  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
110182  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_4_WIDTH },
110183  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
110184  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_5_WIDTH },
110185  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
110186  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_6_WIDTH },
110187  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
110188  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_7_WIDTH },
110189  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
110190  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_8_WIDTH },
110191  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
110192  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_9_WIDTH },
110193  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
110194  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_10_WIDTH },
110195  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
110196  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_11_WIDTH },
110197  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
110198  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_12_WIDTH },
110199  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
110200  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_13_WIDTH },
110201  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
110202  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_GROUP_14_WIDTH },
110203 };
110204 
110210 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_MAX_NUM_CHECKERS] =
110211 {
110212  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
110213  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_0_WIDTH },
110214  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
110215  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_1_WIDTH },
110216  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
110217  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_2_WIDTH },
110218  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
110219  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_GROUP_3_WIDTH },
110220 };
110221 
110227 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_MAX_NUM_CHECKERS] =
110228 {
110229  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_0_CHECKER_TYPE,
110230  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_0_WIDTH },
110231  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_1_CHECKER_TYPE,
110232  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_1_WIDTH },
110233  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_2_CHECKER_TYPE,
110234  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_2_WIDTH },
110235  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_3_CHECKER_TYPE,
110236  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_GROUP_3_WIDTH },
110237 };
110238 
110244 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS] =
110245 {
110246  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
110247  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_0_WIDTH },
110248  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
110249  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_1_WIDTH },
110250  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
110251  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_2_WIDTH },
110252  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
110253  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_3_WIDTH },
110254  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_4_CHECKER_TYPE,
110255  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_4_WIDTH },
110256  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_5_CHECKER_TYPE,
110257  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_5_WIDTH },
110258  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_6_CHECKER_TYPE,
110259  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_6_WIDTH },
110260  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_7_CHECKER_TYPE,
110261  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_7_WIDTH },
110262  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_8_CHECKER_TYPE,
110263  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_8_WIDTH },
110264  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_9_CHECKER_TYPE,
110265  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_9_WIDTH },
110266  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_10_CHECKER_TYPE,
110267  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_10_WIDTH },
110268  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_11_CHECKER_TYPE,
110269  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_11_WIDTH },
110270  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_12_CHECKER_TYPE,
110271  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_12_WIDTH },
110272  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_13_CHECKER_TYPE,
110273  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_GROUP_13_WIDTH },
110274 };
110275 
110281 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_MAX_NUM_CHECKERS] =
110282 {
110283  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
110284  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_0_WIDTH },
110285  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
110286  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_1_WIDTH },
110287  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
110288  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_2_WIDTH },
110289  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
110290  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_3_WIDTH },
110291  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
110292  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_4_WIDTH },
110293  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
110294  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_5_WIDTH },
110295  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
110296  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_6_WIDTH },
110297  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
110298  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_7_WIDTH },
110299  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
110300  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_8_WIDTH },
110301  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
110302  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_9_WIDTH },
110303  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
110304  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_10_WIDTH },
110305  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
110306  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_11_WIDTH },
110307  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
110308  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_12_WIDTH },
110309  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
110310  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_13_WIDTH },
110311  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
110312  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_14_WIDTH },
110313  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
110314  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_15_WIDTH },
110315  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
110316  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_16_WIDTH },
110317  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
110318  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_17_WIDTH },
110319  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
110320  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_18_WIDTH },
110321  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
110322  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_19_WIDTH },
110323  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
110324  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_20_WIDTH },
110325  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
110326  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_21_WIDTH },
110327  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
110328  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_22_WIDTH },
110329  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
110330  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_23_WIDTH },
110331  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
110332  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_24_WIDTH },
110333  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
110334  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_25_WIDTH },
110335  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
110336  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_26_WIDTH },
110337  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
110338  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_27_WIDTH },
110339  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
110340  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_28_WIDTH },
110341  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
110342  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_29_WIDTH },
110343  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
110344  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_30_WIDTH },
110345  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
110346  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_31_WIDTH },
110347  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
110348  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_32_WIDTH },
110349  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
110350  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_33_WIDTH },
110351  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
110352  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_34_WIDTH },
110353  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
110354  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_35_WIDTH },
110355  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
110356  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_36_WIDTH },
110357  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
110358  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_37_WIDTH },
110359  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
110360  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_38_WIDTH },
110361  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
110362  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_39_WIDTH },
110363  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
110364  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_GROUP_40_WIDTH },
110365 };
110366 
110372 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS] =
110373 {
110374  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
110375  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_0_WIDTH },
110376  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
110377  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_1_WIDTH },
110378  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
110379  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_2_WIDTH },
110380  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
110381  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_3_WIDTH },
110382  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_4_CHECKER_TYPE,
110383  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_4_WIDTH },
110384  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_5_CHECKER_TYPE,
110385  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_5_WIDTH },
110386  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_6_CHECKER_TYPE,
110387  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_6_WIDTH },
110388  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_7_CHECKER_TYPE,
110389  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_7_WIDTH },
110390  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_8_CHECKER_TYPE,
110391  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_8_WIDTH },
110392  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_9_CHECKER_TYPE,
110393  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_9_WIDTH },
110394  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_10_CHECKER_TYPE,
110395  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_10_WIDTH },
110396  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_11_CHECKER_TYPE,
110397  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_11_WIDTH },
110398  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_12_CHECKER_TYPE,
110399  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_12_WIDTH },
110400  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_13_CHECKER_TYPE,
110401  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_GROUP_13_WIDTH },
110402 };
110403 
110409 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
110410 {
110411  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
110412  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_0_WIDTH },
110413  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
110414  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_1_WIDTH },
110415  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
110416  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_2_WIDTH },
110417  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
110418  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_3_WIDTH },
110419  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
110420  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_4_WIDTH },
110421  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
110422  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_5_WIDTH },
110423  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
110424  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_6_WIDTH },
110425  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
110426  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_7_WIDTH },
110427  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
110428  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_8_WIDTH },
110429  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
110430  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_9_WIDTH },
110431  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
110432  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_10_WIDTH },
110433  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
110434  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_11_WIDTH },
110435  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
110436  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_12_WIDTH },
110437  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
110438  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_13_WIDTH },
110439  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
110440  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_GROUP_14_WIDTH },
110441 };
110442 
110448 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_MAX_NUM_CHECKERS] =
110449 {
110450  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
110451  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_0_WIDTH },
110452  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
110453  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_1_WIDTH },
110454  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
110455  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_2_WIDTH },
110456  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
110457  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_3_WIDTH },
110458  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
110459  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_4_WIDTH },
110460  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
110461  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_5_WIDTH },
110462  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
110463  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_6_WIDTH },
110464  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
110465  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_7_WIDTH },
110466  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
110467  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_8_WIDTH },
110468  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
110469  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_9_WIDTH },
110470  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
110471  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_10_WIDTH },
110472  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
110473  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_11_WIDTH },
110474  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
110475  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_12_WIDTH },
110476  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
110477  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_13_WIDTH },
110478  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
110479  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_14_WIDTH },
110480  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
110481  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_15_WIDTH },
110482  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
110483  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_16_WIDTH },
110484  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
110485  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_17_WIDTH },
110486  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
110487  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_18_WIDTH },
110488  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
110489  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_19_WIDTH },
110490  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
110491  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_20_WIDTH },
110492  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
110493  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_21_WIDTH },
110494  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
110495  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_22_WIDTH },
110496  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
110497  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_23_WIDTH },
110498  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
110499  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_24_WIDTH },
110500  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
110501  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_25_WIDTH },
110502  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
110503  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_26_WIDTH },
110504  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
110505  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_27_WIDTH },
110506  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
110507  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_28_WIDTH },
110508  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
110509  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_29_WIDTH },
110510  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
110511  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_30_WIDTH },
110512  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
110513  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_31_WIDTH },
110514  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
110515  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_32_WIDTH },
110516  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
110517  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_33_WIDTH },
110518  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
110519  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_34_WIDTH },
110520  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
110521  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_35_WIDTH },
110522  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
110523  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_36_WIDTH },
110524  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
110525  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_37_WIDTH },
110526  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
110527  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_38_WIDTH },
110528  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
110529  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_39_WIDTH },
110530  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
110531  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_GROUP_40_WIDTH },
110532 };
110533 
110539 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_MAX_NUM_CHECKERS] =
110540 {
110541  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
110542  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_0_WIDTH },
110543  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
110544  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_1_WIDTH },
110545  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
110546  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_2_WIDTH },
110547  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
110548  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_3_WIDTH },
110549  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
110550  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_4_WIDTH },
110551  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
110552  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_5_WIDTH },
110553  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
110554  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_6_WIDTH },
110555  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
110556  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_7_WIDTH },
110557  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
110558  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_8_WIDTH },
110559  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
110560  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_9_WIDTH },
110561  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
110562  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_10_WIDTH },
110563  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
110564  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_11_WIDTH },
110565  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
110566  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_12_WIDTH },
110567  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
110568  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_13_WIDTH },
110569  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
110570  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_14_WIDTH },
110571  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
110572  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_15_WIDTH },
110573  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
110574  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_16_WIDTH },
110575  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
110576  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_17_WIDTH },
110577  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
110578  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_18_WIDTH },
110579  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
110580  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_19_WIDTH },
110581  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
110582  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_20_WIDTH },
110583  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
110584  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_21_WIDTH },
110585  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
110586  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_22_WIDTH },
110587  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
110588  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_23_WIDTH },
110589  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
110590  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_24_WIDTH },
110591  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
110592  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_25_WIDTH },
110593  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
110594  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_26_WIDTH },
110595  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
110596  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_27_WIDTH },
110597  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
110598  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_28_WIDTH },
110599  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
110600  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_29_WIDTH },
110601  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
110602  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_30_WIDTH },
110603  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
110604  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_31_WIDTH },
110605  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
110606  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_32_WIDTH },
110607  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
110608  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_33_WIDTH },
110609  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
110610  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_34_WIDTH },
110611  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
110612  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_35_WIDTH },
110613  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
110614  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_36_WIDTH },
110615  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
110616  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_37_WIDTH },
110617  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
110618  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_38_WIDTH },
110619  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
110620  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_39_WIDTH },
110621  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
110622  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_GROUP_40_WIDTH },
110623 };
110624 
110630 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_MAX_NUM_CHECKERS] =
110631 {
110632  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
110633  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_0_WIDTH },
110634  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
110635  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_1_WIDTH },
110636  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
110637  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_2_WIDTH },
110638  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
110639  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_GROUP_3_WIDTH },
110640 };
110641 
110647 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_MAX_NUM_CHECKERS] =
110648 {
110649  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
110650  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_0_WIDTH },
110651  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
110652  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_1_WIDTH },
110653  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
110654  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_2_WIDTH },
110655  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
110656  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_GROUP_3_WIDTH },
110657 };
110658 
110664 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_MAX_NUM_CHECKERS] =
110665 {
110666  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_0_CHECKER_TYPE,
110667  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_0_WIDTH },
110668  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_1_CHECKER_TYPE,
110669  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_1_WIDTH },
110670  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_2_CHECKER_TYPE,
110671  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_2_WIDTH },
110672  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_3_CHECKER_TYPE,
110673  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_GROUP_3_WIDTH },
110674 };
110675 
110681 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_MAX_NUM_CHECKERS] =
110682 {
110683  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_0_CHECKER_TYPE,
110684  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_0_WIDTH },
110685  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_1_CHECKER_TYPE,
110686  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_1_WIDTH },
110687  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_2_CHECKER_TYPE,
110688  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_2_WIDTH },
110689  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_3_CHECKER_TYPE,
110690  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_GROUP_3_WIDTH },
110691 };
110692 
110698 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS] =
110699 {
110700  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
110701  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_0_WIDTH },
110702  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
110703  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_1_WIDTH },
110704  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
110705  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_2_WIDTH },
110706  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
110707  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_GROUP_3_WIDTH },
110708 };
110709 
110715 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_MAX_NUM_CHECKERS] =
110716 {
110717  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_0_CHECKER_TYPE,
110718  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_0_WIDTH },
110719  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_1_CHECKER_TYPE,
110720  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_1_WIDTH },
110721  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_2_CHECKER_TYPE,
110722  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_2_WIDTH },
110723  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_3_CHECKER_TYPE,
110724  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_GROUP_3_WIDTH },
110725 };
110726 
110732 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_MAX_NUM_CHECKERS] =
110733 {
110734  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
110735  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_0_WIDTH },
110736  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
110737  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_1_WIDTH },
110738  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
110739  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_2_WIDTH },
110740  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
110741  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_3_WIDTH },
110742  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
110743  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_4_WIDTH },
110744  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
110745  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_5_WIDTH },
110746  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
110747  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_6_WIDTH },
110748  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
110749  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_7_WIDTH },
110750  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
110751  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_8_WIDTH },
110752  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
110753  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_9_WIDTH },
110754  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
110755  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_10_WIDTH },
110756  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
110757  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_11_WIDTH },
110758  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
110759  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_12_WIDTH },
110760  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
110761  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_13_WIDTH },
110762  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
110763  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_14_WIDTH },
110764  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
110765  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_15_WIDTH },
110766  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
110767  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_16_WIDTH },
110768  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
110769  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_17_WIDTH },
110770  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
110771  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_18_WIDTH },
110772  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
110773  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_19_WIDTH },
110774  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
110775  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_20_WIDTH },
110776  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
110777  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_21_WIDTH },
110778  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
110779  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_22_WIDTH },
110780  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
110781  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_23_WIDTH },
110782  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
110783  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_24_WIDTH },
110784  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
110785  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_25_WIDTH },
110786  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
110787  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_26_WIDTH },
110788  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
110789  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_27_WIDTH },
110790  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
110791  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_28_WIDTH },
110792  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
110793  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_29_WIDTH },
110794  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
110795  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_30_WIDTH },
110796  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
110797  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_31_WIDTH },
110798  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
110799  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_32_WIDTH },
110800  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
110801  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_33_WIDTH },
110802  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
110803  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_34_WIDTH },
110804  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
110805  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_35_WIDTH },
110806  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
110807  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_36_WIDTH },
110808  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
110809  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_37_WIDTH },
110810  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
110811  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_38_WIDTH },
110812  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
110813  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_39_WIDTH },
110814  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
110815  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_GROUP_40_WIDTH },
110816 };
110817 
110823 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS] =
110824 {
110825  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
110826  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_0_WIDTH },
110827  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
110828  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_1_WIDTH },
110829  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
110830  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_2_WIDTH },
110831  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
110832  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_3_WIDTH },
110833  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
110834  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_4_WIDTH },
110835  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
110836  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_5_WIDTH },
110837  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
110838  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_6_WIDTH },
110839  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
110840  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_7_WIDTH },
110841  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
110842  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_8_WIDTH },
110843  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
110844  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_9_WIDTH },
110845  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
110846  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_10_WIDTH },
110847  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
110848  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_11_WIDTH },
110849  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
110850  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_12_WIDTH },
110851  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
110852  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_13_WIDTH },
110853  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
110854  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_14_WIDTH },
110855  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
110856  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_15_WIDTH },
110857  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
110858  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_16_WIDTH },
110859  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
110860  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_17_WIDTH },
110861  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
110862  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_18_WIDTH },
110863  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
110864  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_19_WIDTH },
110865  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
110866  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_20_WIDTH },
110867  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
110868  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_21_WIDTH },
110869  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
110870  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_22_WIDTH },
110871  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
110872  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_23_WIDTH },
110873  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
110874  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_24_WIDTH },
110875  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
110876  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_25_WIDTH },
110877  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
110878  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_26_WIDTH },
110879  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
110880  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_27_WIDTH },
110881  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
110882  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_28_WIDTH },
110883  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
110884  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_29_WIDTH },
110885  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
110886  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_30_WIDTH },
110887  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
110888  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_31_WIDTH },
110889  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
110890  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_32_WIDTH },
110891  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
110892  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_33_WIDTH },
110893  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
110894  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_34_WIDTH },
110895  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
110896  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_35_WIDTH },
110897  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
110898  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_36_WIDTH },
110899  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
110900  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_37_WIDTH },
110901  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
110902  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_38_WIDTH },
110903  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
110904  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_39_WIDTH },
110905  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
110906  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_GROUP_40_WIDTH },
110907 };
110908 
110914 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
110915 {
110916  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
110917  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_0_WIDTH },
110918  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
110919  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_1_WIDTH },
110920  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
110921  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_2_WIDTH },
110922  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
110923  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_3_WIDTH },
110924  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
110925  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_4_WIDTH },
110926  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
110927  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_5_WIDTH },
110928  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
110929  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_6_WIDTH },
110930  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
110931  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_7_WIDTH },
110932  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
110933  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_8_WIDTH },
110934  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
110935  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_9_WIDTH },
110936  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
110937  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_10_WIDTH },
110938  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
110939  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_11_WIDTH },
110940  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
110941  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_12_WIDTH },
110942  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
110943  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_13_WIDTH },
110944  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
110945  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_GROUP_14_WIDTH },
110946 };
110947 
110953 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS] =
110954 {
110955  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_0_CHECKER_TYPE,
110956  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_0_WIDTH },
110957  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_1_CHECKER_TYPE,
110958  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_1_WIDTH },
110959  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_2_CHECKER_TYPE,
110960  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_2_WIDTH },
110961  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_3_CHECKER_TYPE,
110962  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_GROUP_3_WIDTH },
110963 };
110964 
110970 static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
110971 {
110972  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
110973  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
110974  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
110975  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
110976  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
110977  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
110978  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
110979  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
110980  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
110981  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
110982  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
110983  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
110984 };
110985 
110991 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS] =
110992 {
110993  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_CHECKER_TYPE,
110994  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_0_WIDTH },
110995  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_CHECKER_TYPE,
110996  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_1_WIDTH },
110997  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_CHECKER_TYPE,
110998  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_2_WIDTH },
110999  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_CHECKER_TYPE,
111000  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_3_WIDTH },
111001  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_CHECKER_TYPE,
111002  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_4_WIDTH },
111003  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_CHECKER_TYPE,
111004  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_GROUP_5_WIDTH },
111005 };
111006 
111012 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
111013 {
111014  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
111015  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
111016  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
111017  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
111018  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
111019  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
111020 };
111021 
111027 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
111028 {
111029  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
111030  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
111031  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
111032  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
111033  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
111034  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
111035  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
111036  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
111037  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
111038  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
111039  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
111040  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
111041  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
111042  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
111043  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
111044  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
111045  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
111046  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
111047  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
111048  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
111049  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
111050  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
111051  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
111052  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
111053  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
111054  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
111055  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
111056  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
111057  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
111058  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
111059  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
111060  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
111061  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
111062  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
111063  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
111064  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
111065  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
111066  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
111067  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
111068  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
111069  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
111070  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
111071  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
111072  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
111073  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
111074  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
111075  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
111076  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
111077  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
111078  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
111079  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
111080  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
111081  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
111082  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
111083  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
111084  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
111085  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
111086  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
111087  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
111088  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
111089  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
111090  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
111091  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
111092  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
111093  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
111094  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
111095  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
111096  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
111097  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
111098  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
111099  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
111100  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
111101  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
111102  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
111103  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
111104  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
111105  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
111106  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
111107  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
111108  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
111109  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
111110  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
111111  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
111112  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
111113  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
111114  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
111115  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
111116  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
111117  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
111118  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
111119  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
111120  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
111121  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
111122  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
111123  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
111124  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
111125  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
111126  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
111127  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
111128  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
111129  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
111130  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
111131  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
111132  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
111133  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
111134  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
111135  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
111136  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
111137  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
111138  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
111139  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
111140  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
111141  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
111142  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
111143  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
111144  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
111145  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
111146  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
111147  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
111148  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
111149  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
111150  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
111151  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
111152  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
111153  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
111154  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
111155  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
111156  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
111157  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
111158  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
111159  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
111160  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
111161  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
111162  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
111163  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
111164  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
111165  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
111166  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
111167  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
111168  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
111169  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
111170  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
111171  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
111172  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
111173  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
111174  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
111175  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
111176  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
111177  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
111178  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
111179  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
111180  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
111181  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
111182  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
111183  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
111184  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
111185  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
111186  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
111187  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
111188  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
111189  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
111190  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
111191  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
111192  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
111193  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
111194  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
111195 };
111196 
111202 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
111203 {
111204  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
111205  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_0_WIDTH },
111206  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
111207  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_1_WIDTH },
111208  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
111209  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_2_WIDTH },
111210  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
111211  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_3_WIDTH },
111212  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
111213  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_4_WIDTH },
111214  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
111215  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_5_WIDTH },
111216  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
111217  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_6_WIDTH },
111218  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
111219  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_7_WIDTH },
111220  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
111221  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_8_WIDTH },
111222  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
111223  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_9_WIDTH },
111224  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
111225  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_10_WIDTH },
111226  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
111227  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_11_WIDTH },
111228  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
111229  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_GROUP_12_WIDTH },
111230 };
111231 
111237 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_MAX_NUM_CHECKERS] =
111238 {
111239  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_0_CHECKER_TYPE,
111240  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_0_WIDTH },
111241  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_1_CHECKER_TYPE,
111242  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_GROUP_1_WIDTH },
111243 };
111244 
111250 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_MAX_NUM_CHECKERS] =
111251 {
111252  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_0_CHECKER_TYPE,
111253  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_0_WIDTH },
111254  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_1_CHECKER_TYPE,
111255  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_1_WIDTH },
111256  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_2_CHECKER_TYPE,
111257  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_GROUP_2_WIDTH },
111258 };
111259 
111265 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_MAX_NUM_CHECKERS] =
111266 {
111267  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_0_CHECKER_TYPE,
111268  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_0_WIDTH },
111269  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_1_CHECKER_TYPE,
111270  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_GROUP_1_WIDTH },
111271 };
111272 
111278 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_MAX_NUM_CHECKERS] =
111279 {
111280  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_0_CHECKER_TYPE,
111281  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_0_WIDTH },
111282  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_1_CHECKER_TYPE,
111283  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_1_WIDTH },
111284  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_2_CHECKER_TYPE,
111285  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_GROUP_2_WIDTH },
111286 };
111287 
111293 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_MAX_NUM_CHECKERS] =
111294 {
111295  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_0_CHECKER_TYPE,
111296  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_0_WIDTH },
111297  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_1_CHECKER_TYPE,
111298  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_GROUP_1_WIDTH },
111299 };
111300 
111306 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_MAX_NUM_CHECKERS] =
111307 {
111308  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_0_CHECKER_TYPE,
111309  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_0_WIDTH },
111310  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_1_CHECKER_TYPE,
111311  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_1_WIDTH },
111312  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_2_CHECKER_TYPE,
111313  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_GROUP_2_WIDTH },
111314 };
111315 
111321 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_MAX_NUM_CHECKERS] =
111322 {
111323  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_0_CHECKER_TYPE,
111324  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_0_WIDTH },
111325  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_1_CHECKER_TYPE,
111326  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_GROUP_1_WIDTH },
111327 };
111328 
111334 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_MAX_NUM_CHECKERS] =
111335 {
111336  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_0_CHECKER_TYPE,
111337  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_0_WIDTH },
111338  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_1_CHECKER_TYPE,
111339  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_1_WIDTH },
111340  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_2_CHECKER_TYPE,
111341  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_GROUP_2_WIDTH },
111342 };
111343 
111349 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_MAX_NUM_CHECKERS] =
111350 {
111351  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_0_CHECKER_TYPE,
111352  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_0_WIDTH },
111353  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_1_CHECKER_TYPE,
111354  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_1_WIDTH },
111355  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_2_CHECKER_TYPE,
111356  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_2_WIDTH },
111357  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_3_CHECKER_TYPE,
111358  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_3_WIDTH },
111359  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_4_CHECKER_TYPE,
111360  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_4_WIDTH },
111361  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_5_CHECKER_TYPE,
111362  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_5_WIDTH },
111363  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_6_CHECKER_TYPE,
111364  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_6_WIDTH },
111365  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_7_CHECKER_TYPE,
111366  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_7_WIDTH },
111367  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_8_CHECKER_TYPE,
111368  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_8_WIDTH },
111369  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_9_CHECKER_TYPE,
111370  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_9_WIDTH },
111371  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_10_CHECKER_TYPE,
111372  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_10_WIDTH },
111373  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_11_CHECKER_TYPE,
111374  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_11_WIDTH },
111375  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_12_CHECKER_TYPE,
111376  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_12_WIDTH },
111377  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_13_CHECKER_TYPE,
111378  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_13_WIDTH },
111379  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_14_CHECKER_TYPE,
111380  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_14_WIDTH },
111381  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_15_CHECKER_TYPE,
111382  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_15_WIDTH },
111383  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_16_CHECKER_TYPE,
111384  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_16_WIDTH },
111385  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_17_CHECKER_TYPE,
111386  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_17_WIDTH },
111387  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_18_CHECKER_TYPE,
111388  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_18_WIDTH },
111389  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_19_CHECKER_TYPE,
111390  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_19_WIDTH },
111391  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_20_CHECKER_TYPE,
111392  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_20_WIDTH },
111393  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_21_CHECKER_TYPE,
111394  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_21_WIDTH },
111395  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_22_CHECKER_TYPE,
111396  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_22_WIDTH },
111397  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_23_CHECKER_TYPE,
111398  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_23_WIDTH },
111399  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_24_CHECKER_TYPE,
111400  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_24_WIDTH },
111401  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_25_CHECKER_TYPE,
111402  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_25_WIDTH },
111403  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_26_CHECKER_TYPE,
111404  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_26_WIDTH },
111405  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_27_CHECKER_TYPE,
111406  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_27_WIDTH },
111407  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_28_CHECKER_TYPE,
111408  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_28_WIDTH },
111409  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_29_CHECKER_TYPE,
111410  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_29_WIDTH },
111411  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_30_CHECKER_TYPE,
111412  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_30_WIDTH },
111413  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_31_CHECKER_TYPE,
111414  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_31_WIDTH },
111415  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_32_CHECKER_TYPE,
111416  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_32_WIDTH },
111417  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_33_CHECKER_TYPE,
111418  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_33_WIDTH },
111419  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_34_CHECKER_TYPE,
111420  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_34_WIDTH },
111421  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_35_CHECKER_TYPE,
111422  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_35_WIDTH },
111423  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_36_CHECKER_TYPE,
111424  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_36_WIDTH },
111425  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_37_CHECKER_TYPE,
111426  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_37_WIDTH },
111427  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_38_CHECKER_TYPE,
111428  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_38_WIDTH },
111429  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_39_CHECKER_TYPE,
111430  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_39_WIDTH },
111431  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_40_CHECKER_TYPE,
111432  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_40_WIDTH },
111433  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_41_CHECKER_TYPE,
111434  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_41_WIDTH },
111435  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_42_CHECKER_TYPE,
111436  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_42_WIDTH },
111437  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_43_CHECKER_TYPE,
111438  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_43_WIDTH },
111439  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_44_CHECKER_TYPE,
111440  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_44_WIDTH },
111441  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_45_CHECKER_TYPE,
111442  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_45_WIDTH },
111443  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_46_CHECKER_TYPE,
111444  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_46_WIDTH },
111445  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_47_CHECKER_TYPE,
111446  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_47_WIDTH },
111447  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_48_CHECKER_TYPE,
111448  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_48_WIDTH },
111449  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_49_CHECKER_TYPE,
111450  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_49_WIDTH },
111451  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_50_CHECKER_TYPE,
111452  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_50_WIDTH },
111453  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_51_CHECKER_TYPE,
111454  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_51_WIDTH },
111455  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_52_CHECKER_TYPE,
111456  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_52_WIDTH },
111457  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_53_CHECKER_TYPE,
111458  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_53_WIDTH },
111459  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_54_CHECKER_TYPE,
111460  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_54_WIDTH },
111461  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_55_CHECKER_TYPE,
111462  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_55_WIDTH },
111463  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_56_CHECKER_TYPE,
111464  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_56_WIDTH },
111465  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_57_CHECKER_TYPE,
111466  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_57_WIDTH },
111467  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_58_CHECKER_TYPE,
111468  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_58_WIDTH },
111469  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_59_CHECKER_TYPE,
111470  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_59_WIDTH },
111471  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_60_CHECKER_TYPE,
111472  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_60_WIDTH },
111473  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_61_CHECKER_TYPE,
111474  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_61_WIDTH },
111475  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_62_CHECKER_TYPE,
111476  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_62_WIDTH },
111477  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_63_CHECKER_TYPE,
111478  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_63_WIDTH },
111479  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_64_CHECKER_TYPE,
111480  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_64_WIDTH },
111481  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_65_CHECKER_TYPE,
111482  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_65_WIDTH },
111483  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_66_CHECKER_TYPE,
111484  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_66_WIDTH },
111485  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_67_CHECKER_TYPE,
111486  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_67_WIDTH },
111487  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_68_CHECKER_TYPE,
111488  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_68_WIDTH },
111489  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_69_CHECKER_TYPE,
111490  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_69_WIDTH },
111491  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_70_CHECKER_TYPE,
111492  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_70_WIDTH },
111493  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_71_CHECKER_TYPE,
111494  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_71_WIDTH },
111495  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_72_CHECKER_TYPE,
111496  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_72_WIDTH },
111497  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_73_CHECKER_TYPE,
111498  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_73_WIDTH },
111499  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_74_CHECKER_TYPE,
111500  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_74_WIDTH },
111501  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_75_CHECKER_TYPE,
111502  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_75_WIDTH },
111503  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_76_CHECKER_TYPE,
111504  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_76_WIDTH },
111505  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_77_CHECKER_TYPE,
111506  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_77_WIDTH },
111507  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_78_CHECKER_TYPE,
111508  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_78_WIDTH },
111509  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_79_CHECKER_TYPE,
111510  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_79_WIDTH },
111511  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_80_CHECKER_TYPE,
111512  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_80_WIDTH },
111513  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_81_CHECKER_TYPE,
111514  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_81_WIDTH },
111515  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_82_CHECKER_TYPE,
111516  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_82_WIDTH },
111517  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_83_CHECKER_TYPE,
111518  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_83_WIDTH },
111519  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_84_CHECKER_TYPE,
111520  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_84_WIDTH },
111521  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_85_CHECKER_TYPE,
111522  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_85_WIDTH },
111523  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_86_CHECKER_TYPE,
111524  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_86_WIDTH },
111525  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_87_CHECKER_TYPE,
111526  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_87_WIDTH },
111527  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_88_CHECKER_TYPE,
111528  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_88_WIDTH },
111529  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_89_CHECKER_TYPE,
111530  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_89_WIDTH },
111531  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_90_CHECKER_TYPE,
111532  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_90_WIDTH },
111533  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_91_CHECKER_TYPE,
111534  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_91_WIDTH },
111535  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_92_CHECKER_TYPE,
111536  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_92_WIDTH },
111537  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_93_CHECKER_TYPE,
111538  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_93_WIDTH },
111539  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_94_CHECKER_TYPE,
111540  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_94_WIDTH },
111541  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_95_CHECKER_TYPE,
111542  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_95_WIDTH },
111543  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_96_CHECKER_TYPE,
111544  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_96_WIDTH },
111545  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_97_CHECKER_TYPE,
111546  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_97_WIDTH },
111547  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_98_CHECKER_TYPE,
111548  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_98_WIDTH },
111549  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_99_CHECKER_TYPE,
111550  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_GROUP_99_WIDTH },
111551 };
111552 
111558 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_MAX_NUM_CHECKERS] =
111559 {
111560  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_0_CHECKER_TYPE,
111561  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_0_WIDTH },
111562  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_1_CHECKER_TYPE,
111563  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_GROUP_1_WIDTH },
111564 };
111565 
111571 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_MAX_NUM_CHECKERS] =
111572 {
111573  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_0_CHECKER_TYPE,
111574  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_0_WIDTH },
111575  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_1_CHECKER_TYPE,
111576  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_1_WIDTH },
111577  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_2_CHECKER_TYPE,
111578  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_2_WIDTH },
111579  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_3_CHECKER_TYPE,
111580  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_GROUP_3_WIDTH },
111581 };
111582 
111588 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_MAX_NUM_CHECKERS] =
111589 {
111590  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_0_CHECKER_TYPE,
111591  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_0_WIDTH },
111592  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_1_CHECKER_TYPE,
111593  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_1_WIDTH },
111594  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_2_CHECKER_TYPE,
111595  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_2_WIDTH },
111596  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_3_CHECKER_TYPE,
111597  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_GROUP_3_WIDTH },
111598 };
111599 
111605 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_MAX_NUM_CHECKERS] =
111606 {
111607  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_0_CHECKER_TYPE,
111608  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_0_WIDTH },
111609  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_1_CHECKER_TYPE,
111610  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_1_WIDTH },
111611  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_2_CHECKER_TYPE,
111612  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_2_WIDTH },
111613  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_3_CHECKER_TYPE,
111614  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_GROUP_3_WIDTH },
111615 };
111616 
111621 static const SDL_MemConfig_t SDL_DMPAC0_ECC_AGGR_MemEntries[SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
111622 {
111623  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID, 0u,
111624  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_SIZE, 4u,
111625  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_ROW_WIDTH, ((bool)false) },
111626  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID, 0u,
111627  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_SIZE, 4u,
111628  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_ROW_WIDTH, ((bool)false) },
111629  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_ID, 0u,
111630  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_SIZE, 4u,
111631  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_ROW_WIDTH, ((bool)false) },
111632  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID, 0u,
111633  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_SIZE, 4u,
111634  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_ROW_WIDTH, ((bool)false) },
111635  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID, 0u,
111636  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_SIZE, 4u,
111637  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_ROW_WIDTH, ((bool)false) },
111638 };
111639 
111645 static const SDL_GrpChkConfig_t SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
111646 {
111647  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
111648  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
111649  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
111650  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
111651  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
111652  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
111653  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
111654  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
111655  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
111656  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_4_WIDTH },
111657  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
111658  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_5_WIDTH },
111659  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
111660  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_6_WIDTH },
111661  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
111662  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_7_WIDTH },
111663  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
111664  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_8_WIDTH },
111665  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
111666  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_9_WIDTH },
111667  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
111668  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_10_WIDTH },
111669  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
111670  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_11_WIDTH },
111671  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
111672  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_12_WIDTH },
111673  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
111674  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_13_WIDTH },
111675  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
111676  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_14_WIDTH },
111677  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
111678  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_15_WIDTH },
111679  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
111680  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_16_WIDTH },
111681  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
111682  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_17_WIDTH },
111683  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
111684  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_18_WIDTH },
111685  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
111686  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_19_WIDTH },
111687  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
111688  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_20_WIDTH },
111689  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
111690  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_21_WIDTH },
111691  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
111692  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_22_WIDTH },
111693  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
111694  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_23_WIDTH },
111695  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
111696  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_24_WIDTH },
111697  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
111698  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_25_WIDTH },
111699  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
111700  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_26_WIDTH },
111701  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
111702  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_27_WIDTH },
111703  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
111704  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_28_WIDTH },
111705  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
111706  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_29_WIDTH },
111707  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
111708  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_30_WIDTH },
111709  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
111710  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_31_WIDTH },
111711  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
111712  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_32_WIDTH },
111713  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
111714  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_33_WIDTH },
111715  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
111716  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_34_WIDTH },
111717  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
111718  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_35_WIDTH },
111719  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
111720  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_36_WIDTH },
111721  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
111722  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_37_WIDTH },
111723  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
111724  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_38_WIDTH },
111725  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
111726  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_39_WIDTH },
111727  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
111728  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_40_WIDTH },
111729  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
111730  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_41_WIDTH },
111731  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
111732  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_42_WIDTH },
111733  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
111734  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_43_WIDTH },
111735  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
111736  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_GROUP_44_WIDTH },
111737 };
111738 
111744 static const SDL_GrpChkConfig_t SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
111745 {
111746  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
111747  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
111748  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
111749  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
111750  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
111751  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
111752  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
111753  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
111754  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
111755  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_WIDTH },
111756  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
111757  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_WIDTH },
111758  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
111759  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_WIDTH },
111760  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
111761  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_WIDTH },
111762  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
111763  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_WIDTH },
111764  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
111765  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_WIDTH },
111766  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
111767  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_WIDTH },
111768  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
111769  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_WIDTH },
111770  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
111771  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_WIDTH },
111772  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
111773  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_WIDTH },
111774  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
111775  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_WIDTH },
111776  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
111777  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_WIDTH },
111778  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
111779  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_WIDTH },
111780  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
111781  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_WIDTH },
111782  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
111783  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_WIDTH },
111784  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
111785  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_WIDTH },
111786  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
111787  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_WIDTH },
111788  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
111789  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_WIDTH },
111790  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
111791  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_WIDTH },
111792  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
111793  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_WIDTH },
111794  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
111795  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_WIDTH },
111796  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
111797  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_WIDTH },
111798  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
111799  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_WIDTH },
111800  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
111801  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_WIDTH },
111802  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
111803  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_WIDTH },
111804  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
111805  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_WIDTH },
111806  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
111807  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_WIDTH },
111808 };
111809 
111815 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
111816 {
111817  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
111818  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
111819  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
111820  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
111821  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
111822  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
111823  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
111824  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
111825  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
111826  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
111827  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
111828  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
111829  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
111830  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
111831  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
111832  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
111833  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
111834  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
111835  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
111836  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
111837  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
111838  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
111839  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
111840  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
111841  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
111842  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
111843  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
111844  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
111845  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
111846  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
111847  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
111848  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
111849  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
111850  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
111851  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
111852  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
111853  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
111854  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
111855  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
111856  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
111857  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
111858  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
111859  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
111860  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
111861  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
111862  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
111863  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
111864  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
111865  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
111866  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
111867  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
111868  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
111869  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
111870  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
111871  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
111872  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
111873  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
111874  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
111875  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
111876  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
111877  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
111878  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
111879  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
111880  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
111881  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
111882  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
111883  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
111884  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
111885  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
111886  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
111887  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
111888  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
111889  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
111890  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
111891  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
111892  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
111893  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
111894  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
111895  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
111896  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
111897  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
111898  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
111899 };
111900 
111906 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
111907 {
111908  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
111909  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
111910  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
111911  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
111912  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
111913  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
111914  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
111915  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
111916  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
111917  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
111918  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
111919  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
111920  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
111921  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
111922  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
111923  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
111924  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
111925  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
111926  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
111927  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
111928  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
111929  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
111930  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
111931  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
111932  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
111933  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
111934  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
111935  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
111936  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
111937  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
111938  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
111939  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
111940  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
111941  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
111942  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
111943  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
111944  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
111945  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
111946  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
111947  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
111948  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
111949  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
111950  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
111951  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
111952  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
111953  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
111954  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
111955  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
111956  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
111957  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
111958  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
111959  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
111960  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
111961  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
111962  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
111963  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
111964  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
111965  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
111966  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
111967  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
111968  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
111969  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
111970  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
111971  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
111972  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
111973  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
111974  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
111975  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
111976  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
111977  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
111978  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
111979  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
111980  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
111981  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
111982  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
111983  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
111984  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
111985  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
111986  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
111987  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
111988  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
111989  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
111990 };
111991 
111997 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
111998 {
111999  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
112000  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
112001  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
112002  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
112003  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
112004  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
112005  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
112006  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
112007  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
112008  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
112009  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
112010  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
112011  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
112012  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
112013  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
112014  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
112015  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
112016  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
112017  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
112018  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
112019  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
112020  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
112021  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
112022  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
112023  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
112024  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
112025  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
112026  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
112027  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
112028  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
112029  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
112030  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
112031  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
112032  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
112033  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
112034  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
112035 };
112036 
112042 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
112043 {
112044  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
112045  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
112046  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
112047  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
112048  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
112049  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
112050  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
112051  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
112052  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
112053  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
112054  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
112055  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
112056  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
112057  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
112058  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
112059  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
112060  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
112061  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
112062  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
112063  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
112064  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
112065  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
112066  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
112067  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
112068  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
112069  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
112070  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
112071  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
112072  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
112073  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
112074  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
112075  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
112076  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
112077  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
112078  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
112079  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
112080  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
112081  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
112082  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
112083  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
112084  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
112085  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
112086  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
112087  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
112088  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
112089  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
112090 };
112091 
112097 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
112098 {
112099  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
112100  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
112101  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
112102  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
112103  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
112104  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
112105  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
112106  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
112107  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
112108  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
112109  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
112110  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
112111  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
112112  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
112113  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
112114  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
112115  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
112116  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
112117  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
112118  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
112119  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
112120  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
112121  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
112122  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
112123  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
112124  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
112125  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
112126  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
112127  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
112128  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
112129  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
112130  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
112131  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
112132  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
112133  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
112134  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
112135 };
112136 
112142 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
112143 {
112144  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
112145  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
112146  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
112147  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
112148  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
112149  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
112150  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
112151  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
112152  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
112153  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
112154  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
112155  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
112156  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
112157  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
112158  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
112159  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
112160  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
112161  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
112162  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
112163  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
112164  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
112165  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
112166  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
112167  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
112168  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
112169  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
112170  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
112171  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
112172  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
112173  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
112174  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
112175  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
112176  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
112177  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
112178  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
112179  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
112180  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
112181  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
112182  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
112183  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
112184  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
112185  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
112186  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
112187  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
112188  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
112189  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
112190 };
112191 
112197 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
112198 {
112199  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
112200  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
112201  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
112202  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
112203  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
112204  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
112205  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
112206  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
112207  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
112208  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
112209  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
112210  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
112211  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
112212  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
112213  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
112214  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
112215  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
112216  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
112217  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
112218  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
112219  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
112220  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
112221  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
112222  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
112223  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
112224  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
112225  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
112226  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
112227  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
112228  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
112229  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
112230  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
112231  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
112232  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
112233  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
112234  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
112235  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
112236  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
112237  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
112238  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
112239  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
112240  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
112241  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
112242  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
112243  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
112244  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
112245  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
112246  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
112247  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
112248  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
112249  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
112250  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
112251  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
112252  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
112253  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
112254  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
112255  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
112256  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
112257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
112258  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
112259  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
112260  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
112261  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
112262  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
112263  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
112264  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
112265  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
112266  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
112267  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
112268  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
112269  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
112270  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
112271  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
112272  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
112273  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
112274  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
112275  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
112276  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
112277  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
112278  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
112279  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
112280  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
112281 };
112282 
112288 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
112289 {
112290  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
112291  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
112292  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
112293  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
112294  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
112295  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
112296  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
112297  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
112298  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
112299  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
112300  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
112301  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
112302  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
112303  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
112304  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
112305  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
112306  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
112307  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
112308  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
112309  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
112310  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
112311  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
112312  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
112313  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
112314  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
112315  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
112316  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
112317  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
112318  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
112319  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
112320  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
112321  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
112322  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
112323  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
112324  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
112325  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
112326  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
112327  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
112328  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
112329  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
112330  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
112331  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
112332  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
112333  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
112334  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
112335  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
112336  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
112337  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
112338  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
112339  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
112340  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
112341  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
112342  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
112343  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
112344  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
112345  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
112346  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
112347  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
112348  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
112349  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
112350  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
112351  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
112352  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
112353  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
112354  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
112355  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
112356  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
112357  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
112358  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
112359  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
112360  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
112361  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
112362  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
112363  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
112364  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
112365  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
112366  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
112367  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
112368  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
112369  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
112370  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
112371  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
112372 };
112373 
112379 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
112380 {
112381  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
112382  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
112383  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
112384  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
112385  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
112386  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
112387  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
112388  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
112389  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
112390  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
112391  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
112392  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
112393  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
112394  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
112395  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
112396  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
112397  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
112398  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
112399  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
112400  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
112401  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
112402  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
112403  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
112404  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
112405  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
112406  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
112407  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
112408  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
112409  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
112410  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
112411  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
112412  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
112413  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
112414  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
112415  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
112416  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
112417  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
112418  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
112419  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
112420  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
112421  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
112422  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
112423  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
112424  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
112425  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
112426  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
112427  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
112428  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
112429  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
112430  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
112431  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
112432  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
112433  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
112434  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
112435  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
112436  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
112437  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
112438  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
112439  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
112440  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
112441  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
112442  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
112443  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
112444  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
112445  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
112446  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
112447  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
112448  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
112449  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
112450  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
112451  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
112452  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
112453  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
112454  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
112455  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
112456  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
112457  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
112458  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
112459  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
112460  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
112461  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
112462  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
112463  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
112464  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
112465  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
112466  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
112467  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
112468  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
112469  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
112470  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
112471  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
112472  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
112473  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
112474  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
112475  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
112476  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
112477  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
112478  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
112479  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
112480  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
112481  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
112482  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
112483  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
112484  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
112485  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
112486  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
112487  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
112488  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
112489  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
112490  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
112491  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
112492  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
112493  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
112494  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
112495  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
112496  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
112497  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
112498  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
112499  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
112500  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
112501  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
112502  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
112503  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
112504  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
112505  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
112506  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
112507  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
112508  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
112509  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
112510  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
112511  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
112512  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
112513  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
112514  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
112515  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
112516  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
112517  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
112518  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
112519  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
112520  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
112521  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
112522  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
112523  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
112524  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
112525  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
112526  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
112527  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
112528  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
112529  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
112530  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
112531  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
112532  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
112533  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
112534  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
112535  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
112536  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
112537  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
112538  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
112539  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
112540  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
112541  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
112542  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
112543  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
112544  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
112545  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
112546  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
112547  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
112548  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
112549  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
112550  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
112551  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
112552  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
112553  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
112554  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
112555  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
112556  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
112557  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
112558  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
112559  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
112560  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
112561  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
112562  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
112563  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
112564  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
112565  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
112566  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
112567  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
112568  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
112569  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
112570  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
112571  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
112572  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
112573  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
112574  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
112575  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
112576  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
112577  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
112578  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
112579  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
112580  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
112581  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
112582  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
112583  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
112584  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
112585  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
112586  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
112587  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
112588  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
112589  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
112590  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
112591  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
112592  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
112593  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
112594  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
112595  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
112596  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
112597  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
112598  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
112599  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
112600  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
112601  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
112602  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
112603  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
112604  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
112605  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
112606  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
112607  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
112608  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
112609  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
112610  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
112611  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
112612  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
112613  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
112614  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
112615  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
112616  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
112617  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
112618  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
112619  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
112620  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
112621  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
112622  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
112623  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
112624  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
112625  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
112626  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
112627  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
112628  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
112629  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
112630  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
112631  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
112632  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
112633  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
112634  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
112635  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
112636  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
112637  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
112638  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
112639  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
112640  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
112641  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
112642  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
112643  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
112644  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
112645  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
112646  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
112647  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
112648  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
112649  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
112650  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
112651  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
112652  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
112653  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
112654  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
112655  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
112656  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
112657  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
112658  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
112659  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
112660  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
112661  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
112662  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
112663  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
112664  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
112665  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
112666  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
112667  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
112668  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
112669  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
112670  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
112671  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
112672  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
112673  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
112674  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
112675  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
112676  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
112677  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
112678  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
112679  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
112680  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
112681  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
112682  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
112683  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
112684  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
112685  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
112686  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
112687  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
112688  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
112689  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
112690  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
112691  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
112692  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
112693  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
112694  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
112695  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
112696  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
112697  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
112698  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
112699  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
112700  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
112701  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
112702  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
112703  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
112704  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
112705  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
112706  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
112707  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
112708  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
112709  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
112710  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
112711  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
112712  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
112713  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
112714  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
112715  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
112716  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
112717  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
112718  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
112719  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
112720  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
112721  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
112722  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
112723  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
112724  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
112725  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
112726  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
112727  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
112728  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
112729  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
112730  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
112731  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
112732  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
112733  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
112734  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
112735  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
112736  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
112737  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
112738  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
112739  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
112740  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
112741  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
112742  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
112743  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
112744  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
112745  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
112746  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
112747  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
112748  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
112749  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
112750  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
112751  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
112752  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
112753  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
112754  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
112755  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
112756  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
112757  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
112758  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
112759  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
112760  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
112761  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
112762  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
112763  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
112764  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
112765  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
112766  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
112767  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
112768  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
112769  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
112770  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
112771  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
112772  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
112773  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
112774  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
112775  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
112776  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
112777  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
112778  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
112779  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
112780  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
112781  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
112782  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
112783  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
112784  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
112785  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
112786  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
112787  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
112788  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
112789  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
112790  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
112791  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
112792  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
112793  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
112794  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
112795  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
112796  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
112797  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
112798  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
112799  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
112800  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
112801  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
112802  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
112803  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
112804  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
112805  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
112806  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
112807  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
112808  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
112809  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
112810  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
112811  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
112812  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
112813  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
112814  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
112815  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
112816  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
112817  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
112818  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
112819  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
112820  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
112821  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
112822  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
112823  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
112824  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
112825  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
112826  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
112827  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
112828  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
112829  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
112830  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
112831  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
112832  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
112833  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
112834  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
112835  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
112836  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
112837  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
112838  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
112839  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
112840  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
112841  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
112842  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
112843  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
112844  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
112845  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
112846  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
112847  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
112848  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
112849  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
112850  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
112851  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
112852  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
112853  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
112854  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
112855  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
112856  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
112857  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
112858  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
112859  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
112860  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
112861  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
112862  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
112863  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
112864  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
112865  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
112866  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
112867  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
112868  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
112869  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
112870  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
112871  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
112872  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
112873  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
112874  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
112875  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
112876  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
112877  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
112878  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
112879  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
112880  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
112881  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
112882  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
112883  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
112884  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
112885  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
112886  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
112887  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
112888  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
112889  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
112890  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
112891  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
112892  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
112893 };
112894 
112900 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
112901 {
112902  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
112903  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
112904  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
112905  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
112906  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
112907  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
112908  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
112909  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
112910  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
112911  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
112912  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
112913  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
112914  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
112915  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
112916  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
112917  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
112918  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
112919  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
112920  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
112921  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
112922  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
112923  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
112924  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
112925  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
112926  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
112927  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
112928  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
112929  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
112930  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
112931  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
112932  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
112933  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
112934  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
112935  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
112936  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
112937  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
112938  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
112939  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
112940  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
112941  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
112942  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
112943  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
112944  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
112945  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
112946  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
112947  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
112948  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
112949  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
112950  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
112951  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
112952  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
112953  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
112954  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
112955  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
112956  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
112957  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
112958  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
112959  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
112960  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
112961  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
112962  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
112963  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
112964  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
112965  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
112966  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
112967  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
112968  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
112969  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
112970  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
112971  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
112972  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
112973  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
112974  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
112975  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
112976  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
112977  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
112978  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
112979  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
112980  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
112981  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
112982  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
112983  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
112984  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
112985  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
112986  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
112987  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
112988  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
112989  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
112990  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
112991  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
112992  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
112993  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
112994  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
112995  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
112996  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
112997  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
112998  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
112999  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
113000  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
113001  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
113002  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
113003  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
113004  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
113005  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
113006  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
113007  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
113008  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
113009  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
113010  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
113011  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
113012  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
113013  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
113014  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
113015  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
113016  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
113017  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
113018  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
113019  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
113020  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
113021  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
113022  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
113023  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
113024  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
113025  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
113026  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
113027  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
113028  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
113029  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
113030  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
113031  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
113032  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
113033  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
113034  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
113035  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
113036  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
113037  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
113038  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
113039  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
113040  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
113041  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
113042  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
113043  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
113044  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
113045  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
113046  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
113047  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
113048  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
113049  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
113050  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
113051  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
113052  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
113053  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
113054  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
113055  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
113056  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
113057  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
113058  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
113059  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
113060  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
113061  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
113062  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
113063  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
113064  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
113065  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
113066  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
113067  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
113068  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
113069  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
113070  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
113071  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
113072  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
113073  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
113074  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
113075  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
113076  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
113077  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
113078  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
113079  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
113080  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
113081  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
113082  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
113083  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
113084  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
113085  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
113086  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
113087  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
113088  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
113089  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
113090  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
113091  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
113092  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
113093  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
113094  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
113095  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
113096  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
113097  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
113098  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
113099  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
113100  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
113101  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
113102  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
113103  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
113104  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
113105  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
113106  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
113107  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
113108  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
113109  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
113110  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
113111  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
113112  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
113113  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
113114  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
113115  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
113116  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
113117  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
113118  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
113119  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
113120  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
113121  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
113122  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
113123  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
113124  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
113125  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
113126  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
113127  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
113128  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
113129  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
113130  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
113131  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
113132  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
113133  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
113134  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
113135  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
113136  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
113137  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
113138  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
113139  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
113140  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
113141  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
113142  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
113143  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
113144  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
113145  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
113146  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
113147  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
113148  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
113149  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
113150  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
113151  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
113152  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
113153  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
113154  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
113155  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
113156  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
113157  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
113158  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
113159  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
113160  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
113161  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
113162  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
113163  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
113164  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
113165  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
113166  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
113167  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
113168  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
113169  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
113170  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
113171  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
113172  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
113173  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
113174  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
113175  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
113176  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
113177  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
113178  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
113179  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
113180  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
113181  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
113182  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
113183  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
113184  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
113185  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
113186  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
113187  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
113188  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
113189  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
113190  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
113191  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
113192  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
113193  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
113194  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
113195  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
113196  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
113197  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
113198  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
113199  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
113200  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
113201  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
113202  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
113203  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
113204  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
113205  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
113206  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
113207  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
113208  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
113209  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
113210  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
113211  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
113212  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
113213  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
113214  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
113215  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
113216  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
113217  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
113218  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
113219  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
113220  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
113221  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
113222  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
113223  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
113224  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
113225  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
113226  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
113227  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
113228  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
113229  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
113230  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
113231  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
113232  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
113233  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
113234  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
113235  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
113236  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
113237  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
113238  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
113239  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
113240  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
113241  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
113242  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
113243  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
113244  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
113245  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
113246  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
113247  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
113248  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
113249  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
113250  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
113251  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
113252  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
113253  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
113254  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
113255  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
113256  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
113257  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
113258  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
113259  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
113260  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
113261  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
113262  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
113263  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
113264  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
113265  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
113266  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
113267  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
113268  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
113269  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
113270  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
113271  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
113272  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
113273  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
113274  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
113275  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
113276  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
113277  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
113278  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
113279  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
113280  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
113281  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
113282  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
113283  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
113284  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
113285  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
113286  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
113287  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
113288  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
113289  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
113290  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
113291  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
113292  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
113293  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
113294  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
113295  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
113296  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
113297  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
113298  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
113299  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
113300  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
113301  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
113302  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
113303  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
113304  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
113305  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
113306  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
113307  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
113308  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
113309  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
113310  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
113311  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
113312  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
113313  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
113314  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
113315  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
113316  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
113317  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
113318  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
113319  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
113320  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
113321  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
113322  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
113323  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
113324  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
113325  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
113326  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
113327  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
113328  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
113329  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
113330  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
113331  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
113332  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
113333  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
113334  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
113335  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
113336  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
113337  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
113338  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
113339  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
113340  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
113341  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
113342  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
113343  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
113344  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
113345  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
113346  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
113347  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
113348  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
113349  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
113350  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
113351  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
113352  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
113353  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
113354  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
113355  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
113356  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
113357  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
113358  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
113359  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
113360  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
113361  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
113362  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
113363  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
113364  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
113365  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
113366  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
113367  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
113368  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
113369  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
113370  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
113371  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
113372  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
113373  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
113374  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
113375  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
113376  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
113377  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
113378  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
113379  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
113380  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
113381  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
113382  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
113383  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
113384  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
113385  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
113386  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
113387  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
113388  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
113389  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
113390  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
113391  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
113392  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
113393  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
113394  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
113395  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
113396  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
113397  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
113398  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
113399  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
113400  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
113401  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
113402  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
113403  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
113404  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
113405  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
113406  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
113407  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
113408  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
113409  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
113410  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
113411  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
113412  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
113413  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
113414 };
113415 
113421 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
113422 {
113423  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
113424  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
113425  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
113426  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
113427  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
113428  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
113429  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
113430  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
113431  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
113432  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
113433  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
113434  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
113435  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
113436  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
113437  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
113438  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
113439  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
113440  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
113441  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
113442  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
113443  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
113444  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
113445  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
113446  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
113447  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
113448  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
113449  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
113450  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
113451  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
113452  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
113453  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
113454  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
113455  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
113456  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
113457  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
113458  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
113459  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
113460  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
113461  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
113462  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
113463  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
113464  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
113465  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
113466  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
113467  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
113468  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
113469  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
113470  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
113471  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
113472  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
113473  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
113474  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
113475  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
113476  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
113477  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
113478  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
113479  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
113480  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
113481  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
113482  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
113483  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
113484  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
113485  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
113486  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
113487  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
113488  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
113489  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
113490  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
113491  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
113492  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
113493  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
113494  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
113495  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
113496  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
113497  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
113498  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
113499  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
113500  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
113501  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
113502  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
113503  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
113504  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
113505  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
113506  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
113507  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
113508  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
113509  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
113510  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
113511  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
113512  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
113513  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
113514  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
113515  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
113516  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
113517  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
113518  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
113519  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
113520  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
113521  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
113522  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
113523  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
113524  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
113525  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
113526  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
113527  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
113528  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
113529  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
113530  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
113531  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
113532  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
113533  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
113534  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
113535  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
113536  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
113537  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
113538  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
113539  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
113540  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
113541  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
113542  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
113543  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
113544  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
113545  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
113546  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
113547  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
113548  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
113549  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
113550  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
113551  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
113552  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
113553  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
113554  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
113555  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
113556  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
113557  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
113558  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
113559  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
113560  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
113561  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
113562  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
113563  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
113564  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
113565  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
113566  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
113567  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
113568  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
113569  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
113570  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
113571  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
113572  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
113573  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
113574  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
113575  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
113576  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
113577  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
113578  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
113579  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
113580  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
113581  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
113582  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
113583  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
113584  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
113585  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
113586  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
113587  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
113588  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
113589  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
113590  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
113591  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
113592  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
113593  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
113594  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
113595  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
113596  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
113597  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
113598  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
113599  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
113600  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
113601  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
113602  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
113603  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
113604  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
113605  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
113606  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
113607  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
113608  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
113609  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
113610  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
113611  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
113612  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
113613  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
113614  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
113615  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
113616  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
113617  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
113618  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
113619  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
113620  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
113621  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
113622  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
113623  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
113624  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
113625  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
113626  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
113627  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
113628  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
113629  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
113630  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
113631  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
113632  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
113633  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
113634  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
113635  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
113636  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
113637  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
113638  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
113639  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
113640  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
113641  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
113642  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
113643  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
113644  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
113645  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
113646  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
113647  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
113648  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
113649  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
113650  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
113651  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
113652  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
113653  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
113654  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
113655  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
113656  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
113657  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
113658  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
113659  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
113660  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
113661  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
113662  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
113663  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
113664  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
113665  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
113666  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
113667  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
113668  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
113669  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
113670  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
113671  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
113672  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
113673  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
113674  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
113675  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
113676  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
113677  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
113678  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
113679  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
113680  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
113681  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
113682  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
113683  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
113684  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
113685  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
113686  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
113687  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
113688  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
113689  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
113690  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
113691  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
113692  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
113693  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
113694  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
113695  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
113696  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
113697  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
113698  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
113699  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
113700  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
113701  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
113702  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
113703  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
113704  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
113705  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
113706  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
113707  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
113708  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
113709  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
113710  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
113711  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
113712  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
113713  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
113714  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
113715  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
113716  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
113717  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
113718  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
113719  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
113720  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
113721  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
113722  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
113723  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
113724  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
113725  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
113726  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
113727  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
113728  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
113729  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
113730  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
113731  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
113732  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
113733  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
113734  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
113735  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
113736  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
113737  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
113738  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
113739  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
113740  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
113741  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
113742  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
113743  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
113744  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
113745  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
113746  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
113747  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
113748  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
113749  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
113750  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
113751  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
113752  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
113753  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
113754  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
113755  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
113756  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
113757  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
113758  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
113759  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
113760  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
113761  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
113762  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
113763  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
113764  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
113765  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
113766  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
113767  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
113768  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
113769  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
113770  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
113771  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
113772  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
113773  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
113774  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
113775  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
113776  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
113777  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
113778  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
113779  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
113780  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
113781  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
113782  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
113783  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
113784  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
113785  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
113786  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
113787  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
113788  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
113789  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
113790  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
113791  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
113792  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
113793  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
113794  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
113795  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
113796  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
113797  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
113798  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
113799  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
113800  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
113801  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
113802  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
113803  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
113804  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
113805  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
113806  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
113807  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
113808  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
113809  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
113810  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
113811  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
113812  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
113813  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
113814  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
113815  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
113816  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
113817  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
113818  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
113819  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
113820  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
113821  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
113822  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
113823  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
113824  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
113825  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
113826  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
113827  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
113828  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
113829  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
113830  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
113831  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
113832  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
113833  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
113834  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
113835  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
113836  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
113837  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
113838  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
113839  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
113840  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
113841  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
113842  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
113843  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
113844  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
113845  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
113846  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
113847  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
113848  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
113849  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
113850  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
113851  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
113852  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
113853  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
113854  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
113855  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
113856  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
113857  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
113858  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
113859  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
113860  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
113861  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
113862  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
113863  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
113864  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
113865  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
113866  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
113867  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
113868  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
113869  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
113870  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
113871  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
113872  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
113873  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
113874  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
113875  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
113876  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
113877  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
113878  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
113879  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
113880  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
113881  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
113882  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
113883  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
113884  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
113885  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
113886  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
113887  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
113888  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
113889  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
113890  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
113891  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
113892  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
113893  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
113894  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
113895  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
113896  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
113897  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
113898  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
113899  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
113900  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
113901  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
113902  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
113903  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
113904  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
113905  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
113906  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
113907  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
113908  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
113909  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
113910  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
113911  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
113912  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
113913  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
113914  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
113915  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
113916  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
113917  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
113918  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
113919  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
113920  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
113921  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
113922  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
113923  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
113924  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
113925  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
113926  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
113927  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
113928  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
113929  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
113930  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
113931  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
113932  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
113933  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
113934  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
113935 };
113936 
113942 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
113943 {
113944  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
113945  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
113946  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
113947  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
113948  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
113949  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
113950  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
113951  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
113952  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
113953  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
113954  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
113955  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
113956  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
113957  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
113958  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
113959  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
113960  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
113961  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
113962  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
113963  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
113964  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
113965  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
113966  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
113967  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
113968  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
113969  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
113970  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
113971  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
113972  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
113973  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
113974  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
113975  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
113976  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
113977  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
113978  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
113979  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
113980  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
113981  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
113982  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
113983  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
113984  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
113985  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
113986  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
113987  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
113988  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
113989  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
113990  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
113991  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
113992  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
113993  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
113994  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
113995  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
113996  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
113997  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
113998  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
113999  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
114000  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
114001  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
114002  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
114003  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
114004  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
114005  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
114006  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
114007  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
114008  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
114009  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
114010  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
114011  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
114012  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
114013  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
114014  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
114015  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
114016  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
114017  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
114018  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
114019  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
114020  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
114021  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
114022  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
114023  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
114024  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
114025  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
114026  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
114027  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
114028  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
114029  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
114030  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
114031  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
114032  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
114033  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
114034  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
114035  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
114036  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
114037  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
114038  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
114039  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
114040  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
114041  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
114042  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
114043  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
114044  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
114045  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
114046  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
114047  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
114048  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
114049  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
114050  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
114051  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
114052  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
114053  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
114054  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
114055  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
114056  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
114057  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
114058  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
114059  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
114060  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
114061  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
114062  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
114063  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
114064  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
114065  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
114066  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
114067  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
114068  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
114069  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
114070  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
114071  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
114072  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
114073  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
114074  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
114075  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
114076  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
114077  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
114078  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
114079  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
114080  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
114081  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
114082  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
114083  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
114084  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
114085  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
114086  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
114087  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
114088  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
114089  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
114090  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
114091  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
114092  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
114093  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
114094  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
114095  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
114096  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
114097  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
114098  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
114099  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
114100  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
114101  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
114102  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
114103  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
114104  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
114105  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
114106  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
114107  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
114108  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
114109  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
114110  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
114111  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
114112  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
114113  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
114114  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
114115  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
114116  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
114117  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
114118  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
114119  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
114120  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
114121  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
114122  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
114123  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
114124  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
114125  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
114126  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
114127  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
114128  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
114129  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
114130  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
114131  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
114132  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
114133  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
114134  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
114135  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
114136  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
114137  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
114138  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
114139  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
114140  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
114141  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
114142  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
114143  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
114144  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
114145  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
114146  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
114147  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
114148  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
114149  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
114150  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
114151  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
114152  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
114153  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
114154  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
114155  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
114156  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
114157  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
114158  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
114159  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
114160  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
114161  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
114162  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
114163  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
114164  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
114165  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
114166  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
114167  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
114168  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
114169  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
114170  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
114171  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
114172  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
114173  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
114174  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
114175  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
114176  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
114177  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
114178  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
114179  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
114180  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
114181  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
114182  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
114183  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
114184  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
114185  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
114186  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
114187  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
114188  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
114189  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
114190  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
114191  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
114192  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
114193  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
114194  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
114195  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
114196  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
114197  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
114198  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
114199  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
114200  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
114201  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
114202  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
114203  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
114204  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
114205  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
114206  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
114207  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
114208  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
114209  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
114210  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
114211  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
114212  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
114213  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
114214  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
114215  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
114216  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
114217  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
114218  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
114219  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
114220  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
114221  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
114222  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
114223  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
114224  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
114225  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
114226  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
114227  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
114228  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
114229  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
114230  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
114231  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
114232  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
114233  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
114234  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
114235  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
114236  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
114237  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
114238  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
114239  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
114240  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
114241  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
114242  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
114243  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
114244  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
114245  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
114246  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
114247  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
114248  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
114249  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
114250  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
114251  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
114252  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
114253  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
114254  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
114255  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
114256  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
114257  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
114258  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
114259  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
114260  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
114261  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
114262  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
114263  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
114264  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
114265  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
114266  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
114267  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
114268  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
114269  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
114270  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
114271  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
114272  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
114273  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
114274  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
114275  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
114276  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
114277  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
114278  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
114279  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
114280  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
114281  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
114282  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
114283  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
114284  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
114285  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
114286  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
114287  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
114288  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
114289  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
114290  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
114291  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
114292  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
114293  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
114294  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
114295  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
114296  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
114297  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
114298  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
114299  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
114300  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
114301  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
114302  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
114303  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
114304  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
114305  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
114306  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
114307  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
114308  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
114309  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
114310  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
114311  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
114312  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
114313  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
114314  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
114315  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
114316  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
114317  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
114318  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
114319  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
114320  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
114321  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
114322  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
114323  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
114324  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
114325  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
114326  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
114327  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
114328  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
114329  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
114330  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
114331  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
114332  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
114333  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
114334  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
114335  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
114336  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
114337  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
114338  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
114339  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
114340  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
114341  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
114342  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
114343  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
114344  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
114345  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
114346  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
114347  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
114348  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
114349  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
114350  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
114351  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
114352  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
114353  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
114354  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
114355  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
114356  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
114357  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
114358  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
114359  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
114360  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
114361  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
114362  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
114363  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
114364  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
114365  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
114366  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
114367  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
114368  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
114369  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
114370  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
114371  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
114372  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
114373  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
114374  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
114375  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
114376  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
114377  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
114378  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
114379  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
114380  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
114381  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
114382  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
114383  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
114384  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
114385  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
114386  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
114387  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
114388  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
114389  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
114390  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
114391  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
114392  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
114393  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
114394  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
114395  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
114396  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
114397  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
114398  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
114399  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
114400  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
114401  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
114402  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
114403  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
114404  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
114405  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
114406  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
114407  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
114408  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
114409  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
114410  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
114411  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
114412  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
114413  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
114414  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
114415  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
114416  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
114417  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
114418  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
114419  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
114420  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
114421  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
114422  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
114423  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
114424  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
114425  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
114426  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
114427  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
114428  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
114429  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
114430  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
114431  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
114432  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
114433  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
114434  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
114435  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
114436  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
114437  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
114438  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
114439  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
114440  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
114441  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
114442  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
114443  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
114444  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
114445  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
114446  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
114447  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
114448  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
114449  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
114450  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
114451  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
114452  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
114453  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
114454  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
114455  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
114456 };
114457 
114463 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
114464 {
114465  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
114466  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
114467  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
114468  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
114469  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
114470  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
114471  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
114472  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
114473  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
114474  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
114475  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
114476  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
114477  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
114478  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
114479  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
114480  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
114481  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
114482  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
114483 };
114484 
114490 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
114491 {
114492  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
114493  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
114494  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
114495  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
114496  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
114497  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
114498  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
114499  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
114500  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
114501  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
114502  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
114503  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
114504  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
114505  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
114506  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
114507  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
114508  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
114509  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
114510  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
114511  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
114512  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
114513  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
114514  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
114515  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
114516  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
114517  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
114518  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
114519  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
114520  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
114521  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
114522 };
114523 
114529 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
114530 {
114531  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
114532  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
114533  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
114534  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
114535  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
114536  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
114537  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
114538  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
114539 };
114540 
114546 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
114547 {
114548  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
114549  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
114550  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
114551  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
114552  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
114553  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
114554  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
114555  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
114556  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
114557  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
114558  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
114559  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
114560  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
114561  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
114562  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
114563  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
114564  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
114565  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
114566  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
114567  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
114568  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
114569  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
114570  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
114571  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
114572  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
114573  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
114574  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
114575  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
114576  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
114577  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
114578  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
114579  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
114580  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
114581  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
114582  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
114583  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
114584  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
114585  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
114586  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
114587  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
114588  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
114589  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
114590  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
114591  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
114592  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
114593  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
114594  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
114595  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
114596  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
114597  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
114598  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
114599  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
114600  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
114601  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
114602  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
114603  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
114604  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
114605  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
114606  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
114607  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
114608  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
114609  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
114610  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
114611  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
114612  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
114613  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
114614  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
114615  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
114616  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
114617  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
114618  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
114619  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
114620  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
114621  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
114622  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
114623  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
114624  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
114625  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
114626  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
114627  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
114628  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
114629  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
114630  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
114631  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
114632 };
114633 
114639 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
114640 {
114641  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
114642  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
114643  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
114644  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
114645  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
114646  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
114647  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
114648  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
114649  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
114650  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
114651 };
114652 
114658 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_MAX_NUM_CHECKERS] =
114659 {
114660  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_0_CHECKER_TYPE,
114661  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_0_WIDTH },
114662  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_1_CHECKER_TYPE,
114663  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_1_WIDTH },
114664  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_2_CHECKER_TYPE,
114665  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_2_WIDTH },
114666  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_3_CHECKER_TYPE,
114667  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_3_WIDTH },
114668  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_4_CHECKER_TYPE,
114669  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_4_WIDTH },
114670  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_5_CHECKER_TYPE,
114671  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_5_WIDTH },
114672  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_6_CHECKER_TYPE,
114673  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_6_WIDTH },
114674  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_7_CHECKER_TYPE,
114675  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_7_WIDTH },
114676  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_8_CHECKER_TYPE,
114677  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_8_WIDTH },
114678  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_9_CHECKER_TYPE,
114679  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_9_WIDTH },
114680  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_10_CHECKER_TYPE,
114681  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_10_WIDTH },
114682  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_11_CHECKER_TYPE,
114683  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_11_WIDTH },
114684  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_12_CHECKER_TYPE,
114685  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_12_WIDTH },
114686  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_13_CHECKER_TYPE,
114687  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_13_WIDTH },
114688  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_14_CHECKER_TYPE,
114689  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_14_WIDTH },
114690  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_15_CHECKER_TYPE,
114691  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_15_WIDTH },
114692  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_16_CHECKER_TYPE,
114693  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_16_WIDTH },
114694  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_17_CHECKER_TYPE,
114695  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_17_WIDTH },
114696  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_18_CHECKER_TYPE,
114697  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_18_WIDTH },
114698  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_19_CHECKER_TYPE,
114699  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_19_WIDTH },
114700  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_20_CHECKER_TYPE,
114701  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_20_WIDTH },
114702  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_21_CHECKER_TYPE,
114703  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_21_WIDTH },
114704  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_22_CHECKER_TYPE,
114705  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_22_WIDTH },
114706  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_23_CHECKER_TYPE,
114707  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_23_WIDTH },
114708  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_24_CHECKER_TYPE,
114709  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_24_WIDTH },
114710  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_25_CHECKER_TYPE,
114711  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_25_WIDTH },
114712  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_26_CHECKER_TYPE,
114713  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_26_WIDTH },
114714  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_27_CHECKER_TYPE,
114715  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_27_WIDTH },
114716  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_28_CHECKER_TYPE,
114717  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_28_WIDTH },
114718  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_29_CHECKER_TYPE,
114719  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_29_WIDTH },
114720  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_30_CHECKER_TYPE,
114721  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_30_WIDTH },
114722  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_31_CHECKER_TYPE,
114723  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_31_WIDTH },
114724  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_32_CHECKER_TYPE,
114725  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_32_WIDTH },
114726  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_33_CHECKER_TYPE,
114727  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_33_WIDTH },
114728  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_34_CHECKER_TYPE,
114729  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_34_WIDTH },
114730  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_35_CHECKER_TYPE,
114731  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_35_WIDTH },
114732  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_36_CHECKER_TYPE,
114733  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_36_WIDTH },
114734  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_37_CHECKER_TYPE,
114735  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_37_WIDTH },
114736  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_38_CHECKER_TYPE,
114737  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_38_WIDTH },
114738  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_39_CHECKER_TYPE,
114739  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_39_WIDTH },
114740  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_40_CHECKER_TYPE,
114741  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_40_WIDTH },
114742  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_41_CHECKER_TYPE,
114743  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_41_WIDTH },
114744  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_42_CHECKER_TYPE,
114745  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_42_WIDTH },
114746  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_43_CHECKER_TYPE,
114747  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_43_WIDTH },
114748  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_44_CHECKER_TYPE,
114749  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_44_WIDTH },
114750  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_45_CHECKER_TYPE,
114751  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_45_WIDTH },
114752  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_46_CHECKER_TYPE,
114753  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_46_WIDTH },
114754  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_47_CHECKER_TYPE,
114755  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_47_WIDTH },
114756  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_48_CHECKER_TYPE,
114757  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_48_WIDTH },
114758  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_49_CHECKER_TYPE,
114759  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_49_WIDTH },
114760  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_50_CHECKER_TYPE,
114761  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_50_WIDTH },
114762  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_51_CHECKER_TYPE,
114763  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_51_WIDTH },
114764  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_52_CHECKER_TYPE,
114765  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_52_WIDTH },
114766  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_53_CHECKER_TYPE,
114767  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_53_WIDTH },
114768  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_54_CHECKER_TYPE,
114769  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_54_WIDTH },
114770  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_55_CHECKER_TYPE,
114771  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_55_WIDTH },
114772  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_56_CHECKER_TYPE,
114773  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_56_WIDTH },
114774  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_57_CHECKER_TYPE,
114775  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_57_WIDTH },
114776  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_58_CHECKER_TYPE,
114777  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_58_WIDTH },
114778  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_59_CHECKER_TYPE,
114779  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_59_WIDTH },
114780  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_60_CHECKER_TYPE,
114781  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_60_WIDTH },
114782  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_61_CHECKER_TYPE,
114783  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_61_WIDTH },
114784  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_62_CHECKER_TYPE,
114785  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_62_WIDTH },
114786  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_63_CHECKER_TYPE,
114787  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_63_WIDTH },
114788  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_64_CHECKER_TYPE,
114789  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_64_WIDTH },
114790  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_65_CHECKER_TYPE,
114791  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_65_WIDTH },
114792  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_66_CHECKER_TYPE,
114793  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_66_WIDTH },
114794  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_67_CHECKER_TYPE,
114795  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_67_WIDTH },
114796  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_68_CHECKER_TYPE,
114797  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_68_WIDTH },
114798  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_69_CHECKER_TYPE,
114799  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_69_WIDTH },
114800  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_70_CHECKER_TYPE,
114801  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_70_WIDTH },
114802  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_71_CHECKER_TYPE,
114803  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_71_WIDTH },
114804  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_72_CHECKER_TYPE,
114805  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_72_WIDTH },
114806  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_73_CHECKER_TYPE,
114807  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_73_WIDTH },
114808  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_74_CHECKER_TYPE,
114809  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_74_WIDTH },
114810  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_75_CHECKER_TYPE,
114811  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_75_WIDTH },
114812  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_76_CHECKER_TYPE,
114813  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_76_WIDTH },
114814  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_77_CHECKER_TYPE,
114815  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_77_WIDTH },
114816  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_78_CHECKER_TYPE,
114817  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_78_WIDTH },
114818  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_79_CHECKER_TYPE,
114819  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_79_WIDTH },
114820  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_80_CHECKER_TYPE,
114821  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_80_WIDTH },
114822  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_81_CHECKER_TYPE,
114823  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_81_WIDTH },
114824  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_82_CHECKER_TYPE,
114825  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_82_WIDTH },
114826  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_83_CHECKER_TYPE,
114827  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_83_WIDTH },
114828  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_84_CHECKER_TYPE,
114829  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_84_WIDTH },
114830  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_85_CHECKER_TYPE,
114831  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_85_WIDTH },
114832  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_86_CHECKER_TYPE,
114833  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_86_WIDTH },
114834  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_87_CHECKER_TYPE,
114835  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_87_WIDTH },
114836  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_88_CHECKER_TYPE,
114837  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_88_WIDTH },
114838  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_89_CHECKER_TYPE,
114839  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_89_WIDTH },
114840  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_90_CHECKER_TYPE,
114841  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_90_WIDTH },
114842  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_91_CHECKER_TYPE,
114843  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_91_WIDTH },
114844  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_92_CHECKER_TYPE,
114845  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_92_WIDTH },
114846  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_93_CHECKER_TYPE,
114847  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_93_WIDTH },
114848  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_94_CHECKER_TYPE,
114849  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_94_WIDTH },
114850  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_95_CHECKER_TYPE,
114851  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_95_WIDTH },
114852  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_96_CHECKER_TYPE,
114853  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_96_WIDTH },
114854  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_97_CHECKER_TYPE,
114855  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_97_WIDTH },
114856  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_98_CHECKER_TYPE,
114857  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_98_WIDTH },
114858  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_99_CHECKER_TYPE,
114859  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_99_WIDTH },
114860  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_100_CHECKER_TYPE,
114861  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_100_WIDTH },
114862  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_101_CHECKER_TYPE,
114863  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_101_WIDTH },
114864  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_102_CHECKER_TYPE,
114865  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_102_WIDTH },
114866  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_103_CHECKER_TYPE,
114867  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_103_WIDTH },
114868  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_104_CHECKER_TYPE,
114869  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_104_WIDTH },
114870  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_105_CHECKER_TYPE,
114871  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_105_WIDTH },
114872  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_106_CHECKER_TYPE,
114873  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_106_WIDTH },
114874  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_107_CHECKER_TYPE,
114875  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_107_WIDTH },
114876  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_108_CHECKER_TYPE,
114877  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_108_WIDTH },
114878  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_109_CHECKER_TYPE,
114879  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_109_WIDTH },
114880  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_110_CHECKER_TYPE,
114881  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_110_WIDTH },
114882  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_111_CHECKER_TYPE,
114883  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_111_WIDTH },
114884  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_112_CHECKER_TYPE,
114885  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_112_WIDTH },
114886  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_113_CHECKER_TYPE,
114887  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_113_WIDTH },
114888  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_114_CHECKER_TYPE,
114889  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_114_WIDTH },
114890  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_115_CHECKER_TYPE,
114891  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_115_WIDTH },
114892  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_116_CHECKER_TYPE,
114893  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_116_WIDTH },
114894  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_117_CHECKER_TYPE,
114895  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_117_WIDTH },
114896  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_118_CHECKER_TYPE,
114897  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_118_WIDTH },
114898  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_119_CHECKER_TYPE,
114899  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_119_WIDTH },
114900  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_120_CHECKER_TYPE,
114901  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_120_WIDTH },
114902  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_121_CHECKER_TYPE,
114903  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_121_WIDTH },
114904  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_122_CHECKER_TYPE,
114905  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_122_WIDTH },
114906  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_123_CHECKER_TYPE,
114907  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_123_WIDTH },
114908  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_124_CHECKER_TYPE,
114909  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_124_WIDTH },
114910  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_125_CHECKER_TYPE,
114911  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_125_WIDTH },
114912  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_126_CHECKER_TYPE,
114913  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_126_WIDTH },
114914  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_127_CHECKER_TYPE,
114915  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_127_WIDTH },
114916  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_128_CHECKER_TYPE,
114917  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_128_WIDTH },
114918  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_129_CHECKER_TYPE,
114919  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_129_WIDTH },
114920  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_130_CHECKER_TYPE,
114921  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_130_WIDTH },
114922  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_131_CHECKER_TYPE,
114923  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_131_WIDTH },
114924  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_132_CHECKER_TYPE,
114925  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_132_WIDTH },
114926  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_133_CHECKER_TYPE,
114927  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_133_WIDTH },
114928  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_134_CHECKER_TYPE,
114929  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_134_WIDTH },
114930  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_135_CHECKER_TYPE,
114931  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_135_WIDTH },
114932  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_136_CHECKER_TYPE,
114933  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_136_WIDTH },
114934  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_137_CHECKER_TYPE,
114935  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_137_WIDTH },
114936  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_138_CHECKER_TYPE,
114937  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_138_WIDTH },
114938  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_139_CHECKER_TYPE,
114939  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_139_WIDTH },
114940  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_140_CHECKER_TYPE,
114941  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_140_WIDTH },
114942  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_141_CHECKER_TYPE,
114943  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_141_WIDTH },
114944  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_142_CHECKER_TYPE,
114945  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_142_WIDTH },
114946  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_143_CHECKER_TYPE,
114947  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_143_WIDTH },
114948  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_144_CHECKER_TYPE,
114949  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_144_WIDTH },
114950  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_145_CHECKER_TYPE,
114951  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_145_WIDTH },
114952  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_146_CHECKER_TYPE,
114953  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_146_WIDTH },
114954  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_147_CHECKER_TYPE,
114955  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_147_WIDTH },
114956  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_148_CHECKER_TYPE,
114957  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_148_WIDTH },
114958  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_149_CHECKER_TYPE,
114959  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_149_WIDTH },
114960  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_150_CHECKER_TYPE,
114961  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_150_WIDTH },
114962  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_151_CHECKER_TYPE,
114963  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_151_WIDTH },
114964  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_152_CHECKER_TYPE,
114965  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_152_WIDTH },
114966  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_153_CHECKER_TYPE,
114967  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_153_WIDTH },
114968  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_154_CHECKER_TYPE,
114969  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_154_WIDTH },
114970  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_155_CHECKER_TYPE,
114971  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_155_WIDTH },
114972  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_156_CHECKER_TYPE,
114973  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_156_WIDTH },
114974  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_157_CHECKER_TYPE,
114975  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_157_WIDTH },
114976  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_158_CHECKER_TYPE,
114977  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_158_WIDTH },
114978  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_159_CHECKER_TYPE,
114979  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_159_WIDTH },
114980  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_160_CHECKER_TYPE,
114981  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_160_WIDTH },
114982  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_161_CHECKER_TYPE,
114983  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_161_WIDTH },
114984  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_162_CHECKER_TYPE,
114985  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_162_WIDTH },
114986  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_163_CHECKER_TYPE,
114987  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_163_WIDTH },
114988  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_164_CHECKER_TYPE,
114989  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_164_WIDTH },
114990  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_165_CHECKER_TYPE,
114991  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_165_WIDTH },
114992  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_166_CHECKER_TYPE,
114993  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_166_WIDTH },
114994  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_167_CHECKER_TYPE,
114995  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_167_WIDTH },
114996  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_168_CHECKER_TYPE,
114997  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_168_WIDTH },
114998  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_169_CHECKER_TYPE,
114999  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_169_WIDTH },
115000  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_170_CHECKER_TYPE,
115001  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_170_WIDTH },
115002  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_171_CHECKER_TYPE,
115003  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_171_WIDTH },
115004  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_172_CHECKER_TYPE,
115005  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_172_WIDTH },
115006  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_173_CHECKER_TYPE,
115007  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_173_WIDTH },
115008  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_174_CHECKER_TYPE,
115009  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_174_WIDTH },
115010  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_175_CHECKER_TYPE,
115011  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_175_WIDTH },
115012  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_176_CHECKER_TYPE,
115013  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_176_WIDTH },
115014  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_177_CHECKER_TYPE,
115015  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_177_WIDTH },
115016  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_178_CHECKER_TYPE,
115017  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_178_WIDTH },
115018  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_179_CHECKER_TYPE,
115019  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_179_WIDTH },
115020  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_180_CHECKER_TYPE,
115021  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_180_WIDTH },
115022  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_181_CHECKER_TYPE,
115023  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_181_WIDTH },
115024  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_182_CHECKER_TYPE,
115025  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_182_WIDTH },
115026  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_183_CHECKER_TYPE,
115027  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_183_WIDTH },
115028  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_184_CHECKER_TYPE,
115029  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_184_WIDTH },
115030  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_185_CHECKER_TYPE,
115031  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_185_WIDTH },
115032  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_186_CHECKER_TYPE,
115033  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_186_WIDTH },
115034  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_187_CHECKER_TYPE,
115035  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_187_WIDTH },
115036  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_188_CHECKER_TYPE,
115037  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_188_WIDTH },
115038  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_189_CHECKER_TYPE,
115039  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_189_WIDTH },
115040  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_190_CHECKER_TYPE,
115041  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_190_WIDTH },
115042  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_191_CHECKER_TYPE,
115043  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_191_WIDTH },
115044  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_192_CHECKER_TYPE,
115045  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_192_WIDTH },
115046  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_193_CHECKER_TYPE,
115047  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_193_WIDTH },
115048  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_194_CHECKER_TYPE,
115049  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_194_WIDTH },
115050  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_195_CHECKER_TYPE,
115051  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_195_WIDTH },
115052  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_196_CHECKER_TYPE,
115053  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_196_WIDTH },
115054  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_197_CHECKER_TYPE,
115055  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_197_WIDTH },
115056  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_198_CHECKER_TYPE,
115057  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_198_WIDTH },
115058  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_199_CHECKER_TYPE,
115059  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_199_WIDTH },
115060  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_200_CHECKER_TYPE,
115061  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_200_WIDTH },
115062  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_201_CHECKER_TYPE,
115063  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_201_WIDTH },
115064  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_202_CHECKER_TYPE,
115065  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_202_WIDTH },
115066  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_203_CHECKER_TYPE,
115067  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_203_WIDTH },
115068  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_204_CHECKER_TYPE,
115069  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_204_WIDTH },
115070  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_205_CHECKER_TYPE,
115071  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_205_WIDTH },
115072  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_206_CHECKER_TYPE,
115073  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_206_WIDTH },
115074  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_207_CHECKER_TYPE,
115075  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_207_WIDTH },
115076  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_208_CHECKER_TYPE,
115077  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_208_WIDTH },
115078  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_209_CHECKER_TYPE,
115079  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_209_WIDTH },
115080  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_210_CHECKER_TYPE,
115081  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_210_WIDTH },
115082  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_211_CHECKER_TYPE,
115083  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_211_WIDTH },
115084  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_212_CHECKER_TYPE,
115085  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_212_WIDTH },
115086  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_213_CHECKER_TYPE,
115087  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_213_WIDTH },
115088  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_214_CHECKER_TYPE,
115089  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_214_WIDTH },
115090  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_215_CHECKER_TYPE,
115091  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_215_WIDTH },
115092  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_216_CHECKER_TYPE,
115093  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_216_WIDTH },
115094  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_217_CHECKER_TYPE,
115095  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_217_WIDTH },
115096  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_218_CHECKER_TYPE,
115097  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_218_WIDTH },
115098  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_219_CHECKER_TYPE,
115099  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_219_WIDTH },
115100  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_220_CHECKER_TYPE,
115101  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_220_WIDTH },
115102  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_221_CHECKER_TYPE,
115103  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_221_WIDTH },
115104  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_222_CHECKER_TYPE,
115105  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_222_WIDTH },
115106  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_223_CHECKER_TYPE,
115107  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_223_WIDTH },
115108  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_224_CHECKER_TYPE,
115109  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_224_WIDTH },
115110  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_225_CHECKER_TYPE,
115111  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_225_WIDTH },
115112  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_226_CHECKER_TYPE,
115113  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_226_WIDTH },
115114  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_227_CHECKER_TYPE,
115115  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_227_WIDTH },
115116  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_228_CHECKER_TYPE,
115117  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_228_WIDTH },
115118  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_229_CHECKER_TYPE,
115119  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_229_WIDTH },
115120  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_230_CHECKER_TYPE,
115121  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_230_WIDTH },
115122  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_231_CHECKER_TYPE,
115123  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_231_WIDTH },
115124  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_232_CHECKER_TYPE,
115125  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_232_WIDTH },
115126  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_233_CHECKER_TYPE,
115127  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_233_WIDTH },
115128  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_234_CHECKER_TYPE,
115129  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_234_WIDTH },
115130  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_235_CHECKER_TYPE,
115131  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_235_WIDTH },
115132  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_236_CHECKER_TYPE,
115133  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_236_WIDTH },
115134  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_237_CHECKER_TYPE,
115135  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_237_WIDTH },
115136  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_238_CHECKER_TYPE,
115137  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_238_WIDTH },
115138  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_239_CHECKER_TYPE,
115139  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_239_WIDTH },
115140  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_240_CHECKER_TYPE,
115141  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_240_WIDTH },
115142  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_241_CHECKER_TYPE,
115143  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_241_WIDTH },
115144  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_242_CHECKER_TYPE,
115145  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_242_WIDTH },
115146  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_243_CHECKER_TYPE,
115147  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_243_WIDTH },
115148  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_244_CHECKER_TYPE,
115149  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_244_WIDTH },
115150  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_245_CHECKER_TYPE,
115151  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_245_WIDTH },
115152  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_246_CHECKER_TYPE,
115153  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_246_WIDTH },
115154  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_247_CHECKER_TYPE,
115155  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_247_WIDTH },
115156  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_248_CHECKER_TYPE,
115157  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_248_WIDTH },
115158  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_249_CHECKER_TYPE,
115159  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_249_WIDTH },
115160  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_250_CHECKER_TYPE,
115161  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_250_WIDTH },
115162  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_251_CHECKER_TYPE,
115163  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_251_WIDTH },
115164  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_252_CHECKER_TYPE,
115165  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_252_WIDTH },
115166  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_253_CHECKER_TYPE,
115167  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_253_WIDTH },
115168  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_254_CHECKER_TYPE,
115169  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_254_WIDTH },
115170  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_255_CHECKER_TYPE,
115171  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_GROUP_255_WIDTH },
115172 };
115173 
115179 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_MAX_NUM_CHECKERS] =
115180 {
115181  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_0_CHECKER_TYPE,
115182  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_0_WIDTH },
115183  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_1_CHECKER_TYPE,
115184  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_1_WIDTH },
115185  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_2_CHECKER_TYPE,
115186  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_2_WIDTH },
115187  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_3_CHECKER_TYPE,
115188  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_3_WIDTH },
115189  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_4_CHECKER_TYPE,
115190  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_4_WIDTH },
115191  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_5_CHECKER_TYPE,
115192  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_5_WIDTH },
115193  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_6_CHECKER_TYPE,
115194  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_6_WIDTH },
115195  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_7_CHECKER_TYPE,
115196  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_7_WIDTH },
115197  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_8_CHECKER_TYPE,
115198  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_8_WIDTH },
115199  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_9_CHECKER_TYPE,
115200  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_9_WIDTH },
115201  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_10_CHECKER_TYPE,
115202  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_10_WIDTH },
115203  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_11_CHECKER_TYPE,
115204  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_11_WIDTH },
115205  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_12_CHECKER_TYPE,
115206  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_12_WIDTH },
115207  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_13_CHECKER_TYPE,
115208  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_13_WIDTH },
115209  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_14_CHECKER_TYPE,
115210  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_14_WIDTH },
115211  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_15_CHECKER_TYPE,
115212  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_15_WIDTH },
115213  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_16_CHECKER_TYPE,
115214  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_16_WIDTH },
115215  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_17_CHECKER_TYPE,
115216  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_17_WIDTH },
115217  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_18_CHECKER_TYPE,
115218  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_18_WIDTH },
115219  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_19_CHECKER_TYPE,
115220  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_19_WIDTH },
115221  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_20_CHECKER_TYPE,
115222  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_20_WIDTH },
115223  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_21_CHECKER_TYPE,
115224  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_21_WIDTH },
115225  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_22_CHECKER_TYPE,
115226  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_22_WIDTH },
115227  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_23_CHECKER_TYPE,
115228  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_23_WIDTH },
115229  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_24_CHECKER_TYPE,
115230  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_24_WIDTH },
115231  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_25_CHECKER_TYPE,
115232  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_25_WIDTH },
115233  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_26_CHECKER_TYPE,
115234  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_26_WIDTH },
115235  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_27_CHECKER_TYPE,
115236  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_27_WIDTH },
115237  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_28_CHECKER_TYPE,
115238  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_28_WIDTH },
115239  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_29_CHECKER_TYPE,
115240  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_29_WIDTH },
115241  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_30_CHECKER_TYPE,
115242  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_30_WIDTH },
115243  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_31_CHECKER_TYPE,
115244  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_31_WIDTH },
115245  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_32_CHECKER_TYPE,
115246  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_32_WIDTH },
115247  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_33_CHECKER_TYPE,
115248  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_33_WIDTH },
115249  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_34_CHECKER_TYPE,
115250  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_34_WIDTH },
115251  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_35_CHECKER_TYPE,
115252  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_35_WIDTH },
115253  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_36_CHECKER_TYPE,
115254  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_36_WIDTH },
115255  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_37_CHECKER_TYPE,
115256  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_37_WIDTH },
115257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_38_CHECKER_TYPE,
115258  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_38_WIDTH },
115259  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_39_CHECKER_TYPE,
115260  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_39_WIDTH },
115261  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_40_CHECKER_TYPE,
115262  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_40_WIDTH },
115263  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_41_CHECKER_TYPE,
115264  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_41_WIDTH },
115265  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_42_CHECKER_TYPE,
115266  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_42_WIDTH },
115267  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_43_CHECKER_TYPE,
115268  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_43_WIDTH },
115269  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_44_CHECKER_TYPE,
115270  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_44_WIDTH },
115271  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_45_CHECKER_TYPE,
115272  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_45_WIDTH },
115273  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_46_CHECKER_TYPE,
115274  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_46_WIDTH },
115275  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_47_CHECKER_TYPE,
115276  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_47_WIDTH },
115277  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_48_CHECKER_TYPE,
115278  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_48_WIDTH },
115279  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_49_CHECKER_TYPE,
115280  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_49_WIDTH },
115281  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_50_CHECKER_TYPE,
115282  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_50_WIDTH },
115283  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_51_CHECKER_TYPE,
115284  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_51_WIDTH },
115285  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_52_CHECKER_TYPE,
115286  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_52_WIDTH },
115287  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_53_CHECKER_TYPE,
115288  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_53_WIDTH },
115289  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_54_CHECKER_TYPE,
115290  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_54_WIDTH },
115291  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_55_CHECKER_TYPE,
115292  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_55_WIDTH },
115293  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_56_CHECKER_TYPE,
115294  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_56_WIDTH },
115295  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_57_CHECKER_TYPE,
115296  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_57_WIDTH },
115297  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_58_CHECKER_TYPE,
115298  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_58_WIDTH },
115299  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_59_CHECKER_TYPE,
115300  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_59_WIDTH },
115301  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_60_CHECKER_TYPE,
115302  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_60_WIDTH },
115303  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_61_CHECKER_TYPE,
115304  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_61_WIDTH },
115305  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_62_CHECKER_TYPE,
115306  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_62_WIDTH },
115307  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_63_CHECKER_TYPE,
115308  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_63_WIDTH },
115309  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_64_CHECKER_TYPE,
115310  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_64_WIDTH },
115311  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_65_CHECKER_TYPE,
115312  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_65_WIDTH },
115313  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_66_CHECKER_TYPE,
115314  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_66_WIDTH },
115315  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_67_CHECKER_TYPE,
115316  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_67_WIDTH },
115317  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_68_CHECKER_TYPE,
115318  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_68_WIDTH },
115319  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_69_CHECKER_TYPE,
115320  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_69_WIDTH },
115321  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_70_CHECKER_TYPE,
115322  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_70_WIDTH },
115323  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_71_CHECKER_TYPE,
115324  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_71_WIDTH },
115325  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_72_CHECKER_TYPE,
115326  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_72_WIDTH },
115327  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_73_CHECKER_TYPE,
115328  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_73_WIDTH },
115329  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_74_CHECKER_TYPE,
115330  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_74_WIDTH },
115331  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_75_CHECKER_TYPE,
115332  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_75_WIDTH },
115333  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_76_CHECKER_TYPE,
115334  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_76_WIDTH },
115335  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_77_CHECKER_TYPE,
115336  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_77_WIDTH },
115337  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_78_CHECKER_TYPE,
115338  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_78_WIDTH },
115339  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_79_CHECKER_TYPE,
115340  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_79_WIDTH },
115341  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_80_CHECKER_TYPE,
115342  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_80_WIDTH },
115343  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_81_CHECKER_TYPE,
115344  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_81_WIDTH },
115345  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_82_CHECKER_TYPE,
115346  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_82_WIDTH },
115347  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_83_CHECKER_TYPE,
115348  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_83_WIDTH },
115349  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_84_CHECKER_TYPE,
115350  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_84_WIDTH },
115351  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_85_CHECKER_TYPE,
115352  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_85_WIDTH },
115353  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_86_CHECKER_TYPE,
115354  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_86_WIDTH },
115355  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_87_CHECKER_TYPE,
115356  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_87_WIDTH },
115357  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_88_CHECKER_TYPE,
115358  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_88_WIDTH },
115359  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_89_CHECKER_TYPE,
115360  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_89_WIDTH },
115361  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_90_CHECKER_TYPE,
115362  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_90_WIDTH },
115363  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_91_CHECKER_TYPE,
115364  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_91_WIDTH },
115365  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_92_CHECKER_TYPE,
115366  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_92_WIDTH },
115367  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_93_CHECKER_TYPE,
115368  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_93_WIDTH },
115369  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_94_CHECKER_TYPE,
115370  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_94_WIDTH },
115371  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_95_CHECKER_TYPE,
115372  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_95_WIDTH },
115373  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_96_CHECKER_TYPE,
115374  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_96_WIDTH },
115375  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_97_CHECKER_TYPE,
115376  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_97_WIDTH },
115377  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_98_CHECKER_TYPE,
115378  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_98_WIDTH },
115379  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_99_CHECKER_TYPE,
115380  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_99_WIDTH },
115381  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_100_CHECKER_TYPE,
115382  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_100_WIDTH },
115383  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_101_CHECKER_TYPE,
115384  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_101_WIDTH },
115385  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_102_CHECKER_TYPE,
115386  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_102_WIDTH },
115387  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_103_CHECKER_TYPE,
115388  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_103_WIDTH },
115389  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_104_CHECKER_TYPE,
115390  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_104_WIDTH },
115391  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_105_CHECKER_TYPE,
115392  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_105_WIDTH },
115393  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_106_CHECKER_TYPE,
115394  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_106_WIDTH },
115395  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_107_CHECKER_TYPE,
115396  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_107_WIDTH },
115397  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_108_CHECKER_TYPE,
115398  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_108_WIDTH },
115399  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_109_CHECKER_TYPE,
115400  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_109_WIDTH },
115401  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_110_CHECKER_TYPE,
115402  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_110_WIDTH },
115403  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_111_CHECKER_TYPE,
115404  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_111_WIDTH },
115405  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_112_CHECKER_TYPE,
115406  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_112_WIDTH },
115407  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_113_CHECKER_TYPE,
115408  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_113_WIDTH },
115409  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_114_CHECKER_TYPE,
115410  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_114_WIDTH },
115411  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_115_CHECKER_TYPE,
115412  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_115_WIDTH },
115413  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_116_CHECKER_TYPE,
115414  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_116_WIDTH },
115415  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_117_CHECKER_TYPE,
115416  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_117_WIDTH },
115417  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_118_CHECKER_TYPE,
115418  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_118_WIDTH },
115419  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_119_CHECKER_TYPE,
115420  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_119_WIDTH },
115421  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_120_CHECKER_TYPE,
115422  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_120_WIDTH },
115423  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_121_CHECKER_TYPE,
115424  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_121_WIDTH },
115425  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_122_CHECKER_TYPE,
115426  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_122_WIDTH },
115427  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_123_CHECKER_TYPE,
115428  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_123_WIDTH },
115429  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_124_CHECKER_TYPE,
115430  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_124_WIDTH },
115431  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_125_CHECKER_TYPE,
115432  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_125_WIDTH },
115433  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_126_CHECKER_TYPE,
115434  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_126_WIDTH },
115435  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_127_CHECKER_TYPE,
115436  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_127_WIDTH },
115437  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_128_CHECKER_TYPE,
115438  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_128_WIDTH },
115439  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_129_CHECKER_TYPE,
115440  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_129_WIDTH },
115441  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_130_CHECKER_TYPE,
115442  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_130_WIDTH },
115443  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_131_CHECKER_TYPE,
115444  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_131_WIDTH },
115445  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_132_CHECKER_TYPE,
115446  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_132_WIDTH },
115447  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_133_CHECKER_TYPE,
115448  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_133_WIDTH },
115449  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_134_CHECKER_TYPE,
115450  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_134_WIDTH },
115451  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_135_CHECKER_TYPE,
115452  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_135_WIDTH },
115453  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_136_CHECKER_TYPE,
115454  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_136_WIDTH },
115455  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_137_CHECKER_TYPE,
115456  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_137_WIDTH },
115457  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_138_CHECKER_TYPE,
115458  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_138_WIDTH },
115459  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_139_CHECKER_TYPE,
115460  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_139_WIDTH },
115461  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_140_CHECKER_TYPE,
115462  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_140_WIDTH },
115463  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_141_CHECKER_TYPE,
115464  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_141_WIDTH },
115465  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_142_CHECKER_TYPE,
115466  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_142_WIDTH },
115467  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_143_CHECKER_TYPE,
115468  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_143_WIDTH },
115469  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_144_CHECKER_TYPE,
115470  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_144_WIDTH },
115471  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_145_CHECKER_TYPE,
115472  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_145_WIDTH },
115473  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_146_CHECKER_TYPE,
115474  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_146_WIDTH },
115475  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_147_CHECKER_TYPE,
115476  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_147_WIDTH },
115477  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_148_CHECKER_TYPE,
115478  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_148_WIDTH },
115479  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_149_CHECKER_TYPE,
115480  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_149_WIDTH },
115481  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_150_CHECKER_TYPE,
115482  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_150_WIDTH },
115483  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_151_CHECKER_TYPE,
115484  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_151_WIDTH },
115485  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_152_CHECKER_TYPE,
115486  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_152_WIDTH },
115487  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_153_CHECKER_TYPE,
115488  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_153_WIDTH },
115489  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_154_CHECKER_TYPE,
115490  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_154_WIDTH },
115491  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_155_CHECKER_TYPE,
115492  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_155_WIDTH },
115493  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_156_CHECKER_TYPE,
115494  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_156_WIDTH },
115495  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_157_CHECKER_TYPE,
115496  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_157_WIDTH },
115497  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_158_CHECKER_TYPE,
115498  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_158_WIDTH },
115499  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_159_CHECKER_TYPE,
115500  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_159_WIDTH },
115501  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_160_CHECKER_TYPE,
115502  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_160_WIDTH },
115503  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_161_CHECKER_TYPE,
115504  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_161_WIDTH },
115505  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_162_CHECKER_TYPE,
115506  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_162_WIDTH },
115507  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_163_CHECKER_TYPE,
115508  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_163_WIDTH },
115509  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_164_CHECKER_TYPE,
115510  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_164_WIDTH },
115511  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_165_CHECKER_TYPE,
115512  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_165_WIDTH },
115513  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_166_CHECKER_TYPE,
115514  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_166_WIDTH },
115515  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_167_CHECKER_TYPE,
115516  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_167_WIDTH },
115517  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_168_CHECKER_TYPE,
115518  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_168_WIDTH },
115519  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_169_CHECKER_TYPE,
115520  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_169_WIDTH },
115521  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_170_CHECKER_TYPE,
115522  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_170_WIDTH },
115523  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_171_CHECKER_TYPE,
115524  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_171_WIDTH },
115525  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_172_CHECKER_TYPE,
115526  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_172_WIDTH },
115527  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_173_CHECKER_TYPE,
115528  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_173_WIDTH },
115529  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_174_CHECKER_TYPE,
115530  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_174_WIDTH },
115531  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_175_CHECKER_TYPE,
115532  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_175_WIDTH },
115533  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_176_CHECKER_TYPE,
115534  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_176_WIDTH },
115535  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_177_CHECKER_TYPE,
115536  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_177_WIDTH },
115537  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_178_CHECKER_TYPE,
115538  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_178_WIDTH },
115539  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_179_CHECKER_TYPE,
115540  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_179_WIDTH },
115541  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_180_CHECKER_TYPE,
115542  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_180_WIDTH },
115543  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_181_CHECKER_TYPE,
115544  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_181_WIDTH },
115545  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_182_CHECKER_TYPE,
115546  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_182_WIDTH },
115547  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_183_CHECKER_TYPE,
115548  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_183_WIDTH },
115549  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_184_CHECKER_TYPE,
115550  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_184_WIDTH },
115551  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_185_CHECKER_TYPE,
115552  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_185_WIDTH },
115553  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_186_CHECKER_TYPE,
115554  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_186_WIDTH },
115555  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_187_CHECKER_TYPE,
115556  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_187_WIDTH },
115557  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_188_CHECKER_TYPE,
115558  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_188_WIDTH },
115559  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_189_CHECKER_TYPE,
115560  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_189_WIDTH },
115561  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_190_CHECKER_TYPE,
115562  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_190_WIDTH },
115563  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_191_CHECKER_TYPE,
115564  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_191_WIDTH },
115565  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_192_CHECKER_TYPE,
115566  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_192_WIDTH },
115567  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_193_CHECKER_TYPE,
115568  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_193_WIDTH },
115569  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_194_CHECKER_TYPE,
115570  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_194_WIDTH },
115571  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_195_CHECKER_TYPE,
115572  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_195_WIDTH },
115573  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_196_CHECKER_TYPE,
115574  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_196_WIDTH },
115575  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_197_CHECKER_TYPE,
115576  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_197_WIDTH },
115577  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_198_CHECKER_TYPE,
115578  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_198_WIDTH },
115579  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_199_CHECKER_TYPE,
115580  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_199_WIDTH },
115581  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_200_CHECKER_TYPE,
115582  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_200_WIDTH },
115583  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_201_CHECKER_TYPE,
115584  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_201_WIDTH },
115585  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_202_CHECKER_TYPE,
115586  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_202_WIDTH },
115587  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_203_CHECKER_TYPE,
115588  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_203_WIDTH },
115589  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_204_CHECKER_TYPE,
115590  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_204_WIDTH },
115591  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_205_CHECKER_TYPE,
115592  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_205_WIDTH },
115593  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_206_CHECKER_TYPE,
115594  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_206_WIDTH },
115595  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_207_CHECKER_TYPE,
115596  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_207_WIDTH },
115597  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_208_CHECKER_TYPE,
115598  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_208_WIDTH },
115599  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_209_CHECKER_TYPE,
115600  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_209_WIDTH },
115601  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_210_CHECKER_TYPE,
115602  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_210_WIDTH },
115603  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_211_CHECKER_TYPE,
115604  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_211_WIDTH },
115605  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_212_CHECKER_TYPE,
115606  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_212_WIDTH },
115607  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_213_CHECKER_TYPE,
115608  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_213_WIDTH },
115609  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_214_CHECKER_TYPE,
115610  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_214_WIDTH },
115611  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_215_CHECKER_TYPE,
115612  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_215_WIDTH },
115613  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_216_CHECKER_TYPE,
115614  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_216_WIDTH },
115615  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_217_CHECKER_TYPE,
115616  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_217_WIDTH },
115617  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_218_CHECKER_TYPE,
115618  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_218_WIDTH },
115619  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_219_CHECKER_TYPE,
115620  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_219_WIDTH },
115621  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_220_CHECKER_TYPE,
115622  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_220_WIDTH },
115623  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_221_CHECKER_TYPE,
115624  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_221_WIDTH },
115625  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_222_CHECKER_TYPE,
115626  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_222_WIDTH },
115627  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_223_CHECKER_TYPE,
115628  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_223_WIDTH },
115629  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_224_CHECKER_TYPE,
115630  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_224_WIDTH },
115631  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_225_CHECKER_TYPE,
115632  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_225_WIDTH },
115633  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_226_CHECKER_TYPE,
115634  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_226_WIDTH },
115635  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_227_CHECKER_TYPE,
115636  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_227_WIDTH },
115637  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_228_CHECKER_TYPE,
115638  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_228_WIDTH },
115639  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_229_CHECKER_TYPE,
115640  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_229_WIDTH },
115641  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_230_CHECKER_TYPE,
115642  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_230_WIDTH },
115643  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_231_CHECKER_TYPE,
115644  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_231_WIDTH },
115645  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_232_CHECKER_TYPE,
115646  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_232_WIDTH },
115647  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_233_CHECKER_TYPE,
115648  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_233_WIDTH },
115649  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_234_CHECKER_TYPE,
115650  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_234_WIDTH },
115651  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_235_CHECKER_TYPE,
115652  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_235_WIDTH },
115653  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_236_CHECKER_TYPE,
115654  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_236_WIDTH },
115655  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_237_CHECKER_TYPE,
115656  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_237_WIDTH },
115657  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_238_CHECKER_TYPE,
115658  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_238_WIDTH },
115659  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_239_CHECKER_TYPE,
115660  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_239_WIDTH },
115661  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_240_CHECKER_TYPE,
115662  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_240_WIDTH },
115663  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_241_CHECKER_TYPE,
115664  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_241_WIDTH },
115665  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_242_CHECKER_TYPE,
115666  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_242_WIDTH },
115667  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_243_CHECKER_TYPE,
115668  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_243_WIDTH },
115669  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_244_CHECKER_TYPE,
115670  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_244_WIDTH },
115671  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_245_CHECKER_TYPE,
115672  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_245_WIDTH },
115673  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_246_CHECKER_TYPE,
115674  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_246_WIDTH },
115675  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_247_CHECKER_TYPE,
115676  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_247_WIDTH },
115677  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_248_CHECKER_TYPE,
115678  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_248_WIDTH },
115679  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_249_CHECKER_TYPE,
115680  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_249_WIDTH },
115681  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_250_CHECKER_TYPE,
115682  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_250_WIDTH },
115683  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_251_CHECKER_TYPE,
115684  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_251_WIDTH },
115685  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_252_CHECKER_TYPE,
115686  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_252_WIDTH },
115687  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_253_CHECKER_TYPE,
115688  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_253_WIDTH },
115689  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_254_CHECKER_TYPE,
115690  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_254_WIDTH },
115691  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_255_CHECKER_TYPE,
115692  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_GROUP_255_WIDTH },
115693 };
115694 
115700 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_MAX_NUM_CHECKERS] =
115701 {
115702  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_0_CHECKER_TYPE,
115703  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_0_WIDTH },
115704  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_1_CHECKER_TYPE,
115705  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_1_WIDTH },
115706  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_2_CHECKER_TYPE,
115707  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_2_WIDTH },
115708  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_3_CHECKER_TYPE,
115709  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_3_WIDTH },
115710  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_4_CHECKER_TYPE,
115711  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_4_WIDTH },
115712  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_5_CHECKER_TYPE,
115713  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_5_WIDTH },
115714  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_6_CHECKER_TYPE,
115715  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_6_WIDTH },
115716  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_7_CHECKER_TYPE,
115717  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_7_WIDTH },
115718  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_8_CHECKER_TYPE,
115719  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_8_WIDTH },
115720  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_9_CHECKER_TYPE,
115721  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_9_WIDTH },
115722  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_10_CHECKER_TYPE,
115723  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_10_WIDTH },
115724  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_11_CHECKER_TYPE,
115725  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_11_WIDTH },
115726  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_12_CHECKER_TYPE,
115727  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_12_WIDTH },
115728  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_13_CHECKER_TYPE,
115729  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_13_WIDTH },
115730  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_14_CHECKER_TYPE,
115731  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_14_WIDTH },
115732  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_15_CHECKER_TYPE,
115733  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_15_WIDTH },
115734  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_16_CHECKER_TYPE,
115735  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_16_WIDTH },
115736  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_17_CHECKER_TYPE,
115737  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_17_WIDTH },
115738  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_18_CHECKER_TYPE,
115739  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_18_WIDTH },
115740  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_19_CHECKER_TYPE,
115741  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_19_WIDTH },
115742  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_20_CHECKER_TYPE,
115743  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_20_WIDTH },
115744  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_21_CHECKER_TYPE,
115745  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_21_WIDTH },
115746  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_22_CHECKER_TYPE,
115747  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_22_WIDTH },
115748  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_23_CHECKER_TYPE,
115749  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_23_WIDTH },
115750  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_24_CHECKER_TYPE,
115751  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_24_WIDTH },
115752  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_25_CHECKER_TYPE,
115753  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_25_WIDTH },
115754  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_26_CHECKER_TYPE,
115755  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_26_WIDTH },
115756  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_27_CHECKER_TYPE,
115757  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_27_WIDTH },
115758  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_28_CHECKER_TYPE,
115759  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_28_WIDTH },
115760  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_29_CHECKER_TYPE,
115761  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_29_WIDTH },
115762  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_30_CHECKER_TYPE,
115763  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_30_WIDTH },
115764  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_31_CHECKER_TYPE,
115765  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_31_WIDTH },
115766  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_32_CHECKER_TYPE,
115767  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_32_WIDTH },
115768  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_33_CHECKER_TYPE,
115769  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_33_WIDTH },
115770  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_34_CHECKER_TYPE,
115771  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_34_WIDTH },
115772  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_35_CHECKER_TYPE,
115773  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_35_WIDTH },
115774  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_36_CHECKER_TYPE,
115775  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_36_WIDTH },
115776  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_37_CHECKER_TYPE,
115777  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_37_WIDTH },
115778  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_38_CHECKER_TYPE,
115779  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_38_WIDTH },
115780  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_39_CHECKER_TYPE,
115781  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_39_WIDTH },
115782  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_40_CHECKER_TYPE,
115783  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_40_WIDTH },
115784  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_41_CHECKER_TYPE,
115785  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_41_WIDTH },
115786  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_42_CHECKER_TYPE,
115787  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_42_WIDTH },
115788  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_43_CHECKER_TYPE,
115789  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_43_WIDTH },
115790  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_44_CHECKER_TYPE,
115791  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_44_WIDTH },
115792  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_45_CHECKER_TYPE,
115793  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_45_WIDTH },
115794  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_46_CHECKER_TYPE,
115795  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_46_WIDTH },
115796  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_47_CHECKER_TYPE,
115797  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_47_WIDTH },
115798  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_48_CHECKER_TYPE,
115799  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_48_WIDTH },
115800  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_49_CHECKER_TYPE,
115801  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_49_WIDTH },
115802  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_50_CHECKER_TYPE,
115803  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_50_WIDTH },
115804  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_51_CHECKER_TYPE,
115805  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_51_WIDTH },
115806  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_52_CHECKER_TYPE,
115807  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_52_WIDTH },
115808  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_53_CHECKER_TYPE,
115809  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_53_WIDTH },
115810  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_54_CHECKER_TYPE,
115811  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_54_WIDTH },
115812  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_55_CHECKER_TYPE,
115813  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_55_WIDTH },
115814  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_56_CHECKER_TYPE,
115815  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_56_WIDTH },
115816  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_57_CHECKER_TYPE,
115817  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_57_WIDTH },
115818  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_58_CHECKER_TYPE,
115819  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_58_WIDTH },
115820  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_59_CHECKER_TYPE,
115821  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_59_WIDTH },
115822  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_60_CHECKER_TYPE,
115823  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_60_WIDTH },
115824  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_61_CHECKER_TYPE,
115825  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_61_WIDTH },
115826  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_62_CHECKER_TYPE,
115827  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_62_WIDTH },
115828  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_63_CHECKER_TYPE,
115829  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_63_WIDTH },
115830  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_64_CHECKER_TYPE,
115831  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_64_WIDTH },
115832  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_65_CHECKER_TYPE,
115833  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_65_WIDTH },
115834  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_66_CHECKER_TYPE,
115835  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_66_WIDTH },
115836  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_67_CHECKER_TYPE,
115837  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_67_WIDTH },
115838  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_68_CHECKER_TYPE,
115839  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_68_WIDTH },
115840  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_69_CHECKER_TYPE,
115841  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_69_WIDTH },
115842  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_70_CHECKER_TYPE,
115843  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_70_WIDTH },
115844  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_71_CHECKER_TYPE,
115845  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_71_WIDTH },
115846  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_72_CHECKER_TYPE,
115847  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_72_WIDTH },
115848  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_73_CHECKER_TYPE,
115849  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_73_WIDTH },
115850  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_74_CHECKER_TYPE,
115851  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_74_WIDTH },
115852  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_75_CHECKER_TYPE,
115853  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_75_WIDTH },
115854  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_76_CHECKER_TYPE,
115855  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_76_WIDTH },
115856  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_77_CHECKER_TYPE,
115857  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_77_WIDTH },
115858  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_78_CHECKER_TYPE,
115859  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_78_WIDTH },
115860  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_79_CHECKER_TYPE,
115861  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_79_WIDTH },
115862  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_80_CHECKER_TYPE,
115863  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_80_WIDTH },
115864  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_81_CHECKER_TYPE,
115865  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_81_WIDTH },
115866  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_82_CHECKER_TYPE,
115867  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_82_WIDTH },
115868  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_83_CHECKER_TYPE,
115869  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_83_WIDTH },
115870  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_84_CHECKER_TYPE,
115871  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_84_WIDTH },
115872  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_85_CHECKER_TYPE,
115873  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_85_WIDTH },
115874  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_86_CHECKER_TYPE,
115875  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_86_WIDTH },
115876  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_87_CHECKER_TYPE,
115877  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_87_WIDTH },
115878  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_88_CHECKER_TYPE,
115879  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_88_WIDTH },
115880  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_89_CHECKER_TYPE,
115881  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_89_WIDTH },
115882  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_90_CHECKER_TYPE,
115883  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_90_WIDTH },
115884  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_91_CHECKER_TYPE,
115885  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_91_WIDTH },
115886  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_92_CHECKER_TYPE,
115887  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_92_WIDTH },
115888  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_93_CHECKER_TYPE,
115889  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_93_WIDTH },
115890  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_94_CHECKER_TYPE,
115891  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_94_WIDTH },
115892  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_95_CHECKER_TYPE,
115893  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_95_WIDTH },
115894  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_96_CHECKER_TYPE,
115895  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_96_WIDTH },
115896  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_97_CHECKER_TYPE,
115897  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_97_WIDTH },
115898  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_98_CHECKER_TYPE,
115899  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_98_WIDTH },
115900  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_99_CHECKER_TYPE,
115901  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_99_WIDTH },
115902  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_100_CHECKER_TYPE,
115903  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_100_WIDTH },
115904  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_101_CHECKER_TYPE,
115905  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_101_WIDTH },
115906  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_102_CHECKER_TYPE,
115907  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_102_WIDTH },
115908  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_103_CHECKER_TYPE,
115909  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_103_WIDTH },
115910  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_104_CHECKER_TYPE,
115911  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_104_WIDTH },
115912  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_105_CHECKER_TYPE,
115913  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_105_WIDTH },
115914  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_106_CHECKER_TYPE,
115915  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_106_WIDTH },
115916  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_107_CHECKER_TYPE,
115917  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_107_WIDTH },
115918  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_108_CHECKER_TYPE,
115919  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_108_WIDTH },
115920  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_109_CHECKER_TYPE,
115921  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_109_WIDTH },
115922  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_110_CHECKER_TYPE,
115923  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_110_WIDTH },
115924  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_111_CHECKER_TYPE,
115925  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_111_WIDTH },
115926  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_112_CHECKER_TYPE,
115927  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_112_WIDTH },
115928  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_113_CHECKER_TYPE,
115929  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_113_WIDTH },
115930  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_114_CHECKER_TYPE,
115931  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_114_WIDTH },
115932  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_115_CHECKER_TYPE,
115933  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_115_WIDTH },
115934  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_116_CHECKER_TYPE,
115935  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_116_WIDTH },
115936  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_117_CHECKER_TYPE,
115937  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_117_WIDTH },
115938  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_118_CHECKER_TYPE,
115939  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_118_WIDTH },
115940  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_119_CHECKER_TYPE,
115941  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_GROUP_119_WIDTH },
115942 };
115943 
115949 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
115950 {
115951  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
115952  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
115953  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
115954  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
115955  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
115956  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
115957  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
115958  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
115959  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
115960  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
115961  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
115962  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
115963  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
115964  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
115965  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
115966  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
115967  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
115968  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
115969  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
115970  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
115971  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
115972  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
115973  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
115974  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
115975  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
115976  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
115977  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
115978  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
115979  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
115980  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
115981  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
115982  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
115983  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
115984  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
115985  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
115986  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
115987  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
115988  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
115989  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
115990  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
115991  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
115992  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
115993  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
115994  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
115995  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
115996  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
115997  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
115998  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
115999  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
116000  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
116001  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
116002  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
116003  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
116004  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
116005  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
116006  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
116007  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
116008  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
116009  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
116010  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
116011  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
116012  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
116013  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
116014  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
116015  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
116016  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
116017  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
116018  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
116019  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
116020  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
116021  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
116022  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
116023  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
116024  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
116025  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
116026  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
116027  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
116028  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
116029  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
116030  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
116031  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
116032  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
116033 };
116034 
116040 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
116041 {
116042  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
116043  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
116044  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
116045  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
116046  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
116047  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
116048  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
116049  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
116050  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
116051  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
116052  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
116053  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
116054  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
116055  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
116056  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
116057  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
116058  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
116059  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
116060  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
116061  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
116062  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
116063  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
116064  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
116065  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
116066  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
116067  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
116068  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
116069  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
116070  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
116071  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
116072  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
116073  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
116074  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
116075  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
116076  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
116077  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
116078  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
116079  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
116080  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
116081  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
116082  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
116083  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
116084  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
116085  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
116086  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
116087  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
116088  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
116089  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
116090  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
116091  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
116092  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
116093  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
116094  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
116095  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
116096  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
116097  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
116098  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
116099  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
116100  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
116101  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
116102  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
116103  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
116104  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
116105  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
116106  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
116107  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
116108  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
116109  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
116110  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
116111  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
116112  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
116113  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
116114  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
116115  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
116116  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
116117  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
116118  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
116119  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
116120  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
116121  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
116122  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
116123  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
116124 };
116125 
116131 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
116132 {
116133  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
116134  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
116135  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
116136  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
116137  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
116138  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
116139  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
116140  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
116141  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
116142  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
116143  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
116144  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
116145  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
116146  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
116147  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
116148  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
116149  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
116150  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
116151  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
116152  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
116153  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
116154  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
116155  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
116156  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
116157  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
116158  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
116159  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
116160  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
116161  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
116162  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
116163  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
116164  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
116165  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
116166  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
116167  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
116168  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
116169  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
116170  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
116171  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
116172  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
116173  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
116174  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
116175  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
116176  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
116177  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
116178  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
116179  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
116180  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
116181  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
116182  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
116183  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
116184  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
116185  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
116186  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
116187  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
116188  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
116189  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
116190  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
116191  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
116192  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
116193  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
116194  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
116195  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
116196  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
116197  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
116198  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
116199  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
116200  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
116201  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
116202  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
116203  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
116204  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
116205  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
116206  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
116207  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
116208  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
116209  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
116210  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
116211  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
116212  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
116213  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
116214  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
116215  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
116216  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
116217  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
116218  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
116219  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
116220  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
116221  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
116222  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
116223  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
116224  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
116225  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
116226  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
116227  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
116228  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
116229  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
116230  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
116231  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
116232  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
116233  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
116234  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
116235  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
116236  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
116237  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
116238  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
116239  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
116240  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
116241  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
116242  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
116243  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
116244  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
116245  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
116246  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
116247  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
116248  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
116249  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
116250  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
116251  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
116252  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
116253  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
116254  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
116255  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
116256  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
116257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
116258  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
116259  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
116260  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
116261  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
116262  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
116263  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
116264  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
116265  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
116266  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
116267  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
116268  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
116269  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
116270  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
116271  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
116272  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
116273  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
116274  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
116275  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
116276  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
116277  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
116278  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
116279  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
116280  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
116281  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
116282  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
116283  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
116284  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
116285  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
116286  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
116287  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
116288  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
116289  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
116290  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
116291  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
116292  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
116293  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
116294  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
116295  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
116296  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
116297  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
116298  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
116299  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
116300  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
116301  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
116302  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
116303  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
116304  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
116305  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
116306  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
116307  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
116308  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
116309  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
116310  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
116311  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
116312  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
116313  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
116314  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
116315  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
116316  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
116317  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
116318  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
116319  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
116320  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
116321  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
116322  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
116323  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
116324  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
116325  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
116326  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
116327  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
116328  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
116329  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
116330  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
116331  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
116332  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
116333  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
116334  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
116335  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
116336  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
116337  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
116338  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
116339  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
116340  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
116341  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
116342  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
116343  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
116344  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
116345  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
116346  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
116347  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
116348  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
116349  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
116350  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
116351  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
116352  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
116353  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
116354  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
116355  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
116356  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
116357  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
116358  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
116359  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
116360  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
116361  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
116362  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
116363  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
116364  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
116365  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
116366  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
116367  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
116368  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
116369  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
116370  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
116371  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
116372  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
116373  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
116374  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
116375  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
116376  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
116377  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
116378  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
116379  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
116380  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
116381  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
116382  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
116383  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
116384  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
116385  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
116386  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
116387  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
116388  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
116389  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
116390  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
116391  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
116392  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
116393  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
116394  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
116395  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
116396  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
116397  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
116398  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
116399  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
116400  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
116401  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
116402  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
116403  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
116404  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
116405  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
116406  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
116407  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
116408  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
116409  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
116410  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
116411  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
116412  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
116413  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
116414  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
116415  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
116416  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
116417  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
116418  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
116419  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
116420  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
116421  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
116422  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
116423  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
116424  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
116425  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
116426  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
116427  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
116428  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
116429  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
116430  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
116431  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
116432  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
116433  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
116434  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
116435  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
116436  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
116437  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
116438  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
116439  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
116440  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
116441  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
116442  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
116443  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
116444  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
116445  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
116446  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
116447  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
116448  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
116449  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
116450  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
116451  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
116452  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
116453  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
116454  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
116455  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
116456  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
116457  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
116458  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
116459  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
116460  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
116461  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
116462  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
116463  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
116464  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
116465  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
116466  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
116467  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
116468  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
116469  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
116470  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
116471  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
116472  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
116473  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
116474  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
116475  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
116476  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
116477  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
116478  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
116479  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
116480  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
116481  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
116482  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
116483  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
116484  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
116485  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
116486  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
116487  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
116488  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
116489  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
116490  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
116491  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
116492  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
116493  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
116494  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
116495  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
116496  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
116497  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
116498  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
116499  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
116500  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
116501  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
116502  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
116503  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
116504  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
116505  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
116506  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
116507  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
116508  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
116509  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
116510  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
116511  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
116512  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
116513  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
116514  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
116515  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
116516  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
116517  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
116518  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
116519  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
116520  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
116521  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
116522  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
116523  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
116524  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
116525  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
116526  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
116527  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
116528  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
116529  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
116530  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
116531  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
116532  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
116533  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
116534  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
116535  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
116536  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
116537  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
116538  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
116539  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
116540  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
116541  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
116542  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
116543  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
116544  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
116545  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
116546  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
116547  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
116548  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
116549  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
116550  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
116551  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
116552  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
116553  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
116554  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
116555  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
116556  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
116557  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
116558  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
116559  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
116560  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
116561  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
116562  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
116563  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
116564  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
116565  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
116566  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
116567  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
116568  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
116569  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
116570  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
116571  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
116572  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
116573  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
116574  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
116575  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
116576  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
116577  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
116578  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
116579  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
116580  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
116581  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
116582  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
116583  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
116584  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
116585  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
116586  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
116587  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
116588  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
116589  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
116590  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
116591  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
116592  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
116593  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
116594  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
116595  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
116596  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
116597  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
116598  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
116599  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
116600  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
116601  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
116602  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
116603  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
116604  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
116605  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
116606  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
116607  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
116608  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
116609  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
116610  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
116611  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
116612  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
116613  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
116614  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
116615  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
116616  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
116617  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
116618  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
116619  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
116620  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
116621  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
116622  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
116623  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
116624  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
116625  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
116626  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
116627  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
116628  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
116629  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
116630  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
116631  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
116632  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
116633  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
116634  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
116635  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
116636  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
116637  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
116638  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
116639  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
116640  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
116641  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
116642  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
116643  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
116644  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
116645 };
116646 
116652 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
116653 {
116654  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
116655  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
116656  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
116657  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
116658  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
116659  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
116660  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
116661  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
116662  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
116663  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
116664  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
116665  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
116666  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
116667  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
116668  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
116669  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
116670  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
116671  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
116672  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
116673  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
116674  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
116675  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
116676  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
116677  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
116678  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
116679  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
116680  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
116681  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
116682  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
116683  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
116684  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
116685  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
116686  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
116687  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
116688  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
116689  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
116690  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
116691  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
116692  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
116693  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
116694  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
116695  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
116696  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
116697  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
116698  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
116699  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
116700  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
116701  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
116702  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
116703  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
116704  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
116705  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
116706  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
116707  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
116708  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
116709  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
116710  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
116711  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
116712  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
116713  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
116714  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
116715  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
116716  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
116717  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
116718  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
116719  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
116720  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
116721  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
116722  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
116723  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
116724  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
116725  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
116726  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
116727  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
116728  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
116729  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
116730  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
116731  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
116732  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
116733  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
116734  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
116735  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
116736  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
116737  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
116738  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
116739  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
116740  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
116741  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
116742  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
116743  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
116744  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
116745  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
116746  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
116747  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
116748  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
116749  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
116750  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
116751  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
116752  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
116753  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
116754  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
116755  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
116756  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
116757  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
116758  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
116759  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
116760  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
116761  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
116762  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
116763  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
116764  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
116765  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
116766  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
116767  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
116768  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
116769  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
116770  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
116771  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
116772  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
116773  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
116774  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
116775  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
116776  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
116777  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
116778  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
116779  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
116780  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
116781  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
116782  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
116783  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
116784  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
116785  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
116786  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
116787  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
116788  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
116789  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
116790  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
116791  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
116792  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
116793  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
116794  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
116795  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
116796  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
116797  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
116798  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
116799  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
116800  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
116801  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
116802  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
116803  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
116804  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
116805  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
116806  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
116807  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
116808  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
116809  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
116810  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
116811  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
116812  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
116813  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
116814  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
116815  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
116816  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
116817  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
116818  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
116819  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
116820  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
116821  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
116822  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
116823  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
116824  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
116825  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
116826  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
116827  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
116828  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
116829  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
116830  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
116831  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
116832  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
116833  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
116834  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
116835  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
116836  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
116837  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
116838  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
116839  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
116840  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
116841  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
116842  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
116843  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
116844  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
116845  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
116846  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
116847  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
116848  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
116849  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
116850  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
116851  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
116852  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
116853  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
116854  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
116855  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
116856  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
116857  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
116858  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
116859  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
116860  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
116861  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
116862  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
116863  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
116864  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
116865  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
116866  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
116867  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
116868  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
116869  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
116870  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
116871  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
116872  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
116873  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
116874  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
116875  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
116876  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
116877  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
116878  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
116879  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
116880  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
116881  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
116882  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
116883  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
116884  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
116885  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
116886  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
116887  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
116888  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
116889  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
116890  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
116891  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
116892  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
116893  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
116894  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
116895  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
116896  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
116897  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
116898  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
116899  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
116900  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
116901  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
116902  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
116903  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
116904  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
116905  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
116906  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
116907  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
116908  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
116909  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
116910  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
116911  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
116912  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
116913  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
116914  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
116915  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
116916  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
116917  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
116918  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
116919  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
116920  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
116921  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
116922  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
116923  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
116924  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
116925  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
116926  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
116927  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
116928  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
116929  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
116930  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
116931  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
116932  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
116933  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
116934  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
116935  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
116936  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
116937  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
116938  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
116939  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
116940  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
116941  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
116942  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
116943  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
116944  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
116945  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
116946  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
116947  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
116948  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
116949  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
116950  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
116951  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
116952  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
116953  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
116954  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
116955  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
116956  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
116957  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
116958  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
116959  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
116960  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
116961  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
116962  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
116963  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
116964  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
116965  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
116966  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
116967  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
116968  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
116969  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
116970  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
116971  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
116972  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
116973  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
116974  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
116975  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
116976  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
116977  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
116978  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
116979  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
116980  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
116981  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
116982  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
116983  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
116984  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
116985  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
116986  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
116987  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
116988  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
116989  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
116990  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
116991  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
116992  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
116993  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
116994  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
116995  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
116996  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
116997  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
116998  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
116999  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
117000  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
117001  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
117002  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
117003  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
117004 };
117005 
117011 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
117012 {
117013  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
117014  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
117015  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
117016  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
117017  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
117018  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
117019  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
117020  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
117021  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
117022  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
117023  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
117024  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
117025  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
117026  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
117027  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
117028  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
117029 };
117030 
117036 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
117037 {
117038  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
117039  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
117040  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
117041  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
117042  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
117043  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
117044  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
117045  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
117046  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
117047  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
117048  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
117049  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
117050  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
117051  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
117052  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
117053  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
117054  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
117055  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
117056  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
117057  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
117058  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
117059  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
117060  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
117061  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
117062  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
117063  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
117064  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
117065  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
117066  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
117067  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
117068 };
117069 
117075 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
117076 {
117077  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
117078  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
117079  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
117080  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
117081  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
117082  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
117083  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
117084  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
117085 };
117086 
117092 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
117093 {
117094  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
117095  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
117096  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
117097  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
117098  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
117099  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
117100  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
117101  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
117102  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
117103  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
117104  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
117105  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
117106  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
117107  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
117108  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
117109  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
117110  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
117111  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
117112  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
117113  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
117114  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
117115  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
117116  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
117117  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
117118  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
117119  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
117120  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
117121  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
117122  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
117123  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
117124  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
117125  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
117126  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
117127  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
117128  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
117129  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
117130  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
117131  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
117132  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
117133  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
117134  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
117135  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
117136  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
117137  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
117138  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
117139  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
117140  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
117141  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
117142  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
117143  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
117144  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
117145  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
117146  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
117147  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
117148  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
117149  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
117150  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
117151  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
117152  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
117153  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
117154  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
117155  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
117156  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
117157  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
117158  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
117159  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
117160  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
117161  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
117162  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
117163  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
117164  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
117165  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
117166  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
117167  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
117168  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
117169  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
117170  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
117171  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
117172  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
117173  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
117174  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
117175  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
117176  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
117177  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
117178 };
117179 
117185 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
117186 {
117187  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
117188  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
117189  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
117190  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
117191  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
117192  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
117193  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
117194  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
117195  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
117196  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
117197 };
117198 
117204 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS] =
117205 {
117206  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_0_CHECKER_TYPE,
117207  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_0_WIDTH },
117208  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_1_CHECKER_TYPE,
117209  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_1_WIDTH },
117210  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_2_CHECKER_TYPE,
117211  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_2_WIDTH },
117212  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_3_CHECKER_TYPE,
117213  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_3_WIDTH },
117214  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_4_CHECKER_TYPE,
117215  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_4_WIDTH },
117216  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_5_CHECKER_TYPE,
117217  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_5_WIDTH },
117218  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_6_CHECKER_TYPE,
117219  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_6_WIDTH },
117220  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_7_CHECKER_TYPE,
117221  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_7_WIDTH },
117222  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_8_CHECKER_TYPE,
117223  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_8_WIDTH },
117224  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_9_CHECKER_TYPE,
117225  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_9_WIDTH },
117226  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_10_CHECKER_TYPE,
117227  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_10_WIDTH },
117228  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_11_CHECKER_TYPE,
117229  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_11_WIDTH },
117230  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_12_CHECKER_TYPE,
117231  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_12_WIDTH },
117232  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_13_CHECKER_TYPE,
117233  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_13_WIDTH },
117234  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_14_CHECKER_TYPE,
117235  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_14_WIDTH },
117236  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_15_CHECKER_TYPE,
117237  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_15_WIDTH },
117238  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_16_CHECKER_TYPE,
117239  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_16_WIDTH },
117240  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_17_CHECKER_TYPE,
117241  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_17_WIDTH },
117242  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_18_CHECKER_TYPE,
117243  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_18_WIDTH },
117244  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_19_CHECKER_TYPE,
117245  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_19_WIDTH },
117246  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_20_CHECKER_TYPE,
117247  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_20_WIDTH },
117248  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_21_CHECKER_TYPE,
117249  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_21_WIDTH },
117250  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_22_CHECKER_TYPE,
117251  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_22_WIDTH },
117252  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_23_CHECKER_TYPE,
117253  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_23_WIDTH },
117254  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_24_CHECKER_TYPE,
117255  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_24_WIDTH },
117256  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_25_CHECKER_TYPE,
117257  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_25_WIDTH },
117258  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_26_CHECKER_TYPE,
117259  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_26_WIDTH },
117260  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_27_CHECKER_TYPE,
117261  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_27_WIDTH },
117262  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_28_CHECKER_TYPE,
117263  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_28_WIDTH },
117264  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_29_CHECKER_TYPE,
117265  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_29_WIDTH },
117266  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_30_CHECKER_TYPE,
117267  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_30_WIDTH },
117268  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_31_CHECKER_TYPE,
117269  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_31_WIDTH },
117270  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_32_CHECKER_TYPE,
117271  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_32_WIDTH },
117272  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_33_CHECKER_TYPE,
117273  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_33_WIDTH },
117274  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_34_CHECKER_TYPE,
117275  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_34_WIDTH },
117276  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_35_CHECKER_TYPE,
117277  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_35_WIDTH },
117278  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_36_CHECKER_TYPE,
117279  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_36_WIDTH },
117280  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_37_CHECKER_TYPE,
117281  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_37_WIDTH },
117282  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_38_CHECKER_TYPE,
117283  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_38_WIDTH },
117284  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_39_CHECKER_TYPE,
117285  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_39_WIDTH },
117286  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_40_CHECKER_TYPE,
117287  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_40_WIDTH },
117288  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_41_CHECKER_TYPE,
117289  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_41_WIDTH },
117290  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_42_CHECKER_TYPE,
117291  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_42_WIDTH },
117292  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_43_CHECKER_TYPE,
117293  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_43_WIDTH },
117294  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_44_CHECKER_TYPE,
117295  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_44_WIDTH },
117296  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_45_CHECKER_TYPE,
117297  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_45_WIDTH },
117298  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_46_CHECKER_TYPE,
117299  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_46_WIDTH },
117300  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_47_CHECKER_TYPE,
117301  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_47_WIDTH },
117302  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_48_CHECKER_TYPE,
117303  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_48_WIDTH },
117304  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_49_CHECKER_TYPE,
117305  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_49_WIDTH },
117306  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_50_CHECKER_TYPE,
117307  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_50_WIDTH },
117308  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_51_CHECKER_TYPE,
117309  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_51_WIDTH },
117310  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_52_CHECKER_TYPE,
117311  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_52_WIDTH },
117312  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_53_CHECKER_TYPE,
117313  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_53_WIDTH },
117314  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_54_CHECKER_TYPE,
117315  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_54_WIDTH },
117316  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_55_CHECKER_TYPE,
117317  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_55_WIDTH },
117318  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_56_CHECKER_TYPE,
117319  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_56_WIDTH },
117320  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_57_CHECKER_TYPE,
117321  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_57_WIDTH },
117322  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_58_CHECKER_TYPE,
117323  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_58_WIDTH },
117324  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_59_CHECKER_TYPE,
117325  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_59_WIDTH },
117326  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_60_CHECKER_TYPE,
117327  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_60_WIDTH },
117328  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_61_CHECKER_TYPE,
117329  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_61_WIDTH },
117330  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_62_CHECKER_TYPE,
117331  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_62_WIDTH },
117332  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_63_CHECKER_TYPE,
117333  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_63_WIDTH },
117334  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_64_CHECKER_TYPE,
117335  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_64_WIDTH },
117336  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_65_CHECKER_TYPE,
117337  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_65_WIDTH },
117338  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_66_CHECKER_TYPE,
117339  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_66_WIDTH },
117340  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_67_CHECKER_TYPE,
117341  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_67_WIDTH },
117342  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_68_CHECKER_TYPE,
117343  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_68_WIDTH },
117344  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_69_CHECKER_TYPE,
117345  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_69_WIDTH },
117346  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_70_CHECKER_TYPE,
117347  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_70_WIDTH },
117348  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_71_CHECKER_TYPE,
117349  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_71_WIDTH },
117350  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_72_CHECKER_TYPE,
117351  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_72_WIDTH },
117352  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_73_CHECKER_TYPE,
117353  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_73_WIDTH },
117354  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_74_CHECKER_TYPE,
117355  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_74_WIDTH },
117356  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_75_CHECKER_TYPE,
117357  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_75_WIDTH },
117358  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_76_CHECKER_TYPE,
117359  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_76_WIDTH },
117360  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_77_CHECKER_TYPE,
117361  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_77_WIDTH },
117362  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_78_CHECKER_TYPE,
117363  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_78_WIDTH },
117364  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_79_CHECKER_TYPE,
117365  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_79_WIDTH },
117366  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_80_CHECKER_TYPE,
117367  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_80_WIDTH },
117368  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_81_CHECKER_TYPE,
117369  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_81_WIDTH },
117370  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_82_CHECKER_TYPE,
117371  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_82_WIDTH },
117372  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_83_CHECKER_TYPE,
117373  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_83_WIDTH },
117374  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_84_CHECKER_TYPE,
117375  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_84_WIDTH },
117376  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_85_CHECKER_TYPE,
117377  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_85_WIDTH },
117378  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_86_CHECKER_TYPE,
117379  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_86_WIDTH },
117380  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_87_CHECKER_TYPE,
117381  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_87_WIDTH },
117382  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_88_CHECKER_TYPE,
117383  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_88_WIDTH },
117384  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_89_CHECKER_TYPE,
117385  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_89_WIDTH },
117386  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_90_CHECKER_TYPE,
117387  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_90_WIDTH },
117388  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_91_CHECKER_TYPE,
117389  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_91_WIDTH },
117390  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_92_CHECKER_TYPE,
117391  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_92_WIDTH },
117392  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_93_CHECKER_TYPE,
117393  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_93_WIDTH },
117394  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_94_CHECKER_TYPE,
117395  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_94_WIDTH },
117396  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_95_CHECKER_TYPE,
117397  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_95_WIDTH },
117398  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_96_CHECKER_TYPE,
117399  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_96_WIDTH },
117400  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_97_CHECKER_TYPE,
117401  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_97_WIDTH },
117402  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_98_CHECKER_TYPE,
117403  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_98_WIDTH },
117404  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_99_CHECKER_TYPE,
117405  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_99_WIDTH },
117406  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_100_CHECKER_TYPE,
117407  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_100_WIDTH },
117408  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_101_CHECKER_TYPE,
117409  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_101_WIDTH },
117410  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_102_CHECKER_TYPE,
117411  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_102_WIDTH },
117412  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_103_CHECKER_TYPE,
117413  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_103_WIDTH },
117414  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_104_CHECKER_TYPE,
117415  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_104_WIDTH },
117416  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_105_CHECKER_TYPE,
117417  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_105_WIDTH },
117418  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_106_CHECKER_TYPE,
117419  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_106_WIDTH },
117420  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_107_CHECKER_TYPE,
117421  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_107_WIDTH },
117422  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_108_CHECKER_TYPE,
117423  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_108_WIDTH },
117424  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_109_CHECKER_TYPE,
117425  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_109_WIDTH },
117426  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_110_CHECKER_TYPE,
117427  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_110_WIDTH },
117428  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_111_CHECKER_TYPE,
117429  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_111_WIDTH },
117430  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_112_CHECKER_TYPE,
117431  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_112_WIDTH },
117432  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_113_CHECKER_TYPE,
117433  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_113_WIDTH },
117434  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_114_CHECKER_TYPE,
117435  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_114_WIDTH },
117436  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_115_CHECKER_TYPE,
117437  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_115_WIDTH },
117438  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_116_CHECKER_TYPE,
117439  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_116_WIDTH },
117440  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_117_CHECKER_TYPE,
117441  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_117_WIDTH },
117442  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_118_CHECKER_TYPE,
117443  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_118_WIDTH },
117444  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_119_CHECKER_TYPE,
117445  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_119_WIDTH },
117446  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_120_CHECKER_TYPE,
117447  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_120_WIDTH },
117448  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_121_CHECKER_TYPE,
117449  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_121_WIDTH },
117450  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_122_CHECKER_TYPE,
117451  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_122_WIDTH },
117452  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_123_CHECKER_TYPE,
117453  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_123_WIDTH },
117454  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_124_CHECKER_TYPE,
117455  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_124_WIDTH },
117456  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_125_CHECKER_TYPE,
117457  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_125_WIDTH },
117458  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_126_CHECKER_TYPE,
117459  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_126_WIDTH },
117460  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_127_CHECKER_TYPE,
117461  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_127_WIDTH },
117462  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_128_CHECKER_TYPE,
117463  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_128_WIDTH },
117464  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_129_CHECKER_TYPE,
117465  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_129_WIDTH },
117466  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_130_CHECKER_TYPE,
117467  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_130_WIDTH },
117468  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_131_CHECKER_TYPE,
117469  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_131_WIDTH },
117470  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_132_CHECKER_TYPE,
117471  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_132_WIDTH },
117472  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_133_CHECKER_TYPE,
117473  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_133_WIDTH },
117474  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_134_CHECKER_TYPE,
117475  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_134_WIDTH },
117476  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_135_CHECKER_TYPE,
117477  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_135_WIDTH },
117478  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_136_CHECKER_TYPE,
117479  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_136_WIDTH },
117480  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_137_CHECKER_TYPE,
117481  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_137_WIDTH },
117482  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_138_CHECKER_TYPE,
117483  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_138_WIDTH },
117484  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_139_CHECKER_TYPE,
117485  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_139_WIDTH },
117486  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_140_CHECKER_TYPE,
117487  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_140_WIDTH },
117488  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_141_CHECKER_TYPE,
117489  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_141_WIDTH },
117490  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_142_CHECKER_TYPE,
117491  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_142_WIDTH },
117492  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_143_CHECKER_TYPE,
117493  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_143_WIDTH },
117494  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_144_CHECKER_TYPE,
117495  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_144_WIDTH },
117496  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_145_CHECKER_TYPE,
117497  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_145_WIDTH },
117498  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_146_CHECKER_TYPE,
117499  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_146_WIDTH },
117500  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_147_CHECKER_TYPE,
117501  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_147_WIDTH },
117502  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_148_CHECKER_TYPE,
117503  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_148_WIDTH },
117504  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_149_CHECKER_TYPE,
117505  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_149_WIDTH },
117506  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_150_CHECKER_TYPE,
117507  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_150_WIDTH },
117508  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_151_CHECKER_TYPE,
117509  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_151_WIDTH },
117510  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_152_CHECKER_TYPE,
117511  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_152_WIDTH },
117512  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_153_CHECKER_TYPE,
117513  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_153_WIDTH },
117514  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_154_CHECKER_TYPE,
117515  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_154_WIDTH },
117516  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_155_CHECKER_TYPE,
117517  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_155_WIDTH },
117518  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_156_CHECKER_TYPE,
117519  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_156_WIDTH },
117520  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_157_CHECKER_TYPE,
117521  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_157_WIDTH },
117522  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_158_CHECKER_TYPE,
117523  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_158_WIDTH },
117524  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_159_CHECKER_TYPE,
117525  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_159_WIDTH },
117526  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_160_CHECKER_TYPE,
117527  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_160_WIDTH },
117528  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_161_CHECKER_TYPE,
117529  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_161_WIDTH },
117530  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_162_CHECKER_TYPE,
117531  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_162_WIDTH },
117532  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_163_CHECKER_TYPE,
117533  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_163_WIDTH },
117534  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_164_CHECKER_TYPE,
117535  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_164_WIDTH },
117536  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_165_CHECKER_TYPE,
117537  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_165_WIDTH },
117538  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_166_CHECKER_TYPE,
117539  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_166_WIDTH },
117540  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_167_CHECKER_TYPE,
117541  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_167_WIDTH },
117542  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_168_CHECKER_TYPE,
117543  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_168_WIDTH },
117544  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_169_CHECKER_TYPE,
117545  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_169_WIDTH },
117546  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_170_CHECKER_TYPE,
117547  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_170_WIDTH },
117548  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_171_CHECKER_TYPE,
117549  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_171_WIDTH },
117550  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_172_CHECKER_TYPE,
117551  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_172_WIDTH },
117552  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_173_CHECKER_TYPE,
117553  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_173_WIDTH },
117554  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_174_CHECKER_TYPE,
117555  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_174_WIDTH },
117556  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_175_CHECKER_TYPE,
117557  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_175_WIDTH },
117558  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_176_CHECKER_TYPE,
117559  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_176_WIDTH },
117560  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_177_CHECKER_TYPE,
117561  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_177_WIDTH },
117562  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_178_CHECKER_TYPE,
117563  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_178_WIDTH },
117564  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_179_CHECKER_TYPE,
117565  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_179_WIDTH },
117566  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_180_CHECKER_TYPE,
117567  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_180_WIDTH },
117568  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_181_CHECKER_TYPE,
117569  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_181_WIDTH },
117570  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_182_CHECKER_TYPE,
117571  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_182_WIDTH },
117572  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_183_CHECKER_TYPE,
117573  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_183_WIDTH },
117574  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_184_CHECKER_TYPE,
117575  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_184_WIDTH },
117576  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_185_CHECKER_TYPE,
117577  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_185_WIDTH },
117578  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_186_CHECKER_TYPE,
117579  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_186_WIDTH },
117580  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_187_CHECKER_TYPE,
117581  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_187_WIDTH },
117582  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_188_CHECKER_TYPE,
117583  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_188_WIDTH },
117584  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_189_CHECKER_TYPE,
117585  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_189_WIDTH },
117586  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_190_CHECKER_TYPE,
117587  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_190_WIDTH },
117588  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_191_CHECKER_TYPE,
117589  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_191_WIDTH },
117590  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_192_CHECKER_TYPE,
117591  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_192_WIDTH },
117592  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_193_CHECKER_TYPE,
117593  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_193_WIDTH },
117594  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_194_CHECKER_TYPE,
117595  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_194_WIDTH },
117596  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_195_CHECKER_TYPE,
117597  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_195_WIDTH },
117598  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_196_CHECKER_TYPE,
117599  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_196_WIDTH },
117600  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_197_CHECKER_TYPE,
117601  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_197_WIDTH },
117602  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_198_CHECKER_TYPE,
117603  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_198_WIDTH },
117604  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_199_CHECKER_TYPE,
117605  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_199_WIDTH },
117606  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_200_CHECKER_TYPE,
117607  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_200_WIDTH },
117608  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_201_CHECKER_TYPE,
117609  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_201_WIDTH },
117610  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_202_CHECKER_TYPE,
117611  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_202_WIDTH },
117612  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_203_CHECKER_TYPE,
117613  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_203_WIDTH },
117614  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_204_CHECKER_TYPE,
117615  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_204_WIDTH },
117616  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_205_CHECKER_TYPE,
117617  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_205_WIDTH },
117618  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_206_CHECKER_TYPE,
117619  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_206_WIDTH },
117620  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_207_CHECKER_TYPE,
117621  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_207_WIDTH },
117622  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_208_CHECKER_TYPE,
117623  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_208_WIDTH },
117624  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_209_CHECKER_TYPE,
117625  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_209_WIDTH },
117626  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_210_CHECKER_TYPE,
117627  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_210_WIDTH },
117628  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_211_CHECKER_TYPE,
117629  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_211_WIDTH },
117630  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_212_CHECKER_TYPE,
117631  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_212_WIDTH },
117632  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_213_CHECKER_TYPE,
117633  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_213_WIDTH },
117634  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_214_CHECKER_TYPE,
117635  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_214_WIDTH },
117636  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_215_CHECKER_TYPE,
117637  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_215_WIDTH },
117638  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_216_CHECKER_TYPE,
117639  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_216_WIDTH },
117640  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_217_CHECKER_TYPE,
117641  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_217_WIDTH },
117642  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_218_CHECKER_TYPE,
117643  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_218_WIDTH },
117644  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_219_CHECKER_TYPE,
117645  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_219_WIDTH },
117646  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_220_CHECKER_TYPE,
117647  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_220_WIDTH },
117648  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_221_CHECKER_TYPE,
117649  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_221_WIDTH },
117650  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_222_CHECKER_TYPE,
117651  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_222_WIDTH },
117652  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_223_CHECKER_TYPE,
117653  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_223_WIDTH },
117654  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_224_CHECKER_TYPE,
117655  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_224_WIDTH },
117656  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_225_CHECKER_TYPE,
117657  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_225_WIDTH },
117658  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_226_CHECKER_TYPE,
117659  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_226_WIDTH },
117660  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_227_CHECKER_TYPE,
117661  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_227_WIDTH },
117662  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_228_CHECKER_TYPE,
117663  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_228_WIDTH },
117664  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_229_CHECKER_TYPE,
117665  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_229_WIDTH },
117666  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_230_CHECKER_TYPE,
117667  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_230_WIDTH },
117668  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_231_CHECKER_TYPE,
117669  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_231_WIDTH },
117670  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_232_CHECKER_TYPE,
117671  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_232_WIDTH },
117672  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_233_CHECKER_TYPE,
117673  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_233_WIDTH },
117674 };
117675 
117681 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
117682 {
117683  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
117684  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
117685  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
117686  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
117687  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
117688  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
117689  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
117690  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
117691  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
117692  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
117693  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
117694  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
117695  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
117696  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
117697  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
117698  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
117699  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
117700  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
117701  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
117702  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
117703  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
117704  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
117705  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
117706  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
117707  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
117708  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
117709  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
117710  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
117711  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
117712  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
117713 };
117714 
117720 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
117721 {
117722  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
117723  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
117724  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
117725  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
117726  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
117727  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
117728  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
117729  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
117730 };
117731 
117737 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
117738 {
117739  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
117740  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
117741  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
117742  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
117743  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
117744  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
117745  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
117746  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
117747  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
117748  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
117749  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
117750  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
117751  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
117752  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
117753  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
117754  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
117755  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
117756  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
117757  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
117758  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
117759  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
117760  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
117761  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
117762  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
117763  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
117764  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
117765  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
117766  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
117767  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
117768  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
117769  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
117770  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
117771  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
117772  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
117773  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
117774  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
117775  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
117776  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
117777  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
117778  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
117779  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
117780  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
117781  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
117782  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
117783  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
117784  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
117785  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
117786  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
117787  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
117788  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
117789  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
117790  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
117791  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
117792  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
117793  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
117794  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
117795  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
117796  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
117797  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
117798  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
117799  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
117800  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
117801  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
117802  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
117803  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
117804  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
117805  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
117806  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
117807  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
117808  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
117809  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
117810  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
117811  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
117812  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
117813  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
117814  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
117815  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
117816  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
117817  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
117818  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
117819  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
117820  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
117821  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
117822  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
117823  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
117824  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
117825  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
117826  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
117827 };
117828 
117834 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
117835 {
117836  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
117837  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
117838  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
117839  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
117840  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
117841  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
117842  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
117843  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
117844  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
117845  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
117846  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
117847  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
117848  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
117849  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
117850  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
117851  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
117852  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
117853  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
117854  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
117855  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
117856  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
117857  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
117858  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
117859  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
117860  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
117861  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
117862  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
117863  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
117864  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
117865  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
117866 };
117867 
117873 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
117874 {
117875  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
117876  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
117877  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
117878  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
117879  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
117880  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
117881  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
117882  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
117883 };
117884 
117890 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
117891 {
117892  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
117893  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
117894  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
117895  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
117896  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
117897  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
117898  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
117899  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
117900  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
117901  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
117902  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
117903  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
117904  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
117905  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
117906  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
117907  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
117908  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
117909  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
117910  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
117911  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
117912  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
117913  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
117914  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
117915  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
117916  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
117917  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
117918  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
117919  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
117920  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
117921  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
117922 };
117923 
117929 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
117930 {
117931  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
117932  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
117933  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
117934  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
117935  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
117936  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
117937  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
117938  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
117939 };
117940 
117946 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
117947 {
117948  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
117949  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
117950  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
117951  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
117952  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
117953  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
117954  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
117955  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
117956 };
117957 
117963 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
117964 {
117965  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
117966  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
117967  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
117968  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
117969  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
117970  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
117971  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
117972  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
117973  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
117974  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
117975  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
117976  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
117977  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
117978  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
117979  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
117980  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
117981  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
117982  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
117983  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
117984  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
117985  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
117986  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
117987  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
117988  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
117989  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
117990  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
117991  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
117992  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
117993  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
117994  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
117995  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
117996  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
117997  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
117998  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
117999  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
118000  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
118001  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
118002  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
118003  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
118004  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
118005  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
118006  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
118007  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
118008  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
118009  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
118010  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
118011  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
118012  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
118013  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
118014  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
118015  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
118016  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
118017  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
118018  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
118019  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
118020  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
118021  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
118022  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
118023  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
118024  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
118025  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
118026  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
118027  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
118028  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
118029  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
118030  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
118031  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
118032  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
118033  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
118034  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
118035  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
118036  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
118037  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
118038  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
118039  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
118040  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
118041  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
118042  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
118043  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
118044  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
118045  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
118046  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
118047  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
118048  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
118049 };
118050 
118056 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
118057 {
118058  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
118059  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
118060  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
118061  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
118062  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
118063  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
118064  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
118065  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
118066  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
118067  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
118068  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
118069  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
118070  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
118071  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
118072  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
118073  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
118074  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
118075  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
118076  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
118077  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
118078  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
118079  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
118080  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
118081  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
118082  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
118083  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
118084  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
118085  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
118086  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
118087  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
118088  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
118089  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
118090  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
118091  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
118092  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
118093  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
118094  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
118095  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
118096  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
118097  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
118098  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
118099  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
118100  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
118101  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
118102  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
118103  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
118104  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
118105  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
118106  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
118107  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
118108  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
118109  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
118110  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
118111  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
118112  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
118113  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
118114 };
118115 
118121 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
118122 {
118123  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
118124  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
118125  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
118126  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
118127  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
118128  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
118129  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
118130  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
118131  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
118132  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
118133  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
118134  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
118135  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
118136  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
118137  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
118138  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
118139  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
118140  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
118141  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
118142  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
118143  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
118144  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
118145  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
118146  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
118147  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
118148  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
118149  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
118150  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
118151  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
118152  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
118153  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
118154  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
118155  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
118156  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
118157  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
118158  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
118159  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
118160  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
118161  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
118162  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
118163  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
118164  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
118165  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
118166  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
118167  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
118168  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
118169  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
118170  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
118171  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
118172  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
118173  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
118174  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
118175  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
118176  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
118177  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
118178  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
118179  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
118180  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
118181  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
118182  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
118183  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
118184  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
118185  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
118186  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
118187  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
118188  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
118189  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
118190  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
118191  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
118192  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
118193  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
118194  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
118195  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
118196  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
118197  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
118198  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
118199  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
118200  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
118201  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
118202  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
118203  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
118204  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
118205  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
118206  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
118207 };
118208 
118214 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
118215 {
118216  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
118217  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
118218  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
118219  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
118220  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
118221  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
118222  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
118223  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
118224 };
118225 
118231 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
118232 {
118233  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
118234  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
118235  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
118236  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
118237  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
118238  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
118239  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
118240  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
118241  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
118242  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
118243  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
118244  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
118245  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
118246  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
118247  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
118248  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
118249  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
118250  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
118251  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
118252  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
118253  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
118254  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
118255  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
118256  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
118257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
118258  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
118259  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
118260  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
118261  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
118262  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
118263 };
118264 
118270 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
118271 {
118272  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
118273  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
118274  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
118275  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
118276  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
118277  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
118278  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
118279  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
118280  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
118281  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
118282  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
118283  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
118284  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
118285  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
118286  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
118287  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
118288  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
118289  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
118290  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
118291  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
118292  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
118293  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
118294  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
118295  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
118296  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
118297  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
118298  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
118299  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
118300  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
118301  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
118302  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
118303  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
118304  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
118305  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
118306  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
118307  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
118308  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
118309  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
118310  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
118311  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
118312  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
118313  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
118314  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
118315  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
118316  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
118317  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
118318  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
118319  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
118320  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
118321  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
118322  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
118323  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
118324  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
118325  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
118326  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
118327  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
118328  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
118329  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
118330  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
118331  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
118332  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
118333  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
118334  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
118335  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
118336  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
118337  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
118338  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
118339  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
118340  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
118341  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
118342  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
118343  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
118344  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
118345  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
118346  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
118347  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
118348  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
118349  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
118350  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
118351  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
118352  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
118353  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
118354  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
118355  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
118356  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
118357  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
118358  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
118359  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
118360  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
118361  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
118362  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
118363  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
118364  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
118365  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
118366  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
118367  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
118368  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
118369  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
118370  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
118371  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
118372  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
118373  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
118374  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
118375  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
118376  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
118377  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
118378  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
118379  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
118380  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
118381  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
118382  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
118383  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
118384  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
118385  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
118386  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
118387  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
118388  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
118389  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
118390  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
118391  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
118392  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
118393  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
118394  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
118395  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
118396  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
118397  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
118398  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
118399  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
118400  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
118401  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
118402  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
118403  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
118404  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
118405  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
118406  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
118407  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
118408  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
118409  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
118410  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
118411  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
118412  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
118413  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
118414  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
118415  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
118416  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
118417  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
118418  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
118419  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
118420  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
118421  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
118422  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
118423  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
118424  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
118425  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
118426  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
118427  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
118428  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
118429  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
118430  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
118431  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
118432  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
118433  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
118434  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
118435  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
118436  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
118437  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
118438  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
118439  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
118440  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
118441  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
118442  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
118443  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
118444  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
118445  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
118446  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
118447  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
118448  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
118449  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
118450  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
118451  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
118452  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
118453  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
118454  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
118455  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
118456  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
118457  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
118458  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
118459  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
118460  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
118461  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
118462  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
118463  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
118464  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
118465  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
118466  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
118467  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
118468  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
118469  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
118470  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
118471  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
118472  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
118473  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
118474  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
118475  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
118476  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
118477  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
118478  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
118479  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
118480  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
118481  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
118482  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
118483  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
118484  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
118485  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
118486  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
118487  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
118488  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
118489  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
118490  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
118491  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
118492  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
118493  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
118494  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
118495  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
118496  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
118497  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
118498  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
118499  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
118500  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
118501  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
118502  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
118503  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
118504  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
118505  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
118506  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
118507  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
118508  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
118509  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
118510  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
118511  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
118512  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
118513  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
118514  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
118515  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
118516  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
118517  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
118518  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
118519  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
118520  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
118521  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
118522  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
118523  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
118524  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
118525  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
118526  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
118527  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
118528  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
118529  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
118530  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
118531  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
118532  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
118533  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
118534  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
118535  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
118536  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
118537  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
118538  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
118539  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
118540  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
118541  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
118542  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
118543  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
118544  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
118545  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
118546  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
118547  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
118548  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
118549  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
118550  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
118551  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
118552  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
118553  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
118554  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
118555  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
118556  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
118557  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
118558  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
118559  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
118560  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
118561  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
118562  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
118563  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
118564  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
118565  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
118566  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
118567  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
118568  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
118569  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
118570  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
118571  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
118572  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
118573  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
118574  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
118575  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
118576  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
118577  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
118578  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
118579  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
118580  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
118581  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
118582  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
118583  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
118584  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
118585  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
118586  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
118587  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
118588  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
118589  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
118590  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
118591  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
118592  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
118593  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
118594  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
118595  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
118596  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
118597  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
118598  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
118599  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
118600  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
118601  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
118602  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
118603  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
118604  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
118605  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
118606  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
118607  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
118608  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
118609  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
118610  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
118611  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
118612  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
118613  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
118614  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
118615  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
118616  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
118617  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
118618  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
118619  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
118620  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
118621  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
118622  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
118623  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
118624  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
118625  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
118626  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
118627  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
118628  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
118629  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
118630  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
118631  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
118632  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
118633  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
118634  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
118635  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
118636  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
118637  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
118638  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
118639  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
118640  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
118641  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
118642  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
118643  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
118644  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
118645  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
118646  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
118647  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
118648  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
118649  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
118650  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
118651  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
118652  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
118653  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
118654  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
118655  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
118656  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
118657  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
118658  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
118659  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
118660  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
118661  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
118662  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
118663  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
118664  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
118665  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
118666  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
118667  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
118668  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
118669  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
118670  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
118671  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
118672  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
118673  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
118674  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
118675  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
118676  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
118677  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
118678  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
118679  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
118680  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
118681  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
118682  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
118683  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
118684  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
118685  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
118686  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
118687  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
118688  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
118689  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
118690  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
118691  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
118692  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
118693  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
118694  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
118695  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
118696  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
118697  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
118698  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
118699  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
118700  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
118701  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
118702  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
118703  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
118704  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
118705  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
118706  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
118707  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
118708  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
118709  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
118710  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
118711  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
118712  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
118713  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
118714  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
118715  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
118716  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
118717  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
118718  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
118719  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
118720  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
118721  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
118722  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
118723  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
118724  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
118725  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
118726  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
118727  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
118728  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
118729  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
118730  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
118731  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
118732  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
118733  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
118734  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
118735  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
118736  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
118737  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
118738  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
118739  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
118740  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
118741  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
118742  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
118743  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
118744  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
118745  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
118746  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
118747  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
118748  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
118749  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
118750  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
118751  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
118752  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
118753  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
118754  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
118755  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
118756  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
118757  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
118758  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
118759  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
118760  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
118761  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
118762  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
118763  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
118764  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
118765  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
118766  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
118767  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
118768  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
118769  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
118770  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
118771  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
118772  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
118773  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
118774  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
118775  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
118776  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
118777  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
118778  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
118779  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
118780  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
118781  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
118782  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
118783  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
118784 };
118785 
118791 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
118792 {
118793  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
118794  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
118795  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
118796  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
118797  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
118798  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
118799  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
118800  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
118801  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
118802  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
118803  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
118804  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
118805  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
118806  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
118807  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
118808  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
118809  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
118810  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
118811  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
118812  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
118813  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
118814  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
118815  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
118816  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
118817  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
118818  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
118819  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
118820  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
118821  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
118822  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
118823  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
118824  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
118825  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
118826  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
118827  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
118828  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
118829  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
118830  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
118831  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
118832  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
118833  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
118834  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
118835  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
118836  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
118837  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
118838  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
118839  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
118840  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
118841  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
118842  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
118843  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
118844  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
118845  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
118846  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
118847  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
118848  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
118849  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
118850  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
118851  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
118852  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
118853  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
118854  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
118855  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
118856  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
118857  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
118858  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
118859  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
118860  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
118861  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
118862  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
118863  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
118864  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
118865  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
118866  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
118867  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
118868  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
118869  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
118870  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
118871  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
118872  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
118873  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
118874  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
118875  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
118876  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
118877  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
118878  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
118879  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
118880  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
118881  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
118882  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
118883  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
118884  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
118885  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
118886  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
118887  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
118888  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
118889  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
118890  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
118891  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
118892  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
118893  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
118894  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
118895  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
118896  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
118897  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
118898  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
118899  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
118900  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
118901  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
118902  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
118903  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
118904  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
118905  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
118906  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
118907  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
118908  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
118909  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
118910  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
118911  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
118912  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
118913  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
118914  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
118915  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
118916  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
118917  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
118918  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
118919  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
118920  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
118921  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
118922  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
118923  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
118924  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
118925  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
118926  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
118927  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
118928  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
118929  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
118930  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
118931  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
118932  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
118933  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
118934  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
118935  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
118936  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
118937  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
118938  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
118939  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
118940  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
118941  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
118942  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
118943  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
118944  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
118945  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
118946  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
118947  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
118948  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
118949  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
118950  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
118951  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
118952  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
118953  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
118954  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
118955  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
118956  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
118957  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
118958  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
118959  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
118960  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
118961  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
118962  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
118963  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
118964  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
118965  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
118966  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
118967  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
118968  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
118969  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
118970  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
118971  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
118972  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
118973  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
118974  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
118975  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
118976  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
118977  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
118978  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
118979  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
118980  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
118981  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
118982  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
118983  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
118984  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
118985  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
118986  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
118987  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
118988  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
118989  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
118990  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
118991  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
118992  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
118993  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
118994  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
118995  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
118996  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
118997  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
118998  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
118999  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
119000  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
119001  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
119002  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
119003  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
119004  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
119005  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
119006  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
119007  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
119008  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
119009  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
119010  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
119011  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
119012  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
119013  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
119014  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
119015  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
119016  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
119017  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
119018  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
119019  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
119020  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
119021  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
119022  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
119023  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
119024  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
119025  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
119026  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
119027  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
119028  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
119029  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
119030  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
119031  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
119032  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
119033  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
119034  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
119035  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
119036  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
119037  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
119038  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
119039  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
119040  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
119041  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
119042  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
119043  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
119044  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
119045  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
119046  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
119047  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
119048  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
119049  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
119050  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
119051  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
119052  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
119053  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
119054  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
119055  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
119056  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
119057  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
119058  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
119059  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
119060  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
119061  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
119062  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
119063  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
119064  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
119065  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
119066  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
119067  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
119068  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
119069  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
119070  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
119071  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
119072  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
119073  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
119074  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
119075  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
119076  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
119077  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
119078  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
119079  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
119080  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
119081  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
119082  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
119083  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
119084  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
119085  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
119086  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
119087  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
119088  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
119089  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
119090  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
119091  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
119092  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
119093  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
119094  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
119095  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
119096  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
119097  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
119098  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
119099  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
119100  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
119101  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
119102  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
119103  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
119104  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
119105  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
119106  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
119107  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
119108  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
119109  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
119110  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
119111  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
119112  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
119113  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
119114  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
119115  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
119116  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
119117  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
119118  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
119119  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
119120  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
119121  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
119122  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
119123  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
119124  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
119125  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
119126  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
119127  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
119128  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
119129  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
119130  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
119131  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
119132  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
119133  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
119134  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
119135  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
119136  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
119137  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
119138  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
119139  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
119140  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
119141  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
119142  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
119143  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
119144  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
119145  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
119146  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
119147  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
119148  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
119149  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
119150  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
119151  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
119152  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
119153  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
119154  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
119155  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
119156  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
119157  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
119158  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
119159  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
119160  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
119161  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
119162  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
119163  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
119164  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
119165  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
119166  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
119167  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
119168  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
119169  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
119170  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
119171  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
119172  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
119173  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
119174  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
119175  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
119176  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
119177  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
119178  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
119179  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
119180  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
119181  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
119182  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
119183  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
119184  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
119185  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
119186  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
119187  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
119188  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
119189  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
119190  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
119191  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
119192  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
119193  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
119194  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
119195  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
119196  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
119197  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
119198  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
119199  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
119200  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
119201  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
119202  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
119203  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
119204  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
119205  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
119206  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
119207  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
119208  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
119209  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
119210  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
119211  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
119212  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
119213  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
119214  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
119215  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
119216  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
119217  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
119218  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
119219  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
119220  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
119221  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
119222  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
119223  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
119224  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
119225  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
119226  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
119227  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
119228  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
119229  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
119230  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
119231  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
119232  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
119233  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
119234  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
119235  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
119236  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
119237  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
119238  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
119239  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
119240  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
119241  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
119242  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
119243  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
119244  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
119245  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
119246  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
119247  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
119248  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
119249  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
119250  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
119251  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
119252  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
119253  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
119254  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
119255  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
119256  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
119257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
119258  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
119259  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
119260  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
119261  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
119262  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
119263  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
119264  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
119265  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
119266  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
119267  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
119268  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
119269  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
119270  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
119271  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
119272  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
119273  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
119274  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
119275  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
119276  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
119277  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
119278  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
119279  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
119280  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
119281  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
119282  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
119283  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
119284  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
119285  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
119286  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
119287  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
119288  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
119289  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
119290  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
119291  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
119292  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
119293  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
119294  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
119295  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
119296  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
119297  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
119298  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
119299  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
119300  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
119301  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
119302  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
119303  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
119304  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
119305 };
119306 
119312 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
119313 {
119314  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
119315  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
119316  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
119317  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
119318  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
119319  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
119320  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
119321  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
119322  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
119323  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
119324  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
119325  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
119326  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
119327  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
119328  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
119329  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
119330  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
119331  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
119332  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
119333  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
119334  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
119335  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
119336  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
119337  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
119338  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
119339  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
119340  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
119341  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
119342  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
119343  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
119344  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
119345  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
119346  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
119347  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
119348  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
119349  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
119350  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
119351  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
119352  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
119353  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
119354  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
119355  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
119356  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
119357  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
119358  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
119359  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
119360  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
119361  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
119362  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
119363  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
119364  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
119365  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
119366  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
119367  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
119368  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
119369  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
119370  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
119371  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
119372  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
119373  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
119374  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
119375  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
119376  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
119377  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
119378  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
119379  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
119380  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
119381  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
119382  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
119383  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
119384  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
119385  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
119386  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
119387  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
119388  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
119389  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
119390  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
119391  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
119392  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
119393  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
119394  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
119395  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
119396  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
119397  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
119398  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
119399  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
119400  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
119401  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
119402  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
119403  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
119404  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
119405  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
119406  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
119407  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
119408  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
119409  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
119410  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
119411  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
119412  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
119413  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
119414  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
119415  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
119416  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
119417  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
119418  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
119419  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
119420  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
119421  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
119422  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
119423  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
119424  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
119425  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
119426  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
119427  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
119428  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
119429  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
119430  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
119431  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
119432  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
119433  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
119434  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
119435  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
119436  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
119437  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
119438  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
119439  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
119440  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
119441  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
119442  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
119443  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
119444  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
119445  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
119446  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
119447  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
119448  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
119449  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
119450  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
119451  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
119452  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
119453  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
119454  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
119455  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
119456  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
119457  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
119458  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
119459  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
119460  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
119461  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
119462  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
119463  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
119464  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
119465  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
119466  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
119467  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
119468  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
119469  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
119470  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
119471  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
119472  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
119473  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
119474  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
119475  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
119476  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
119477  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
119478  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
119479  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
119480  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
119481  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
119482  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
119483  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
119484  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
119485  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
119486  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
119487  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
119488  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
119489  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
119490  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
119491  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
119492  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
119493  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
119494  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
119495  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
119496  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
119497  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
119498  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
119499  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
119500  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
119501  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
119502  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
119503  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
119504  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
119505  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
119506  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
119507  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
119508  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
119509  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
119510  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
119511  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
119512  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
119513  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
119514  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
119515  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
119516  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
119517  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
119518  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
119519  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
119520  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
119521  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
119522  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
119523  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
119524  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
119525  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
119526  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
119527  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
119528  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
119529  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
119530  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
119531  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
119532  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
119533  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
119534  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
119535  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
119536  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
119537  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
119538  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
119539  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
119540  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
119541  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
119542  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
119543  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
119544  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
119545  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
119546  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
119547  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
119548  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
119549  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
119550  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
119551  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
119552  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
119553  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
119554  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
119555  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
119556  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
119557  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
119558  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
119559  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
119560  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
119561  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
119562  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
119563  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
119564  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
119565  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
119566  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
119567  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
119568  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
119569  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
119570  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
119571  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
119572  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
119573  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
119574  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
119575  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
119576  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
119577  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
119578  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
119579  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
119580  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
119581  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
119582  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
119583  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
119584  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
119585  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
119586  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
119587  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
119588  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
119589  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
119590  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
119591  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
119592  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
119593  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
119594  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
119595  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
119596  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
119597  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
119598  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
119599  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
119600  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
119601  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
119602  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
119603  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
119604  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
119605  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
119606  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
119607  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
119608  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
119609  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
119610  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
119611  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
119612  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
119613  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
119614  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
119615  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
119616  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
119617  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
119618  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
119619  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
119620  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
119621  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
119622  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
119623  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
119624  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
119625  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
119626  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
119627  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
119628  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
119629  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
119630  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
119631  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
119632  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
119633  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
119634  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
119635  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
119636  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
119637  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
119638  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
119639  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
119640  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
119641  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
119642  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
119643  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
119644  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
119645  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
119646  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
119647  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
119648  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
119649  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
119650  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
119651  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
119652  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
119653  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
119654  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
119655  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
119656  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
119657  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
119658  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
119659  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
119660  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
119661  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
119662  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
119663  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
119664  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
119665  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
119666  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
119667  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
119668  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
119669  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
119670  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
119671  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
119672  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
119673  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
119674  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
119675  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
119676  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
119677  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
119678  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
119679  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
119680  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
119681  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
119682  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
119683  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
119684  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
119685  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
119686  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
119687  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
119688  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_187_CHECKER_TYPE,
119689  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_187_WIDTH },
119690  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_188_CHECKER_TYPE,
119691  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_188_WIDTH },
119692  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_189_CHECKER_TYPE,
119693  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_189_WIDTH },
119694  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_190_CHECKER_TYPE,
119695  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_190_WIDTH },
119696  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_191_CHECKER_TYPE,
119697  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_191_WIDTH },
119698  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_192_CHECKER_TYPE,
119699  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_192_WIDTH },
119700  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_193_CHECKER_TYPE,
119701  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_193_WIDTH },
119702  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_194_CHECKER_TYPE,
119703  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_194_WIDTH },
119704  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_195_CHECKER_TYPE,
119705  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_195_WIDTH },
119706  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_196_CHECKER_TYPE,
119707  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_196_WIDTH },
119708  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_197_CHECKER_TYPE,
119709  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_197_WIDTH },
119710  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_198_CHECKER_TYPE,
119711  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_198_WIDTH },
119712  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_199_CHECKER_TYPE,
119713  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_199_WIDTH },
119714  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_200_CHECKER_TYPE,
119715  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_200_WIDTH },
119716  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_201_CHECKER_TYPE,
119717  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_201_WIDTH },
119718  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_202_CHECKER_TYPE,
119719  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_202_WIDTH },
119720  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_203_CHECKER_TYPE,
119721  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_203_WIDTH },
119722  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_204_CHECKER_TYPE,
119723  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_204_WIDTH },
119724  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_205_CHECKER_TYPE,
119725  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_205_WIDTH },
119726  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_206_CHECKER_TYPE,
119727  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_206_WIDTH },
119728  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_207_CHECKER_TYPE,
119729  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_207_WIDTH },
119730  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_208_CHECKER_TYPE,
119731  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_208_WIDTH },
119732  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_209_CHECKER_TYPE,
119733  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_209_WIDTH },
119734  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_210_CHECKER_TYPE,
119735  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_210_WIDTH },
119736  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_211_CHECKER_TYPE,
119737  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_211_WIDTH },
119738  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_212_CHECKER_TYPE,
119739  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_212_WIDTH },
119740  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_213_CHECKER_TYPE,
119741  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_213_WIDTH },
119742  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_214_CHECKER_TYPE,
119743  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_214_WIDTH },
119744  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_215_CHECKER_TYPE,
119745  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_215_WIDTH },
119746  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_216_CHECKER_TYPE,
119747  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_216_WIDTH },
119748  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_217_CHECKER_TYPE,
119749  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_217_WIDTH },
119750  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_218_CHECKER_TYPE,
119751  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_218_WIDTH },
119752  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_219_CHECKER_TYPE,
119753  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_219_WIDTH },
119754  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_220_CHECKER_TYPE,
119755  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_220_WIDTH },
119756  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_221_CHECKER_TYPE,
119757  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_221_WIDTH },
119758  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_222_CHECKER_TYPE,
119759  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_222_WIDTH },
119760  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_223_CHECKER_TYPE,
119761  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_223_WIDTH },
119762  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_224_CHECKER_TYPE,
119763  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_224_WIDTH },
119764  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_225_CHECKER_TYPE,
119765  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_225_WIDTH },
119766  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_226_CHECKER_TYPE,
119767  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_226_WIDTH },
119768  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_227_CHECKER_TYPE,
119769  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_227_WIDTH },
119770  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_228_CHECKER_TYPE,
119771  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_228_WIDTH },
119772  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_229_CHECKER_TYPE,
119773  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_229_WIDTH },
119774  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_230_CHECKER_TYPE,
119775  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_230_WIDTH },
119776  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_231_CHECKER_TYPE,
119777  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_231_WIDTH },
119778  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_232_CHECKER_TYPE,
119779  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_232_WIDTH },
119780  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_233_CHECKER_TYPE,
119781  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_233_WIDTH },
119782  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_234_CHECKER_TYPE,
119783  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_234_WIDTH },
119784  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_235_CHECKER_TYPE,
119785  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_235_WIDTH },
119786  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_236_CHECKER_TYPE,
119787  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_236_WIDTH },
119788  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_237_CHECKER_TYPE,
119789  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_237_WIDTH },
119790  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_238_CHECKER_TYPE,
119791  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_238_WIDTH },
119792  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_239_CHECKER_TYPE,
119793  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_239_WIDTH },
119794  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_240_CHECKER_TYPE,
119795  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_240_WIDTH },
119796  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_241_CHECKER_TYPE,
119797  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_241_WIDTH },
119798  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_242_CHECKER_TYPE,
119799  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_242_WIDTH },
119800  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_243_CHECKER_TYPE,
119801  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_243_WIDTH },
119802  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_244_CHECKER_TYPE,
119803  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_244_WIDTH },
119804  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_245_CHECKER_TYPE,
119805  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_245_WIDTH },
119806  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_246_CHECKER_TYPE,
119807  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_246_WIDTH },
119808  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_247_CHECKER_TYPE,
119809  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_247_WIDTH },
119810  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_248_CHECKER_TYPE,
119811  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_248_WIDTH },
119812  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_249_CHECKER_TYPE,
119813  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_249_WIDTH },
119814  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_250_CHECKER_TYPE,
119815  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_250_WIDTH },
119816  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_251_CHECKER_TYPE,
119817  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_251_WIDTH },
119818  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_252_CHECKER_TYPE,
119819  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_252_WIDTH },
119820  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_253_CHECKER_TYPE,
119821  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_253_WIDTH },
119822  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_254_CHECKER_TYPE,
119823  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_254_WIDTH },
119824  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_255_CHECKER_TYPE,
119825  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_GROUP_255_WIDTH },
119826 };
119827 
119833 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS] =
119834 {
119835  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_0_CHECKER_TYPE,
119836  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_0_WIDTH },
119837  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_1_CHECKER_TYPE,
119838  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_1_WIDTH },
119839  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_2_CHECKER_TYPE,
119840  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_2_WIDTH },
119841  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_3_CHECKER_TYPE,
119842  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_3_WIDTH },
119843  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_4_CHECKER_TYPE,
119844  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_4_WIDTH },
119845  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_5_CHECKER_TYPE,
119846  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_5_WIDTH },
119847  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_6_CHECKER_TYPE,
119848  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_6_WIDTH },
119849  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_7_CHECKER_TYPE,
119850  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_7_WIDTH },
119851  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_8_CHECKER_TYPE,
119852  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_8_WIDTH },
119853  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_9_CHECKER_TYPE,
119854  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_9_WIDTH },
119855  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_10_CHECKER_TYPE,
119856  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_10_WIDTH },
119857  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_11_CHECKER_TYPE,
119858  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_11_WIDTH },
119859  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_12_CHECKER_TYPE,
119860  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_12_WIDTH },
119861  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_13_CHECKER_TYPE,
119862  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_13_WIDTH },
119863  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_14_CHECKER_TYPE,
119864  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_14_WIDTH },
119865  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_15_CHECKER_TYPE,
119866  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_15_WIDTH },
119867  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_16_CHECKER_TYPE,
119868  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_16_WIDTH },
119869  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_17_CHECKER_TYPE,
119870  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_17_WIDTH },
119871  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_18_CHECKER_TYPE,
119872  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_18_WIDTH },
119873  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_19_CHECKER_TYPE,
119874  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_19_WIDTH },
119875  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_20_CHECKER_TYPE,
119876  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_20_WIDTH },
119877  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_21_CHECKER_TYPE,
119878  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_21_WIDTH },
119879  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_22_CHECKER_TYPE,
119880  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_22_WIDTH },
119881  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_23_CHECKER_TYPE,
119882  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_23_WIDTH },
119883  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_24_CHECKER_TYPE,
119884  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_24_WIDTH },
119885  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_25_CHECKER_TYPE,
119886  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_25_WIDTH },
119887  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_26_CHECKER_TYPE,
119888  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_26_WIDTH },
119889  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_27_CHECKER_TYPE,
119890  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_27_WIDTH },
119891  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_28_CHECKER_TYPE,
119892  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_28_WIDTH },
119893  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_29_CHECKER_TYPE,
119894  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_29_WIDTH },
119895  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_30_CHECKER_TYPE,
119896  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_30_WIDTH },
119897  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_31_CHECKER_TYPE,
119898  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_31_WIDTH },
119899  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_32_CHECKER_TYPE,
119900  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_32_WIDTH },
119901  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_33_CHECKER_TYPE,
119902  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_33_WIDTH },
119903  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_34_CHECKER_TYPE,
119904  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_34_WIDTH },
119905  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_35_CHECKER_TYPE,
119906  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_35_WIDTH },
119907  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_36_CHECKER_TYPE,
119908  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_36_WIDTH },
119909  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_37_CHECKER_TYPE,
119910  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_37_WIDTH },
119911  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_38_CHECKER_TYPE,
119912  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_38_WIDTH },
119913  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_39_CHECKER_TYPE,
119914  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_39_WIDTH },
119915  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_40_CHECKER_TYPE,
119916  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_40_WIDTH },
119917  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_41_CHECKER_TYPE,
119918  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_41_WIDTH },
119919  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_42_CHECKER_TYPE,
119920  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_42_WIDTH },
119921  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_43_CHECKER_TYPE,
119922  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_43_WIDTH },
119923  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_44_CHECKER_TYPE,
119924  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_44_WIDTH },
119925  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_45_CHECKER_TYPE,
119926  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_45_WIDTH },
119927  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_46_CHECKER_TYPE,
119928  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_46_WIDTH },
119929  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_47_CHECKER_TYPE,
119930  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_47_WIDTH },
119931  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_48_CHECKER_TYPE,
119932  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_48_WIDTH },
119933  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_49_CHECKER_TYPE,
119934  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_49_WIDTH },
119935  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_50_CHECKER_TYPE,
119936  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_50_WIDTH },
119937  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_51_CHECKER_TYPE,
119938  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_51_WIDTH },
119939  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_52_CHECKER_TYPE,
119940  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_52_WIDTH },
119941  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_53_CHECKER_TYPE,
119942  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_53_WIDTH },
119943  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_54_CHECKER_TYPE,
119944  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_54_WIDTH },
119945  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_55_CHECKER_TYPE,
119946  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_55_WIDTH },
119947  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_56_CHECKER_TYPE,
119948  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_56_WIDTH },
119949  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_57_CHECKER_TYPE,
119950  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_57_WIDTH },
119951  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_58_CHECKER_TYPE,
119952  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_58_WIDTH },
119953  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_59_CHECKER_TYPE,
119954  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_59_WIDTH },
119955  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_60_CHECKER_TYPE,
119956  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_60_WIDTH },
119957  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_61_CHECKER_TYPE,
119958  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_61_WIDTH },
119959  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_62_CHECKER_TYPE,
119960  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_62_WIDTH },
119961  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_63_CHECKER_TYPE,
119962  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_63_WIDTH },
119963  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_64_CHECKER_TYPE,
119964  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_64_WIDTH },
119965  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_65_CHECKER_TYPE,
119966  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_65_WIDTH },
119967  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_66_CHECKER_TYPE,
119968  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_66_WIDTH },
119969  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_67_CHECKER_TYPE,
119970  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_67_WIDTH },
119971  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_68_CHECKER_TYPE,
119972  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_68_WIDTH },
119973  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_69_CHECKER_TYPE,
119974  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_69_WIDTH },
119975  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_70_CHECKER_TYPE,
119976  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_70_WIDTH },
119977  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_71_CHECKER_TYPE,
119978  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_71_WIDTH },
119979  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_72_CHECKER_TYPE,
119980  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_72_WIDTH },
119981  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_73_CHECKER_TYPE,
119982  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_73_WIDTH },
119983  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_74_CHECKER_TYPE,
119984  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_74_WIDTH },
119985  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_75_CHECKER_TYPE,
119986  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_75_WIDTH },
119987  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_76_CHECKER_TYPE,
119988  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_76_WIDTH },
119989  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_77_CHECKER_TYPE,
119990  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_77_WIDTH },
119991  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_78_CHECKER_TYPE,
119992  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_78_WIDTH },
119993  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_79_CHECKER_TYPE,
119994  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_79_WIDTH },
119995  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_80_CHECKER_TYPE,
119996  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_80_WIDTH },
119997  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_81_CHECKER_TYPE,
119998  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_81_WIDTH },
119999  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_82_CHECKER_TYPE,
120000  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_82_WIDTH },
120001  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_83_CHECKER_TYPE,
120002  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_83_WIDTH },
120003  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_84_CHECKER_TYPE,
120004  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_84_WIDTH },
120005  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_85_CHECKER_TYPE,
120006  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_85_WIDTH },
120007  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_86_CHECKER_TYPE,
120008  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_86_WIDTH },
120009  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_87_CHECKER_TYPE,
120010  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_87_WIDTH },
120011  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_88_CHECKER_TYPE,
120012  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_88_WIDTH },
120013  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_89_CHECKER_TYPE,
120014  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_89_WIDTH },
120015  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_90_CHECKER_TYPE,
120016  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_90_WIDTH },
120017  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_91_CHECKER_TYPE,
120018  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_91_WIDTH },
120019  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_92_CHECKER_TYPE,
120020  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_92_WIDTH },
120021  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_93_CHECKER_TYPE,
120022  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_93_WIDTH },
120023  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_94_CHECKER_TYPE,
120024  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_94_WIDTH },
120025  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_95_CHECKER_TYPE,
120026  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_95_WIDTH },
120027  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_96_CHECKER_TYPE,
120028  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_96_WIDTH },
120029  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_97_CHECKER_TYPE,
120030  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_97_WIDTH },
120031  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_98_CHECKER_TYPE,
120032  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_98_WIDTH },
120033  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_99_CHECKER_TYPE,
120034  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_99_WIDTH },
120035  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_100_CHECKER_TYPE,
120036  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_100_WIDTH },
120037  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_101_CHECKER_TYPE,
120038  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_101_WIDTH },
120039  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_102_CHECKER_TYPE,
120040  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_102_WIDTH },
120041  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_103_CHECKER_TYPE,
120042  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_103_WIDTH },
120043  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_104_CHECKER_TYPE,
120044  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_104_WIDTH },
120045  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_105_CHECKER_TYPE,
120046  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_105_WIDTH },
120047  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_106_CHECKER_TYPE,
120048  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_106_WIDTH },
120049  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_107_CHECKER_TYPE,
120050  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_107_WIDTH },
120051  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_108_CHECKER_TYPE,
120052  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_108_WIDTH },
120053  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_109_CHECKER_TYPE,
120054  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_109_WIDTH },
120055  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_110_CHECKER_TYPE,
120056  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_110_WIDTH },
120057  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_111_CHECKER_TYPE,
120058  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_111_WIDTH },
120059  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_112_CHECKER_TYPE,
120060  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_112_WIDTH },
120061  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_113_CHECKER_TYPE,
120062  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_113_WIDTH },
120063  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_114_CHECKER_TYPE,
120064  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_114_WIDTH },
120065  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_115_CHECKER_TYPE,
120066  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_115_WIDTH },
120067  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_116_CHECKER_TYPE,
120068  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_116_WIDTH },
120069  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_117_CHECKER_TYPE,
120070  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_117_WIDTH },
120071  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_118_CHECKER_TYPE,
120072  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_118_WIDTH },
120073  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_119_CHECKER_TYPE,
120074  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_119_WIDTH },
120075  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_120_CHECKER_TYPE,
120076  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_120_WIDTH },
120077  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_121_CHECKER_TYPE,
120078  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_121_WIDTH },
120079  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_122_CHECKER_TYPE,
120080  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_122_WIDTH },
120081  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_123_CHECKER_TYPE,
120082  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_123_WIDTH },
120083  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_124_CHECKER_TYPE,
120084  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_124_WIDTH },
120085  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_125_CHECKER_TYPE,
120086  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_125_WIDTH },
120087  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_126_CHECKER_TYPE,
120088  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_126_WIDTH },
120089  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_127_CHECKER_TYPE,
120090  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_127_WIDTH },
120091  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_128_CHECKER_TYPE,
120092  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_128_WIDTH },
120093  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_129_CHECKER_TYPE,
120094  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_129_WIDTH },
120095  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_130_CHECKER_TYPE,
120096  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_130_WIDTH },
120097  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_131_CHECKER_TYPE,
120098  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_131_WIDTH },
120099  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_132_CHECKER_TYPE,
120100  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_132_WIDTH },
120101  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_133_CHECKER_TYPE,
120102  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_133_WIDTH },
120103  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_134_CHECKER_TYPE,
120104  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_134_WIDTH },
120105  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_135_CHECKER_TYPE,
120106  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_135_WIDTH },
120107  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_136_CHECKER_TYPE,
120108  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_136_WIDTH },
120109  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_137_CHECKER_TYPE,
120110  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_137_WIDTH },
120111  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_138_CHECKER_TYPE,
120112  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_138_WIDTH },
120113  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_139_CHECKER_TYPE,
120114  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_139_WIDTH },
120115  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_140_CHECKER_TYPE,
120116  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_140_WIDTH },
120117  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_141_CHECKER_TYPE,
120118  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_141_WIDTH },
120119  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_142_CHECKER_TYPE,
120120  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_142_WIDTH },
120121  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_143_CHECKER_TYPE,
120122  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_143_WIDTH },
120123  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_144_CHECKER_TYPE,
120124  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_144_WIDTH },
120125  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_145_CHECKER_TYPE,
120126  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_145_WIDTH },
120127  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_146_CHECKER_TYPE,
120128  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_146_WIDTH },
120129  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_147_CHECKER_TYPE,
120130  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_147_WIDTH },
120131  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_148_CHECKER_TYPE,
120132  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_148_WIDTH },
120133  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_149_CHECKER_TYPE,
120134  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_149_WIDTH },
120135  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_150_CHECKER_TYPE,
120136  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_150_WIDTH },
120137  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_151_CHECKER_TYPE,
120138  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_151_WIDTH },
120139  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_152_CHECKER_TYPE,
120140  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_152_WIDTH },
120141  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_153_CHECKER_TYPE,
120142  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_153_WIDTH },
120143  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_154_CHECKER_TYPE,
120144  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_154_WIDTH },
120145  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_155_CHECKER_TYPE,
120146  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_155_WIDTH },
120147  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_156_CHECKER_TYPE,
120148  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_156_WIDTH },
120149  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_157_CHECKER_TYPE,
120150  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_157_WIDTH },
120151  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_158_CHECKER_TYPE,
120152  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_158_WIDTH },
120153  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_159_CHECKER_TYPE,
120154  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_159_WIDTH },
120155  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_160_CHECKER_TYPE,
120156  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_160_WIDTH },
120157  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_161_CHECKER_TYPE,
120158  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_161_WIDTH },
120159  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_162_CHECKER_TYPE,
120160  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_162_WIDTH },
120161  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_163_CHECKER_TYPE,
120162  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_163_WIDTH },
120163  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_164_CHECKER_TYPE,
120164  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_164_WIDTH },
120165  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_165_CHECKER_TYPE,
120166  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_165_WIDTH },
120167  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_166_CHECKER_TYPE,
120168  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_166_WIDTH },
120169  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_167_CHECKER_TYPE,
120170  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_167_WIDTH },
120171  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_168_CHECKER_TYPE,
120172  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_168_WIDTH },
120173  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_169_CHECKER_TYPE,
120174  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_169_WIDTH },
120175  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_170_CHECKER_TYPE,
120176  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_170_WIDTH },
120177  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_171_CHECKER_TYPE,
120178  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_171_WIDTH },
120179  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_172_CHECKER_TYPE,
120180  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_172_WIDTH },
120181  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_173_CHECKER_TYPE,
120182  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_173_WIDTH },
120183  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_174_CHECKER_TYPE,
120184  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_174_WIDTH },
120185  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_175_CHECKER_TYPE,
120186  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_175_WIDTH },
120187  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_176_CHECKER_TYPE,
120188  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_176_WIDTH },
120189  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_177_CHECKER_TYPE,
120190  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_177_WIDTH },
120191  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_178_CHECKER_TYPE,
120192  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_178_WIDTH },
120193  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_179_CHECKER_TYPE,
120194  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_179_WIDTH },
120195  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_180_CHECKER_TYPE,
120196  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_180_WIDTH },
120197  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_181_CHECKER_TYPE,
120198  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_181_WIDTH },
120199  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_182_CHECKER_TYPE,
120200  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_182_WIDTH },
120201  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_183_CHECKER_TYPE,
120202  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_183_WIDTH },
120203  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_184_CHECKER_TYPE,
120204  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_184_WIDTH },
120205  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_185_CHECKER_TYPE,
120206  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_185_WIDTH },
120207  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_186_CHECKER_TYPE,
120208  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_186_WIDTH },
120209  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_187_CHECKER_TYPE,
120210  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_187_WIDTH },
120211  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_188_CHECKER_TYPE,
120212  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_188_WIDTH },
120213  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_189_CHECKER_TYPE,
120214  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_189_WIDTH },
120215  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_190_CHECKER_TYPE,
120216  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_190_WIDTH },
120217  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_191_CHECKER_TYPE,
120218  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_191_WIDTH },
120219  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_192_CHECKER_TYPE,
120220  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_192_WIDTH },
120221  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_193_CHECKER_TYPE,
120222  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_193_WIDTH },
120223  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_194_CHECKER_TYPE,
120224  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_194_WIDTH },
120225  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_195_CHECKER_TYPE,
120226  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_195_WIDTH },
120227  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_196_CHECKER_TYPE,
120228  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_196_WIDTH },
120229  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_197_CHECKER_TYPE,
120230  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_197_WIDTH },
120231  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_198_CHECKER_TYPE,
120232  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_198_WIDTH },
120233  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_199_CHECKER_TYPE,
120234  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_199_WIDTH },
120235  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_200_CHECKER_TYPE,
120236  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_200_WIDTH },
120237  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_201_CHECKER_TYPE,
120238  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_201_WIDTH },
120239  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_202_CHECKER_TYPE,
120240  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_202_WIDTH },
120241  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_203_CHECKER_TYPE,
120242  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_203_WIDTH },
120243  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_204_CHECKER_TYPE,
120244  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_204_WIDTH },
120245  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_205_CHECKER_TYPE,
120246  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_205_WIDTH },
120247  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_206_CHECKER_TYPE,
120248  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_206_WIDTH },
120249  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_207_CHECKER_TYPE,
120250  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_207_WIDTH },
120251  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_208_CHECKER_TYPE,
120252  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_208_WIDTH },
120253  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_209_CHECKER_TYPE,
120254  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_209_WIDTH },
120255  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_210_CHECKER_TYPE,
120256  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_210_WIDTH },
120257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_211_CHECKER_TYPE,
120258  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_211_WIDTH },
120259  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_212_CHECKER_TYPE,
120260  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_212_WIDTH },
120261  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_213_CHECKER_TYPE,
120262  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_213_WIDTH },
120263  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_214_CHECKER_TYPE,
120264  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_214_WIDTH },
120265  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_215_CHECKER_TYPE,
120266  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_215_WIDTH },
120267  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_216_CHECKER_TYPE,
120268  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_216_WIDTH },
120269  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_217_CHECKER_TYPE,
120270  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_217_WIDTH },
120271  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_218_CHECKER_TYPE,
120272  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_218_WIDTH },
120273  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_219_CHECKER_TYPE,
120274  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_219_WIDTH },
120275  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_220_CHECKER_TYPE,
120276  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_220_WIDTH },
120277  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_221_CHECKER_TYPE,
120278  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_221_WIDTH },
120279  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_222_CHECKER_TYPE,
120280  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_222_WIDTH },
120281  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_223_CHECKER_TYPE,
120282  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_223_WIDTH },
120283  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_224_CHECKER_TYPE,
120284  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_224_WIDTH },
120285  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_225_CHECKER_TYPE,
120286  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_225_WIDTH },
120287  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_226_CHECKER_TYPE,
120288  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_226_WIDTH },
120289  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_227_CHECKER_TYPE,
120290  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_227_WIDTH },
120291  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_228_CHECKER_TYPE,
120292  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_228_WIDTH },
120293  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_229_CHECKER_TYPE,
120294  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_229_WIDTH },
120295  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_230_CHECKER_TYPE,
120296  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_230_WIDTH },
120297  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_231_CHECKER_TYPE,
120298  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_231_WIDTH },
120299  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_232_CHECKER_TYPE,
120300  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_232_WIDTH },
120301  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_233_CHECKER_TYPE,
120302  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_233_WIDTH },
120303  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_234_CHECKER_TYPE,
120304  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_234_WIDTH },
120305  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_235_CHECKER_TYPE,
120306  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_235_WIDTH },
120307  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_236_CHECKER_TYPE,
120308  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_236_WIDTH },
120309  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_237_CHECKER_TYPE,
120310  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_237_WIDTH },
120311  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_238_CHECKER_TYPE,
120312  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_238_WIDTH },
120313  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_239_CHECKER_TYPE,
120314  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_239_WIDTH },
120315  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_240_CHECKER_TYPE,
120316  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_240_WIDTH },
120317  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_241_CHECKER_TYPE,
120318  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_241_WIDTH },
120319  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_242_CHECKER_TYPE,
120320  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_242_WIDTH },
120321  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_243_CHECKER_TYPE,
120322  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_243_WIDTH },
120323  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_244_CHECKER_TYPE,
120324  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_244_WIDTH },
120325  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_245_CHECKER_TYPE,
120326  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_245_WIDTH },
120327  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_246_CHECKER_TYPE,
120328  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_246_WIDTH },
120329  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_247_CHECKER_TYPE,
120330  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_247_WIDTH },
120331  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_248_CHECKER_TYPE,
120332  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_248_WIDTH },
120333  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_249_CHECKER_TYPE,
120334  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_249_WIDTH },
120335  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_250_CHECKER_TYPE,
120336  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_250_WIDTH },
120337  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_251_CHECKER_TYPE,
120338  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_251_WIDTH },
120339  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_252_CHECKER_TYPE,
120340  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_252_WIDTH },
120341  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_253_CHECKER_TYPE,
120342  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_253_WIDTH },
120343  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_254_CHECKER_TYPE,
120344  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_254_WIDTH },
120345  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_255_CHECKER_TYPE,
120346  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_GROUP_255_WIDTH },
120347 };
120348 
120354 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS] =
120355 {
120356  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_0_CHECKER_TYPE,
120357  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_0_WIDTH },
120358  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_1_CHECKER_TYPE,
120359  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_1_WIDTH },
120360  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_2_CHECKER_TYPE,
120361  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_2_WIDTH },
120362  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_3_CHECKER_TYPE,
120363  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_3_WIDTH },
120364  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_4_CHECKER_TYPE,
120365  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_4_WIDTH },
120366  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_5_CHECKER_TYPE,
120367  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_5_WIDTH },
120368  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_6_CHECKER_TYPE,
120369  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_6_WIDTH },
120370  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_7_CHECKER_TYPE,
120371  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_7_WIDTH },
120372  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_8_CHECKER_TYPE,
120373  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_8_WIDTH },
120374  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_9_CHECKER_TYPE,
120375  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_9_WIDTH },
120376  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_10_CHECKER_TYPE,
120377  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_10_WIDTH },
120378  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_11_CHECKER_TYPE,
120379  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_11_WIDTH },
120380  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_12_CHECKER_TYPE,
120381  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_12_WIDTH },
120382  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_13_CHECKER_TYPE,
120383  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_13_WIDTH },
120384  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_14_CHECKER_TYPE,
120385  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_14_WIDTH },
120386  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_15_CHECKER_TYPE,
120387  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_15_WIDTH },
120388  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_16_CHECKER_TYPE,
120389  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_16_WIDTH },
120390  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_17_CHECKER_TYPE,
120391  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_17_WIDTH },
120392  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_18_CHECKER_TYPE,
120393  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_18_WIDTH },
120394  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_19_CHECKER_TYPE,
120395  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_19_WIDTH },
120396  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_20_CHECKER_TYPE,
120397  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_20_WIDTH },
120398  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_21_CHECKER_TYPE,
120399  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_21_WIDTH },
120400  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_22_CHECKER_TYPE,
120401  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_22_WIDTH },
120402  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_23_CHECKER_TYPE,
120403  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_23_WIDTH },
120404  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_24_CHECKER_TYPE,
120405  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_24_WIDTH },
120406  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_25_CHECKER_TYPE,
120407  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_25_WIDTH },
120408  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_26_CHECKER_TYPE,
120409  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_26_WIDTH },
120410  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_27_CHECKER_TYPE,
120411  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_27_WIDTH },
120412  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_28_CHECKER_TYPE,
120413  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_28_WIDTH },
120414  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_29_CHECKER_TYPE,
120415  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_29_WIDTH },
120416  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_30_CHECKER_TYPE,
120417  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_30_WIDTH },
120418  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_31_CHECKER_TYPE,
120419  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_31_WIDTH },
120420  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_32_CHECKER_TYPE,
120421  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_32_WIDTH },
120422  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_33_CHECKER_TYPE,
120423  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_33_WIDTH },
120424  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_34_CHECKER_TYPE,
120425  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_34_WIDTH },
120426  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_35_CHECKER_TYPE,
120427  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_35_WIDTH },
120428  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_36_CHECKER_TYPE,
120429  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_36_WIDTH },
120430  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_37_CHECKER_TYPE,
120431  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_37_WIDTH },
120432  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_38_CHECKER_TYPE,
120433  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_38_WIDTH },
120434  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_39_CHECKER_TYPE,
120435  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_39_WIDTH },
120436  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_40_CHECKER_TYPE,
120437  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_40_WIDTH },
120438  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_41_CHECKER_TYPE,
120439  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_41_WIDTH },
120440  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_42_CHECKER_TYPE,
120441  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_42_WIDTH },
120442  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_43_CHECKER_TYPE,
120443  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_43_WIDTH },
120444  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_44_CHECKER_TYPE,
120445  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_44_WIDTH },
120446  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_45_CHECKER_TYPE,
120447  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_45_WIDTH },
120448  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_46_CHECKER_TYPE,
120449  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_46_WIDTH },
120450  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_47_CHECKER_TYPE,
120451  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_47_WIDTH },
120452  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_48_CHECKER_TYPE,
120453  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_48_WIDTH },
120454  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_49_CHECKER_TYPE,
120455  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_49_WIDTH },
120456  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_50_CHECKER_TYPE,
120457  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_50_WIDTH },
120458  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_51_CHECKER_TYPE,
120459  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_51_WIDTH },
120460  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_52_CHECKER_TYPE,
120461  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_52_WIDTH },
120462  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_53_CHECKER_TYPE,
120463  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_53_WIDTH },
120464  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_54_CHECKER_TYPE,
120465  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_54_WIDTH },
120466  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_55_CHECKER_TYPE,
120467  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_55_WIDTH },
120468  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_56_CHECKER_TYPE,
120469  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_56_WIDTH },
120470  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_57_CHECKER_TYPE,
120471  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_57_WIDTH },
120472  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_58_CHECKER_TYPE,
120473  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_58_WIDTH },
120474  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_59_CHECKER_TYPE,
120475  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_59_WIDTH },
120476  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_60_CHECKER_TYPE,
120477  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_60_WIDTH },
120478  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_61_CHECKER_TYPE,
120479  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_61_WIDTH },
120480  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_62_CHECKER_TYPE,
120481  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_62_WIDTH },
120482  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_63_CHECKER_TYPE,
120483  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_63_WIDTH },
120484  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_64_CHECKER_TYPE,
120485  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_64_WIDTH },
120486  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_65_CHECKER_TYPE,
120487  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_65_WIDTH },
120488  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_66_CHECKER_TYPE,
120489  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_66_WIDTH },
120490  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_67_CHECKER_TYPE,
120491  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_67_WIDTH },
120492  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_68_CHECKER_TYPE,
120493  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_68_WIDTH },
120494  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_69_CHECKER_TYPE,
120495  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_69_WIDTH },
120496  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_70_CHECKER_TYPE,
120497  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_70_WIDTH },
120498  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_71_CHECKER_TYPE,
120499  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_71_WIDTH },
120500  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_72_CHECKER_TYPE,
120501  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_72_WIDTH },
120502  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_73_CHECKER_TYPE,
120503  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_73_WIDTH },
120504  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_74_CHECKER_TYPE,
120505  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_74_WIDTH },
120506  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_75_CHECKER_TYPE,
120507  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_75_WIDTH },
120508  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_76_CHECKER_TYPE,
120509  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_76_WIDTH },
120510  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_77_CHECKER_TYPE,
120511  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_77_WIDTH },
120512  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_78_CHECKER_TYPE,
120513  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_78_WIDTH },
120514  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_79_CHECKER_TYPE,
120515  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_79_WIDTH },
120516  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_80_CHECKER_TYPE,
120517  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_80_WIDTH },
120518  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_81_CHECKER_TYPE,
120519  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_81_WIDTH },
120520  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_82_CHECKER_TYPE,
120521  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_82_WIDTH },
120522  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_83_CHECKER_TYPE,
120523  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_83_WIDTH },
120524  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_84_CHECKER_TYPE,
120525  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_84_WIDTH },
120526  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_85_CHECKER_TYPE,
120527  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_85_WIDTH },
120528  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_86_CHECKER_TYPE,
120529  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_86_WIDTH },
120530  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_87_CHECKER_TYPE,
120531  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_87_WIDTH },
120532  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_88_CHECKER_TYPE,
120533  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_88_WIDTH },
120534  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_89_CHECKER_TYPE,
120535  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_89_WIDTH },
120536  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_90_CHECKER_TYPE,
120537  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_90_WIDTH },
120538  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_91_CHECKER_TYPE,
120539  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_91_WIDTH },
120540  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_92_CHECKER_TYPE,
120541  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_92_WIDTH },
120542  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_93_CHECKER_TYPE,
120543  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_93_WIDTH },
120544  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_94_CHECKER_TYPE,
120545  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_94_WIDTH },
120546  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_95_CHECKER_TYPE,
120547  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_95_WIDTH },
120548  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_96_CHECKER_TYPE,
120549  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_96_WIDTH },
120550  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_97_CHECKER_TYPE,
120551  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_97_WIDTH },
120552  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_98_CHECKER_TYPE,
120553  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_98_WIDTH },
120554  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_99_CHECKER_TYPE,
120555  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_99_WIDTH },
120556  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_100_CHECKER_TYPE,
120557  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_100_WIDTH },
120558  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_101_CHECKER_TYPE,
120559  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_101_WIDTH },
120560  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_102_CHECKER_TYPE,
120561  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_102_WIDTH },
120562  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_103_CHECKER_TYPE,
120563  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_103_WIDTH },
120564  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_104_CHECKER_TYPE,
120565  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_104_WIDTH },
120566  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_105_CHECKER_TYPE,
120567  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_105_WIDTH },
120568  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_106_CHECKER_TYPE,
120569  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_106_WIDTH },
120570  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_107_CHECKER_TYPE,
120571  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_107_WIDTH },
120572  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_108_CHECKER_TYPE,
120573  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_108_WIDTH },
120574  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_109_CHECKER_TYPE,
120575  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_109_WIDTH },
120576  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_110_CHECKER_TYPE,
120577  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_110_WIDTH },
120578  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_111_CHECKER_TYPE,
120579  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_111_WIDTH },
120580  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_112_CHECKER_TYPE,
120581  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_112_WIDTH },
120582  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_113_CHECKER_TYPE,
120583  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_113_WIDTH },
120584  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_114_CHECKER_TYPE,
120585  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_114_WIDTH },
120586  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_115_CHECKER_TYPE,
120587  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_115_WIDTH },
120588  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_116_CHECKER_TYPE,
120589  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_116_WIDTH },
120590  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_117_CHECKER_TYPE,
120591  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_117_WIDTH },
120592  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_118_CHECKER_TYPE,
120593  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_118_WIDTH },
120594  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_119_CHECKER_TYPE,
120595  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_119_WIDTH },
120596  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_120_CHECKER_TYPE,
120597  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_120_WIDTH },
120598  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_121_CHECKER_TYPE,
120599  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_121_WIDTH },
120600  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_122_CHECKER_TYPE,
120601  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_122_WIDTH },
120602  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_123_CHECKER_TYPE,
120603  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_123_WIDTH },
120604  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_124_CHECKER_TYPE,
120605  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_124_WIDTH },
120606  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_125_CHECKER_TYPE,
120607  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_125_WIDTH },
120608  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_126_CHECKER_TYPE,
120609  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_126_WIDTH },
120610  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_127_CHECKER_TYPE,
120611  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_127_WIDTH },
120612  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_128_CHECKER_TYPE,
120613  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_128_WIDTH },
120614  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_129_CHECKER_TYPE,
120615  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_129_WIDTH },
120616  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_130_CHECKER_TYPE,
120617  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_130_WIDTH },
120618  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_131_CHECKER_TYPE,
120619  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_131_WIDTH },
120620  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_132_CHECKER_TYPE,
120621  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_132_WIDTH },
120622  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_133_CHECKER_TYPE,
120623  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_133_WIDTH },
120624  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_134_CHECKER_TYPE,
120625  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_134_WIDTH },
120626  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_135_CHECKER_TYPE,
120627  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_135_WIDTH },
120628  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_136_CHECKER_TYPE,
120629  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_136_WIDTH },
120630  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_137_CHECKER_TYPE,
120631  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_137_WIDTH },
120632  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_138_CHECKER_TYPE,
120633  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_138_WIDTH },
120634  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_139_CHECKER_TYPE,
120635  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_139_WIDTH },
120636  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_140_CHECKER_TYPE,
120637  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_140_WIDTH },
120638  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_141_CHECKER_TYPE,
120639  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_141_WIDTH },
120640  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_142_CHECKER_TYPE,
120641  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_142_WIDTH },
120642  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_143_CHECKER_TYPE,
120643  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_143_WIDTH },
120644  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_144_CHECKER_TYPE,
120645  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_144_WIDTH },
120646  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_145_CHECKER_TYPE,
120647  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_145_WIDTH },
120648  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_146_CHECKER_TYPE,
120649  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_146_WIDTH },
120650  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_147_CHECKER_TYPE,
120651  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_147_WIDTH },
120652  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_148_CHECKER_TYPE,
120653  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_148_WIDTH },
120654  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_149_CHECKER_TYPE,
120655  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_149_WIDTH },
120656  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_150_CHECKER_TYPE,
120657  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_150_WIDTH },
120658  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_151_CHECKER_TYPE,
120659  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_151_WIDTH },
120660  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_152_CHECKER_TYPE,
120661  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_152_WIDTH },
120662  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_153_CHECKER_TYPE,
120663  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_153_WIDTH },
120664  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_154_CHECKER_TYPE,
120665  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_154_WIDTH },
120666  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_155_CHECKER_TYPE,
120667  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_155_WIDTH },
120668  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_156_CHECKER_TYPE,
120669  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_156_WIDTH },
120670  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_157_CHECKER_TYPE,
120671  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_157_WIDTH },
120672  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_158_CHECKER_TYPE,
120673  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_158_WIDTH },
120674  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_159_CHECKER_TYPE,
120675  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_159_WIDTH },
120676  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_160_CHECKER_TYPE,
120677  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_160_WIDTH },
120678  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_161_CHECKER_TYPE,
120679  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_161_WIDTH },
120680  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_162_CHECKER_TYPE,
120681  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_162_WIDTH },
120682  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_163_CHECKER_TYPE,
120683  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_163_WIDTH },
120684  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_164_CHECKER_TYPE,
120685  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_164_WIDTH },
120686  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_165_CHECKER_TYPE,
120687  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_165_WIDTH },
120688  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_166_CHECKER_TYPE,
120689  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_166_WIDTH },
120690  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_167_CHECKER_TYPE,
120691  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_167_WIDTH },
120692  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_168_CHECKER_TYPE,
120693  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_168_WIDTH },
120694  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_169_CHECKER_TYPE,
120695  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_169_WIDTH },
120696  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_170_CHECKER_TYPE,
120697  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_170_WIDTH },
120698  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_171_CHECKER_TYPE,
120699  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_171_WIDTH },
120700  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_172_CHECKER_TYPE,
120701  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_172_WIDTH },
120702  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_173_CHECKER_TYPE,
120703  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_173_WIDTH },
120704  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_174_CHECKER_TYPE,
120705  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_174_WIDTH },
120706  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_175_CHECKER_TYPE,
120707  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_175_WIDTH },
120708  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_176_CHECKER_TYPE,
120709  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_176_WIDTH },
120710  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_177_CHECKER_TYPE,
120711  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_177_WIDTH },
120712  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_178_CHECKER_TYPE,
120713  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_178_WIDTH },
120714  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_179_CHECKER_TYPE,
120715  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_179_WIDTH },
120716  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_180_CHECKER_TYPE,
120717  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_180_WIDTH },
120718  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_181_CHECKER_TYPE,
120719  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_181_WIDTH },
120720  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_182_CHECKER_TYPE,
120721  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_182_WIDTH },
120722  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_183_CHECKER_TYPE,
120723  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_183_WIDTH },
120724  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_184_CHECKER_TYPE,
120725  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_184_WIDTH },
120726  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_185_CHECKER_TYPE,
120727  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_185_WIDTH },
120728  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_186_CHECKER_TYPE,
120729  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_186_WIDTH },
120730  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_187_CHECKER_TYPE,
120731  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_187_WIDTH },
120732  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_188_CHECKER_TYPE,
120733  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_188_WIDTH },
120734  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_189_CHECKER_TYPE,
120735  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_189_WIDTH },
120736  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_190_CHECKER_TYPE,
120737  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_190_WIDTH },
120738  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_191_CHECKER_TYPE,
120739  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_191_WIDTH },
120740  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_192_CHECKER_TYPE,
120741  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_192_WIDTH },
120742  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_193_CHECKER_TYPE,
120743  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_193_WIDTH },
120744  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_194_CHECKER_TYPE,
120745  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_194_WIDTH },
120746  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_195_CHECKER_TYPE,
120747  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_195_WIDTH },
120748  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_196_CHECKER_TYPE,
120749  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_196_WIDTH },
120750  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_197_CHECKER_TYPE,
120751  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_197_WIDTH },
120752  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_198_CHECKER_TYPE,
120753  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_198_WIDTH },
120754  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_199_CHECKER_TYPE,
120755  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_199_WIDTH },
120756  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_200_CHECKER_TYPE,
120757  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_200_WIDTH },
120758  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_201_CHECKER_TYPE,
120759  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_201_WIDTH },
120760  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_202_CHECKER_TYPE,
120761  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_202_WIDTH },
120762  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_203_CHECKER_TYPE,
120763  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_203_WIDTH },
120764  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_204_CHECKER_TYPE,
120765  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_204_WIDTH },
120766  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_205_CHECKER_TYPE,
120767  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_205_WIDTH },
120768  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_206_CHECKER_TYPE,
120769  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_206_WIDTH },
120770  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_207_CHECKER_TYPE,
120771  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_207_WIDTH },
120772  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_208_CHECKER_TYPE,
120773  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_208_WIDTH },
120774  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_209_CHECKER_TYPE,
120775  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_209_WIDTH },
120776  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_210_CHECKER_TYPE,
120777  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_210_WIDTH },
120778  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_211_CHECKER_TYPE,
120779  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_211_WIDTH },
120780  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_212_CHECKER_TYPE,
120781  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_212_WIDTH },
120782  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_213_CHECKER_TYPE,
120783  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_213_WIDTH },
120784  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_214_CHECKER_TYPE,
120785  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_214_WIDTH },
120786  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_215_CHECKER_TYPE,
120787  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_215_WIDTH },
120788  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_216_CHECKER_TYPE,
120789  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_216_WIDTH },
120790  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_217_CHECKER_TYPE,
120791  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_217_WIDTH },
120792  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_218_CHECKER_TYPE,
120793  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_218_WIDTH },
120794  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_219_CHECKER_TYPE,
120795  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_219_WIDTH },
120796  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_220_CHECKER_TYPE,
120797  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_220_WIDTH },
120798  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_221_CHECKER_TYPE,
120799  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_221_WIDTH },
120800  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_222_CHECKER_TYPE,
120801  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_222_WIDTH },
120802  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_223_CHECKER_TYPE,
120803  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_223_WIDTH },
120804  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_224_CHECKER_TYPE,
120805  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_224_WIDTH },
120806  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_225_CHECKER_TYPE,
120807  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_225_WIDTH },
120808  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_226_CHECKER_TYPE,
120809  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_226_WIDTH },
120810  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_227_CHECKER_TYPE,
120811  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_227_WIDTH },
120812  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_228_CHECKER_TYPE,
120813  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_228_WIDTH },
120814  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_229_CHECKER_TYPE,
120815  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_229_WIDTH },
120816  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_230_CHECKER_TYPE,
120817  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_230_WIDTH },
120818  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_231_CHECKER_TYPE,
120819  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_231_WIDTH },
120820  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_232_CHECKER_TYPE,
120821  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_232_WIDTH },
120822  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_233_CHECKER_TYPE,
120823  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_233_WIDTH },
120824  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_234_CHECKER_TYPE,
120825  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_234_WIDTH },
120826  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_235_CHECKER_TYPE,
120827  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_235_WIDTH },
120828  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_236_CHECKER_TYPE,
120829  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_236_WIDTH },
120830  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_237_CHECKER_TYPE,
120831  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_237_WIDTH },
120832  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_238_CHECKER_TYPE,
120833  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_238_WIDTH },
120834  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_239_CHECKER_TYPE,
120835  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_239_WIDTH },
120836  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_240_CHECKER_TYPE,
120837  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_240_WIDTH },
120838  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_241_CHECKER_TYPE,
120839  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_241_WIDTH },
120840  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_242_CHECKER_TYPE,
120841  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_242_WIDTH },
120842  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_243_CHECKER_TYPE,
120843  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_243_WIDTH },
120844  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_244_CHECKER_TYPE,
120845  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_244_WIDTH },
120846  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_245_CHECKER_TYPE,
120847  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_245_WIDTH },
120848  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_246_CHECKER_TYPE,
120849  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_246_WIDTH },
120850  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_247_CHECKER_TYPE,
120851  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_247_WIDTH },
120852  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_248_CHECKER_TYPE,
120853  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_248_WIDTH },
120854  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_249_CHECKER_TYPE,
120855  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_249_WIDTH },
120856  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_250_CHECKER_TYPE,
120857  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_250_WIDTH },
120858  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_251_CHECKER_TYPE,
120859  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_251_WIDTH },
120860  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_252_CHECKER_TYPE,
120861  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_252_WIDTH },
120862  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_253_CHECKER_TYPE,
120863  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_253_WIDTH },
120864  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_254_CHECKER_TYPE,
120865  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_254_WIDTH },
120866  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_255_CHECKER_TYPE,
120867  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_GROUP_255_WIDTH },
120868 };
120869 
120875 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS] =
120876 {
120877  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_0_CHECKER_TYPE,
120878  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_0_WIDTH },
120879  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_1_CHECKER_TYPE,
120880  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_1_WIDTH },
120881  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_2_CHECKER_TYPE,
120882  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_2_WIDTH },
120883  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_3_CHECKER_TYPE,
120884  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_3_WIDTH },
120885  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_4_CHECKER_TYPE,
120886  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_4_WIDTH },
120887  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_5_CHECKER_TYPE,
120888  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_5_WIDTH },
120889  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_6_CHECKER_TYPE,
120890  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_6_WIDTH },
120891  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_7_CHECKER_TYPE,
120892  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_7_WIDTH },
120893  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_8_CHECKER_TYPE,
120894  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_8_WIDTH },
120895  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_9_CHECKER_TYPE,
120896  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_9_WIDTH },
120897  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_10_CHECKER_TYPE,
120898  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_10_WIDTH },
120899  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_11_CHECKER_TYPE,
120900  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_11_WIDTH },
120901  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_12_CHECKER_TYPE,
120902  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_12_WIDTH },
120903  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_13_CHECKER_TYPE,
120904  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_13_WIDTH },
120905  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_14_CHECKER_TYPE,
120906  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_14_WIDTH },
120907  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_15_CHECKER_TYPE,
120908  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_15_WIDTH },
120909  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_16_CHECKER_TYPE,
120910  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_16_WIDTH },
120911  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_17_CHECKER_TYPE,
120912  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_17_WIDTH },
120913  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_18_CHECKER_TYPE,
120914  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_18_WIDTH },
120915  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_19_CHECKER_TYPE,
120916  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_19_WIDTH },
120917  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_20_CHECKER_TYPE,
120918  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_20_WIDTH },
120919  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_21_CHECKER_TYPE,
120920  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_21_WIDTH },
120921  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_22_CHECKER_TYPE,
120922  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_22_WIDTH },
120923  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_23_CHECKER_TYPE,
120924  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_23_WIDTH },
120925  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_24_CHECKER_TYPE,
120926  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_24_WIDTH },
120927  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_25_CHECKER_TYPE,
120928  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_25_WIDTH },
120929  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_26_CHECKER_TYPE,
120930  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_26_WIDTH },
120931  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_27_CHECKER_TYPE,
120932  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_27_WIDTH },
120933  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_28_CHECKER_TYPE,
120934  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_28_WIDTH },
120935  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_29_CHECKER_TYPE,
120936  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_29_WIDTH },
120937  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_30_CHECKER_TYPE,
120938  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_30_WIDTH },
120939  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_31_CHECKER_TYPE,
120940  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_31_WIDTH },
120941  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_32_CHECKER_TYPE,
120942  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_32_WIDTH },
120943  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_33_CHECKER_TYPE,
120944  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_33_WIDTH },
120945  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_34_CHECKER_TYPE,
120946  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_34_WIDTH },
120947  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_35_CHECKER_TYPE,
120948  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_35_WIDTH },
120949  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_36_CHECKER_TYPE,
120950  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_36_WIDTH },
120951  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_37_CHECKER_TYPE,
120952  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_37_WIDTH },
120953  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_38_CHECKER_TYPE,
120954  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_38_WIDTH },
120955  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_39_CHECKER_TYPE,
120956  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_39_WIDTH },
120957  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_40_CHECKER_TYPE,
120958  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_40_WIDTH },
120959  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_41_CHECKER_TYPE,
120960  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_41_WIDTH },
120961  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_42_CHECKER_TYPE,
120962  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_42_WIDTH },
120963  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_43_CHECKER_TYPE,
120964  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_43_WIDTH },
120965  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_44_CHECKER_TYPE,
120966  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_44_WIDTH },
120967  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_45_CHECKER_TYPE,
120968  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_45_WIDTH },
120969  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_46_CHECKER_TYPE,
120970  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_46_WIDTH },
120971  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_47_CHECKER_TYPE,
120972  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_47_WIDTH },
120973  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_48_CHECKER_TYPE,
120974  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_48_WIDTH },
120975  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_49_CHECKER_TYPE,
120976  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_49_WIDTH },
120977  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_50_CHECKER_TYPE,
120978  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_50_WIDTH },
120979  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_51_CHECKER_TYPE,
120980  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_51_WIDTH },
120981  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_52_CHECKER_TYPE,
120982  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_52_WIDTH },
120983  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_53_CHECKER_TYPE,
120984  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_53_WIDTH },
120985  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_54_CHECKER_TYPE,
120986  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_54_WIDTH },
120987  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_55_CHECKER_TYPE,
120988  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_55_WIDTH },
120989  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_56_CHECKER_TYPE,
120990  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_56_WIDTH },
120991  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_57_CHECKER_TYPE,
120992  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_57_WIDTH },
120993  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_58_CHECKER_TYPE,
120994  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_58_WIDTH },
120995  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_59_CHECKER_TYPE,
120996  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_59_WIDTH },
120997  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_60_CHECKER_TYPE,
120998  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_60_WIDTH },
120999  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_61_CHECKER_TYPE,
121000  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_61_WIDTH },
121001  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_62_CHECKER_TYPE,
121002  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_62_WIDTH },
121003  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_63_CHECKER_TYPE,
121004  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_63_WIDTH },
121005  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_64_CHECKER_TYPE,
121006  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_64_WIDTH },
121007  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_65_CHECKER_TYPE,
121008  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_65_WIDTH },
121009  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_66_CHECKER_TYPE,
121010  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_66_WIDTH },
121011  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_67_CHECKER_TYPE,
121012  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_67_WIDTH },
121013  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_68_CHECKER_TYPE,
121014  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_68_WIDTH },
121015  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_69_CHECKER_TYPE,
121016  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_69_WIDTH },
121017  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_70_CHECKER_TYPE,
121018  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_70_WIDTH },
121019  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_71_CHECKER_TYPE,
121020  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_71_WIDTH },
121021  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_72_CHECKER_TYPE,
121022  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_72_WIDTH },
121023  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_73_CHECKER_TYPE,
121024  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_73_WIDTH },
121025  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_74_CHECKER_TYPE,
121026  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_74_WIDTH },
121027  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_75_CHECKER_TYPE,
121028  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_75_WIDTH },
121029  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_76_CHECKER_TYPE,
121030  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_76_WIDTH },
121031  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_77_CHECKER_TYPE,
121032  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_77_WIDTH },
121033  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_78_CHECKER_TYPE,
121034  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_78_WIDTH },
121035  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_79_CHECKER_TYPE,
121036  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_79_WIDTH },
121037  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_80_CHECKER_TYPE,
121038  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_80_WIDTH },
121039  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_81_CHECKER_TYPE,
121040  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_81_WIDTH },
121041  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_82_CHECKER_TYPE,
121042  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_82_WIDTH },
121043  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_83_CHECKER_TYPE,
121044  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_83_WIDTH },
121045  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_84_CHECKER_TYPE,
121046  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_84_WIDTH },
121047  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_85_CHECKER_TYPE,
121048  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_85_WIDTH },
121049  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_86_CHECKER_TYPE,
121050  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_86_WIDTH },
121051  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_87_CHECKER_TYPE,
121052  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_87_WIDTH },
121053  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_88_CHECKER_TYPE,
121054  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_88_WIDTH },
121055  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_89_CHECKER_TYPE,
121056  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_89_WIDTH },
121057  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_90_CHECKER_TYPE,
121058  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_90_WIDTH },
121059  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_91_CHECKER_TYPE,
121060  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_91_WIDTH },
121061  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_92_CHECKER_TYPE,
121062  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_92_WIDTH },
121063  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_93_CHECKER_TYPE,
121064  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_93_WIDTH },
121065  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_94_CHECKER_TYPE,
121066  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_94_WIDTH },
121067  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_95_CHECKER_TYPE,
121068  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_95_WIDTH },
121069  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_96_CHECKER_TYPE,
121070  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_96_WIDTH },
121071  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_97_CHECKER_TYPE,
121072  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_97_WIDTH },
121073  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_98_CHECKER_TYPE,
121074  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_98_WIDTH },
121075  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_99_CHECKER_TYPE,
121076  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_99_WIDTH },
121077  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_100_CHECKER_TYPE,
121078  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_100_WIDTH },
121079  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_101_CHECKER_TYPE,
121080  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_101_WIDTH },
121081  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_102_CHECKER_TYPE,
121082  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_102_WIDTH },
121083  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_103_CHECKER_TYPE,
121084  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_103_WIDTH },
121085  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_104_CHECKER_TYPE,
121086  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_104_WIDTH },
121087  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_105_CHECKER_TYPE,
121088  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_105_WIDTH },
121089  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_106_CHECKER_TYPE,
121090  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_106_WIDTH },
121091  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_107_CHECKER_TYPE,
121092  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_107_WIDTH },
121093  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_108_CHECKER_TYPE,
121094  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_GROUP_108_WIDTH },
121095 };
121096 
121102 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
121103 {
121104  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
121105  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
121106  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
121107  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
121108  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
121109  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
121110  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
121111  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
121112  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
121113  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
121114  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
121115  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
121116  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
121117  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
121118  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
121119  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
121120  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
121121  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
121122  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
121123  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
121124  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
121125  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
121126  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
121127  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
121128  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
121129  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
121130  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
121131  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
121132  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
121133  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
121134 };
121135 
121141 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
121142 {
121143  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
121144  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
121145  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
121146  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
121147  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
121148  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
121149  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
121150  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
121151 };
121152 
121158 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
121159 {
121160  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
121161  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
121162  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
121163  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
121164  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
121165  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
121166  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
121167  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
121168  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
121169  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
121170  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
121171  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
121172  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
121173  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
121174  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
121175  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
121176  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
121177  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
121178  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
121179  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
121180  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
121181  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
121182  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
121183  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
121184  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
121185  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
121186  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
121187  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
121188  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
121189  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
121190 };
121191 
121197 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
121198 {
121199  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
121200  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
121201  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
121202  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
121203  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
121204  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
121205  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
121206  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
121207 };
121208 
121214 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
121215 {
121216  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
121217  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
121218  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
121219  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
121220  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
121221  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
121222  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
121223  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
121224  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
121225  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
121226  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
121227  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
121228  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
121229  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
121230  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
121231  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
121232  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
121233  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
121234  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
121235  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
121236  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
121237  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
121238  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
121239  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
121240  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
121241  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
121242  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
121243  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
121244  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
121245  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
121246 };
121247 
121253 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
121254 {
121255  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
121256  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
121257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
121258  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
121259  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
121260  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
121261 };
121262 
121268 static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
121269 {
121270  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
121271  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
121272  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
121273  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
121274  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
121275  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
121276  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
121277  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
121278  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
121279  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
121280  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
121281  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
121282 };
121283 
121289 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_MAX_NUM_CHECKERS] =
121290 {
121291  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_0_CHECKER_TYPE,
121292  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_0_WIDTH },
121293  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_1_CHECKER_TYPE,
121294  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_1_WIDTH },
121295  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_2_CHECKER_TYPE,
121296  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_2_WIDTH },
121297  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_3_CHECKER_TYPE,
121298  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_3_WIDTH },
121299  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_4_CHECKER_TYPE,
121300  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_4_WIDTH },
121301  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_5_CHECKER_TYPE,
121302  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_GROUP_5_WIDTH },
121303 };
121304 
121310 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS] =
121311 {
121312  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_0_CHECKER_TYPE,
121313  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_0_WIDTH },
121314  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_1_CHECKER_TYPE,
121315  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_1_WIDTH },
121316  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_2_CHECKER_TYPE,
121317  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_2_WIDTH },
121318  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_3_CHECKER_TYPE,
121319  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_3_WIDTH },
121320  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_4_CHECKER_TYPE,
121321  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_4_WIDTH },
121322  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_5_CHECKER_TYPE,
121323  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_5_WIDTH },
121324  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_6_CHECKER_TYPE,
121325  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_6_WIDTH },
121326  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_7_CHECKER_TYPE,
121327  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_7_WIDTH },
121328  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_8_CHECKER_TYPE,
121329  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_8_WIDTH },
121330  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_9_CHECKER_TYPE,
121331  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_9_WIDTH },
121332  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_10_CHECKER_TYPE,
121333  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_10_WIDTH },
121334  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_11_CHECKER_TYPE,
121335  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_11_WIDTH },
121336  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_12_CHECKER_TYPE,
121337  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_12_WIDTH },
121338  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_13_CHECKER_TYPE,
121339  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_13_WIDTH },
121340  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_14_CHECKER_TYPE,
121341  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_14_WIDTH },
121342  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_15_CHECKER_TYPE,
121343  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_15_WIDTH },
121344  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_16_CHECKER_TYPE,
121345  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_16_WIDTH },
121346  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_17_CHECKER_TYPE,
121347  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_17_WIDTH },
121348  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_18_CHECKER_TYPE,
121349  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_GROUP_18_WIDTH },
121350 };
121351 
121357 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
121358 {
121359  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
121360  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
121361  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
121362  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
121363  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
121364  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
121365  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
121366  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
121367 };
121368 
121374 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_MAX_NUM_CHECKERS] =
121375 {
121376  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_0_CHECKER_TYPE,
121377  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_0_WIDTH },
121378  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_1_CHECKER_TYPE,
121379  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_1_WIDTH },
121380  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_2_CHECKER_TYPE,
121381  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_2_WIDTH },
121382  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_3_CHECKER_TYPE,
121383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_3_WIDTH },
121384  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_4_CHECKER_TYPE,
121385  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_4_WIDTH },
121386  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_5_CHECKER_TYPE,
121387  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_GROUP_5_WIDTH },
121388 };
121389 
121395 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
121396 {
121397  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
121398  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
121399  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
121400  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
121401  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
121402  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
121403 };
121404 
121410 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
121411 {
121412  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
121413  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
121414  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
121415  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
121416  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
121417  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
121418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
121419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
121420  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
121421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
121422  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
121423  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
121424  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
121425  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
121426  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
121427  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
121428  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
121429  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
121430  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
121431  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
121432  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
121433  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
121434  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
121435  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
121436  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
121437  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
121438  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
121439  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
121440  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
121441  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
121442  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
121443  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
121444  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
121445  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
121446  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
121447  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
121448  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
121449  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
121450  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
121451  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
121452  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
121453  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
121454  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
121455  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
121456  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
121457  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
121458  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
121459  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
121460  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
121461  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
121462  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
121463  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
121464  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
121465  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
121466  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
121467  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
121468  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
121469  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
121470  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
121471  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
121472  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
121473  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
121474  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
121475  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
121476  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
121477  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
121478  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
121479  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
121480  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
121481  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
121482  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
121483  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
121484  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
121485  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
121486  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
121487  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
121488  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
121489  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
121490  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
121491  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
121492  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
121493  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
121494  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
121495  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
121496  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
121497  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
121498  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
121499  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
121500  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
121501  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
121502  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
121503  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
121504  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
121505  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
121506  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
121507  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
121508  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
121509  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
121510  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
121511  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
121512  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
121513  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
121514  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
121515  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
121516  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
121517  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
121518  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
121519  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
121520  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
121521  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
121522  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
121523  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
121524  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
121525  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
121526  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
121527  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
121528  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
121529  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
121530  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
121531  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
121532  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
121533  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
121534  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
121535  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
121536  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
121537  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
121538  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
121539  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
121540  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
121541  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
121542  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
121543  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
121544  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
121545  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
121546  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
121547  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
121548  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
121549  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
121550  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
121551  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
121552  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
121553  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
121554  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
121555  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
121556  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
121557  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
121558  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
121559  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
121560  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
121561  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
121562  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
121563  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
121564  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
121565  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
121566  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
121567  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
121568  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
121569  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
121570  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
121571  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
121572  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
121573  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
121574  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
121575  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
121576  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
121577  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
121578  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
121579  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
121580  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
121581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
121582  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
121583  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
121584  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
121585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
121586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
121587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
121588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
121589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
121590  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
121591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
121592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
121593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
121594  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
121595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
121596  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
121597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
121598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
121599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
121600  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
121601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
121602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
121603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
121604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
121605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
121606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
121607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
121608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
121609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
121610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
121611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
121612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
121613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
121614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
121615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
121616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
121617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
121618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
121619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
121620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
121621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
121622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
121623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
121624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
121625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
121626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
121627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
121628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
121629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
121630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
121631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
121632  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
121633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
121634  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
121635  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
121636  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
121637  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
121638  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
121639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
121640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
121641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
121642  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
121643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
121644  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
121645  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
121646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
121647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
121648  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
121649  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
121650  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
121651  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
121652  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
121653  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
121654  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
121655  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
121656  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
121657  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
121658  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
121659  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
121660  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
121661  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
121662  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
121663  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
121664  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
121665  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
121666  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
121667  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
121668  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
121669  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
121670  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
121671  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
121672  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
121673  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
121674  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
121675  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
121676  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
121677  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
121678  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
121679  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
121680  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
121681  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
121682  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
121683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
121684  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
121685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
121686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
121687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
121688 };
121689 
121695 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
121696 {
121697  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
121698  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_0_WIDTH },
121699  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
121700  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_1_WIDTH },
121701  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
121702  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_2_WIDTH },
121703  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
121704  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_3_WIDTH },
121705  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
121706  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_4_WIDTH },
121707  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
121708  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_5_WIDTH },
121709  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
121710  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_6_WIDTH },
121711  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
121712  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_7_WIDTH },
121713  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
121714  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_8_WIDTH },
121715  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
121716  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_9_WIDTH },
121717  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
121718  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_10_WIDTH },
121719  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
121720  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_11_WIDTH },
121721  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
121722  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_12_WIDTH },
121723  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
121724  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_13_WIDTH },
121725  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
121726  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_14_WIDTH },
121727  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
121728  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_15_WIDTH },
121729  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
121730  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_16_WIDTH },
121731  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
121732  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_17_WIDTH },
121733  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
121734  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_18_WIDTH },
121735  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
121736  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_19_WIDTH },
121737  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
121738  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_20_WIDTH },
121739  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
121740  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_21_WIDTH },
121741  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
121742  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_22_WIDTH },
121743  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
121744  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_23_WIDTH },
121745  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
121746  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_24_WIDTH },
121747  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
121748  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_25_WIDTH },
121749  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
121750  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_26_WIDTH },
121751  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
121752  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_27_WIDTH },
121753  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
121754  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_28_WIDTH },
121755  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
121756  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_29_WIDTH },
121757  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
121758  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_30_WIDTH },
121759  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
121760  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_31_WIDTH },
121761  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
121762  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_32_WIDTH },
121763  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
121764  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_33_WIDTH },
121765  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
121766  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_34_WIDTH },
121767  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
121768  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_35_WIDTH },
121769  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
121770  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_36_WIDTH },
121771  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
121772  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_37_WIDTH },
121773  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
121774  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_38_WIDTH },
121775  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
121776  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_39_WIDTH },
121777  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
121778  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_40_WIDTH },
121779  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
121780  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_41_WIDTH },
121781  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
121782  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_42_WIDTH },
121783  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
121784  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_43_WIDTH },
121785  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
121786  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_44_WIDTH },
121787  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
121788  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_45_WIDTH },
121789  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
121790  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_46_WIDTH },
121791  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
121792  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_47_WIDTH },
121793  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
121794  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_48_WIDTH },
121795  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
121796  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_49_WIDTH },
121797  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
121798  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_50_WIDTH },
121799  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
121800  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_51_WIDTH },
121801  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
121802  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_52_WIDTH },
121803  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
121804  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_53_WIDTH },
121805  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
121806  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_54_WIDTH },
121807  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
121808  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_55_WIDTH },
121809  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
121810  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_56_WIDTH },
121811  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
121812  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_57_WIDTH },
121813  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
121814  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_58_WIDTH },
121815  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
121816  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_59_WIDTH },
121817  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
121818  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_60_WIDTH },
121819  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
121820  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_61_WIDTH },
121821  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
121822  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_GROUP_62_WIDTH },
121823 };
121824 
121830 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_MAX_NUM_CHECKERS] =
121831 {
121832  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
121833  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_0_WIDTH },
121834  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
121835  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_1_WIDTH },
121836  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
121837  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_2_WIDTH },
121838  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
121839  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_3_WIDTH },
121840  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
121841  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_4_WIDTH },
121842  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
121843  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_5_WIDTH },
121844  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
121845  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_6_WIDTH },
121846  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
121847  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_7_WIDTH },
121848  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
121849  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_8_WIDTH },
121850  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
121851  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_9_WIDTH },
121852  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
121853  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_10_WIDTH },
121854  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
121855  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_11_WIDTH },
121856  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
121857  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_12_WIDTH },
121858  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
121859  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_13_WIDTH },
121860  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
121861  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_14_WIDTH },
121862  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
121863  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_15_WIDTH },
121864  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
121865  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_16_WIDTH },
121866  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
121867  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_17_WIDTH },
121868  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
121869  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_18_WIDTH },
121870  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
121871  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_19_WIDTH },
121872  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
121873  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_20_WIDTH },
121874  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
121875  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_21_WIDTH },
121876  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
121877  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_22_WIDTH },
121878  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
121879  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_23_WIDTH },
121880  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
121881  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_24_WIDTH },
121882  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
121883  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_25_WIDTH },
121884  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
121885  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_26_WIDTH },
121886  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
121887  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_27_WIDTH },
121888  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
121889  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_28_WIDTH },
121890  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
121891  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_29_WIDTH },
121892  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
121893  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_30_WIDTH },
121894  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
121895  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_31_WIDTH },
121896  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
121897  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_32_WIDTH },
121898  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
121899  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_33_WIDTH },
121900  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
121901  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_34_WIDTH },
121902  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
121903  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_35_WIDTH },
121904  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
121905  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_36_WIDTH },
121906  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
121907  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_37_WIDTH },
121908  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
121909  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_38_WIDTH },
121910  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
121911  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_39_WIDTH },
121912  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
121913  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_40_WIDTH },
121914  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
121915  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_41_WIDTH },
121916  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
121917  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_42_WIDTH },
121918  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
121919  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_43_WIDTH },
121920  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
121921  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_44_WIDTH },
121922  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
121923  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_45_WIDTH },
121924  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
121925  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_46_WIDTH },
121926  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
121927  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_GROUP_47_WIDTH },
121928 };
121929 
121935 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_MAX_NUM_CHECKERS] =
121936 {
121937  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
121938  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_0_WIDTH },
121939  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
121940  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_1_WIDTH },
121941  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
121942  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_2_WIDTH },
121943  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
121944  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_3_WIDTH },
121945  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
121946  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_4_WIDTH },
121947  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
121948  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_5_WIDTH },
121949  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
121950  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_6_WIDTH },
121951  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
121952  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_7_WIDTH },
121953  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
121954  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_8_WIDTH },
121955  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
121956  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_9_WIDTH },
121957  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
121958  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_10_WIDTH },
121959  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
121960  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_11_WIDTH },
121961  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
121962  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_12_WIDTH },
121963  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
121964  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_13_WIDTH },
121965  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
121966  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_14_WIDTH },
121967  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
121968  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_15_WIDTH },
121969  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
121970  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_16_WIDTH },
121971  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
121972  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_17_WIDTH },
121973  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
121974  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_18_WIDTH },
121975  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
121976  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_19_WIDTH },
121977  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
121978  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_20_WIDTH },
121979  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
121980  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_21_WIDTH },
121981  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
121982  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_22_WIDTH },
121983  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
121984  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_23_WIDTH },
121985  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
121986  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_24_WIDTH },
121987  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
121988  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_25_WIDTH },
121989  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
121990  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_26_WIDTH },
121991  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
121992  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_27_WIDTH },
121993  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
121994  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_28_WIDTH },
121995  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
121996  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_29_WIDTH },
121997  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
121998  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_30_WIDTH },
121999  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
122000  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_GROUP_31_WIDTH },
122001 };
122002 
122008 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122009 {
122010  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122011  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_0_WIDTH },
122012  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_1_WIDTH },
122014  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_2_WIDTH },
122016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
122017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_3_WIDTH },
122018  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
122019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_4_WIDTH },
122020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
122021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_5_WIDTH },
122022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
122023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_6_WIDTH },
122024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
122025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_7_WIDTH },
122026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
122027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_8_WIDTH },
122028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
122029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_9_WIDTH },
122030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
122031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_10_WIDTH },
122032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
122033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_11_WIDTH },
122034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
122035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_12_WIDTH },
122036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
122037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_13_WIDTH },
122038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
122039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_14_WIDTH },
122040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
122041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_15_WIDTH },
122042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
122043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_16_WIDTH },
122044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
122045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_17_WIDTH },
122046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
122047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_18_WIDTH },
122048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
122049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_19_WIDTH },
122050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
122051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_20_WIDTH },
122052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
122053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_21_WIDTH },
122054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
122055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_22_WIDTH },
122056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
122057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_23_WIDTH },
122058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
122059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_24_WIDTH },
122060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
122061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_25_WIDTH },
122062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
122063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_26_WIDTH },
122064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
122065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_27_WIDTH },
122066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
122067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_28_WIDTH },
122068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
122069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_29_WIDTH },
122070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
122071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_30_WIDTH },
122072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
122073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_31_WIDTH },
122074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
122075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_32_WIDTH },
122076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
122077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_33_WIDTH },
122078  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
122079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_34_WIDTH },
122080  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
122081  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_35_WIDTH },
122082  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
122083  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_36_WIDTH },
122084  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
122085  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_37_WIDTH },
122086  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
122087  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_38_WIDTH },
122088  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
122089  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_GROUP_39_WIDTH },
122090 };
122091 
122097 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122098 {
122099  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122100  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
122101  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122102  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
122103  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122104  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
122105  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
122106  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
122107  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
122108  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
122109  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
122110  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
122111  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
122112  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
122113  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
122114  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
122115  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
122116  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
122117  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
122118  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
122119  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
122120  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
122121  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
122122  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
122123  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
122124  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
122125  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
122126  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
122127  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
122128  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
122129  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
122130  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
122131  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
122132  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
122133  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
122134  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
122135  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
122136  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
122137  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
122138  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
122139  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
122140  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
122141  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
122142  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
122143  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
122144  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
122145  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
122146  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
122147  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
122148  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
122149  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
122150  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
122151  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
122152  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
122153  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
122154  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
122155  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
122156  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
122157  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
122158  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
122159  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
122160  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
122161  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
122162  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
122163  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
122164  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
122165  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
122166  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
122167  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
122168  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
122169  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
122170  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
122171  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
122172  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
122173  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
122174  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
122175  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
122176  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
122177  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
122178  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
122179  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
122180  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
122181  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
122182  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
122183  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
122184  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
122185  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
122186  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
122187  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
122188  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
122189  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
122190  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
122191  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
122192  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
122193  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
122194  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
122195  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
122196  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
122197  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
122198  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
122199  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
122200  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
122201  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
122202  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
122203  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
122204  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
122205  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
122206  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
122207  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
122208  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
122209  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
122210  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
122211  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
122212  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
122213  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
122214  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
122215  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
122216  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
122217  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
122218  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
122219  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
122220  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
122221  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
122222  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
122223  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
122224  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
122225  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
122226  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
122227  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
122228  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
122229  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
122230  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
122231  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
122232  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
122233  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
122234  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
122235  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
122236  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
122237  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
122238  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
122239  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
122240  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
122241  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
122242  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
122243  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
122244  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
122245  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
122246  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
122247  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
122248  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
122249  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
122250  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
122251  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
122252  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
122253  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
122254  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
122255  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
122256  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
122257  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
122258  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
122259  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
122260  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
122261  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
122262  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
122263  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
122264  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
122265  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
122266  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
122267  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
122268  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
122269  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
122270  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
122271  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
122272  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
122273  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
122274  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
122275  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
122276  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
122277  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
122278  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
122279  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
122280  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
122281  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
122282  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
122283  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
122284  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
122285  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
122286  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
122287  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
122288  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
122289  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
122290  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
122291  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
122292  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
122293  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
122294  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
122295  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
122296  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
122297  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
122298  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
122299  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
122300  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
122301  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
122302  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
122303  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
122304  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
122305  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
122306  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
122307  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
122308  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
122309  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
122310  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
122311  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
122312  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
122313  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
122314  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
122315  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
122316  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
122317  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
122318  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
122319  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
122320  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
122321  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
122322  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
122323  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
122324  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
122325  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
122326  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
122327  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
122328  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
122329  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
122330  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
122331  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
122332  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
122333  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
122334  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
122335  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
122336  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
122337  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
122338  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
122339  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
122340  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
122341  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
122342  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
122343  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
122344  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
122345  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
122346  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
122347  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
122348  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
122349  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
122350  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
122351  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
122352  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
122353  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
122354  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
122355  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
122356  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
122357  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
122358  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
122359  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
122360  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
122361  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
122362  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
122363  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
122364  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_132_WIDTH },
122365  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
122366  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_133_WIDTH },
122367  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
122368  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_134_WIDTH },
122369  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
122370  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_135_WIDTH },
122371  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
122372  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_136_WIDTH },
122373  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
122374  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_137_WIDTH },
122375  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
122376  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_138_WIDTH },
122377  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
122378  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_139_WIDTH },
122379  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
122380  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_140_WIDTH },
122381  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
122382  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_141_WIDTH },
122383  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
122384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_142_WIDTH },
122385  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
122386  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_143_WIDTH },
122387  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
122388  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_144_WIDTH },
122389  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
122390  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_145_WIDTH },
122391  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
122392  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_146_WIDTH },
122393  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
122394  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_147_WIDTH },
122395  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
122396  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_148_WIDTH },
122397  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
122398  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_149_WIDTH },
122399  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
122400  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_150_WIDTH },
122401  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
122402  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_151_WIDTH },
122403  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
122404  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_152_WIDTH },
122405  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
122406  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_153_WIDTH },
122407  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
122408  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_154_WIDTH },
122409  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
122410  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_155_WIDTH },
122411  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
122412  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_156_WIDTH },
122413  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
122414  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_157_WIDTH },
122415  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
122416  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_158_WIDTH },
122417  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
122418  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_159_WIDTH },
122419  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
122420  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_160_WIDTH },
122421  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
122422  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_161_WIDTH },
122423  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
122424  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_162_WIDTH },
122425  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
122426  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_163_WIDTH },
122427  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
122428  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_164_WIDTH },
122429  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
122430  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_165_WIDTH },
122431  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
122432  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_166_WIDTH },
122433  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
122434  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_167_WIDTH },
122435  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
122436  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_168_WIDTH },
122437  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
122438  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_169_WIDTH },
122439  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
122440  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_GROUP_170_WIDTH },
122441 };
122442 
122448 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122449 {
122450  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122451  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
122452  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122453  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
122454  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122455  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
122456 };
122457 
122463 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122464 {
122465  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122466  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
122467  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122468  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
122469  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122470  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
122471 };
122472 
122478 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122479 {
122480  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122481  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_0_WIDTH },
122482  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122483  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_1_WIDTH },
122484  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122485  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_2_WIDTH },
122486  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
122487  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_3_WIDTH },
122488  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
122489  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_4_WIDTH },
122490  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
122491  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_5_WIDTH },
122492  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
122493  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_6_WIDTH },
122494  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
122495  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_7_WIDTH },
122496  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
122497  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_8_WIDTH },
122498  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
122499  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_9_WIDTH },
122500  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
122501  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_10_WIDTH },
122502  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
122503  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_11_WIDTH },
122504  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
122505  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_12_WIDTH },
122506  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
122507  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_13_WIDTH },
122508  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
122509  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_14_WIDTH },
122510  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
122511  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_15_WIDTH },
122512  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
122513  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_16_WIDTH },
122514  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
122515  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_17_WIDTH },
122516  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
122517  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_18_WIDTH },
122518  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
122519  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_19_WIDTH },
122520  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
122521  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_20_WIDTH },
122522  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
122523  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_21_WIDTH },
122524  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
122525  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_22_WIDTH },
122526  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
122527  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_23_WIDTH },
122528  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
122529  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_24_WIDTH },
122530  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
122531  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_25_WIDTH },
122532  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
122533  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_26_WIDTH },
122534  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
122535  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_27_WIDTH },
122536  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
122537  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_28_WIDTH },
122538  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
122539  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_29_WIDTH },
122540  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
122541  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_30_WIDTH },
122542  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
122543  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_31_WIDTH },
122544  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
122545  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_32_WIDTH },
122546  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
122547  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_33_WIDTH },
122548  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
122549  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_34_WIDTH },
122550  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
122551  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_35_WIDTH },
122552  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
122553  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_36_WIDTH },
122554  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
122555  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_37_WIDTH },
122556  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
122557  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_GROUP_38_WIDTH },
122558 };
122559 
122565 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS] =
122566 {
122567  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
122568  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
122569  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
122570  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
122571  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
122572  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
122573  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
122574  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
122575 };
122576 
122582 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
122583 {
122584  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
122585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_0_WIDTH },
122586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
122587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_1_WIDTH },
122588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
122589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_2_WIDTH },
122590  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
122591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_3_WIDTH },
122592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
122593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_4_WIDTH },
122594  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
122595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_5_WIDTH },
122596  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
122597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_6_WIDTH },
122598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
122599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_7_WIDTH },
122600  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
122601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_8_WIDTH },
122602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
122603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_9_WIDTH },
122604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
122605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_10_WIDTH },
122606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
122607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_11_WIDTH },
122608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
122609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_12_WIDTH },
122610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
122611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_13_WIDTH },
122612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
122613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_14_WIDTH },
122614 };
122615 
122621 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
122622 {
122623  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
122624  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_0_WIDTH },
122625  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
122626  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_1_WIDTH },
122627  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
122628  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_2_WIDTH },
122629  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
122630  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_GROUP_3_WIDTH },
122631 };
122632 
122638 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122639 {
122640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
122642  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
122644  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122645  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
122646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
122647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
122648  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
122649  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
122650  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
122651  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
122652  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
122653  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
122654  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
122655  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
122656  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
122657  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
122658  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
122659  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
122660  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
122661  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
122662  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
122663  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
122664  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
122665  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
122666  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
122667  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
122668  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
122669  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
122670 };
122671 
122677 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
122678 {
122679  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
122680  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
122681 };
122682 
122688 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122689 {
122690  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122691  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
122692  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
122694  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
122696 };
122697 
122703 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122704 {
122705  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122706  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_GROUP_0_WIDTH },
122707 };
122708 
122714 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122715 {
122716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
122718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
122720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
122722 };
122723 
122729 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_MAX_NUM_CHECKERS] =
122730 {
122731  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
122732  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_0_WIDTH },
122733  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
122734  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_1_WIDTH },
122735  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
122736  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_2_WIDTH },
122737  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
122738  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_GROUP_3_WIDTH },
122739 };
122740 
122746 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_MAX_NUM_CHECKERS] =
122747 {
122748  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_0_CHECKER_TYPE,
122749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_0_WIDTH },
122750  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_1_CHECKER_TYPE,
122751  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_1_WIDTH },
122752  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_2_CHECKER_TYPE,
122753  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_GROUP_2_WIDTH },
122754 };
122755 
122761 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
122762 {
122763  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
122764  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
122765 };
122766 
122772 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122773 {
122774  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122775  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
122776  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122777  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
122778  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122779  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
122780  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
122781  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
122782  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
122783  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
122784  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
122785  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
122786  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
122787  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
122788  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
122789  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
122790  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
122791  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
122792  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
122793  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
122794  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
122795  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
122796  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
122797  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
122798  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
122799  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
122800  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
122801  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
122802  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
122803  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
122804  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
122805  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
122806  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
122807  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
122808  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
122809  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
122810 };
122811 
122817 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122818 {
122819  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122820  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
122821  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122822  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
122823  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122824  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
122825  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
122826  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
122827  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
122828  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_4_WIDTH },
122829  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
122830  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_5_WIDTH },
122831  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
122832  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_6_WIDTH },
122833  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
122834  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_7_WIDTH },
122835  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
122836  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_8_WIDTH },
122837  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
122838  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_9_WIDTH },
122839  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
122840  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_10_WIDTH },
122841  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
122842  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_11_WIDTH },
122843  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
122844  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_12_WIDTH },
122845  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
122846  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_13_WIDTH },
122847  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
122848  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_14_WIDTH },
122849  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
122850  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_15_WIDTH },
122851  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
122852  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_16_WIDTH },
122853  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
122854  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_17_WIDTH },
122855  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
122856  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_18_WIDTH },
122857  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
122858  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_19_WIDTH },
122859  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
122860  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_20_WIDTH },
122861  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
122862  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_21_WIDTH },
122863  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
122864  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_GROUP_22_WIDTH },
122865 };
122866 
122872 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
122873 {
122874  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
122875  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_0_WIDTH },
122876  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
122877  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_1_WIDTH },
122878  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
122879  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_2_WIDTH },
122880  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
122881  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_3_WIDTH },
122882  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
122883  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_4_WIDTH },
122884  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
122885  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_5_WIDTH },
122886  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
122887  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_6_WIDTH },
122888  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
122889  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_7_WIDTH },
122890  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
122891  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_8_WIDTH },
122892  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
122893  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_9_WIDTH },
122894  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
122895  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_10_WIDTH },
122896  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
122897  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_11_WIDTH },
122898  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
122899  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_12_WIDTH },
122900  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
122901  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_13_WIDTH },
122902  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
122903  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_GROUP_14_WIDTH },
122904 };
122905 
122911 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_MAX_NUM_CHECKERS] =
122912 {
122913  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
122914  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_0_WIDTH },
122915  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
122916  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_1_WIDTH },
122917  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
122918  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_2_WIDTH },
122919  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
122920  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_3_WIDTH },
122921  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
122922  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_4_WIDTH },
122923  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
122924  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_5_WIDTH },
122925  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
122926  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_6_WIDTH },
122927  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
122928  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_7_WIDTH },
122929  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
122930  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_8_WIDTH },
122931  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
122932  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_9_WIDTH },
122933  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
122934  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_10_WIDTH },
122935  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
122936  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_11_WIDTH },
122937  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
122938  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_12_WIDTH },
122939  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
122940  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_13_WIDTH },
122941  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
122942  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_GROUP_14_WIDTH },
122943 };
122944 
122950 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS] =
122951 {
122952  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
122953  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_0_WIDTH },
122954  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
122955  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_1_WIDTH },
122956  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
122957  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_GROUP_2_WIDTH },
122958 };
122959 
122964 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MemEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
122965 {
122966  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_ID, 0u,
122967  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_SIZE, 4u,
122968  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ROW_WIDTH, ((bool)false) },
122969  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID, 0u,
122970  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_SIZE, 4u,
122971  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ROW_WIDTH, ((bool)false) },
122972 };
122973 
122979 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_MAX_NUM_CHECKERS] =
122980 {
122981  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_0_CHECKER_TYPE,
122982  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_0_WIDTH },
122983  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_1_CHECKER_TYPE,
122984  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_1_WIDTH },
122985  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_2_CHECKER_TYPE,
122986  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_2_WIDTH },
122987  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_3_CHECKER_TYPE,
122988  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_3_WIDTH },
122989  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_4_CHECKER_TYPE,
122990  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_4_WIDTH },
122991  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_5_CHECKER_TYPE,
122992  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_GROUP_5_WIDTH },
122993 };
122994 
123000 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_MAX_NUM_CHECKERS] =
123001 {
123002  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_0_CHECKER_TYPE,
123003  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_0_WIDTH },
123004  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_1_CHECKER_TYPE,
123005  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_1_WIDTH },
123006  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_2_CHECKER_TYPE,
123007  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_2_WIDTH },
123008  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_3_CHECKER_TYPE,
123009  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_3_WIDTH },
123010  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_4_CHECKER_TYPE,
123011  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_4_WIDTH },
123012  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_5_CHECKER_TYPE,
123013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_5_WIDTH },
123014  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_6_CHECKER_TYPE,
123015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_6_WIDTH },
123016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_7_CHECKER_TYPE,
123017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_7_WIDTH },
123018  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_8_CHECKER_TYPE,
123019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_8_WIDTH },
123020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_9_CHECKER_TYPE,
123021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_9_WIDTH },
123022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_10_CHECKER_TYPE,
123023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_10_WIDTH },
123024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_11_CHECKER_TYPE,
123025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_11_WIDTH },
123026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_12_CHECKER_TYPE,
123027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_12_WIDTH },
123028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_13_CHECKER_TYPE,
123029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_13_WIDTH },
123030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_14_CHECKER_TYPE,
123031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_14_WIDTH },
123032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_15_CHECKER_TYPE,
123033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_15_WIDTH },
123034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_16_CHECKER_TYPE,
123035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_16_WIDTH },
123036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_17_CHECKER_TYPE,
123037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_17_WIDTH },
123038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_18_CHECKER_TYPE,
123039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_18_WIDTH },
123040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_19_CHECKER_TYPE,
123041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_19_WIDTH },
123042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_20_CHECKER_TYPE,
123043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_20_WIDTH },
123044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_21_CHECKER_TYPE,
123045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_21_WIDTH },
123046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_22_CHECKER_TYPE,
123047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_22_WIDTH },
123048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_23_CHECKER_TYPE,
123049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_23_WIDTH },
123050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_24_CHECKER_TYPE,
123051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_24_WIDTH },
123052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_25_CHECKER_TYPE,
123053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_25_WIDTH },
123054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_26_CHECKER_TYPE,
123055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_26_WIDTH },
123056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_27_CHECKER_TYPE,
123057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_27_WIDTH },
123058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_28_CHECKER_TYPE,
123059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_28_WIDTH },
123060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_29_CHECKER_TYPE,
123061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_29_WIDTH },
123062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_30_CHECKER_TYPE,
123063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_30_WIDTH },
123064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_31_CHECKER_TYPE,
123065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_31_WIDTH },
123066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_32_CHECKER_TYPE,
123067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_32_WIDTH },
123068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_33_CHECKER_TYPE,
123069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_33_WIDTH },
123070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_34_CHECKER_TYPE,
123071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_34_WIDTH },
123072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_35_CHECKER_TYPE,
123073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_35_WIDTH },
123074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_36_CHECKER_TYPE,
123075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_36_WIDTH },
123076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_37_CHECKER_TYPE,
123077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_37_WIDTH },
123078  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_38_CHECKER_TYPE,
123079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_38_WIDTH },
123080  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_39_CHECKER_TYPE,
123081  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_39_WIDTH },
123082  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_40_CHECKER_TYPE,
123083  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_40_WIDTH },
123084  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_41_CHECKER_TYPE,
123085  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_41_WIDTH },
123086  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_42_CHECKER_TYPE,
123087  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_42_WIDTH },
123088  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_43_CHECKER_TYPE,
123089  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_43_WIDTH },
123090  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_44_CHECKER_TYPE,
123091  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_44_WIDTH },
123092  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_45_CHECKER_TYPE,
123093  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_45_WIDTH },
123094  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_46_CHECKER_TYPE,
123095  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_46_WIDTH },
123096  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_47_CHECKER_TYPE,
123097  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_47_WIDTH },
123098  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_48_CHECKER_TYPE,
123099  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_48_WIDTH },
123100  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_49_CHECKER_TYPE,
123101  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_GROUP_49_WIDTH },
123102 };
123103 
123109 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_MAX_NUM_CHECKERS] =
123110 {
123111  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_0_CHECKER_TYPE,
123112  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_0_WIDTH },
123113  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_1_CHECKER_TYPE,
123114  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_1_WIDTH },
123115  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_2_CHECKER_TYPE,
123116  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_2_WIDTH },
123117  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_3_CHECKER_TYPE,
123118  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_3_WIDTH },
123119  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_4_CHECKER_TYPE,
123120  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_4_WIDTH },
123121  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_5_CHECKER_TYPE,
123122  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_5_WIDTH },
123123  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_6_CHECKER_TYPE,
123124  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_6_WIDTH },
123125  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_7_CHECKER_TYPE,
123126  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_7_WIDTH },
123127  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_8_CHECKER_TYPE,
123128  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_8_WIDTH },
123129  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_9_CHECKER_TYPE,
123130  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_9_WIDTH },
123131  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_10_CHECKER_TYPE,
123132  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_10_WIDTH },
123133  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_11_CHECKER_TYPE,
123134  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_11_WIDTH },
123135  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_12_CHECKER_TYPE,
123136  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_12_WIDTH },
123137  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_13_CHECKER_TYPE,
123138  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_13_WIDTH },
123139  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_14_CHECKER_TYPE,
123140  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_GROUP_14_WIDTH },
123141 };
123142 
123148 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_MAX_NUM_CHECKERS] =
123149 {
123150  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_0_CHECKER_TYPE,
123151  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_0_WIDTH },
123152  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_1_CHECKER_TYPE,
123153  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_1_WIDTH },
123154  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_2_CHECKER_TYPE,
123155  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_2_WIDTH },
123156  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_3_CHECKER_TYPE,
123157  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_3_WIDTH },
123158  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_4_CHECKER_TYPE,
123159  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_4_WIDTH },
123160  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_5_CHECKER_TYPE,
123161  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_5_WIDTH },
123162  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_6_CHECKER_TYPE,
123163  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_6_WIDTH },
123164  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_7_CHECKER_TYPE,
123165  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_7_WIDTH },
123166  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_8_CHECKER_TYPE,
123167  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_8_WIDTH },
123168  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_9_CHECKER_TYPE,
123169  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_9_WIDTH },
123170  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_10_CHECKER_TYPE,
123171  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_10_WIDTH },
123172  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_11_CHECKER_TYPE,
123173  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_11_WIDTH },
123174  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_12_CHECKER_TYPE,
123175  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_12_WIDTH },
123176  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_13_CHECKER_TYPE,
123177  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_13_WIDTH },
123178  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_14_CHECKER_TYPE,
123179  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_14_WIDTH },
123180  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_15_CHECKER_TYPE,
123181  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_15_WIDTH },
123182  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_16_CHECKER_TYPE,
123183  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_16_WIDTH },
123184  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_17_CHECKER_TYPE,
123185  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_17_WIDTH },
123186  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_18_CHECKER_TYPE,
123187  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_18_WIDTH },
123188  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_19_CHECKER_TYPE,
123189  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_19_WIDTH },
123190  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_20_CHECKER_TYPE,
123191  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_20_WIDTH },
123192  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_21_CHECKER_TYPE,
123193  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_21_WIDTH },
123194  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_22_CHECKER_TYPE,
123195  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_22_WIDTH },
123196  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_23_CHECKER_TYPE,
123197  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_23_WIDTH },
123198  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_24_CHECKER_TYPE,
123199  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_24_WIDTH },
123200  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_25_CHECKER_TYPE,
123201  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_25_WIDTH },
123202  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_26_CHECKER_TYPE,
123203  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_26_WIDTH },
123204  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_27_CHECKER_TYPE,
123205  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_27_WIDTH },
123206  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_28_CHECKER_TYPE,
123207  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_28_WIDTH },
123208  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_29_CHECKER_TYPE,
123209  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_29_WIDTH },
123210  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_30_CHECKER_TYPE,
123211  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_30_WIDTH },
123212  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_31_CHECKER_TYPE,
123213  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_31_WIDTH },
123214  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_32_CHECKER_TYPE,
123215  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_32_WIDTH },
123216  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_33_CHECKER_TYPE,
123217  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_33_WIDTH },
123218  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_34_CHECKER_TYPE,
123219  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_34_WIDTH },
123220  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_35_CHECKER_TYPE,
123221  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_35_WIDTH },
123222  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_36_CHECKER_TYPE,
123223  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_36_WIDTH },
123224  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_37_CHECKER_TYPE,
123225  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_37_WIDTH },
123226  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_38_CHECKER_TYPE,
123227  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_38_WIDTH },
123228  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_39_CHECKER_TYPE,
123229  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_39_WIDTH },
123230  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_40_CHECKER_TYPE,
123231  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_GROUP_40_WIDTH },
123232 };
123233 
123239 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_MAX_NUM_CHECKERS] =
123240 {
123241  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_0_CHECKER_TYPE,
123242  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_0_WIDTH },
123243  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_1_CHECKER_TYPE,
123244  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_1_WIDTH },
123245  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_2_CHECKER_TYPE,
123246  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_2_WIDTH },
123247  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_3_CHECKER_TYPE,
123248  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_GROUP_3_WIDTH },
123249 };
123250 
123256 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_MAX_NUM_CHECKERS] =
123257 {
123258  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_0_CHECKER_TYPE,
123259  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_0_WIDTH },
123260  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_1_CHECKER_TYPE,
123261  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_1_WIDTH },
123262  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_2_CHECKER_TYPE,
123263  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_2_WIDTH },
123264  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_3_CHECKER_TYPE,
123265  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_3_WIDTH },
123266  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_4_CHECKER_TYPE,
123267  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_4_WIDTH },
123268  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_5_CHECKER_TYPE,
123269  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_5_WIDTH },
123270  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_6_CHECKER_TYPE,
123271  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_6_WIDTH },
123272  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_7_CHECKER_TYPE,
123273  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_7_WIDTH },
123274  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_8_CHECKER_TYPE,
123275  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_8_WIDTH },
123276  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_9_CHECKER_TYPE,
123277  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_9_WIDTH },
123278  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_10_CHECKER_TYPE,
123279  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_10_WIDTH },
123280  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_11_CHECKER_TYPE,
123281  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_11_WIDTH },
123282  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_12_CHECKER_TYPE,
123283  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_12_WIDTH },
123284  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_13_CHECKER_TYPE,
123285  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_13_WIDTH },
123286  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_14_CHECKER_TYPE,
123287  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_GROUP_14_WIDTH },
123288 };
123289 
123295 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_MAX_NUM_CHECKERS] =
123296 {
123297  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_0_CHECKER_TYPE,
123298  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_0_WIDTH },
123299  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_1_CHECKER_TYPE,
123300  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_1_WIDTH },
123301  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_2_CHECKER_TYPE,
123302  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_2_WIDTH },
123303  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_3_CHECKER_TYPE,
123304  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_3_WIDTH },
123305  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_4_CHECKER_TYPE,
123306  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_4_WIDTH },
123307  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_5_CHECKER_TYPE,
123308  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_5_WIDTH },
123309  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_6_CHECKER_TYPE,
123310  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_6_WIDTH },
123311  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_7_CHECKER_TYPE,
123312  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_7_WIDTH },
123313  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_8_CHECKER_TYPE,
123314  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_8_WIDTH },
123315  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_9_CHECKER_TYPE,
123316  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_9_WIDTH },
123317  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_10_CHECKER_TYPE,
123318  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_10_WIDTH },
123319  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_11_CHECKER_TYPE,
123320  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_11_WIDTH },
123321  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_12_CHECKER_TYPE,
123322  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_12_WIDTH },
123323  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_13_CHECKER_TYPE,
123324  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_13_WIDTH },
123325  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_14_CHECKER_TYPE,
123326  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_14_WIDTH },
123327  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_15_CHECKER_TYPE,
123328  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_15_WIDTH },
123329  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_16_CHECKER_TYPE,
123330  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_16_WIDTH },
123331  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_17_CHECKER_TYPE,
123332  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_17_WIDTH },
123333  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_18_CHECKER_TYPE,
123334  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_18_WIDTH },
123335  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_19_CHECKER_TYPE,
123336  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_19_WIDTH },
123337  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_20_CHECKER_TYPE,
123338  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_20_WIDTH },
123339  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_21_CHECKER_TYPE,
123340  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_21_WIDTH },
123341  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_22_CHECKER_TYPE,
123342  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_22_WIDTH },
123343  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_23_CHECKER_TYPE,
123344  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_23_WIDTH },
123345  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_24_CHECKER_TYPE,
123346  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_24_WIDTH },
123347  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_25_CHECKER_TYPE,
123348  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_25_WIDTH },
123349  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_26_CHECKER_TYPE,
123350  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_26_WIDTH },
123351  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_27_CHECKER_TYPE,
123352  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_27_WIDTH },
123353  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_28_CHECKER_TYPE,
123354  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_28_WIDTH },
123355  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_29_CHECKER_TYPE,
123356  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_29_WIDTH },
123357  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_30_CHECKER_TYPE,
123358  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_30_WIDTH },
123359  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_31_CHECKER_TYPE,
123360  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_31_WIDTH },
123361  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_32_CHECKER_TYPE,
123362  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_32_WIDTH },
123363  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_33_CHECKER_TYPE,
123364  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_33_WIDTH },
123365  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_34_CHECKER_TYPE,
123366  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_34_WIDTH },
123367  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_35_CHECKER_TYPE,
123368  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_35_WIDTH },
123369  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_36_CHECKER_TYPE,
123370  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_36_WIDTH },
123371  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_37_CHECKER_TYPE,
123372  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_37_WIDTH },
123373  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_38_CHECKER_TYPE,
123374  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_38_WIDTH },
123375  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_39_CHECKER_TYPE,
123376  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_39_WIDTH },
123377  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_40_CHECKER_TYPE,
123378  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_40_WIDTH },
123379  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_41_CHECKER_TYPE,
123380  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_41_WIDTH },
123381  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_42_CHECKER_TYPE,
123382  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_42_WIDTH },
123383  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_43_CHECKER_TYPE,
123384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_43_WIDTH },
123385  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_44_CHECKER_TYPE,
123386  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_44_WIDTH },
123387  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_45_CHECKER_TYPE,
123388  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_45_WIDTH },
123389  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_46_CHECKER_TYPE,
123390  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_46_WIDTH },
123391  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_47_CHECKER_TYPE,
123392  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_47_WIDTH },
123393  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_48_CHECKER_TYPE,
123394  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_48_WIDTH },
123395  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_49_CHECKER_TYPE,
123396  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_49_WIDTH },
123397  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_50_CHECKER_TYPE,
123398  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_50_WIDTH },
123399  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_51_CHECKER_TYPE,
123400  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_51_WIDTH },
123401  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_52_CHECKER_TYPE,
123402  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_52_WIDTH },
123403  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_53_CHECKER_TYPE,
123404  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_53_WIDTH },
123405  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_54_CHECKER_TYPE,
123406  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_54_WIDTH },
123407  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_55_CHECKER_TYPE,
123408  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_GROUP_55_WIDTH },
123409 };
123410 
123416 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_MAX_NUM_CHECKERS] =
123417 {
123418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_0_CHECKER_TYPE,
123419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_0_WIDTH },
123420  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_1_CHECKER_TYPE,
123421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_1_WIDTH },
123422  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_2_CHECKER_TYPE,
123423  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_GROUP_2_WIDTH },
123424 };
123425 
123431 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_MAX_NUM_CHECKERS] =
123432 {
123433  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_0_CHECKER_TYPE,
123434  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_0_WIDTH },
123435  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_1_CHECKER_TYPE,
123436  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_1_WIDTH },
123437  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_2_CHECKER_TYPE,
123438  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_2_WIDTH },
123439  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_3_CHECKER_TYPE,
123440  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_3_WIDTH },
123441  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_4_CHECKER_TYPE,
123442  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_4_WIDTH },
123443  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_5_CHECKER_TYPE,
123444  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_5_WIDTH },
123445  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_6_CHECKER_TYPE,
123446  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_GROUP_6_WIDTH },
123447 };
123448 
123454 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_MAX_NUM_CHECKERS] =
123455 {
123456  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_0_CHECKER_TYPE,
123457  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_0_WIDTH },
123458  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_1_CHECKER_TYPE,
123459  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_1_WIDTH },
123460  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_2_CHECKER_TYPE,
123461  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_2_WIDTH },
123462  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_3_CHECKER_TYPE,
123463  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_3_WIDTH },
123464  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_4_CHECKER_TYPE,
123465  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_4_WIDTH },
123466  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_5_CHECKER_TYPE,
123467  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_5_WIDTH },
123468  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_6_CHECKER_TYPE,
123469  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_6_WIDTH },
123470  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_7_CHECKER_TYPE,
123471  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_7_WIDTH },
123472  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_8_CHECKER_TYPE,
123473  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_8_WIDTH },
123474  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_9_CHECKER_TYPE,
123475  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_9_WIDTH },
123476  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_10_CHECKER_TYPE,
123477  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_10_WIDTH },
123478  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_11_CHECKER_TYPE,
123479  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_11_WIDTH },
123480  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_12_CHECKER_TYPE,
123481  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_12_WIDTH },
123482  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_13_CHECKER_TYPE,
123483  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_13_WIDTH },
123484  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_14_CHECKER_TYPE,
123485  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_14_WIDTH },
123486  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_15_CHECKER_TYPE,
123487  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_15_WIDTH },
123488  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_16_CHECKER_TYPE,
123489  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_16_WIDTH },
123490  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_17_CHECKER_TYPE,
123491  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_17_WIDTH },
123492  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_18_CHECKER_TYPE,
123493  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_18_WIDTH },
123494  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_19_CHECKER_TYPE,
123495  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_19_WIDTH },
123496  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_20_CHECKER_TYPE,
123497  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_20_WIDTH },
123498  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_21_CHECKER_TYPE,
123499  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_21_WIDTH },
123500  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_22_CHECKER_TYPE,
123501  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_22_WIDTH },
123502  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_23_CHECKER_TYPE,
123503  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_23_WIDTH },
123504  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_24_CHECKER_TYPE,
123505  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_24_WIDTH },
123506  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_25_CHECKER_TYPE,
123507  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_25_WIDTH },
123508  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_26_CHECKER_TYPE,
123509  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_26_WIDTH },
123510  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_27_CHECKER_TYPE,
123511  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_27_WIDTH },
123512  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_28_CHECKER_TYPE,
123513  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_28_WIDTH },
123514  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_29_CHECKER_TYPE,
123515  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_29_WIDTH },
123516  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_30_CHECKER_TYPE,
123517  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_30_WIDTH },
123518  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_31_CHECKER_TYPE,
123519  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_31_WIDTH },
123520  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_32_CHECKER_TYPE,
123521  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_32_WIDTH },
123522  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_33_CHECKER_TYPE,
123523  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_33_WIDTH },
123524  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_34_CHECKER_TYPE,
123525  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_34_WIDTH },
123526  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_35_CHECKER_TYPE,
123527  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_35_WIDTH },
123528  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_36_CHECKER_TYPE,
123529  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_36_WIDTH },
123530  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_37_CHECKER_TYPE,
123531  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_37_WIDTH },
123532  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_38_CHECKER_TYPE,
123533  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_38_WIDTH },
123534  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_39_CHECKER_TYPE,
123535  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_39_WIDTH },
123536  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_40_CHECKER_TYPE,
123537  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_40_WIDTH },
123538  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_41_CHECKER_TYPE,
123539  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_41_WIDTH },
123540  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_42_CHECKER_TYPE,
123541  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_42_WIDTH },
123542  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_43_CHECKER_TYPE,
123543  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_43_WIDTH },
123544  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_44_CHECKER_TYPE,
123545  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_44_WIDTH },
123546  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_45_CHECKER_TYPE,
123547  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_45_WIDTH },
123548  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_46_CHECKER_TYPE,
123549  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_46_WIDTH },
123550  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_47_CHECKER_TYPE,
123551  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_47_WIDTH },
123552  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_48_CHECKER_TYPE,
123553  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_48_WIDTH },
123554  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_49_CHECKER_TYPE,
123555  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_49_WIDTH },
123556  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_50_CHECKER_TYPE,
123557  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_50_WIDTH },
123558  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_51_CHECKER_TYPE,
123559  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_51_WIDTH },
123560  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_52_CHECKER_TYPE,
123561  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_52_WIDTH },
123562  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_53_CHECKER_TYPE,
123563  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_53_WIDTH },
123564  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_54_CHECKER_TYPE,
123565  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_54_WIDTH },
123566  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_55_CHECKER_TYPE,
123567  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_55_WIDTH },
123568  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_56_CHECKER_TYPE,
123569  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_56_WIDTH },
123570  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_57_CHECKER_TYPE,
123571  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_57_WIDTH },
123572  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_58_CHECKER_TYPE,
123573  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_58_WIDTH },
123574  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_59_CHECKER_TYPE,
123575  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_59_WIDTH },
123576  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_60_CHECKER_TYPE,
123577  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_60_WIDTH },
123578  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_61_CHECKER_TYPE,
123579  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_61_WIDTH },
123580  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_62_CHECKER_TYPE,
123581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_62_WIDTH },
123582  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_63_CHECKER_TYPE,
123583  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_63_WIDTH },
123584  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_64_CHECKER_TYPE,
123585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_64_WIDTH },
123586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_65_CHECKER_TYPE,
123587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_65_WIDTH },
123588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_66_CHECKER_TYPE,
123589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_66_WIDTH },
123590  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_67_CHECKER_TYPE,
123591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_67_WIDTH },
123592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_68_CHECKER_TYPE,
123593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_68_WIDTH },
123594  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_69_CHECKER_TYPE,
123595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_69_WIDTH },
123596  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_70_CHECKER_TYPE,
123597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_70_WIDTH },
123598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_71_CHECKER_TYPE,
123599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_71_WIDTH },
123600  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_72_CHECKER_TYPE,
123601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_72_WIDTH },
123602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_73_CHECKER_TYPE,
123603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_73_WIDTH },
123604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_74_CHECKER_TYPE,
123605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_74_WIDTH },
123606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_75_CHECKER_TYPE,
123607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_75_WIDTH },
123608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_76_CHECKER_TYPE,
123609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_76_WIDTH },
123610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_77_CHECKER_TYPE,
123611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_77_WIDTH },
123612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_78_CHECKER_TYPE,
123613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_78_WIDTH },
123614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_79_CHECKER_TYPE,
123615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_79_WIDTH },
123616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_80_CHECKER_TYPE,
123617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_80_WIDTH },
123618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_81_CHECKER_TYPE,
123619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_81_WIDTH },
123620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_82_CHECKER_TYPE,
123621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_82_WIDTH },
123622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_83_CHECKER_TYPE,
123623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_83_WIDTH },
123624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_84_CHECKER_TYPE,
123625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_84_WIDTH },
123626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_85_CHECKER_TYPE,
123627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_85_WIDTH },
123628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_86_CHECKER_TYPE,
123629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_86_WIDTH },
123630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_87_CHECKER_TYPE,
123631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_87_WIDTH },
123632  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_88_CHECKER_TYPE,
123633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_88_WIDTH },
123634  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_89_CHECKER_TYPE,
123635  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_89_WIDTH },
123636  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_90_CHECKER_TYPE,
123637  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_90_WIDTH },
123638  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_91_CHECKER_TYPE,
123639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_91_WIDTH },
123640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_92_CHECKER_TYPE,
123641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_92_WIDTH },
123642  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_93_CHECKER_TYPE,
123643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_93_WIDTH },
123644  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_94_CHECKER_TYPE,
123645  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_94_WIDTH },
123646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_95_CHECKER_TYPE,
123647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_95_WIDTH },
123648  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_96_CHECKER_TYPE,
123649  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_96_WIDTH },
123650  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_97_CHECKER_TYPE,
123651  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_GROUP_97_WIDTH },
123652 };
123653 
123659 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_MAX_NUM_CHECKERS] =
123660 {
123661  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_0_CHECKER_TYPE,
123662  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_0_WIDTH },
123663  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_1_CHECKER_TYPE,
123664  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_1_WIDTH },
123665  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_2_CHECKER_TYPE,
123666  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_2_WIDTH },
123667  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_3_CHECKER_TYPE,
123668  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_GROUP_3_WIDTH },
123669 };
123670 
123676 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS] =
123677 {
123678  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
123679  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
123680  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
123681  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
123682  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
123683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
123684  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
123685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
123686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
123687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_4_WIDTH },
123688  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
123689  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_5_WIDTH },
123690  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
123691  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_6_WIDTH },
123692  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
123693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_7_WIDTH },
123694  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
123695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_8_WIDTH },
123696  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
123697  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_9_WIDTH },
123698  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
123699  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_10_WIDTH },
123700  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
123701  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_11_WIDTH },
123702  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
123703  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_12_WIDTH },
123704  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
123705  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_13_WIDTH },
123706  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
123707  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_14_WIDTH },
123708  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
123709  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_15_WIDTH },
123710  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
123711  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_16_WIDTH },
123712  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
123713  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_17_WIDTH },
123714  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
123715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_18_WIDTH },
123716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
123717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_19_WIDTH },
123718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
123719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_20_WIDTH },
123720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
123721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_21_WIDTH },
123722  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
123723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_22_WIDTH },
123724  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
123725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_23_WIDTH },
123726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
123727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_24_WIDTH },
123728  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
123729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_25_WIDTH },
123730  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
123731  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_26_WIDTH },
123732  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
123733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_27_WIDTH },
123734  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
123735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_28_WIDTH },
123736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
123737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_29_WIDTH },
123738  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
123739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_GROUP_30_WIDTH },
123740 };
123741 
123747 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_MAX_NUM_CHECKERS] =
123748 {
123749  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_0_CHECKER_TYPE,
123750  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_0_WIDTH },
123751  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_1_CHECKER_TYPE,
123752  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_1_WIDTH },
123753  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_2_CHECKER_TYPE,
123754  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_2_WIDTH },
123755  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_3_CHECKER_TYPE,
123756  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_3_WIDTH },
123757  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_4_CHECKER_TYPE,
123758  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_4_WIDTH },
123759  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_5_CHECKER_TYPE,
123760  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_5_WIDTH },
123761  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_6_CHECKER_TYPE,
123762  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_6_WIDTH },
123763  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_7_CHECKER_TYPE,
123764  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_7_WIDTH },
123765  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_8_CHECKER_TYPE,
123766  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_8_WIDTH },
123767  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_9_CHECKER_TYPE,
123768  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_9_WIDTH },
123769  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_10_CHECKER_TYPE,
123770  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_10_WIDTH },
123771  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_11_CHECKER_TYPE,
123772  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_11_WIDTH },
123773  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_12_CHECKER_TYPE,
123774  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_12_WIDTH },
123775  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_13_CHECKER_TYPE,
123776  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_13_WIDTH },
123777  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_14_CHECKER_TYPE,
123778  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_14_WIDTH },
123779  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_15_CHECKER_TYPE,
123780  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_15_WIDTH },
123781  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_16_CHECKER_TYPE,
123782  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_16_WIDTH },
123783  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_17_CHECKER_TYPE,
123784  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_17_WIDTH },
123785  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_18_CHECKER_TYPE,
123786  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_18_WIDTH },
123787  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_19_CHECKER_TYPE,
123788  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_19_WIDTH },
123789  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_20_CHECKER_TYPE,
123790  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_20_WIDTH },
123791  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_21_CHECKER_TYPE,
123792  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_21_WIDTH },
123793  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_22_CHECKER_TYPE,
123794  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_22_WIDTH },
123795  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_23_CHECKER_TYPE,
123796  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_23_WIDTH },
123797  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_24_CHECKER_TYPE,
123798  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_GROUP_24_WIDTH },
123799 };
123800 
123806 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_MAX_NUM_CHECKERS] =
123807 {
123808  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_0_CHECKER_TYPE,
123809  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_0_WIDTH },
123810  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_1_CHECKER_TYPE,
123811  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_1_WIDTH },
123812  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_2_CHECKER_TYPE,
123813  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_2_WIDTH },
123814  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_3_CHECKER_TYPE,
123815  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_3_WIDTH },
123816  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_4_CHECKER_TYPE,
123817  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_4_WIDTH },
123818  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_5_CHECKER_TYPE,
123819  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_5_WIDTH },
123820  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_6_CHECKER_TYPE,
123821  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_6_WIDTH },
123822  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_7_CHECKER_TYPE,
123823  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_7_WIDTH },
123824  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_8_CHECKER_TYPE,
123825  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_8_WIDTH },
123826  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_9_CHECKER_TYPE,
123827  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_9_WIDTH },
123828  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_10_CHECKER_TYPE,
123829  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_10_WIDTH },
123830  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_11_CHECKER_TYPE,
123831  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_11_WIDTH },
123832  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_12_CHECKER_TYPE,
123833  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_12_WIDTH },
123834  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_13_CHECKER_TYPE,
123835  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_13_WIDTH },
123836  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_14_CHECKER_TYPE,
123837  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_14_WIDTH },
123838  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_15_CHECKER_TYPE,
123839  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_15_WIDTH },
123840  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_16_CHECKER_TYPE,
123841  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_16_WIDTH },
123842  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_17_CHECKER_TYPE,
123843  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_GROUP_17_WIDTH },
123844 };
123845 
123851 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_MAX_NUM_CHECKERS] =
123852 {
123853  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_0_CHECKER_TYPE,
123854  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_0_WIDTH },
123855  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_1_CHECKER_TYPE,
123856  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_1_WIDTH },
123857  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_2_CHECKER_TYPE,
123858  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_2_WIDTH },
123859  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_3_CHECKER_TYPE,
123860  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_3_WIDTH },
123861  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_4_CHECKER_TYPE,
123862  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_4_WIDTH },
123863  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_5_CHECKER_TYPE,
123864  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_5_WIDTH },
123865  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_6_CHECKER_TYPE,
123866  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_6_WIDTH },
123867  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_7_CHECKER_TYPE,
123868  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_7_WIDTH },
123869  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_8_CHECKER_TYPE,
123870  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_8_WIDTH },
123871  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_9_CHECKER_TYPE,
123872  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_9_WIDTH },
123873  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_10_CHECKER_TYPE,
123874  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_10_WIDTH },
123875  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_11_CHECKER_TYPE,
123876  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_11_WIDTH },
123877  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_12_CHECKER_TYPE,
123878  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_12_WIDTH },
123879  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_13_CHECKER_TYPE,
123880  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_13_WIDTH },
123881  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_14_CHECKER_TYPE,
123882  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_14_WIDTH },
123883  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_15_CHECKER_TYPE,
123884  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_15_WIDTH },
123885  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_16_CHECKER_TYPE,
123886  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_16_WIDTH },
123887  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_17_CHECKER_TYPE,
123888  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_17_WIDTH },
123889  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_18_CHECKER_TYPE,
123890  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_18_WIDTH },
123891  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_19_CHECKER_TYPE,
123892  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_19_WIDTH },
123893  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_20_CHECKER_TYPE,
123894  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_20_WIDTH },
123895  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_21_CHECKER_TYPE,
123896  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_21_WIDTH },
123897  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_22_CHECKER_TYPE,
123898  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_22_WIDTH },
123899  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_23_CHECKER_TYPE,
123900  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_23_WIDTH },
123901  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_24_CHECKER_TYPE,
123902  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_24_WIDTH },
123903  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_25_CHECKER_TYPE,
123904  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_25_WIDTH },
123905  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_26_CHECKER_TYPE,
123906  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_26_WIDTH },
123907  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_27_CHECKER_TYPE,
123908  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_27_WIDTH },
123909  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_28_CHECKER_TYPE,
123910  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_28_WIDTH },
123911  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_29_CHECKER_TYPE,
123912  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_29_WIDTH },
123913  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_30_CHECKER_TYPE,
123914  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_30_WIDTH },
123915  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_31_CHECKER_TYPE,
123916  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_31_WIDTH },
123917  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_32_CHECKER_TYPE,
123918  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_32_WIDTH },
123919  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_33_CHECKER_TYPE,
123920  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_33_WIDTH },
123921  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_34_CHECKER_TYPE,
123922  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_34_WIDTH },
123923  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_35_CHECKER_TYPE,
123924  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_35_WIDTH },
123925  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_36_CHECKER_TYPE,
123926  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_36_WIDTH },
123927  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_37_CHECKER_TYPE,
123928  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_37_WIDTH },
123929  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_38_CHECKER_TYPE,
123930  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_38_WIDTH },
123931  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_39_CHECKER_TYPE,
123932  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_39_WIDTH },
123933  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_40_CHECKER_TYPE,
123934  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_40_WIDTH },
123935  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_41_CHECKER_TYPE,
123936  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_41_WIDTH },
123937  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_42_CHECKER_TYPE,
123938  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_42_WIDTH },
123939  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_43_CHECKER_TYPE,
123940  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_43_WIDTH },
123941  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_44_CHECKER_TYPE,
123942  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_GROUP_44_WIDTH },
123943 };
123944 
123950 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_MAX_NUM_CHECKERS] =
123951 {
123952  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_0_CHECKER_TYPE,
123953  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_0_WIDTH },
123954  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_1_CHECKER_TYPE,
123955  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_1_WIDTH },
123956  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_2_CHECKER_TYPE,
123957  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_2_WIDTH },
123958  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_3_CHECKER_TYPE,
123959  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_GROUP_3_WIDTH },
123960 };
123961 
123967 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_MAX_NUM_CHECKERS] =
123968 {
123969  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_0_CHECKER_TYPE,
123970  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_0_WIDTH },
123971  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_1_CHECKER_TYPE,
123972  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_1_WIDTH },
123973  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_2_CHECKER_TYPE,
123974  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_2_WIDTH },
123975  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_3_CHECKER_TYPE,
123976  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_3_WIDTH },
123977  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_4_CHECKER_TYPE,
123978  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_4_WIDTH },
123979  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_5_CHECKER_TYPE,
123980  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_5_WIDTH },
123981  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_6_CHECKER_TYPE,
123982  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_6_WIDTH },
123983  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_7_CHECKER_TYPE,
123984  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_7_WIDTH },
123985  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_8_CHECKER_TYPE,
123986  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_8_WIDTH },
123987  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_9_CHECKER_TYPE,
123988  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_9_WIDTH },
123989  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_10_CHECKER_TYPE,
123990  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_10_WIDTH },
123991  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_11_CHECKER_TYPE,
123992  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_11_WIDTH },
123993  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_12_CHECKER_TYPE,
123994  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_12_WIDTH },
123995  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_13_CHECKER_TYPE,
123996  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_13_WIDTH },
123997  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_14_CHECKER_TYPE,
123998  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_14_WIDTH },
123999  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_15_CHECKER_TYPE,
124000  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_GROUP_15_WIDTH },
124001 };
124002 
124008 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS] =
124009 {
124010  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_CHECKER_TYPE,
124011  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_WIDTH },
124012  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_CHECKER_TYPE,
124013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_WIDTH },
124014  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_CHECKER_TYPE,
124015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_WIDTH },
124016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_CHECKER_TYPE,
124017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_WIDTH },
124018  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_CHECKER_TYPE,
124019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_WIDTH },
124020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_CHECKER_TYPE,
124021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_WIDTH },
124022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_CHECKER_TYPE,
124023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_WIDTH },
124024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_CHECKER_TYPE,
124025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_WIDTH },
124026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_CHECKER_TYPE,
124027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_WIDTH },
124028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_CHECKER_TYPE,
124029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_WIDTH },
124030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_CHECKER_TYPE,
124031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_WIDTH },
124032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_CHECKER_TYPE,
124033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_WIDTH },
124034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_CHECKER_TYPE,
124035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_WIDTH },
124036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_CHECKER_TYPE,
124037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_WIDTH },
124038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_CHECKER_TYPE,
124039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_WIDTH },
124040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_CHECKER_TYPE,
124041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_WIDTH },
124042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_CHECKER_TYPE,
124043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_WIDTH },
124044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_CHECKER_TYPE,
124045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_WIDTH },
124046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_CHECKER_TYPE,
124047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_WIDTH },
124048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_CHECKER_TYPE,
124049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_WIDTH },
124050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_CHECKER_TYPE,
124051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_WIDTH },
124052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_CHECKER_TYPE,
124053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_WIDTH },
124054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_CHECKER_TYPE,
124055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_WIDTH },
124056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_CHECKER_TYPE,
124057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_WIDTH },
124058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_CHECKER_TYPE,
124059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_WIDTH },
124060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_CHECKER_TYPE,
124061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_WIDTH },
124062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_CHECKER_TYPE,
124063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_WIDTH },
124064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_CHECKER_TYPE,
124065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_WIDTH },
124066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_CHECKER_TYPE,
124067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_WIDTH },
124068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_CHECKER_TYPE,
124069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_WIDTH },
124070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_CHECKER_TYPE,
124071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_WIDTH },
124072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_CHECKER_TYPE,
124073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_WIDTH },
124074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_CHECKER_TYPE,
124075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_WIDTH },
124076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_CHECKER_TYPE,
124077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_WIDTH },
124078 };
124079 
124085 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_MAX_NUM_CHECKERS] =
124086 {
124087  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_0_CHECKER_TYPE,
124088  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_0_WIDTH },
124089  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_1_CHECKER_TYPE,
124090  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_GROUP_1_WIDTH },
124091 };
124092 
124098 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124099 {
124100  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124101  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124102  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124103  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124104  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124105  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124106  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124107  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124108  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124109  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124110  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124111  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124112  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124113  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124114  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124115  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124116  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124117  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124118  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
124119  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
124120  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_10_CHECKER_TYPE,
124121  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_10_WIDTH },
124122  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_11_CHECKER_TYPE,
124123  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_11_WIDTH },
124124  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_12_CHECKER_TYPE,
124125  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_12_WIDTH },
124126  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_13_CHECKER_TYPE,
124127  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_13_WIDTH },
124128  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_14_CHECKER_TYPE,
124129  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_14_WIDTH },
124130  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_15_CHECKER_TYPE,
124131  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_15_WIDTH },
124132  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_16_CHECKER_TYPE,
124133  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_16_WIDTH },
124134  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_17_CHECKER_TYPE,
124135  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_17_WIDTH },
124136  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_18_CHECKER_TYPE,
124137  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_18_WIDTH },
124138  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_19_CHECKER_TYPE,
124139  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_19_WIDTH },
124140  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_20_CHECKER_TYPE,
124141  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_20_WIDTH },
124142  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_21_CHECKER_TYPE,
124143  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_21_WIDTH },
124144  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_22_CHECKER_TYPE,
124145  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_22_WIDTH },
124146  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_23_CHECKER_TYPE,
124147  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_23_WIDTH },
124148  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_24_CHECKER_TYPE,
124149  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_24_WIDTH },
124150  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_25_CHECKER_TYPE,
124151  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_25_WIDTH },
124152  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_26_CHECKER_TYPE,
124153  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_26_WIDTH },
124154  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_27_CHECKER_TYPE,
124155  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_27_WIDTH },
124156  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_28_CHECKER_TYPE,
124157  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_28_WIDTH },
124158  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_29_CHECKER_TYPE,
124159  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_29_WIDTH },
124160  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_30_CHECKER_TYPE,
124161  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_30_WIDTH },
124162  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_31_CHECKER_TYPE,
124163  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_31_WIDTH },
124164  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_32_CHECKER_TYPE,
124165  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_32_WIDTH },
124166  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_33_CHECKER_TYPE,
124167  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_33_WIDTH },
124168  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_34_CHECKER_TYPE,
124169  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_34_WIDTH },
124170  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_35_CHECKER_TYPE,
124171  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_35_WIDTH },
124172  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_36_CHECKER_TYPE,
124173  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_36_WIDTH },
124174  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_37_CHECKER_TYPE,
124175  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_37_WIDTH },
124176  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_38_CHECKER_TYPE,
124177  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_38_WIDTH },
124178  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_39_CHECKER_TYPE,
124179  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_39_WIDTH },
124180  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_40_CHECKER_TYPE,
124181  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_40_WIDTH },
124182  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_41_CHECKER_TYPE,
124183  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_41_WIDTH },
124184  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_42_CHECKER_TYPE,
124185  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_42_WIDTH },
124186  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_43_CHECKER_TYPE,
124187  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_43_WIDTH },
124188  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_44_CHECKER_TYPE,
124189  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_44_WIDTH },
124190  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_45_CHECKER_TYPE,
124191  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_45_WIDTH },
124192  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_46_CHECKER_TYPE,
124193  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_46_WIDTH },
124194  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_47_CHECKER_TYPE,
124195  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_47_WIDTH },
124196  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_48_CHECKER_TYPE,
124197  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_48_WIDTH },
124198  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_49_CHECKER_TYPE,
124199  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_49_WIDTH },
124200  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_50_CHECKER_TYPE,
124201  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_50_WIDTH },
124202  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_51_CHECKER_TYPE,
124203  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_51_WIDTH },
124204  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_52_CHECKER_TYPE,
124205  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_52_WIDTH },
124206  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_53_CHECKER_TYPE,
124207  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_53_WIDTH },
124208  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_54_CHECKER_TYPE,
124209  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_54_WIDTH },
124210  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_55_CHECKER_TYPE,
124211  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_55_WIDTH },
124212  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_56_CHECKER_TYPE,
124213  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_56_WIDTH },
124214  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_57_CHECKER_TYPE,
124215  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_57_WIDTH },
124216  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_58_CHECKER_TYPE,
124217  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_GROUP_58_WIDTH },
124218 };
124219 
124225 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124226 {
124227  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124228  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124229  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124230  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124231  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124232  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124233  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124234  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124235  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124236  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124237  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124238  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124239  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124240  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124241  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124242  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124243  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124244  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124245  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
124246  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
124247  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_10_CHECKER_TYPE,
124248  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_10_WIDTH },
124249  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_11_CHECKER_TYPE,
124250  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_11_WIDTH },
124251  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_12_CHECKER_TYPE,
124252  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_12_WIDTH },
124253  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_13_CHECKER_TYPE,
124254  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_13_WIDTH },
124255  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_14_CHECKER_TYPE,
124256  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_14_WIDTH },
124257  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_15_CHECKER_TYPE,
124258  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_15_WIDTH },
124259  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_16_CHECKER_TYPE,
124260  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_16_WIDTH },
124261  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_17_CHECKER_TYPE,
124262  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_17_WIDTH },
124263  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_18_CHECKER_TYPE,
124264  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_18_WIDTH },
124265  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_19_CHECKER_TYPE,
124266  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_19_WIDTH },
124267  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_20_CHECKER_TYPE,
124268  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_20_WIDTH },
124269  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_21_CHECKER_TYPE,
124270  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_21_WIDTH },
124271  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_22_CHECKER_TYPE,
124272  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_22_WIDTH },
124273  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_23_CHECKER_TYPE,
124274  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_23_WIDTH },
124275  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_24_CHECKER_TYPE,
124276  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_24_WIDTH },
124277  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_25_CHECKER_TYPE,
124278  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_25_WIDTH },
124279  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_26_CHECKER_TYPE,
124280  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_26_WIDTH },
124281  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_27_CHECKER_TYPE,
124282  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_27_WIDTH },
124283  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_28_CHECKER_TYPE,
124284  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_28_WIDTH },
124285  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_29_CHECKER_TYPE,
124286  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_29_WIDTH },
124287  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_30_CHECKER_TYPE,
124288  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_30_WIDTH },
124289  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_31_CHECKER_TYPE,
124290  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_31_WIDTH },
124291  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_32_CHECKER_TYPE,
124292  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_32_WIDTH },
124293  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_33_CHECKER_TYPE,
124294  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_33_WIDTH },
124295  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_34_CHECKER_TYPE,
124296  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_34_WIDTH },
124297  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_35_CHECKER_TYPE,
124298  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_35_WIDTH },
124299  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_36_CHECKER_TYPE,
124300  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_36_WIDTH },
124301  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_37_CHECKER_TYPE,
124302  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_37_WIDTH },
124303  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_38_CHECKER_TYPE,
124304  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_38_WIDTH },
124305  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_39_CHECKER_TYPE,
124306  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_39_WIDTH },
124307  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_40_CHECKER_TYPE,
124308  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_40_WIDTH },
124309  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_41_CHECKER_TYPE,
124310  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_41_WIDTH },
124311  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_42_CHECKER_TYPE,
124312  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_42_WIDTH },
124313  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_43_CHECKER_TYPE,
124314  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_43_WIDTH },
124315  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_44_CHECKER_TYPE,
124316  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_44_WIDTH },
124317  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_45_CHECKER_TYPE,
124318  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_45_WIDTH },
124319  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_46_CHECKER_TYPE,
124320  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_46_WIDTH },
124321  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_47_CHECKER_TYPE,
124322  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_47_WIDTH },
124323  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_48_CHECKER_TYPE,
124324  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_48_WIDTH },
124325  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_49_CHECKER_TYPE,
124326  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_49_WIDTH },
124327  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_50_CHECKER_TYPE,
124328  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_50_WIDTH },
124329  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_51_CHECKER_TYPE,
124330  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_51_WIDTH },
124331  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_52_CHECKER_TYPE,
124332  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_52_WIDTH },
124333  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_53_CHECKER_TYPE,
124334  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_53_WIDTH },
124335  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_54_CHECKER_TYPE,
124336  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_54_WIDTH },
124337  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_55_CHECKER_TYPE,
124338  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_55_WIDTH },
124339  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_56_CHECKER_TYPE,
124340  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_56_WIDTH },
124341  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_57_CHECKER_TYPE,
124342  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_57_WIDTH },
124343  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_58_CHECKER_TYPE,
124344  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_GROUP_58_WIDTH },
124345 };
124346 
124352 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124353 {
124354  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124355  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124356  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124357  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124358  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124359  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124360  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124361  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124362  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124363  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124364  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124365  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124366  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124367  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124368  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124369  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124370 };
124371 
124377 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124378 {
124379  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124380  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124381  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124382  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124383  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124385  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124386  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124387  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124388  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124389  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124390  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124391  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124392  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124393  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124394  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124395 };
124396 
124402 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_MAX_NUM_CHECKERS] =
124403 {
124404  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
124405  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_0_WIDTH },
124406  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
124407  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_1_WIDTH },
124408  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
124409  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_2_WIDTH },
124410  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
124411  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_3_WIDTH },
124412  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
124413  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_4_WIDTH },
124414  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
124415  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_5_WIDTH },
124416  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
124417  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_6_WIDTH },
124418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
124419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_7_WIDTH },
124420  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
124421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_8_WIDTH },
124422  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
124423  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_9_WIDTH },
124424  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
124425  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_10_WIDTH },
124426  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
124427  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_11_WIDTH },
124428  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
124429  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_12_WIDTH },
124430  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
124431  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_13_WIDTH },
124432  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
124433  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_14_WIDTH },
124434  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
124435  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_15_WIDTH },
124436  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
124437  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_16_WIDTH },
124438  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
124439  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_17_WIDTH },
124440  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
124441  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_18_WIDTH },
124442  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
124443  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_19_WIDTH },
124444  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
124445  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_20_WIDTH },
124446  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
124447  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_21_WIDTH },
124448  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
124449  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_22_WIDTH },
124450  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
124451  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_23_WIDTH },
124452  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
124453  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_24_WIDTH },
124454  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
124455  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_25_WIDTH },
124456  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
124457  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_26_WIDTH },
124458  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_27_CHECKER_TYPE,
124459  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_27_WIDTH },
124460  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_28_CHECKER_TYPE,
124461  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_28_WIDTH },
124462  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_29_CHECKER_TYPE,
124463  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_29_WIDTH },
124464  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_30_CHECKER_TYPE,
124465  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_30_WIDTH },
124466  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_31_CHECKER_TYPE,
124467  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_31_WIDTH },
124468  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_32_CHECKER_TYPE,
124469  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_32_WIDTH },
124470  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_33_CHECKER_TYPE,
124471  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_33_WIDTH },
124472  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_34_CHECKER_TYPE,
124473  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_GROUP_34_WIDTH },
124474 };
124475 
124481 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_MAX_NUM_CHECKERS] =
124482 {
124483  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
124484  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_0_WIDTH },
124485  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
124486  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_1_WIDTH },
124487  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
124488  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_2_WIDTH },
124489  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
124490  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_3_WIDTH },
124491  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
124492  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_4_WIDTH },
124493  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
124494  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_5_WIDTH },
124495  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
124496  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_6_WIDTH },
124497  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
124498  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_7_WIDTH },
124499  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
124500  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_8_WIDTH },
124501  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
124502  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_9_WIDTH },
124503  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
124504  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_GROUP_10_WIDTH },
124505 };
124506 
124512 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124513 {
124514  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124515  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124516  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124517  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124518  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124519  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124520  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124521  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124522  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124523  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124524  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124525  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124526  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124527  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124528  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124529  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124530  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124531  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124532  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
124533  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
124534  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_10_CHECKER_TYPE,
124535  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_10_WIDTH },
124536  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_11_CHECKER_TYPE,
124537  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_11_WIDTH },
124538  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_12_CHECKER_TYPE,
124539  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_12_WIDTH },
124540  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_13_CHECKER_TYPE,
124541  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_13_WIDTH },
124542  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_14_CHECKER_TYPE,
124543  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_14_WIDTH },
124544  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_15_CHECKER_TYPE,
124545  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_15_WIDTH },
124546  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_16_CHECKER_TYPE,
124547  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_16_WIDTH },
124548  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_17_CHECKER_TYPE,
124549  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_17_WIDTH },
124550  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_18_CHECKER_TYPE,
124551  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_18_WIDTH },
124552  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_19_CHECKER_TYPE,
124553  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_19_WIDTH },
124554  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_20_CHECKER_TYPE,
124555  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_20_WIDTH },
124556  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_21_CHECKER_TYPE,
124557  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_21_WIDTH },
124558  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_22_CHECKER_TYPE,
124559  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_22_WIDTH },
124560  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_23_CHECKER_TYPE,
124561  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_23_WIDTH },
124562  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_24_CHECKER_TYPE,
124563  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_24_WIDTH },
124564  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_25_CHECKER_TYPE,
124565  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_25_WIDTH },
124566  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_26_CHECKER_TYPE,
124567  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_26_WIDTH },
124568  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_27_CHECKER_TYPE,
124569  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_27_WIDTH },
124570  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_28_CHECKER_TYPE,
124571  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_28_WIDTH },
124572  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_29_CHECKER_TYPE,
124573  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_29_WIDTH },
124574  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_30_CHECKER_TYPE,
124575  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_30_WIDTH },
124576  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_31_CHECKER_TYPE,
124577  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_31_WIDTH },
124578  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_32_CHECKER_TYPE,
124579  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_32_WIDTH },
124580  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_33_CHECKER_TYPE,
124581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_33_WIDTH },
124582  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_34_CHECKER_TYPE,
124583  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_34_WIDTH },
124584  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_35_CHECKER_TYPE,
124585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_35_WIDTH },
124586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_36_CHECKER_TYPE,
124587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_36_WIDTH },
124588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_37_CHECKER_TYPE,
124589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_37_WIDTH },
124590  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_38_CHECKER_TYPE,
124591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_38_WIDTH },
124592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_39_CHECKER_TYPE,
124593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_39_WIDTH },
124594  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_40_CHECKER_TYPE,
124595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_40_WIDTH },
124596  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_41_CHECKER_TYPE,
124597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_41_WIDTH },
124598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_42_CHECKER_TYPE,
124599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_42_WIDTH },
124600  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_43_CHECKER_TYPE,
124601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_43_WIDTH },
124602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_44_CHECKER_TYPE,
124603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_44_WIDTH },
124604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_45_CHECKER_TYPE,
124605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_45_WIDTH },
124606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_46_CHECKER_TYPE,
124607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_46_WIDTH },
124608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_47_CHECKER_TYPE,
124609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_47_WIDTH },
124610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_48_CHECKER_TYPE,
124611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_48_WIDTH },
124612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_49_CHECKER_TYPE,
124613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_49_WIDTH },
124614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_50_CHECKER_TYPE,
124615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_50_WIDTH },
124616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_51_CHECKER_TYPE,
124617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_51_WIDTH },
124618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_52_CHECKER_TYPE,
124619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_52_WIDTH },
124620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_53_CHECKER_TYPE,
124621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_53_WIDTH },
124622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_54_CHECKER_TYPE,
124623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_54_WIDTH },
124624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_55_CHECKER_TYPE,
124625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_55_WIDTH },
124626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_56_CHECKER_TYPE,
124627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_56_WIDTH },
124628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_57_CHECKER_TYPE,
124629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_57_WIDTH },
124630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_58_CHECKER_TYPE,
124631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_GROUP_58_WIDTH },
124632 };
124633 
124639 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124640 {
124641  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124642  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124643  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124644  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124645  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124646  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124647  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124648  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124649  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124650  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124651  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124652  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124653  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124654  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124655  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124656  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124657  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124658  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124659 };
124660 
124666 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124667 {
124668  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124669  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124670  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124671  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124672  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124673  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124674  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124675  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124676  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124677  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124678  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124679  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124680  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124681  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124682  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124684  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
124687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
124688  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_10_CHECKER_TYPE,
124689  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_10_WIDTH },
124690  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_11_CHECKER_TYPE,
124691  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_11_WIDTH },
124692  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_12_CHECKER_TYPE,
124693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_12_WIDTH },
124694  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_13_CHECKER_TYPE,
124695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_13_WIDTH },
124696  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_14_CHECKER_TYPE,
124697  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_14_WIDTH },
124698  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_15_CHECKER_TYPE,
124699  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_15_WIDTH },
124700  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_16_CHECKER_TYPE,
124701  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_16_WIDTH },
124702  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_17_CHECKER_TYPE,
124703  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_17_WIDTH },
124704  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_18_CHECKER_TYPE,
124705  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_18_WIDTH },
124706  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_19_CHECKER_TYPE,
124707  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_19_WIDTH },
124708  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_20_CHECKER_TYPE,
124709  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_20_WIDTH },
124710  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_21_CHECKER_TYPE,
124711  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_21_WIDTH },
124712  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_22_CHECKER_TYPE,
124713  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_22_WIDTH },
124714  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_23_CHECKER_TYPE,
124715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_23_WIDTH },
124716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_24_CHECKER_TYPE,
124717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_24_WIDTH },
124718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_25_CHECKER_TYPE,
124719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_25_WIDTH },
124720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_26_CHECKER_TYPE,
124721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_26_WIDTH },
124722  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_27_CHECKER_TYPE,
124723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_27_WIDTH },
124724  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_28_CHECKER_TYPE,
124725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_28_WIDTH },
124726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_29_CHECKER_TYPE,
124727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_29_WIDTH },
124728  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_30_CHECKER_TYPE,
124729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_30_WIDTH },
124730  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_31_CHECKER_TYPE,
124731  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_31_WIDTH },
124732  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_32_CHECKER_TYPE,
124733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_32_WIDTH },
124734  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_33_CHECKER_TYPE,
124735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_33_WIDTH },
124736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_34_CHECKER_TYPE,
124737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_34_WIDTH },
124738  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_35_CHECKER_TYPE,
124739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_35_WIDTH },
124740  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_36_CHECKER_TYPE,
124741  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_36_WIDTH },
124742  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_37_CHECKER_TYPE,
124743  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_37_WIDTH },
124744  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_38_CHECKER_TYPE,
124745  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_38_WIDTH },
124746  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_39_CHECKER_TYPE,
124747  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_39_WIDTH },
124748  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_40_CHECKER_TYPE,
124749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_40_WIDTH },
124750  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_41_CHECKER_TYPE,
124751  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_41_WIDTH },
124752  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_42_CHECKER_TYPE,
124753  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_42_WIDTH },
124754  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_43_CHECKER_TYPE,
124755  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_43_WIDTH },
124756  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_44_CHECKER_TYPE,
124757  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_44_WIDTH },
124758  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_45_CHECKER_TYPE,
124759  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_45_WIDTH },
124760  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_46_CHECKER_TYPE,
124761  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_46_WIDTH },
124762  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_47_CHECKER_TYPE,
124763  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_47_WIDTH },
124764  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_48_CHECKER_TYPE,
124765  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_48_WIDTH },
124766  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_49_CHECKER_TYPE,
124767  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_49_WIDTH },
124768  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_50_CHECKER_TYPE,
124769  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_50_WIDTH },
124770  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_51_CHECKER_TYPE,
124771  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_51_WIDTH },
124772  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_52_CHECKER_TYPE,
124773  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_52_WIDTH },
124774  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_53_CHECKER_TYPE,
124775  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_53_WIDTH },
124776  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_54_CHECKER_TYPE,
124777  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_54_WIDTH },
124778  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_55_CHECKER_TYPE,
124779  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_55_WIDTH },
124780  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_56_CHECKER_TYPE,
124781  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_56_WIDTH },
124782  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_57_CHECKER_TYPE,
124783  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_57_WIDTH },
124784  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_58_CHECKER_TYPE,
124785  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_GROUP_58_WIDTH },
124786 };
124787 
124793 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124794 {
124795  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124796  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124797  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124798  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124799  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124800  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124801  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124802  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124803  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124804  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124805  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124806  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124807  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124808  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124809  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124810  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124811  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124812  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124813 };
124814 
124820 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124821 {
124822  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124823  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124824  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124825  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124826  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124827  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124828  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124829  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124830  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124831  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124832  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124833  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124834  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124835  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124836  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124837  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124838  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124839  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124840  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
124841  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
124842  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_10_CHECKER_TYPE,
124843  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_10_WIDTH },
124844  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_11_CHECKER_TYPE,
124845  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_11_WIDTH },
124846  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_12_CHECKER_TYPE,
124847  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_12_WIDTH },
124848  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_13_CHECKER_TYPE,
124849  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_13_WIDTH },
124850  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_14_CHECKER_TYPE,
124851  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_14_WIDTH },
124852  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_15_CHECKER_TYPE,
124853  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_15_WIDTH },
124854  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_16_CHECKER_TYPE,
124855  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_16_WIDTH },
124856  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_17_CHECKER_TYPE,
124857  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_17_WIDTH },
124858  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_18_CHECKER_TYPE,
124859  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_18_WIDTH },
124860  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_19_CHECKER_TYPE,
124861  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_19_WIDTH },
124862  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_20_CHECKER_TYPE,
124863  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_20_WIDTH },
124864  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_21_CHECKER_TYPE,
124865  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_21_WIDTH },
124866  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_22_CHECKER_TYPE,
124867  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_22_WIDTH },
124868  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_23_CHECKER_TYPE,
124869  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_23_WIDTH },
124870  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_24_CHECKER_TYPE,
124871  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_24_WIDTH },
124872  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_25_CHECKER_TYPE,
124873  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_25_WIDTH },
124874  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_26_CHECKER_TYPE,
124875  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_26_WIDTH },
124876  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_27_CHECKER_TYPE,
124877  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_27_WIDTH },
124878  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_28_CHECKER_TYPE,
124879  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_28_WIDTH },
124880  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_29_CHECKER_TYPE,
124881  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_29_WIDTH },
124882  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_30_CHECKER_TYPE,
124883  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_30_WIDTH },
124884  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_31_CHECKER_TYPE,
124885  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_31_WIDTH },
124886  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_32_CHECKER_TYPE,
124887  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_32_WIDTH },
124888  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_33_CHECKER_TYPE,
124889  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_33_WIDTH },
124890  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_34_CHECKER_TYPE,
124891  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_34_WIDTH },
124892  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_35_CHECKER_TYPE,
124893  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_35_WIDTH },
124894  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_36_CHECKER_TYPE,
124895  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_36_WIDTH },
124896  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_37_CHECKER_TYPE,
124897  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_37_WIDTH },
124898  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_38_CHECKER_TYPE,
124899  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_38_WIDTH },
124900  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_39_CHECKER_TYPE,
124901  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_39_WIDTH },
124902  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_40_CHECKER_TYPE,
124903  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_40_WIDTH },
124904  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_41_CHECKER_TYPE,
124905  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_41_WIDTH },
124906  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_42_CHECKER_TYPE,
124907  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_42_WIDTH },
124908  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_43_CHECKER_TYPE,
124909  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_43_WIDTH },
124910  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_44_CHECKER_TYPE,
124911  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_44_WIDTH },
124912  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_45_CHECKER_TYPE,
124913  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_45_WIDTH },
124914  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_46_CHECKER_TYPE,
124915  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_46_WIDTH },
124916  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_47_CHECKER_TYPE,
124917  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_47_WIDTH },
124918  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_48_CHECKER_TYPE,
124919  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_48_WIDTH },
124920  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_49_CHECKER_TYPE,
124921  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_49_WIDTH },
124922  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_50_CHECKER_TYPE,
124923  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_50_WIDTH },
124924  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_51_CHECKER_TYPE,
124925  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_51_WIDTH },
124926  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_52_CHECKER_TYPE,
124927  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_52_WIDTH },
124928  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_53_CHECKER_TYPE,
124929  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_53_WIDTH },
124930  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_54_CHECKER_TYPE,
124931  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_54_WIDTH },
124932  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_55_CHECKER_TYPE,
124933  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_55_WIDTH },
124934  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_56_CHECKER_TYPE,
124935  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_56_WIDTH },
124936  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_57_CHECKER_TYPE,
124937  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_57_WIDTH },
124938  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_58_CHECKER_TYPE,
124939  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_GROUP_58_WIDTH },
124940 };
124941 
124947 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124948 {
124949  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124950  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124951  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124952  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124953  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124954  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124955  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124956  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124957  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124958  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124959  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124960  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124961  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124962  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124963  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124964  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124965  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124966  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124967  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
124968  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
124969 };
124970 
124976 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
124977 {
124978  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
124979  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
124980  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
124981  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
124982  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
124983  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
124984  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
124985  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
124986  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
124987  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
124988  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
124989  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
124990  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
124991  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
124992  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
124993  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
124994  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
124995  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
124996  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
124997  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
124998  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_10_CHECKER_TYPE,
124999  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_10_WIDTH },
125000  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_11_CHECKER_TYPE,
125001  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_11_WIDTH },
125002  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_12_CHECKER_TYPE,
125003  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_12_WIDTH },
125004  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_13_CHECKER_TYPE,
125005  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_13_WIDTH },
125006  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_14_CHECKER_TYPE,
125007  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_14_WIDTH },
125008  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_15_CHECKER_TYPE,
125009  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_15_WIDTH },
125010  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_16_CHECKER_TYPE,
125011  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_16_WIDTH },
125012  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_17_CHECKER_TYPE,
125013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_17_WIDTH },
125014  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_18_CHECKER_TYPE,
125015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_18_WIDTH },
125016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_19_CHECKER_TYPE,
125017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_19_WIDTH },
125018  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_20_CHECKER_TYPE,
125019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_20_WIDTH },
125020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_21_CHECKER_TYPE,
125021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_21_WIDTH },
125022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_22_CHECKER_TYPE,
125023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_22_WIDTH },
125024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_23_CHECKER_TYPE,
125025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_23_WIDTH },
125026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_24_CHECKER_TYPE,
125027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_24_WIDTH },
125028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_25_CHECKER_TYPE,
125029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_25_WIDTH },
125030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_26_CHECKER_TYPE,
125031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_26_WIDTH },
125032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_27_CHECKER_TYPE,
125033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_27_WIDTH },
125034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_28_CHECKER_TYPE,
125035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_28_WIDTH },
125036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_29_CHECKER_TYPE,
125037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_29_WIDTH },
125038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_30_CHECKER_TYPE,
125039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_30_WIDTH },
125040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_31_CHECKER_TYPE,
125041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_31_WIDTH },
125042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_32_CHECKER_TYPE,
125043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_32_WIDTH },
125044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_33_CHECKER_TYPE,
125045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_33_WIDTH },
125046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_34_CHECKER_TYPE,
125047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_34_WIDTH },
125048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_35_CHECKER_TYPE,
125049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_35_WIDTH },
125050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_36_CHECKER_TYPE,
125051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_36_WIDTH },
125052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_37_CHECKER_TYPE,
125053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_37_WIDTH },
125054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_38_CHECKER_TYPE,
125055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_38_WIDTH },
125056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_39_CHECKER_TYPE,
125057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_39_WIDTH },
125058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_40_CHECKER_TYPE,
125059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_40_WIDTH },
125060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_41_CHECKER_TYPE,
125061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_41_WIDTH },
125062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_42_CHECKER_TYPE,
125063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_42_WIDTH },
125064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_43_CHECKER_TYPE,
125065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_43_WIDTH },
125066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_44_CHECKER_TYPE,
125067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_44_WIDTH },
125068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_45_CHECKER_TYPE,
125069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_45_WIDTH },
125070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_46_CHECKER_TYPE,
125071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_46_WIDTH },
125072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_47_CHECKER_TYPE,
125073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_47_WIDTH },
125074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_48_CHECKER_TYPE,
125075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_48_WIDTH },
125076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_49_CHECKER_TYPE,
125077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_49_WIDTH },
125078  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_50_CHECKER_TYPE,
125079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_50_WIDTH },
125080  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_51_CHECKER_TYPE,
125081  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_51_WIDTH },
125082  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_52_CHECKER_TYPE,
125083  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_52_WIDTH },
125084  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_53_CHECKER_TYPE,
125085  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_53_WIDTH },
125086  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_54_CHECKER_TYPE,
125087  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_54_WIDTH },
125088  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_55_CHECKER_TYPE,
125089  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_55_WIDTH },
125090  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_56_CHECKER_TYPE,
125091  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_56_WIDTH },
125092  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_57_CHECKER_TYPE,
125093  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_57_WIDTH },
125094  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_58_CHECKER_TYPE,
125095  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_GROUP_58_WIDTH },
125096 };
125097 
125103 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS] =
125104 {
125105  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_0_CHECKER_TYPE,
125106  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_0_WIDTH },
125107  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_1_CHECKER_TYPE,
125108  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_1_WIDTH },
125109  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_2_CHECKER_TYPE,
125110  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_2_WIDTH },
125111  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_3_CHECKER_TYPE,
125112  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_3_WIDTH },
125113  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_4_CHECKER_TYPE,
125114  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_4_WIDTH },
125115  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_5_CHECKER_TYPE,
125116  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_5_WIDTH },
125117  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_6_CHECKER_TYPE,
125118  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_6_WIDTH },
125119  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_7_CHECKER_TYPE,
125120  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_7_WIDTH },
125121  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_8_CHECKER_TYPE,
125122  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_8_WIDTH },
125123  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_9_CHECKER_TYPE,
125124  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_GROUP_9_WIDTH },
125125 };
125126 
125132 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_MAX_NUM_CHECKERS] =
125133 {
125134  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_0_CHECKER_TYPE,
125135  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_0_WIDTH },
125136  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_1_CHECKER_TYPE,
125137  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_GROUP_1_WIDTH },
125138 };
125139 
125145 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_MAX_NUM_CHECKERS] =
125146 {
125147  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_0_CHECKER_TYPE,
125148  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_0_WIDTH },
125149  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_1_CHECKER_TYPE,
125150  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_1_WIDTH },
125151  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_2_CHECKER_TYPE,
125152  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_2_WIDTH },
125153  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_3_CHECKER_TYPE,
125154  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_3_WIDTH },
125155  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_4_CHECKER_TYPE,
125156  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_4_WIDTH },
125157  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_5_CHECKER_TYPE,
125158  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_5_WIDTH },
125159  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_6_CHECKER_TYPE,
125160  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_6_WIDTH },
125161  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_7_CHECKER_TYPE,
125162  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_7_WIDTH },
125163  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_8_CHECKER_TYPE,
125164  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_8_WIDTH },
125165  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_9_CHECKER_TYPE,
125166  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_9_WIDTH },
125167  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_10_CHECKER_TYPE,
125168  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_10_WIDTH },
125169  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_11_CHECKER_TYPE,
125170  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_11_WIDTH },
125171  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_12_CHECKER_TYPE,
125172  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_12_WIDTH },
125173  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_13_CHECKER_TYPE,
125174  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_13_WIDTH },
125175  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_14_CHECKER_TYPE,
125176  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_14_WIDTH },
125177  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_15_CHECKER_TYPE,
125178  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_15_WIDTH },
125179  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_16_CHECKER_TYPE,
125180  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_16_WIDTH },
125181  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_17_CHECKER_TYPE,
125182  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_17_WIDTH },
125183  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_18_CHECKER_TYPE,
125184  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_18_WIDTH },
125185  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_19_CHECKER_TYPE,
125186  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_19_WIDTH },
125187  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_20_CHECKER_TYPE,
125188  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_20_WIDTH },
125189  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_21_CHECKER_TYPE,
125190  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_21_WIDTH },
125191  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_22_CHECKER_TYPE,
125192  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_22_WIDTH },
125193  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_23_CHECKER_TYPE,
125194  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_23_WIDTH },
125195  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_24_CHECKER_TYPE,
125196  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_24_WIDTH },
125197  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_25_CHECKER_TYPE,
125198  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_25_WIDTH },
125199  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_26_CHECKER_TYPE,
125200  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_26_WIDTH },
125201  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_27_CHECKER_TYPE,
125202  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_27_WIDTH },
125203  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_28_CHECKER_TYPE,
125204  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_28_WIDTH },
125205  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_29_CHECKER_TYPE,
125206  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_29_WIDTH },
125207  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_30_CHECKER_TYPE,
125208  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_30_WIDTH },
125209  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_31_CHECKER_TYPE,
125210  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_31_WIDTH },
125211  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_32_CHECKER_TYPE,
125212  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_32_WIDTH },
125213  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_33_CHECKER_TYPE,
125214  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_33_WIDTH },
125215  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_34_CHECKER_TYPE,
125216  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_34_WIDTH },
125217  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_35_CHECKER_TYPE,
125218  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_35_WIDTH },
125219  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_36_CHECKER_TYPE,
125220  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_36_WIDTH },
125221  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_37_CHECKER_TYPE,
125222  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_37_WIDTH },
125223  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_38_CHECKER_TYPE,
125224  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_38_WIDTH },
125225  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_39_CHECKER_TYPE,
125226  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_39_WIDTH },
125227  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_40_CHECKER_TYPE,
125228  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_40_WIDTH },
125229  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_41_CHECKER_TYPE,
125230  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_41_WIDTH },
125231  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_42_CHECKER_TYPE,
125232  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_42_WIDTH },
125233  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_43_CHECKER_TYPE,
125234  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_43_WIDTH },
125235  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_44_CHECKER_TYPE,
125236  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_44_WIDTH },
125237  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_45_CHECKER_TYPE,
125238  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_45_WIDTH },
125239  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_46_CHECKER_TYPE,
125240  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_46_WIDTH },
125241  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_47_CHECKER_TYPE,
125242  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_47_WIDTH },
125243  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_48_CHECKER_TYPE,
125244  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_48_WIDTH },
125245  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_49_CHECKER_TYPE,
125246  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_49_WIDTH },
125247  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_50_CHECKER_TYPE,
125248  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_50_WIDTH },
125249  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_51_CHECKER_TYPE,
125250  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_51_WIDTH },
125251  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_52_CHECKER_TYPE,
125252  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_52_WIDTH },
125253  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_53_CHECKER_TYPE,
125254  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_53_WIDTH },
125255  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_54_CHECKER_TYPE,
125256  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_54_WIDTH },
125257  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_55_CHECKER_TYPE,
125258  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_55_WIDTH },
125259  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_56_CHECKER_TYPE,
125260  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_56_WIDTH },
125261  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_57_CHECKER_TYPE,
125262  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_57_WIDTH },
125263  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_58_CHECKER_TYPE,
125264  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_58_WIDTH },
125265  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_59_CHECKER_TYPE,
125266  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_59_WIDTH },
125267  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_60_CHECKER_TYPE,
125268  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_60_WIDTH },
125269  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_61_CHECKER_TYPE,
125270  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_61_WIDTH },
125271  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_62_CHECKER_TYPE,
125272  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_62_WIDTH },
125273  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_63_CHECKER_TYPE,
125274  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_63_WIDTH },
125275  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_64_CHECKER_TYPE,
125276  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_64_WIDTH },
125277  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_65_CHECKER_TYPE,
125278  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_65_WIDTH },
125279  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_66_CHECKER_TYPE,
125280  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_66_WIDTH },
125281  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_67_CHECKER_TYPE,
125282  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_67_WIDTH },
125283  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_68_CHECKER_TYPE,
125284  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_68_WIDTH },
125285  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_69_CHECKER_TYPE,
125286  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_69_WIDTH },
125287  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_70_CHECKER_TYPE,
125288  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_70_WIDTH },
125289  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_71_CHECKER_TYPE,
125290  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_71_WIDTH },
125291  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_72_CHECKER_TYPE,
125292  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_72_WIDTH },
125293  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_73_CHECKER_TYPE,
125294  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_73_WIDTH },
125295  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_74_CHECKER_TYPE,
125296  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_74_WIDTH },
125297  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_75_CHECKER_TYPE,
125298  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_75_WIDTH },
125299  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_76_CHECKER_TYPE,
125300  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_76_WIDTH },
125301  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_77_CHECKER_TYPE,
125302  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_77_WIDTH },
125303  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_78_CHECKER_TYPE,
125304  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_78_WIDTH },
125305  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_79_CHECKER_TYPE,
125306  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_79_WIDTH },
125307  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_80_CHECKER_TYPE,
125308  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_80_WIDTH },
125309  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_81_CHECKER_TYPE,
125310  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_81_WIDTH },
125311  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_82_CHECKER_TYPE,
125312  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_82_WIDTH },
125313  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_83_CHECKER_TYPE,
125314  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_83_WIDTH },
125315  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_84_CHECKER_TYPE,
125316  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_84_WIDTH },
125317  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_85_CHECKER_TYPE,
125318  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_85_WIDTH },
125319  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_86_CHECKER_TYPE,
125320  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_86_WIDTH },
125321  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_87_CHECKER_TYPE,
125322  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_87_WIDTH },
125323  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_88_CHECKER_TYPE,
125324  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_88_WIDTH },
125325  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_89_CHECKER_TYPE,
125326  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_89_WIDTH },
125327  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_90_CHECKER_TYPE,
125328  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_90_WIDTH },
125329  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_91_CHECKER_TYPE,
125330  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_91_WIDTH },
125331  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_92_CHECKER_TYPE,
125332  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_92_WIDTH },
125333  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_93_CHECKER_TYPE,
125334  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_93_WIDTH },
125335  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_94_CHECKER_TYPE,
125336  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_94_WIDTH },
125337  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_95_CHECKER_TYPE,
125338  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_95_WIDTH },
125339  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_96_CHECKER_TYPE,
125340  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_96_WIDTH },
125341  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_97_CHECKER_TYPE,
125342  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_97_WIDTH },
125343  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_98_CHECKER_TYPE,
125344  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_98_WIDTH },
125345  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_99_CHECKER_TYPE,
125346  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_99_WIDTH },
125347  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_100_CHECKER_TYPE,
125348  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_100_WIDTH },
125349  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_101_CHECKER_TYPE,
125350  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_GROUP_101_WIDTH },
125351 };
125352 
125358 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_MAX_NUM_CHECKERS] =
125359 {
125360  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_0_CHECKER_TYPE,
125361  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_0_WIDTH },
125362  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_1_CHECKER_TYPE,
125363  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_1_WIDTH },
125364  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_2_CHECKER_TYPE,
125365  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_2_WIDTH },
125366  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_3_CHECKER_TYPE,
125367  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_3_WIDTH },
125368  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_4_CHECKER_TYPE,
125369  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_4_WIDTH },
125370  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_5_CHECKER_TYPE,
125371  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_5_WIDTH },
125372  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_6_CHECKER_TYPE,
125373  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_6_WIDTH },
125374  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_7_CHECKER_TYPE,
125375  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_7_WIDTH },
125376  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_8_CHECKER_TYPE,
125377  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_8_WIDTH },
125378  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_9_CHECKER_TYPE,
125379  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_9_WIDTH },
125380  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_10_CHECKER_TYPE,
125381  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_10_WIDTH },
125382  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_11_CHECKER_TYPE,
125383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_11_WIDTH },
125384  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_12_CHECKER_TYPE,
125385  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_12_WIDTH },
125386  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_13_CHECKER_TYPE,
125387  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_13_WIDTH },
125388  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_14_CHECKER_TYPE,
125389  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_14_WIDTH },
125390  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_15_CHECKER_TYPE,
125391  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_15_WIDTH },
125392  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_16_CHECKER_TYPE,
125393  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_16_WIDTH },
125394  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_17_CHECKER_TYPE,
125395  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_17_WIDTH },
125396  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_18_CHECKER_TYPE,
125397  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_18_WIDTH },
125398  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_19_CHECKER_TYPE,
125399  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_19_WIDTH },
125400  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_20_CHECKER_TYPE,
125401  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_20_WIDTH },
125402  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_21_CHECKER_TYPE,
125403  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_21_WIDTH },
125404  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_22_CHECKER_TYPE,
125405  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_22_WIDTH },
125406  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_23_CHECKER_TYPE,
125407  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_23_WIDTH },
125408  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_24_CHECKER_TYPE,
125409  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_24_WIDTH },
125410  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_25_CHECKER_TYPE,
125411  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_25_WIDTH },
125412  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_26_CHECKER_TYPE,
125413  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_26_WIDTH },
125414  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_27_CHECKER_TYPE,
125415  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_27_WIDTH },
125416  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_28_CHECKER_TYPE,
125417  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_28_WIDTH },
125418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_29_CHECKER_TYPE,
125419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_29_WIDTH },
125420  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_30_CHECKER_TYPE,
125421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_30_WIDTH },
125422  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_31_CHECKER_TYPE,
125423  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_31_WIDTH },
125424  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_32_CHECKER_TYPE,
125425  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_32_WIDTH },
125426  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_33_CHECKER_TYPE,
125427  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_33_WIDTH },
125428  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_34_CHECKER_TYPE,
125429  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_34_WIDTH },
125430  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_35_CHECKER_TYPE,
125431  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_35_WIDTH },
125432  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_36_CHECKER_TYPE,
125433  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_36_WIDTH },
125434  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_37_CHECKER_TYPE,
125435  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_37_WIDTH },
125436  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_38_CHECKER_TYPE,
125437  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_38_WIDTH },
125438  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_39_CHECKER_TYPE,
125439  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_39_WIDTH },
125440  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_40_CHECKER_TYPE,
125441  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_40_WIDTH },
125442  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_41_CHECKER_TYPE,
125443  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_41_WIDTH },
125444  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_42_CHECKER_TYPE,
125445  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_42_WIDTH },
125446  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_43_CHECKER_TYPE,
125447  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_43_WIDTH },
125448  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_44_CHECKER_TYPE,
125449  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_44_WIDTH },
125450  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_45_CHECKER_TYPE,
125451  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_45_WIDTH },
125452  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_46_CHECKER_TYPE,
125453  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_46_WIDTH },
125454  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_47_CHECKER_TYPE,
125455  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_47_WIDTH },
125456  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_48_CHECKER_TYPE,
125457  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_48_WIDTH },
125458  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_49_CHECKER_TYPE,
125459  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_49_WIDTH },
125460  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_50_CHECKER_TYPE,
125461  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_50_WIDTH },
125462  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_51_CHECKER_TYPE,
125463  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_51_WIDTH },
125464  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_52_CHECKER_TYPE,
125465  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_GROUP_52_WIDTH },
125466 };
125467 
125473 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS] =
125474 {
125475  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
125476  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_0_WIDTH },
125477  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
125478  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_1_WIDTH },
125479  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
125480  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_2_WIDTH },
125481  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
125482  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_3_WIDTH },
125483  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
125484  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_4_WIDTH },
125485  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
125486  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_5_WIDTH },
125487  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
125488  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_6_WIDTH },
125489  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
125490  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_7_WIDTH },
125491  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
125492  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_8_WIDTH },
125493  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
125494  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_9_WIDTH },
125495  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
125496  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_10_WIDTH },
125497  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
125498  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_11_WIDTH },
125499  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
125500  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_12_WIDTH },
125501  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
125502  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_13_WIDTH },
125503  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
125504  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_14_WIDTH },
125505  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
125506  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_15_WIDTH },
125507  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
125508  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_16_WIDTH },
125509  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
125510  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_17_WIDTH },
125511  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
125512  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_18_WIDTH },
125513  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
125514  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_19_WIDTH },
125515  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
125516  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_20_WIDTH },
125517  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
125518  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_21_WIDTH },
125519  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
125520  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_22_WIDTH },
125521  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
125522  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_23_WIDTH },
125523  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
125524  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_24_WIDTH },
125525  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
125526  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_25_WIDTH },
125527  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
125528  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_26_WIDTH },
125529  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_27_CHECKER_TYPE,
125530  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_27_WIDTH },
125531  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_28_CHECKER_TYPE,
125532  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_28_WIDTH },
125533  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_29_CHECKER_TYPE,
125534  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_29_WIDTH },
125535  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_30_CHECKER_TYPE,
125536  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_30_WIDTH },
125537  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_31_CHECKER_TYPE,
125538  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_31_WIDTH },
125539  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_32_CHECKER_TYPE,
125540  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_32_WIDTH },
125541  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_33_CHECKER_TYPE,
125542  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_33_WIDTH },
125543  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_34_CHECKER_TYPE,
125544  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_34_WIDTH },
125545  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_35_CHECKER_TYPE,
125546  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_35_WIDTH },
125547  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_36_CHECKER_TYPE,
125548  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_36_WIDTH },
125549  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_37_CHECKER_TYPE,
125550  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_37_WIDTH },
125551  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_38_CHECKER_TYPE,
125552  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_38_WIDTH },
125553  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_39_CHECKER_TYPE,
125554  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_39_WIDTH },
125555  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_40_CHECKER_TYPE,
125556  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_40_WIDTH },
125557  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_41_CHECKER_TYPE,
125558  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_41_WIDTH },
125559  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_42_CHECKER_TYPE,
125560  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_42_WIDTH },
125561  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_43_CHECKER_TYPE,
125562  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_43_WIDTH },
125563  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_44_CHECKER_TYPE,
125564  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_44_WIDTH },
125565  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_45_CHECKER_TYPE,
125566  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_45_WIDTH },
125567  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_46_CHECKER_TYPE,
125568  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_46_WIDTH },
125569  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_47_CHECKER_TYPE,
125570  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_GROUP_47_WIDTH },
125571 };
125572 
125578 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_MAX_NUM_CHECKERS] =
125579 {
125580  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_0_CHECKER_TYPE,
125581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_0_WIDTH },
125582  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_1_CHECKER_TYPE,
125583  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_1_WIDTH },
125584  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_2_CHECKER_TYPE,
125585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_2_WIDTH },
125586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_3_CHECKER_TYPE,
125587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_3_WIDTH },
125588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_4_CHECKER_TYPE,
125589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_4_WIDTH },
125590  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_5_CHECKER_TYPE,
125591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_5_WIDTH },
125592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_6_CHECKER_TYPE,
125593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_6_WIDTH },
125594  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_7_CHECKER_TYPE,
125595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_7_WIDTH },
125596  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_8_CHECKER_TYPE,
125597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_8_WIDTH },
125598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_9_CHECKER_TYPE,
125599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_9_WIDTH },
125600  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_10_CHECKER_TYPE,
125601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_10_WIDTH },
125602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_11_CHECKER_TYPE,
125603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_11_WIDTH },
125604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_12_CHECKER_TYPE,
125605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_12_WIDTH },
125606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_13_CHECKER_TYPE,
125607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_13_WIDTH },
125608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_14_CHECKER_TYPE,
125609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_14_WIDTH },
125610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_15_CHECKER_TYPE,
125611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_15_WIDTH },
125612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_16_CHECKER_TYPE,
125613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_16_WIDTH },
125614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_17_CHECKER_TYPE,
125615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_17_WIDTH },
125616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_18_CHECKER_TYPE,
125617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_18_WIDTH },
125618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_19_CHECKER_TYPE,
125619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_19_WIDTH },
125620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_20_CHECKER_TYPE,
125621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_20_WIDTH },
125622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_21_CHECKER_TYPE,
125623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_21_WIDTH },
125624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_22_CHECKER_TYPE,
125625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_22_WIDTH },
125626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_23_CHECKER_TYPE,
125627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_23_WIDTH },
125628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_24_CHECKER_TYPE,
125629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_24_WIDTH },
125630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_25_CHECKER_TYPE,
125631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_25_WIDTH },
125632  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_26_CHECKER_TYPE,
125633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_26_WIDTH },
125634  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_27_CHECKER_TYPE,
125635  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_27_WIDTH },
125636  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_28_CHECKER_TYPE,
125637  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_28_WIDTH },
125638  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_29_CHECKER_TYPE,
125639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_29_WIDTH },
125640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_30_CHECKER_TYPE,
125641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_30_WIDTH },
125642  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_31_CHECKER_TYPE,
125643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_31_WIDTH },
125644  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_32_CHECKER_TYPE,
125645  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_32_WIDTH },
125646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_33_CHECKER_TYPE,
125647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_33_WIDTH },
125648  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_34_CHECKER_TYPE,
125649  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_34_WIDTH },
125650  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_35_CHECKER_TYPE,
125651  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_35_WIDTH },
125652  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_36_CHECKER_TYPE,
125653  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_36_WIDTH },
125654  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_37_CHECKER_TYPE,
125655  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_37_WIDTH },
125656  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_38_CHECKER_TYPE,
125657  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_38_WIDTH },
125658  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_39_CHECKER_TYPE,
125659  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_39_WIDTH },
125660  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_40_CHECKER_TYPE,
125661  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_40_WIDTH },
125662  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_41_CHECKER_TYPE,
125663  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_41_WIDTH },
125664  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_42_CHECKER_TYPE,
125665  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_42_WIDTH },
125666  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_43_CHECKER_TYPE,
125667  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_43_WIDTH },
125668  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_44_CHECKER_TYPE,
125669  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_44_WIDTH },
125670  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_45_CHECKER_TYPE,
125671  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_45_WIDTH },
125672  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_46_CHECKER_TYPE,
125673  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_46_WIDTH },
125674  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_47_CHECKER_TYPE,
125675  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_47_WIDTH },
125676  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_48_CHECKER_TYPE,
125677  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_48_WIDTH },
125678  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_49_CHECKER_TYPE,
125679  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_49_WIDTH },
125680  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_50_CHECKER_TYPE,
125681  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_50_WIDTH },
125682  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_51_CHECKER_TYPE,
125683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_51_WIDTH },
125684  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_52_CHECKER_TYPE,
125685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_52_WIDTH },
125686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_53_CHECKER_TYPE,
125687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_53_WIDTH },
125688  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_54_CHECKER_TYPE,
125689  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_54_WIDTH },
125690  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_55_CHECKER_TYPE,
125691  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_55_WIDTH },
125692  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_56_CHECKER_TYPE,
125693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_56_WIDTH },
125694  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_57_CHECKER_TYPE,
125695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_57_WIDTH },
125696  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_58_CHECKER_TYPE,
125697  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_58_WIDTH },
125698  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_59_CHECKER_TYPE,
125699  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_59_WIDTH },
125700  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_60_CHECKER_TYPE,
125701  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_60_WIDTH },
125702  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_61_CHECKER_TYPE,
125703  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_61_WIDTH },
125704  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_62_CHECKER_TYPE,
125705  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_62_WIDTH },
125706  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_63_CHECKER_TYPE,
125707  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_63_WIDTH },
125708  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_64_CHECKER_TYPE,
125709  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_64_WIDTH },
125710  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_65_CHECKER_TYPE,
125711  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_65_WIDTH },
125712  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_66_CHECKER_TYPE,
125713  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_66_WIDTH },
125714  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_67_CHECKER_TYPE,
125715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_67_WIDTH },
125716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_68_CHECKER_TYPE,
125717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_68_WIDTH },
125718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_69_CHECKER_TYPE,
125719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_69_WIDTH },
125720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_70_CHECKER_TYPE,
125721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_70_WIDTH },
125722  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_71_CHECKER_TYPE,
125723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_71_WIDTH },
125724  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_72_CHECKER_TYPE,
125725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_72_WIDTH },
125726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_73_CHECKER_TYPE,
125727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_73_WIDTH },
125728  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_74_CHECKER_TYPE,
125729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_74_WIDTH },
125730  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_75_CHECKER_TYPE,
125731  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_75_WIDTH },
125732  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_76_CHECKER_TYPE,
125733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_76_WIDTH },
125734  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_77_CHECKER_TYPE,
125735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_77_WIDTH },
125736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_78_CHECKER_TYPE,
125737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_78_WIDTH },
125738  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_79_CHECKER_TYPE,
125739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_79_WIDTH },
125740  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_80_CHECKER_TYPE,
125741  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_80_WIDTH },
125742  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_81_CHECKER_TYPE,
125743  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_81_WIDTH },
125744  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_82_CHECKER_TYPE,
125745  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_82_WIDTH },
125746  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_83_CHECKER_TYPE,
125747  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_83_WIDTH },
125748  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_84_CHECKER_TYPE,
125749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_84_WIDTH },
125750  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_85_CHECKER_TYPE,
125751  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_85_WIDTH },
125752  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_86_CHECKER_TYPE,
125753  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_86_WIDTH },
125754  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_87_CHECKER_TYPE,
125755  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_87_WIDTH },
125756  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_88_CHECKER_TYPE,
125757  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_88_WIDTH },
125758  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_89_CHECKER_TYPE,
125759  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_89_WIDTH },
125760  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_90_CHECKER_TYPE,
125761  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_90_WIDTH },
125762  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_91_CHECKER_TYPE,
125763  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_91_WIDTH },
125764  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_92_CHECKER_TYPE,
125765  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_92_WIDTH },
125766  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_93_CHECKER_TYPE,
125767  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_93_WIDTH },
125768  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_94_CHECKER_TYPE,
125769  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_94_WIDTH },
125770  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_95_CHECKER_TYPE,
125771  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_95_WIDTH },
125772  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_96_CHECKER_TYPE,
125773  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_96_WIDTH },
125774  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_97_CHECKER_TYPE,
125775  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_97_WIDTH },
125776  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_98_CHECKER_TYPE,
125777  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_98_WIDTH },
125778  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_99_CHECKER_TYPE,
125779  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_99_WIDTH },
125780  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_100_CHECKER_TYPE,
125781  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_100_WIDTH },
125782  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_101_CHECKER_TYPE,
125783  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_101_WIDTH },
125784  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_102_CHECKER_TYPE,
125785  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_102_WIDTH },
125786  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_103_CHECKER_TYPE,
125787  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_103_WIDTH },
125788  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_104_CHECKER_TYPE,
125789  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_104_WIDTH },
125790  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_105_CHECKER_TYPE,
125791  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_105_WIDTH },
125792  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_106_CHECKER_TYPE,
125793  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_106_WIDTH },
125794  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_107_CHECKER_TYPE,
125795  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_107_WIDTH },
125796  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_108_CHECKER_TYPE,
125797  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_108_WIDTH },
125798  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_109_CHECKER_TYPE,
125799  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_109_WIDTH },
125800  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_110_CHECKER_TYPE,
125801  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_110_WIDTH },
125802  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_111_CHECKER_TYPE,
125803  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_111_WIDTH },
125804  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_112_CHECKER_TYPE,
125805  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_112_WIDTH },
125806  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_113_CHECKER_TYPE,
125807  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_113_WIDTH },
125808  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_114_CHECKER_TYPE,
125809  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_114_WIDTH },
125810  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_115_CHECKER_TYPE,
125811  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_115_WIDTH },
125812  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_116_CHECKER_TYPE,
125813  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_116_WIDTH },
125814  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_117_CHECKER_TYPE,
125815  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_117_WIDTH },
125816  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_118_CHECKER_TYPE,
125817  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_118_WIDTH },
125818  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_119_CHECKER_TYPE,
125819  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_119_WIDTH },
125820  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_120_CHECKER_TYPE,
125821  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_120_WIDTH },
125822  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_121_CHECKER_TYPE,
125823  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_121_WIDTH },
125824  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_122_CHECKER_TYPE,
125825  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_122_WIDTH },
125826  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_123_CHECKER_TYPE,
125827  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_123_WIDTH },
125828  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_124_CHECKER_TYPE,
125829  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_124_WIDTH },
125830  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_125_CHECKER_TYPE,
125831  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_125_WIDTH },
125832  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_126_CHECKER_TYPE,
125833  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_126_WIDTH },
125834  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_127_CHECKER_TYPE,
125835  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_127_WIDTH },
125836  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_128_CHECKER_TYPE,
125837  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_128_WIDTH },
125838  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_129_CHECKER_TYPE,
125839  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_129_WIDTH },
125840  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_130_CHECKER_TYPE,
125841  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_130_WIDTH },
125842  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_131_CHECKER_TYPE,
125843  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_131_WIDTH },
125844  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_132_CHECKER_TYPE,
125845  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_132_WIDTH },
125846  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_133_CHECKER_TYPE,
125847  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_133_WIDTH },
125848  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_134_CHECKER_TYPE,
125849  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_134_WIDTH },
125850  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_135_CHECKER_TYPE,
125851  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_135_WIDTH },
125852  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_136_CHECKER_TYPE,
125853  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_136_WIDTH },
125854  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_137_CHECKER_TYPE,
125855  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_137_WIDTH },
125856  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_138_CHECKER_TYPE,
125857  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_138_WIDTH },
125858  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_139_CHECKER_TYPE,
125859  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_139_WIDTH },
125860  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_140_CHECKER_TYPE,
125861  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_140_WIDTH },
125862  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_141_CHECKER_TYPE,
125863  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_141_WIDTH },
125864  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_142_CHECKER_TYPE,
125865  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_142_WIDTH },
125866  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_143_CHECKER_TYPE,
125867  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_143_WIDTH },
125868  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_144_CHECKER_TYPE,
125869  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_144_WIDTH },
125870  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_145_CHECKER_TYPE,
125871  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_145_WIDTH },
125872  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_146_CHECKER_TYPE,
125873  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_146_WIDTH },
125874  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_147_CHECKER_TYPE,
125875  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_147_WIDTH },
125876  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_148_CHECKER_TYPE,
125877  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_148_WIDTH },
125878  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_149_CHECKER_TYPE,
125879  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_149_WIDTH },
125880  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_150_CHECKER_TYPE,
125881  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_150_WIDTH },
125882  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_151_CHECKER_TYPE,
125883  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_151_WIDTH },
125884  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_152_CHECKER_TYPE,
125885  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_152_WIDTH },
125886  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_153_CHECKER_TYPE,
125887  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_153_WIDTH },
125888  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_154_CHECKER_TYPE,
125889  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_154_WIDTH },
125890  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_155_CHECKER_TYPE,
125891  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_155_WIDTH },
125892  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_156_CHECKER_TYPE,
125893  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_156_WIDTH },
125894  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_157_CHECKER_TYPE,
125895  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_157_WIDTH },
125896  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_158_CHECKER_TYPE,
125897  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_158_WIDTH },
125898  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_159_CHECKER_TYPE,
125899  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_159_WIDTH },
125900  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_160_CHECKER_TYPE,
125901  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_160_WIDTH },
125902  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_161_CHECKER_TYPE,
125903  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_161_WIDTH },
125904  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_162_CHECKER_TYPE,
125905  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_162_WIDTH },
125906  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_163_CHECKER_TYPE,
125907  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_163_WIDTH },
125908  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_164_CHECKER_TYPE,
125909  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_164_WIDTH },
125910  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_165_CHECKER_TYPE,
125911  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_165_WIDTH },
125912  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_166_CHECKER_TYPE,
125913  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_166_WIDTH },
125914  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_167_CHECKER_TYPE,
125915  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_167_WIDTH },
125916  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_168_CHECKER_TYPE,
125917  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_168_WIDTH },
125918  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_169_CHECKER_TYPE,
125919  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_169_WIDTH },
125920  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_170_CHECKER_TYPE,
125921  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_170_WIDTH },
125922  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_171_CHECKER_TYPE,
125923  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_171_WIDTH },
125924  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_172_CHECKER_TYPE,
125925  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_172_WIDTH },
125926  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_173_CHECKER_TYPE,
125927  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_173_WIDTH },
125928  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_174_CHECKER_TYPE,
125929  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_174_WIDTH },
125930  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_175_CHECKER_TYPE,
125931  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_175_WIDTH },
125932  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_176_CHECKER_TYPE,
125933  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_176_WIDTH },
125934  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_177_CHECKER_TYPE,
125935  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_177_WIDTH },
125936  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_178_CHECKER_TYPE,
125937  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_178_WIDTH },
125938  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_179_CHECKER_TYPE,
125939  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_179_WIDTH },
125940  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_180_CHECKER_TYPE,
125941  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_180_WIDTH },
125942  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_181_CHECKER_TYPE,
125943  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_181_WIDTH },
125944  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_182_CHECKER_TYPE,
125945  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_182_WIDTH },
125946  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_183_CHECKER_TYPE,
125947  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_183_WIDTH },
125948  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_184_CHECKER_TYPE,
125949  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_184_WIDTH },
125950  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_185_CHECKER_TYPE,
125951  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_185_WIDTH },
125952  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_186_CHECKER_TYPE,
125953  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_186_WIDTH },
125954  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_187_CHECKER_TYPE,
125955  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_187_WIDTH },
125956  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_188_CHECKER_TYPE,
125957  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_188_WIDTH },
125958  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_189_CHECKER_TYPE,
125959  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_189_WIDTH },
125960  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_190_CHECKER_TYPE,
125961  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_190_WIDTH },
125962  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_191_CHECKER_TYPE,
125963  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_191_WIDTH },
125964  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_192_CHECKER_TYPE,
125965  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_192_WIDTH },
125966  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_193_CHECKER_TYPE,
125967  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_193_WIDTH },
125968  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_194_CHECKER_TYPE,
125969  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_194_WIDTH },
125970  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_195_CHECKER_TYPE,
125971  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_195_WIDTH },
125972  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_196_CHECKER_TYPE,
125973  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_196_WIDTH },
125974  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_197_CHECKER_TYPE,
125975  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_197_WIDTH },
125976  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_198_CHECKER_TYPE,
125977  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_198_WIDTH },
125978  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_199_CHECKER_TYPE,
125979  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_199_WIDTH },
125980  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_200_CHECKER_TYPE,
125981  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_200_WIDTH },
125982  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_201_CHECKER_TYPE,
125983  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_201_WIDTH },
125984  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_202_CHECKER_TYPE,
125985  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_202_WIDTH },
125986  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_203_CHECKER_TYPE,
125987  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_203_WIDTH },
125988  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_204_CHECKER_TYPE,
125989  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_204_WIDTH },
125990  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_205_CHECKER_TYPE,
125991  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_205_WIDTH },
125992  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_206_CHECKER_TYPE,
125993  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_206_WIDTH },
125994  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_207_CHECKER_TYPE,
125995  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_207_WIDTH },
125996  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_208_CHECKER_TYPE,
125997  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_208_WIDTH },
125998  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_209_CHECKER_TYPE,
125999  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_209_WIDTH },
126000  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_210_CHECKER_TYPE,
126001  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_210_WIDTH },
126002  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_211_CHECKER_TYPE,
126003  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_211_WIDTH },
126004  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_212_CHECKER_TYPE,
126005  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_212_WIDTH },
126006  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_213_CHECKER_TYPE,
126007  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_213_WIDTH },
126008  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_214_CHECKER_TYPE,
126009  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_214_WIDTH },
126010  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_215_CHECKER_TYPE,
126011  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_215_WIDTH },
126012  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_216_CHECKER_TYPE,
126013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_216_WIDTH },
126014  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_217_CHECKER_TYPE,
126015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_217_WIDTH },
126016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_218_CHECKER_TYPE,
126017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_218_WIDTH },
126018  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_219_CHECKER_TYPE,
126019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_219_WIDTH },
126020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_220_CHECKER_TYPE,
126021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_220_WIDTH },
126022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_221_CHECKER_TYPE,
126023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_221_WIDTH },
126024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_222_CHECKER_TYPE,
126025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_222_WIDTH },
126026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_223_CHECKER_TYPE,
126027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_223_WIDTH },
126028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_224_CHECKER_TYPE,
126029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_224_WIDTH },
126030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_225_CHECKER_TYPE,
126031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_225_WIDTH },
126032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_226_CHECKER_TYPE,
126033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_226_WIDTH },
126034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_227_CHECKER_TYPE,
126035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_227_WIDTH },
126036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_228_CHECKER_TYPE,
126037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_228_WIDTH },
126038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_229_CHECKER_TYPE,
126039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_229_WIDTH },
126040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_230_CHECKER_TYPE,
126041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_230_WIDTH },
126042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_231_CHECKER_TYPE,
126043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_231_WIDTH },
126044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_232_CHECKER_TYPE,
126045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_232_WIDTH },
126046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_233_CHECKER_TYPE,
126047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_233_WIDTH },
126048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_234_CHECKER_TYPE,
126049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_234_WIDTH },
126050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_235_CHECKER_TYPE,
126051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_235_WIDTH },
126052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_236_CHECKER_TYPE,
126053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_236_WIDTH },
126054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_237_CHECKER_TYPE,
126055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_237_WIDTH },
126056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_238_CHECKER_TYPE,
126057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_238_WIDTH },
126058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_239_CHECKER_TYPE,
126059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_239_WIDTH },
126060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_240_CHECKER_TYPE,
126061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_240_WIDTH },
126062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_241_CHECKER_TYPE,
126063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_241_WIDTH },
126064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_242_CHECKER_TYPE,
126065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_242_WIDTH },
126066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_243_CHECKER_TYPE,
126067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_243_WIDTH },
126068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_244_CHECKER_TYPE,
126069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_244_WIDTH },
126070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_245_CHECKER_TYPE,
126071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_245_WIDTH },
126072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_246_CHECKER_TYPE,
126073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_246_WIDTH },
126074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_247_CHECKER_TYPE,
126075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_247_WIDTH },
126076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_248_CHECKER_TYPE,
126077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_248_WIDTH },
126078  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_249_CHECKER_TYPE,
126079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_249_WIDTH },
126080  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_250_CHECKER_TYPE,
126081  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_250_WIDTH },
126082  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_251_CHECKER_TYPE,
126083  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_251_WIDTH },
126084  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_252_CHECKER_TYPE,
126085  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_252_WIDTH },
126086  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_253_CHECKER_TYPE,
126087  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_253_WIDTH },
126088  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_254_CHECKER_TYPE,
126089  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_254_WIDTH },
126090  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_255_CHECKER_TYPE,
126091  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_GROUP_255_WIDTH },
126092 };
126093 
126099 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_MAX_NUM_CHECKERS] =
126100 {
126101  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_0_CHECKER_TYPE,
126102  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_0_WIDTH },
126103  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_1_CHECKER_TYPE,
126104  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_1_WIDTH },
126105  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_2_CHECKER_TYPE,
126106  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_2_WIDTH },
126107  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_3_CHECKER_TYPE,
126108  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_3_WIDTH },
126109  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_4_CHECKER_TYPE,
126110  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_4_WIDTH },
126111  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_5_CHECKER_TYPE,
126112  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_5_WIDTH },
126113  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_6_CHECKER_TYPE,
126114  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_6_WIDTH },
126115  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_7_CHECKER_TYPE,
126116  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_7_WIDTH },
126117  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_8_CHECKER_TYPE,
126118  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_8_WIDTH },
126119  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_9_CHECKER_TYPE,
126120  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_9_WIDTH },
126121  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_10_CHECKER_TYPE,
126122  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_10_WIDTH },
126123  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_11_CHECKER_TYPE,
126124  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_11_WIDTH },
126125  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_12_CHECKER_TYPE,
126126  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_12_WIDTH },
126127  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_13_CHECKER_TYPE,
126128  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_13_WIDTH },
126129  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_14_CHECKER_TYPE,
126130  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_14_WIDTH },
126131  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_15_CHECKER_TYPE,
126132  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_15_WIDTH },
126133  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_16_CHECKER_TYPE,
126134  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_16_WIDTH },
126135  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_17_CHECKER_TYPE,
126136  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_17_WIDTH },
126137  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_18_CHECKER_TYPE,
126138  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_18_WIDTH },
126139  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_19_CHECKER_TYPE,
126140  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_19_WIDTH },
126141  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_20_CHECKER_TYPE,
126142  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_20_WIDTH },
126143  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_21_CHECKER_TYPE,
126144  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_21_WIDTH },
126145  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_22_CHECKER_TYPE,
126146  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_22_WIDTH },
126147  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_23_CHECKER_TYPE,
126148  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_23_WIDTH },
126149  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_24_CHECKER_TYPE,
126150  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_24_WIDTH },
126151  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_25_CHECKER_TYPE,
126152  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_25_WIDTH },
126153  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_26_CHECKER_TYPE,
126154  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_26_WIDTH },
126155  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_27_CHECKER_TYPE,
126156  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_27_WIDTH },
126157  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_28_CHECKER_TYPE,
126158  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_28_WIDTH },
126159  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_29_CHECKER_TYPE,
126160  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_29_WIDTH },
126161  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_30_CHECKER_TYPE,
126162  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_30_WIDTH },
126163  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_31_CHECKER_TYPE,
126164  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_31_WIDTH },
126165  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_32_CHECKER_TYPE,
126166  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_32_WIDTH },
126167  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_33_CHECKER_TYPE,
126168  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_33_WIDTH },
126169  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_34_CHECKER_TYPE,
126170  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_34_WIDTH },
126171  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_35_CHECKER_TYPE,
126172  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_35_WIDTH },
126173  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_36_CHECKER_TYPE,
126174  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_36_WIDTH },
126175  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_37_CHECKER_TYPE,
126176  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_37_WIDTH },
126177  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_38_CHECKER_TYPE,
126178  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_38_WIDTH },
126179  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_39_CHECKER_TYPE,
126180  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_39_WIDTH },
126181  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_40_CHECKER_TYPE,
126182  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_40_WIDTH },
126183  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_41_CHECKER_TYPE,
126184  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_41_WIDTH },
126185  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_42_CHECKER_TYPE,
126186  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_42_WIDTH },
126187  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_43_CHECKER_TYPE,
126188  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_43_WIDTH },
126189  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_44_CHECKER_TYPE,
126190  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_44_WIDTH },
126191  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_45_CHECKER_TYPE,
126192  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_45_WIDTH },
126193  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_46_CHECKER_TYPE,
126194  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_46_WIDTH },
126195  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_47_CHECKER_TYPE,
126196  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_47_WIDTH },
126197  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_48_CHECKER_TYPE,
126198  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_48_WIDTH },
126199  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_49_CHECKER_TYPE,
126200  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_49_WIDTH },
126201  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_50_CHECKER_TYPE,
126202  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_50_WIDTH },
126203  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_51_CHECKER_TYPE,
126204  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_51_WIDTH },
126205  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_52_CHECKER_TYPE,
126206  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_52_WIDTH },
126207  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_53_CHECKER_TYPE,
126208  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_53_WIDTH },
126209  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_54_CHECKER_TYPE,
126210  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_54_WIDTH },
126211  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_55_CHECKER_TYPE,
126212  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_55_WIDTH },
126213  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_56_CHECKER_TYPE,
126214  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_56_WIDTH },
126215  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_57_CHECKER_TYPE,
126216  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_57_WIDTH },
126217  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_58_CHECKER_TYPE,
126218  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_58_WIDTH },
126219  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_59_CHECKER_TYPE,
126220  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_59_WIDTH },
126221  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_60_CHECKER_TYPE,
126222  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_60_WIDTH },
126223  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_61_CHECKER_TYPE,
126224  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_61_WIDTH },
126225  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_62_CHECKER_TYPE,
126226  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_62_WIDTH },
126227  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_63_CHECKER_TYPE,
126228  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_63_WIDTH },
126229  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_64_CHECKER_TYPE,
126230  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_64_WIDTH },
126231  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_65_CHECKER_TYPE,
126232  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_65_WIDTH },
126233  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_66_CHECKER_TYPE,
126234  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_66_WIDTH },
126235  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_67_CHECKER_TYPE,
126236  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_67_WIDTH },
126237  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_68_CHECKER_TYPE,
126238  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_68_WIDTH },
126239  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_69_CHECKER_TYPE,
126240  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_69_WIDTH },
126241  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_70_CHECKER_TYPE,
126242  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_70_WIDTH },
126243  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_71_CHECKER_TYPE,
126244  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_71_WIDTH },
126245  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_72_CHECKER_TYPE,
126246  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_72_WIDTH },
126247  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_73_CHECKER_TYPE,
126248  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_73_WIDTH },
126249  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_74_CHECKER_TYPE,
126250  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_74_WIDTH },
126251  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_75_CHECKER_TYPE,
126252  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_75_WIDTH },
126253  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_76_CHECKER_TYPE,
126254  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_76_WIDTH },
126255  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_77_CHECKER_TYPE,
126256  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_77_WIDTH },
126257  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_78_CHECKER_TYPE,
126258  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_78_WIDTH },
126259  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_79_CHECKER_TYPE,
126260  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_79_WIDTH },
126261  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_80_CHECKER_TYPE,
126262  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_80_WIDTH },
126263  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_81_CHECKER_TYPE,
126264  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_81_WIDTH },
126265  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_82_CHECKER_TYPE,
126266  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_82_WIDTH },
126267  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_83_CHECKER_TYPE,
126268  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_83_WIDTH },
126269  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_84_CHECKER_TYPE,
126270  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_84_WIDTH },
126271  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_85_CHECKER_TYPE,
126272  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_85_WIDTH },
126273  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_86_CHECKER_TYPE,
126274  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_86_WIDTH },
126275  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_87_CHECKER_TYPE,
126276  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_87_WIDTH },
126277  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_88_CHECKER_TYPE,
126278  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_88_WIDTH },
126279  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_89_CHECKER_TYPE,
126280  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_89_WIDTH },
126281  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_90_CHECKER_TYPE,
126282  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_90_WIDTH },
126283  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_91_CHECKER_TYPE,
126284  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_91_WIDTH },
126285  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_92_CHECKER_TYPE,
126286  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_92_WIDTH },
126287  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_93_CHECKER_TYPE,
126288  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_93_WIDTH },
126289  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_94_CHECKER_TYPE,
126290  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_94_WIDTH },
126291  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_95_CHECKER_TYPE,
126292  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_95_WIDTH },
126293  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_96_CHECKER_TYPE,
126294  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_96_WIDTH },
126295  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_97_CHECKER_TYPE,
126296  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_97_WIDTH },
126297  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_98_CHECKER_TYPE,
126298  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_98_WIDTH },
126299  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_99_CHECKER_TYPE,
126300  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_99_WIDTH },
126301  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_100_CHECKER_TYPE,
126302  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_100_WIDTH },
126303  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_101_CHECKER_TYPE,
126304  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_101_WIDTH },
126305  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_102_CHECKER_TYPE,
126306  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_102_WIDTH },
126307  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_103_CHECKER_TYPE,
126308  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_103_WIDTH },
126309  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_104_CHECKER_TYPE,
126310  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_104_WIDTH },
126311  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_105_CHECKER_TYPE,
126312  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_105_WIDTH },
126313  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_106_CHECKER_TYPE,
126314  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_106_WIDTH },
126315  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_107_CHECKER_TYPE,
126316  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_107_WIDTH },
126317  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_108_CHECKER_TYPE,
126318  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_108_WIDTH },
126319  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_109_CHECKER_TYPE,
126320  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_109_WIDTH },
126321  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_110_CHECKER_TYPE,
126322  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_110_WIDTH },
126323  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_111_CHECKER_TYPE,
126324  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_111_WIDTH },
126325  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_112_CHECKER_TYPE,
126326  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_112_WIDTH },
126327  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_113_CHECKER_TYPE,
126328  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_113_WIDTH },
126329  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_114_CHECKER_TYPE,
126330  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_114_WIDTH },
126331  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_115_CHECKER_TYPE,
126332  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_115_WIDTH },
126333  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_116_CHECKER_TYPE,
126334  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_116_WIDTH },
126335  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_117_CHECKER_TYPE,
126336  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_117_WIDTH },
126337  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_118_CHECKER_TYPE,
126338  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_118_WIDTH },
126339  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_119_CHECKER_TYPE,
126340  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_119_WIDTH },
126341  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_120_CHECKER_TYPE,
126342  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_120_WIDTH },
126343  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_121_CHECKER_TYPE,
126344  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_121_WIDTH },
126345  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_122_CHECKER_TYPE,
126346  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_122_WIDTH },
126347  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_123_CHECKER_TYPE,
126348  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_123_WIDTH },
126349  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_124_CHECKER_TYPE,
126350  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_124_WIDTH },
126351  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_125_CHECKER_TYPE,
126352  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_125_WIDTH },
126353  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_126_CHECKER_TYPE,
126354  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_126_WIDTH },
126355  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_127_CHECKER_TYPE,
126356  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_127_WIDTH },
126357  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_128_CHECKER_TYPE,
126358  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_128_WIDTH },
126359  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_129_CHECKER_TYPE,
126360  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_129_WIDTH },
126361  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_130_CHECKER_TYPE,
126362  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_130_WIDTH },
126363  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_131_CHECKER_TYPE,
126364  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_131_WIDTH },
126365  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_132_CHECKER_TYPE,
126366  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_132_WIDTH },
126367  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_133_CHECKER_TYPE,
126368  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_133_WIDTH },
126369  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_134_CHECKER_TYPE,
126370  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_134_WIDTH },
126371  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_135_CHECKER_TYPE,
126372  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_135_WIDTH },
126373  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_136_CHECKER_TYPE,
126374  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_136_WIDTH },
126375  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_137_CHECKER_TYPE,
126376  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_137_WIDTH },
126377  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_138_CHECKER_TYPE,
126378  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_138_WIDTH },
126379  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_139_CHECKER_TYPE,
126380  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_139_WIDTH },
126381  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_140_CHECKER_TYPE,
126382  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_140_WIDTH },
126383  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_141_CHECKER_TYPE,
126384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_141_WIDTH },
126385  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_142_CHECKER_TYPE,
126386  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_142_WIDTH },
126387  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_143_CHECKER_TYPE,
126388  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_143_WIDTH },
126389  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_144_CHECKER_TYPE,
126390  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_144_WIDTH },
126391  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_145_CHECKER_TYPE,
126392  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_145_WIDTH },
126393  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_146_CHECKER_TYPE,
126394  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_146_WIDTH },
126395  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_147_CHECKER_TYPE,
126396  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_147_WIDTH },
126397  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_148_CHECKER_TYPE,
126398  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_148_WIDTH },
126399  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_149_CHECKER_TYPE,
126400  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_149_WIDTH },
126401  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_150_CHECKER_TYPE,
126402  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_150_WIDTH },
126403  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_151_CHECKER_TYPE,
126404  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_151_WIDTH },
126405  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_152_CHECKER_TYPE,
126406  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_152_WIDTH },
126407  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_153_CHECKER_TYPE,
126408  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_153_WIDTH },
126409  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_154_CHECKER_TYPE,
126410  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_154_WIDTH },
126411  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_155_CHECKER_TYPE,
126412  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_155_WIDTH },
126413  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_156_CHECKER_TYPE,
126414  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_156_WIDTH },
126415  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_157_CHECKER_TYPE,
126416  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_157_WIDTH },
126417  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_158_CHECKER_TYPE,
126418  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_158_WIDTH },
126419  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_159_CHECKER_TYPE,
126420  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_159_WIDTH },
126421  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_160_CHECKER_TYPE,
126422  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_160_WIDTH },
126423  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_161_CHECKER_TYPE,
126424  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_161_WIDTH },
126425  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_162_CHECKER_TYPE,
126426  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_162_WIDTH },
126427  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_163_CHECKER_TYPE,
126428  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_163_WIDTH },
126429  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_164_CHECKER_TYPE,
126430  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_164_WIDTH },
126431  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_165_CHECKER_TYPE,
126432  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_165_WIDTH },
126433  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_166_CHECKER_TYPE,
126434  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_166_WIDTH },
126435  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_167_CHECKER_TYPE,
126436  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_167_WIDTH },
126437  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_168_CHECKER_TYPE,
126438  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_168_WIDTH },
126439  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_169_CHECKER_TYPE,
126440  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_169_WIDTH },
126441  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_170_CHECKER_TYPE,
126442  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_170_WIDTH },
126443  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_171_CHECKER_TYPE,
126444  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_171_WIDTH },
126445  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_172_CHECKER_TYPE,
126446  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_172_WIDTH },
126447  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_173_CHECKER_TYPE,
126448  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_173_WIDTH },
126449  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_174_CHECKER_TYPE,
126450  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_174_WIDTH },
126451  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_175_CHECKER_TYPE,
126452  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_175_WIDTH },
126453  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_176_CHECKER_TYPE,
126454  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_176_WIDTH },
126455  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_177_CHECKER_TYPE,
126456  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_177_WIDTH },
126457  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_178_CHECKER_TYPE,
126458  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_178_WIDTH },
126459  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_179_CHECKER_TYPE,
126460  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_179_WIDTH },
126461  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_180_CHECKER_TYPE,
126462  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_180_WIDTH },
126463  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_181_CHECKER_TYPE,
126464  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_181_WIDTH },
126465  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_182_CHECKER_TYPE,
126466  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_182_WIDTH },
126467  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_183_CHECKER_TYPE,
126468  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_183_WIDTH },
126469  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_184_CHECKER_TYPE,
126470  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_184_WIDTH },
126471  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_185_CHECKER_TYPE,
126472  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_185_WIDTH },
126473  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_186_CHECKER_TYPE,
126474  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_186_WIDTH },
126475  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_187_CHECKER_TYPE,
126476  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_187_WIDTH },
126477  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_188_CHECKER_TYPE,
126478  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_188_WIDTH },
126479  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_189_CHECKER_TYPE,
126480  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_189_WIDTH },
126481  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_190_CHECKER_TYPE,
126482  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_190_WIDTH },
126483  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_191_CHECKER_TYPE,
126484  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_GROUP_191_WIDTH },
126485 };
126486 
126492 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS] =
126493 {
126494  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_0_CHECKER_TYPE,
126495  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_0_WIDTH },
126496  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_1_CHECKER_TYPE,
126497  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_1_WIDTH },
126498  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_2_CHECKER_TYPE,
126499  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_2_WIDTH },
126500  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_3_CHECKER_TYPE,
126501  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_3_WIDTH },
126502  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_4_CHECKER_TYPE,
126503  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_4_WIDTH },
126504  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_5_CHECKER_TYPE,
126505  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_5_WIDTH },
126506  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_6_CHECKER_TYPE,
126507  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_6_WIDTH },
126508  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_7_CHECKER_TYPE,
126509  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_7_WIDTH },
126510  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_8_CHECKER_TYPE,
126511  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_8_WIDTH },
126512  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_9_CHECKER_TYPE,
126513  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_9_WIDTH },
126514  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_10_CHECKER_TYPE,
126515  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_10_WIDTH },
126516  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_11_CHECKER_TYPE,
126517  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_11_WIDTH },
126518  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_12_CHECKER_TYPE,
126519  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_12_WIDTH },
126520  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_13_CHECKER_TYPE,
126521  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_13_WIDTH },
126522  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_14_CHECKER_TYPE,
126523  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_14_WIDTH },
126524  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_15_CHECKER_TYPE,
126525  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_15_WIDTH },
126526  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_16_CHECKER_TYPE,
126527  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_16_WIDTH },
126528  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_17_CHECKER_TYPE,
126529  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_17_WIDTH },
126530  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_18_CHECKER_TYPE,
126531  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_18_WIDTH },
126532  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_19_CHECKER_TYPE,
126533  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_19_WIDTH },
126534  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_20_CHECKER_TYPE,
126535  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_20_WIDTH },
126536  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_21_CHECKER_TYPE,
126537  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_21_WIDTH },
126538  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_22_CHECKER_TYPE,
126539  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_GROUP_22_WIDTH },
126540 };
126541 
126547 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS] =
126548 {
126549  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
126550  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_0_WIDTH },
126551  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
126552  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_1_WIDTH },
126553  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
126554  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_2_WIDTH },
126555  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
126556  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_3_WIDTH },
126557  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
126558  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_4_WIDTH },
126559  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
126560  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_5_WIDTH },
126561  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
126562  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_6_WIDTH },
126563  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
126564  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_7_WIDTH },
126565  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
126566  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_8_WIDTH },
126567  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
126568  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_9_WIDTH },
126569  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
126570  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_10_WIDTH },
126571  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
126572  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_11_WIDTH },
126573  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
126574  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_12_WIDTH },
126575  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
126576  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_13_WIDTH },
126577  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
126578  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_14_WIDTH },
126579  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
126580  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_15_WIDTH },
126581  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
126582  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_16_WIDTH },
126583  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
126584  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_17_WIDTH },
126585  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
126586  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_18_WIDTH },
126587  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
126588  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_19_WIDTH },
126589  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
126590  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_20_WIDTH },
126591  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
126592  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_21_WIDTH },
126593  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
126594  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_22_WIDTH },
126595  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
126596  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_23_WIDTH },
126597  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
126598  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_24_WIDTH },
126599  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
126600  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_25_WIDTH },
126601  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
126602  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_GROUP_26_WIDTH },
126603 };
126604 
126610 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_MAX_NUM_CHECKERS] =
126611 {
126612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
126613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_0_WIDTH },
126614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
126615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_1_WIDTH },
126616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
126617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_2_WIDTH },
126618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
126619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_3_WIDTH },
126620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
126621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_4_WIDTH },
126622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
126623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_5_WIDTH },
126624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
126625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_6_WIDTH },
126626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
126627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_7_WIDTH },
126628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
126629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_8_WIDTH },
126630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
126631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_9_WIDTH },
126632  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
126633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_10_WIDTH },
126634  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_11_CHECKER_TYPE,
126635  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_11_WIDTH },
126636  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_12_CHECKER_TYPE,
126637  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_12_WIDTH },
126638  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_13_CHECKER_TYPE,
126639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_13_WIDTH },
126640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_14_CHECKER_TYPE,
126641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_14_WIDTH },
126642  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_15_CHECKER_TYPE,
126643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_GROUP_15_WIDTH },
126644 };
126645 
126651 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_MAX_NUM_CHECKERS] =
126652 {
126653  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_0_CHECKER_TYPE,
126654  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_0_WIDTH },
126655  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_1_CHECKER_TYPE,
126656  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_1_WIDTH },
126657  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_2_CHECKER_TYPE,
126658  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_2_WIDTH },
126659  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_3_CHECKER_TYPE,
126660  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_3_WIDTH },
126661  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_4_CHECKER_TYPE,
126662  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_4_WIDTH },
126663  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_5_CHECKER_TYPE,
126664  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_5_WIDTH },
126665  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_6_CHECKER_TYPE,
126666  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_6_WIDTH },
126667  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_7_CHECKER_TYPE,
126668  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_7_WIDTH },
126669  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_8_CHECKER_TYPE,
126670  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_8_WIDTH },
126671  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_9_CHECKER_TYPE,
126672  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_9_WIDTH },
126673  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_10_CHECKER_TYPE,
126674  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_10_WIDTH },
126675  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_11_CHECKER_TYPE,
126676  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_11_WIDTH },
126677  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_12_CHECKER_TYPE,
126678  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_12_WIDTH },
126679  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_13_CHECKER_TYPE,
126680  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_GROUP_13_WIDTH },
126681 };
126682 
126688 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_MAX_NUM_CHECKERS] =
126689 {
126690  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_0_CHECKER_TYPE,
126691  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_0_WIDTH },
126692  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_1_CHECKER_TYPE,
126693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_1_WIDTH },
126694  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_2_CHECKER_TYPE,
126695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_2_WIDTH },
126696  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_3_CHECKER_TYPE,
126697  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_3_WIDTH },
126698  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_4_CHECKER_TYPE,
126699  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_4_WIDTH },
126700  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_5_CHECKER_TYPE,
126701  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_5_WIDTH },
126702  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_6_CHECKER_TYPE,
126703  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_6_WIDTH },
126704  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_7_CHECKER_TYPE,
126705  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_7_WIDTH },
126706  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_8_CHECKER_TYPE,
126707  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_8_WIDTH },
126708  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_9_CHECKER_TYPE,
126709  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_9_WIDTH },
126710  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_10_CHECKER_TYPE,
126711  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_10_WIDTH },
126712  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_11_CHECKER_TYPE,
126713  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_11_WIDTH },
126714  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_12_CHECKER_TYPE,
126715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_12_WIDTH },
126716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_13_CHECKER_TYPE,
126717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_13_WIDTH },
126718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_14_CHECKER_TYPE,
126719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_14_WIDTH },
126720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_15_CHECKER_TYPE,
126721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_15_WIDTH },
126722  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_16_CHECKER_TYPE,
126723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_16_WIDTH },
126724  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_17_CHECKER_TYPE,
126725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_17_WIDTH },
126726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_18_CHECKER_TYPE,
126727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_18_WIDTH },
126728  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_19_CHECKER_TYPE,
126729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_19_WIDTH },
126730  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_20_CHECKER_TYPE,
126731  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_20_WIDTH },
126732  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_21_CHECKER_TYPE,
126733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_21_WIDTH },
126734  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_22_CHECKER_TYPE,
126735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_22_WIDTH },
126736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_23_CHECKER_TYPE,
126737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_23_WIDTH },
126738  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_24_CHECKER_TYPE,
126739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_24_WIDTH },
126740  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_25_CHECKER_TYPE,
126741  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_25_WIDTH },
126742  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_26_CHECKER_TYPE,
126743  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_26_WIDTH },
126744  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_27_CHECKER_TYPE,
126745  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_27_WIDTH },
126746  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_28_CHECKER_TYPE,
126747  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_28_WIDTH },
126748  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_29_CHECKER_TYPE,
126749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_29_WIDTH },
126750  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_30_CHECKER_TYPE,
126751  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_30_WIDTH },
126752  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_31_CHECKER_TYPE,
126753  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_31_WIDTH },
126754  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_32_CHECKER_TYPE,
126755  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_32_WIDTH },
126756  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_33_CHECKER_TYPE,
126757  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_33_WIDTH },
126758  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_34_CHECKER_TYPE,
126759  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_34_WIDTH },
126760  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_35_CHECKER_TYPE,
126761  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_35_WIDTH },
126762  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_36_CHECKER_TYPE,
126763  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_36_WIDTH },
126764  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_37_CHECKER_TYPE,
126765  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_37_WIDTH },
126766  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_38_CHECKER_TYPE,
126767  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_38_WIDTH },
126768  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_39_CHECKER_TYPE,
126769  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_39_WIDTH },
126770  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_40_CHECKER_TYPE,
126771  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_40_WIDTH },
126772  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_41_CHECKER_TYPE,
126773  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_41_WIDTH },
126774  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_42_CHECKER_TYPE,
126775  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_42_WIDTH },
126776  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_43_CHECKER_TYPE,
126777  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_43_WIDTH },
126778  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_44_CHECKER_TYPE,
126779  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_44_WIDTH },
126780  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_45_CHECKER_TYPE,
126781  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_45_WIDTH },
126782  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_46_CHECKER_TYPE,
126783  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_46_WIDTH },
126784  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_47_CHECKER_TYPE,
126785  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_47_WIDTH },
126786  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_48_CHECKER_TYPE,
126787  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_48_WIDTH },
126788  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_49_CHECKER_TYPE,
126789  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_49_WIDTH },
126790  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_50_CHECKER_TYPE,
126791  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_50_WIDTH },
126792  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_51_CHECKER_TYPE,
126793  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_51_WIDTH },
126794  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_52_CHECKER_TYPE,
126795  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_GROUP_52_WIDTH },
126796 };
126797 
126803 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS] =
126804 {
126805  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
126806  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_0_WIDTH },
126807  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
126808  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_1_WIDTH },
126809  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
126810  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_2_WIDTH },
126811  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
126812  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_3_WIDTH },
126813  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
126814  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_4_WIDTH },
126815  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
126816  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_5_WIDTH },
126817  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
126818  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_6_WIDTH },
126819  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
126820  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_7_WIDTH },
126821  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
126822  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_8_WIDTH },
126823  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
126824  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_9_WIDTH },
126825  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
126826  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_10_WIDTH },
126827  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
126828  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_11_WIDTH },
126829  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
126830  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_12_WIDTH },
126831  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
126832  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_13_WIDTH },
126833  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
126834  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_14_WIDTH },
126835  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
126836  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_15_WIDTH },
126837  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
126838  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_16_WIDTH },
126839  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
126840  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_17_WIDTH },
126841  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
126842  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_18_WIDTH },
126843  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
126844  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_19_WIDTH },
126845  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
126846  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_20_WIDTH },
126847  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
126848  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_21_WIDTH },
126849  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
126850  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_22_WIDTH },
126851  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
126852  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_23_WIDTH },
126853  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
126854  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_24_WIDTH },
126855  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
126856  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_25_WIDTH },
126857  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
126858  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_26_WIDTH },
126859  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_27_CHECKER_TYPE,
126860  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_27_WIDTH },
126861  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_28_CHECKER_TYPE,
126862  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_28_WIDTH },
126863  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_29_CHECKER_TYPE,
126864  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_29_WIDTH },
126865  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_30_CHECKER_TYPE,
126866  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_30_WIDTH },
126867  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_31_CHECKER_TYPE,
126868  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_31_WIDTH },
126869  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_32_CHECKER_TYPE,
126870  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_32_WIDTH },
126871  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_33_CHECKER_TYPE,
126872  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_33_WIDTH },
126873  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_34_CHECKER_TYPE,
126874  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_34_WIDTH },
126875  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_35_CHECKER_TYPE,
126876  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_35_WIDTH },
126877  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_36_CHECKER_TYPE,
126878  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_36_WIDTH },
126879  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_37_CHECKER_TYPE,
126880  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_37_WIDTH },
126881  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_38_CHECKER_TYPE,
126882  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_38_WIDTH },
126883  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_39_CHECKER_TYPE,
126884  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_39_WIDTH },
126885  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_40_CHECKER_TYPE,
126886  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_40_WIDTH },
126887  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_41_CHECKER_TYPE,
126888  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_41_WIDTH },
126889  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_42_CHECKER_TYPE,
126890  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_42_WIDTH },
126891  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_43_CHECKER_TYPE,
126892  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_43_WIDTH },
126893  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_44_CHECKER_TYPE,
126894  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_44_WIDTH },
126895  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_45_CHECKER_TYPE,
126896  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_45_WIDTH },
126897  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_46_CHECKER_TYPE,
126898  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_46_WIDTH },
126899  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_47_CHECKER_TYPE,
126900  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_GROUP_47_WIDTH },
126901 };
126902 
126908 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_MAX_NUM_CHECKERS] =
126909 {
126910  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_0_CHECKER_TYPE,
126911  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_0_WIDTH },
126912  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_1_CHECKER_TYPE,
126913  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_1_WIDTH },
126914  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_2_CHECKER_TYPE,
126915  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_2_WIDTH },
126916  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_3_CHECKER_TYPE,
126917  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_3_WIDTH },
126918  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_4_CHECKER_TYPE,
126919  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_4_WIDTH },
126920  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_5_CHECKER_TYPE,
126921  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_5_WIDTH },
126922  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_6_CHECKER_TYPE,
126923  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_6_WIDTH },
126924  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_7_CHECKER_TYPE,
126925  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_7_WIDTH },
126926  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_8_CHECKER_TYPE,
126927  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_8_WIDTH },
126928  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_9_CHECKER_TYPE,
126929  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_9_WIDTH },
126930  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_10_CHECKER_TYPE,
126931  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_10_WIDTH },
126932  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_11_CHECKER_TYPE,
126933  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_11_WIDTH },
126934  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_12_CHECKER_TYPE,
126935  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_12_WIDTH },
126936  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_13_CHECKER_TYPE,
126937  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_13_WIDTH },
126938  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_14_CHECKER_TYPE,
126939  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_14_WIDTH },
126940  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_15_CHECKER_TYPE,
126941  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_15_WIDTH },
126942  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_16_CHECKER_TYPE,
126943  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_16_WIDTH },
126944  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_17_CHECKER_TYPE,
126945  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_17_WIDTH },
126946  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_18_CHECKER_TYPE,
126947  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_18_WIDTH },
126948  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_19_CHECKER_TYPE,
126949  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_19_WIDTH },
126950  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_20_CHECKER_TYPE,
126951  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_20_WIDTH },
126952  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_21_CHECKER_TYPE,
126953  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_21_WIDTH },
126954  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_22_CHECKER_TYPE,
126955  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_22_WIDTH },
126956  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_23_CHECKER_TYPE,
126957  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_23_WIDTH },
126958  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_24_CHECKER_TYPE,
126959  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_24_WIDTH },
126960  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_25_CHECKER_TYPE,
126961  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_25_WIDTH },
126962  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_26_CHECKER_TYPE,
126963  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_26_WIDTH },
126964  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_27_CHECKER_TYPE,
126965  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_27_WIDTH },
126966  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_28_CHECKER_TYPE,
126967  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_28_WIDTH },
126968  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_29_CHECKER_TYPE,
126969  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_29_WIDTH },
126970  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_30_CHECKER_TYPE,
126971  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_30_WIDTH },
126972  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_31_CHECKER_TYPE,
126973  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_31_WIDTH },
126974  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_32_CHECKER_TYPE,
126975  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_32_WIDTH },
126976  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_33_CHECKER_TYPE,
126977  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_33_WIDTH },
126978  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_34_CHECKER_TYPE,
126979  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_34_WIDTH },
126980  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_35_CHECKER_TYPE,
126981  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_35_WIDTH },
126982  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_36_CHECKER_TYPE,
126983  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_36_WIDTH },
126984  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_37_CHECKER_TYPE,
126985  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_37_WIDTH },
126986  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_38_CHECKER_TYPE,
126987  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_38_WIDTH },
126988  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_39_CHECKER_TYPE,
126989  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_39_WIDTH },
126990  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_40_CHECKER_TYPE,
126991  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_40_WIDTH },
126992  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_41_CHECKER_TYPE,
126993  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_41_WIDTH },
126994  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_42_CHECKER_TYPE,
126995  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_42_WIDTH },
126996  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_43_CHECKER_TYPE,
126997  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_43_WIDTH },
126998  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_44_CHECKER_TYPE,
126999  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_44_WIDTH },
127000  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_45_CHECKER_TYPE,
127001  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_45_WIDTH },
127002  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_46_CHECKER_TYPE,
127003  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_46_WIDTH },
127004  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_47_CHECKER_TYPE,
127005  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_47_WIDTH },
127006  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_48_CHECKER_TYPE,
127007  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_48_WIDTH },
127008  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_49_CHECKER_TYPE,
127009  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_49_WIDTH },
127010  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_50_CHECKER_TYPE,
127011  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_50_WIDTH },
127012  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_51_CHECKER_TYPE,
127013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_51_WIDTH },
127014  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_52_CHECKER_TYPE,
127015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_52_WIDTH },
127016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_53_CHECKER_TYPE,
127017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_53_WIDTH },
127018  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_54_CHECKER_TYPE,
127019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_54_WIDTH },
127020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_55_CHECKER_TYPE,
127021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_55_WIDTH },
127022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_56_CHECKER_TYPE,
127023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_56_WIDTH },
127024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_57_CHECKER_TYPE,
127025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_57_WIDTH },
127026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_58_CHECKER_TYPE,
127027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_58_WIDTH },
127028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_59_CHECKER_TYPE,
127029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_59_WIDTH },
127030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_60_CHECKER_TYPE,
127031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_60_WIDTH },
127032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_61_CHECKER_TYPE,
127033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_61_WIDTH },
127034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_62_CHECKER_TYPE,
127035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_62_WIDTH },
127036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_63_CHECKER_TYPE,
127037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_63_WIDTH },
127038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_64_CHECKER_TYPE,
127039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_64_WIDTH },
127040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_65_CHECKER_TYPE,
127041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_65_WIDTH },
127042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_66_CHECKER_TYPE,
127043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_66_WIDTH },
127044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_67_CHECKER_TYPE,
127045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_67_WIDTH },
127046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_68_CHECKER_TYPE,
127047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_68_WIDTH },
127048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_69_CHECKER_TYPE,
127049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_69_WIDTH },
127050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_70_CHECKER_TYPE,
127051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_70_WIDTH },
127052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_71_CHECKER_TYPE,
127053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_71_WIDTH },
127054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_72_CHECKER_TYPE,
127055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_72_WIDTH },
127056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_73_CHECKER_TYPE,
127057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_73_WIDTH },
127058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_74_CHECKER_TYPE,
127059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_74_WIDTH },
127060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_75_CHECKER_TYPE,
127061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_75_WIDTH },
127062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_76_CHECKER_TYPE,
127063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_76_WIDTH },
127064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_77_CHECKER_TYPE,
127065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_77_WIDTH },
127066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_78_CHECKER_TYPE,
127067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_78_WIDTH },
127068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_79_CHECKER_TYPE,
127069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_79_WIDTH },
127070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_80_CHECKER_TYPE,
127071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_80_WIDTH },
127072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_81_CHECKER_TYPE,
127073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_81_WIDTH },
127074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_82_CHECKER_TYPE,
127075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_82_WIDTH },
127076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_83_CHECKER_TYPE,
127077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_83_WIDTH },
127078  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_84_CHECKER_TYPE,
127079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_84_WIDTH },
127080  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_85_CHECKER_TYPE,
127081  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_85_WIDTH },
127082  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_86_CHECKER_TYPE,
127083  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_86_WIDTH },
127084  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_87_CHECKER_TYPE,
127085  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_87_WIDTH },
127086  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_88_CHECKER_TYPE,
127087  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_88_WIDTH },
127088  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_89_CHECKER_TYPE,
127089  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_89_WIDTH },
127090  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_90_CHECKER_TYPE,
127091  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_90_WIDTH },
127092  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_91_CHECKER_TYPE,
127093  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_91_WIDTH },
127094  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_92_CHECKER_TYPE,
127095  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_92_WIDTH },
127096  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_93_CHECKER_TYPE,
127097  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_93_WIDTH },
127098  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_94_CHECKER_TYPE,
127099  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_94_WIDTH },
127100  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_95_CHECKER_TYPE,
127101  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_95_WIDTH },
127102  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_96_CHECKER_TYPE,
127103  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_96_WIDTH },
127104  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_97_CHECKER_TYPE,
127105  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_97_WIDTH },
127106  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_98_CHECKER_TYPE,
127107  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_98_WIDTH },
127108  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_99_CHECKER_TYPE,
127109  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_99_WIDTH },
127110  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_100_CHECKER_TYPE,
127111  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_100_WIDTH },
127112  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_101_CHECKER_TYPE,
127113  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_101_WIDTH },
127114  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_102_CHECKER_TYPE,
127115  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_102_WIDTH },
127116  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_103_CHECKER_TYPE,
127117  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_103_WIDTH },
127118  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_104_CHECKER_TYPE,
127119  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_104_WIDTH },
127120  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_105_CHECKER_TYPE,
127121  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_105_WIDTH },
127122  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_106_CHECKER_TYPE,
127123  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_106_WIDTH },
127124  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_107_CHECKER_TYPE,
127125  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_107_WIDTH },
127126  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_108_CHECKER_TYPE,
127127  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_108_WIDTH },
127128  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_109_CHECKER_TYPE,
127129  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_109_WIDTH },
127130  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_110_CHECKER_TYPE,
127131  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_110_WIDTH },
127132  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_111_CHECKER_TYPE,
127133  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_111_WIDTH },
127134  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_112_CHECKER_TYPE,
127135  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_112_WIDTH },
127136  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_113_CHECKER_TYPE,
127137  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_113_WIDTH },
127138  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_114_CHECKER_TYPE,
127139  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_114_WIDTH },
127140  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_115_CHECKER_TYPE,
127141  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_115_WIDTH },
127142  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_116_CHECKER_TYPE,
127143  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_116_WIDTH },
127144  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_117_CHECKER_TYPE,
127145  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_117_WIDTH },
127146  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_118_CHECKER_TYPE,
127147  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_118_WIDTH },
127148  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_119_CHECKER_TYPE,
127149  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_119_WIDTH },
127150  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_120_CHECKER_TYPE,
127151  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_120_WIDTH },
127152  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_121_CHECKER_TYPE,
127153  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_121_WIDTH },
127154  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_122_CHECKER_TYPE,
127155  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_122_WIDTH },
127156  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_123_CHECKER_TYPE,
127157  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_123_WIDTH },
127158  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_124_CHECKER_TYPE,
127159  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_124_WIDTH },
127160  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_125_CHECKER_TYPE,
127161  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_125_WIDTH },
127162  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_126_CHECKER_TYPE,
127163  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_126_WIDTH },
127164  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_127_CHECKER_TYPE,
127165  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_127_WIDTH },
127166  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_128_CHECKER_TYPE,
127167  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_128_WIDTH },
127168  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_129_CHECKER_TYPE,
127169  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_129_WIDTH },
127170  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_130_CHECKER_TYPE,
127171  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_130_WIDTH },
127172  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_131_CHECKER_TYPE,
127173  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_131_WIDTH },
127174  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_132_CHECKER_TYPE,
127175  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_132_WIDTH },
127176  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_133_CHECKER_TYPE,
127177  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_133_WIDTH },
127178  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_134_CHECKER_TYPE,
127179  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_134_WIDTH },
127180  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_135_CHECKER_TYPE,
127181  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_135_WIDTH },
127182  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_136_CHECKER_TYPE,
127183  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_136_WIDTH },
127184  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_137_CHECKER_TYPE,
127185  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_137_WIDTH },
127186  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_138_CHECKER_TYPE,
127187  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_138_WIDTH },
127188  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_139_CHECKER_TYPE,
127189  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_139_WIDTH },
127190  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_140_CHECKER_TYPE,
127191  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_140_WIDTH },
127192  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_141_CHECKER_TYPE,
127193  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_141_WIDTH },
127194  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_142_CHECKER_TYPE,
127195  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_142_WIDTH },
127196  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_143_CHECKER_TYPE,
127197  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_143_WIDTH },
127198  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_144_CHECKER_TYPE,
127199  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_144_WIDTH },
127200  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_145_CHECKER_TYPE,
127201  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_145_WIDTH },
127202  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_146_CHECKER_TYPE,
127203  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_146_WIDTH },
127204  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_147_CHECKER_TYPE,
127205  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_147_WIDTH },
127206  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_148_CHECKER_TYPE,
127207  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_148_WIDTH },
127208  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_149_CHECKER_TYPE,
127209  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_149_WIDTH },
127210  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_150_CHECKER_TYPE,
127211  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_150_WIDTH },
127212  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_151_CHECKER_TYPE,
127213  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_151_WIDTH },
127214  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_152_CHECKER_TYPE,
127215  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_152_WIDTH },
127216  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_153_CHECKER_TYPE,
127217  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_153_WIDTH },
127218  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_154_CHECKER_TYPE,
127219  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_154_WIDTH },
127220  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_155_CHECKER_TYPE,
127221  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_155_WIDTH },
127222  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_156_CHECKER_TYPE,
127223  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_156_WIDTH },
127224  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_157_CHECKER_TYPE,
127225  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_157_WIDTH },
127226  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_158_CHECKER_TYPE,
127227  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_158_WIDTH },
127228  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_159_CHECKER_TYPE,
127229  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_159_WIDTH },
127230  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_160_CHECKER_TYPE,
127231  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_160_WIDTH },
127232  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_161_CHECKER_TYPE,
127233  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_161_WIDTH },
127234  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_162_CHECKER_TYPE,
127235  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_162_WIDTH },
127236  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_163_CHECKER_TYPE,
127237  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_163_WIDTH },
127238  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_164_CHECKER_TYPE,
127239  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_164_WIDTH },
127240  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_165_CHECKER_TYPE,
127241  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_165_WIDTH },
127242  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_166_CHECKER_TYPE,
127243  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_166_WIDTH },
127244  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_167_CHECKER_TYPE,
127245  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_167_WIDTH },
127246  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_168_CHECKER_TYPE,
127247  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_168_WIDTH },
127248  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_169_CHECKER_TYPE,
127249  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_169_WIDTH },
127250  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_170_CHECKER_TYPE,
127251  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_170_WIDTH },
127252  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_171_CHECKER_TYPE,
127253  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_171_WIDTH },
127254  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_172_CHECKER_TYPE,
127255  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_172_WIDTH },
127256  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_173_CHECKER_TYPE,
127257  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_173_WIDTH },
127258  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_174_CHECKER_TYPE,
127259  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_174_WIDTH },
127260  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_175_CHECKER_TYPE,
127261  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_175_WIDTH },
127262  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_176_CHECKER_TYPE,
127263  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_176_WIDTH },
127264  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_177_CHECKER_TYPE,
127265  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_177_WIDTH },
127266  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_178_CHECKER_TYPE,
127267  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_178_WIDTH },
127268  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_179_CHECKER_TYPE,
127269  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_179_WIDTH },
127270  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_180_CHECKER_TYPE,
127271  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_180_WIDTH },
127272  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_181_CHECKER_TYPE,
127273  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_181_WIDTH },
127274  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_182_CHECKER_TYPE,
127275  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_182_WIDTH },
127276  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_183_CHECKER_TYPE,
127277  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_183_WIDTH },
127278  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_184_CHECKER_TYPE,
127279  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_184_WIDTH },
127280  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_185_CHECKER_TYPE,
127281  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_185_WIDTH },
127282  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_186_CHECKER_TYPE,
127283  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_186_WIDTH },
127284  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_187_CHECKER_TYPE,
127285  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_187_WIDTH },
127286  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_188_CHECKER_TYPE,
127287  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_188_WIDTH },
127288  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_189_CHECKER_TYPE,
127289  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_189_WIDTH },
127290  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_190_CHECKER_TYPE,
127291  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_190_WIDTH },
127292  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_191_CHECKER_TYPE,
127293  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_191_WIDTH },
127294  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_192_CHECKER_TYPE,
127295  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_192_WIDTH },
127296  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_193_CHECKER_TYPE,
127297  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_193_WIDTH },
127298  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_194_CHECKER_TYPE,
127299  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_194_WIDTH },
127300  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_195_CHECKER_TYPE,
127301  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_195_WIDTH },
127302  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_196_CHECKER_TYPE,
127303  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_196_WIDTH },
127304  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_197_CHECKER_TYPE,
127305  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_197_WIDTH },
127306  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_198_CHECKER_TYPE,
127307  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_198_WIDTH },
127308  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_199_CHECKER_TYPE,
127309  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_199_WIDTH },
127310  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_200_CHECKER_TYPE,
127311  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_200_WIDTH },
127312  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_201_CHECKER_TYPE,
127313  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_201_WIDTH },
127314  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_202_CHECKER_TYPE,
127315  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_202_WIDTH },
127316  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_203_CHECKER_TYPE,
127317  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_203_WIDTH },
127318  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_204_CHECKER_TYPE,
127319  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_204_WIDTH },
127320  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_205_CHECKER_TYPE,
127321  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_205_WIDTH },
127322  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_206_CHECKER_TYPE,
127323  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_206_WIDTH },
127324  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_207_CHECKER_TYPE,
127325  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_207_WIDTH },
127326  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_208_CHECKER_TYPE,
127327  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_208_WIDTH },
127328  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_209_CHECKER_TYPE,
127329  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_209_WIDTH },
127330  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_210_CHECKER_TYPE,
127331  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_210_WIDTH },
127332  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_211_CHECKER_TYPE,
127333  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_211_WIDTH },
127334  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_212_CHECKER_TYPE,
127335  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_212_WIDTH },
127336  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_213_CHECKER_TYPE,
127337  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_213_WIDTH },
127338  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_214_CHECKER_TYPE,
127339  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_214_WIDTH },
127340  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_215_CHECKER_TYPE,
127341  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_215_WIDTH },
127342  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_216_CHECKER_TYPE,
127343  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_216_WIDTH },
127344  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_217_CHECKER_TYPE,
127345  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_217_WIDTH },
127346  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_218_CHECKER_TYPE,
127347  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_218_WIDTH },
127348  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_219_CHECKER_TYPE,
127349  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_219_WIDTH },
127350  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_220_CHECKER_TYPE,
127351  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_220_WIDTH },
127352  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_221_CHECKER_TYPE,
127353  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_221_WIDTH },
127354  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_222_CHECKER_TYPE,
127355  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_222_WIDTH },
127356  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_223_CHECKER_TYPE,
127357  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_223_WIDTH },
127358  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_224_CHECKER_TYPE,
127359  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_224_WIDTH },
127360  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_225_CHECKER_TYPE,
127361  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_225_WIDTH },
127362  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_226_CHECKER_TYPE,
127363  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_226_WIDTH },
127364  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_227_CHECKER_TYPE,
127365  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_227_WIDTH },
127366  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_228_CHECKER_TYPE,
127367  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_228_WIDTH },
127368  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_229_CHECKER_TYPE,
127369  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_229_WIDTH },
127370  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_230_CHECKER_TYPE,
127371  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_230_WIDTH },
127372  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_231_CHECKER_TYPE,
127373  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_231_WIDTH },
127374  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_232_CHECKER_TYPE,
127375  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_232_WIDTH },
127376  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_233_CHECKER_TYPE,
127377  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_233_WIDTH },
127378  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_234_CHECKER_TYPE,
127379  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_234_WIDTH },
127380  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_235_CHECKER_TYPE,
127381  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_235_WIDTH },
127382  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_236_CHECKER_TYPE,
127383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_236_WIDTH },
127384  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_237_CHECKER_TYPE,
127385  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_237_WIDTH },
127386  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_238_CHECKER_TYPE,
127387  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_238_WIDTH },
127388  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_239_CHECKER_TYPE,
127389  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_239_WIDTH },
127390  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_240_CHECKER_TYPE,
127391  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_240_WIDTH },
127392  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_241_CHECKER_TYPE,
127393  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_241_WIDTH },
127394  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_242_CHECKER_TYPE,
127395  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_242_WIDTH },
127396  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_243_CHECKER_TYPE,
127397  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_243_WIDTH },
127398  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_244_CHECKER_TYPE,
127399  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_244_WIDTH },
127400  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_245_CHECKER_TYPE,
127401  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_245_WIDTH },
127402  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_246_CHECKER_TYPE,
127403  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_246_WIDTH },
127404  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_247_CHECKER_TYPE,
127405  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_247_WIDTH },
127406  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_248_CHECKER_TYPE,
127407  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_248_WIDTH },
127408  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_249_CHECKER_TYPE,
127409  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_249_WIDTH },
127410  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_250_CHECKER_TYPE,
127411  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_250_WIDTH },
127412  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_251_CHECKER_TYPE,
127413  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_251_WIDTH },
127414  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_252_CHECKER_TYPE,
127415  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_252_WIDTH },
127416  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_253_CHECKER_TYPE,
127417  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_253_WIDTH },
127418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_254_CHECKER_TYPE,
127419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_254_WIDTH },
127420  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_255_CHECKER_TYPE,
127421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_GROUP_255_WIDTH },
127422 };
127423 
127429 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_MAX_NUM_CHECKERS] =
127430 {
127431  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_0_CHECKER_TYPE,
127432  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_0_WIDTH },
127433  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_1_CHECKER_TYPE,
127434  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_1_WIDTH },
127435  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_2_CHECKER_TYPE,
127436  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_2_WIDTH },
127437  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_3_CHECKER_TYPE,
127438  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_3_WIDTH },
127439  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_4_CHECKER_TYPE,
127440  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_4_WIDTH },
127441  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_5_CHECKER_TYPE,
127442  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_5_WIDTH },
127443  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_6_CHECKER_TYPE,
127444  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_6_WIDTH },
127445  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_7_CHECKER_TYPE,
127446  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_7_WIDTH },
127447  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_8_CHECKER_TYPE,
127448  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_8_WIDTH },
127449  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_9_CHECKER_TYPE,
127450  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_9_WIDTH },
127451  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_10_CHECKER_TYPE,
127452  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_10_WIDTH },
127453  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_11_CHECKER_TYPE,
127454  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_11_WIDTH },
127455  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_12_CHECKER_TYPE,
127456  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_12_WIDTH },
127457  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_13_CHECKER_TYPE,
127458  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_13_WIDTH },
127459  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_14_CHECKER_TYPE,
127460  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_14_WIDTH },
127461  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_15_CHECKER_TYPE,
127462  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_15_WIDTH },
127463  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_16_CHECKER_TYPE,
127464  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_16_WIDTH },
127465  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_17_CHECKER_TYPE,
127466  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_17_WIDTH },
127467  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_18_CHECKER_TYPE,
127468  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_18_WIDTH },
127469  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_19_CHECKER_TYPE,
127470  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_19_WIDTH },
127471  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_20_CHECKER_TYPE,
127472  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_20_WIDTH },
127473  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_21_CHECKER_TYPE,
127474  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_21_WIDTH },
127475  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_22_CHECKER_TYPE,
127476  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_22_WIDTH },
127477  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_23_CHECKER_TYPE,
127478  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_23_WIDTH },
127479  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_24_CHECKER_TYPE,
127480  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_24_WIDTH },
127481  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_25_CHECKER_TYPE,
127482  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_25_WIDTH },
127483  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_26_CHECKER_TYPE,
127484  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_26_WIDTH },
127485  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_27_CHECKER_TYPE,
127486  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_27_WIDTH },
127487  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_28_CHECKER_TYPE,
127488  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_28_WIDTH },
127489  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_29_CHECKER_TYPE,
127490  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_29_WIDTH },
127491  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_30_CHECKER_TYPE,
127492  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_30_WIDTH },
127493  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_31_CHECKER_TYPE,
127494  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_31_WIDTH },
127495  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_32_CHECKER_TYPE,
127496  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_32_WIDTH },
127497  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_33_CHECKER_TYPE,
127498  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_33_WIDTH },
127499  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_34_CHECKER_TYPE,
127500  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_34_WIDTH },
127501  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_35_CHECKER_TYPE,
127502  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_35_WIDTH },
127503  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_36_CHECKER_TYPE,
127504  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_36_WIDTH },
127505  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_37_CHECKER_TYPE,
127506  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_37_WIDTH },
127507  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_38_CHECKER_TYPE,
127508  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_38_WIDTH },
127509  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_39_CHECKER_TYPE,
127510  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_39_WIDTH },
127511  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_40_CHECKER_TYPE,
127512  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_40_WIDTH },
127513  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_41_CHECKER_TYPE,
127514  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_41_WIDTH },
127515  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_42_CHECKER_TYPE,
127516  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_42_WIDTH },
127517  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_43_CHECKER_TYPE,
127518  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_43_WIDTH },
127519  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_44_CHECKER_TYPE,
127520  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_44_WIDTH },
127521  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_45_CHECKER_TYPE,
127522  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_45_WIDTH },
127523  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_46_CHECKER_TYPE,
127524  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_46_WIDTH },
127525  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_47_CHECKER_TYPE,
127526  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_47_WIDTH },
127527  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_48_CHECKER_TYPE,
127528  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_48_WIDTH },
127529  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_49_CHECKER_TYPE,
127530  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_49_WIDTH },
127531  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_50_CHECKER_TYPE,
127532  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_50_WIDTH },
127533  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_51_CHECKER_TYPE,
127534  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_51_WIDTH },
127535  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_52_CHECKER_TYPE,
127536  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_52_WIDTH },
127537  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_53_CHECKER_TYPE,
127538  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_53_WIDTH },
127539  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_54_CHECKER_TYPE,
127540  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_54_WIDTH },
127541  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_55_CHECKER_TYPE,
127542  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_55_WIDTH },
127543  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_56_CHECKER_TYPE,
127544  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_56_WIDTH },
127545  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_57_CHECKER_TYPE,
127546  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_57_WIDTH },
127547  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_58_CHECKER_TYPE,
127548  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_58_WIDTH },
127549  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_59_CHECKER_TYPE,
127550  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_59_WIDTH },
127551  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_60_CHECKER_TYPE,
127552  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_60_WIDTH },
127553  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_61_CHECKER_TYPE,
127554  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_61_WIDTH },
127555  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_62_CHECKER_TYPE,
127556  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_62_WIDTH },
127557  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_63_CHECKER_TYPE,
127558  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_63_WIDTH },
127559  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_64_CHECKER_TYPE,
127560  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_64_WIDTH },
127561  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_65_CHECKER_TYPE,
127562  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_65_WIDTH },
127563  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_66_CHECKER_TYPE,
127564  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_66_WIDTH },
127565  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_67_CHECKER_TYPE,
127566  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_67_WIDTH },
127567  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_68_CHECKER_TYPE,
127568  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_68_WIDTH },
127569  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_69_CHECKER_TYPE,
127570  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_69_WIDTH },
127571  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_70_CHECKER_TYPE,
127572  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_70_WIDTH },
127573  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_71_CHECKER_TYPE,
127574  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_71_WIDTH },
127575  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_72_CHECKER_TYPE,
127576  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_72_WIDTH },
127577  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_73_CHECKER_TYPE,
127578  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_73_WIDTH },
127579  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_74_CHECKER_TYPE,
127580  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_74_WIDTH },
127581  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_75_CHECKER_TYPE,
127582  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_75_WIDTH },
127583  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_76_CHECKER_TYPE,
127584  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_76_WIDTH },
127585  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_77_CHECKER_TYPE,
127586  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_77_WIDTH },
127587  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_78_CHECKER_TYPE,
127588  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_78_WIDTH },
127589  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_79_CHECKER_TYPE,
127590  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_79_WIDTH },
127591  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_80_CHECKER_TYPE,
127592  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_80_WIDTH },
127593  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_81_CHECKER_TYPE,
127594  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_81_WIDTH },
127595  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_82_CHECKER_TYPE,
127596  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_82_WIDTH },
127597  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_83_CHECKER_TYPE,
127598  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_83_WIDTH },
127599  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_84_CHECKER_TYPE,
127600  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_84_WIDTH },
127601  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_85_CHECKER_TYPE,
127602  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_85_WIDTH },
127603  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_86_CHECKER_TYPE,
127604  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_86_WIDTH },
127605  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_87_CHECKER_TYPE,
127606  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_87_WIDTH },
127607  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_88_CHECKER_TYPE,
127608  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_88_WIDTH },
127609  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_89_CHECKER_TYPE,
127610  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_89_WIDTH },
127611  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_90_CHECKER_TYPE,
127612  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_90_WIDTH },
127613  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_91_CHECKER_TYPE,
127614  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_91_WIDTH },
127615  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_92_CHECKER_TYPE,
127616  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_92_WIDTH },
127617  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_93_CHECKER_TYPE,
127618  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_93_WIDTH },
127619  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_94_CHECKER_TYPE,
127620  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_94_WIDTH },
127621  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_95_CHECKER_TYPE,
127622  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_95_WIDTH },
127623  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_96_CHECKER_TYPE,
127624  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_96_WIDTH },
127625  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_97_CHECKER_TYPE,
127626  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_97_WIDTH },
127627  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_98_CHECKER_TYPE,
127628  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_98_WIDTH },
127629  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_99_CHECKER_TYPE,
127630  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_99_WIDTH },
127631  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_100_CHECKER_TYPE,
127632  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_100_WIDTH },
127633  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_101_CHECKER_TYPE,
127634  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_101_WIDTH },
127635  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_102_CHECKER_TYPE,
127636  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_102_WIDTH },
127637  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_103_CHECKER_TYPE,
127638  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_103_WIDTH },
127639  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_104_CHECKER_TYPE,
127640  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_104_WIDTH },
127641  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_105_CHECKER_TYPE,
127642  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_105_WIDTH },
127643  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_106_CHECKER_TYPE,
127644  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_106_WIDTH },
127645  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_107_CHECKER_TYPE,
127646  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_107_WIDTH },
127647  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_108_CHECKER_TYPE,
127648  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_108_WIDTH },
127649  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_109_CHECKER_TYPE,
127650  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_109_WIDTH },
127651  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_110_CHECKER_TYPE,
127652  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_110_WIDTH },
127653  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_111_CHECKER_TYPE,
127654  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_111_WIDTH },
127655  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_112_CHECKER_TYPE,
127656  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_112_WIDTH },
127657  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_113_CHECKER_TYPE,
127658  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_113_WIDTH },
127659  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_114_CHECKER_TYPE,
127660  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_114_WIDTH },
127661  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_115_CHECKER_TYPE,
127662  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_115_WIDTH },
127663  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_116_CHECKER_TYPE,
127664  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_116_WIDTH },
127665  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_117_CHECKER_TYPE,
127666  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_117_WIDTH },
127667  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_118_CHECKER_TYPE,
127668  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_118_WIDTH },
127669  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_119_CHECKER_TYPE,
127670  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_119_WIDTH },
127671  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_120_CHECKER_TYPE,
127672  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_120_WIDTH },
127673  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_121_CHECKER_TYPE,
127674  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_121_WIDTH },
127675  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_122_CHECKER_TYPE,
127676  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_122_WIDTH },
127677  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_123_CHECKER_TYPE,
127678  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_123_WIDTH },
127679  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_124_CHECKER_TYPE,
127680  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_124_WIDTH },
127681  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_125_CHECKER_TYPE,
127682  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_125_WIDTH },
127683  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_126_CHECKER_TYPE,
127684  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_126_WIDTH },
127685  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_127_CHECKER_TYPE,
127686  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_127_WIDTH },
127687  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_128_CHECKER_TYPE,
127688  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_128_WIDTH },
127689  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_129_CHECKER_TYPE,
127690  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_129_WIDTH },
127691  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_130_CHECKER_TYPE,
127692  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_130_WIDTH },
127693  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_131_CHECKER_TYPE,
127694  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_131_WIDTH },
127695  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_132_CHECKER_TYPE,
127696  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_132_WIDTH },
127697  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_133_CHECKER_TYPE,
127698  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_133_WIDTH },
127699  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_134_CHECKER_TYPE,
127700  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_134_WIDTH },
127701  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_135_CHECKER_TYPE,
127702  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_135_WIDTH },
127703  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_136_CHECKER_TYPE,
127704  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_136_WIDTH },
127705  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_137_CHECKER_TYPE,
127706  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_137_WIDTH },
127707  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_138_CHECKER_TYPE,
127708  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_138_WIDTH },
127709  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_139_CHECKER_TYPE,
127710  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_139_WIDTH },
127711  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_140_CHECKER_TYPE,
127712  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_140_WIDTH },
127713  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_141_CHECKER_TYPE,
127714  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_141_WIDTH },
127715  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_142_CHECKER_TYPE,
127716  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_142_WIDTH },
127717  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_143_CHECKER_TYPE,
127718  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_143_WIDTH },
127719  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_144_CHECKER_TYPE,
127720  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_144_WIDTH },
127721  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_145_CHECKER_TYPE,
127722  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_145_WIDTH },
127723  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_146_CHECKER_TYPE,
127724  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_146_WIDTH },
127725  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_147_CHECKER_TYPE,
127726  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_147_WIDTH },
127727  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_148_CHECKER_TYPE,
127728  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_148_WIDTH },
127729  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_149_CHECKER_TYPE,
127730  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_149_WIDTH },
127731  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_150_CHECKER_TYPE,
127732  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_150_WIDTH },
127733  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_151_CHECKER_TYPE,
127734  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_151_WIDTH },
127735  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_152_CHECKER_TYPE,
127736  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_152_WIDTH },
127737  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_153_CHECKER_TYPE,
127738  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_153_WIDTH },
127739  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_154_CHECKER_TYPE,
127740  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_154_WIDTH },
127741  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_155_CHECKER_TYPE,
127742  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_155_WIDTH },
127743  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_156_CHECKER_TYPE,
127744  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_156_WIDTH },
127745  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_157_CHECKER_TYPE,
127746  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_157_WIDTH },
127747  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_158_CHECKER_TYPE,
127748  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_158_WIDTH },
127749  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_159_CHECKER_TYPE,
127750  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_159_WIDTH },
127751  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_160_CHECKER_TYPE,
127752  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_160_WIDTH },
127753  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_161_CHECKER_TYPE,
127754  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_161_WIDTH },
127755  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_162_CHECKER_TYPE,
127756  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_162_WIDTH },
127757  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_163_CHECKER_TYPE,
127758  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_163_WIDTH },
127759  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_164_CHECKER_TYPE,
127760  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_164_WIDTH },
127761  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_165_CHECKER_TYPE,
127762  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_165_WIDTH },
127763  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_166_CHECKER_TYPE,
127764  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_166_WIDTH },
127765  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_167_CHECKER_TYPE,
127766  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_167_WIDTH },
127767  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_168_CHECKER_TYPE,
127768  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_168_WIDTH },
127769  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_169_CHECKER_TYPE,
127770  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_169_WIDTH },
127771  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_170_CHECKER_TYPE,
127772  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_170_WIDTH },
127773  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_171_CHECKER_TYPE,
127774  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_171_WIDTH },
127775  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_172_CHECKER_TYPE,
127776  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_172_WIDTH },
127777  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_173_CHECKER_TYPE,
127778  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_173_WIDTH },
127779  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_174_CHECKER_TYPE,
127780  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_174_WIDTH },
127781  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_175_CHECKER_TYPE,
127782  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_175_WIDTH },
127783  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_176_CHECKER_TYPE,
127784  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_176_WIDTH },
127785  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_177_CHECKER_TYPE,
127786  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_177_WIDTH },
127787  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_178_CHECKER_TYPE,
127788  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_178_WIDTH },
127789  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_179_CHECKER_TYPE,
127790  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_179_WIDTH },
127791  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_180_CHECKER_TYPE,
127792  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_180_WIDTH },
127793  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_181_CHECKER_TYPE,
127794  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_181_WIDTH },
127795  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_182_CHECKER_TYPE,
127796  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_182_WIDTH },
127797  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_183_CHECKER_TYPE,
127798  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_183_WIDTH },
127799  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_184_CHECKER_TYPE,
127800  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_184_WIDTH },
127801  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_185_CHECKER_TYPE,
127802  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_185_WIDTH },
127803  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_186_CHECKER_TYPE,
127804  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_186_WIDTH },
127805  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_187_CHECKER_TYPE,
127806  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_187_WIDTH },
127807  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_188_CHECKER_TYPE,
127808  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_188_WIDTH },
127809  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_189_CHECKER_TYPE,
127810  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_189_WIDTH },
127811  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_190_CHECKER_TYPE,
127812  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_190_WIDTH },
127813  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_191_CHECKER_TYPE,
127814  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_GROUP_191_WIDTH },
127815 };
127816 
127822 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS] =
127823 {
127824  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_0_CHECKER_TYPE,
127825  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_0_WIDTH },
127826  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_1_CHECKER_TYPE,
127827  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_1_WIDTH },
127828  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_2_CHECKER_TYPE,
127829  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_2_WIDTH },
127830  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_3_CHECKER_TYPE,
127831  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_3_WIDTH },
127832  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_4_CHECKER_TYPE,
127833  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_4_WIDTH },
127834  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_5_CHECKER_TYPE,
127835  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_5_WIDTH },
127836  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_6_CHECKER_TYPE,
127837  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_6_WIDTH },
127838  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_7_CHECKER_TYPE,
127839  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_7_WIDTH },
127840  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_8_CHECKER_TYPE,
127841  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_8_WIDTH },
127842  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_9_CHECKER_TYPE,
127843  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_9_WIDTH },
127844  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_10_CHECKER_TYPE,
127845  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_10_WIDTH },
127846  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_11_CHECKER_TYPE,
127847  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_11_WIDTH },
127848  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_12_CHECKER_TYPE,
127849  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_12_WIDTH },
127850  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_13_CHECKER_TYPE,
127851  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_13_WIDTH },
127852  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_14_CHECKER_TYPE,
127853  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_14_WIDTH },
127854  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_15_CHECKER_TYPE,
127855  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_15_WIDTH },
127856  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_16_CHECKER_TYPE,
127857  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_16_WIDTH },
127858  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_17_CHECKER_TYPE,
127859  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_17_WIDTH },
127860  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_18_CHECKER_TYPE,
127861  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_18_WIDTH },
127862  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_19_CHECKER_TYPE,
127863  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_19_WIDTH },
127864  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_20_CHECKER_TYPE,
127865  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_20_WIDTH },
127866  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_21_CHECKER_TYPE,
127867  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_21_WIDTH },
127868  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_22_CHECKER_TYPE,
127869  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_GROUP_22_WIDTH },
127870 };
127871 
127877 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS] =
127878 {
127879  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
127880  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_0_WIDTH },
127881  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
127882  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_1_WIDTH },
127883  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
127884  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_2_WIDTH },
127885  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
127886  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_3_WIDTH },
127887  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
127888  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_4_WIDTH },
127889  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
127890  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_5_WIDTH },
127891  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
127892  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_6_WIDTH },
127893  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
127894  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_7_WIDTH },
127895  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
127896  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_8_WIDTH },
127897  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
127898  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_9_WIDTH },
127899  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
127900  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_10_WIDTH },
127901  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
127902  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_11_WIDTH },
127903  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
127904  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_12_WIDTH },
127905  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
127906  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_13_WIDTH },
127907  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
127908  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_14_WIDTH },
127909  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
127910  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_15_WIDTH },
127911  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
127912  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_16_WIDTH },
127913  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
127914  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_17_WIDTH },
127915  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
127916  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_18_WIDTH },
127917  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
127918  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_19_WIDTH },
127919  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
127920  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_20_WIDTH },
127921  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
127922  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_21_WIDTH },
127923  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
127924  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_22_WIDTH },
127925  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
127926  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_23_WIDTH },
127927  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
127928  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_24_WIDTH },
127929  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
127930  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_25_WIDTH },
127931  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
127932  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_GROUP_26_WIDTH },
127933 };
127934 
127940 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_MAX_NUM_CHECKERS] =
127941 {
127942  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
127943  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_0_WIDTH },
127944  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
127945  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_1_WIDTH },
127946  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
127947  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_2_WIDTH },
127948  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
127949  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_3_WIDTH },
127950  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
127951  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_4_WIDTH },
127952  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
127953  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_5_WIDTH },
127954  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
127955  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_6_WIDTH },
127956  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
127957  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_7_WIDTH },
127958  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
127959  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_8_WIDTH },
127960  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
127961  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_9_WIDTH },
127962  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
127963  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_10_WIDTH },
127964  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_11_CHECKER_TYPE,
127965  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_11_WIDTH },
127966  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_12_CHECKER_TYPE,
127967  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_12_WIDTH },
127968  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_13_CHECKER_TYPE,
127969  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_13_WIDTH },
127970  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_14_CHECKER_TYPE,
127971  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_14_WIDTH },
127972  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_15_CHECKER_TYPE,
127973  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_GROUP_15_WIDTH },
127974 };
127975 
127981 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_MAX_NUM_CHECKERS] =
127982 {
127983  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_0_CHECKER_TYPE,
127984  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_0_WIDTH },
127985  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_1_CHECKER_TYPE,
127986  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_1_WIDTH },
127987  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_2_CHECKER_TYPE,
127988  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_2_WIDTH },
127989  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_3_CHECKER_TYPE,
127990  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_3_WIDTH },
127991  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_4_CHECKER_TYPE,
127992  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_4_WIDTH },
127993  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_5_CHECKER_TYPE,
127994  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_5_WIDTH },
127995  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_6_CHECKER_TYPE,
127996  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_6_WIDTH },
127997  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_7_CHECKER_TYPE,
127998  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_7_WIDTH },
127999  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_8_CHECKER_TYPE,
128000  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_8_WIDTH },
128001  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_9_CHECKER_TYPE,
128002  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_9_WIDTH },
128003  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_10_CHECKER_TYPE,
128004  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_10_WIDTH },
128005  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_11_CHECKER_TYPE,
128006  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_11_WIDTH },
128007  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_12_CHECKER_TYPE,
128008  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_12_WIDTH },
128009  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_13_CHECKER_TYPE,
128010  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_GROUP_13_WIDTH },
128011 };
128012 
128018 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_MAX_NUM_CHECKERS] =
128019 {
128020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_0_CHECKER_TYPE,
128021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_0_WIDTH },
128022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_1_CHECKER_TYPE,
128023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_1_WIDTH },
128024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_2_CHECKER_TYPE,
128025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_2_WIDTH },
128026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_3_CHECKER_TYPE,
128027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_3_WIDTH },
128028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_4_CHECKER_TYPE,
128029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_4_WIDTH },
128030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_5_CHECKER_TYPE,
128031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_5_WIDTH },
128032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_6_CHECKER_TYPE,
128033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_6_WIDTH },
128034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_7_CHECKER_TYPE,
128035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_7_WIDTH },
128036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_8_CHECKER_TYPE,
128037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_8_WIDTH },
128038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_9_CHECKER_TYPE,
128039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_9_WIDTH },
128040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_10_CHECKER_TYPE,
128041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_10_WIDTH },
128042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_11_CHECKER_TYPE,
128043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_11_WIDTH },
128044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_12_CHECKER_TYPE,
128045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_12_WIDTH },
128046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_13_CHECKER_TYPE,
128047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_13_WIDTH },
128048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_14_CHECKER_TYPE,
128049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_14_WIDTH },
128050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_15_CHECKER_TYPE,
128051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_15_WIDTH },
128052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_16_CHECKER_TYPE,
128053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_16_WIDTH },
128054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_17_CHECKER_TYPE,
128055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_17_WIDTH },
128056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_18_CHECKER_TYPE,
128057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_18_WIDTH },
128058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_19_CHECKER_TYPE,
128059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_19_WIDTH },
128060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_20_CHECKER_TYPE,
128061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_20_WIDTH },
128062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_21_CHECKER_TYPE,
128063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_21_WIDTH },
128064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_22_CHECKER_TYPE,
128065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_22_WIDTH },
128066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_23_CHECKER_TYPE,
128067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_23_WIDTH },
128068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_24_CHECKER_TYPE,
128069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_24_WIDTH },
128070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_25_CHECKER_TYPE,
128071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_25_WIDTH },
128072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_26_CHECKER_TYPE,
128073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_26_WIDTH },
128074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_27_CHECKER_TYPE,
128075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_27_WIDTH },
128076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_28_CHECKER_TYPE,
128077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_28_WIDTH },
128078  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_29_CHECKER_TYPE,
128079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_29_WIDTH },
128080  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_30_CHECKER_TYPE,
128081  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_30_WIDTH },
128082  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_31_CHECKER_TYPE,
128083  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_31_WIDTH },
128084  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_32_CHECKER_TYPE,
128085  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_32_WIDTH },
128086  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_33_CHECKER_TYPE,
128087  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_33_WIDTH },
128088  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_34_CHECKER_TYPE,
128089  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_34_WIDTH },
128090  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_35_CHECKER_TYPE,
128091  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_35_WIDTH },
128092  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_36_CHECKER_TYPE,
128093  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_36_WIDTH },
128094  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_37_CHECKER_TYPE,
128095  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_37_WIDTH },
128096  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_38_CHECKER_TYPE,
128097  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_38_WIDTH },
128098  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_39_CHECKER_TYPE,
128099  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_39_WIDTH },
128100  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_40_CHECKER_TYPE,
128101  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_40_WIDTH },
128102  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_41_CHECKER_TYPE,
128103  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_41_WIDTH },
128104  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_42_CHECKER_TYPE,
128105  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_42_WIDTH },
128106  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_43_CHECKER_TYPE,
128107  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_43_WIDTH },
128108  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_44_CHECKER_TYPE,
128109  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_44_WIDTH },
128110  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_45_CHECKER_TYPE,
128111  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_45_WIDTH },
128112  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_46_CHECKER_TYPE,
128113  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_46_WIDTH },
128114  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_47_CHECKER_TYPE,
128115  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_47_WIDTH },
128116  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_48_CHECKER_TYPE,
128117  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_48_WIDTH },
128118  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_49_CHECKER_TYPE,
128119  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_49_WIDTH },
128120  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_50_CHECKER_TYPE,
128121  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_50_WIDTH },
128122  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_51_CHECKER_TYPE,
128123  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_51_WIDTH },
128124  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_52_CHECKER_TYPE,
128125  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_GROUP_52_WIDTH },
128126 };
128127 
128133 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS] =
128134 {
128135  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
128136  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_0_WIDTH },
128137  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
128138  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_1_WIDTH },
128139  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
128140  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_2_WIDTH },
128141  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
128142  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_3_WIDTH },
128143  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
128144  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_4_WIDTH },
128145  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
128146  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_5_WIDTH },
128147  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
128148  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_6_WIDTH },
128149  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
128150  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_7_WIDTH },
128151  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
128152  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_8_WIDTH },
128153  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
128154  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_9_WIDTH },
128155  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
128156  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_10_WIDTH },
128157  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
128158  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_11_WIDTH },
128159  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
128160  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_12_WIDTH },
128161  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
128162  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_13_WIDTH },
128163  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
128164  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_14_WIDTH },
128165  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
128166  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_15_WIDTH },
128167  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
128168  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_16_WIDTH },
128169  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
128170  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_17_WIDTH },
128171  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
128172  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_18_WIDTH },
128173  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
128174  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_19_WIDTH },
128175  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
128176  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_20_WIDTH },
128177  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
128178  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_21_WIDTH },
128179  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
128180  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_22_WIDTH },
128181  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
128182  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_23_WIDTH },
128183  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
128184  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_24_WIDTH },
128185  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
128186  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_25_WIDTH },
128187  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
128188  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_26_WIDTH },
128189  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_27_CHECKER_TYPE,
128190  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_27_WIDTH },
128191  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_28_CHECKER_TYPE,
128192  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_28_WIDTH },
128193  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_29_CHECKER_TYPE,
128194  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_29_WIDTH },
128195  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_30_CHECKER_TYPE,
128196  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_30_WIDTH },
128197  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_31_CHECKER_TYPE,
128198  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_31_WIDTH },
128199  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_32_CHECKER_TYPE,
128200  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_32_WIDTH },
128201  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_33_CHECKER_TYPE,
128202  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_33_WIDTH },
128203  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_34_CHECKER_TYPE,
128204  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_34_WIDTH },
128205  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_35_CHECKER_TYPE,
128206  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_35_WIDTH },
128207  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_36_CHECKER_TYPE,
128208  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_36_WIDTH },
128209  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_37_CHECKER_TYPE,
128210  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_37_WIDTH },
128211  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_38_CHECKER_TYPE,
128212  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_38_WIDTH },
128213  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_39_CHECKER_TYPE,
128214  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_39_WIDTH },
128215  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_40_CHECKER_TYPE,
128216  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_40_WIDTH },
128217  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_41_CHECKER_TYPE,
128218  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_41_WIDTH },
128219  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_42_CHECKER_TYPE,
128220  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_42_WIDTH },
128221  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_43_CHECKER_TYPE,
128222  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_43_WIDTH },
128223  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_44_CHECKER_TYPE,
128224  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_44_WIDTH },
128225  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_45_CHECKER_TYPE,
128226  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_45_WIDTH },
128227  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_46_CHECKER_TYPE,
128228  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_46_WIDTH },
128229  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_47_CHECKER_TYPE,
128230  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_47_WIDTH },
128231 };
128232 
128238 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_MAX_NUM_CHECKERS] =
128239 {
128240  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_0_CHECKER_TYPE,
128241  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_0_WIDTH },
128242  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_1_CHECKER_TYPE,
128243  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_1_WIDTH },
128244  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_2_CHECKER_TYPE,
128245  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_2_WIDTH },
128246  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_3_CHECKER_TYPE,
128247  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_3_WIDTH },
128248  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_4_CHECKER_TYPE,
128249  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_4_WIDTH },
128250  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_5_CHECKER_TYPE,
128251  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_5_WIDTH },
128252  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_6_CHECKER_TYPE,
128253  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_6_WIDTH },
128254  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_7_CHECKER_TYPE,
128255  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_7_WIDTH },
128256  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_8_CHECKER_TYPE,
128257  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_8_WIDTH },
128258  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_9_CHECKER_TYPE,
128259  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_9_WIDTH },
128260  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_10_CHECKER_TYPE,
128261  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_10_WIDTH },
128262  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_11_CHECKER_TYPE,
128263  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_11_WIDTH },
128264  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_12_CHECKER_TYPE,
128265  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_12_WIDTH },
128266  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_13_CHECKER_TYPE,
128267  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_13_WIDTH },
128268  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_14_CHECKER_TYPE,
128269  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_14_WIDTH },
128270  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_15_CHECKER_TYPE,
128271  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_15_WIDTH },
128272  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_16_CHECKER_TYPE,
128273  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_16_WIDTH },
128274  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_17_CHECKER_TYPE,
128275  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_17_WIDTH },
128276  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_18_CHECKER_TYPE,
128277  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_18_WIDTH },
128278  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_19_CHECKER_TYPE,
128279  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_19_WIDTH },
128280  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_20_CHECKER_TYPE,
128281  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_20_WIDTH },
128282  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_21_CHECKER_TYPE,
128283  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_21_WIDTH },
128284  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_22_CHECKER_TYPE,
128285  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_22_WIDTH },
128286  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_23_CHECKER_TYPE,
128287  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_23_WIDTH },
128288  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_24_CHECKER_TYPE,
128289  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_24_WIDTH },
128290  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_25_CHECKER_TYPE,
128291  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_25_WIDTH },
128292  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_26_CHECKER_TYPE,
128293  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_26_WIDTH },
128294  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_27_CHECKER_TYPE,
128295  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_27_WIDTH },
128296  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_28_CHECKER_TYPE,
128297  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_28_WIDTH },
128298  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_29_CHECKER_TYPE,
128299  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_29_WIDTH },
128300  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_30_CHECKER_TYPE,
128301  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_30_WIDTH },
128302  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_31_CHECKER_TYPE,
128303  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_31_WIDTH },
128304  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_32_CHECKER_TYPE,
128305  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_32_WIDTH },
128306  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_33_CHECKER_TYPE,
128307  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_33_WIDTH },
128308  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_34_CHECKER_TYPE,
128309  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_34_WIDTH },
128310  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_35_CHECKER_TYPE,
128311  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_35_WIDTH },
128312  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_36_CHECKER_TYPE,
128313  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_36_WIDTH },
128314  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_37_CHECKER_TYPE,
128315  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_37_WIDTH },
128316  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_38_CHECKER_TYPE,
128317  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_38_WIDTH },
128318  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_39_CHECKER_TYPE,
128319  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_39_WIDTH },
128320  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_40_CHECKER_TYPE,
128321  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_40_WIDTH },
128322  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_41_CHECKER_TYPE,
128323  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_41_WIDTH },
128324  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_42_CHECKER_TYPE,
128325  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_42_WIDTH },
128326  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_43_CHECKER_TYPE,
128327  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_43_WIDTH },
128328  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_44_CHECKER_TYPE,
128329  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_44_WIDTH },
128330  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_45_CHECKER_TYPE,
128331  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_45_WIDTH },
128332  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_46_CHECKER_TYPE,
128333  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_46_WIDTH },
128334  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_47_CHECKER_TYPE,
128335  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_47_WIDTH },
128336  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_48_CHECKER_TYPE,
128337  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_48_WIDTH },
128338  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_49_CHECKER_TYPE,
128339  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_49_WIDTH },
128340  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_50_CHECKER_TYPE,
128341  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_50_WIDTH },
128342  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_51_CHECKER_TYPE,
128343  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_51_WIDTH },
128344  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_52_CHECKER_TYPE,
128345  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_52_WIDTH },
128346  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_53_CHECKER_TYPE,
128347  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_53_WIDTH },
128348  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_54_CHECKER_TYPE,
128349  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_54_WIDTH },
128350  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_55_CHECKER_TYPE,
128351  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_55_WIDTH },
128352  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_56_CHECKER_TYPE,
128353  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_56_WIDTH },
128354  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_57_CHECKER_TYPE,
128355  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_57_WIDTH },
128356  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_58_CHECKER_TYPE,
128357  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_58_WIDTH },
128358  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_59_CHECKER_TYPE,
128359  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_59_WIDTH },
128360  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_60_CHECKER_TYPE,
128361  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_60_WIDTH },
128362  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_61_CHECKER_TYPE,
128363  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_61_WIDTH },
128364  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_62_CHECKER_TYPE,
128365  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_62_WIDTH },
128366  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_63_CHECKER_TYPE,
128367  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_63_WIDTH },
128368  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_64_CHECKER_TYPE,
128369  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_64_WIDTH },
128370  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_65_CHECKER_TYPE,
128371  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_65_WIDTH },
128372  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_66_CHECKER_TYPE,
128373  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_66_WIDTH },
128374  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_67_CHECKER_TYPE,
128375  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_67_WIDTH },
128376  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_68_CHECKER_TYPE,
128377  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_68_WIDTH },
128378  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_69_CHECKER_TYPE,
128379  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_69_WIDTH },
128380  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_70_CHECKER_TYPE,
128381  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_70_WIDTH },
128382  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_71_CHECKER_TYPE,
128383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_71_WIDTH },
128384  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_72_CHECKER_TYPE,
128385  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_72_WIDTH },
128386  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_73_CHECKER_TYPE,
128387  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_73_WIDTH },
128388  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_74_CHECKER_TYPE,
128389  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_74_WIDTH },
128390  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_75_CHECKER_TYPE,
128391  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_75_WIDTH },
128392  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_76_CHECKER_TYPE,
128393  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_76_WIDTH },
128394  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_77_CHECKER_TYPE,
128395  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_77_WIDTH },
128396  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_78_CHECKER_TYPE,
128397  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_78_WIDTH },
128398  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_79_CHECKER_TYPE,
128399  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_79_WIDTH },
128400  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_80_CHECKER_TYPE,
128401  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_80_WIDTH },
128402  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_81_CHECKER_TYPE,
128403  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_81_WIDTH },
128404  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_82_CHECKER_TYPE,
128405  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_82_WIDTH },
128406  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_83_CHECKER_TYPE,
128407  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_83_WIDTH },
128408  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_84_CHECKER_TYPE,
128409  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_84_WIDTH },
128410  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_85_CHECKER_TYPE,
128411  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_85_WIDTH },
128412  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_86_CHECKER_TYPE,
128413  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_86_WIDTH },
128414  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_87_CHECKER_TYPE,
128415  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_87_WIDTH },
128416  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_88_CHECKER_TYPE,
128417  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_88_WIDTH },
128418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_89_CHECKER_TYPE,
128419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_89_WIDTH },
128420  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_90_CHECKER_TYPE,
128421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_90_WIDTH },
128422  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_91_CHECKER_TYPE,
128423  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_91_WIDTH },
128424  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_92_CHECKER_TYPE,
128425  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_92_WIDTH },
128426  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_93_CHECKER_TYPE,
128427  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_93_WIDTH },
128428  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_94_CHECKER_TYPE,
128429  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_94_WIDTH },
128430  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_95_CHECKER_TYPE,
128431  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_95_WIDTH },
128432  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_96_CHECKER_TYPE,
128433  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_96_WIDTH },
128434  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_97_CHECKER_TYPE,
128435  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_97_WIDTH },
128436  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_98_CHECKER_TYPE,
128437  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_98_WIDTH },
128438  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_99_CHECKER_TYPE,
128439  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_99_WIDTH },
128440  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_100_CHECKER_TYPE,
128441  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_100_WIDTH },
128442  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_101_CHECKER_TYPE,
128443  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_101_WIDTH },
128444  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_102_CHECKER_TYPE,
128445  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_102_WIDTH },
128446  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_103_CHECKER_TYPE,
128447  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_103_WIDTH },
128448  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_104_CHECKER_TYPE,
128449  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_104_WIDTH },
128450  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_105_CHECKER_TYPE,
128451  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_105_WIDTH },
128452  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_106_CHECKER_TYPE,
128453  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_106_WIDTH },
128454  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_107_CHECKER_TYPE,
128455  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_107_WIDTH },
128456  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_108_CHECKER_TYPE,
128457  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_108_WIDTH },
128458  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_109_CHECKER_TYPE,
128459  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_109_WIDTH },
128460  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_110_CHECKER_TYPE,
128461  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_110_WIDTH },
128462  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_111_CHECKER_TYPE,
128463  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_111_WIDTH },
128464  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_112_CHECKER_TYPE,
128465  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_112_WIDTH },
128466  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_113_CHECKER_TYPE,
128467  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_113_WIDTH },
128468  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_114_CHECKER_TYPE,
128469  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_114_WIDTH },
128470  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_115_CHECKER_TYPE,
128471  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_115_WIDTH },
128472  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_116_CHECKER_TYPE,
128473  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_116_WIDTH },
128474  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_117_CHECKER_TYPE,
128475  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_117_WIDTH },
128476  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_118_CHECKER_TYPE,
128477  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_118_WIDTH },
128478  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_119_CHECKER_TYPE,
128479  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_119_WIDTH },
128480  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_120_CHECKER_TYPE,
128481  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_120_WIDTH },
128482  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_121_CHECKER_TYPE,
128483  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_121_WIDTH },
128484  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_122_CHECKER_TYPE,
128485  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_122_WIDTH },
128486  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_123_CHECKER_TYPE,
128487  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_123_WIDTH },
128488  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_124_CHECKER_TYPE,
128489  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_124_WIDTH },
128490  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_125_CHECKER_TYPE,
128491  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_125_WIDTH },
128492  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_126_CHECKER_TYPE,
128493  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_126_WIDTH },
128494  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_127_CHECKER_TYPE,
128495  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_127_WIDTH },
128496  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_128_CHECKER_TYPE,
128497  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_128_WIDTH },
128498  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_129_CHECKER_TYPE,
128499  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_129_WIDTH },
128500  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_130_CHECKER_TYPE,
128501  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_130_WIDTH },
128502  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_131_CHECKER_TYPE,
128503  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_131_WIDTH },
128504  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_132_CHECKER_TYPE,
128505  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_132_WIDTH },
128506  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_133_CHECKER_TYPE,
128507  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_133_WIDTH },
128508  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_134_CHECKER_TYPE,
128509  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_134_WIDTH },
128510  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_135_CHECKER_TYPE,
128511  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_135_WIDTH },
128512  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_136_CHECKER_TYPE,
128513  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_136_WIDTH },
128514  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_137_CHECKER_TYPE,
128515  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_137_WIDTH },
128516  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_138_CHECKER_TYPE,
128517  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_138_WIDTH },
128518  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_139_CHECKER_TYPE,
128519  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_139_WIDTH },
128520  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_140_CHECKER_TYPE,
128521  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_140_WIDTH },
128522  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_141_CHECKER_TYPE,
128523  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_141_WIDTH },
128524  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_142_CHECKER_TYPE,
128525  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_142_WIDTH },
128526  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_143_CHECKER_TYPE,
128527  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_143_WIDTH },
128528  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_144_CHECKER_TYPE,
128529  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_144_WIDTH },
128530  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_145_CHECKER_TYPE,
128531  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_145_WIDTH },
128532  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_146_CHECKER_TYPE,
128533  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_146_WIDTH },
128534  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_147_CHECKER_TYPE,
128535  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_147_WIDTH },
128536  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_148_CHECKER_TYPE,
128537  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_148_WIDTH },
128538  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_149_CHECKER_TYPE,
128539  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_149_WIDTH },
128540  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_150_CHECKER_TYPE,
128541  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_150_WIDTH },
128542  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_151_CHECKER_TYPE,
128543  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_151_WIDTH },
128544  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_152_CHECKER_TYPE,
128545  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_152_WIDTH },
128546  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_153_CHECKER_TYPE,
128547  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_153_WIDTH },
128548  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_154_CHECKER_TYPE,
128549  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_154_WIDTH },
128550  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_155_CHECKER_TYPE,
128551  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_155_WIDTH },
128552  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_156_CHECKER_TYPE,
128553  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_156_WIDTH },
128554  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_157_CHECKER_TYPE,
128555  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_157_WIDTH },
128556  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_158_CHECKER_TYPE,
128557  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_158_WIDTH },
128558  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_159_CHECKER_TYPE,
128559  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_159_WIDTH },
128560  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_160_CHECKER_TYPE,
128561  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_160_WIDTH },
128562  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_161_CHECKER_TYPE,
128563  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_161_WIDTH },
128564  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_162_CHECKER_TYPE,
128565  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_162_WIDTH },
128566  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_163_CHECKER_TYPE,
128567  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_163_WIDTH },
128568  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_164_CHECKER_TYPE,
128569  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_164_WIDTH },
128570  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_165_CHECKER_TYPE,
128571  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_165_WIDTH },
128572  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_166_CHECKER_TYPE,
128573  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_166_WIDTH },
128574  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_167_CHECKER_TYPE,
128575  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_167_WIDTH },
128576  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_168_CHECKER_TYPE,
128577  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_168_WIDTH },
128578  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_169_CHECKER_TYPE,
128579  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_169_WIDTH },
128580  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_170_CHECKER_TYPE,
128581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_170_WIDTH },
128582  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_171_CHECKER_TYPE,
128583  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_171_WIDTH },
128584  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_172_CHECKER_TYPE,
128585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_172_WIDTH },
128586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_173_CHECKER_TYPE,
128587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_173_WIDTH },
128588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_174_CHECKER_TYPE,
128589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_174_WIDTH },
128590  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_175_CHECKER_TYPE,
128591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_175_WIDTH },
128592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_176_CHECKER_TYPE,
128593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_176_WIDTH },
128594  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_177_CHECKER_TYPE,
128595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_177_WIDTH },
128596  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_178_CHECKER_TYPE,
128597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_178_WIDTH },
128598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_179_CHECKER_TYPE,
128599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_179_WIDTH },
128600  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_180_CHECKER_TYPE,
128601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_180_WIDTH },
128602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_181_CHECKER_TYPE,
128603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_181_WIDTH },
128604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_182_CHECKER_TYPE,
128605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_182_WIDTH },
128606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_183_CHECKER_TYPE,
128607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_183_WIDTH },
128608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_184_CHECKER_TYPE,
128609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_184_WIDTH },
128610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_185_CHECKER_TYPE,
128611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_185_WIDTH },
128612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_186_CHECKER_TYPE,
128613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_186_WIDTH },
128614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_187_CHECKER_TYPE,
128615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_187_WIDTH },
128616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_188_CHECKER_TYPE,
128617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_188_WIDTH },
128618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_189_CHECKER_TYPE,
128619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_189_WIDTH },
128620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_190_CHECKER_TYPE,
128621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_190_WIDTH },
128622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_191_CHECKER_TYPE,
128623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_191_WIDTH },
128624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_192_CHECKER_TYPE,
128625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_192_WIDTH },
128626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_193_CHECKER_TYPE,
128627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_193_WIDTH },
128628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_194_CHECKER_TYPE,
128629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_194_WIDTH },
128630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_195_CHECKER_TYPE,
128631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_195_WIDTH },
128632  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_196_CHECKER_TYPE,
128633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_196_WIDTH },
128634  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_197_CHECKER_TYPE,
128635  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_197_WIDTH },
128636  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_198_CHECKER_TYPE,
128637  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_198_WIDTH },
128638  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_199_CHECKER_TYPE,
128639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_199_WIDTH },
128640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_200_CHECKER_TYPE,
128641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_200_WIDTH },
128642  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_201_CHECKER_TYPE,
128643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_201_WIDTH },
128644  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_202_CHECKER_TYPE,
128645  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_202_WIDTH },
128646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_203_CHECKER_TYPE,
128647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_203_WIDTH },
128648  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_204_CHECKER_TYPE,
128649  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_204_WIDTH },
128650  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_205_CHECKER_TYPE,
128651  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_205_WIDTH },
128652  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_206_CHECKER_TYPE,
128653  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_206_WIDTH },
128654  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_207_CHECKER_TYPE,
128655  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_207_WIDTH },
128656  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_208_CHECKER_TYPE,
128657  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_208_WIDTH },
128658  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_209_CHECKER_TYPE,
128659  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_209_WIDTH },
128660  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_210_CHECKER_TYPE,
128661  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_210_WIDTH },
128662  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_211_CHECKER_TYPE,
128663  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_211_WIDTH },
128664  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_212_CHECKER_TYPE,
128665  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_212_WIDTH },
128666  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_213_CHECKER_TYPE,
128667  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_213_WIDTH },
128668  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_214_CHECKER_TYPE,
128669  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_214_WIDTH },
128670  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_215_CHECKER_TYPE,
128671  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_215_WIDTH },
128672  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_216_CHECKER_TYPE,
128673  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_216_WIDTH },
128674  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_217_CHECKER_TYPE,
128675  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_217_WIDTH },
128676  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_218_CHECKER_TYPE,
128677  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_218_WIDTH },
128678  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_219_CHECKER_TYPE,
128679  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_219_WIDTH },
128680  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_220_CHECKER_TYPE,
128681  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_220_WIDTH },
128682  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_221_CHECKER_TYPE,
128683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_221_WIDTH },
128684  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_222_CHECKER_TYPE,
128685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_222_WIDTH },
128686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_223_CHECKER_TYPE,
128687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_223_WIDTH },
128688  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_224_CHECKER_TYPE,
128689  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_224_WIDTH },
128690  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_225_CHECKER_TYPE,
128691  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_225_WIDTH },
128692  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_226_CHECKER_TYPE,
128693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_226_WIDTH },
128694  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_227_CHECKER_TYPE,
128695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_227_WIDTH },
128696  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_228_CHECKER_TYPE,
128697  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_228_WIDTH },
128698  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_229_CHECKER_TYPE,
128699  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_229_WIDTH },
128700  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_230_CHECKER_TYPE,
128701  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_230_WIDTH },
128702  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_231_CHECKER_TYPE,
128703  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_231_WIDTH },
128704  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_232_CHECKER_TYPE,
128705  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_232_WIDTH },
128706  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_233_CHECKER_TYPE,
128707  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_233_WIDTH },
128708  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_234_CHECKER_TYPE,
128709  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_234_WIDTH },
128710  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_235_CHECKER_TYPE,
128711  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_235_WIDTH },
128712  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_236_CHECKER_TYPE,
128713  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_236_WIDTH },
128714  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_237_CHECKER_TYPE,
128715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_237_WIDTH },
128716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_238_CHECKER_TYPE,
128717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_238_WIDTH },
128718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_239_CHECKER_TYPE,
128719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_239_WIDTH },
128720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_240_CHECKER_TYPE,
128721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_240_WIDTH },
128722  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_241_CHECKER_TYPE,
128723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_241_WIDTH },
128724  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_242_CHECKER_TYPE,
128725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_242_WIDTH },
128726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_243_CHECKER_TYPE,
128727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_243_WIDTH },
128728  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_244_CHECKER_TYPE,
128729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_244_WIDTH },
128730  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_245_CHECKER_TYPE,
128731  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_245_WIDTH },
128732  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_246_CHECKER_TYPE,
128733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_246_WIDTH },
128734  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_247_CHECKER_TYPE,
128735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_247_WIDTH },
128736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_248_CHECKER_TYPE,
128737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_248_WIDTH },
128738  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_249_CHECKER_TYPE,
128739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_249_WIDTH },
128740  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_250_CHECKER_TYPE,
128741  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_250_WIDTH },
128742  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_251_CHECKER_TYPE,
128743  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_251_WIDTH },
128744  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_252_CHECKER_TYPE,
128745  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_252_WIDTH },
128746  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_253_CHECKER_TYPE,
128747  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_253_WIDTH },
128748  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_254_CHECKER_TYPE,
128749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_254_WIDTH },
128750  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_255_CHECKER_TYPE,
128751  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_GROUP_255_WIDTH },
128752 };
128753 
128759 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_MAX_NUM_CHECKERS] =
128760 {
128761  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_0_CHECKER_TYPE,
128762  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_0_WIDTH },
128763  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_1_CHECKER_TYPE,
128764  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_1_WIDTH },
128765  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_2_CHECKER_TYPE,
128766  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_2_WIDTH },
128767  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_3_CHECKER_TYPE,
128768  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_3_WIDTH },
128769  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_4_CHECKER_TYPE,
128770  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_4_WIDTH },
128771  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_5_CHECKER_TYPE,
128772  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_5_WIDTH },
128773  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_6_CHECKER_TYPE,
128774  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_6_WIDTH },
128775  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_7_CHECKER_TYPE,
128776  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_7_WIDTH },
128777  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_8_CHECKER_TYPE,
128778  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_8_WIDTH },
128779  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_9_CHECKER_TYPE,
128780  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_9_WIDTH },
128781  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_10_CHECKER_TYPE,
128782  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_10_WIDTH },
128783  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_11_CHECKER_TYPE,
128784  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_11_WIDTH },
128785  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_12_CHECKER_TYPE,
128786  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_12_WIDTH },
128787  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_13_CHECKER_TYPE,
128788  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_13_WIDTH },
128789  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_14_CHECKER_TYPE,
128790  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_14_WIDTH },
128791  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_15_CHECKER_TYPE,
128792  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_15_WIDTH },
128793  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_16_CHECKER_TYPE,
128794  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_16_WIDTH },
128795  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_17_CHECKER_TYPE,
128796  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_17_WIDTH },
128797  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_18_CHECKER_TYPE,
128798  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_18_WIDTH },
128799  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_19_CHECKER_TYPE,
128800  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_19_WIDTH },
128801  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_20_CHECKER_TYPE,
128802  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_20_WIDTH },
128803  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_21_CHECKER_TYPE,
128804  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_21_WIDTH },
128805  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_22_CHECKER_TYPE,
128806  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_22_WIDTH },
128807  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_23_CHECKER_TYPE,
128808  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_23_WIDTH },
128809  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_24_CHECKER_TYPE,
128810  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_24_WIDTH },
128811  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_25_CHECKER_TYPE,
128812  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_25_WIDTH },
128813  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_26_CHECKER_TYPE,
128814  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_26_WIDTH },
128815  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_27_CHECKER_TYPE,
128816  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_27_WIDTH },
128817  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_28_CHECKER_TYPE,
128818  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_28_WIDTH },
128819  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_29_CHECKER_TYPE,
128820  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_29_WIDTH },
128821  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_30_CHECKER_TYPE,
128822  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_30_WIDTH },
128823  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_31_CHECKER_TYPE,
128824  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_31_WIDTH },
128825  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_32_CHECKER_TYPE,
128826  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_32_WIDTH },
128827  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_33_CHECKER_TYPE,
128828  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_33_WIDTH },
128829  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_34_CHECKER_TYPE,
128830  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_34_WIDTH },
128831  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_35_CHECKER_TYPE,
128832  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_35_WIDTH },
128833  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_36_CHECKER_TYPE,
128834  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_36_WIDTH },
128835  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_37_CHECKER_TYPE,
128836  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_37_WIDTH },
128837  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_38_CHECKER_TYPE,
128838  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_38_WIDTH },
128839  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_39_CHECKER_TYPE,
128840  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_39_WIDTH },
128841  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_40_CHECKER_TYPE,
128842  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_40_WIDTH },
128843  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_41_CHECKER_TYPE,
128844  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_41_WIDTH },
128845  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_42_CHECKER_TYPE,
128846  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_42_WIDTH },
128847  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_43_CHECKER_TYPE,
128848  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_43_WIDTH },
128849  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_44_CHECKER_TYPE,
128850  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_44_WIDTH },
128851  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_45_CHECKER_TYPE,
128852  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_45_WIDTH },
128853  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_46_CHECKER_TYPE,
128854  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_46_WIDTH },
128855  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_47_CHECKER_TYPE,
128856  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_47_WIDTH },
128857  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_48_CHECKER_TYPE,
128858  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_48_WIDTH },
128859  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_49_CHECKER_TYPE,
128860  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_49_WIDTH },
128861  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_50_CHECKER_TYPE,
128862  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_50_WIDTH },
128863  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_51_CHECKER_TYPE,
128864  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_51_WIDTH },
128865  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_52_CHECKER_TYPE,
128866  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_52_WIDTH },
128867  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_53_CHECKER_TYPE,
128868  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_53_WIDTH },
128869  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_54_CHECKER_TYPE,
128870  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_54_WIDTH },
128871  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_55_CHECKER_TYPE,
128872  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_55_WIDTH },
128873  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_56_CHECKER_TYPE,
128874  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_56_WIDTH },
128875  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_57_CHECKER_TYPE,
128876  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_57_WIDTH },
128877  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_58_CHECKER_TYPE,
128878  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_58_WIDTH },
128879  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_59_CHECKER_TYPE,
128880  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_59_WIDTH },
128881  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_60_CHECKER_TYPE,
128882  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_60_WIDTH },
128883  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_61_CHECKER_TYPE,
128884  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_61_WIDTH },
128885  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_62_CHECKER_TYPE,
128886  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_62_WIDTH },
128887  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_63_CHECKER_TYPE,
128888  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_63_WIDTH },
128889  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_64_CHECKER_TYPE,
128890  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_64_WIDTH },
128891  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_65_CHECKER_TYPE,
128892  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_65_WIDTH },
128893  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_66_CHECKER_TYPE,
128894  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_66_WIDTH },
128895  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_67_CHECKER_TYPE,
128896  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_67_WIDTH },
128897  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_68_CHECKER_TYPE,
128898  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_68_WIDTH },
128899  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_69_CHECKER_TYPE,
128900  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_69_WIDTH },
128901  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_70_CHECKER_TYPE,
128902  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_70_WIDTH },
128903  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_71_CHECKER_TYPE,
128904  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_71_WIDTH },
128905  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_72_CHECKER_TYPE,
128906  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_72_WIDTH },
128907  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_73_CHECKER_TYPE,
128908  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_73_WIDTH },
128909  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_74_CHECKER_TYPE,
128910  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_74_WIDTH },
128911  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_75_CHECKER_TYPE,
128912  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_75_WIDTH },
128913  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_76_CHECKER_TYPE,
128914  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_76_WIDTH },
128915  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_77_CHECKER_TYPE,
128916  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_77_WIDTH },
128917  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_78_CHECKER_TYPE,
128918  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_78_WIDTH },
128919  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_79_CHECKER_TYPE,
128920  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_79_WIDTH },
128921  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_80_CHECKER_TYPE,
128922  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_80_WIDTH },
128923  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_81_CHECKER_TYPE,
128924  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_81_WIDTH },
128925  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_82_CHECKER_TYPE,
128926  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_82_WIDTH },
128927  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_83_CHECKER_TYPE,
128928  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_83_WIDTH },
128929  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_84_CHECKER_TYPE,
128930  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_84_WIDTH },
128931  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_85_CHECKER_TYPE,
128932  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_85_WIDTH },
128933  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_86_CHECKER_TYPE,
128934  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_86_WIDTH },
128935  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_87_CHECKER_TYPE,
128936  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_87_WIDTH },
128937  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_88_CHECKER_TYPE,
128938  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_88_WIDTH },
128939  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_89_CHECKER_TYPE,
128940  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_89_WIDTH },
128941  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_90_CHECKER_TYPE,
128942  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_90_WIDTH },
128943  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_91_CHECKER_TYPE,
128944  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_91_WIDTH },
128945  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_92_CHECKER_TYPE,
128946  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_92_WIDTH },
128947  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_93_CHECKER_TYPE,
128948  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_93_WIDTH },
128949  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_94_CHECKER_TYPE,
128950  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_94_WIDTH },
128951  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_95_CHECKER_TYPE,
128952  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_95_WIDTH },
128953  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_96_CHECKER_TYPE,
128954  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_96_WIDTH },
128955  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_97_CHECKER_TYPE,
128956  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_97_WIDTH },
128957  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_98_CHECKER_TYPE,
128958  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_98_WIDTH },
128959  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_99_CHECKER_TYPE,
128960  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_99_WIDTH },
128961  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_100_CHECKER_TYPE,
128962  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_100_WIDTH },
128963  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_101_CHECKER_TYPE,
128964  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_101_WIDTH },
128965  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_102_CHECKER_TYPE,
128966  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_102_WIDTH },
128967  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_103_CHECKER_TYPE,
128968  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_103_WIDTH },
128969  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_104_CHECKER_TYPE,
128970  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_104_WIDTH },
128971  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_105_CHECKER_TYPE,
128972  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_105_WIDTH },
128973  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_106_CHECKER_TYPE,
128974  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_106_WIDTH },
128975  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_107_CHECKER_TYPE,
128976  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_107_WIDTH },
128977  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_108_CHECKER_TYPE,
128978  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_108_WIDTH },
128979  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_109_CHECKER_TYPE,
128980  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_109_WIDTH },
128981  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_110_CHECKER_TYPE,
128982  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_110_WIDTH },
128983  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_111_CHECKER_TYPE,
128984  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_111_WIDTH },
128985  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_112_CHECKER_TYPE,
128986  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_112_WIDTH },
128987  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_113_CHECKER_TYPE,
128988  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_113_WIDTH },
128989  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_114_CHECKER_TYPE,
128990  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_114_WIDTH },
128991  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_115_CHECKER_TYPE,
128992  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_115_WIDTH },
128993  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_116_CHECKER_TYPE,
128994  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_116_WIDTH },
128995  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_117_CHECKER_TYPE,
128996  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_117_WIDTH },
128997  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_118_CHECKER_TYPE,
128998  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_118_WIDTH },
128999  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_119_CHECKER_TYPE,
129000  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_119_WIDTH },
129001  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_120_CHECKER_TYPE,
129002  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_120_WIDTH },
129003  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_121_CHECKER_TYPE,
129004  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_121_WIDTH },
129005  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_122_CHECKER_TYPE,
129006  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_122_WIDTH },
129007  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_123_CHECKER_TYPE,
129008  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_123_WIDTH },
129009  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_124_CHECKER_TYPE,
129010  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_124_WIDTH },
129011  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_125_CHECKER_TYPE,
129012  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_125_WIDTH },
129013  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_126_CHECKER_TYPE,
129014  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_126_WIDTH },
129015  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_127_CHECKER_TYPE,
129016  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_127_WIDTH },
129017  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_128_CHECKER_TYPE,
129018  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_128_WIDTH },
129019  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_129_CHECKER_TYPE,
129020  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_129_WIDTH },
129021  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_130_CHECKER_TYPE,
129022  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_130_WIDTH },
129023  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_131_CHECKER_TYPE,
129024  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_131_WIDTH },
129025  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_132_CHECKER_TYPE,
129026  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_132_WIDTH },
129027  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_133_CHECKER_TYPE,
129028  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_133_WIDTH },
129029  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_134_CHECKER_TYPE,
129030  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_134_WIDTH },
129031  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_135_CHECKER_TYPE,
129032  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_135_WIDTH },
129033  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_136_CHECKER_TYPE,
129034  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_136_WIDTH },
129035  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_137_CHECKER_TYPE,
129036  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_137_WIDTH },
129037  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_138_CHECKER_TYPE,
129038  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_138_WIDTH },
129039  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_139_CHECKER_TYPE,
129040  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_139_WIDTH },
129041  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_140_CHECKER_TYPE,
129042  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_140_WIDTH },
129043  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_141_CHECKER_TYPE,
129044  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_141_WIDTH },
129045  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_142_CHECKER_TYPE,
129046  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_142_WIDTH },
129047  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_143_CHECKER_TYPE,
129048  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_143_WIDTH },
129049  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_144_CHECKER_TYPE,
129050  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_144_WIDTH },
129051  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_145_CHECKER_TYPE,
129052  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_145_WIDTH },
129053  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_146_CHECKER_TYPE,
129054  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_146_WIDTH },
129055  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_147_CHECKER_TYPE,
129056  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_147_WIDTH },
129057  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_148_CHECKER_TYPE,
129058  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_148_WIDTH },
129059  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_149_CHECKER_TYPE,
129060  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_149_WIDTH },
129061  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_150_CHECKER_TYPE,
129062  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_150_WIDTH },
129063  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_151_CHECKER_TYPE,
129064  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_151_WIDTH },
129065  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_152_CHECKER_TYPE,
129066  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_152_WIDTH },
129067  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_153_CHECKER_TYPE,
129068  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_153_WIDTH },
129069  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_154_CHECKER_TYPE,
129070  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_154_WIDTH },
129071  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_155_CHECKER_TYPE,
129072  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_155_WIDTH },
129073  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_156_CHECKER_TYPE,
129074  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_156_WIDTH },
129075  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_157_CHECKER_TYPE,
129076  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_157_WIDTH },
129077  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_158_CHECKER_TYPE,
129078  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_158_WIDTH },
129079  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_159_CHECKER_TYPE,
129080  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_159_WIDTH },
129081  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_160_CHECKER_TYPE,
129082  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_160_WIDTH },
129083  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_161_CHECKER_TYPE,
129084  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_161_WIDTH },
129085  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_162_CHECKER_TYPE,
129086  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_162_WIDTH },
129087  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_163_CHECKER_TYPE,
129088  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_163_WIDTH },
129089  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_164_CHECKER_TYPE,
129090  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_164_WIDTH },
129091  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_165_CHECKER_TYPE,
129092  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_165_WIDTH },
129093  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_166_CHECKER_TYPE,
129094  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_166_WIDTH },
129095  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_167_CHECKER_TYPE,
129096  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_167_WIDTH },
129097  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_168_CHECKER_TYPE,
129098  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_168_WIDTH },
129099  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_169_CHECKER_TYPE,
129100  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_169_WIDTH },
129101  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_170_CHECKER_TYPE,
129102  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_170_WIDTH },
129103  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_171_CHECKER_TYPE,
129104  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_171_WIDTH },
129105  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_172_CHECKER_TYPE,
129106  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_172_WIDTH },
129107  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_173_CHECKER_TYPE,
129108  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_173_WIDTH },
129109  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_174_CHECKER_TYPE,
129110  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_174_WIDTH },
129111  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_175_CHECKER_TYPE,
129112  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_175_WIDTH },
129113  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_176_CHECKER_TYPE,
129114  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_176_WIDTH },
129115  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_177_CHECKER_TYPE,
129116  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_177_WIDTH },
129117  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_178_CHECKER_TYPE,
129118  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_178_WIDTH },
129119  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_179_CHECKER_TYPE,
129120  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_179_WIDTH },
129121  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_180_CHECKER_TYPE,
129122  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_180_WIDTH },
129123  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_181_CHECKER_TYPE,
129124  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_181_WIDTH },
129125  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_182_CHECKER_TYPE,
129126  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_182_WIDTH },
129127  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_183_CHECKER_TYPE,
129128  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_183_WIDTH },
129129  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_184_CHECKER_TYPE,
129130  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_184_WIDTH },
129131  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_185_CHECKER_TYPE,
129132  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_185_WIDTH },
129133  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_186_CHECKER_TYPE,
129134  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_186_WIDTH },
129135  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_187_CHECKER_TYPE,
129136  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_187_WIDTH },
129137  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_188_CHECKER_TYPE,
129138  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_188_WIDTH },
129139  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_189_CHECKER_TYPE,
129140  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_189_WIDTH },
129141  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_190_CHECKER_TYPE,
129142  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_190_WIDTH },
129143  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_191_CHECKER_TYPE,
129144  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_GROUP_191_WIDTH },
129145 };
129146 
129152 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS] =
129153 {
129154  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_0_CHECKER_TYPE,
129155  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_0_WIDTH },
129156  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_1_CHECKER_TYPE,
129157  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_1_WIDTH },
129158  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_2_CHECKER_TYPE,
129159  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_2_WIDTH },
129160  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_3_CHECKER_TYPE,
129161  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_3_WIDTH },
129162  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_4_CHECKER_TYPE,
129163  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_4_WIDTH },
129164  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_5_CHECKER_TYPE,
129165  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_5_WIDTH },
129166  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_6_CHECKER_TYPE,
129167  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_6_WIDTH },
129168  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_7_CHECKER_TYPE,
129169  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_7_WIDTH },
129170  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_8_CHECKER_TYPE,
129171  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_8_WIDTH },
129172  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_9_CHECKER_TYPE,
129173  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_9_WIDTH },
129174  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_10_CHECKER_TYPE,
129175  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_10_WIDTH },
129176  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_11_CHECKER_TYPE,
129177  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_11_WIDTH },
129178  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_12_CHECKER_TYPE,
129179  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_12_WIDTH },
129180  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_13_CHECKER_TYPE,
129181  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_13_WIDTH },
129182  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_14_CHECKER_TYPE,
129183  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_14_WIDTH },
129184  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_15_CHECKER_TYPE,
129185  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_15_WIDTH },
129186  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_16_CHECKER_TYPE,
129187  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_16_WIDTH },
129188  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_17_CHECKER_TYPE,
129189  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_17_WIDTH },
129190  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_18_CHECKER_TYPE,
129191  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_18_WIDTH },
129192  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_19_CHECKER_TYPE,
129193  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_19_WIDTH },
129194  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_20_CHECKER_TYPE,
129195  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_20_WIDTH },
129196  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_21_CHECKER_TYPE,
129197  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_21_WIDTH },
129198  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_22_CHECKER_TYPE,
129199  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_GROUP_22_WIDTH },
129200 };
129201 
129207 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS] =
129208 {
129209  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
129210  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_0_WIDTH },
129211  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
129212  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_1_WIDTH },
129213  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
129214  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_2_WIDTH },
129215  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
129216  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_3_WIDTH },
129217  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
129218  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_4_WIDTH },
129219  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
129220  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_5_WIDTH },
129221  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
129222  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_6_WIDTH },
129223  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
129224  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_7_WIDTH },
129225  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
129226  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_8_WIDTH },
129227  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
129228  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_9_WIDTH },
129229  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
129230  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_10_WIDTH },
129231  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
129232  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_11_WIDTH },
129233  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
129234  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_12_WIDTH },
129235  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
129236  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_13_WIDTH },
129237  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
129238  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_14_WIDTH },
129239  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
129240  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_15_WIDTH },
129241  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
129242  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_16_WIDTH },
129243  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
129244  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_17_WIDTH },
129245  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
129246  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_18_WIDTH },
129247  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
129248  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_19_WIDTH },
129249  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
129250  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_20_WIDTH },
129251  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
129252  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_21_WIDTH },
129253  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
129254  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_22_WIDTH },
129255  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
129256  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_23_WIDTH },
129257  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
129258  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_24_WIDTH },
129259  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
129260  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_25_WIDTH },
129261  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
129262  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_GROUP_26_WIDTH },
129263 };
129264 
129270 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_MAX_NUM_CHECKERS] =
129271 {
129272  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_0_CHECKER_TYPE,
129273  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_0_WIDTH },
129274  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_1_CHECKER_TYPE,
129275  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_1_WIDTH },
129276  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_2_CHECKER_TYPE,
129277  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_2_WIDTH },
129278  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_3_CHECKER_TYPE,
129279  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_3_WIDTH },
129280  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_4_CHECKER_TYPE,
129281  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_4_WIDTH },
129282  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_5_CHECKER_TYPE,
129283  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_5_WIDTH },
129284  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_6_CHECKER_TYPE,
129285  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_6_WIDTH },
129286  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_7_CHECKER_TYPE,
129287  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_7_WIDTH },
129288  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_8_CHECKER_TYPE,
129289  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_8_WIDTH },
129290  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_9_CHECKER_TYPE,
129291  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_9_WIDTH },
129292  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_10_CHECKER_TYPE,
129293  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_10_WIDTH },
129294  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_11_CHECKER_TYPE,
129295  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_11_WIDTH },
129296  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_12_CHECKER_TYPE,
129297  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_12_WIDTH },
129298  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_13_CHECKER_TYPE,
129299  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_13_WIDTH },
129300  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_14_CHECKER_TYPE,
129301  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_14_WIDTH },
129302  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_15_CHECKER_TYPE,
129303  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_GROUP_15_WIDTH },
129304 };
129305 
129311 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_MAX_NUM_CHECKERS] =
129312 {
129313  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_0_CHECKER_TYPE,
129314  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_0_WIDTH },
129315  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_1_CHECKER_TYPE,
129316  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_1_WIDTH },
129317  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_2_CHECKER_TYPE,
129318  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_2_WIDTH },
129319  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_3_CHECKER_TYPE,
129320  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_3_WIDTH },
129321  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_4_CHECKER_TYPE,
129322  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_4_WIDTH },
129323  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_5_CHECKER_TYPE,
129324  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_5_WIDTH },
129325  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_6_CHECKER_TYPE,
129326  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_6_WIDTH },
129327  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_7_CHECKER_TYPE,
129328  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_7_WIDTH },
129329  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_8_CHECKER_TYPE,
129330  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_8_WIDTH },
129331  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_9_CHECKER_TYPE,
129332  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_9_WIDTH },
129333  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_10_CHECKER_TYPE,
129334  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_10_WIDTH },
129335  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_11_CHECKER_TYPE,
129336  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_11_WIDTH },
129337  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_12_CHECKER_TYPE,
129338  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_12_WIDTH },
129339  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_13_CHECKER_TYPE,
129340  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_GROUP_13_WIDTH },
129341 };
129342 
129348 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_MAX_NUM_CHECKERS] =
129349 {
129350  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_0_CHECKER_TYPE,
129351  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_0_WIDTH },
129352  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_1_CHECKER_TYPE,
129353  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_1_WIDTH },
129354  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_2_CHECKER_TYPE,
129355  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_2_WIDTH },
129356  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_3_CHECKER_TYPE,
129357  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_3_WIDTH },
129358  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_4_CHECKER_TYPE,
129359  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_4_WIDTH },
129360  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_5_CHECKER_TYPE,
129361  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_5_WIDTH },
129362  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_6_CHECKER_TYPE,
129363  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_6_WIDTH },
129364  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_7_CHECKER_TYPE,
129365  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_7_WIDTH },
129366  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_8_CHECKER_TYPE,
129367  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_8_WIDTH },
129368  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_9_CHECKER_TYPE,
129369  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_9_WIDTH },
129370  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_10_CHECKER_TYPE,
129371  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_10_WIDTH },
129372  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_11_CHECKER_TYPE,
129373  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_11_WIDTH },
129374  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_12_CHECKER_TYPE,
129375  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_12_WIDTH },
129376  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_13_CHECKER_TYPE,
129377  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_13_WIDTH },
129378  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_14_CHECKER_TYPE,
129379  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_14_WIDTH },
129380  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_15_CHECKER_TYPE,
129381  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_15_WIDTH },
129382  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_16_CHECKER_TYPE,
129383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_16_WIDTH },
129384  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_17_CHECKER_TYPE,
129385  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_17_WIDTH },
129386  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_18_CHECKER_TYPE,
129387  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_18_WIDTH },
129388  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_19_CHECKER_TYPE,
129389  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_19_WIDTH },
129390  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_20_CHECKER_TYPE,
129391  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_20_WIDTH },
129392  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_21_CHECKER_TYPE,
129393  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_21_WIDTH },
129394  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_22_CHECKER_TYPE,
129395  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_22_WIDTH },
129396  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_23_CHECKER_TYPE,
129397  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_23_WIDTH },
129398  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_24_CHECKER_TYPE,
129399  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_24_WIDTH },
129400  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_25_CHECKER_TYPE,
129401  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_25_WIDTH },
129402  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_26_CHECKER_TYPE,
129403  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_26_WIDTH },
129404  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_27_CHECKER_TYPE,
129405  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_27_WIDTH },
129406  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_28_CHECKER_TYPE,
129407  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_28_WIDTH },
129408  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_29_CHECKER_TYPE,
129409  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_29_WIDTH },
129410  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_30_CHECKER_TYPE,
129411  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_30_WIDTH },
129412  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_31_CHECKER_TYPE,
129413  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_31_WIDTH },
129414  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_32_CHECKER_TYPE,
129415  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_32_WIDTH },
129416  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_33_CHECKER_TYPE,
129417  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_33_WIDTH },
129418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_34_CHECKER_TYPE,
129419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_34_WIDTH },
129420  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_35_CHECKER_TYPE,
129421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_35_WIDTH },
129422  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_36_CHECKER_TYPE,
129423  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_36_WIDTH },
129424  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_37_CHECKER_TYPE,
129425  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_37_WIDTH },
129426  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_38_CHECKER_TYPE,
129427  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_38_WIDTH },
129428  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_39_CHECKER_TYPE,
129429  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_39_WIDTH },
129430  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_40_CHECKER_TYPE,
129431  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_40_WIDTH },
129432  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_41_CHECKER_TYPE,
129433  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_41_WIDTH },
129434  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_42_CHECKER_TYPE,
129435  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_42_WIDTH },
129436  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_43_CHECKER_TYPE,
129437  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_43_WIDTH },
129438  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_44_CHECKER_TYPE,
129439  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_44_WIDTH },
129440  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_45_CHECKER_TYPE,
129441  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_45_WIDTH },
129442  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_46_CHECKER_TYPE,
129443  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_46_WIDTH },
129444  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_47_CHECKER_TYPE,
129445  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_47_WIDTH },
129446  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_48_CHECKER_TYPE,
129447  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_48_WIDTH },
129448  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_49_CHECKER_TYPE,
129449  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_49_WIDTH },
129450  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_50_CHECKER_TYPE,
129451  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_50_WIDTH },
129452  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_51_CHECKER_TYPE,
129453  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_51_WIDTH },
129454  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_52_CHECKER_TYPE,
129455  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_GROUP_52_WIDTH },
129456 };
129457 
129463 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS] =
129464 {
129465  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
129466  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_0_WIDTH },
129467  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
129468  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_1_WIDTH },
129469  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
129470  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_2_WIDTH },
129471  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
129472  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_3_WIDTH },
129473  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
129474  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_4_WIDTH },
129475  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
129476  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_5_WIDTH },
129477  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
129478  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_6_WIDTH },
129479  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
129480  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_7_WIDTH },
129481  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
129482  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_8_WIDTH },
129483  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
129484  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_9_WIDTH },
129485  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
129486  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_10_WIDTH },
129487  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
129488  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_11_WIDTH },
129489  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
129490  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_12_WIDTH },
129491  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
129492  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_13_WIDTH },
129493  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
129494  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_14_WIDTH },
129495  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
129496  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_15_WIDTH },
129497  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
129498  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_16_WIDTH },
129499  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
129500  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_17_WIDTH },
129501  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
129502  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_18_WIDTH },
129503  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
129504  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_19_WIDTH },
129505  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
129506  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_20_WIDTH },
129507  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
129508  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_21_WIDTH },
129509  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
129510  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_22_WIDTH },
129511  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
129512  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_23_WIDTH },
129513  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
129514  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_24_WIDTH },
129515  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
129516  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_25_WIDTH },
129517  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
129518  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_26_WIDTH },
129519  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_27_CHECKER_TYPE,
129520  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_27_WIDTH },
129521  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_28_CHECKER_TYPE,
129522  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_28_WIDTH },
129523  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_29_CHECKER_TYPE,
129524  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_29_WIDTH },
129525  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_30_CHECKER_TYPE,
129526  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_30_WIDTH },
129527  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_31_CHECKER_TYPE,
129528  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_31_WIDTH },
129529  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_32_CHECKER_TYPE,
129530  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_32_WIDTH },
129531  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_33_CHECKER_TYPE,
129532  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_33_WIDTH },
129533  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_34_CHECKER_TYPE,
129534  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_34_WIDTH },
129535  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_35_CHECKER_TYPE,
129536  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_35_WIDTH },
129537  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_36_CHECKER_TYPE,
129538  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_36_WIDTH },
129539  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_37_CHECKER_TYPE,
129540  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_37_WIDTH },
129541  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_38_CHECKER_TYPE,
129542  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_38_WIDTH },
129543  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_39_CHECKER_TYPE,
129544  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_39_WIDTH },
129545  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_40_CHECKER_TYPE,
129546  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_40_WIDTH },
129547  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_41_CHECKER_TYPE,
129548  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_41_WIDTH },
129549  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_42_CHECKER_TYPE,
129550  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_42_WIDTH },
129551  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_43_CHECKER_TYPE,
129552  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_43_WIDTH },
129553  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_44_CHECKER_TYPE,
129554  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_44_WIDTH },
129555  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_45_CHECKER_TYPE,
129556  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_45_WIDTH },
129557  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_46_CHECKER_TYPE,
129558  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_46_WIDTH },
129559  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_47_CHECKER_TYPE,
129560  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_GROUP_47_WIDTH },
129561 };
129562 
129568 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_MAX_NUM_CHECKERS] =
129569 {
129570  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_0_CHECKER_TYPE,
129571  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_0_WIDTH },
129572  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_1_CHECKER_TYPE,
129573  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_1_WIDTH },
129574  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_2_CHECKER_TYPE,
129575  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_2_WIDTH },
129576  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_3_CHECKER_TYPE,
129577  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_3_WIDTH },
129578  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_4_CHECKER_TYPE,
129579  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_4_WIDTH },
129580  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_5_CHECKER_TYPE,
129581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_5_WIDTH },
129582  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_6_CHECKER_TYPE,
129583  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_6_WIDTH },
129584  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_7_CHECKER_TYPE,
129585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_7_WIDTH },
129586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_8_CHECKER_TYPE,
129587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_8_WIDTH },
129588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_9_CHECKER_TYPE,
129589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_9_WIDTH },
129590  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_10_CHECKER_TYPE,
129591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_10_WIDTH },
129592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_11_CHECKER_TYPE,
129593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_11_WIDTH },
129594  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_12_CHECKER_TYPE,
129595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_12_WIDTH },
129596  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_13_CHECKER_TYPE,
129597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_13_WIDTH },
129598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_14_CHECKER_TYPE,
129599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_14_WIDTH },
129600  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_15_CHECKER_TYPE,
129601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_15_WIDTH },
129602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_16_CHECKER_TYPE,
129603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_16_WIDTH },
129604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_17_CHECKER_TYPE,
129605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_17_WIDTH },
129606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_18_CHECKER_TYPE,
129607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_18_WIDTH },
129608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_19_CHECKER_TYPE,
129609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_19_WIDTH },
129610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_20_CHECKER_TYPE,
129611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_20_WIDTH },
129612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_21_CHECKER_TYPE,
129613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_21_WIDTH },
129614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_22_CHECKER_TYPE,
129615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_22_WIDTH },
129616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_23_CHECKER_TYPE,
129617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_23_WIDTH },
129618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_24_CHECKER_TYPE,
129619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_24_WIDTH },
129620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_25_CHECKER_TYPE,
129621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_25_WIDTH },
129622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_26_CHECKER_TYPE,
129623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_26_WIDTH },
129624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_27_CHECKER_TYPE,
129625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_27_WIDTH },
129626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_28_CHECKER_TYPE,
129627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_28_WIDTH },
129628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_29_CHECKER_TYPE,
129629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_29_WIDTH },
129630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_30_CHECKER_TYPE,
129631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_30_WIDTH },
129632  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_31_CHECKER_TYPE,
129633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_31_WIDTH },
129634  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_32_CHECKER_TYPE,
129635  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_32_WIDTH },
129636  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_33_CHECKER_TYPE,
129637  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_33_WIDTH },
129638  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_34_CHECKER_TYPE,
129639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_34_WIDTH },
129640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_35_CHECKER_TYPE,
129641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_35_WIDTH },
129642  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_36_CHECKER_TYPE,
129643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_36_WIDTH },
129644  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_37_CHECKER_TYPE,
129645  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_37_WIDTH },
129646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_38_CHECKER_TYPE,
129647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_38_WIDTH },
129648  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_39_CHECKER_TYPE,
129649  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_39_WIDTH },
129650  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_40_CHECKER_TYPE,
129651  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_40_WIDTH },
129652  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_41_CHECKER_TYPE,
129653  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_41_WIDTH },
129654  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_42_CHECKER_TYPE,
129655  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_42_WIDTH },
129656  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_43_CHECKER_TYPE,
129657  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_43_WIDTH },
129658  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_44_CHECKER_TYPE,
129659  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_44_WIDTH },
129660  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_45_CHECKER_TYPE,
129661  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_45_WIDTH },
129662  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_46_CHECKER_TYPE,
129663  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_46_WIDTH },
129664  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_47_CHECKER_TYPE,
129665  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_47_WIDTH },
129666  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_48_CHECKER_TYPE,
129667  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_48_WIDTH },
129668  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_49_CHECKER_TYPE,
129669  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_49_WIDTH },
129670  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_50_CHECKER_TYPE,
129671  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_50_WIDTH },
129672  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_51_CHECKER_TYPE,
129673  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_51_WIDTH },
129674  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_52_CHECKER_TYPE,
129675  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_52_WIDTH },
129676  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_53_CHECKER_TYPE,
129677  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_53_WIDTH },
129678  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_54_CHECKER_TYPE,
129679  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_54_WIDTH },
129680  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_55_CHECKER_TYPE,
129681  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_55_WIDTH },
129682  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_56_CHECKER_TYPE,
129683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_56_WIDTH },
129684  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_57_CHECKER_TYPE,
129685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_57_WIDTH },
129686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_58_CHECKER_TYPE,
129687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_58_WIDTH },
129688  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_59_CHECKER_TYPE,
129689  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_59_WIDTH },
129690  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_60_CHECKER_TYPE,
129691  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_60_WIDTH },
129692  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_61_CHECKER_TYPE,
129693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_61_WIDTH },
129694  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_62_CHECKER_TYPE,
129695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_62_WIDTH },
129696  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_63_CHECKER_TYPE,
129697  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_63_WIDTH },
129698  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_64_CHECKER_TYPE,
129699  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_64_WIDTH },
129700  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_65_CHECKER_TYPE,
129701  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_65_WIDTH },
129702  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_66_CHECKER_TYPE,
129703  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_66_WIDTH },
129704  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_67_CHECKER_TYPE,
129705  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_67_WIDTH },
129706  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_68_CHECKER_TYPE,
129707  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_68_WIDTH },
129708  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_69_CHECKER_TYPE,
129709  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_69_WIDTH },
129710  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_70_CHECKER_TYPE,
129711  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_70_WIDTH },
129712  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_71_CHECKER_TYPE,
129713  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_71_WIDTH },
129714  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_72_CHECKER_TYPE,
129715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_72_WIDTH },
129716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_73_CHECKER_TYPE,
129717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_73_WIDTH },
129718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_74_CHECKER_TYPE,
129719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_74_WIDTH },
129720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_75_CHECKER_TYPE,
129721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_75_WIDTH },
129722  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_76_CHECKER_TYPE,
129723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_76_WIDTH },
129724  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_77_CHECKER_TYPE,
129725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_77_WIDTH },
129726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_78_CHECKER_TYPE,
129727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_78_WIDTH },
129728  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_79_CHECKER_TYPE,
129729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_79_WIDTH },
129730  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_80_CHECKER_TYPE,
129731  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_80_WIDTH },
129732  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_81_CHECKER_TYPE,
129733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_81_WIDTH },
129734  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_82_CHECKER_TYPE,
129735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_82_WIDTH },
129736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_83_CHECKER_TYPE,
129737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_83_WIDTH },
129738  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_84_CHECKER_TYPE,
129739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_84_WIDTH },
129740  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_85_CHECKER_TYPE,
129741  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_85_WIDTH },
129742  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_86_CHECKER_TYPE,
129743  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_86_WIDTH },
129744  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_87_CHECKER_TYPE,
129745  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_87_WIDTH },
129746  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_88_CHECKER_TYPE,
129747  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_88_WIDTH },
129748  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_89_CHECKER_TYPE,
129749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_89_WIDTH },
129750  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_90_CHECKER_TYPE,
129751  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_90_WIDTH },
129752  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_91_CHECKER_TYPE,
129753  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_91_WIDTH },
129754  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_92_CHECKER_TYPE,
129755  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_92_WIDTH },
129756  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_93_CHECKER_TYPE,
129757  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_93_WIDTH },
129758  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_94_CHECKER_TYPE,
129759  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_94_WIDTH },
129760  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_95_CHECKER_TYPE,
129761  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_95_WIDTH },
129762  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_96_CHECKER_TYPE,
129763  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_96_WIDTH },
129764  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_97_CHECKER_TYPE,
129765  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_97_WIDTH },
129766  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_98_CHECKER_TYPE,
129767  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_98_WIDTH },
129768  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_99_CHECKER_TYPE,
129769  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_99_WIDTH },
129770  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_100_CHECKER_TYPE,
129771  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_100_WIDTH },
129772  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_101_CHECKER_TYPE,
129773  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_101_WIDTH },
129774  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_102_CHECKER_TYPE,
129775  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_102_WIDTH },
129776  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_103_CHECKER_TYPE,
129777  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_103_WIDTH },
129778  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_104_CHECKER_TYPE,
129779  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_104_WIDTH },
129780  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_105_CHECKER_TYPE,
129781  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_105_WIDTH },
129782  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_106_CHECKER_TYPE,
129783  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_106_WIDTH },
129784  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_107_CHECKER_TYPE,
129785  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_107_WIDTH },
129786  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_108_CHECKER_TYPE,
129787  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_108_WIDTH },
129788  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_109_CHECKER_TYPE,
129789  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_109_WIDTH },
129790  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_110_CHECKER_TYPE,
129791  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_110_WIDTH },
129792  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_111_CHECKER_TYPE,
129793  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_111_WIDTH },
129794  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_112_CHECKER_TYPE,
129795  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_112_WIDTH },
129796  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_113_CHECKER_TYPE,
129797  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_113_WIDTH },
129798  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_114_CHECKER_TYPE,
129799  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_114_WIDTH },
129800  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_115_CHECKER_TYPE,
129801  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_115_WIDTH },
129802  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_116_CHECKER_TYPE,
129803  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_116_WIDTH },
129804  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_117_CHECKER_TYPE,
129805  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_117_WIDTH },
129806  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_118_CHECKER_TYPE,
129807  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_118_WIDTH },
129808  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_119_CHECKER_TYPE,
129809  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_119_WIDTH },
129810  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_120_CHECKER_TYPE,
129811  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_120_WIDTH },
129812  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_121_CHECKER_TYPE,
129813  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_121_WIDTH },
129814  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_122_CHECKER_TYPE,
129815  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_122_WIDTH },
129816  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_123_CHECKER_TYPE,
129817  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_123_WIDTH },
129818  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_124_CHECKER_TYPE,
129819  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_124_WIDTH },
129820  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_125_CHECKER_TYPE,
129821  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_125_WIDTH },
129822  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_126_CHECKER_TYPE,
129823  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_126_WIDTH },
129824  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_127_CHECKER_TYPE,
129825  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_127_WIDTH },
129826  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_128_CHECKER_TYPE,
129827  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_128_WIDTH },
129828  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_129_CHECKER_TYPE,
129829  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_129_WIDTH },
129830  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_130_CHECKER_TYPE,
129831  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_130_WIDTH },
129832  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_131_CHECKER_TYPE,
129833  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_131_WIDTH },
129834  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_132_CHECKER_TYPE,
129835  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_132_WIDTH },
129836  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_133_CHECKER_TYPE,
129837  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_133_WIDTH },
129838  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_134_CHECKER_TYPE,
129839  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_134_WIDTH },
129840  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_135_CHECKER_TYPE,
129841  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_135_WIDTH },
129842  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_136_CHECKER_TYPE,
129843  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_136_WIDTH },
129844  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_137_CHECKER_TYPE,
129845  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_137_WIDTH },
129846  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_138_CHECKER_TYPE,
129847  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_138_WIDTH },
129848  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_139_CHECKER_TYPE,
129849  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_139_WIDTH },
129850  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_140_CHECKER_TYPE,
129851  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_140_WIDTH },
129852  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_141_CHECKER_TYPE,
129853  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_141_WIDTH },
129854  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_142_CHECKER_TYPE,
129855  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_142_WIDTH },
129856  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_143_CHECKER_TYPE,
129857  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_143_WIDTH },
129858  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_144_CHECKER_TYPE,
129859  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_144_WIDTH },
129860  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_145_CHECKER_TYPE,
129861  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_145_WIDTH },
129862  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_146_CHECKER_TYPE,
129863  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_146_WIDTH },
129864  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_147_CHECKER_TYPE,
129865  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_147_WIDTH },
129866  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_148_CHECKER_TYPE,
129867  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_148_WIDTH },
129868  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_149_CHECKER_TYPE,
129869  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_149_WIDTH },
129870  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_150_CHECKER_TYPE,
129871  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_150_WIDTH },
129872  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_151_CHECKER_TYPE,
129873  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_151_WIDTH },
129874  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_152_CHECKER_TYPE,
129875  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_152_WIDTH },
129876  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_153_CHECKER_TYPE,
129877  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_153_WIDTH },
129878  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_154_CHECKER_TYPE,
129879  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_154_WIDTH },
129880  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_155_CHECKER_TYPE,
129881  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_155_WIDTH },
129882  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_156_CHECKER_TYPE,
129883  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_156_WIDTH },
129884  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_157_CHECKER_TYPE,
129885  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_157_WIDTH },
129886  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_158_CHECKER_TYPE,
129887  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_158_WIDTH },
129888  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_159_CHECKER_TYPE,
129889  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_159_WIDTH },
129890  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_160_CHECKER_TYPE,
129891  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_160_WIDTH },
129892  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_161_CHECKER_TYPE,
129893  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_161_WIDTH },
129894  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_162_CHECKER_TYPE,
129895  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_162_WIDTH },
129896  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_163_CHECKER_TYPE,
129897  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_163_WIDTH },
129898  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_164_CHECKER_TYPE,
129899  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_164_WIDTH },
129900  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_165_CHECKER_TYPE,
129901  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_165_WIDTH },
129902  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_166_CHECKER_TYPE,
129903  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_166_WIDTH },
129904  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_167_CHECKER_TYPE,
129905  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_167_WIDTH },
129906  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_168_CHECKER_TYPE,
129907  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_168_WIDTH },
129908  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_169_CHECKER_TYPE,
129909  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_169_WIDTH },
129910  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_170_CHECKER_TYPE,
129911  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_170_WIDTH },
129912  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_171_CHECKER_TYPE,
129913  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_171_WIDTH },
129914  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_172_CHECKER_TYPE,
129915  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_172_WIDTH },
129916  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_173_CHECKER_TYPE,
129917  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_173_WIDTH },
129918  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_174_CHECKER_TYPE,
129919  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_174_WIDTH },
129920  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_175_CHECKER_TYPE,
129921  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_175_WIDTH },
129922  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_176_CHECKER_TYPE,
129923  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_176_WIDTH },
129924  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_177_CHECKER_TYPE,
129925  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_177_WIDTH },
129926  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_178_CHECKER_TYPE,
129927  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_178_WIDTH },
129928  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_179_CHECKER_TYPE,
129929  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_179_WIDTH },
129930  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_180_CHECKER_TYPE,
129931  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_180_WIDTH },
129932  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_181_CHECKER_TYPE,
129933  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_181_WIDTH },
129934  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_182_CHECKER_TYPE,
129935  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_182_WIDTH },
129936  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_183_CHECKER_TYPE,
129937  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_183_WIDTH },
129938  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_184_CHECKER_TYPE,
129939  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_184_WIDTH },
129940  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_185_CHECKER_TYPE,
129941  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_185_WIDTH },
129942  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_186_CHECKER_TYPE,
129943  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_186_WIDTH },
129944  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_187_CHECKER_TYPE,
129945  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_187_WIDTH },
129946  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_188_CHECKER_TYPE,
129947  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_188_WIDTH },
129948  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_189_CHECKER_TYPE,
129949  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_189_WIDTH },
129950  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_190_CHECKER_TYPE,
129951  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_190_WIDTH },
129952  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_191_CHECKER_TYPE,
129953  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_191_WIDTH },
129954  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_192_CHECKER_TYPE,
129955  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_192_WIDTH },
129956  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_193_CHECKER_TYPE,
129957  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_193_WIDTH },
129958  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_194_CHECKER_TYPE,
129959  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_194_WIDTH },
129960  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_195_CHECKER_TYPE,
129961  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_195_WIDTH },
129962  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_196_CHECKER_TYPE,
129963  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_196_WIDTH },
129964  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_197_CHECKER_TYPE,
129965  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_197_WIDTH },
129966  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_198_CHECKER_TYPE,
129967  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_198_WIDTH },
129968  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_199_CHECKER_TYPE,
129969  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_199_WIDTH },
129970  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_200_CHECKER_TYPE,
129971  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_200_WIDTH },
129972  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_201_CHECKER_TYPE,
129973  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_201_WIDTH },
129974  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_202_CHECKER_TYPE,
129975  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_202_WIDTH },
129976  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_203_CHECKER_TYPE,
129977  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_203_WIDTH },
129978  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_204_CHECKER_TYPE,
129979  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_204_WIDTH },
129980  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_205_CHECKER_TYPE,
129981  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_205_WIDTH },
129982  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_206_CHECKER_TYPE,
129983  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_206_WIDTH },
129984  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_207_CHECKER_TYPE,
129985  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_207_WIDTH },
129986  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_208_CHECKER_TYPE,
129987  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_208_WIDTH },
129988  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_209_CHECKER_TYPE,
129989  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_209_WIDTH },
129990  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_210_CHECKER_TYPE,
129991  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_210_WIDTH },
129992  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_211_CHECKER_TYPE,
129993  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_211_WIDTH },
129994  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_212_CHECKER_TYPE,
129995  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_212_WIDTH },
129996  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_213_CHECKER_TYPE,
129997  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_213_WIDTH },
129998  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_214_CHECKER_TYPE,
129999  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_214_WIDTH },
130000  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_215_CHECKER_TYPE,
130001  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_215_WIDTH },
130002  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_216_CHECKER_TYPE,
130003  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_216_WIDTH },
130004  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_217_CHECKER_TYPE,
130005  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_217_WIDTH },
130006  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_218_CHECKER_TYPE,
130007  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_218_WIDTH },
130008  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_219_CHECKER_TYPE,
130009  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_219_WIDTH },
130010  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_220_CHECKER_TYPE,
130011  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_220_WIDTH },
130012  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_221_CHECKER_TYPE,
130013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_221_WIDTH },
130014  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_222_CHECKER_TYPE,
130015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_222_WIDTH },
130016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_223_CHECKER_TYPE,
130017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_223_WIDTH },
130018  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_224_CHECKER_TYPE,
130019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_224_WIDTH },
130020  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_225_CHECKER_TYPE,
130021  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_225_WIDTH },
130022  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_226_CHECKER_TYPE,
130023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_226_WIDTH },
130024  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_227_CHECKER_TYPE,
130025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_227_WIDTH },
130026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_228_CHECKER_TYPE,
130027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_228_WIDTH },
130028  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_229_CHECKER_TYPE,
130029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_229_WIDTH },
130030  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_230_CHECKER_TYPE,
130031  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_230_WIDTH },
130032  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_231_CHECKER_TYPE,
130033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_231_WIDTH },
130034  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_232_CHECKER_TYPE,
130035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_232_WIDTH },
130036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_233_CHECKER_TYPE,
130037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_233_WIDTH },
130038  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_234_CHECKER_TYPE,
130039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_234_WIDTH },
130040  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_235_CHECKER_TYPE,
130041  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_235_WIDTH },
130042  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_236_CHECKER_TYPE,
130043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_236_WIDTH },
130044  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_237_CHECKER_TYPE,
130045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_237_WIDTH },
130046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_238_CHECKER_TYPE,
130047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_238_WIDTH },
130048  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_239_CHECKER_TYPE,
130049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_239_WIDTH },
130050  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_240_CHECKER_TYPE,
130051  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_240_WIDTH },
130052  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_241_CHECKER_TYPE,
130053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_241_WIDTH },
130054  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_242_CHECKER_TYPE,
130055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_242_WIDTH },
130056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_243_CHECKER_TYPE,
130057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_243_WIDTH },
130058  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_244_CHECKER_TYPE,
130059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_244_WIDTH },
130060  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_245_CHECKER_TYPE,
130061  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_245_WIDTH },
130062  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_246_CHECKER_TYPE,
130063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_246_WIDTH },
130064  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_247_CHECKER_TYPE,
130065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_247_WIDTH },
130066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_248_CHECKER_TYPE,
130067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_248_WIDTH },
130068  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_249_CHECKER_TYPE,
130069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_249_WIDTH },
130070  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_250_CHECKER_TYPE,
130071  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_250_WIDTH },
130072  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_251_CHECKER_TYPE,
130073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_251_WIDTH },
130074  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_252_CHECKER_TYPE,
130075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_252_WIDTH },
130076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_253_CHECKER_TYPE,
130077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_253_WIDTH },
130078  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_254_CHECKER_TYPE,
130079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_254_WIDTH },
130080  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_255_CHECKER_TYPE,
130081  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_GROUP_255_WIDTH },
130082 };
130083 
130089 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_MAX_NUM_CHECKERS] =
130090 {
130091  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_0_CHECKER_TYPE,
130092  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_0_WIDTH },
130093  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_1_CHECKER_TYPE,
130094  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_1_WIDTH },
130095  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_2_CHECKER_TYPE,
130096  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_2_WIDTH },
130097  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_3_CHECKER_TYPE,
130098  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_3_WIDTH },
130099  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_4_CHECKER_TYPE,
130100  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_4_WIDTH },
130101  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_5_CHECKER_TYPE,
130102  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_5_WIDTH },
130103  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_6_CHECKER_TYPE,
130104  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_6_WIDTH },
130105  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_7_CHECKER_TYPE,
130106  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_7_WIDTH },
130107  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_8_CHECKER_TYPE,
130108  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_8_WIDTH },
130109  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_9_CHECKER_TYPE,
130110  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_9_WIDTH },
130111  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_10_CHECKER_TYPE,
130112  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_10_WIDTH },
130113  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_11_CHECKER_TYPE,
130114  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_11_WIDTH },
130115  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_12_CHECKER_TYPE,
130116  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_12_WIDTH },
130117  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_13_CHECKER_TYPE,
130118  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_13_WIDTH },
130119  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_14_CHECKER_TYPE,
130120  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_14_WIDTH },
130121  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_15_CHECKER_TYPE,
130122  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_15_WIDTH },
130123  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_16_CHECKER_TYPE,
130124  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_16_WIDTH },
130125  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_17_CHECKER_TYPE,
130126  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_17_WIDTH },
130127  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_18_CHECKER_TYPE,
130128  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_18_WIDTH },
130129  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_19_CHECKER_TYPE,
130130  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_19_WIDTH },
130131  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_20_CHECKER_TYPE,
130132  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_20_WIDTH },
130133  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_21_CHECKER_TYPE,
130134  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_21_WIDTH },
130135  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_22_CHECKER_TYPE,
130136  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_22_WIDTH },
130137  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_23_CHECKER_TYPE,
130138  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_23_WIDTH },
130139  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_24_CHECKER_TYPE,
130140  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_24_WIDTH },
130141  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_25_CHECKER_TYPE,
130142  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_25_WIDTH },
130143  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_26_CHECKER_TYPE,
130144  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_26_WIDTH },
130145  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_27_CHECKER_TYPE,
130146  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_27_WIDTH },
130147  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_28_CHECKER_TYPE,
130148  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_28_WIDTH },
130149  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_29_CHECKER_TYPE,
130150  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_29_WIDTH },
130151  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_30_CHECKER_TYPE,
130152  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_30_WIDTH },
130153  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_31_CHECKER_TYPE,
130154  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_31_WIDTH },
130155  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_32_CHECKER_TYPE,
130156  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_32_WIDTH },
130157  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_33_CHECKER_TYPE,
130158  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_33_WIDTH },
130159  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_34_CHECKER_TYPE,
130160  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_34_WIDTH },
130161  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_35_CHECKER_TYPE,
130162  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_35_WIDTH },
130163  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_36_CHECKER_TYPE,
130164  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_36_WIDTH },
130165  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_37_CHECKER_TYPE,
130166  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_37_WIDTH },
130167  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_38_CHECKER_TYPE,
130168  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_38_WIDTH },
130169  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_39_CHECKER_TYPE,
130170  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_39_WIDTH },
130171  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_40_CHECKER_TYPE,
130172  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_40_WIDTH },
130173  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_41_CHECKER_TYPE,
130174  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_41_WIDTH },
130175  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_42_CHECKER_TYPE,
130176  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_42_WIDTH },
130177  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_43_CHECKER_TYPE,
130178  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_43_WIDTH },
130179  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_44_CHECKER_TYPE,
130180  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_44_WIDTH },
130181  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_45_CHECKER_TYPE,
130182  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_45_WIDTH },
130183  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_46_CHECKER_TYPE,
130184  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_46_WIDTH },
130185  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_47_CHECKER_TYPE,
130186  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_47_WIDTH },
130187  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_48_CHECKER_TYPE,
130188  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_48_WIDTH },
130189  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_49_CHECKER_TYPE,
130190  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_49_WIDTH },
130191  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_50_CHECKER_TYPE,
130192  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_50_WIDTH },
130193  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_51_CHECKER_TYPE,
130194  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_51_WIDTH },
130195  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_52_CHECKER_TYPE,
130196  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_52_WIDTH },
130197  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_53_CHECKER_TYPE,
130198  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_53_WIDTH },
130199  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_54_CHECKER_TYPE,
130200  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_54_WIDTH },
130201  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_55_CHECKER_TYPE,
130202  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_55_WIDTH },
130203  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_56_CHECKER_TYPE,
130204  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_56_WIDTH },
130205  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_57_CHECKER_TYPE,
130206  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_57_WIDTH },
130207  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_58_CHECKER_TYPE,
130208  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_58_WIDTH },
130209  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_59_CHECKER_TYPE,
130210  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_59_WIDTH },
130211  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_60_CHECKER_TYPE,
130212  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_60_WIDTH },
130213  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_61_CHECKER_TYPE,
130214  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_61_WIDTH },
130215  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_62_CHECKER_TYPE,
130216  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_62_WIDTH },
130217  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_63_CHECKER_TYPE,
130218  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_63_WIDTH },
130219  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_64_CHECKER_TYPE,
130220  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_64_WIDTH },
130221  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_65_CHECKER_TYPE,
130222  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_65_WIDTH },
130223  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_66_CHECKER_TYPE,
130224  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_66_WIDTH },
130225  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_67_CHECKER_TYPE,
130226  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_67_WIDTH },
130227  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_68_CHECKER_TYPE,
130228  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_68_WIDTH },
130229  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_69_CHECKER_TYPE,
130230  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_69_WIDTH },
130231  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_70_CHECKER_TYPE,
130232  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_70_WIDTH },
130233  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_71_CHECKER_TYPE,
130234  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_71_WIDTH },
130235  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_72_CHECKER_TYPE,
130236  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_72_WIDTH },
130237  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_73_CHECKER_TYPE,
130238  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_73_WIDTH },
130239  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_74_CHECKER_TYPE,
130240  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_74_WIDTH },
130241  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_75_CHECKER_TYPE,
130242  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_75_WIDTH },
130243  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_76_CHECKER_TYPE,
130244  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_76_WIDTH },
130245  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_77_CHECKER_TYPE,
130246  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_77_WIDTH },
130247  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_78_CHECKER_TYPE,
130248  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_78_WIDTH },
130249  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_79_CHECKER_TYPE,
130250  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_79_WIDTH },
130251  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_80_CHECKER_TYPE,
130252  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_80_WIDTH },
130253  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_81_CHECKER_TYPE,
130254  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_81_WIDTH },
130255  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_82_CHECKER_TYPE,
130256  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_82_WIDTH },
130257  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_83_CHECKER_TYPE,
130258  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_83_WIDTH },
130259  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_84_CHECKER_TYPE,
130260  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_84_WIDTH },
130261  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_85_CHECKER_TYPE,
130262  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_85_WIDTH },
130263  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_86_CHECKER_TYPE,
130264  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_86_WIDTH },
130265  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_87_CHECKER_TYPE,
130266  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_87_WIDTH },
130267  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_88_CHECKER_TYPE,
130268  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_88_WIDTH },
130269  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_89_CHECKER_TYPE,
130270  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_89_WIDTH },
130271  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_90_CHECKER_TYPE,
130272  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_90_WIDTH },
130273  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_91_CHECKER_TYPE,
130274  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_91_WIDTH },
130275  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_92_CHECKER_TYPE,
130276  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_92_WIDTH },
130277  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_93_CHECKER_TYPE,
130278  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_93_WIDTH },
130279  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_94_CHECKER_TYPE,
130280  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_94_WIDTH },
130281  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_95_CHECKER_TYPE,
130282  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_95_WIDTH },
130283  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_96_CHECKER_TYPE,
130284  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_96_WIDTH },
130285  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_97_CHECKER_TYPE,
130286  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_97_WIDTH },
130287  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_98_CHECKER_TYPE,
130288  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_98_WIDTH },
130289  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_99_CHECKER_TYPE,
130290  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_99_WIDTH },
130291  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_100_CHECKER_TYPE,
130292  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_100_WIDTH },
130293  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_101_CHECKER_TYPE,
130294  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_101_WIDTH },
130295  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_102_CHECKER_TYPE,
130296  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_102_WIDTH },
130297  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_103_CHECKER_TYPE,
130298  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_103_WIDTH },
130299  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_104_CHECKER_TYPE,
130300  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_104_WIDTH },
130301  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_105_CHECKER_TYPE,
130302  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_105_WIDTH },
130303  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_106_CHECKER_TYPE,
130304  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_106_WIDTH },
130305  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_107_CHECKER_TYPE,
130306  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_107_WIDTH },
130307  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_108_CHECKER_TYPE,
130308  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_108_WIDTH },
130309  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_109_CHECKER_TYPE,
130310  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_109_WIDTH },
130311  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_110_CHECKER_TYPE,
130312  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_110_WIDTH },
130313  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_111_CHECKER_TYPE,
130314  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_111_WIDTH },
130315  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_112_CHECKER_TYPE,
130316  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_112_WIDTH },
130317  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_113_CHECKER_TYPE,
130318  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_113_WIDTH },
130319  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_114_CHECKER_TYPE,
130320  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_114_WIDTH },
130321  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_115_CHECKER_TYPE,
130322  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_115_WIDTH },
130323  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_116_CHECKER_TYPE,
130324  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_116_WIDTH },
130325  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_117_CHECKER_TYPE,
130326  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_117_WIDTH },
130327  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_118_CHECKER_TYPE,
130328  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_118_WIDTH },
130329  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_119_CHECKER_TYPE,
130330  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_119_WIDTH },
130331  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_120_CHECKER_TYPE,
130332  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_120_WIDTH },
130333  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_121_CHECKER_TYPE,
130334  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_121_WIDTH },
130335  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_122_CHECKER_TYPE,
130336  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_122_WIDTH },
130337  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_123_CHECKER_TYPE,
130338  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_123_WIDTH },
130339  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_124_CHECKER_TYPE,
130340  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_124_WIDTH },
130341  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_125_CHECKER_TYPE,
130342  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_125_WIDTH },
130343  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_126_CHECKER_TYPE,
130344  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_126_WIDTH },
130345  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_127_CHECKER_TYPE,
130346  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_127_WIDTH },
130347  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_128_CHECKER_TYPE,
130348  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_128_WIDTH },
130349  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_129_CHECKER_TYPE,
130350  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_129_WIDTH },
130351  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_130_CHECKER_TYPE,
130352  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_130_WIDTH },
130353  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_131_CHECKER_TYPE,
130354  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_131_WIDTH },
130355  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_132_CHECKER_TYPE,
130356  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_132_WIDTH },
130357  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_133_CHECKER_TYPE,
130358  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_133_WIDTH },
130359  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_134_CHECKER_TYPE,
130360  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_134_WIDTH },
130361  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_135_CHECKER_TYPE,
130362  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_135_WIDTH },
130363  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_136_CHECKER_TYPE,
130364  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_136_WIDTH },
130365  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_137_CHECKER_TYPE,
130366  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_137_WIDTH },
130367  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_138_CHECKER_TYPE,
130368  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_138_WIDTH },
130369  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_139_CHECKER_TYPE,
130370  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_139_WIDTH },
130371  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_140_CHECKER_TYPE,
130372  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_140_WIDTH },
130373  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_141_CHECKER_TYPE,
130374  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_141_WIDTH },
130375  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_142_CHECKER_TYPE,
130376  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_142_WIDTH },
130377  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_143_CHECKER_TYPE,
130378  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_143_WIDTH },
130379  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_144_CHECKER_TYPE,
130380  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_144_WIDTH },
130381  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_145_CHECKER_TYPE,
130382  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_145_WIDTH },
130383  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_146_CHECKER_TYPE,
130384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_146_WIDTH },
130385  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_147_CHECKER_TYPE,
130386  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_147_WIDTH },
130387  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_148_CHECKER_TYPE,
130388  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_148_WIDTH },
130389  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_149_CHECKER_TYPE,
130390  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_149_WIDTH },
130391  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_150_CHECKER_TYPE,
130392  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_150_WIDTH },
130393  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_151_CHECKER_TYPE,
130394  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_151_WIDTH },
130395  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_152_CHECKER_TYPE,
130396  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_152_WIDTH },
130397  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_153_CHECKER_TYPE,
130398  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_153_WIDTH },
130399  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_154_CHECKER_TYPE,
130400  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_154_WIDTH },
130401  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_155_CHECKER_TYPE,
130402  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_155_WIDTH },
130403  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_156_CHECKER_TYPE,
130404  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_156_WIDTH },
130405  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_157_CHECKER_TYPE,
130406  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_157_WIDTH },
130407  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_158_CHECKER_TYPE,
130408  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_158_WIDTH },
130409  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_159_CHECKER_TYPE,
130410  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_159_WIDTH },
130411  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_160_CHECKER_TYPE,
130412  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_160_WIDTH },
130413  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_161_CHECKER_TYPE,
130414  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_161_WIDTH },
130415  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_162_CHECKER_TYPE,
130416  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_162_WIDTH },
130417  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_163_CHECKER_TYPE,
130418  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_163_WIDTH },
130419  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_164_CHECKER_TYPE,
130420  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_164_WIDTH },
130421  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_165_CHECKER_TYPE,
130422  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_165_WIDTH },
130423  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_166_CHECKER_TYPE,
130424  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_166_WIDTH },
130425  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_167_CHECKER_TYPE,
130426  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_167_WIDTH },
130427  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_168_CHECKER_TYPE,
130428  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_168_WIDTH },
130429  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_169_CHECKER_TYPE,
130430  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_169_WIDTH },
130431  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_170_CHECKER_TYPE,
130432  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_170_WIDTH },
130433  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_171_CHECKER_TYPE,
130434  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_171_WIDTH },
130435  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_172_CHECKER_TYPE,
130436  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_172_WIDTH },
130437  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_173_CHECKER_TYPE,
130438  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_173_WIDTH },
130439  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_174_CHECKER_TYPE,
130440  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_174_WIDTH },
130441  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_175_CHECKER_TYPE,
130442  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_175_WIDTH },
130443  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_176_CHECKER_TYPE,
130444  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_176_WIDTH },
130445  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_177_CHECKER_TYPE,
130446  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_177_WIDTH },
130447  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_178_CHECKER_TYPE,
130448  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_178_WIDTH },
130449  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_179_CHECKER_TYPE,
130450  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_179_WIDTH },
130451  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_180_CHECKER_TYPE,
130452  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_180_WIDTH },
130453  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_181_CHECKER_TYPE,
130454  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_181_WIDTH },
130455  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_182_CHECKER_TYPE,
130456  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_182_WIDTH },
130457  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_183_CHECKER_TYPE,
130458  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_183_WIDTH },
130459  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_184_CHECKER_TYPE,
130460  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_184_WIDTH },
130461  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_185_CHECKER_TYPE,
130462  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_185_WIDTH },
130463  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_186_CHECKER_TYPE,
130464  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_186_WIDTH },
130465  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_187_CHECKER_TYPE,
130466  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_187_WIDTH },
130467  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_188_CHECKER_TYPE,
130468  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_188_WIDTH },
130469  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_189_CHECKER_TYPE,
130470  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_189_WIDTH },
130471  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_190_CHECKER_TYPE,
130472  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_190_WIDTH },
130473  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_191_CHECKER_TYPE,
130474  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_GROUP_191_WIDTH },
130475 };
130476 
130482 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS] =
130483 {
130484  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_0_CHECKER_TYPE,
130485  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_0_WIDTH },
130486  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_1_CHECKER_TYPE,
130487  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_1_WIDTH },
130488  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_2_CHECKER_TYPE,
130489  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_2_WIDTH },
130490  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_3_CHECKER_TYPE,
130491  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_3_WIDTH },
130492  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_4_CHECKER_TYPE,
130493  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_4_WIDTH },
130494  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_5_CHECKER_TYPE,
130495  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_5_WIDTH },
130496  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_6_CHECKER_TYPE,
130497  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_6_WIDTH },
130498  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_7_CHECKER_TYPE,
130499  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_7_WIDTH },
130500  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_8_CHECKER_TYPE,
130501  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_8_WIDTH },
130502  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_9_CHECKER_TYPE,
130503  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_9_WIDTH },
130504  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_10_CHECKER_TYPE,
130505  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_10_WIDTH },
130506  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_11_CHECKER_TYPE,
130507  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_11_WIDTH },
130508  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_12_CHECKER_TYPE,
130509  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_12_WIDTH },
130510  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_13_CHECKER_TYPE,
130511  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_13_WIDTH },
130512  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_14_CHECKER_TYPE,
130513  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_14_WIDTH },
130514  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_15_CHECKER_TYPE,
130515  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_15_WIDTH },
130516  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_16_CHECKER_TYPE,
130517  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_16_WIDTH },
130518  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_17_CHECKER_TYPE,
130519  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_17_WIDTH },
130520  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_18_CHECKER_TYPE,
130521  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_18_WIDTH },
130522  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_19_CHECKER_TYPE,
130523  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_19_WIDTH },
130524  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_20_CHECKER_TYPE,
130525  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_20_WIDTH },
130526  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_21_CHECKER_TYPE,
130527  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_21_WIDTH },
130528  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_22_CHECKER_TYPE,
130529  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_GROUP_22_WIDTH },
130530 };
130531 
130537 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS] =
130538 {
130539  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
130540  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_0_WIDTH },
130541  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
130542  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_1_WIDTH },
130543  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
130544  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_2_WIDTH },
130545  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
130546  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_3_WIDTH },
130547  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
130548  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_4_WIDTH },
130549  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
130550  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_5_WIDTH },
130551  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
130552  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_6_WIDTH },
130553  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
130554  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_7_WIDTH },
130555  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
130556  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_8_WIDTH },
130557  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
130558  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_9_WIDTH },
130559  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
130560  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_10_WIDTH },
130561  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
130562  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_11_WIDTH },
130563  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
130564  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_12_WIDTH },
130565  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
130566  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_13_WIDTH },
130567  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
130568  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_14_WIDTH },
130569  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
130570  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_15_WIDTH },
130571  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
130572  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_16_WIDTH },
130573  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
130574  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_17_WIDTH },
130575  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
130576  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_18_WIDTH },
130577  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
130578  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_19_WIDTH },
130579  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
130580  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_20_WIDTH },
130581  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
130582  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_21_WIDTH },
130583  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
130584  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_22_WIDTH },
130585  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
130586  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_23_WIDTH },
130587  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
130588  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_24_WIDTH },
130589  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
130590  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_25_WIDTH },
130591  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
130592  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_GROUP_26_WIDTH },
130593 };
130594 
130600 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_MAX_NUM_CHECKERS] =
130601 {
130602  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_0_CHECKER_TYPE,
130603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_0_WIDTH },
130604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_1_CHECKER_TYPE,
130605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_1_WIDTH },
130606  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_2_CHECKER_TYPE,
130607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_2_WIDTH },
130608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_3_CHECKER_TYPE,
130609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_3_WIDTH },
130610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_4_CHECKER_TYPE,
130611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_4_WIDTH },
130612  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_5_CHECKER_TYPE,
130613  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_5_WIDTH },
130614  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_6_CHECKER_TYPE,
130615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_6_WIDTH },
130616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_7_CHECKER_TYPE,
130617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_7_WIDTH },
130618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_8_CHECKER_TYPE,
130619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_8_WIDTH },
130620  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_9_CHECKER_TYPE,
130621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_9_WIDTH },
130622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_10_CHECKER_TYPE,
130623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_10_WIDTH },
130624  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_11_CHECKER_TYPE,
130625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_11_WIDTH },
130626  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_12_CHECKER_TYPE,
130627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_12_WIDTH },
130628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_13_CHECKER_TYPE,
130629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_13_WIDTH },
130630  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_14_CHECKER_TYPE,
130631  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_14_WIDTH },
130632  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_15_CHECKER_TYPE,
130633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_GROUP_15_WIDTH },
130634 };
130635 
130641 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_MAX_NUM_CHECKERS] =
130642 {
130643  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_0_CHECKER_TYPE,
130644  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_0_WIDTH },
130645  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_1_CHECKER_TYPE,
130646  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_1_WIDTH },
130647  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_2_CHECKER_TYPE,
130648  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_2_WIDTH },
130649  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_3_CHECKER_TYPE,
130650  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_3_WIDTH },
130651  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_4_CHECKER_TYPE,
130652  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_4_WIDTH },
130653  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_5_CHECKER_TYPE,
130654  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_5_WIDTH },
130655  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_6_CHECKER_TYPE,
130656  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_6_WIDTH },
130657  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_7_CHECKER_TYPE,
130658  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_7_WIDTH },
130659  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_8_CHECKER_TYPE,
130660  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_8_WIDTH },
130661  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_9_CHECKER_TYPE,
130662  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_9_WIDTH },
130663  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_10_CHECKER_TYPE,
130664  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_10_WIDTH },
130665  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_11_CHECKER_TYPE,
130666  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_11_WIDTH },
130667  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_12_CHECKER_TYPE,
130668  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_12_WIDTH },
130669  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_13_CHECKER_TYPE,
130670  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_GROUP_13_WIDTH },
130671 };
130672 
130678 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS] =
130679 {
130680  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
130681  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_0_WIDTH },
130682  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
130683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_1_WIDTH },
130684  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
130685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_2_WIDTH },
130686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
130687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_GROUP_3_WIDTH },
130688 };
130689 
130695 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_MAX_NUM_CHECKERS] =
130696 {
130697  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_0_CHECKER_TYPE,
130698  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_0_WIDTH },
130699  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_1_CHECKER_TYPE,
130700  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_1_WIDTH },
130701  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_2_CHECKER_TYPE,
130702  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_2_WIDTH },
130703  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_3_CHECKER_TYPE,
130704  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_GROUP_3_WIDTH },
130705 };
130706 
130712 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_MAX_NUM_CHECKERS] =
130713 {
130714  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_0_CHECKER_TYPE,
130715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_0_WIDTH },
130716  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_1_CHECKER_TYPE,
130717  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_1_WIDTH },
130718  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_2_CHECKER_TYPE,
130719  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_2_WIDTH },
130720  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_3_CHECKER_TYPE,
130721  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_3_WIDTH },
130722  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_4_CHECKER_TYPE,
130723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_4_WIDTH },
130724  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_5_CHECKER_TYPE,
130725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_5_WIDTH },
130726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_6_CHECKER_TYPE,
130727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_6_WIDTH },
130728  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_7_CHECKER_TYPE,
130729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_7_WIDTH },
130730  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_8_CHECKER_TYPE,
130731  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_8_WIDTH },
130732  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_9_CHECKER_TYPE,
130733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_9_WIDTH },
130734  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_10_CHECKER_TYPE,
130735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_10_WIDTH },
130736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_11_CHECKER_TYPE,
130737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_11_WIDTH },
130738  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_12_CHECKER_TYPE,
130739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_12_WIDTH },
130740  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_13_CHECKER_TYPE,
130741  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_13_WIDTH },
130742  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_14_CHECKER_TYPE,
130743  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_14_WIDTH },
130744  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_15_CHECKER_TYPE,
130745  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_15_WIDTH },
130746  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_16_CHECKER_TYPE,
130747  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_16_WIDTH },
130748  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_17_CHECKER_TYPE,
130749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_17_WIDTH },
130750  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_18_CHECKER_TYPE,
130751  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_18_WIDTH },
130752  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_19_CHECKER_TYPE,
130753  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_19_WIDTH },
130754  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_20_CHECKER_TYPE,
130755  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_20_WIDTH },
130756  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_21_CHECKER_TYPE,
130757  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_21_WIDTH },
130758  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_22_CHECKER_TYPE,
130759  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_22_WIDTH },
130760  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_23_CHECKER_TYPE,
130761  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_23_WIDTH },
130762  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_24_CHECKER_TYPE,
130763  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_24_WIDTH },
130764  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_25_CHECKER_TYPE,
130765  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_25_WIDTH },
130766  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_26_CHECKER_TYPE,
130767  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_26_WIDTH },
130768  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_27_CHECKER_TYPE,
130769  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_27_WIDTH },
130770  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_28_CHECKER_TYPE,
130771  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_28_WIDTH },
130772  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_29_CHECKER_TYPE,
130773  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_GROUP_29_WIDTH },
130774 };
130775 
130781 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
130782 {
130783  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
130784  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
130785 };
130786 
130791 static const SDL_MemConfig_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
130792 {
130793  { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x27C8000u,
130794  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
130795  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
130796 };
130797 
130803 static const SDL_GrpChkConfig_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
130804 {
130805  { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
130806  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
130807 };
130808 
130813 static const SDL_MemConfig_t SDL_VPAC0_LDC_ECC_AGGR_MemEntries[SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
130814 {
130815  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_ID, 0u,
130816  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_SIZE, 4u,
130817  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
130818  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_ID, 0u,
130819  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_SIZE, 4u,
130820  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
130821  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_ID, 0u,
130822  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_SIZE, 4u,
130823  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_ROW_WIDTH, ((bool)false) },
130824  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_ID, 0u,
130825  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_SIZE, 4u,
130826  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_ROW_WIDTH, ((bool)false) },
130827  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_ID, 0u,
130828  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_SIZE, 4u,
130829  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_ROW_WIDTH, ((bool)false) },
130830  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_ID, 0u,
130831  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_SIZE, 4u,
130832  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_ROW_WIDTH, ((bool)false) },
130833  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_ID, 0u,
130834  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_SIZE, 4u,
130835  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_ROW_WIDTH, ((bool)false) },
130836  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_ID, 0u,
130837  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_SIZE, 4u,
130838  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_ROW_WIDTH, ((bool)false) },
130839  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_ID, 0u,
130840  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_SIZE, 4u,
130841  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_ROW_WIDTH, ((bool)false) },
130842  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_ID, 0u,
130843  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_SIZE, 4u,
130844  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_ROW_WIDTH, ((bool)false) },
130845  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_ID, 0u,
130846  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_SIZE, 4u,
130847  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_ROW_WIDTH, ((bool)false) },
130848  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_ID, 0u,
130849  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_SIZE, 4u,
130850  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_ROW_WIDTH, ((bool)false) },
130851 };
130852 
130857 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
130858 {
130859  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
130860  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
130861  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
130862  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
130863  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
130864  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
130865  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
130866  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
130867  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
130868  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
130869  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
130870  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
130871  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
130872  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
130873  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
130874  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
130875  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
130876  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
130877  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
130878  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
130879  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
130880  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
130881  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
130882  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
130883  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
130884  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
130885  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
130886  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
130887  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
130888  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
130889  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
130890  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
130891  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
130892  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
130893  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
130894  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
130895  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
130896  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
130897  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
130898  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
130899  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
130900  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
130901  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
130902  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
130903  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
130904  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
130905  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
130906  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
130907  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
130908  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
130909  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
130910  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
130911  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
130912  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
130913  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
130914  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
130915  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
130916  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
130917  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
130918  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
130919  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
130920  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
130921  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
130922  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0u,
130923  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 8u,
130924  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
130925  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x0u,
130926  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
130927  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
130928  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x0,
130929  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
130930  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
130931  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x0u,
130932  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
130933  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
130934  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x0u,
130935  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
130936  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
130937  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x0u,
130938  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
130939  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
130940  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0u,
130941  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
130942  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)false) },
130943 };
130944 
130950 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS] =
130951 {
130952  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
130953  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_0_WIDTH },
130954  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
130955  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_1_WIDTH },
130956  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
130957  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_2_WIDTH },
130958  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
130959  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_3_WIDTH },
130960  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
130961  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_4_WIDTH },
130962  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
130963  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_5_WIDTH },
130964  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
130965  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_6_WIDTH },
130966  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
130967  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_7_WIDTH },
130968  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
130969  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_8_WIDTH },
130970  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
130971  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_9_WIDTH },
130972  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
130973  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_10_WIDTH },
130974  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
130975  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_11_WIDTH },
130976  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
130977  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_12_WIDTH },
130978  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_13_CHECKER_TYPE,
130979  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_13_WIDTH },
130980  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_14_CHECKER_TYPE,
130981  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_14_WIDTH },
130982  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_15_CHECKER_TYPE,
130983  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_15_WIDTH },
130984  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_16_CHECKER_TYPE,
130985  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_16_WIDTH },
130986  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_17_CHECKER_TYPE,
130987  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_17_WIDTH },
130988  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_18_CHECKER_TYPE,
130989  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_18_WIDTH },
130990  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_19_CHECKER_TYPE,
130991  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_19_WIDTH },
130992  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_20_CHECKER_TYPE,
130993  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_20_WIDTH },
130994  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_21_CHECKER_TYPE,
130995  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_21_WIDTH },
130996  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_22_CHECKER_TYPE,
130997  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_22_WIDTH },
130998  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_23_CHECKER_TYPE,
130999  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_23_WIDTH },
131000  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_24_CHECKER_TYPE,
131001  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_24_WIDTH },
131002  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_25_CHECKER_TYPE,
131003  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_25_WIDTH },
131004  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_26_CHECKER_TYPE,
131005  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_26_WIDTH },
131006  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_27_CHECKER_TYPE,
131007  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_27_WIDTH },
131008  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_28_CHECKER_TYPE,
131009  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_28_WIDTH },
131010  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_29_CHECKER_TYPE,
131011  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_29_WIDTH },
131012  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_30_CHECKER_TYPE,
131013  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_30_WIDTH },
131014  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_31_CHECKER_TYPE,
131015  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_31_WIDTH },
131016  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_32_CHECKER_TYPE,
131017  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_32_WIDTH },
131018  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_33_CHECKER_TYPE,
131019  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_33_WIDTH },
131020  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_34_CHECKER_TYPE,
131021  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_34_WIDTH },
131022  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_35_CHECKER_TYPE,
131023  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_35_WIDTH },
131024  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_36_CHECKER_TYPE,
131025  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_36_WIDTH },
131026  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_37_CHECKER_TYPE,
131027  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_37_WIDTH },
131028  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_38_CHECKER_TYPE,
131029  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_38_WIDTH },
131030  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_39_CHECKER_TYPE,
131031  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_39_WIDTH },
131032  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_40_CHECKER_TYPE,
131033  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_40_WIDTH },
131034  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_41_CHECKER_TYPE,
131035  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_41_WIDTH },
131036  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_42_CHECKER_TYPE,
131037  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_42_WIDTH },
131038  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_43_CHECKER_TYPE,
131039  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_43_WIDTH },
131040  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_44_CHECKER_TYPE,
131041  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_44_WIDTH },
131042  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_45_CHECKER_TYPE,
131043  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_45_WIDTH },
131044  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_46_CHECKER_TYPE,
131045  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_46_WIDTH },
131046  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_47_CHECKER_TYPE,
131047  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_47_WIDTH },
131048  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_48_CHECKER_TYPE,
131049  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_48_WIDTH },
131050 };
131051 
131057 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
131058 {
131059  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
131060  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
131061  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
131062  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
131063  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
131064  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
131065  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
131066  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
131067  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
131068  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
131069  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
131070  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
131071  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
131072  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
131073  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
131074  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
131075  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
131076  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
131077  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
131078  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
131079  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
131080  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
131081  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
131082  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
131083  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
131084  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
131085  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
131086  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
131087  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
131088  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
131089  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
131090  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
131091  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
131092  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
131093  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
131094  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
131095  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
131096  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
131097  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
131098  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
131099  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
131100  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
131101  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
131102  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
131103  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
131104  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
131105  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
131106  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
131107  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
131108  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
131109  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
131110  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
131111  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
131112  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
131113  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
131114  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
131115  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
131116  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
131117  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
131118  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
131119  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
131120  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
131121 };
131122 
131128 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
131129 {
131130  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
131131  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
131132  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
131133  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
131134  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
131135  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
131136  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
131137  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
131138  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
131139  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
131140  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
131141  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
131142  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
131143  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
131144  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
131145  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
131146  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
131147  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
131148  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
131149  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
131150  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
131151  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
131152  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
131153  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
131154  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
131155  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
131156  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
131157  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
131158  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
131159  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
131160  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_CHECKER_TYPE,
131161  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_WIDTH },
131162 };
131163 
131169 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
131170 {
131171  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
131172  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
131173  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
131174  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
131175  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
131176  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
131177  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
131178  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
131179  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
131180  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
131181  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
131182  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
131183  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
131184  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
131185  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
131186  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
131187  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
131188  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
131189  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
131190  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
131191  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
131192  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
131193  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
131194  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
131195  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
131196  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
131197  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
131198  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
131199  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
131200  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
131201  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
131202  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
131203  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
131204  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
131205  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
131206  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
131207  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
131208  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
131209  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
131210  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
131211  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
131212  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
131213  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
131214  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
131215  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
131216  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
131217  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
131218  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
131219  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
131220  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
131221  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
131222  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
131223  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
131224  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
131225  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
131226  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
131227  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
131228  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
131229  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
131230  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
131231  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
131232  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
131233 };
131234 
131240 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
131241 {
131242  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
131243  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
131244  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
131245  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
131246  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
131247  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
131248  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
131249  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
131250  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
131251  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
131252  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
131253  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
131254  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
131255  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
131256  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
131257  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
131258  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
131259  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
131260  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
131261  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
131262  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
131263  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
131264  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
131265  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
131266  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
131267  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
131268  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
131269  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
131270  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
131271  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
131272 };
131273 
131279 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS] =
131280 {
131281  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
131282  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_WIDTH },
131283  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
131284  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_WIDTH },
131285  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
131286  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_WIDTH },
131287  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
131288  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_WIDTH },
131289  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
131290  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_WIDTH },
131291  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
131292  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_WIDTH },
131293  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
131294  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_WIDTH },
131295  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
131296  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_WIDTH },
131297  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
131298  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_WIDTH },
131299  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
131300  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_WIDTH },
131301  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
131302  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_WIDTH },
131303  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
131304  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_WIDTH },
131305  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
131306  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_WIDTH },
131307 };
131308 
131314 static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
131315 {
131316  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
131317  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
131318  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
131319  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
131320  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
131321  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
131322  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
131323  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
131324  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
131325  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
131326  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
131327  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
131328 };
131329 
131335 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS] =
131336 {
131337  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
131338  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
131339  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
131340  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
131341  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
131342  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
131343  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
131344  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
131345  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
131346  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
131347  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
131348  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
131349  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
131350  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
131351  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
131352  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
131353  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
131354  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
131355  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
131356  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
131357  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
131358  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
131359  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
131360  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
131361  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
131362  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
131363  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
131364  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
131365  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
131366  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
131367  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
131368  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
131369  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
131370  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
131371  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
131372  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
131373  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
131374  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
131375  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
131376  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
131377  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
131378  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
131379  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
131380  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
131381  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
131382  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
131383  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
131384  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
131385  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
131386  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
131387  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
131388  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
131389  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
131390  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
131391  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
131392  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
131393  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
131394  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
131395  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
131396  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
131397  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
131398  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
131399  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
131400  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
131401  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
131402  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
131403  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
131404  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
131405 };
131406 
131412 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
131413 {
131414  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
131415  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
131416  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
131417  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
131418  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
131419  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
131420  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
131421  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
131422 };
131423 
131429 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
131430 {
131431  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
131432  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
131433  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
131434  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
131435  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
131436  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
131437  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
131438  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
131439  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
131440  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
131441  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
131442  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
131443  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
131444  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
131445  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
131446  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
131447  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
131448  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
131449  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
131450  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
131451  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
131452  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
131453  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
131454  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
131455  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
131456  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
131457  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
131458  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
131459  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
131460  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
131461 };
131462 
131468 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
131469 {
131470  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
131471  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
131472  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
131473  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
131474  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
131475  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
131476  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
131477  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
131478 };
131479 
131485 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
131486 {
131487  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
131488  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
131489  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
131490  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
131491  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
131492  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
131493  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
131494  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
131495  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
131496  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
131497  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
131498  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
131499  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
131500  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
131501  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
131502  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
131503  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
131504  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
131505  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
131506  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
131507  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
131508  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
131509  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
131510  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
131511  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
131512  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
131513  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
131514  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
131515  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
131516  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
131517 };
131518 
131524 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
131525 {
131526  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
131527  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
131528  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
131529  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
131530  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
131531  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
131532  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
131533  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
131534 };
131535 
131541 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
131542 {
131543  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
131544  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
131545  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
131546  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
131547  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
131548  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
131549  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
131550  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
131551  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
131552  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
131553  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
131554  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
131555  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
131556  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
131557  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
131558  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
131559  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
131560  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
131561  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
131562  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
131563  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
131564  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
131565  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
131566  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
131567  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
131568  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
131569  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
131570  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
131571  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
131572  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
131573 };
131574 
131580 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS] =
131581 {
131582  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
131583  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_0_WIDTH },
131584  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
131585  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_1_WIDTH },
131586  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
131587  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_2_WIDTH },
131588  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
131589  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_GROUP_3_WIDTH },
131590 };
131591 
131597 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS] =
131598 {
131599  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
131600  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
131601  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
131602  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
131603  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
131604  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
131605  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
131606  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
131607 };
131608 
131614 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
131615 {
131616  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
131617  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
131618 };
131619 
131625 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
131626 {
131627  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
131628  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_0_WIDTH },
131629  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
131630  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_1_WIDTH },
131631  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
131632  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_2_WIDTH },
131633  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
131634  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_3_WIDTH },
131635  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
131636  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_4_WIDTH },
131637  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
131638  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_5_WIDTH },
131639  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
131640  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_6_WIDTH },
131641  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
131642  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_7_WIDTH },
131643  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
131644  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_8_WIDTH },
131645  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
131646  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_9_WIDTH },
131647  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
131648  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_10_WIDTH },
131649  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
131650  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_11_WIDTH },
131651  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
131652  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_12_WIDTH },
131653  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
131654  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_13_WIDTH },
131655  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
131656  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_GROUP_14_WIDTH },
131657 };
131658 
131664 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_MAX_NUM_CHECKERS] =
131665 {
131666  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
131667  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_0_WIDTH },
131668  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
131669  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_1_WIDTH },
131670  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
131671  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_2_WIDTH },
131672  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
131673  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_GROUP_3_WIDTH },
131674 };
131675 
131681 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS] =
131682 {
131683  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
131684  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
131685  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
131686  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
131687  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
131688  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
131689  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
131690  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
131691 };
131692 
131698 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
131699 {
131700  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
131701  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
131702 };
131703 
131709 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
131710 {
131711  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
131712  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_0_WIDTH },
131713  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
131714  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_1_WIDTH },
131715  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
131716  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_2_WIDTH },
131717  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
131718  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_3_WIDTH },
131719  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
131720  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_4_WIDTH },
131721  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
131722  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_5_WIDTH },
131723  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
131724  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_6_WIDTH },
131725  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
131726  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_7_WIDTH },
131727  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
131728  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_8_WIDTH },
131729  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
131730  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_9_WIDTH },
131731  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
131732  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_10_WIDTH },
131733  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
131734  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_11_WIDTH },
131735  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
131736  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_12_WIDTH },
131737  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
131738  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_13_WIDTH },
131739  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
131740  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_GROUP_14_WIDTH },
131741 };
131742 
131748 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_MAX_NUM_CHECKERS] =
131749 {
131750  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_0_CHECKER_TYPE,
131751  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_0_WIDTH },
131752  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_1_CHECKER_TYPE,
131753  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_1_WIDTH },
131754  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_2_CHECKER_TYPE,
131755  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_2_WIDTH },
131756  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_3_CHECKER_TYPE,
131757  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_GROUP_3_WIDTH },
131758 };
131759 
131765 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_MAX_NUM_CHECKERS] =
131766 {
131767  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
131768  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_0_WIDTH },
131769  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
131770  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_1_WIDTH },
131771  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
131772  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_2_WIDTH },
131773  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
131774  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_3_WIDTH },
131775  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
131776  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_4_WIDTH },
131777  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
131778  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_5_WIDTH },
131779  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
131780  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_6_WIDTH },
131781  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
131782  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_7_WIDTH },
131783  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
131784  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_8_WIDTH },
131785  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
131786  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_9_WIDTH },
131787  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
131788  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_10_WIDTH },
131789  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
131790  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_11_WIDTH },
131791  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
131792  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_12_WIDTH },
131793  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
131794  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_13_WIDTH },
131795  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
131796  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_14_WIDTH },
131797  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
131798  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_15_WIDTH },
131799  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
131800  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_16_WIDTH },
131801  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
131802  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_17_WIDTH },
131803  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
131804  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_18_WIDTH },
131805  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
131806  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_19_WIDTH },
131807  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
131808  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_20_WIDTH },
131809  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
131810  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_21_WIDTH },
131811  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
131812  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_22_WIDTH },
131813  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
131814  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_23_WIDTH },
131815  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
131816  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_24_WIDTH },
131817  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
131818  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_25_WIDTH },
131819  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
131820  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_26_WIDTH },
131821  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
131822  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_27_WIDTH },
131823  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
131824  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_28_WIDTH },
131825  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
131826  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_29_WIDTH },
131827  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
131828  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_30_WIDTH },
131829  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
131830  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_31_WIDTH },
131831  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
131832  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_32_WIDTH },
131833  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
131834  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_33_WIDTH },
131835  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
131836  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_34_WIDTH },
131837  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
131838  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_35_WIDTH },
131839  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
131840  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_36_WIDTH },
131841  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
131842  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_37_WIDTH },
131843  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
131844  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_38_WIDTH },
131845  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
131846  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_39_WIDTH },
131847  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
131848  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_GROUP_40_WIDTH },
131849 };
131850 
131856 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_MAX_NUM_CHECKERS] =
131857 {
131858  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_0_CHECKER_TYPE,
131859  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_0_WIDTH },
131860  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_1_CHECKER_TYPE,
131861  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_1_WIDTH },
131862  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_2_CHECKER_TYPE,
131863  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_2_WIDTH },
131864  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_3_CHECKER_TYPE,
131865  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_GROUP_3_WIDTH },
131866 };
131867 
131873 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_MAX_NUM_CHECKERS] =
131874 {
131875  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
131876  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_0_WIDTH },
131877  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
131878  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_1_WIDTH },
131879  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
131880  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_2_WIDTH },
131881  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
131882  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_3_WIDTH },
131883  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
131884  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_4_WIDTH },
131885  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
131886  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_5_WIDTH },
131887  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
131888  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_6_WIDTH },
131889  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
131890  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_7_WIDTH },
131891  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
131892  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_8_WIDTH },
131893  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
131894  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_9_WIDTH },
131895  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
131896  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_10_WIDTH },
131897  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
131898  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_11_WIDTH },
131899  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
131900  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_12_WIDTH },
131901  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
131902  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_13_WIDTH },
131903  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
131904  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_14_WIDTH },
131905  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
131906  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_15_WIDTH },
131907  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
131908  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_16_WIDTH },
131909  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
131910  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_17_WIDTH },
131911  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
131912  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_18_WIDTH },
131913  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
131914  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_19_WIDTH },
131915  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
131916  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_20_WIDTH },
131917  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
131918  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_21_WIDTH },
131919  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
131920  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_22_WIDTH },
131921  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
131922  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_23_WIDTH },
131923  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
131924  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_24_WIDTH },
131925  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
131926  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_25_WIDTH },
131927  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
131928  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_26_WIDTH },
131929  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
131930  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_27_WIDTH },
131931  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
131932  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_28_WIDTH },
131933  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
131934  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_29_WIDTH },
131935  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
131936  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_30_WIDTH },
131937  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
131938  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_31_WIDTH },
131939  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
131940  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_32_WIDTH },
131941  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
131942  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_33_WIDTH },
131943  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
131944  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_34_WIDTH },
131945  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
131946  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_35_WIDTH },
131947  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
131948  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_36_WIDTH },
131949  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
131950  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_37_WIDTH },
131951  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
131952  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_38_WIDTH },
131953  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
131954  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_39_WIDTH },
131955  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
131956  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_GROUP_40_WIDTH },
131957 };
131958 
131964 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_MAX_NUM_CHECKERS] =
131965 {
131966  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_0_CHECKER_TYPE,
131967  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_0_WIDTH },
131968  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_1_CHECKER_TYPE,
131969  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_1_WIDTH },
131970  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_2_CHECKER_TYPE,
131971  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_2_WIDTH },
131972  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_3_CHECKER_TYPE,
131973  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_GROUP_3_WIDTH },
131974 };
131975 
131981 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_MAX_NUM_CHECKERS] =
131982 {
131983  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
131984  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_0_WIDTH },
131985  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
131986  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_1_WIDTH },
131987  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
131988  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_2_WIDTH },
131989  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
131990  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_3_WIDTH },
131991  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
131992  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_4_WIDTH },
131993  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
131994  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_5_WIDTH },
131995  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
131996  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_6_WIDTH },
131997  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
131998  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_7_WIDTH },
131999  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
132000  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_8_WIDTH },
132001  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
132002  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_9_WIDTH },
132003  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
132004  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_10_WIDTH },
132005  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
132006  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_11_WIDTH },
132007  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
132008  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_12_WIDTH },
132009  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
132010  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_13_WIDTH },
132011  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
132012  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_14_WIDTH },
132013  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
132014  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_15_WIDTH },
132015  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
132016  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_16_WIDTH },
132017  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
132018  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_17_WIDTH },
132019  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
132020  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_18_WIDTH },
132021  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
132022  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_19_WIDTH },
132023  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
132024  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_20_WIDTH },
132025  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
132026  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_21_WIDTH },
132027  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
132028  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_22_WIDTH },
132029  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
132030  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_23_WIDTH },
132031  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
132032  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_24_WIDTH },
132033  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
132034  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_25_WIDTH },
132035  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
132036  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_26_WIDTH },
132037  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
132038  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_27_WIDTH },
132039  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
132040  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_28_WIDTH },
132041  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
132042  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_29_WIDTH },
132043  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
132044  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_30_WIDTH },
132045  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
132046  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_31_WIDTH },
132047  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
132048  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_32_WIDTH },
132049  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
132050  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_33_WIDTH },
132051  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
132052  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_34_WIDTH },
132053  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
132054  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_35_WIDTH },
132055  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
132056  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_36_WIDTH },
132057  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
132058  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_37_WIDTH },
132059  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
132060  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_38_WIDTH },
132061  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
132062  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_39_WIDTH },
132063  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
132064  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_GROUP_40_WIDTH },
132065 };
132066 
132072 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_MAX_NUM_CHECKERS] =
132073 {
132074  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
132075  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_0_WIDTH },
132076  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
132077  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_1_WIDTH },
132078  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
132079  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_2_WIDTH },
132080  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
132081  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_GROUP_3_WIDTH },
132082 };
132083 
132089 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_MAX_NUM_CHECKERS] =
132090 {
132091  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
132092  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_0_WIDTH },
132093  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
132094  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_1_WIDTH },
132095  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
132096  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_2_WIDTH },
132097  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
132098  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_GROUP_3_WIDTH },
132099 };
132100 
132106 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_MAX_NUM_CHECKERS] =
132107 {
132108  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
132109  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_0_WIDTH },
132110  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
132111  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_1_WIDTH },
132112  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
132113  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_2_WIDTH },
132114  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
132115  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_GROUP_3_WIDTH },
132116 };
132117 
132123 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_MAX_NUM_CHECKERS] =
132124 {
132125  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
132126  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_0_WIDTH },
132127  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
132128  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_1_WIDTH },
132129  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
132130  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_2_WIDTH },
132131  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
132132  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_GROUP_3_WIDTH },
132133 };
132134 
132140 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS] =
132141 {
132142  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
132143  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_0_WIDTH },
132144  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
132145  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_1_WIDTH },
132146  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
132147  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_2_WIDTH },
132148  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
132149  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_GROUP_3_WIDTH },
132150 };
132151 
132157 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
132158 {
132159  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
132160  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
132161 };
132162 
132168 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS] =
132169 {
132170  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
132171  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
132172  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
132173  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
132174  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
132175  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
132176  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
132177  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
132178 };
132179 
132185 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
132186 {
132187  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
132188  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_0_WIDTH },
132189  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
132190  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_1_WIDTH },
132191  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
132192  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_2_WIDTH },
132193  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
132194  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_3_WIDTH },
132195  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
132196  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_4_WIDTH },
132197  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
132198  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_5_WIDTH },
132199  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
132200  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_6_WIDTH },
132201  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
132202  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_7_WIDTH },
132203  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
132204  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_8_WIDTH },
132205  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
132206  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_9_WIDTH },
132207  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
132208  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_10_WIDTH },
132209  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
132210  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_11_WIDTH },
132211  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
132212  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_12_WIDTH },
132213  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
132214  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_13_WIDTH },
132215  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
132216  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_GROUP_14_WIDTH },
132217 };
132218 
132224 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
132225 {
132226  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
132227  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
132228 };
132229 
132235 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
132236 {
132237  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
132238  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_GROUP_0_WIDTH },
132239 };
132240 
132246 static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
132247 {
132248  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132249  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
132250  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132251  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
132252  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132253  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
132254  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132255  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
132256  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132257  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
132258  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132259  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
132260 };
132261 
132266 static const SDL_MemConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
132267 {
132268  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
132269  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
132270  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
132271  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
132272  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
132273  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
132274  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
132275  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
132276  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
132277  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
132278  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
132279  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
132280  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
132281  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
132282  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)true) },
132283  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
132284  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
132285  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)true) },
132286  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
132287  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
132288  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)true) },
132289  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
132290  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
132291  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)true) },
132292  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
132293  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
132294  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
132295  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
132296  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
132297  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
132298  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
132299  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
132300  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
132301  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
132302  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
132303  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
132304  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
132305  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
132306  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
132307  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
132308  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
132309  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)true) },
132310  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
132311  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
132312  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)true) },
132313  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
132314  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
132315  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)true) },
132316  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
132317  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
132318  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)true) },
132319  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
132320  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
132321  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)true) },
132322  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
132323  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
132324  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)true) },
132325  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
132326  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
132327  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)true) },
132328  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
132329  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
132330  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)true) },
132331  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0u,
132332  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
132333  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
132334  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0u,
132335  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
132336  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
132337  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0u,
132338  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
132339  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
132340  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0u,
132341  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
132342  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
132343  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0u,
132344  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
132345  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
132346  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0u,
132347  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
132348  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
132349  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0u,
132350  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
132351  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)false) },
132352 };
132353 
132359 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS] =
132360 {
132361  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132362  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_0_WIDTH },
132363  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132364  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_1_WIDTH },
132365  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132366  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_2_WIDTH },
132367  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132368  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_3_WIDTH },
132369  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132370  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_4_WIDTH },
132371  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132372  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_5_WIDTH },
132373  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
132374  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_6_WIDTH },
132375  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
132376  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_7_WIDTH },
132377  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
132378  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_8_WIDTH },
132379  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
132380  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_9_WIDTH },
132381  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
132382  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_10_WIDTH },
132383  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
132384  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_11_WIDTH },
132385  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
132386  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_12_WIDTH },
132387  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_13_CHECKER_TYPE,
132388  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_13_WIDTH },
132389  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_14_CHECKER_TYPE,
132390  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_14_WIDTH },
132391  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_15_CHECKER_TYPE,
132392  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_15_WIDTH },
132393  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_16_CHECKER_TYPE,
132394  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_16_WIDTH },
132395  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_17_CHECKER_TYPE,
132396  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_17_WIDTH },
132397  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_18_CHECKER_TYPE,
132398  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_18_WIDTH },
132399  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_19_CHECKER_TYPE,
132400  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_19_WIDTH },
132401  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_20_CHECKER_TYPE,
132402  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_20_WIDTH },
132403  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_21_CHECKER_TYPE,
132404  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_21_WIDTH },
132405  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_22_CHECKER_TYPE,
132406  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_22_WIDTH },
132407  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_23_CHECKER_TYPE,
132408  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_23_WIDTH },
132409  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_24_CHECKER_TYPE,
132410  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_24_WIDTH },
132411  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_25_CHECKER_TYPE,
132412  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_25_WIDTH },
132413  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_26_CHECKER_TYPE,
132414  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_26_WIDTH },
132415  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_27_CHECKER_TYPE,
132416  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_27_WIDTH },
132417  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_28_CHECKER_TYPE,
132418  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_28_WIDTH },
132419  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_29_CHECKER_TYPE,
132420  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_29_WIDTH },
132421  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_30_CHECKER_TYPE,
132422  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_30_WIDTH },
132423  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_31_CHECKER_TYPE,
132424  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_31_WIDTH },
132425  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_32_CHECKER_TYPE,
132426  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_32_WIDTH },
132427  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_33_CHECKER_TYPE,
132428  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_33_WIDTH },
132429  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_34_CHECKER_TYPE,
132430  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_34_WIDTH },
132431  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_35_CHECKER_TYPE,
132432  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_35_WIDTH },
132433  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_36_CHECKER_TYPE,
132434  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_36_WIDTH },
132435  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_37_CHECKER_TYPE,
132436  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_37_WIDTH },
132437  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_38_CHECKER_TYPE,
132438  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_38_WIDTH },
132439  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_39_CHECKER_TYPE,
132440  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_39_WIDTH },
132441  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_40_CHECKER_TYPE,
132442  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_40_WIDTH },
132443  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_41_CHECKER_TYPE,
132444  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_41_WIDTH },
132445  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_42_CHECKER_TYPE,
132446  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_42_WIDTH },
132447  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_43_CHECKER_TYPE,
132448  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_43_WIDTH },
132449  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_44_CHECKER_TYPE,
132450  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_44_WIDTH },
132451  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_45_CHECKER_TYPE,
132452  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_45_WIDTH },
132453  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_46_CHECKER_TYPE,
132454  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_46_WIDTH },
132455  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_47_CHECKER_TYPE,
132456  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_47_WIDTH },
132457  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_48_CHECKER_TYPE,
132458  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_GROUP_48_WIDTH },
132459 };
132460 
132466 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
132467 {
132468  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132469  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
132470  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132471  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
132472  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132473  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
132474  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132475  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
132476  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132477  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
132478  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132479  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
132480  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
132481  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
132482  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
132483  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
132484  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
132485  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
132486  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
132487  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
132488  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
132489  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
132490  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
132491  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
132492  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
132493  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
132494  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
132495  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
132496  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
132497  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
132498  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
132499  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
132500  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
132501  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
132502  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
132503  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
132504  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
132505  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
132506  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
132507  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
132508  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
132509  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
132510  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
132511  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
132512  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
132513  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
132514  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
132515  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
132516  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
132517  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
132518  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
132519  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
132520  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
132521  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
132522  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
132523  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
132524  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
132525  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
132526  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
132527  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
132528  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
132529  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
132530 };
132531 
132537 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
132538 {
132539  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132540  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
132541  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132542  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
132543  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132544  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
132545  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132546  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
132547  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132548  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
132549  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132550  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
132551  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
132552  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
132553  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
132554  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
132555  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
132556  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
132557  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
132558  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
132559  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
132560  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
132561  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
132562  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
132563  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
132564  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
132565  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
132566  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
132567  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
132568  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
132569  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_CHECKER_TYPE,
132570  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_15_WIDTH },
132571 };
132572 
132578 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS] =
132579 {
132580  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132581  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_0_WIDTH },
132582  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132583  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_1_WIDTH },
132584  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132585  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_2_WIDTH },
132586  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132587  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_3_WIDTH },
132588  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132589  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_4_WIDTH },
132590  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132591  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_5_WIDTH },
132592  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_CHECKER_TYPE,
132593  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_6_WIDTH },
132594  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_CHECKER_TYPE,
132595  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_7_WIDTH },
132596  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_CHECKER_TYPE,
132597  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_8_WIDTH },
132598  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_CHECKER_TYPE,
132599  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_9_WIDTH },
132600  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_CHECKER_TYPE,
132601  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_10_WIDTH },
132602  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_CHECKER_TYPE,
132603  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_11_WIDTH },
132604  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_CHECKER_TYPE,
132605  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_12_WIDTH },
132606  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_CHECKER_TYPE,
132607  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_13_WIDTH },
132608  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_CHECKER_TYPE,
132609  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_14_WIDTH },
132610  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_CHECKER_TYPE,
132611  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_15_WIDTH },
132612  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_CHECKER_TYPE,
132613  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_16_WIDTH },
132614  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_CHECKER_TYPE,
132615  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_17_WIDTH },
132616  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_CHECKER_TYPE,
132617  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_18_WIDTH },
132618  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_CHECKER_TYPE,
132619  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_19_WIDTH },
132620  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_CHECKER_TYPE,
132621  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_20_WIDTH },
132622  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_CHECKER_TYPE,
132623  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_21_WIDTH },
132624  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_CHECKER_TYPE,
132625  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_22_WIDTH },
132626  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_CHECKER_TYPE,
132627  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_23_WIDTH },
132628  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_CHECKER_TYPE,
132629  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_24_WIDTH },
132630  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_CHECKER_TYPE,
132631  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_25_WIDTH },
132632  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_CHECKER_TYPE,
132633  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_26_WIDTH },
132634  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_CHECKER_TYPE,
132635  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_27_WIDTH },
132636  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_CHECKER_TYPE,
132637  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_28_WIDTH },
132638  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_CHECKER_TYPE,
132639  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_29_WIDTH },
132640  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_CHECKER_TYPE,
132641  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_GROUP_30_WIDTH },
132642 };
132643 
132649 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS] =
132650 {
132651  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132652  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_0_WIDTH },
132653  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132654  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_1_WIDTH },
132655  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132656  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_2_WIDTH },
132657  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132658  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_3_WIDTH },
132659  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132660  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_4_WIDTH },
132661  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132662  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_5_WIDTH },
132663  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_CHECKER_TYPE,
132664  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_6_WIDTH },
132665  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_CHECKER_TYPE,
132666  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_7_WIDTH },
132667  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_CHECKER_TYPE,
132668  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_8_WIDTH },
132669  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_CHECKER_TYPE,
132670  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_9_WIDTH },
132671  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_CHECKER_TYPE,
132672  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_10_WIDTH },
132673  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_CHECKER_TYPE,
132674  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_11_WIDTH },
132675  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_CHECKER_TYPE,
132676  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_12_WIDTH },
132677  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_CHECKER_TYPE,
132678  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_13_WIDTH },
132679  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_CHECKER_TYPE,
132680  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_GROUP_14_WIDTH },
132681 };
132682 
132688 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS] =
132689 {
132690  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132691  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_0_WIDTH },
132692  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132693  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_1_WIDTH },
132694  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132695  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_2_WIDTH },
132696  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132697  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_3_WIDTH },
132698  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132699  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_4_WIDTH },
132700  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132701  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_5_WIDTH },
132702  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_CHECKER_TYPE,
132703  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_6_WIDTH },
132704  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_CHECKER_TYPE,
132705  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_7_WIDTH },
132706  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_CHECKER_TYPE,
132707  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_8_WIDTH },
132708  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_CHECKER_TYPE,
132709  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_9_WIDTH },
132710  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_CHECKER_TYPE,
132711  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_10_WIDTH },
132712  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_CHECKER_TYPE,
132713  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_11_WIDTH },
132714  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_CHECKER_TYPE,
132715  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_GROUP_12_WIDTH },
132716 };
132717 
132723 static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS] =
132724 {
132725  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132726  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
132727  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132728  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
132729  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132730  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
132731  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132732  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
132733  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132734  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
132735  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132736  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
132737 };
132738 
132743 static const SDL_MemConfig_t SDL_MCU_CBASS_ECC_AGGR0_MemEntries[SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES] =
132744 {
132745  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_ID, 0u,
132746  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_SIZE, 4u,
132747  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
132748  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_ID, 0u,
132749  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_SIZE, 4u,
132750  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
132751  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_ID, 0u,
132752  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_SIZE, 4u,
132753  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ROW_WIDTH, ((bool)false) },
132754  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_ID, 0u,
132755  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_SIZE, 4u,
132756  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ROW_WIDTH, ((bool)false) },
132757  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_RAM_ID, 0u,
132758  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_RAM_SIZE, 4u,
132759  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_ROW_WIDTH, ((bool)false) },
132760  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_RAM_ID, 0u,
132761  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_RAM_SIZE, 4u,
132762  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_ROW_WIDTH, ((bool)false) },
132763 };
132764 
132770 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS] =
132771 {
132772  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_0_CHECKER_TYPE,
132773  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_0_WIDTH },
132774  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_1_CHECKER_TYPE,
132775  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_1_WIDTH },
132776  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_2_CHECKER_TYPE,
132777  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_2_WIDTH },
132778  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_3_CHECKER_TYPE,
132779  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_3_WIDTH },
132780  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_4_CHECKER_TYPE,
132781  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_4_WIDTH },
132782  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_5_CHECKER_TYPE,
132783  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_5_WIDTH },
132784  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_6_CHECKER_TYPE,
132785  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_6_WIDTH },
132786  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_7_CHECKER_TYPE,
132787  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_7_WIDTH },
132788  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_8_CHECKER_TYPE,
132789  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_8_WIDTH },
132790  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_9_CHECKER_TYPE,
132791  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_9_WIDTH },
132792  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_10_CHECKER_TYPE,
132793  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_10_WIDTH },
132794  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_11_CHECKER_TYPE,
132795  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_11_WIDTH },
132796  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_12_CHECKER_TYPE,
132797  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_12_WIDTH },
132798  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_13_CHECKER_TYPE,
132799  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_13_WIDTH },
132800  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_14_CHECKER_TYPE,
132801  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_14_WIDTH },
132802  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_15_CHECKER_TYPE,
132803  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_15_WIDTH },
132804  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_16_CHECKER_TYPE,
132805  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_16_WIDTH },
132806  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_17_CHECKER_TYPE,
132807  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_17_WIDTH },
132808  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_18_CHECKER_TYPE,
132809  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_18_WIDTH },
132810  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_19_CHECKER_TYPE,
132811  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_19_WIDTH },
132812  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_20_CHECKER_TYPE,
132813  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_20_WIDTH },
132814  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_21_CHECKER_TYPE,
132815  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_21_WIDTH },
132816  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_22_CHECKER_TYPE,
132817  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_22_WIDTH },
132818  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_23_CHECKER_TYPE,
132819  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_23_WIDTH },
132820  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_24_CHECKER_TYPE,
132821  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_24_WIDTH },
132822  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_25_CHECKER_TYPE,
132823  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_25_WIDTH },
132824  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_26_CHECKER_TYPE,
132825  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_26_WIDTH },
132826  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_27_CHECKER_TYPE,
132827  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_27_WIDTH },
132828  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_28_CHECKER_TYPE,
132829  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_28_WIDTH },
132830  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_29_CHECKER_TYPE,
132831  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_29_WIDTH },
132832  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_30_CHECKER_TYPE,
132833  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_30_WIDTH },
132834  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_31_CHECKER_TYPE,
132835  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_31_WIDTH },
132836  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_32_CHECKER_TYPE,
132837  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_32_WIDTH },
132838  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_33_CHECKER_TYPE,
132839  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_33_WIDTH },
132840  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_34_CHECKER_TYPE,
132841  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_34_WIDTH },
132842  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_35_CHECKER_TYPE,
132843  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_35_WIDTH },
132844  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_36_CHECKER_TYPE,
132845  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_36_WIDTH },
132846  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_37_CHECKER_TYPE,
132847  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_37_WIDTH },
132848  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_38_CHECKER_TYPE,
132849  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_38_WIDTH },
132850  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_39_CHECKER_TYPE,
132851  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_39_WIDTH },
132852  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_40_CHECKER_TYPE,
132853  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_40_WIDTH },
132854  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_41_CHECKER_TYPE,
132855  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_41_WIDTH },
132856  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_42_CHECKER_TYPE,
132857  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_42_WIDTH },
132858  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_43_CHECKER_TYPE,
132859  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_43_WIDTH },
132860  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_44_CHECKER_TYPE,
132861  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_44_WIDTH },
132862  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_45_CHECKER_TYPE,
132863  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_45_WIDTH },
132864  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_46_CHECKER_TYPE,
132865  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_46_WIDTH },
132866  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_47_CHECKER_TYPE,
132867  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_47_WIDTH },
132868  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_48_CHECKER_TYPE,
132869  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_48_WIDTH },
132870  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_49_CHECKER_TYPE,
132871  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_49_WIDTH },
132872  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_50_CHECKER_TYPE,
132873  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_50_WIDTH },
132874  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_51_CHECKER_TYPE,
132875  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_51_WIDTH },
132876  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_52_CHECKER_TYPE,
132877  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_GROUP_52_WIDTH },
132878 };
132879 
132885 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS] =
132886 {
132887  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
132888  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
132889  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
132890  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
132891  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
132892  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
132893  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
132894  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
132895 };
132896 
132902 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS] =
132903 {
132904  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
132905  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_WIDTH },
132906  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
132907  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_WIDTH },
132908  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
132909  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_WIDTH },
132910  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
132911  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_WIDTH },
132912  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_4_CHECKER_TYPE,
132913  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_4_WIDTH },
132914  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_5_CHECKER_TYPE,
132915  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_5_WIDTH },
132916  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_6_CHECKER_TYPE,
132917  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_6_WIDTH },
132918  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_7_CHECKER_TYPE,
132919  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_7_WIDTH },
132920  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_8_CHECKER_TYPE,
132921  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_8_WIDTH },
132922  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_9_CHECKER_TYPE,
132923  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_9_WIDTH },
132924  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_10_CHECKER_TYPE,
132925  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_10_WIDTH },
132926  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_11_CHECKER_TYPE,
132927  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_11_WIDTH },
132928  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_12_CHECKER_TYPE,
132929  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_12_WIDTH },
132930  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_13_CHECKER_TYPE,
132931  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_13_WIDTH },
132932  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_14_CHECKER_TYPE,
132933  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_14_WIDTH },
132934  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_15_CHECKER_TYPE,
132935  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_15_WIDTH },
132936  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_16_CHECKER_TYPE,
132937  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_16_WIDTH },
132938  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_17_CHECKER_TYPE,
132939  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_17_WIDTH },
132940  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_18_CHECKER_TYPE,
132941  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_18_WIDTH },
132942  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_19_CHECKER_TYPE,
132943  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_19_WIDTH },
132944  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_20_CHECKER_TYPE,
132945  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_20_WIDTH },
132946  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_21_CHECKER_TYPE,
132947  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_21_WIDTH },
132948  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_22_CHECKER_TYPE,
132949  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_22_WIDTH },
132950  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_23_CHECKER_TYPE,
132951  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_23_WIDTH },
132952  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_24_CHECKER_TYPE,
132953  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_24_WIDTH },
132954  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_25_CHECKER_TYPE,
132955  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_25_WIDTH },
132956  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_26_CHECKER_TYPE,
132957  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_26_WIDTH },
132958  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_27_CHECKER_TYPE,
132959  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_27_WIDTH },
132960  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_28_CHECKER_TYPE,
132961  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_28_WIDTH },
132962  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_29_CHECKER_TYPE,
132963  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_29_WIDTH },
132964  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_30_CHECKER_TYPE,
132965  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_30_WIDTH },
132966  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_31_CHECKER_TYPE,
132967  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_31_WIDTH },
132968  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_32_CHECKER_TYPE,
132969  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_32_WIDTH },
132970  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_33_CHECKER_TYPE,
132971  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_33_WIDTH },
132972  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_34_CHECKER_TYPE,
132973  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_34_WIDTH },
132974  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_35_CHECKER_TYPE,
132975  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_35_WIDTH },
132976  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_36_CHECKER_TYPE,
132977  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_36_WIDTH },
132978  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_37_CHECKER_TYPE,
132979  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_37_WIDTH },
132980  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_38_CHECKER_TYPE,
132981  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_38_WIDTH },
132982  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_39_CHECKER_TYPE,
132983  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_39_WIDTH },
132984  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_40_CHECKER_TYPE,
132985  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_GROUP_40_WIDTH },
132986 };
132987 
132993 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
132994 {
132995  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
132996  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
132997 };
132998 
133004 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
133005 {
133006  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
133007  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_0_WIDTH },
133008  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
133009  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_1_WIDTH },
133010  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
133011  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_2_WIDTH },
133012  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
133013  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_3_WIDTH },
133014  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
133015  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_4_WIDTH },
133016  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
133017  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_5_WIDTH },
133018  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
133019  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_6_WIDTH },
133020  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
133021  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_7_WIDTH },
133022  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
133023  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_8_WIDTH },
133024  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
133025  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_9_WIDTH },
133026  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
133027  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_10_WIDTH },
133028  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
133029  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_11_WIDTH },
133030  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
133031  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_12_WIDTH },
133032  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
133033  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_13_WIDTH },
133034  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
133035  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_14_WIDTH },
133036 };
133037 
133043 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS] =
133044 {
133045  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_CHECKER_TYPE,
133046  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_0_WIDTH },
133047  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_CHECKER_TYPE,
133048  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_1_WIDTH },
133049  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_CHECKER_TYPE,
133050  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_2_WIDTH },
133051  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_CHECKER_TYPE,
133052  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_GROUP_3_WIDTH },
133053 };
133054 
133060 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS] =
133061 {
133062  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_0_CHECKER_TYPE,
133063  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_0_WIDTH },
133064  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_1_CHECKER_TYPE,
133065  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_1_WIDTH },
133066  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_2_CHECKER_TYPE,
133067  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_2_WIDTH },
133068  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_3_CHECKER_TYPE,
133069  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_3_WIDTH },
133070  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_4_CHECKER_TYPE,
133071  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_4_WIDTH },
133072  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_5_CHECKER_TYPE,
133073  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_5_WIDTH },
133074  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_6_CHECKER_TYPE,
133075  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_6_WIDTH },
133076  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_7_CHECKER_TYPE,
133077  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_7_WIDTH },
133078  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_8_CHECKER_TYPE,
133079  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_8_WIDTH },
133080  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_9_CHECKER_TYPE,
133081  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_9_WIDTH },
133082  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_10_CHECKER_TYPE,
133083  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_10_WIDTH },
133084  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_11_CHECKER_TYPE,
133085  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_11_WIDTH },
133086  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_12_CHECKER_TYPE,
133087  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_12_WIDTH },
133088  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_13_CHECKER_TYPE,
133089  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_13_WIDTH },
133090  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_14_CHECKER_TYPE,
133091  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_14_WIDTH },
133092  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_15_CHECKER_TYPE,
133093  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_15_WIDTH },
133094  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_16_CHECKER_TYPE,
133095  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_16_WIDTH },
133096  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_17_CHECKER_TYPE,
133097  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_17_WIDTH },
133098  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_18_CHECKER_TYPE,
133099  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_18_WIDTH },
133100  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_19_CHECKER_TYPE,
133101  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_19_WIDTH },
133102  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_20_CHECKER_TYPE,
133103  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_20_WIDTH },
133104  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_21_CHECKER_TYPE,
133105  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_21_WIDTH },
133106  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_22_CHECKER_TYPE,
133107  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_22_WIDTH },
133108  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_23_CHECKER_TYPE,
133109  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_23_WIDTH },
133110  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_24_CHECKER_TYPE,
133111  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_24_WIDTH },
133112  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_25_CHECKER_TYPE,
133113  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_25_WIDTH },
133114  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_26_CHECKER_TYPE,
133115  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_26_WIDTH },
133116  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_27_CHECKER_TYPE,
133117  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_27_WIDTH },
133118  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_28_CHECKER_TYPE,
133119  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_28_WIDTH },
133120  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_29_CHECKER_TYPE,
133121  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_29_WIDTH },
133122  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_30_CHECKER_TYPE,
133123  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_30_WIDTH },
133124  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_31_CHECKER_TYPE,
133125  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_31_WIDTH },
133126  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_32_CHECKER_TYPE,
133127  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_32_WIDTH },
133128  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_33_CHECKER_TYPE,
133129  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_33_WIDTH },
133130  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_34_CHECKER_TYPE,
133131  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_34_WIDTH },
133132  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_35_CHECKER_TYPE,
133133  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_35_WIDTH },
133134  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_36_CHECKER_TYPE,
133135  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_36_WIDTH },
133136  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_37_CHECKER_TYPE,
133137  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_37_WIDTH },
133138  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_38_CHECKER_TYPE,
133139  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_38_WIDTH },
133140  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_39_CHECKER_TYPE,
133141  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_39_WIDTH },
133142  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_40_CHECKER_TYPE,
133143  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_GROUP_40_WIDTH },
133144 };
133145 
133151 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS] =
133152 {
133153  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
133154  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_0_WIDTH },
133155  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
133156  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_1_WIDTH },
133157  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
133158  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_2_WIDTH },
133159  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
133160  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_GROUP_3_WIDTH },
133161 };
133162 
133168 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS] =
133169 {
133170  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_0_CHECKER_TYPE,
133171  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_0_WIDTH },
133172  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_1_CHECKER_TYPE,
133173  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_1_WIDTH },
133174  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_2_CHECKER_TYPE,
133175  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_2_WIDTH },
133176  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_3_CHECKER_TYPE,
133177  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_3_WIDTH },
133178  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_4_CHECKER_TYPE,
133179  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_4_WIDTH },
133180  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_5_CHECKER_TYPE,
133181  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_5_WIDTH },
133182  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_6_CHECKER_TYPE,
133183  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_6_WIDTH },
133184  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_7_CHECKER_TYPE,
133185  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_7_WIDTH },
133186  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_8_CHECKER_TYPE,
133187  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_8_WIDTH },
133188  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_9_CHECKER_TYPE,
133189  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_9_WIDTH },
133190  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_10_CHECKER_TYPE,
133191  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_10_WIDTH },
133192  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_11_CHECKER_TYPE,
133193  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_11_WIDTH },
133194  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_12_CHECKER_TYPE,
133195  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_12_WIDTH },
133196  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_13_CHECKER_TYPE,
133197  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_13_WIDTH },
133198  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_14_CHECKER_TYPE,
133199  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_14_WIDTH },
133200  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_15_CHECKER_TYPE,
133201  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_15_WIDTH },
133202  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_16_CHECKER_TYPE,
133203  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_16_WIDTH },
133204  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_17_CHECKER_TYPE,
133205  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_17_WIDTH },
133206  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_18_CHECKER_TYPE,
133207  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_18_WIDTH },
133208  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_19_CHECKER_TYPE,
133209  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_19_WIDTH },
133210  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_20_CHECKER_TYPE,
133211  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_20_WIDTH },
133212  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_21_CHECKER_TYPE,
133213  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_21_WIDTH },
133214  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_22_CHECKER_TYPE,
133215  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_22_WIDTH },
133216  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_23_CHECKER_TYPE,
133217  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_23_WIDTH },
133218  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_24_CHECKER_TYPE,
133219  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_24_WIDTH },
133220  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_25_CHECKER_TYPE,
133221  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_25_WIDTH },
133222  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_26_CHECKER_TYPE,
133223  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_26_WIDTH },
133224  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_27_CHECKER_TYPE,
133225  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_27_WIDTH },
133226  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_28_CHECKER_TYPE,
133227  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_28_WIDTH },
133228  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_29_CHECKER_TYPE,
133229  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_29_WIDTH },
133230  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_30_CHECKER_TYPE,
133231  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_30_WIDTH },
133232  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_31_CHECKER_TYPE,
133233  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_31_WIDTH },
133234  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_32_CHECKER_TYPE,
133235  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_32_WIDTH },
133236  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_33_CHECKER_TYPE,
133237  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_33_WIDTH },
133238  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_34_CHECKER_TYPE,
133239  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_34_WIDTH },
133240  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_35_CHECKER_TYPE,
133241  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_35_WIDTH },
133242  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_36_CHECKER_TYPE,
133243  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_36_WIDTH },
133244  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_37_CHECKER_TYPE,
133245  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_37_WIDTH },
133246  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_38_CHECKER_TYPE,
133247  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_38_WIDTH },
133248  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_39_CHECKER_TYPE,
133249  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_39_WIDTH },
133250  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_40_CHECKER_TYPE,
133251  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_40_WIDTH },
133252  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_41_CHECKER_TYPE,
133253  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_41_WIDTH },
133254  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_42_CHECKER_TYPE,
133255  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_42_WIDTH },
133256  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_43_CHECKER_TYPE,
133257  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_43_WIDTH },
133258  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_44_CHECKER_TYPE,
133259  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_44_WIDTH },
133260  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_45_CHECKER_TYPE,
133261  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_45_WIDTH },
133262  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_46_CHECKER_TYPE,
133263  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_46_WIDTH },
133264  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_47_CHECKER_TYPE,
133265  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_47_WIDTH },
133266  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_48_CHECKER_TYPE,
133267  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_48_WIDTH },
133268  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_49_CHECKER_TYPE,
133269  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_49_WIDTH },
133270  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_50_CHECKER_TYPE,
133271  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_50_WIDTH },
133272  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_51_CHECKER_TYPE,
133273  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_51_WIDTH },
133274  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_52_CHECKER_TYPE,
133275  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_GROUP_52_WIDTH },
133276 };
133277 
133283 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS] =
133284 {
133285  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_CHECKER_TYPE,
133286  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_0_WIDTH },
133287  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_CHECKER_TYPE,
133288  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_1_WIDTH },
133289  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_CHECKER_TYPE,
133290  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_2_WIDTH },
133291  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_CHECKER_TYPE,
133292  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_GROUP_3_WIDTH },
133293 };
133294 
133300 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS] =
133301 {
133302  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_CHECKER_TYPE,
133303  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_0_WIDTH },
133304  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_CHECKER_TYPE,
133305  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_1_WIDTH },
133306  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_CHECKER_TYPE,
133307  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_2_WIDTH },
133308  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_CHECKER_TYPE,
133309  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_3_WIDTH },
133310  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_4_CHECKER_TYPE,
133311  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_4_WIDTH },
133312  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_5_CHECKER_TYPE,
133313  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_5_WIDTH },
133314  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_6_CHECKER_TYPE,
133315  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_6_WIDTH },
133316  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_7_CHECKER_TYPE,
133317  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_7_WIDTH },
133318  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_8_CHECKER_TYPE,
133319  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_8_WIDTH },
133320  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_9_CHECKER_TYPE,
133321  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_9_WIDTH },
133322  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_10_CHECKER_TYPE,
133323  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_10_WIDTH },
133324  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_11_CHECKER_TYPE,
133325  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_11_WIDTH },
133326  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_12_CHECKER_TYPE,
133327  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_12_WIDTH },
133328  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_13_CHECKER_TYPE,
133329  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_13_WIDTH },
133330  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_14_CHECKER_TYPE,
133331  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_GROUP_14_WIDTH },
133332 };
133333 
133339 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS] =
133340 {
133341  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_CHECKER_TYPE,
133342  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_GROUP_0_WIDTH },
133343 };
133344 
133350 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS] =
133351 {
133352  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
133353  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_0_WIDTH },
133354  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
133355  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_1_WIDTH },
133356  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
133357  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_2_WIDTH },
133358  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
133359  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_3_WIDTH },
133360  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
133361  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_4_WIDTH },
133362  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
133363  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_5_WIDTH },
133364  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
133365  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_6_WIDTH },
133366  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
133367  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_7_WIDTH },
133368  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
133369  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_8_WIDTH },
133370  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
133371  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_9_WIDTH },
133372  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
133373  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_10_WIDTH },
133374  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
133375  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_11_WIDTH },
133376  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
133377  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_12_WIDTH },
133378  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
133379  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_13_WIDTH },
133380  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
133381  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_GROUP_14_WIDTH },
133382 };
133383 
133389 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
133390 {
133391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
133392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
133393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
133394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
133395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
133396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
133397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
133398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
133399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
133400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
133401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
133402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
133403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
133404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
133405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
133406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
133407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
133408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
133409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
133410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
133411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
133412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
133413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
133414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
133415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
133416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
133417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
133418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
133419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
133420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
133421 };
133422 
133428 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
133429 {
133430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
133431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
133432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
133433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
133434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
133435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
133436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
133437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
133438 };
133439 
133445 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
133446 {
133447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
133448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
133449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
133450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
133451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
133452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
133453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
133454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
133455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
133456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
133457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
133458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
133459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
133460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
133461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
133462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
133463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
133464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
133465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
133466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
133467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
133468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
133469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
133470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
133471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
133472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
133473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
133474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
133475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
133476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
133477 };
133478 
133484 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
133485 {
133486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
133487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
133488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
133489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
133490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
133491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
133492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
133493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
133494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
133495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
133496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
133497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
133498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
133499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
133500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_7_CHECKER_TYPE,
133501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_7_WIDTH },
133502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_8_CHECKER_TYPE,
133503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_8_WIDTH },
133504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_9_CHECKER_TYPE,
133505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_9_WIDTH },
133506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_10_CHECKER_TYPE,
133507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_10_WIDTH },
133508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_11_CHECKER_TYPE,
133509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_11_WIDTH },
133510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_12_CHECKER_TYPE,
133511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_12_WIDTH },
133512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_13_CHECKER_TYPE,
133513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_GROUP_13_WIDTH },
133514 };
133515 
133521 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
133522 {
133523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
133524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
133525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
133526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
133527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
133528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
133529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
133530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
133531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
133532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
133533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
133534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
133535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
133536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
133537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
133538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
133539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
133540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
133541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
133542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
133543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
133544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
133545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
133546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
133547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
133548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
133549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
133550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
133551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
133552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
133553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
133554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
133555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
133556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
133557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
133558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
133559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
133560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
133561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
133562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
133563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
133564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
133565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
133566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
133567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
133568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
133569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
133570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
133571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
133572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
133573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
133574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
133575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
133576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
133577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
133578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
133579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
133580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
133581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
133582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
133583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
133584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
133585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
133586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
133587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
133588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
133589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
133590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
133591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
133592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
133593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
133594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
133595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
133596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
133597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
133598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
133599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
133600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
133601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
133602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
133603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
133604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
133605 };
133606 
133612 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
133613 {
133614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
133615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
133616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
133617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
133618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
133619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
133620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
133621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
133622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
133623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
133624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
133625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
133626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
133627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
133628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
133629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
133630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
133631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
133632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
133633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
133634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
133635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
133636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
133637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
133638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
133639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
133640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
133641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
133642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
133643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
133644 };
133645 
133651 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
133652 {
133653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
133654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
133655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
133656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
133657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
133658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
133659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
133660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
133661 };
133662 
133668 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
133669 {
133670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
133671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
133672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
133673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
133674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
133675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
133676 };
133677 
133683 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
133684 {
133685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
133686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
133687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
133688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
133689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
133690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
133691 };
133692 
133698 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
133699 {
133700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
133701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
133702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
133703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
133704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
133705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
133706 };
133707 
133713 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
133714 {
133715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
133716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
133717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
133718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
133719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
133720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
133721 };
133722 
133728 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
133729 {
133730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
133731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
133732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
133733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
133734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
133735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
133736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
133737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
133738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
133739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
133740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
133741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
133742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
133743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
133744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
133745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
133746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
133747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
133748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
133749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
133750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
133751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
133752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
133753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
133754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
133755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
133756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
133757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
133758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
133759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
133760 };
133761 
133767 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
133768 {
133769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
133770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
133771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
133772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
133773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
133774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
133775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
133776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
133777 };
133778 
133784 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
133785 {
133786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
133787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
133788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
133789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
133790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
133791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
133792 };
133793 
133799 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
133800 {
133801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
133802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
133803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
133804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
133805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
133806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
133807 };
133808 
133814 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
133815 {
133816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
133817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
133818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
133819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
133820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
133821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
133822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
133823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
133824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
133825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
133826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
133827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
133828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
133829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
133830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
133831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
133832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
133833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
133834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
133835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
133836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
133837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
133838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
133839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
133840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
133841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
133842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
133843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
133844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
133845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
133846 };
133847 
133853 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
133854 {
133855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
133856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
133857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
133858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
133859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
133860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
133861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
133862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
133863 };
133864 
133870 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
133871 {
133872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
133873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
133874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
133875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
133876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
133877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
133878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
133879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
133880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
133881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
133882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
133883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
133884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
133885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
133886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
133887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
133888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
133889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
133890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
133891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
133892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
133893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
133894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
133895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
133896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
133897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
133898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
133899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
133900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
133901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
133902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
133903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
133904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
133905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
133906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
133907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
133908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
133909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
133910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
133911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
133912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
133913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
133914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
133915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
133916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
133917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
133918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
133919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
133920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
133921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
133922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
133923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
133924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
133925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
133926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
133927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
133928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
133929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
133930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
133931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
133932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
133933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
133934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
133935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
133936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
133937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
133938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
133939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
133940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
133941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
133942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
133943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
133944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
133945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
133946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
133947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
133948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
133949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
133950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
133951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
133952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
133953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
133954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
133955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
133956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
133957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
133958 };
133959 
133965 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
133966 {
133967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
133968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
133969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
133970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
133971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
133972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
133973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
133974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
133975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
133976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
133977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
133978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
133979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
133980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
133981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
133982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
133983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
133984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
133985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
133986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
133987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
133988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
133989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
133990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
133991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
133992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
133993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
133994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
133995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
133996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
133997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
133998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
133999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
134000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
134001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
134002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
134003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
134004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
134005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
134006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
134007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
134008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
134009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
134010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
134011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
134012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
134013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
134014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
134015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
134016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
134017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
134018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
134019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
134020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
134021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
134022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
134023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
134024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
134025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
134026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
134027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
134028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
134029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
134030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
134031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
134032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
134033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
134034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
134035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
134036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
134037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
134038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
134039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
134040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
134041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
134042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
134043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
134044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
134045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
134046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
134047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
134048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
134049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
134050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
134051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
134052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
134053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
134054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
134055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
134056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
134057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
134058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
134059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
134060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
134061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
134062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
134063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
134064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
134065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
134066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
134067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
134068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
134069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
134070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
134071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
134072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
134073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
134074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
134075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
134076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
134077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
134078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
134079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
134080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
134081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
134082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
134083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
134084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
134085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
134086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
134087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
134088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
134089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
134090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
134091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
134092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
134093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
134094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
134095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
134096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
134097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
134098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
134099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
134100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
134101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
134102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
134103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
134104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
134105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
134106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
134107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
134108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
134109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
134110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
134111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
134112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
134113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
134114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
134115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
134116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
134117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
134118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
134119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
134120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
134121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
134122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
134123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
134124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
134125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
134126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
134127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
134128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
134129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
134130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
134131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
134132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
134133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
134134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
134135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
134136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
134137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
134138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
134139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
134140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
134141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
134142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
134143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
134144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
134145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
134146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
134147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
134148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
134149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
134150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
134151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
134152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
134153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
134154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
134155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
134156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
134157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
134158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
134159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
134160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
134161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
134162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
134163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
134164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
134165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
134166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
134167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
134168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
134169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
134170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
134171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
134172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
134173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
134174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
134175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
134176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
134177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
134178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
134179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
134180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
134181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
134182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
134183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
134184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
134185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
134186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
134187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
134188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
134189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
134190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
134191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
134192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
134193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
134194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
134195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
134196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
134197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
134198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
134199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
134200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
134201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
134202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
134203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
134204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
134205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
134206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
134207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
134208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
134209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
134210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
134211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
134212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
134213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
134214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
134215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
134216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
134217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
134218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
134219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
134220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
134221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
134222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
134223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
134224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
134225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
134226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
134227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
134228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
134229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
134230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
134231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
134232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
134233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
134234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
134235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
134236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
134237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
134238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
134239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
134240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
134241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
134242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
134243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
134244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
134245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
134246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
134247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
134248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
134249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
134250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
134251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
134252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
134253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
134254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
134255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
134256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
134257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
134258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
134259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
134260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
134261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
134262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
134263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
134264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
134265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
134266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
134267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
134268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
134269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
134270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
134271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
134272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
134273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
134274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
134275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
134276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
134277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
134278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
134279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
134280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
134281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
134282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
134283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
134284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
134285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
134286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
134287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
134288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
134289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
134290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
134291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
134292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
134293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
134294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
134295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
134296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
134297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
134298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
134299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
134300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
134301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
134302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
134303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
134304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
134305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
134306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
134307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
134308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
134309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
134310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
134311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
134312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
134313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
134314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
134315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
134316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
134317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
134318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
134319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
134320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
134321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
134322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
134323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
134324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
134325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
134326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
134327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
134328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
134329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
134330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
134331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
134332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
134333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
134334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
134335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
134336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
134337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
134338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
134339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
134340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
134341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
134342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
134343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
134344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
134345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
134346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
134347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
134348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
134349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
134350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
134351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
134352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
134353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
134354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
134355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
134356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
134357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
134358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
134359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
134360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
134361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
134362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
134363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
134364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
134365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
134366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
134367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
134368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
134369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
134370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
134371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
134372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
134373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
134374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
134375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
134376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
134377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
134378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
134379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
134380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
134381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
134382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
134383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
134384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
134385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
134386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
134387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
134388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
134389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
134390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
134391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
134392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
134393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
134394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
134395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
134396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
134397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
134398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
134399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
134400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
134401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
134402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
134403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
134404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
134405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
134406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
134407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
134408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
134409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
134410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
134411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
134412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
134413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
134414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
134415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
134416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
134417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
134418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
134419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
134420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
134421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
134422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
134423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
134424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
134425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
134426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
134427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
134428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
134429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
134430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
134431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
134432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
134433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
134434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
134435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
134436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
134437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
134438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
134439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
134440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
134441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
134442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
134443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
134444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
134445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
134446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
134447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
134448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
134449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
134450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
134451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
134452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
134453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
134454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
134455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
134456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
134457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
134458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
134459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
134460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
134461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
134462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
134463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
134464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
134465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
134466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
134467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
134468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
134469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
134470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
134471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
134472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
134473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
134474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
134475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
134476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
134477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
134478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
134479 };
134480 
134486 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
134487 {
134488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
134489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
134490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
134491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
134492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
134493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
134494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
134495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
134496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
134497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
134498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
134499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
134500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
134501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
134502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
134503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
134504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
134505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
134506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
134507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
134508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
134509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
134510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
134511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
134512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
134513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
134514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
134515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
134516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
134517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
134518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
134519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
134520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
134521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
134522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
134523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
134524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
134525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
134526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
134527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
134528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
134529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
134530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
134531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
134532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
134533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
134534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
134535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
134536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
134537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
134538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
134539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
134540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
134541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
134542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
134543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
134544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
134545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
134546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
134547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
134548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
134549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
134550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
134551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
134552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
134553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
134554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
134555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
134556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
134557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
134558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
134559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
134560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
134561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
134562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
134563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
134564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
134565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
134566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
134567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
134568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
134569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
134570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
134571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
134572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
134573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
134574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
134575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
134576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
134577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
134578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
134579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
134580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
134581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
134582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
134583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
134584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
134585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
134586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
134587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
134588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
134589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
134590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
134591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
134592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
134593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
134594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
134595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
134596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
134597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
134598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
134599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
134600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
134601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
134602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
134603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
134604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
134605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
134606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
134607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
134608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
134609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
134610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
134611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
134612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
134613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
134614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
134615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
134616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
134617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
134618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
134619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
134620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
134621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
134622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
134623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
134624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
134625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
134626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
134627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
134628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
134629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
134630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
134631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
134632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
134633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
134634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
134635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
134636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
134637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
134638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
134639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
134640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
134641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
134642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
134643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
134644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
134645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
134646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
134647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
134648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
134649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
134650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
134651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
134652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
134653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
134654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
134655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
134656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
134657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
134658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
134659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
134660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
134661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
134662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
134663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
134664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
134665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
134666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
134667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
134668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
134669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
134670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
134671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
134672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
134673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
134674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
134675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
134676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
134677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
134678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
134679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
134680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
134681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
134682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
134683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
134684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
134685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
134686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
134687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
134688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
134689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
134690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
134691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
134692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
134693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
134694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
134695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
134696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
134697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
134698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
134699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
134700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
134701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
134702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
134703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
134704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
134705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
134706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
134707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
134708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
134709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
134710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
134711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
134712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
134713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
134714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
134715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
134716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
134717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
134718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
134719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
134720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
134721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
134722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
134723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
134724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
134725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
134726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
134727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
134728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
134729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
134730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
134731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
134732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
134733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
134734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
134735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
134736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
134737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
134738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
134739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
134740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
134741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
134742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
134743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
134744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
134745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
134746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
134747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
134748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
134749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
134750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
134751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
134752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
134753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
134754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
134755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
134756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
134757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
134758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
134759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
134760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
134761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
134762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
134763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
134764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
134765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
134766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
134767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
134768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
134769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
134770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
134771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
134772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
134773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
134774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
134775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
134776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
134777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
134778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
134779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
134780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
134781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
134782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
134783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
134784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
134785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
134786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
134787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
134788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
134789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
134790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
134791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
134792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
134793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
134794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
134795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
134796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
134797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
134798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
134799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
134800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
134801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
134802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
134803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
134804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
134805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
134806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
134807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
134808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
134809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
134810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
134811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
134812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
134813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
134814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
134815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
134816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
134817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
134818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
134819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
134820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
134821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
134822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
134823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
134824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
134825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
134826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
134827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
134828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
134829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
134830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
134831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
134832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
134833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
134834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
134835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
134836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
134837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
134838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
134839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
134840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
134841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
134842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
134843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
134844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
134845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
134846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
134847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
134848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
134849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
134850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
134851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
134852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
134853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
134854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
134855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
134856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
134857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
134858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
134859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
134860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
134861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
134862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
134863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
134864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
134865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
134866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
134867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
134868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
134869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
134870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
134871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
134872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
134873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
134874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
134875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
134876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
134877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
134878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
134879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
134880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
134881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
134882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
134883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
134884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
134885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
134886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
134887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
134888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
134889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
134890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
134891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
134892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
134893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
134894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
134895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
134896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
134897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
134898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
134899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
134900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
134901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
134902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
134903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
134904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
134905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
134906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
134907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
134908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
134909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
134910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
134911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
134912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
134913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
134914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
134915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
134916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
134917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
134918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
134919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
134920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
134921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
134922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
134923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
134924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
134925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
134926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
134927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
134928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
134929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
134930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
134931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
134932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
134933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
134934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
134935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
134936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
134937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
134938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
134939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
134940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
134941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
134942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
134943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
134944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
134945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
134946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
134947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
134948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
134949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
134950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
134951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
134952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
134953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
134954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
134955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
134956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
134957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
134958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
134959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
134960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
134961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
134962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
134963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
134964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
134965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
134966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
134967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
134968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
134969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
134970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
134971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
134972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
134973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
134974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
134975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
134976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
134977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
134978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
134979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
134980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
134981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
134982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
134983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
134984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
134985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
134986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
134987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
134988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
134989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
134990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
134991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
134992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
134993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
134994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
134995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
134996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
134997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
134998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
134999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
135000 };
135001 
135007 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
135008 {
135009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
135010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
135011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
135012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
135013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
135014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
135015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
135016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
135017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
135018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
135019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
135020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
135021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
135022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
135023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
135024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
135025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
135026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
135027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
135028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
135029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
135030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
135031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
135032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
135033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
135034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
135035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
135036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
135037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
135038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
135039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
135040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
135041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
135042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
135043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
135044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
135045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
135046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
135047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
135048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
135049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
135050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
135051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
135052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
135053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
135054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
135055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
135056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
135057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
135058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
135059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
135060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
135061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
135062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
135063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
135064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
135065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
135066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
135067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
135068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
135069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
135070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
135071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
135072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
135073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
135074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
135075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
135076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
135077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
135078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
135079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
135080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
135081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
135082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
135083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
135084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
135085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
135086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
135087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
135088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
135089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
135090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
135091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
135092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
135093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
135094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
135095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
135096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
135097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
135098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
135099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
135100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
135101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
135102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
135103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
135104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
135105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
135106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
135107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
135108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
135109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
135110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
135111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
135112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
135113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
135114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
135115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
135116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
135117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
135118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
135119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
135120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
135121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
135122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
135123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
135124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
135125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
135126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
135127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
135128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
135129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
135130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
135131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
135132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
135133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
135134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
135135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
135136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
135137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
135138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
135139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
135140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
135141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
135142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
135143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
135144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
135145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
135146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
135147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
135148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
135149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
135150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
135151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
135152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
135153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
135154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
135155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
135156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
135157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
135158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
135159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
135160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
135161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
135162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
135163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
135164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
135165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
135166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
135167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
135168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
135169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
135170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
135171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
135172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
135173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
135174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
135175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
135176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
135177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
135178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
135179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
135180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
135181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
135182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
135183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
135184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
135185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
135186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
135187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
135188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
135189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
135190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
135191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
135192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
135193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
135194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
135195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
135196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
135197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
135198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
135199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
135200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
135201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
135202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
135203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
135204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
135205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
135206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
135207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
135208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
135209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
135210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
135211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
135212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
135213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
135214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
135215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
135216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
135217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
135218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
135219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
135220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
135221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
135222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
135223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
135224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
135225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
135226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
135227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
135228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
135229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
135230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
135231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
135232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
135233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
135234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
135235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
135236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
135237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
135238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
135239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
135240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
135241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
135242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
135243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
135244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
135245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
135246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
135247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
135248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
135249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
135250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
135251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
135252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
135253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
135254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
135255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
135256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
135257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
135258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
135259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
135260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
135261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
135262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
135263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
135264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
135265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
135266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
135267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
135268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
135269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
135270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
135271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
135272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
135273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
135274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
135275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
135276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
135277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
135278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
135279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
135280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
135281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
135282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
135283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
135284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
135285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
135286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
135287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
135288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
135289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
135290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
135291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
135292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
135293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
135294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
135295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
135296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
135297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
135298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
135299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
135300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
135301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
135302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
135303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
135304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
135305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
135306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
135307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
135308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
135309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
135310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
135311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
135312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
135313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
135314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
135315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
135316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
135317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
135318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
135319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
135320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
135321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
135322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
135323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
135324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
135325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
135326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
135327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
135328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
135329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
135330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
135331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
135332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
135333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
135334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
135335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
135336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
135337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
135338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
135339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
135340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
135341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
135342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
135343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
135344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
135345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
135346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
135347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
135348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
135349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
135350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
135351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
135352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
135353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
135354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
135355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
135356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
135357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
135358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
135359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
135360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
135361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
135362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
135363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
135364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
135365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
135366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
135367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
135368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
135369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
135370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
135371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
135372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
135373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
135374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
135375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
135376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
135377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
135378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
135379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
135380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
135381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
135382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
135383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
135384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
135385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
135386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
135387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
135388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
135389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
135390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
135391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
135392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
135393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
135394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
135395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
135396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
135397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
135398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
135399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
135400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
135401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
135402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
135403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
135404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
135405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
135406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
135407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
135408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
135409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
135410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
135411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
135412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
135413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
135414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
135415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
135416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
135417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
135418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
135419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
135420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
135421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
135422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
135423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
135424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
135425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
135426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
135427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
135428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
135429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
135430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
135431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
135432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
135433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
135434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
135435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
135436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
135437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
135438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
135439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
135440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
135441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
135442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
135443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
135444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
135445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
135446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
135447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
135448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
135449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
135450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
135451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
135452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
135453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
135454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
135455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
135456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
135457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
135458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
135459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
135460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
135461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
135462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
135463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
135464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
135465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
135466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
135467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
135468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
135469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
135470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
135471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
135472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
135473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
135474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
135475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
135476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
135477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
135478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
135479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
135480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
135481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
135482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
135483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
135484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
135485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
135486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
135487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
135488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
135489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
135490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
135491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
135492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
135493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
135494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
135495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
135496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
135497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
135498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
135499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
135500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
135501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
135502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
135503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
135504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
135505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
135506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
135507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
135508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
135509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
135510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
135511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
135512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
135513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
135514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
135515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
135516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
135517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
135518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
135519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
135520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
135521 };
135522 
135528 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
135529 {
135530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
135531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
135532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
135533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
135534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
135535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
135536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
135537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
135538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
135539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
135540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
135541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
135542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
135543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
135544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
135545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
135546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
135547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
135548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
135549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
135550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
135551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
135552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
135553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
135554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
135555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
135556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
135557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
135558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
135559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
135560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
135561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
135562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
135563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
135564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
135565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
135566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
135567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
135568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
135569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
135570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
135571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
135572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
135573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
135574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
135575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
135576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
135577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
135578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
135579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
135580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
135581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
135582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
135583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
135584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
135585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
135586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
135587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
135588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
135589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
135590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
135591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
135592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
135593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
135594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
135595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
135596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
135597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
135598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
135599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
135600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
135601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
135602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
135603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
135604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
135605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
135606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
135607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
135608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
135609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
135610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
135611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
135612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
135613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
135614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
135615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
135616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
135617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
135618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
135619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
135620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
135621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
135622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
135623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
135624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
135625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
135626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
135627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
135628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
135629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
135630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
135631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
135632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
135633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
135634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
135635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
135636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
135637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
135638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
135639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
135640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
135641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
135642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
135643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
135644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
135645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
135646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
135647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
135648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
135649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
135650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
135651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
135652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
135653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
135654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
135655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
135656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
135657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
135658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
135659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
135660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
135661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
135662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
135663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
135664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
135665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
135666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
135667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
135668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
135669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
135670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
135671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
135672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
135673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
135674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
135675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
135676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
135677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
135678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
135679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
135680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
135681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
135682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
135683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
135684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
135685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
135686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
135687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
135688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
135689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
135690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
135691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
135692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
135693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
135694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
135695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
135696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
135697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
135698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
135699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
135700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
135701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
135702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
135703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
135704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
135705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
135706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
135707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
135708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
135709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
135710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
135711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
135712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
135713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
135714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
135715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
135716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
135717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
135718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
135719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
135720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
135721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
135722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
135723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
135724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
135725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
135726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
135727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
135728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
135729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
135730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
135731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
135732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
135733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
135734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
135735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
135736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
135737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
135738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
135739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
135740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
135741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
135742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
135743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
135744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
135745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
135746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
135747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
135748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
135749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
135750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
135751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
135752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
135753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
135754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
135755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
135756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
135757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
135758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
135759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
135760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
135761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
135762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
135763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
135764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
135765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
135766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
135767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
135768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
135769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
135770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
135771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
135772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
135773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
135774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
135775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
135776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
135777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
135778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
135779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
135780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
135781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
135782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
135783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
135784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
135785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
135786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
135787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
135788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
135789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
135790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
135791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
135792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
135793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
135794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
135795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
135796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
135797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
135798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
135799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
135800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
135801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
135802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
135803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
135804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
135805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
135806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
135807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
135808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
135809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
135810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
135811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
135812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
135813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
135814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
135815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
135816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
135817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
135818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
135819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
135820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
135821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
135822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
135823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
135824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
135825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
135826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
135827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
135828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
135829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
135830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
135831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
135832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
135833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
135834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
135835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
135836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
135837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
135838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
135839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
135840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
135841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
135842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
135843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
135844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
135845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
135846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
135847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
135848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
135849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
135850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
135851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
135852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
135853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
135854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
135855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
135856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
135857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
135858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
135859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
135860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
135861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
135862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
135863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
135864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
135865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
135866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
135867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
135868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
135869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
135870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
135871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
135872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
135873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
135874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
135875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
135876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
135877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
135878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
135879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
135880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
135881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
135882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
135883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
135884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
135885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
135886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
135887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
135888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
135889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
135890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
135891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
135892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
135893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
135894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
135895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
135896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
135897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
135898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
135899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
135900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
135901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
135902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
135903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
135904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
135905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
135906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
135907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
135908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
135909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
135910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
135911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
135912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
135913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
135914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
135915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
135916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
135917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
135918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
135919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
135920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
135921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
135922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
135923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
135924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
135925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
135926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
135927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
135928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
135929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
135930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
135931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
135932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
135933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
135934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
135935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
135936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
135937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
135938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
135939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
135940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
135941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
135942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
135943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
135944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
135945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
135946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
135947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
135948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
135949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
135950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
135951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
135952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
135953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
135954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
135955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
135956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
135957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
135958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
135959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
135960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
135961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
135962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
135963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
135964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
135965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
135966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
135967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
135968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
135969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
135970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
135971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
135972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
135973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
135974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
135975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
135976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
135977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
135978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
135979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
135980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
135981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
135982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
135983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
135984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
135985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
135986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
135987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
135988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
135989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
135990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
135991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
135992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
135993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
135994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
135995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
135996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
135997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
135998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
135999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
136000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
136001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
136002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
136003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
136004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
136005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
136006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
136007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
136008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
136009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
136010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
136011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
136012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
136013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
136014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
136015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
136016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
136017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
136018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
136019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
136020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
136021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
136022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
136023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
136024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
136025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
136026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
136027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
136028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
136029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
136030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
136031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
136032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
136033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
136034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
136035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
136036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
136037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
136038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
136039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
136040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
136041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
136042 };
136043 
136049 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
136050 {
136051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
136052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
136053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
136054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
136055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
136056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
136057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
136058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
136059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
136060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
136061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
136062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
136063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
136064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
136065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
136066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
136067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
136068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
136069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
136070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
136071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
136072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
136073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
136074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
136075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
136076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
136077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
136078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
136079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
136080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
136081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
136082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
136083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
136084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
136085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
136086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
136087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
136088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
136089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
136090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
136091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
136092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
136093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
136094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
136095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
136096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
136097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
136098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
136099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
136100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
136101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
136102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
136103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
136104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
136105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
136106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
136107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
136108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
136109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
136110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
136111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
136112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
136113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
136114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
136115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
136116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
136117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
136118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
136119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
136120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
136121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
136122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
136123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
136124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
136125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
136126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
136127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
136128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
136129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
136130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
136131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
136132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
136133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
136134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
136135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
136136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
136137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
136138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
136139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
136140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
136141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
136142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
136143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
136144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
136145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
136146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
136147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
136148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
136149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
136150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
136151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
136152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
136153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
136154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
136155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
136156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
136157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
136158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
136159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
136160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
136161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
136162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
136163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
136164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
136165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
136166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
136167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
136168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
136169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
136170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
136171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
136172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
136173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
136174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
136175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
136176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
136177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
136178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
136179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
136180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
136181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
136182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
136183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
136184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
136185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
136186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
136187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
136188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
136189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
136190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
136191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
136192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
136193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
136194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
136195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
136196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
136197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
136198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
136199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
136200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
136201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
136202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
136203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
136204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
136205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
136206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
136207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
136208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
136209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
136210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
136211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
136212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
136213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
136214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
136215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
136216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
136217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
136218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
136219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
136220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
136221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
136222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
136223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
136224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
136225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
136226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
136227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
136228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
136229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
136230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
136231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
136232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
136233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
136234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
136235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
136236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
136237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
136238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
136239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
136240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
136241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
136242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
136243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
136244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
136245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
136246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
136247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
136248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
136249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
136250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
136251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
136252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
136253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
136254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
136255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
136256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
136257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
136258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
136259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
136260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
136261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
136262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
136263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
136264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
136265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
136266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
136267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
136268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
136269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
136270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
136271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
136272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
136273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
136274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
136275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
136276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
136277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
136278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
136279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
136280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
136281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
136282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
136283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
136284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
136285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
136286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
136287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
136288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
136289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
136290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
136291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
136292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
136293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
136294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
136295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
136296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
136297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
136298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
136299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
136300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
136301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
136302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
136303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
136304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
136305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
136306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
136307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
136308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
136309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
136310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
136311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
136312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
136313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
136314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
136315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
136316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
136317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
136318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
136319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
136320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
136321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
136322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
136323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
136324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
136325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
136326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
136327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
136328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
136329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
136330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
136331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
136332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
136333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
136334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
136335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
136336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
136337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
136338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
136339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
136340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
136341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
136342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
136343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
136344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
136345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
136346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
136347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
136348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
136349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
136350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
136351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
136352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
136353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
136354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
136355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
136356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
136357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
136358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
136359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
136360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
136361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
136362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
136363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
136364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
136365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
136366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
136367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
136368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
136369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
136370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
136371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
136372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
136373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
136374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
136375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
136376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
136377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
136378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
136379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
136380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
136381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
136382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
136383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
136384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
136385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
136386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
136387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
136388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
136389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
136390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
136391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
136392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
136393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
136394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
136395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
136396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
136397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
136398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
136399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
136400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
136401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
136402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
136403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
136404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
136405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
136406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
136407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
136408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
136409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
136410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
136411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
136412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
136413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
136414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
136415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
136416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
136417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
136418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
136419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
136420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
136421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
136422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
136423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
136424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
136425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
136426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
136427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
136428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
136429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
136430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
136431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
136432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
136433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
136434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
136435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
136436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
136437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
136438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
136439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
136440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
136441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
136442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
136443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
136444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
136445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
136446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
136447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
136448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
136449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
136450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
136451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
136452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
136453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
136454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
136455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
136456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
136457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
136458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
136459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
136460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
136461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
136462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
136463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
136464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
136465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
136466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
136467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
136468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
136469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
136470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
136471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
136472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
136473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
136474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
136475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
136476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
136477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
136478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
136479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
136480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
136481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
136482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
136483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
136484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
136485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
136486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
136487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
136488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
136489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
136490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
136491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
136492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
136493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
136494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
136495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
136496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
136497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
136498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
136499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
136500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
136501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
136502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
136503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
136504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
136505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
136506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
136507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
136508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
136509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
136510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
136511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
136512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
136513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
136514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
136515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
136516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
136517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
136518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
136519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
136520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
136521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
136522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
136523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
136524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
136525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
136526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
136527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
136528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
136529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
136530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
136531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
136532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
136533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
136534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
136535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
136536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
136537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
136538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
136539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
136540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
136541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
136542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
136543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
136544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
136545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
136546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
136547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
136548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
136549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
136550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
136551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
136552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
136553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
136554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
136555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
136556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
136557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
136558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
136559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
136560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
136561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
136562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
136563 };
136564 
136570 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
136571 {
136572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
136573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
136574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
136575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
136576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
136577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
136578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
136579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
136580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
136581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
136582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
136583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
136584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
136585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
136586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
136587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
136588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
136589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
136590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
136591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
136592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
136593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
136594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
136595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
136596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
136597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
136598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
136599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
136600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
136601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
136602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
136603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
136604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
136605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
136606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
136607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
136608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
136609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
136610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
136611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
136612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
136613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
136614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
136615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
136616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
136617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
136618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
136619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
136620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
136621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
136622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
136623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
136624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
136625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
136626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
136627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
136628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
136629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
136630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
136631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
136632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
136633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
136634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
136635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
136636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
136637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
136638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
136639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
136640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
136641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
136642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
136643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
136644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
136645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
136646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
136647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
136648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
136649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
136650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
136651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
136652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
136653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
136654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
136655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
136656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
136657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
136658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
136659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
136660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
136661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
136662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
136663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
136664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
136665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
136666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
136667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
136668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
136669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
136670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
136671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
136672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
136673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
136674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
136675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
136676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
136677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
136678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
136679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
136680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
136681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
136682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
136683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
136684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
136685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
136686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
136687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
136688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
136689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
136690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
136691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
136692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
136693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
136694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
136695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
136696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
136697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
136698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
136699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
136700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
136701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
136702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
136703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
136704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
136705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
136706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
136707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
136708 };
136709 
136715 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
136716 {
136717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
136718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
136719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
136720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
136721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
136722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
136723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
136724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
136725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
136726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
136727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
136728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
136729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
136730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
136731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
136732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
136733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
136734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
136735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
136736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
136737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
136738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
136739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
136740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
136741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
136742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
136743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
136744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
136745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
136746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
136747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
136748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
136749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
136750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
136751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
136752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
136753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
136754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
136755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
136756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
136757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
136758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
136759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
136760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
136761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
136762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
136763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
136764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
136765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
136766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
136767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
136768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
136769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
136770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
136771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
136772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
136773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
136774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
136775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
136776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
136777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
136778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
136779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
136780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
136781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
136782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
136783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
136784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
136785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
136786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
136787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
136788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
136789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
136790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
136791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
136792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
136793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
136794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
136795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
136796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
136797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
136798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
136799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
136800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
136801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
136802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
136803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
136804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
136805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
136806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
136807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
136808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
136809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
136810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
136811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
136812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
136813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
136814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
136815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
136816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
136817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
136818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
136819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
136820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
136821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
136822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
136823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
136824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
136825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
136826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
136827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
136828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
136829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
136830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
136831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
136832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
136833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
136834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
136835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
136836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
136837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
136838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
136839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
136840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
136841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
136842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
136843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
136844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
136845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
136846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
136847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
136848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
136849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
136850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
136851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
136852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
136853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
136854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
136855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
136856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
136857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
136858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
136859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
136860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
136861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
136862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
136863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
136864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
136865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
136866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
136867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
136868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
136869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
136870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
136871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
136872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
136873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
136874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
136875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
136876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
136877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
136878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
136879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
136880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
136881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
136882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
136883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
136884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
136885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
136886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
136887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
136888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
136889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
136890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
136891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
136892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
136893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
136894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
136895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
136896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
136897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
136898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
136899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
136900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
136901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
136902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
136903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
136904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
136905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
136906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
136907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
136908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
136909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
136910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
136911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
136912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
136913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
136914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
136915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
136916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
136917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
136918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
136919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
136920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
136921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
136922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
136923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
136924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
136925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
136926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
136927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
136928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
136929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
136930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
136931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
136932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
136933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
136934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
136935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
136936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
136937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
136938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
136939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
136940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
136941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
136942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
136943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
136944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
136945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
136946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
136947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
136948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
136949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
136950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
136951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
136952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
136953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
136954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
136955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
136956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
136957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
136958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
136959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
136960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
136961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
136962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
136963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
136964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
136965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
136966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
136967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
136968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
136969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
136970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
136971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
136972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
136973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
136974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
136975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
136976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
136977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
136978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
136979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
136980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
136981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
136982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
136983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
136984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
136985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
136986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
136987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
136988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
136989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
136990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
136991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
136992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
136993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
136994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
136995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
136996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
136997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
136998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
136999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
137000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
137001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
137002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
137003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
137004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
137005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
137006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
137007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
137008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
137009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
137010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
137011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
137012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
137013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
137014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
137015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
137016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
137017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
137018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
137019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
137020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
137021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
137022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
137023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
137024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
137025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
137026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
137027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
137028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
137029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
137030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
137031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
137032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
137033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
137034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
137035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
137036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
137037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
137038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
137039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
137040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
137041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
137042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
137043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
137044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
137045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
137046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
137047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
137048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
137049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
137050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
137051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
137052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
137053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
137054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
137055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
137056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
137057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
137058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
137059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
137060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
137061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
137062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
137063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
137064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
137065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
137066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
137067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
137068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
137069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
137070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
137071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
137072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
137073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
137074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
137075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
137076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
137077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
137078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
137079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
137080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
137081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
137082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
137083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
137084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
137085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
137086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
137087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
137088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
137089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
137090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
137091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
137092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
137093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
137094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
137095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
137096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
137097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
137098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
137099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
137100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
137101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
137102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
137103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
137104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
137105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
137106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
137107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
137108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
137109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
137110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
137111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
137112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
137113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
137114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
137115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
137116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
137117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
137118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
137119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
137120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
137121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
137122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
137123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
137124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
137125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
137126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
137127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
137128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
137129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
137130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
137131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
137132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
137133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
137134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
137135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
137136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
137137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
137138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
137139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
137140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
137141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
137142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
137143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
137144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
137145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
137146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
137147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
137148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
137149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
137150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
137151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
137152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
137153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
137154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
137155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
137156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
137157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
137158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
137159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
137160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
137161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
137162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
137163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
137164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
137165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
137166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
137167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
137168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
137169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
137170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
137171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
137172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
137173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
137174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
137175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
137176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
137177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
137178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
137179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
137180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
137181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
137182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
137183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
137184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
137185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
137186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
137187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
137188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
137189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
137190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
137191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
137192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
137193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
137194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
137195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
137196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
137197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
137198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
137199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
137200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
137201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
137202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
137203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
137204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
137205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
137206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
137207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
137208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
137209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
137210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
137211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
137212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
137213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
137214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
137215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
137216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
137217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
137218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
137219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
137220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
137221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
137222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
137223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
137224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
137225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
137226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
137227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
137228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
137229 };
137230 
137236 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
137237 {
137238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
137239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
137240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
137241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
137242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
137243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
137244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
137245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
137246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
137247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
137248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
137249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
137250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
137251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
137252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
137253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
137254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
137255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
137256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
137257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
137258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
137259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
137260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
137261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
137262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
137263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
137264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
137265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
137266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
137267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
137268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
137269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
137270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
137271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
137272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
137273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
137274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
137275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
137276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
137277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
137278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
137279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
137280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
137281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
137282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
137283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
137284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
137285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
137286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
137287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
137288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
137289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
137290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
137291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
137292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
137293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
137294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
137295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
137296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
137297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
137298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
137299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
137300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
137301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
137302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
137303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
137304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
137305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
137306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
137307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
137308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
137309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
137310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
137311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
137312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
137313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
137314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
137315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
137316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
137317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
137318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
137319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
137320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
137321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
137322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
137323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
137324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
137325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
137326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
137327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
137328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
137329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
137330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
137331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
137332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
137333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
137334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
137335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
137336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
137337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
137338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
137339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
137340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
137341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
137342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
137343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
137344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
137345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
137346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
137347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
137348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
137349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
137350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
137351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
137352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
137353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
137354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
137355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
137356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
137357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
137358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
137359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
137360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
137361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
137362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
137363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
137364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
137365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
137366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
137367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
137368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
137369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
137370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
137371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
137372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
137373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
137374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
137375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
137376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
137377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
137378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
137379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
137380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
137381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
137382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
137383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
137384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
137385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
137386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
137387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
137388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
137389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
137390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
137391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
137392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
137393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
137394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
137395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
137396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
137397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
137398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
137399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
137400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
137401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
137402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
137403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
137404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
137405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
137406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
137407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
137408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
137409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
137410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
137411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
137412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
137413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
137414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
137415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
137416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
137417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
137418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
137419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
137420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
137421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
137422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
137423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
137424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
137425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
137426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
137427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
137428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
137429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
137430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
137431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
137432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
137433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
137434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
137435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
137436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
137437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
137438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
137439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
137440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
137441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
137442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
137443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
137444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
137445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
137446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
137447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
137448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
137449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
137450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
137451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
137452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
137453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
137454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
137455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
137456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
137457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
137458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
137459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
137460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
137461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
137462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
137463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
137464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
137465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
137466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
137467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
137468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
137469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
137470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
137471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
137472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
137473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
137474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
137475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
137476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
137477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
137478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
137479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
137480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
137481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
137482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
137483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
137484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
137485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
137486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
137487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
137488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
137489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
137490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
137491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
137492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
137493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
137494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
137495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
137496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
137497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
137498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
137499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
137500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
137501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
137502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
137503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
137504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
137505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
137506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
137507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
137508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
137509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
137510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
137511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
137512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
137513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
137514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
137515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
137516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
137517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
137518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
137519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
137520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
137521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
137522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
137523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
137524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
137525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
137526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
137527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
137528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
137529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
137530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
137531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
137532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
137533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
137534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
137535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
137536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
137537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
137538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
137539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
137540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
137541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
137542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
137543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
137544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
137545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
137546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
137547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
137548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
137549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
137550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
137551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
137552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
137553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
137554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
137555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
137556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
137557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
137558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
137559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
137560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
137561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
137562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
137563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
137564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
137565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
137566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
137567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
137568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
137569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
137570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
137571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
137572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
137573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
137574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
137575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
137576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
137577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
137578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
137579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
137580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
137581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
137582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
137583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
137584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
137585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
137586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
137587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
137588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
137589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
137590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
137591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
137592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
137593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
137594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
137595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
137596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
137597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
137598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
137599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
137600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
137601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
137602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
137603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
137604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
137605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
137606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
137607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
137608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
137609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
137610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
137611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
137612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
137613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
137614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
137615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
137616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
137617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
137618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
137619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
137620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
137621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
137622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
137623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
137624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
137625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
137626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
137627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
137628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
137629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
137630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
137631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
137632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
137633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
137634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
137635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
137636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
137637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
137638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
137639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
137640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
137641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
137642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
137643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
137644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
137645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
137646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
137647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
137648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
137649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
137650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
137651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
137652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
137653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
137654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
137655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
137656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
137657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
137658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
137659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
137660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
137661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
137662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
137663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
137664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
137665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
137666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
137667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
137668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
137669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
137670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
137671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
137672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
137673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
137674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
137675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
137676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
137677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
137678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
137679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
137680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
137681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
137682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
137683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
137684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
137685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
137686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
137687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
137688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
137689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
137690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
137691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
137692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
137693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
137694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
137695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
137696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
137697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
137698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
137699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
137700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
137701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
137702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
137703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
137704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
137705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
137706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
137707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
137708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
137709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
137710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
137711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
137712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
137713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
137714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
137715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
137716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
137717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
137718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
137719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
137720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
137721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
137722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
137723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
137724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
137725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
137726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
137727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
137728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
137729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
137730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
137731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
137732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
137733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
137734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
137735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
137736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
137737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
137738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
137739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
137740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
137741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
137742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
137743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
137744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
137745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
137746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
137747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
137748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
137749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
137750 };
137751 
137757 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
137758 {
137759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
137760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
137761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
137762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
137763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
137764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
137765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
137766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
137767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
137768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
137769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
137770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
137771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
137772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
137773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
137774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
137775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
137776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
137777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
137778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
137779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
137780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
137781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
137782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
137783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
137784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
137785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
137786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
137787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
137788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
137789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
137790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
137791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
137792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
137793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
137794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
137795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
137796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
137797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
137798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
137799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
137800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
137801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
137802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
137803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
137804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
137805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
137806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
137807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
137808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
137809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
137810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
137811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
137812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
137813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
137814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
137815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
137816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
137817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
137818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
137819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
137820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
137821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
137822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
137823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
137824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
137825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
137826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
137827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
137828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
137829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
137830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
137831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
137832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
137833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
137834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
137835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
137836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
137837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
137838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
137839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
137840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
137841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
137842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
137843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
137844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
137845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
137846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
137847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
137848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
137849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
137850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
137851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
137852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
137853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
137854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
137855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
137856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
137857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
137858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
137859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
137860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
137861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
137862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
137863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
137864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
137865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
137866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
137867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
137868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
137869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
137870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
137871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
137872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
137873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
137874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
137875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
137876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
137877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
137878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
137879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
137880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
137881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
137882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
137883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
137884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
137885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
137886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
137887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
137888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
137889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
137890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
137891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
137892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
137893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
137894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
137895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
137896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
137897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
137898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
137899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
137900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
137901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
137902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
137903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
137904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
137905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
137906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
137907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
137908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
137909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
137910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
137911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
137912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
137913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
137914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
137915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
137916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
137917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
137918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
137919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
137920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
137921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
137922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
137923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
137924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
137925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
137926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
137927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
137928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
137929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
137930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
137931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
137932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
137933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
137934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
137935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
137936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
137937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
137938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
137939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
137940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
137941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
137942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
137943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
137944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
137945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
137946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
137947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
137948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
137949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
137950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
137951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
137952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
137953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
137954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
137955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
137956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
137957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
137958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
137959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
137960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
137961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
137962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
137963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
137964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
137965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
137966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
137967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
137968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
137969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
137970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
137971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
137972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
137973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
137974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
137975 };
137976 
137982 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
137983 {
137984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
137985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
137986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
137987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
137988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
137989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
137990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
137991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
137992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
137993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
137994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
137995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
137996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
137997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
137998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
137999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
138000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
138001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
138002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
138003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
138004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
138005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
138006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
138007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
138008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
138009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
138010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
138011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
138012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
138013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
138014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
138015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
138016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
138017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
138018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
138019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
138020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
138021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
138022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
138023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
138024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
138025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
138026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
138027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
138028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
138029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
138030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
138031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
138032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
138033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
138034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
138035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
138036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
138037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
138038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
138039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
138040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
138041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
138042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
138043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
138044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
138045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
138046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
138047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
138048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
138049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
138050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
138051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
138052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
138053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
138054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
138055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
138056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
138057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
138058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
138059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
138060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
138061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
138062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
138063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
138064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
138065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
138066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
138067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
138068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
138069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
138070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
138071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
138072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
138073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
138074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
138075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
138076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
138077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
138078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
138079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
138080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
138081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
138082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
138083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
138084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
138085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
138086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
138087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
138088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
138089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
138090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
138091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
138092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
138093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
138094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
138095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
138096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
138097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
138098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
138099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
138100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
138101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
138102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
138103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
138104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
138105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
138106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
138107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
138108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
138109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
138110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
138111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
138112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
138113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
138114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
138115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
138116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
138117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
138118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
138119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
138120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
138121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
138122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
138123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
138124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
138125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
138126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
138127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
138128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
138129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
138130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
138131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
138132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
138133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
138134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
138135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
138136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
138137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
138138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
138139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
138140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
138141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
138142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
138143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
138144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
138145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
138146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
138147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
138148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
138149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
138150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
138151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
138152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
138153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
138154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
138155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
138156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
138157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
138158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
138159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
138160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
138161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
138162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
138163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
138164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
138165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
138166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
138167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
138168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
138169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
138170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
138171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
138172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
138173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
138174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
138175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
138176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
138177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
138178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
138179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
138180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
138181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
138182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
138183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
138184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
138185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
138186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
138187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
138188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
138189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
138190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
138191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
138192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
138193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
138194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
138195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
138196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
138197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
138198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
138199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
138200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
138201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
138202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
138203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
138204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
138205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
138206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
138207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
138208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
138209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
138210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
138211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
138212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
138213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
138214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
138215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
138216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
138217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
138218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
138219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
138220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
138221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
138222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
138223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
138224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
138225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
138226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
138227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
138228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
138229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
138230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
138231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
138232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
138233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
138234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
138235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
138236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
138237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
138238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
138239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
138240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
138241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
138242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
138243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
138244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
138245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
138246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
138247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
138248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
138249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
138250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
138251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
138252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
138253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
138254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
138255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
138256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
138257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
138258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
138259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
138260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
138261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
138262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
138263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
138264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
138265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
138266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
138267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
138268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
138269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
138270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
138271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
138272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
138273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
138274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
138275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
138276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
138277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
138278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
138279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
138280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
138281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
138282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
138283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
138284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
138285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
138286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
138287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
138288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
138289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
138290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
138291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
138292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
138293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
138294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
138295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
138296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
138297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
138298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
138299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
138300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
138301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
138302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
138303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
138304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
138305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
138306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
138307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
138308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
138309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
138310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
138311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
138312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
138313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
138314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
138315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
138316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
138317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
138318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
138319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
138320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
138321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
138322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
138323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
138324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
138325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
138326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
138327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
138328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
138329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
138330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
138331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
138332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
138333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
138334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
138335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
138336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
138337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
138338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
138339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
138340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
138341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
138342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
138343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
138344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
138345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
138346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
138347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
138348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
138349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
138350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
138351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
138352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
138353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
138354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
138355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
138356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
138357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
138358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
138359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
138360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
138361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
138362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
138363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
138364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
138365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
138366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
138367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
138368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
138369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
138370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
138371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
138372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
138373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
138374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
138375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
138376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
138377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
138378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
138379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
138380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
138381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
138382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
138383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
138384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
138385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
138386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
138387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
138388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
138389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
138390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
138391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
138392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
138393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
138394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
138395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
138396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
138397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
138398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
138399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
138400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
138401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
138402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
138403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
138404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
138405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
138406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
138407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
138408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
138409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
138410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
138411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
138412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
138413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
138414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
138415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
138416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
138417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
138418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
138419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
138420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
138421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
138422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
138423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
138424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
138425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
138426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
138427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
138428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
138429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
138430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
138431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
138432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
138433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
138434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
138435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
138436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
138437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
138438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
138439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
138440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
138441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
138442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
138443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
138444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
138445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
138446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
138447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
138448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
138449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
138450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
138451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
138452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
138453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
138454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
138455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
138456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
138457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
138458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
138459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
138460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
138461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
138462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
138463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
138464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
138465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
138466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
138467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
138468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
138469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
138470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
138471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
138472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
138473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
138474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
138475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
138476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
138477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
138478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
138479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
138480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
138481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
138482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
138483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
138484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
138485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
138486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
138487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
138488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
138489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
138490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
138491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
138492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
138493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
138494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
138495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
138496 };
138497 
138503 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
138504 {
138505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
138506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
138507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
138508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
138509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
138510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
138511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
138512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
138513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
138514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
138515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
138516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
138517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
138518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
138519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
138520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
138521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
138522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
138523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
138524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
138525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
138526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
138527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
138528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
138529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
138530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
138531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
138532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
138533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
138534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
138535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
138536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
138537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
138538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
138539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
138540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
138541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
138542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
138543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
138544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
138545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
138546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
138547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
138548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
138549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
138550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
138551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
138552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
138553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
138554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
138555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
138556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
138557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
138558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
138559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
138560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
138561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
138562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
138563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
138564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
138565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
138566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
138567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
138568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
138569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
138570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
138571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
138572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
138573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
138574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
138575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
138576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
138577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
138578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
138579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
138580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
138581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
138582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
138583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
138584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
138585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
138586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
138587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
138588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
138589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
138590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
138591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
138592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
138593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
138594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
138595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
138596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
138597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
138598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
138599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
138600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
138601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
138602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
138603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
138604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
138605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
138606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
138607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
138608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
138609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
138610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
138611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
138612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
138613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
138614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
138615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
138616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
138617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
138618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
138619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
138620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
138621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
138622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
138623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
138624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
138625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
138626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
138627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
138628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
138629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
138630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
138631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
138632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
138633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
138634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
138635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
138636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
138637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
138638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
138639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
138640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
138641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
138642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
138643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
138644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
138645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
138646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
138647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
138648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
138649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
138650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
138651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
138652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
138653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
138654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
138655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
138656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
138657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
138658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
138659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
138660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
138661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
138662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
138663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
138664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
138665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
138666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
138667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
138668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
138669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
138670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
138671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
138672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
138673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
138674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
138675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
138676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
138677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
138678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
138679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
138680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
138681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
138682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
138683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
138684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
138685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
138686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
138687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
138688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
138689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
138690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
138691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
138692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
138693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
138694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
138695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
138696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
138697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
138698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
138699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
138700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
138701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
138702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
138703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
138704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
138705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
138706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
138707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
138708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
138709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
138710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
138711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
138712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
138713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
138714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
138715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
138716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
138717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
138718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
138719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
138720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
138721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
138722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
138723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
138724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
138725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
138726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
138727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
138728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
138729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
138730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
138731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
138732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
138733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
138734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
138735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
138736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
138737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
138738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
138739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
138740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
138741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
138742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
138743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
138744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
138745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
138746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
138747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
138748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
138749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
138750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
138751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
138752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
138753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
138754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
138755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
138756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
138757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
138758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
138759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
138760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
138761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
138762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
138763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
138764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
138765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
138766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
138767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
138768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
138769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
138770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
138771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
138772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
138773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
138774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
138775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
138776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
138777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
138778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
138779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
138780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
138781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
138782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
138783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
138784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
138785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
138786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
138787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
138788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
138789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
138790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
138791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
138792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
138793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
138794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
138795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
138796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
138797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
138798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
138799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
138800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
138801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
138802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
138803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
138804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
138805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
138806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
138807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
138808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
138809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
138810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
138811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
138812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
138813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
138814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
138815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
138816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
138817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
138818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
138819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
138820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
138821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
138822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
138823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
138824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
138825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
138826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
138827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
138828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
138829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
138830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
138831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
138832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
138833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
138834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
138835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
138836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
138837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
138838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
138839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
138840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
138841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
138842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
138843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
138844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
138845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
138846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
138847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
138848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
138849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
138850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
138851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
138852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
138853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
138854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
138855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
138856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
138857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
138858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
138859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
138860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
138861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
138862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
138863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
138864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
138865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
138866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
138867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
138868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
138869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
138870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
138871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
138872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
138873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
138874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
138875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
138876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
138877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
138878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
138879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
138880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
138881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
138882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
138883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
138884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
138885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
138886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
138887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
138888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
138889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
138890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
138891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
138892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
138893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
138894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
138895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
138896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
138897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
138898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
138899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
138900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
138901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
138902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
138903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
138904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
138905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
138906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
138907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
138908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
138909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
138910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
138911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
138912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
138913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
138914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
138915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
138916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
138917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
138918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
138919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
138920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
138921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
138922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
138923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
138924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
138925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
138926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
138927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
138928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
138929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
138930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
138931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
138932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
138933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
138934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
138935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
138936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
138937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
138938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
138939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
138940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
138941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
138942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
138943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
138944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
138945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
138946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
138947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
138948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
138949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
138950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
138951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
138952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
138953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
138954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
138955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
138956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
138957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
138958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
138959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
138960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
138961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
138962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
138963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
138964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
138965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
138966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
138967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
138968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
138969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
138970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
138971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
138972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
138973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
138974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
138975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
138976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
138977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
138978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
138979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
138980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
138981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
138982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
138983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
138984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
138985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
138986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
138987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
138988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
138989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
138990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
138991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
138992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
138993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
138994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
138995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
138996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
138997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
138998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
138999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
139000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
139001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
139002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
139003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
139004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
139005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
139006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
139007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
139008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
139009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
139010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
139011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
139012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
139013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
139014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
139015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
139016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
139017 };
139018 
139024 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
139025 {
139026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
139027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
139028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
139029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
139030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
139031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
139032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
139033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
139034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
139035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
139036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
139037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
139038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
139039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
139040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
139041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
139042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
139043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
139044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
139045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
139046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
139047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
139048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
139049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
139050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
139051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
139052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
139053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
139054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
139055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
139056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
139057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
139058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
139059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
139060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
139061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
139062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
139063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
139064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
139065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
139066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
139067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
139068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
139069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
139070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
139071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
139072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
139073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
139074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
139075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
139076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
139077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
139078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
139079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
139080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
139081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
139082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
139083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
139084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
139085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
139086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
139087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
139088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
139089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
139090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
139091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
139092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
139093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
139094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
139095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
139096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
139097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
139098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
139099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
139100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
139101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
139102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
139103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
139104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
139105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
139106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
139107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
139108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
139109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
139110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
139111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
139112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
139113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
139114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
139115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
139116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
139117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
139118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
139119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
139120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
139121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
139122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
139123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
139124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
139125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
139126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
139127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
139128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
139129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
139130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
139131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
139132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
139133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
139134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
139135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
139136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
139137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
139138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
139139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
139140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
139141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
139142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
139143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
139144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
139145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
139146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
139147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
139148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
139149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
139150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
139151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
139152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
139153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
139154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
139155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
139156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
139157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
139158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
139159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
139160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
139161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
139162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
139163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
139164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
139165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
139166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
139167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
139168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
139169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
139170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
139171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
139172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
139173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
139174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
139175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
139176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
139177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
139178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
139179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
139180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
139181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
139182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
139183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
139184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
139185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
139186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
139187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
139188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
139189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
139190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
139191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
139192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
139193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
139194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
139195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
139196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
139197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
139198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
139199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
139200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
139201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
139202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
139203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
139204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
139205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
139206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
139207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
139208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
139209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
139210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
139211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
139212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
139213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
139214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
139215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
139216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
139217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
139218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
139219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
139220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
139221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
139222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
139223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
139224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
139225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
139226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
139227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
139228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
139229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
139230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
139231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
139232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
139233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
139234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
139235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
139236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
139237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
139238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
139239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
139240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
139241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
139242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
139243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
139244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
139245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
139246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
139247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
139248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
139249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
139250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
139251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
139252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
139253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
139254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
139255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
139256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
139257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
139258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
139259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
139260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
139261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
139262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
139263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
139264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
139265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
139266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
139267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
139268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
139269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
139270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
139271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
139272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
139273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
139274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
139275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
139276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
139277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
139278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
139279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
139280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
139281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
139282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
139283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
139284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
139285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
139286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
139287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
139288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
139289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
139290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
139291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
139292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
139293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
139294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
139295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
139296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
139297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
139298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
139299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
139300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
139301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
139302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
139303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
139304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
139305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
139306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
139307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
139308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
139309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
139310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
139311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
139312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
139313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
139314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
139315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
139316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
139317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
139318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
139319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
139320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
139321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
139322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
139323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
139324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
139325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
139326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
139327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
139328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
139329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
139330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
139331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
139332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
139333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
139334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
139335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
139336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
139337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
139338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
139339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
139340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
139341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
139342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
139343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
139344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
139345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
139346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
139347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
139348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
139349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
139350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
139351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
139352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
139353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
139354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
139355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
139356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
139357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
139358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
139359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
139360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
139361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
139362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
139363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
139364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
139365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
139366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
139367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
139368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
139369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
139370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
139371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
139372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
139373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
139374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
139375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
139376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
139377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
139378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
139379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
139380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
139381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
139382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
139383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
139384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
139385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
139386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
139387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
139388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
139389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
139390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
139391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
139392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
139393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
139394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
139395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
139396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
139397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
139398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
139399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
139400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
139401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
139402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
139403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
139404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
139405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
139406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
139407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
139408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
139409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
139410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
139411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
139412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
139413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
139414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
139415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
139416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
139417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
139418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
139419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
139420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
139421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
139422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
139423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
139424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
139425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
139426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
139427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
139428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
139429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
139430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
139431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
139432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
139433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
139434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
139435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
139436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
139437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
139438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
139439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
139440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
139441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
139442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
139443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
139444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
139445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
139446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
139447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
139448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
139449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
139450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
139451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
139452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
139453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
139454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
139455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
139456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
139457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
139458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
139459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
139460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
139461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
139462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
139463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
139464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
139465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
139466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
139467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
139468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
139469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
139470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
139471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
139472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
139473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
139474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
139475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
139476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
139477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
139478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
139479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
139480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
139481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
139482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
139483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
139484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
139485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
139486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
139487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
139488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
139489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
139490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
139491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
139492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
139493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
139494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
139495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
139496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
139497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
139498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
139499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
139500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
139501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
139502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
139503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
139504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
139505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
139506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
139507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
139508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
139509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
139510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
139511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
139512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
139513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
139514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
139515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
139516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
139517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
139518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
139519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
139520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
139521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
139522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
139523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
139524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
139525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
139526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
139527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
139528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
139529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
139530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
139531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
139532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
139533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
139534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
139535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
139536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
139537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
139538 };
139539 
139545 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
139546 {
139547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
139548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
139549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
139550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
139551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
139552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
139553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
139554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
139555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
139556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
139557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
139558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
139559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
139560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
139561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
139562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
139563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
139564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
139565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
139566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
139567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
139568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
139569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
139570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
139571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
139572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
139573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
139574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
139575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
139576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
139577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
139578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
139579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
139580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
139581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
139582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
139583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
139584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
139585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
139586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
139587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
139588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
139589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
139590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
139591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
139592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
139593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
139594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
139595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
139596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
139597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
139598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
139599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
139600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
139601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
139602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
139603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
139604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
139605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
139606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
139607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
139608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
139609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
139610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
139611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
139612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
139613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
139614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
139615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
139616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
139617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
139618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
139619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
139620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
139621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
139622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
139623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
139624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
139625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
139626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
139627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
139628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
139629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
139630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
139631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
139632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
139633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
139634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
139635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
139636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
139637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
139638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
139639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
139640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
139641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
139642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
139643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
139644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
139645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
139646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
139647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
139648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
139649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
139650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
139651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
139652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
139653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
139654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
139655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
139656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
139657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
139658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
139659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
139660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
139661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
139662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
139663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
139664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
139665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
139666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
139667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
139668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
139669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
139670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
139671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
139672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
139673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
139674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
139675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
139676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
139677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
139678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
139679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
139680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
139681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
139682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
139683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
139684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
139685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
139686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
139687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
139688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
139689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
139690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
139691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
139692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
139693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
139694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
139695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
139696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
139697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
139698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
139699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
139700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
139701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
139702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
139703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
139704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
139705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
139706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
139707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
139708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
139709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
139710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
139711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
139712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
139713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
139714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
139715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
139716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
139717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
139718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
139719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
139720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
139721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
139722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
139723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
139724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
139725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
139726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
139727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
139728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
139729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
139730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
139731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
139732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
139733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
139734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
139735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
139736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
139737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
139738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
139739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
139740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
139741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
139742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
139743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
139744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
139745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
139746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
139747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
139748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
139749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
139750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
139751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
139752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
139753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
139754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
139755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
139756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
139757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
139758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
139759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
139760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
139761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
139762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
139763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
139764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
139765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
139766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
139767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
139768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
139769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
139770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
139771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
139772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
139773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
139774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
139775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
139776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
139777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
139778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
139779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
139780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
139781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
139782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
139783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
139784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
139785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
139786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
139787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
139788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
139789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
139790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
139791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
139792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
139793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
139794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
139795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
139796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
139797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
139798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
139799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
139800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
139801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
139802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
139803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
139804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
139805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
139806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
139807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
139808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
139809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
139810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
139811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
139812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
139813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
139814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
139815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
139816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
139817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
139818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
139819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
139820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
139821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
139822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
139823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
139824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
139825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
139826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
139827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
139828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
139829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
139830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
139831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
139832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
139833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
139834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
139835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
139836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
139837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
139838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
139839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
139840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
139841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
139842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
139843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
139844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
139845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
139846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
139847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
139848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
139849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
139850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
139851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
139852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
139853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
139854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
139855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
139856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
139857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
139858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
139859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
139860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
139861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
139862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
139863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
139864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
139865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
139866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
139867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
139868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
139869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
139870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
139871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
139872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
139873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
139874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
139875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
139876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
139877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
139878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
139879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
139880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
139881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
139882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
139883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
139884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
139885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
139886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
139887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
139888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
139889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
139890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
139891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
139892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
139893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
139894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
139895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
139896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
139897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
139898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
139899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
139900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
139901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
139902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
139903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
139904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
139905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
139906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
139907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
139908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
139909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
139910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
139911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
139912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
139913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
139914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
139915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
139916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
139917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
139918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
139919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
139920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
139921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
139922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
139923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
139924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
139925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
139926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
139927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
139928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
139929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
139930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
139931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
139932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
139933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
139934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
139935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
139936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
139937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
139938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
139939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
139940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
139941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
139942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
139943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
139944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
139945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
139946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
139947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
139948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
139949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
139950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
139951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
139952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
139953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
139954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
139955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
139956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
139957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
139958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
139959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
139960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
139961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
139962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
139963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
139964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
139965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
139966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
139967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
139968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
139969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
139970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
139971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
139972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
139973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
139974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
139975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
139976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
139977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
139978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
139979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
139980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
139981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
139982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
139983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
139984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
139985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
139986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
139987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
139988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
139989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
139990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
139991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
139992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
139993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
139994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
139995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
139996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
139997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
139998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
139999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
140000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
140001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
140002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
140003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
140004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
140005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
140006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
140007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
140008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
140009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
140010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
140011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
140012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
140013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
140014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
140015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
140016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
140017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
140018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
140019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
140020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
140021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
140022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
140023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
140024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
140025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
140026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
140027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
140028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
140029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
140030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
140031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
140032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
140033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
140034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
140035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
140036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
140037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
140038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
140039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
140040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
140041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
140042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
140043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
140044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
140045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
140046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
140047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
140048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
140049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
140050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
140051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
140052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
140053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
140054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
140055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
140056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
140057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
140058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
140059 };
140060 
140066 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
140067 {
140068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
140069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
140070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
140071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
140072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
140073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
140074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
140075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
140076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
140077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
140078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
140079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
140080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
140081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
140082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
140083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
140084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
140085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
140086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
140087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
140088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
140089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
140090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
140091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
140092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
140093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
140094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
140095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
140096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
140097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
140098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
140099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
140100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
140101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
140102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
140103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
140104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
140105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
140106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
140107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
140108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
140109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
140110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
140111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
140112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
140113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
140114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
140115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
140116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
140117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
140118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
140119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
140120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
140121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
140122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
140123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
140124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
140125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
140126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
140127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
140128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
140129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
140130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
140131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
140132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
140133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
140134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
140135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
140136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
140137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
140138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
140139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
140140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
140141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
140142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
140143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
140144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
140145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
140146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
140147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
140148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
140149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
140150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
140151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
140152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
140153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
140154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
140155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
140156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
140157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
140158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
140159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
140160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
140161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
140162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
140163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
140164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
140165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
140166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
140167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
140168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
140169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
140170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
140171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
140172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
140173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
140174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
140175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
140176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
140177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
140178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
140179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
140180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
140181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
140182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
140183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
140184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
140185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
140186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
140187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
140188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
140189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
140190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
140191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
140192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
140193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
140194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
140195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
140196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
140197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
140198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
140199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
140200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
140201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
140202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
140203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
140204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
140205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
140206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
140207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
140208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
140209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
140210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
140211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
140212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
140213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
140214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
140215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
140216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
140217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
140218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
140219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
140220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
140221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
140222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
140223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
140224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
140225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
140226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
140227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
140228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
140229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
140230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
140231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
140232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
140233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
140234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
140235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
140236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
140237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
140238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
140239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
140240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
140241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
140242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
140243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
140244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
140245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
140246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
140247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
140248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
140249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
140250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
140251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
140252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
140253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
140254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
140255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
140256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
140257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
140258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
140259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
140260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
140261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
140262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
140263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
140264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
140265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
140266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
140267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
140268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
140269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
140270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
140271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
140272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
140273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
140274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
140275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
140276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
140277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
140278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
140279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
140280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
140281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
140282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
140283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
140284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
140285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
140286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
140287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
140288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
140289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
140290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
140291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
140292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
140293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
140294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
140295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
140296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
140297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
140298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
140299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
140300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
140301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
140302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
140303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
140304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
140305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
140306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
140307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
140308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
140309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
140310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
140311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
140312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
140313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
140314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
140315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
140316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
140317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
140318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
140319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
140320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
140321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
140322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
140323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
140324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
140325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
140326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
140327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
140328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
140329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
140330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
140331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
140332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
140333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
140334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
140335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
140336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
140337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
140338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
140339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
140340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
140341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
140342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
140343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
140344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
140345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
140346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
140347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
140348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
140349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
140350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
140351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
140352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
140353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
140354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
140355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
140356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
140357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
140358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
140359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
140360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
140361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
140362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
140363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
140364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
140365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
140366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
140367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
140368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
140369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
140370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
140371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
140372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
140373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
140374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
140375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
140376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
140377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
140378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
140379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
140380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
140381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
140382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
140383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
140384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
140385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
140386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
140387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
140388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
140389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
140390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
140391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
140392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
140393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
140394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
140395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
140396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
140397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
140398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
140399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
140400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
140401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
140402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
140403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
140404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
140405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
140406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
140407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
140408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
140409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
140410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
140411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
140412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
140413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
140414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
140415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
140416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
140417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
140418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
140419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
140420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
140421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
140422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
140423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
140424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
140425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
140426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
140427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
140428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
140429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
140430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
140431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
140432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
140433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
140434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
140435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
140436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
140437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
140438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
140439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
140440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
140441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
140442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
140443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
140444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
140445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
140446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
140447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
140448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
140449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
140450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
140451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
140452 };
140453 
140459 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
140460 {
140461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
140462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
140463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
140464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
140465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
140466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
140467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
140468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
140469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
140470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
140471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
140472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
140473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
140474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
140475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
140476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
140477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
140478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
140479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
140480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
140481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
140482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
140483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
140484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
140485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
140486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
140487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
140488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
140489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
140490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
140491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
140492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
140493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
140494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
140495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
140496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
140497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
140498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
140499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
140500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
140501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
140502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
140503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
140504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
140505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
140506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
140507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
140508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
140509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
140510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
140511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
140512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
140513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
140514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
140515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
140516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
140517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
140518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
140519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
140520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
140521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
140522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
140523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
140524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
140525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
140526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
140527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
140528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
140529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
140530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
140531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
140532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
140533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
140534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
140535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
140536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
140537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
140538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
140539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
140540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
140541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
140542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
140543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
140544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
140545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
140546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
140547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
140548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
140549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
140550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
140551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
140552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
140553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
140554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
140555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
140556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
140557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
140558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
140559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
140560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
140561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
140562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
140563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
140564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
140565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
140566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
140567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
140568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
140569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
140570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
140571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
140572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
140573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
140574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
140575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
140576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
140577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
140578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
140579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
140580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
140581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
140582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
140583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
140584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
140585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
140586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
140587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
140588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
140589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
140590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
140591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
140592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
140593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
140594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
140595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
140596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
140597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
140598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
140599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
140600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
140601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
140602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
140603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
140604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
140605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
140606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
140607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
140608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
140609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
140610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
140611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
140612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
140613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
140614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
140615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
140616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
140617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
140618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
140619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
140620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
140621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
140622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
140623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
140624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
140625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
140626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
140627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
140628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
140629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
140630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
140631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
140632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
140633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
140634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
140635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
140636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
140637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
140638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
140639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
140640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
140641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
140642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
140643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
140644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
140645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
140646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
140647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
140648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
140649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
140650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
140651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
140652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
140653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
140654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
140655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
140656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
140657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
140658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
140659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
140660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
140661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
140662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
140663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
140664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
140665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
140666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
140667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
140668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
140669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
140670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
140671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
140672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
140673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
140674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
140675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
140676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
140677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
140678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
140679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
140680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
140681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
140682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
140683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
140684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
140685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
140686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
140687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
140688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
140689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
140690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
140691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
140692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
140693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
140694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
140695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
140696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
140697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
140698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
140699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
140700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
140701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
140702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
140703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
140704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
140705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
140706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
140707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
140708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
140709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
140710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
140711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
140712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
140713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
140714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
140715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
140716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
140717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
140718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
140719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
140720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
140721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
140722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
140723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
140724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
140725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
140726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
140727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_133_CHECKER_TYPE,
140728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
140729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_134_CHECKER_TYPE,
140730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
140731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_135_CHECKER_TYPE,
140732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
140733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_136_CHECKER_TYPE,
140734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
140735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_137_CHECKER_TYPE,
140736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
140737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_138_CHECKER_TYPE,
140738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
140739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_139_CHECKER_TYPE,
140740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
140741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_140_CHECKER_TYPE,
140742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
140743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_141_CHECKER_TYPE,
140744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
140745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_142_CHECKER_TYPE,
140746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
140747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_143_CHECKER_TYPE,
140748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
140749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_144_CHECKER_TYPE,
140750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
140751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_145_CHECKER_TYPE,
140752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
140753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_146_CHECKER_TYPE,
140754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
140755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_147_CHECKER_TYPE,
140756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
140757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_148_CHECKER_TYPE,
140758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
140759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_149_CHECKER_TYPE,
140760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
140761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_150_CHECKER_TYPE,
140762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
140763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_151_CHECKER_TYPE,
140764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
140765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_152_CHECKER_TYPE,
140766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
140767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_153_CHECKER_TYPE,
140768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
140769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_154_CHECKER_TYPE,
140770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
140771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_155_CHECKER_TYPE,
140772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
140773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_156_CHECKER_TYPE,
140774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
140775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_157_CHECKER_TYPE,
140776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
140777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_158_CHECKER_TYPE,
140778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
140779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_159_CHECKER_TYPE,
140780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
140781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_160_CHECKER_TYPE,
140782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
140783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_161_CHECKER_TYPE,
140784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
140785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_162_CHECKER_TYPE,
140786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
140787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_163_CHECKER_TYPE,
140788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
140789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_164_CHECKER_TYPE,
140790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
140791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_165_CHECKER_TYPE,
140792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
140793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_166_CHECKER_TYPE,
140794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_166_WIDTH },
140795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_167_CHECKER_TYPE,
140796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_167_WIDTH },
140797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_168_CHECKER_TYPE,
140798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_GROUP_168_WIDTH },
140799 };
140800 
140806 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
140807 {
140808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
140809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
140810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
140811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
140812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
140813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
140814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
140815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
140816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
140817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
140818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
140819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
140820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
140821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
140822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
140823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
140824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
140825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
140826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
140827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
140828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
140829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
140830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
140831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
140832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
140833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
140834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
140835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
140836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
140837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
140838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
140839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
140840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
140841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
140842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
140843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
140844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
140845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
140846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
140847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
140848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
140849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
140850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
140851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
140852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
140853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
140854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
140855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
140856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
140857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
140858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
140859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
140860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
140861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
140862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
140863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
140864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
140865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
140866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
140867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
140868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
140869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
140870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
140871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
140872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
140873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
140874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
140875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
140876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
140877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
140878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
140879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
140880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
140881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
140882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
140883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
140884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
140885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
140886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
140887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
140888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
140889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
140890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
140891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
140892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
140893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
140894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
140895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
140896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
140897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
140898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
140899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
140900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
140901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
140902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
140903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
140904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
140905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
140906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
140907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
140908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
140909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
140910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
140911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
140912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
140913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
140914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
140915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
140916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
140917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
140918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
140919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
140920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
140921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
140922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
140923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
140924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
140925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
140926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
140927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
140928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
140929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
140930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
140931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
140932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
140933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
140934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
140935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
140936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
140937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
140938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
140939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
140940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
140941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
140942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
140943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
140944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
140945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
140946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
140947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
140948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
140949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
140950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
140951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
140952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
140953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
140954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
140955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
140956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
140957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
140958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
140959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
140960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
140961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
140962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
140963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
140964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
140965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
140966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
140967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
140968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
140969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
140970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
140971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
140972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
140973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
140974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
140975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
140976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
140977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
140978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
140979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
140980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
140981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
140982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
140983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
140984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
140985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
140986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
140987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
140988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
140989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
140990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
140991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
140992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
140993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
140994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
140995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
140996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
140997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
140998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
140999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
141000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
141001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
141002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
141003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
141004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
141005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
141006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
141007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
141008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
141009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
141010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
141011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
141012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
141013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
141014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
141015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
141016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
141017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
141018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
141019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
141020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
141021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
141022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
141023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
141024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
141025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
141026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
141027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
141028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
141029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
141030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
141031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
141032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
141033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
141034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
141035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
141036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
141037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
141038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
141039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
141040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
141041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
141042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
141043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
141044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
141045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
141046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
141047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
141048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
141049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
141050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
141051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
141052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
141053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
141054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
141055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
141056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
141057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
141058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
141059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
141060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
141061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
141062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
141063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
141064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
141065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
141066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
141067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
141068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
141069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
141070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
141071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
141072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
141073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
141074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
141075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
141076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
141077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
141078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
141079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
141080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
141081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
141082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
141083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
141084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
141085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
141086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
141087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
141088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
141089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
141090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
141091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
141092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
141093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
141094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
141095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
141096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
141097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
141098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
141099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
141100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
141101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
141102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
141103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
141104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
141105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
141106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
141107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
141108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
141109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
141110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
141111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
141112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
141113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
141114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
141115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
141116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
141117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
141118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
141119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
141120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
141121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
141122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
141123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
141124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
141125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
141126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
141127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
141128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
141129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
141130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
141131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
141132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
141133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
141134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
141135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
141136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
141137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
141138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
141139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
141140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
141141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
141142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
141143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
141144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
141145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
141146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
141147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
141148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
141149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
141150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
141151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
141152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
141153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
141154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
141155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
141156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
141157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
141158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
141159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
141160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
141161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
141162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
141163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
141164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
141165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
141166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
141167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
141168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
141169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
141170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
141171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
141172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
141173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
141174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
141175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
141176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
141177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
141178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
141179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
141180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
141181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
141182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
141183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
141184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
141185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
141186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
141187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
141188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
141189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
141190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
141191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
141192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
141193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
141194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
141195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
141196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
141197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
141198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
141199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
141200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
141201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
141202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
141203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
141204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
141205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
141206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
141207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
141208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
141209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
141210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
141211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
141212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
141213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
141214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
141215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
141216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
141217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
141218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
141219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
141220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
141221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
141222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
141223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
141224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
141225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
141226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
141227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
141228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
141229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
141230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
141231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
141232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
141233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
141234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
141235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
141236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
141237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
141238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
141239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
141240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
141241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
141242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
141243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
141244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
141245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
141246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
141247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
141248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
141249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
141250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
141251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
141252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
141253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
141254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
141255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
141256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
141257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
141258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
141259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
141260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
141261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
141262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
141263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
141264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
141265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
141266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
141267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
141268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
141269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
141270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
141271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
141272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
141273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
141274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
141275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
141276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
141277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
141278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
141279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
141280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
141281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
141282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
141283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
141284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
141285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
141286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
141287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
141288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
141289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
141290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
141291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
141292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
141293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
141294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
141295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
141296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
141297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
141298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
141299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
141300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
141301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
141302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
141303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
141304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
141305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
141306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
141307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
141308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
141309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
141310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
141311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
141312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
141313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
141314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
141315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
141316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
141317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
141318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
141319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
141320 };
141321 
141327 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
141328 {
141329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
141330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
141331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
141332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
141333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
141334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
141335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
141336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
141337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
141338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
141339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
141340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
141341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
141342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
141343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
141344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
141345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
141346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
141347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
141348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
141349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
141350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
141351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
141352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
141353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
141354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
141355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
141356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
141357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
141358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
141359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
141360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
141361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
141362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
141363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
141364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
141365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
141366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
141367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
141368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
141369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
141370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
141371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
141372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
141373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
141374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
141375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
141376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
141377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
141378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
141379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
141380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
141381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
141382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
141383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
141384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
141385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
141386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
141387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
141388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
141389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
141390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
141391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
141392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
141393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
141394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
141395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
141396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
141397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
141398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
141399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
141400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
141401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
141402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
141403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
141404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
141405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
141406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
141407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
141408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
141409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
141410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
141411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
141412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
141413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
141414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
141415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
141416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
141417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
141418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
141419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
141420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
141421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
141422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
141423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
141424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
141425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
141426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
141427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
141428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
141429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
141430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
141431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
141432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
141433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
141434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
141435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
141436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
141437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
141438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
141439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
141440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
141441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
141442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
141443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
141444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
141445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
141446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
141447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
141448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
141449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
141450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
141451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
141452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
141453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
141454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
141455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
141456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
141457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
141458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
141459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
141460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
141461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
141462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
141463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
141464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
141465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
141466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
141467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
141468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
141469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
141470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
141471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
141472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
141473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
141474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
141475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
141476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
141477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
141478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
141479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
141480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
141481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
141482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
141483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
141484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
141485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
141486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
141487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
141488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
141489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
141490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
141491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
141492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
141493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
141494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
141495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
141496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
141497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
141498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
141499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
141500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
141501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
141502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
141503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
141504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
141505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
141506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
141507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
141508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
141509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
141510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
141511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
141512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
141513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
141514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
141515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
141516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
141517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
141518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
141519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
141520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
141521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
141522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
141523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
141524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
141525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
141526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
141527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
141528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
141529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
141530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
141531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
141532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
141533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
141534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
141535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
141536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
141537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
141538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
141539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
141540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
141541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
141542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
141543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
141544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
141545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
141546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
141547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
141548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
141549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
141550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
141551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
141552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
141553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
141554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
141555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
141556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
141557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
141558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
141559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
141560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
141561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
141562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
141563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
141564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
141565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
141566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
141567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
141568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
141569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
141570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
141571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
141572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
141573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
141574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
141575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
141576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
141577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
141578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
141579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
141580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
141581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
141582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
141583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
141584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
141585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
141586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
141587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
141588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
141589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
141590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
141591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
141592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
141593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
141594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
141595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
141596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
141597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
141598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
141599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
141600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
141601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
141602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
141603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
141604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
141605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
141606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
141607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
141608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
141609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
141610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
141611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
141612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
141613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
141614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
141615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
141616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
141617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
141618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
141619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
141620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
141621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
141622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
141623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
141624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
141625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
141626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
141627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
141628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
141629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
141630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
141631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
141632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
141633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
141634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
141635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
141636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
141637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
141638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
141639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
141640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
141641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
141642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
141643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
141644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
141645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
141646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
141647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
141648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
141649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
141650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
141651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
141652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
141653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
141654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
141655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
141656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
141657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
141658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
141659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
141660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
141661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
141662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
141663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
141664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
141665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
141666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
141667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
141668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
141669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
141670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
141671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
141672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
141673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
141674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
141675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
141676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
141677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
141678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
141679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
141680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
141681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
141682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
141683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
141684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
141685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
141686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
141687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
141688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
141689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
141690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
141691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
141692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
141693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
141694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
141695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
141696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
141697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
141698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
141699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
141700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
141701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
141702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
141703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
141704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
141705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
141706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
141707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
141708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
141709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
141710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
141711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
141712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
141713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
141714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
141715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
141716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
141717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
141718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
141719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
141720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
141721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
141722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
141723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
141724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
141725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
141726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
141727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
141728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
141729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
141730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
141731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
141732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
141733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
141734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
141735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
141736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
141737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
141738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
141739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
141740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
141741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
141742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
141743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
141744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
141745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
141746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
141747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
141748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
141749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
141750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
141751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
141752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
141753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
141754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
141755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
141756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
141757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
141758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
141759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
141760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
141761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
141762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
141763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
141764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
141765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
141766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
141767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
141768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
141769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
141770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
141771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
141772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
141773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
141774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
141775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
141776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
141777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
141778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
141779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
141780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
141781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
141782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
141783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
141784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
141785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
141786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
141787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
141788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
141789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
141790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
141791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
141792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
141793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
141794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
141795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
141796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
141797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
141798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
141799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
141800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
141801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
141802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
141803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
141804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
141805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
141806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
141807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
141808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
141809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
141810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
141811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
141812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
141813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
141814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
141815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
141816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
141817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
141818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
141819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
141820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
141821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
141822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
141823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
141824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
141825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
141826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
141827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
141828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
141829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
141830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
141831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
141832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
141833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
141834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
141835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
141836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
141837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
141838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
141839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
141840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
141841 };
141842 
141848 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
141849 {
141850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
141851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
141852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
141853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
141854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
141855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
141856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
141857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
141858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
141859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
141860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
141861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
141862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
141863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
141864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
141865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
141866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
141867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
141868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
141869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
141870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
141871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
141872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
141873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
141874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
141875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
141876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
141877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
141878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
141879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
141880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
141881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
141882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
141883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
141884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
141885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
141886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
141887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
141888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
141889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
141890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
141891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
141892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
141893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
141894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
141895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
141896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
141897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
141898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
141899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
141900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
141901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
141902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
141903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
141904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
141905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
141906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
141907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
141908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
141909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
141910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
141911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
141912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
141913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
141914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
141915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
141916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
141917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
141918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
141919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
141920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
141921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
141922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
141923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
141924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
141925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
141926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
141927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
141928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
141929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
141930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
141931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
141932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
141933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
141934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
141935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
141936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
141937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
141938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
141939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
141940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
141941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
141942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
141943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
141944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
141945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
141946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
141947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
141948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
141949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
141950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
141951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
141952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
141953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
141954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
141955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
141956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
141957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
141958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
141959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
141960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
141961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
141962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
141963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
141964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
141965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
141966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
141967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
141968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
141969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
141970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
141971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
141972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
141973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
141974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
141975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
141976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
141977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
141978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
141979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
141980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
141981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
141982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
141983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
141984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
141985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
141986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
141987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
141988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
141989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
141990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
141991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
141992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
141993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
141994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
141995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
141996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
141997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
141998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
141999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
142000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
142001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
142002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
142003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
142004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
142005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
142006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
142007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
142008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
142009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
142010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
142011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
142012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
142013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
142014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
142015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
142016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
142017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
142018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
142019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
142020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
142021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
142022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
142023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
142024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
142025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
142026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
142027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
142028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
142029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
142030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
142031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
142032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
142033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
142034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
142035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
142036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
142037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
142038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
142039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
142040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
142041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
142042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
142043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
142044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
142045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
142046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
142047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
142048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
142049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
142050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
142051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
142052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
142053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
142054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
142055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
142056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
142057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
142058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
142059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
142060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
142061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
142062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
142063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
142064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
142065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
142066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
142067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
142068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
142069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
142070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
142071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
142072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
142073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
142074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
142075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
142076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
142077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
142078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
142079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
142080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
142081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
142082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
142083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
142084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
142085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
142086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
142087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
142088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
142089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
142090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
142091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
142092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
142093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
142094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
142095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
142096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
142097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
142098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
142099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
142100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
142101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
142102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
142103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
142104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
142105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
142106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
142107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
142108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
142109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
142110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
142111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
142112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
142113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
142114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
142115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
142116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
142117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
142118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
142119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
142120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
142121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
142122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
142123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
142124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
142125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
142126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
142127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
142128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
142129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
142130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
142131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
142132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
142133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
142134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
142135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
142136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
142137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
142138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
142139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
142140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
142141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
142142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
142143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
142144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
142145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
142146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
142147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
142148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
142149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
142150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
142151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
142152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
142153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
142154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
142155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
142156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
142157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
142158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
142159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
142160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
142161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
142162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
142163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
142164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
142165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
142166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
142167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
142168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
142169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
142170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
142171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
142172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
142173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
142174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
142175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
142176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
142177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
142178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
142179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
142180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
142181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
142182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
142183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
142184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
142185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
142186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
142187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
142188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
142189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
142190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
142191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
142192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
142193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
142194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
142195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
142196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
142197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
142198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
142199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
142200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
142201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
142202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
142203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
142204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
142205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
142206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
142207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
142208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
142209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
142210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
142211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
142212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
142213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
142214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
142215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
142216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
142217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
142218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
142219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
142220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
142221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
142222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
142223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
142224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
142225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
142226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
142227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
142228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
142229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
142230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
142231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
142232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
142233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
142234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
142235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
142236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
142237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
142238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
142239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
142240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
142241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
142242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
142243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
142244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
142245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
142246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
142247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
142248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
142249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
142250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
142251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
142252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
142253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
142254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
142255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
142256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
142257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
142258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
142259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
142260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
142261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
142262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
142263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
142264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
142265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
142266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
142267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
142268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
142269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
142270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
142271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
142272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
142273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
142274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
142275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
142276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
142277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
142278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
142279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
142280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
142281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
142282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
142283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
142284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
142285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
142286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
142287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
142288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
142289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
142290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
142291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
142292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
142293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
142294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
142295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
142296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
142297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
142298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
142299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
142300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
142301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
142302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
142303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
142304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
142305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
142306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
142307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
142308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
142309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
142310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
142311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
142312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
142313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
142314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
142315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
142316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
142317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
142318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
142319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
142320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
142321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
142322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
142323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
142324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
142325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
142326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
142327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
142328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
142329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
142330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
142331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
142332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
142333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
142334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
142335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
142336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
142337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
142338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
142339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
142340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
142341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
142342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
142343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
142344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
142345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
142346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
142347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
142348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
142349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
142350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
142351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
142352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
142353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
142354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
142355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
142356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
142357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
142358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
142359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
142360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
142361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
142362 };
142363 
142369 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
142370 {
142371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
142372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
142373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
142374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
142375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
142376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
142377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
142378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
142379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
142380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
142381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
142382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
142383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
142384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
142385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
142386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
142387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
142388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
142389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
142390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
142391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
142392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
142393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
142394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
142395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
142396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
142397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
142398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
142399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
142400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
142401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
142402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
142403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
142404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
142405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
142406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
142407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
142408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
142409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
142410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
142411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
142412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
142413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
142414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
142415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
142416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
142417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
142418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
142419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
142420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
142421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
142422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
142423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
142424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
142425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
142426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
142427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
142428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
142429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
142430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
142431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
142432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
142433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
142434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
142435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
142436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
142437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
142438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
142439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
142440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
142441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
142442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
142443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
142444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
142445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
142446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
142447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
142448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
142449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
142450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
142451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
142452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
142453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
142454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
142455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
142456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
142457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
142458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
142459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
142460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
142461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
142462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
142463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
142464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
142465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
142466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
142467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
142468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
142469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
142470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
142471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
142472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
142473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
142474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
142475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
142476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
142477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
142478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
142479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
142480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
142481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
142482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
142483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
142484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
142485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
142486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
142487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
142488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
142489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
142490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
142491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
142492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
142493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
142494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
142495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
142496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
142497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
142498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
142499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
142500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
142501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
142502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
142503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
142504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
142505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
142506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
142507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
142508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
142509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
142510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
142511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
142512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
142513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
142514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
142515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
142516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
142517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
142518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
142519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
142520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
142521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
142522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
142523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
142524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
142525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
142526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
142527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
142528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
142529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
142530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
142531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
142532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
142533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
142534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
142535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
142536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
142537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
142538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
142539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
142540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
142541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
142542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
142543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
142544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
142545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
142546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
142547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
142548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
142549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
142550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
142551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
142552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
142553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
142554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
142555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
142556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
142557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
142558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
142559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
142560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
142561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
142562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
142563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
142564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
142565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
142566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
142567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
142568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
142569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
142570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
142571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
142572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
142573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
142574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
142575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
142576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
142577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
142578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
142579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
142580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
142581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
142582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
142583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
142584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
142585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
142586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
142587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
142588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
142589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
142590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
142591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
142592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
142593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
142594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
142595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
142596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
142597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
142598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
142599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
142600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
142601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
142602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
142603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
142604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
142605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
142606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
142607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
142608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
142609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
142610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
142611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
142612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
142613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
142614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
142615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
142616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
142617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
142618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
142619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
142620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
142621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
142622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
142623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
142624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
142625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
142626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
142627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
142628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
142629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
142630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
142631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
142632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
142633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
142634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
142635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
142636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
142637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
142638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
142639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
142640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
142641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
142642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
142643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
142644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
142645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
142646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
142647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
142648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
142649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
142650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
142651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
142652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
142653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
142654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
142655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
142656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
142657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
142658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
142659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
142660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
142661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
142662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
142663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
142664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
142665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
142666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
142667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
142668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
142669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
142670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
142671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
142672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
142673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
142674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
142675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
142676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
142677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
142678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
142679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
142680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
142681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
142682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
142683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
142684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
142685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
142686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
142687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
142688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
142689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
142690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
142691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
142692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
142693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
142694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
142695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
142696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
142697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
142698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
142699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
142700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
142701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
142702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
142703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
142704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
142705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
142706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
142707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
142708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
142709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
142710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
142711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
142712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
142713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
142714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
142715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
142716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
142717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
142718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
142719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
142720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
142721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
142722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
142723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
142724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
142725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
142726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
142727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
142728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
142729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
142730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
142731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
142732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
142733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
142734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
142735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
142736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
142737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
142738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
142739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
142740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
142741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
142742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
142743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
142744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
142745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
142746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
142747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
142748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
142749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
142750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
142751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
142752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
142753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
142754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
142755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
142756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
142757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
142758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
142759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
142760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
142761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
142762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
142763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
142764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
142765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
142766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
142767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
142768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
142769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
142770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
142771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
142772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
142773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
142774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
142775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
142776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
142777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
142778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
142779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
142780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
142781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
142782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
142783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
142784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
142785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
142786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
142787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
142788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
142789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
142790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
142791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
142792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
142793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
142794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
142795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
142796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
142797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
142798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
142799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
142800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
142801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
142802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
142803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
142804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
142805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
142806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
142807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
142808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
142809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
142810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
142811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
142812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
142813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
142814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
142815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
142816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
142817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
142818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
142819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
142820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
142821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
142822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
142823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
142824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
142825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
142826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
142827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
142828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
142829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
142830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
142831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
142832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
142833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
142834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
142835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
142836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
142837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
142838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
142839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
142840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
142841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
142842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
142843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
142844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
142845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
142846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
142847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
142848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
142849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
142850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
142851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
142852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
142853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
142854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
142855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
142856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
142857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
142858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
142859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
142860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
142861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
142862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
142863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
142864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
142865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
142866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
142867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
142868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
142869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
142870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
142871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
142872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
142873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
142874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
142875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
142876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
142877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
142878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
142879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
142880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
142881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
142882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
142883 };
142884 
142890 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
142891 {
142892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
142893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
142894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
142895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
142896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
142897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
142898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
142899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
142900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
142901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
142902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
142903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
142904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
142905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
142906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
142907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
142908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
142909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
142910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
142911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
142912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
142913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
142914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
142915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
142916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
142917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
142918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
142919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
142920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
142921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
142922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
142923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
142924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
142925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
142926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
142927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
142928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
142929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
142930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
142931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
142932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
142933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
142934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
142935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
142936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
142937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
142938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
142939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
142940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
142941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
142942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
142943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
142944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
142945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
142946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
142947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
142948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
142949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
142950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
142951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
142952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
142953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
142954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
142955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
142956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
142957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
142958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
142959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
142960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
142961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
142962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
142963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
142964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
142965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
142966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
142967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
142968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
142969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
142970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
142971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
142972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
142973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
142974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
142975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
142976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
142977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
142978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
142979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
142980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
142981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
142982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
142983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
142984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
142985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
142986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
142987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
142988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
142989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
142990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
142991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
142992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
142993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
142994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
142995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
142996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
142997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
142998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
142999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
143000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
143001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
143002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
143003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
143004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
143005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
143006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
143007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
143008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
143009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
143010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
143011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
143012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
143013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
143014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
143015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
143016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
143017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
143018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
143019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
143020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
143021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
143022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
143023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
143024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
143025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
143026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
143027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
143028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
143029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
143030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
143031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
143032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
143033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
143034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
143035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
143036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
143037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
143038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
143039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
143040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
143041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
143042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
143043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
143044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
143045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
143046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
143047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
143048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
143049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
143050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
143051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
143052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
143053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
143054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
143055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
143056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
143057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
143058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
143059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
143060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
143061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
143062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
143063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
143064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
143065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
143066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
143067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
143068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
143069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
143070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
143071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
143072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
143073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
143074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
143075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
143076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
143077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
143078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
143079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
143080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
143081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
143082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
143083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
143084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
143085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
143086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
143087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
143088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
143089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
143090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
143091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
143092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
143093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
143094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
143095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
143096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
143097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
143098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
143099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
143100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
143101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
143102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
143103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
143104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
143105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
143106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
143107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
143108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
143109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
143110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
143111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
143112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
143113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
143114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
143115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
143116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
143117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
143118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
143119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
143120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
143121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
143122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
143123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
143124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
143125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
143126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
143127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
143128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
143129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
143130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
143131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
143132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
143133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
143134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
143135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
143136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
143137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
143138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
143139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
143140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
143141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
143142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
143143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
143144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
143145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
143146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
143147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
143148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
143149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
143150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
143151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
143152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
143153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
143154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
143155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
143156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
143157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
143158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
143159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
143160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
143161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
143162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
143163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
143164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
143165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
143166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
143167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
143168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
143169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
143170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
143171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
143172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
143173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
143174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
143175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
143176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
143177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
143178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
143179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
143180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
143181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
143182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
143183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
143184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
143185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
143186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
143187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
143188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
143189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
143190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
143191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
143192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
143193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
143194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
143195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
143196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
143197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
143198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
143199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
143200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
143201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
143202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
143203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
143204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
143205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
143206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
143207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
143208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
143209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
143210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
143211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
143212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
143213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
143214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
143215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
143216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
143217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
143218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
143219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
143220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
143221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
143222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
143223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
143224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
143225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
143226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
143227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
143228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
143229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
143230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
143231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
143232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
143233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
143234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
143235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
143236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
143237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
143238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
143239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
143240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
143241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
143242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
143243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
143244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
143245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
143246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
143247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
143248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
143249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
143250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
143251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
143252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
143253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
143254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
143255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
143256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
143257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
143258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
143259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
143260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
143261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
143262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
143263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
143264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
143265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
143266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
143267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
143268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
143269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
143270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
143271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
143272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
143273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
143274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
143275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
143276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
143277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
143278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
143279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
143280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
143281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
143282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
143283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
143284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
143285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
143286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
143287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
143288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
143289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
143290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
143291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
143292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
143293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
143294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
143295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
143296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
143297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
143298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
143299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
143300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
143301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
143302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
143303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
143304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
143305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
143306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
143307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
143308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
143309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
143310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
143311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
143312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
143313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
143314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
143315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
143316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
143317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
143318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
143319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
143320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
143321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
143322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
143323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
143324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
143325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
143326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
143327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
143328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
143329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
143330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
143331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
143332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
143333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
143334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
143335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
143336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
143337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
143338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
143339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
143340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
143341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
143342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
143343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
143344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
143345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
143346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
143347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
143348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
143349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
143350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
143351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
143352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
143353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
143354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
143355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
143356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
143357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
143358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
143359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
143360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
143361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
143362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
143363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
143364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
143365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
143366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
143367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
143368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
143369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
143370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
143371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
143372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
143373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
143374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
143375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
143376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
143377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
143378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
143379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
143380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
143381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
143382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
143383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
143384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
143385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
143386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
143387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
143388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
143389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
143390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
143391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
143392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
143393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
143394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
143395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
143396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
143397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
143398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
143399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
143400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
143401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
143402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
143403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
143404 };
143405 
143411 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
143412 {
143413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
143414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
143415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
143416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
143417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
143418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
143419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
143420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
143421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
143422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
143423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
143424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
143425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
143426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
143427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
143428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
143429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
143430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
143431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
143432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
143433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
143434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
143435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
143436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
143437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
143438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
143439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
143440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
143441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
143442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
143443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
143444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
143445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
143446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
143447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
143448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
143449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
143450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
143451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
143452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
143453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
143454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
143455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
143456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
143457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
143458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
143459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
143460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
143461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
143462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
143463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
143464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
143465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
143466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
143467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
143468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
143469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
143470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
143471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
143472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
143473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
143474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
143475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
143476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
143477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
143478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
143479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
143480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
143481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
143482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
143483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
143484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
143485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
143486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
143487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
143488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
143489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
143490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
143491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
143492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
143493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
143494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
143495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
143496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
143497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
143498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
143499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
143500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
143501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
143502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
143503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
143504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
143505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
143506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
143507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
143508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
143509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
143510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
143511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
143512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
143513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
143514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
143515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
143516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
143517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
143518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
143519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
143520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
143521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
143522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
143523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
143524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
143525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
143526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
143527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
143528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
143529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
143530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
143531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
143532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
143533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
143534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
143535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
143536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
143537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
143538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
143539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
143540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
143541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
143542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
143543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
143544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
143545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
143546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
143547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
143548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
143549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
143550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
143551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
143552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
143553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
143554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
143555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
143556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
143557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
143558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
143559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
143560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
143561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
143562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
143563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
143564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
143565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
143566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
143567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
143568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
143569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
143570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
143571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
143572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
143573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
143574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
143575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
143576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
143577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
143578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
143579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
143580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
143581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
143582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
143583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
143584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
143585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
143586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
143587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
143588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
143589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
143590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
143591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
143592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
143593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
143594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
143595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
143596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
143597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
143598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
143599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
143600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
143601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
143602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
143603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
143604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
143605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
143606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
143607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
143608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
143609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
143610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
143611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
143612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
143613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
143614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
143615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
143616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
143617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
143618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
143619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
143620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
143621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
143622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
143623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
143624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
143625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
143626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
143627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
143628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
143629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
143630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
143631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
143632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
143633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
143634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
143635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
143636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
143637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
143638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
143639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
143640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
143641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
143642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
143643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
143644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
143645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
143646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
143647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
143648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
143649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
143650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
143651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
143652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
143653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
143654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
143655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
143656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
143657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
143658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
143659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
143660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
143661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
143662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
143663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
143664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
143665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
143666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
143667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
143668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
143669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
143670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
143671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
143672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
143673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
143674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
143675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
143676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
143677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
143678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
143679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
143680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
143681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
143682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
143683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
143684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
143685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
143686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
143687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
143688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
143689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
143690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
143691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
143692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
143693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
143694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
143695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
143696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
143697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
143698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
143699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
143700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
143701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
143702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
143703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
143704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
143705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
143706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
143707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
143708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
143709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
143710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
143711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
143712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
143713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
143714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
143715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
143716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
143717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
143718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
143719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
143720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
143721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
143722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
143723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
143724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
143725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
143726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
143727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
143728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
143729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
143730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
143731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
143732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
143733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
143734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
143735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
143736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
143737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
143738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
143739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
143740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
143741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
143742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
143743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
143744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
143745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
143746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
143747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
143748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
143749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
143750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
143751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
143752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
143753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
143754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
143755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
143756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
143757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
143758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
143759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
143760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
143761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
143762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
143763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
143764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
143765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
143766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
143767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
143768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
143769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
143770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
143771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
143772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
143773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
143774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
143775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
143776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
143777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
143778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
143779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
143780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
143781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
143782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
143783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
143784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
143785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
143786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
143787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
143788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
143789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
143790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
143791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
143792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
143793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
143794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
143795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
143796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
143797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
143798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
143799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
143800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
143801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
143802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
143803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
143804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
143805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
143806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
143807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
143808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
143809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
143810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
143811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
143812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
143813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
143814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
143815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
143816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
143817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
143818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
143819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
143820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
143821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
143822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
143823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
143824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
143825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
143826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
143827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
143828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
143829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
143830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
143831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
143832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
143833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
143834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
143835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
143836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
143837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
143838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
143839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
143840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
143841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
143842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
143843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
143844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
143845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
143846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
143847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
143848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
143849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
143850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
143851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
143852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
143853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
143854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
143855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
143856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
143857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
143858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
143859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
143860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
143861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
143862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
143863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
143864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
143865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
143866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
143867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
143868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
143869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
143870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
143871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
143872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
143873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
143874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
143875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
143876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
143877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
143878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
143879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
143880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
143881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
143882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
143883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
143884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
143885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
143886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
143887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
143888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
143889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
143890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
143891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
143892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
143893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
143894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
143895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
143896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
143897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
143898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
143899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
143900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
143901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
143902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
143903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
143904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
143905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
143906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
143907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
143908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
143909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
143910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
143911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
143912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
143913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
143914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
143915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
143916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
143917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
143918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
143919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
143920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
143921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
143922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
143923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
143924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
143925 };
143926 
143932 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
143933 {
143934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
143935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
143936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
143937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
143938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
143939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
143940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
143941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
143942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
143943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
143944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
143945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
143946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
143947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
143948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
143949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
143950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
143951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
143952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
143953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
143954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
143955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
143956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
143957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
143958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
143959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
143960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
143961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
143962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
143963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
143964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
143965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
143966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
143967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
143968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
143969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
143970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
143971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
143972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
143973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
143974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
143975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
143976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
143977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
143978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
143979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
143980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
143981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
143982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
143983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
143984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
143985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
143986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
143987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
143988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
143989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
143990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
143991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
143992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
143993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
143994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
143995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
143996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
143997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
143998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
143999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
144000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
144001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
144002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
144003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
144004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
144005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
144006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
144007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
144008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
144009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
144010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
144011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
144012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
144013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
144014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
144015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
144016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
144017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
144018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
144019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
144020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
144021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
144022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
144023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
144024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
144025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
144026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
144027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
144028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
144029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
144030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
144031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
144032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
144033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
144034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
144035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
144036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
144037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
144038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
144039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
144040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
144041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
144042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
144043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
144044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
144045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
144046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
144047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
144048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
144049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
144050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
144051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
144052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
144053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
144054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
144055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
144056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
144057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
144058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
144059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
144060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
144061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
144062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
144063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
144064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
144065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
144066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
144067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
144068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
144069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
144070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
144071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
144072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
144073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
144074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
144075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
144076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
144077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
144078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
144079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
144080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
144081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
144082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
144083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
144084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
144085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
144086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
144087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
144088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
144089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
144090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
144091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
144092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
144093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
144094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
144095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
144096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
144097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
144098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
144099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
144100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
144101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
144102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
144103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
144104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
144105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
144106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
144107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
144108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
144109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
144110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
144111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
144112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
144113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
144114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
144115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
144116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
144117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
144118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
144119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
144120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
144121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
144122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
144123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
144124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
144125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
144126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
144127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
144128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
144129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
144130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
144131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
144132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
144133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
144134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
144135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
144136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
144137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
144138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
144139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
144140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
144141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
144142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
144143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
144144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
144145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
144146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
144147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
144148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
144149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
144150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
144151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
144152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
144153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
144154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
144155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
144156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
144157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
144158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
144159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
144160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
144161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
144162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
144163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
144164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
144165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
144166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
144167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
144168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
144169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
144170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
144171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
144172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
144173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
144174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
144175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
144176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
144177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
144178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
144179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
144180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
144181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
144182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
144183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
144184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
144185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
144186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
144187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
144188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
144189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
144190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
144191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
144192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
144193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
144194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
144195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
144196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
144197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
144198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
144199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
144200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
144201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
144202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
144203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
144204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
144205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
144206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
144207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
144208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
144209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
144210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
144211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
144212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
144213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
144214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
144215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
144216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
144217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
144218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
144219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
144220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
144221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
144222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
144223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
144224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
144225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
144226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
144227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
144228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
144229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
144230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
144231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
144232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
144233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
144234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
144235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
144236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
144237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
144238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
144239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
144240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
144241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
144242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
144243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
144244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
144245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
144246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
144247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
144248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
144249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
144250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
144251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
144252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
144253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
144254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
144255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
144256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
144257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
144258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
144259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
144260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
144261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
144262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
144263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
144264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
144265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
144266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
144267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
144268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
144269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
144270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
144271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
144272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
144273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
144274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
144275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
144276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
144277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
144278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
144279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
144280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
144281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
144282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
144283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
144284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
144285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
144286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
144287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
144288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
144289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
144290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
144291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
144292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
144293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
144294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
144295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
144296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
144297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
144298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
144299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
144300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
144301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
144302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
144303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
144304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
144305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
144306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
144307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
144308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_CHECKER_TYPE,
144309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_WIDTH },
144310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_CHECKER_TYPE,
144311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_WIDTH },
144312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_CHECKER_TYPE,
144313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_WIDTH },
144314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_CHECKER_TYPE,
144315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_WIDTH },
144316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_CHECKER_TYPE,
144317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_WIDTH },
144318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_CHECKER_TYPE,
144319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_WIDTH },
144320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_CHECKER_TYPE,
144321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_WIDTH },
144322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_CHECKER_TYPE,
144323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_WIDTH },
144324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_CHECKER_TYPE,
144325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_WIDTH },
144326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_CHECKER_TYPE,
144327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_WIDTH },
144328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_CHECKER_TYPE,
144329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_WIDTH },
144330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_CHECKER_TYPE,
144331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_WIDTH },
144332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_CHECKER_TYPE,
144333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_WIDTH },
144334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_CHECKER_TYPE,
144335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_WIDTH },
144336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_CHECKER_TYPE,
144337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_WIDTH },
144338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_CHECKER_TYPE,
144339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_WIDTH },
144340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_CHECKER_TYPE,
144341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_WIDTH },
144342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_CHECKER_TYPE,
144343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_WIDTH },
144344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_CHECKER_TYPE,
144345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_WIDTH },
144346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_CHECKER_TYPE,
144347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_WIDTH },
144348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_CHECKER_TYPE,
144349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_WIDTH },
144350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_CHECKER_TYPE,
144351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_WIDTH },
144352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_CHECKER_TYPE,
144353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_WIDTH },
144354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_CHECKER_TYPE,
144355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_WIDTH },
144356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_CHECKER_TYPE,
144357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_WIDTH },
144358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_CHECKER_TYPE,
144359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_WIDTH },
144360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_CHECKER_TYPE,
144361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_WIDTH },
144362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_CHECKER_TYPE,
144363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_WIDTH },
144364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_CHECKER_TYPE,
144365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_WIDTH },
144366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_CHECKER_TYPE,
144367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_WIDTH },
144368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_CHECKER_TYPE,
144369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_WIDTH },
144370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_CHECKER_TYPE,
144371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_WIDTH },
144372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_CHECKER_TYPE,
144373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_WIDTH },
144374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_CHECKER_TYPE,
144375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_WIDTH },
144376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_CHECKER_TYPE,
144377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_WIDTH },
144378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_CHECKER_TYPE,
144379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_WIDTH },
144380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_CHECKER_TYPE,
144381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_WIDTH },
144382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_CHECKER_TYPE,
144383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_WIDTH },
144384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_CHECKER_TYPE,
144385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_WIDTH },
144386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_CHECKER_TYPE,
144387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_WIDTH },
144388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_CHECKER_TYPE,
144389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_WIDTH },
144390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_CHECKER_TYPE,
144391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_WIDTH },
144392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_CHECKER_TYPE,
144393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_WIDTH },
144394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_CHECKER_TYPE,
144395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_WIDTH },
144396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_CHECKER_TYPE,
144397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_WIDTH },
144398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_CHECKER_TYPE,
144399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_WIDTH },
144400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_CHECKER_TYPE,
144401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_WIDTH },
144402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_CHECKER_TYPE,
144403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_WIDTH },
144404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_CHECKER_TYPE,
144405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_WIDTH },
144406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_CHECKER_TYPE,
144407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_WIDTH },
144408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_CHECKER_TYPE,
144409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_WIDTH },
144410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_CHECKER_TYPE,
144411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_WIDTH },
144412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_CHECKER_TYPE,
144413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_WIDTH },
144414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_CHECKER_TYPE,
144415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_WIDTH },
144416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_CHECKER_TYPE,
144417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_WIDTH },
144418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_CHECKER_TYPE,
144419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_WIDTH },
144420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_CHECKER_TYPE,
144421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_WIDTH },
144422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_CHECKER_TYPE,
144423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_WIDTH },
144424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_CHECKER_TYPE,
144425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_WIDTH },
144426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_CHECKER_TYPE,
144427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_WIDTH },
144428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_CHECKER_TYPE,
144429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_WIDTH },
144430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_CHECKER_TYPE,
144431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_WIDTH },
144432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_CHECKER_TYPE,
144433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_WIDTH },
144434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_CHECKER_TYPE,
144435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_WIDTH },
144436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_CHECKER_TYPE,
144437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_WIDTH },
144438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_CHECKER_TYPE,
144439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_WIDTH },
144440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_CHECKER_TYPE,
144441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_WIDTH },
144442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_CHECKER_TYPE,
144443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_WIDTH },
144444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_CHECKER_TYPE,
144445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_WIDTH },
144446 };
144447 
144453 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS] =
144454 {
144455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_CHECKER_TYPE,
144456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_WIDTH },
144457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_CHECKER_TYPE,
144458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_WIDTH },
144459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_CHECKER_TYPE,
144460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_WIDTH },
144461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_CHECKER_TYPE,
144462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_WIDTH },
144463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_CHECKER_TYPE,
144464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_WIDTH },
144465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_CHECKER_TYPE,
144466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_WIDTH },
144467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_CHECKER_TYPE,
144468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_WIDTH },
144469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_CHECKER_TYPE,
144470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_WIDTH },
144471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_CHECKER_TYPE,
144472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_WIDTH },
144473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_CHECKER_TYPE,
144474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_WIDTH },
144475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_CHECKER_TYPE,
144476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_WIDTH },
144477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_CHECKER_TYPE,
144478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_WIDTH },
144479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_CHECKER_TYPE,
144480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_WIDTH },
144481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_CHECKER_TYPE,
144482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_WIDTH },
144483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_CHECKER_TYPE,
144484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_WIDTH },
144485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_CHECKER_TYPE,
144486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_WIDTH },
144487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_CHECKER_TYPE,
144488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_WIDTH },
144489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_CHECKER_TYPE,
144490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_WIDTH },
144491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_CHECKER_TYPE,
144492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_WIDTH },
144493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_CHECKER_TYPE,
144494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_WIDTH },
144495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_CHECKER_TYPE,
144496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_WIDTH },
144497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_CHECKER_TYPE,
144498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_WIDTH },
144499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_CHECKER_TYPE,
144500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_WIDTH },
144501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_CHECKER_TYPE,
144502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_WIDTH },
144503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_CHECKER_TYPE,
144504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_WIDTH },
144505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_CHECKER_TYPE,
144506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_WIDTH },
144507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_CHECKER_TYPE,
144508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_WIDTH },
144509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_CHECKER_TYPE,
144510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_WIDTH },
144511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_CHECKER_TYPE,
144512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_WIDTH },
144513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_CHECKER_TYPE,
144514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_WIDTH },
144515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_CHECKER_TYPE,
144516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_WIDTH },
144517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_CHECKER_TYPE,
144518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_WIDTH },
144519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_CHECKER_TYPE,
144520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_WIDTH },
144521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_CHECKER_TYPE,
144522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_WIDTH },
144523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_CHECKER_TYPE,
144524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_WIDTH },
144525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_CHECKER_TYPE,
144526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_WIDTH },
144527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_CHECKER_TYPE,
144528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_WIDTH },
144529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_CHECKER_TYPE,
144530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_WIDTH },
144531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_CHECKER_TYPE,
144532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_WIDTH },
144533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_CHECKER_TYPE,
144534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_WIDTH },
144535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_CHECKER_TYPE,
144536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_WIDTH },
144537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_CHECKER_TYPE,
144538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_WIDTH },
144539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_CHECKER_TYPE,
144540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_WIDTH },
144541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_CHECKER_TYPE,
144542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_WIDTH },
144543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_CHECKER_TYPE,
144544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_WIDTH },
144545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_CHECKER_TYPE,
144546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_WIDTH },
144547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_CHECKER_TYPE,
144548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_WIDTH },
144549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_CHECKER_TYPE,
144550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_WIDTH },
144551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_CHECKER_TYPE,
144552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_WIDTH },
144553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_CHECKER_TYPE,
144554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_WIDTH },
144555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_CHECKER_TYPE,
144556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_WIDTH },
144557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_CHECKER_TYPE,
144558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_WIDTH },
144559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_CHECKER_TYPE,
144560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_WIDTH },
144561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_CHECKER_TYPE,
144562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_WIDTH },
144563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_CHECKER_TYPE,
144564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_WIDTH },
144565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_CHECKER_TYPE,
144566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_WIDTH },
144567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_CHECKER_TYPE,
144568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_WIDTH },
144569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_CHECKER_TYPE,
144570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_WIDTH },
144571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_CHECKER_TYPE,
144572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_WIDTH },
144573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_CHECKER_TYPE,
144574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_WIDTH },
144575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_CHECKER_TYPE,
144576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_WIDTH },
144577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_CHECKER_TYPE,
144578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_WIDTH },
144579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_CHECKER_TYPE,
144580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_WIDTH },
144581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_CHECKER_TYPE,
144582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_WIDTH },
144583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_CHECKER_TYPE,
144584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_WIDTH },
144585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_CHECKER_TYPE,
144586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_WIDTH },
144587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_CHECKER_TYPE,
144588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_WIDTH },
144589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_CHECKER_TYPE,
144590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_WIDTH },
144591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_CHECKER_TYPE,
144592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_WIDTH },
144593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_CHECKER_TYPE,
144594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_WIDTH },
144595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_CHECKER_TYPE,
144596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_WIDTH },
144597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_CHECKER_TYPE,
144598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_WIDTH },
144599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_CHECKER_TYPE,
144600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_WIDTH },
144601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_CHECKER_TYPE,
144602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_WIDTH },
144603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_CHECKER_TYPE,
144604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_WIDTH },
144605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_CHECKER_TYPE,
144606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_WIDTH },
144607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_CHECKER_TYPE,
144608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_WIDTH },
144609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_CHECKER_TYPE,
144610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_WIDTH },
144611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_CHECKER_TYPE,
144612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_WIDTH },
144613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_CHECKER_TYPE,
144614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_WIDTH },
144615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_CHECKER_TYPE,
144616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_WIDTH },
144617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_CHECKER_TYPE,
144618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_WIDTH },
144619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_CHECKER_TYPE,
144620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_WIDTH },
144621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_CHECKER_TYPE,
144622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_WIDTH },
144623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_CHECKER_TYPE,
144624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_WIDTH },
144625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_CHECKER_TYPE,
144626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_WIDTH },
144627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_CHECKER_TYPE,
144628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_WIDTH },
144629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_CHECKER_TYPE,
144630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_WIDTH },
144631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_CHECKER_TYPE,
144632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_WIDTH },
144633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_CHECKER_TYPE,
144634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_WIDTH },
144635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_CHECKER_TYPE,
144636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_WIDTH },
144637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_CHECKER_TYPE,
144638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_WIDTH },
144639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_CHECKER_TYPE,
144640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_WIDTH },
144641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_CHECKER_TYPE,
144642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_WIDTH },
144643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_CHECKER_TYPE,
144644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_WIDTH },
144645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_CHECKER_TYPE,
144646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_WIDTH },
144647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_CHECKER_TYPE,
144648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_WIDTH },
144649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_CHECKER_TYPE,
144650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_WIDTH },
144651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_CHECKER_TYPE,
144652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_WIDTH },
144653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_CHECKER_TYPE,
144654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_WIDTH },
144655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_CHECKER_TYPE,
144656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_WIDTH },
144657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_CHECKER_TYPE,
144658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_WIDTH },
144659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_102_CHECKER_TYPE,
144660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_102_WIDTH },
144661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_103_CHECKER_TYPE,
144662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_103_WIDTH },
144663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_104_CHECKER_TYPE,
144664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_104_WIDTH },
144665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_105_CHECKER_TYPE,
144666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_105_WIDTH },
144667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_106_CHECKER_TYPE,
144668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_106_WIDTH },
144669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_107_CHECKER_TYPE,
144670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_107_WIDTH },
144671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_108_CHECKER_TYPE,
144672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_108_WIDTH },
144673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_109_CHECKER_TYPE,
144674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_109_WIDTH },
144675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_110_CHECKER_TYPE,
144676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_110_WIDTH },
144677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_111_CHECKER_TYPE,
144678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_111_WIDTH },
144679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_112_CHECKER_TYPE,
144680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_112_WIDTH },
144681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_113_CHECKER_TYPE,
144682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_113_WIDTH },
144683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_114_CHECKER_TYPE,
144684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_114_WIDTH },
144685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_115_CHECKER_TYPE,
144686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_115_WIDTH },
144687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_116_CHECKER_TYPE,
144688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_116_WIDTH },
144689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_117_CHECKER_TYPE,
144690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_117_WIDTH },
144691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_118_CHECKER_TYPE,
144692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_118_WIDTH },
144693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_119_CHECKER_TYPE,
144694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_119_WIDTH },
144695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_120_CHECKER_TYPE,
144696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_120_WIDTH },
144697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_121_CHECKER_TYPE,
144698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_121_WIDTH },
144699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_122_CHECKER_TYPE,
144700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_122_WIDTH },
144701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_123_CHECKER_TYPE,
144702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_123_WIDTH },
144703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_124_CHECKER_TYPE,
144704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_124_WIDTH },
144705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_125_CHECKER_TYPE,
144706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_125_WIDTH },
144707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_126_CHECKER_TYPE,
144708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_126_WIDTH },
144709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_127_CHECKER_TYPE,
144710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_127_WIDTH },
144711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_128_CHECKER_TYPE,
144712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_128_WIDTH },
144713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_129_CHECKER_TYPE,
144714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_129_WIDTH },
144715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_130_CHECKER_TYPE,
144716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_130_WIDTH },
144717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_131_CHECKER_TYPE,
144718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_131_WIDTH },
144719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_132_CHECKER_TYPE,
144720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_132_WIDTH },
144721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_133_CHECKER_TYPE,
144722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_133_WIDTH },
144723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_134_CHECKER_TYPE,
144724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_134_WIDTH },
144725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_135_CHECKER_TYPE,
144726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_135_WIDTH },
144727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_136_CHECKER_TYPE,
144728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_136_WIDTH },
144729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_137_CHECKER_TYPE,
144730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_137_WIDTH },
144731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_138_CHECKER_TYPE,
144732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_138_WIDTH },
144733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_139_CHECKER_TYPE,
144734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_139_WIDTH },
144735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_140_CHECKER_TYPE,
144736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_140_WIDTH },
144737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_141_CHECKER_TYPE,
144738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_141_WIDTH },
144739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_142_CHECKER_TYPE,
144740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_142_WIDTH },
144741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_143_CHECKER_TYPE,
144742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_143_WIDTH },
144743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_144_CHECKER_TYPE,
144744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_144_WIDTH },
144745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_145_CHECKER_TYPE,
144746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_145_WIDTH },
144747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_146_CHECKER_TYPE,
144748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_146_WIDTH },
144749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_147_CHECKER_TYPE,
144750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_147_WIDTH },
144751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_148_CHECKER_TYPE,
144752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_148_WIDTH },
144753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_149_CHECKER_TYPE,
144754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_149_WIDTH },
144755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_150_CHECKER_TYPE,
144756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_150_WIDTH },
144757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_151_CHECKER_TYPE,
144758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_151_WIDTH },
144759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_152_CHECKER_TYPE,
144760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_152_WIDTH },
144761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_153_CHECKER_TYPE,
144762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_153_WIDTH },
144763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_154_CHECKER_TYPE,
144764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_154_WIDTH },
144765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_155_CHECKER_TYPE,
144766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_155_WIDTH },
144767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_156_CHECKER_TYPE,
144768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_156_WIDTH },
144769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_157_CHECKER_TYPE,
144770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_157_WIDTH },
144771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_158_CHECKER_TYPE,
144772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_158_WIDTH },
144773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_159_CHECKER_TYPE,
144774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_159_WIDTH },
144775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_160_CHECKER_TYPE,
144776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_160_WIDTH },
144777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_161_CHECKER_TYPE,
144778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_161_WIDTH },
144779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_162_CHECKER_TYPE,
144780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_162_WIDTH },
144781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_163_CHECKER_TYPE,
144782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_163_WIDTH },
144783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_164_CHECKER_TYPE,
144784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_164_WIDTH },
144785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_165_CHECKER_TYPE,
144786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_165_WIDTH },
144787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_166_CHECKER_TYPE,
144788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_166_WIDTH },
144789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_167_CHECKER_TYPE,
144790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_167_WIDTH },
144791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_168_CHECKER_TYPE,
144792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_168_WIDTH },
144793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_169_CHECKER_TYPE,
144794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_169_WIDTH },
144795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_170_CHECKER_TYPE,
144796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_170_WIDTH },
144797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_171_CHECKER_TYPE,
144798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_171_WIDTH },
144799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_172_CHECKER_TYPE,
144800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_172_WIDTH },
144801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_173_CHECKER_TYPE,
144802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_173_WIDTH },
144803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_174_CHECKER_TYPE,
144804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_174_WIDTH },
144805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_175_CHECKER_TYPE,
144806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_175_WIDTH },
144807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_176_CHECKER_TYPE,
144808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_176_WIDTH },
144809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_177_CHECKER_TYPE,
144810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_177_WIDTH },
144811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_178_CHECKER_TYPE,
144812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_178_WIDTH },
144813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_179_CHECKER_TYPE,
144814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_179_WIDTH },
144815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_180_CHECKER_TYPE,
144816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_180_WIDTH },
144817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_181_CHECKER_TYPE,
144818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_181_WIDTH },
144819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_182_CHECKER_TYPE,
144820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_182_WIDTH },
144821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_183_CHECKER_TYPE,
144822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_183_WIDTH },
144823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_184_CHECKER_TYPE,
144824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_184_WIDTH },
144825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_185_CHECKER_TYPE,
144826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_185_WIDTH },
144827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_186_CHECKER_TYPE,
144828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_186_WIDTH },
144829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_187_CHECKER_TYPE,
144830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_187_WIDTH },
144831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_188_CHECKER_TYPE,
144832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_188_WIDTH },
144833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_189_CHECKER_TYPE,
144834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_189_WIDTH },
144835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_190_CHECKER_TYPE,
144836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_190_WIDTH },
144837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_191_CHECKER_TYPE,
144838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_191_WIDTH },
144839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_192_CHECKER_TYPE,
144840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_192_WIDTH },
144841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_193_CHECKER_TYPE,
144842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_193_WIDTH },
144843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_194_CHECKER_TYPE,
144844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_194_WIDTH },
144845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_195_CHECKER_TYPE,
144846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_195_WIDTH },
144847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_196_CHECKER_TYPE,
144848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_196_WIDTH },
144849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_197_CHECKER_TYPE,
144850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_197_WIDTH },
144851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_198_CHECKER_TYPE,
144852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_198_WIDTH },
144853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_199_CHECKER_TYPE,
144854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_199_WIDTH },
144855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_200_CHECKER_TYPE,
144856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_200_WIDTH },
144857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_201_CHECKER_TYPE,
144858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_201_WIDTH },
144859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_202_CHECKER_TYPE,
144860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_202_WIDTH },
144861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_203_CHECKER_TYPE,
144862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_203_WIDTH },
144863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_204_CHECKER_TYPE,
144864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_204_WIDTH },
144865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_205_CHECKER_TYPE,
144866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_205_WIDTH },
144867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_206_CHECKER_TYPE,
144868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_206_WIDTH },
144869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_207_CHECKER_TYPE,
144870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_207_WIDTH },
144871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_208_CHECKER_TYPE,
144872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_208_WIDTH },
144873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_209_CHECKER_TYPE,
144874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_209_WIDTH },
144875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_210_CHECKER_TYPE,
144876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_210_WIDTH },
144877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_211_CHECKER_TYPE,
144878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_211_WIDTH },
144879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_212_CHECKER_TYPE,
144880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_212_WIDTH },
144881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_213_CHECKER_TYPE,
144882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_213_WIDTH },
144883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_214_CHECKER_TYPE,
144884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_214_WIDTH },
144885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_215_CHECKER_TYPE,
144886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_215_WIDTH },
144887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_216_CHECKER_TYPE,
144888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_216_WIDTH },
144889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_217_CHECKER_TYPE,
144890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_217_WIDTH },
144891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_218_CHECKER_TYPE,
144892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_218_WIDTH },
144893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_219_CHECKER_TYPE,
144894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_219_WIDTH },
144895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_220_CHECKER_TYPE,
144896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_220_WIDTH },
144897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_221_CHECKER_TYPE,
144898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_221_WIDTH },
144899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_222_CHECKER_TYPE,
144900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_222_WIDTH },
144901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_223_CHECKER_TYPE,
144902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_223_WIDTH },
144903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_224_CHECKER_TYPE,
144904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_224_WIDTH },
144905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_225_CHECKER_TYPE,
144906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_225_WIDTH },
144907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_226_CHECKER_TYPE,
144908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_226_WIDTH },
144909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_227_CHECKER_TYPE,
144910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_227_WIDTH },
144911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_228_CHECKER_TYPE,
144912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_228_WIDTH },
144913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_229_CHECKER_TYPE,
144914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_229_WIDTH },
144915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_230_CHECKER_TYPE,
144916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_230_WIDTH },
144917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_231_CHECKER_TYPE,
144918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_231_WIDTH },
144919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_232_CHECKER_TYPE,
144920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_232_WIDTH },
144921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_233_CHECKER_TYPE,
144922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_233_WIDTH },
144923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_234_CHECKER_TYPE,
144924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_234_WIDTH },
144925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_235_CHECKER_TYPE,
144926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_235_WIDTH },
144927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_236_CHECKER_TYPE,
144928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_236_WIDTH },
144929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_237_CHECKER_TYPE,
144930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_237_WIDTH },
144931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_238_CHECKER_TYPE,
144932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_238_WIDTH },
144933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_239_CHECKER_TYPE,
144934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_239_WIDTH },
144935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_240_CHECKER_TYPE,
144936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_240_WIDTH },
144937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_241_CHECKER_TYPE,
144938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_241_WIDTH },
144939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_242_CHECKER_TYPE,
144940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_242_WIDTH },
144941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_243_CHECKER_TYPE,
144942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_243_WIDTH },
144943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_244_CHECKER_TYPE,
144944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_244_WIDTH },
144945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_245_CHECKER_TYPE,
144946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_245_WIDTH },
144947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_246_CHECKER_TYPE,
144948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_246_WIDTH },
144949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_247_CHECKER_TYPE,
144950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_247_WIDTH },
144951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_248_CHECKER_TYPE,
144952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_248_WIDTH },
144953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_249_CHECKER_TYPE,
144954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_249_WIDTH },
144955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_250_CHECKER_TYPE,
144956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_250_WIDTH },
144957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_251_CHECKER_TYPE,
144958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_251_WIDTH },
144959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_252_CHECKER_TYPE,
144960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_252_WIDTH },
144961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_253_CHECKER_TYPE,
144962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_253_WIDTH },
144963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_254_CHECKER_TYPE,
144964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_254_WIDTH },
144965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_255_CHECKER_TYPE,
144966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_GROUP_255_WIDTH },
144967 };
144968 
144974 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS] =
144975 {
144976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_0_CHECKER_TYPE,
144977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_0_WIDTH },
144978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_1_CHECKER_TYPE,
144979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_1_WIDTH },
144980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_2_CHECKER_TYPE,
144981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_2_WIDTH },
144982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_3_CHECKER_TYPE,
144983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_3_WIDTH },
144984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_4_CHECKER_TYPE,
144985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_4_WIDTH },
144986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_5_CHECKER_TYPE,
144987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_5_WIDTH },
144988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_6_CHECKER_TYPE,
144989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_6_WIDTH },
144990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_7_CHECKER_TYPE,
144991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_7_WIDTH },
144992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_8_CHECKER_TYPE,
144993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_8_WIDTH },
144994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_9_CHECKER_TYPE,
144995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_9_WIDTH },
144996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_10_CHECKER_TYPE,
144997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_10_WIDTH },
144998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_11_CHECKER_TYPE,
144999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_11_WIDTH },
145000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_12_CHECKER_TYPE,
145001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_12_WIDTH },
145002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_13_CHECKER_TYPE,
145003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_13_WIDTH },
145004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_14_CHECKER_TYPE,
145005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_14_WIDTH },
145006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_15_CHECKER_TYPE,
145007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_15_WIDTH },
145008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_16_CHECKER_TYPE,
145009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_16_WIDTH },
145010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_17_CHECKER_TYPE,
145011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_17_WIDTH },
145012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_18_CHECKER_TYPE,
145013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_18_WIDTH },
145014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_19_CHECKER_TYPE,
145015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_19_WIDTH },
145016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_20_CHECKER_TYPE,
145017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_20_WIDTH },
145018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_21_CHECKER_TYPE,
145019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_21_WIDTH },
145020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_22_CHECKER_TYPE,
145021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_22_WIDTH },
145022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_23_CHECKER_TYPE,
145023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_23_WIDTH },
145024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_24_CHECKER_TYPE,
145025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_24_WIDTH },
145026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_25_CHECKER_TYPE,
145027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_25_WIDTH },
145028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_26_CHECKER_TYPE,
145029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_26_WIDTH },
145030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_27_CHECKER_TYPE,
145031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_27_WIDTH },
145032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_28_CHECKER_TYPE,
145033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_28_WIDTH },
145034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_29_CHECKER_TYPE,
145035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_29_WIDTH },
145036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_30_CHECKER_TYPE,
145037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_30_WIDTH },
145038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_31_CHECKER_TYPE,
145039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_31_WIDTH },
145040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_32_CHECKER_TYPE,
145041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_32_WIDTH },
145042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_33_CHECKER_TYPE,
145043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_33_WIDTH },
145044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_34_CHECKER_TYPE,
145045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_34_WIDTH },
145046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_35_CHECKER_TYPE,
145047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_35_WIDTH },
145048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_36_CHECKER_TYPE,
145049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_36_WIDTH },
145050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_37_CHECKER_TYPE,
145051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_37_WIDTH },
145052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_38_CHECKER_TYPE,
145053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_38_WIDTH },
145054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_39_CHECKER_TYPE,
145055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_39_WIDTH },
145056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_40_CHECKER_TYPE,
145057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_40_WIDTH },
145058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_41_CHECKER_TYPE,
145059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_41_WIDTH },
145060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_42_CHECKER_TYPE,
145061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_42_WIDTH },
145062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_43_CHECKER_TYPE,
145063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_43_WIDTH },
145064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_44_CHECKER_TYPE,
145065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_44_WIDTH },
145066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_45_CHECKER_TYPE,
145067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_45_WIDTH },
145068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_46_CHECKER_TYPE,
145069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_46_WIDTH },
145070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_47_CHECKER_TYPE,
145071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_47_WIDTH },
145072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_48_CHECKER_TYPE,
145073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_48_WIDTH },
145074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_49_CHECKER_TYPE,
145075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_49_WIDTH },
145076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_50_CHECKER_TYPE,
145077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_50_WIDTH },
145078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_51_CHECKER_TYPE,
145079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_51_WIDTH },
145080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_52_CHECKER_TYPE,
145081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_52_WIDTH },
145082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_53_CHECKER_TYPE,
145083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_53_WIDTH },
145084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_54_CHECKER_TYPE,
145085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_54_WIDTH },
145086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_55_CHECKER_TYPE,
145087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_55_WIDTH },
145088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_56_CHECKER_TYPE,
145089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_56_WIDTH },
145090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_57_CHECKER_TYPE,
145091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_57_WIDTH },
145092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_58_CHECKER_TYPE,
145093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_58_WIDTH },
145094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_59_CHECKER_TYPE,
145095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_59_WIDTH },
145096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_60_CHECKER_TYPE,
145097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_60_WIDTH },
145098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_61_CHECKER_TYPE,
145099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_61_WIDTH },
145100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_62_CHECKER_TYPE,
145101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_62_WIDTH },
145102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_63_CHECKER_TYPE,
145103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_63_WIDTH },
145104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_64_CHECKER_TYPE,
145105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_64_WIDTH },
145106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_65_CHECKER_TYPE,
145107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_65_WIDTH },
145108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_66_CHECKER_TYPE,
145109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_66_WIDTH },
145110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_67_CHECKER_TYPE,
145111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_67_WIDTH },
145112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_68_CHECKER_TYPE,
145113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_68_WIDTH },
145114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_69_CHECKER_TYPE,
145115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_69_WIDTH },
145116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_70_CHECKER_TYPE,
145117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_70_WIDTH },
145118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_71_CHECKER_TYPE,
145119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_71_WIDTH },
145120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_72_CHECKER_TYPE,
145121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_72_WIDTH },
145122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_73_CHECKER_TYPE,
145123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_73_WIDTH },
145124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_74_CHECKER_TYPE,
145125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_74_WIDTH },
145126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_75_CHECKER_TYPE,
145127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_75_WIDTH },
145128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_76_CHECKER_TYPE,
145129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_76_WIDTH },
145130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_77_CHECKER_TYPE,
145131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_77_WIDTH },
145132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_78_CHECKER_TYPE,
145133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_78_WIDTH },
145134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_79_CHECKER_TYPE,
145135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_79_WIDTH },
145136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_80_CHECKER_TYPE,
145137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_80_WIDTH },
145138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_81_CHECKER_TYPE,
145139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_81_WIDTH },
145140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_82_CHECKER_TYPE,
145141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_82_WIDTH },
145142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_83_CHECKER_TYPE,
145143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_83_WIDTH },
145144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_84_CHECKER_TYPE,
145145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_84_WIDTH },
145146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_85_CHECKER_TYPE,
145147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_85_WIDTH },
145148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_86_CHECKER_TYPE,
145149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_86_WIDTH },
145150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_87_CHECKER_TYPE,
145151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_87_WIDTH },
145152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_88_CHECKER_TYPE,
145153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_88_WIDTH },
145154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_89_CHECKER_TYPE,
145155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_89_WIDTH },
145156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_90_CHECKER_TYPE,
145157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_90_WIDTH },
145158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_91_CHECKER_TYPE,
145159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_91_WIDTH },
145160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_92_CHECKER_TYPE,
145161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_92_WIDTH },
145162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_93_CHECKER_TYPE,
145163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_93_WIDTH },
145164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_94_CHECKER_TYPE,
145165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_94_WIDTH },
145166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_95_CHECKER_TYPE,
145167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_95_WIDTH },
145168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_96_CHECKER_TYPE,
145169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_96_WIDTH },
145170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_97_CHECKER_TYPE,
145171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_97_WIDTH },
145172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_98_CHECKER_TYPE,
145173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_98_WIDTH },
145174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_99_CHECKER_TYPE,
145175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_99_WIDTH },
145176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_100_CHECKER_TYPE,
145177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_100_WIDTH },
145178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_101_CHECKER_TYPE,
145179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_101_WIDTH },
145180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_102_CHECKER_TYPE,
145181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_102_WIDTH },
145182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_103_CHECKER_TYPE,
145183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_103_WIDTH },
145184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_104_CHECKER_TYPE,
145185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_104_WIDTH },
145186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_105_CHECKER_TYPE,
145187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_105_WIDTH },
145188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_106_CHECKER_TYPE,
145189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_106_WIDTH },
145190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_107_CHECKER_TYPE,
145191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_107_WIDTH },
145192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_108_CHECKER_TYPE,
145193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_108_WIDTH },
145194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_109_CHECKER_TYPE,
145195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_109_WIDTH },
145196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_110_CHECKER_TYPE,
145197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_110_WIDTH },
145198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_111_CHECKER_TYPE,
145199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_111_WIDTH },
145200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_112_CHECKER_TYPE,
145201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_112_WIDTH },
145202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_113_CHECKER_TYPE,
145203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_113_WIDTH },
145204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_114_CHECKER_TYPE,
145205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_114_WIDTH },
145206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_115_CHECKER_TYPE,
145207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_115_WIDTH },
145208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_116_CHECKER_TYPE,
145209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_116_WIDTH },
145210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_117_CHECKER_TYPE,
145211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_117_WIDTH },
145212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_118_CHECKER_TYPE,
145213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_118_WIDTH },
145214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_119_CHECKER_TYPE,
145215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_119_WIDTH },
145216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_120_CHECKER_TYPE,
145217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_120_WIDTH },
145218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_121_CHECKER_TYPE,
145219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_121_WIDTH },
145220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_122_CHECKER_TYPE,
145221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_122_WIDTH },
145222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_123_CHECKER_TYPE,
145223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_123_WIDTH },
145224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_124_CHECKER_TYPE,
145225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_124_WIDTH },
145226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_125_CHECKER_TYPE,
145227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_125_WIDTH },
145228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_126_CHECKER_TYPE,
145229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_126_WIDTH },
145230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_127_CHECKER_TYPE,
145231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_127_WIDTH },
145232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_128_CHECKER_TYPE,
145233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_128_WIDTH },
145234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_129_CHECKER_TYPE,
145235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_129_WIDTH },
145236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_130_CHECKER_TYPE,
145237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_130_WIDTH },
145238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_131_CHECKER_TYPE,
145239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_131_WIDTH },
145240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_132_CHECKER_TYPE,
145241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_132_WIDTH },
145242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_133_CHECKER_TYPE,
145243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_133_WIDTH },
145244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_134_CHECKER_TYPE,
145245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_134_WIDTH },
145246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_135_CHECKER_TYPE,
145247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_135_WIDTH },
145248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_136_CHECKER_TYPE,
145249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_136_WIDTH },
145250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_137_CHECKER_TYPE,
145251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_137_WIDTH },
145252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_138_CHECKER_TYPE,
145253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_138_WIDTH },
145254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_139_CHECKER_TYPE,
145255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_139_WIDTH },
145256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_140_CHECKER_TYPE,
145257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_140_WIDTH },
145258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_141_CHECKER_TYPE,
145259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_141_WIDTH },
145260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_142_CHECKER_TYPE,
145261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_142_WIDTH },
145262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_143_CHECKER_TYPE,
145263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_143_WIDTH },
145264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_144_CHECKER_TYPE,
145265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_144_WIDTH },
145266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_145_CHECKER_TYPE,
145267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_145_WIDTH },
145268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_146_CHECKER_TYPE,
145269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_146_WIDTH },
145270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_147_CHECKER_TYPE,
145271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_147_WIDTH },
145272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_148_CHECKER_TYPE,
145273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_148_WIDTH },
145274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_149_CHECKER_TYPE,
145275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_149_WIDTH },
145276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_150_CHECKER_TYPE,
145277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_150_WIDTH },
145278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_151_CHECKER_TYPE,
145279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_151_WIDTH },
145280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_152_CHECKER_TYPE,
145281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_152_WIDTH },
145282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_153_CHECKER_TYPE,
145283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_153_WIDTH },
145284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_154_CHECKER_TYPE,
145285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_154_WIDTH },
145286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_155_CHECKER_TYPE,
145287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_155_WIDTH },
145288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_156_CHECKER_TYPE,
145289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_156_WIDTH },
145290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_157_CHECKER_TYPE,
145291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_157_WIDTH },
145292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_158_CHECKER_TYPE,
145293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_158_WIDTH },
145294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_159_CHECKER_TYPE,
145295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_159_WIDTH },
145296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_160_CHECKER_TYPE,
145297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_160_WIDTH },
145298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_161_CHECKER_TYPE,
145299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_161_WIDTH },
145300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_162_CHECKER_TYPE,
145301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_162_WIDTH },
145302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_163_CHECKER_TYPE,
145303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_163_WIDTH },
145304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_164_CHECKER_TYPE,
145305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_164_WIDTH },
145306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_165_CHECKER_TYPE,
145307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_165_WIDTH },
145308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_166_CHECKER_TYPE,
145309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_166_WIDTH },
145310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_167_CHECKER_TYPE,
145311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_167_WIDTH },
145312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_168_CHECKER_TYPE,
145313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_168_WIDTH },
145314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_169_CHECKER_TYPE,
145315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_169_WIDTH },
145316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_170_CHECKER_TYPE,
145317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_170_WIDTH },
145318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_171_CHECKER_TYPE,
145319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_171_WIDTH },
145320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_172_CHECKER_TYPE,
145321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_172_WIDTH },
145322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_173_CHECKER_TYPE,
145323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_173_WIDTH },
145324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_174_CHECKER_TYPE,
145325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_174_WIDTH },
145326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_175_CHECKER_TYPE,
145327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_175_WIDTH },
145328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_176_CHECKER_TYPE,
145329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_176_WIDTH },
145330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_177_CHECKER_TYPE,
145331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_177_WIDTH },
145332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_178_CHECKER_TYPE,
145333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_178_WIDTH },
145334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_179_CHECKER_TYPE,
145335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_179_WIDTH },
145336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_180_CHECKER_TYPE,
145337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_180_WIDTH },
145338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_181_CHECKER_TYPE,
145339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_181_WIDTH },
145340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_182_CHECKER_TYPE,
145341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_182_WIDTH },
145342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_183_CHECKER_TYPE,
145343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_183_WIDTH },
145344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_184_CHECKER_TYPE,
145345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_184_WIDTH },
145346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_185_CHECKER_TYPE,
145347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_185_WIDTH },
145348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_186_CHECKER_TYPE,
145349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_186_WIDTH },
145350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_187_CHECKER_TYPE,
145351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_187_WIDTH },
145352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_188_CHECKER_TYPE,
145353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_188_WIDTH },
145354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_189_CHECKER_TYPE,
145355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_189_WIDTH },
145356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_190_CHECKER_TYPE,
145357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_190_WIDTH },
145358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_191_CHECKER_TYPE,
145359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_191_WIDTH },
145360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_192_CHECKER_TYPE,
145361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_192_WIDTH },
145362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_193_CHECKER_TYPE,
145363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_193_WIDTH },
145364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_194_CHECKER_TYPE,
145365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_194_WIDTH },
145366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_195_CHECKER_TYPE,
145367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_195_WIDTH },
145368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_196_CHECKER_TYPE,
145369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_196_WIDTH },
145370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_197_CHECKER_TYPE,
145371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_197_WIDTH },
145372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_198_CHECKER_TYPE,
145373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_198_WIDTH },
145374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_199_CHECKER_TYPE,
145375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_199_WIDTH },
145376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_200_CHECKER_TYPE,
145377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_200_WIDTH },
145378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_201_CHECKER_TYPE,
145379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_201_WIDTH },
145380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_202_CHECKER_TYPE,
145381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_202_WIDTH },
145382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_203_CHECKER_TYPE,
145383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_203_WIDTH },
145384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_204_CHECKER_TYPE,
145385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_204_WIDTH },
145386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_205_CHECKER_TYPE,
145387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_205_WIDTH },
145388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_206_CHECKER_TYPE,
145389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_206_WIDTH },
145390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_207_CHECKER_TYPE,
145391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_207_WIDTH },
145392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_208_CHECKER_TYPE,
145393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_208_WIDTH },
145394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_209_CHECKER_TYPE,
145395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_209_WIDTH },
145396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_210_CHECKER_TYPE,
145397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_210_WIDTH },
145398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_211_CHECKER_TYPE,
145399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_211_WIDTH },
145400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_212_CHECKER_TYPE,
145401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_212_WIDTH },
145402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_213_CHECKER_TYPE,
145403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_213_WIDTH },
145404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_214_CHECKER_TYPE,
145405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_214_WIDTH },
145406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_215_CHECKER_TYPE,
145407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_215_WIDTH },
145408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_216_CHECKER_TYPE,
145409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_216_WIDTH },
145410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_217_CHECKER_TYPE,
145411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_217_WIDTH },
145412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_218_CHECKER_TYPE,
145413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_218_WIDTH },
145414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_219_CHECKER_TYPE,
145415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_219_WIDTH },
145416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_220_CHECKER_TYPE,
145417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_220_WIDTH },
145418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_221_CHECKER_TYPE,
145419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_221_WIDTH },
145420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_222_CHECKER_TYPE,
145421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_222_WIDTH },
145422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_223_CHECKER_TYPE,
145423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_223_WIDTH },
145424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_224_CHECKER_TYPE,
145425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_224_WIDTH },
145426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_225_CHECKER_TYPE,
145427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_225_WIDTH },
145428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_226_CHECKER_TYPE,
145429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_226_WIDTH },
145430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_227_CHECKER_TYPE,
145431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_227_WIDTH },
145432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_228_CHECKER_TYPE,
145433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_228_WIDTH },
145434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_229_CHECKER_TYPE,
145435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_229_WIDTH },
145436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_230_CHECKER_TYPE,
145437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_230_WIDTH },
145438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_231_CHECKER_TYPE,
145439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_231_WIDTH },
145440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_232_CHECKER_TYPE,
145441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_232_WIDTH },
145442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_233_CHECKER_TYPE,
145443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_233_WIDTH },
145444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_234_CHECKER_TYPE,
145445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_234_WIDTH },
145446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_235_CHECKER_TYPE,
145447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_235_WIDTH },
145448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_236_CHECKER_TYPE,
145449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_236_WIDTH },
145450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_237_CHECKER_TYPE,
145451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_237_WIDTH },
145452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_238_CHECKER_TYPE,
145453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_238_WIDTH },
145454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_239_CHECKER_TYPE,
145455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_239_WIDTH },
145456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_240_CHECKER_TYPE,
145457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_240_WIDTH },
145458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_241_CHECKER_TYPE,
145459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_241_WIDTH },
145460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_242_CHECKER_TYPE,
145461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_242_WIDTH },
145462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_243_CHECKER_TYPE,
145463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_243_WIDTH },
145464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_244_CHECKER_TYPE,
145465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_244_WIDTH },
145466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_245_CHECKER_TYPE,
145467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_245_WIDTH },
145468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_246_CHECKER_TYPE,
145469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_246_WIDTH },
145470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_247_CHECKER_TYPE,
145471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_247_WIDTH },
145472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_248_CHECKER_TYPE,
145473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_248_WIDTH },
145474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_249_CHECKER_TYPE,
145475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_249_WIDTH },
145476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_250_CHECKER_TYPE,
145477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_250_WIDTH },
145478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_251_CHECKER_TYPE,
145479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_251_WIDTH },
145480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_252_CHECKER_TYPE,
145481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_252_WIDTH },
145482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_253_CHECKER_TYPE,
145483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_253_WIDTH },
145484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_254_CHECKER_TYPE,
145485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_254_WIDTH },
145486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_255_CHECKER_TYPE,
145487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_GROUP_255_WIDTH },
145488 };
145489 
145495 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS] =
145496 {
145497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_0_CHECKER_TYPE,
145498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_0_WIDTH },
145499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_1_CHECKER_TYPE,
145500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_1_WIDTH },
145501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_2_CHECKER_TYPE,
145502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_2_WIDTH },
145503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_3_CHECKER_TYPE,
145504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_3_WIDTH },
145505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_4_CHECKER_TYPE,
145506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_4_WIDTH },
145507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_5_CHECKER_TYPE,
145508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_5_WIDTH },
145509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_6_CHECKER_TYPE,
145510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_6_WIDTH },
145511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_7_CHECKER_TYPE,
145512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_7_WIDTH },
145513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_8_CHECKER_TYPE,
145514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_8_WIDTH },
145515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_9_CHECKER_TYPE,
145516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_9_WIDTH },
145517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_10_CHECKER_TYPE,
145518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_10_WIDTH },
145519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_11_CHECKER_TYPE,
145520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_11_WIDTH },
145521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_12_CHECKER_TYPE,
145522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_12_WIDTH },
145523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_13_CHECKER_TYPE,
145524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_13_WIDTH },
145525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_14_CHECKER_TYPE,
145526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_14_WIDTH },
145527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_15_CHECKER_TYPE,
145528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_15_WIDTH },
145529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_16_CHECKER_TYPE,
145530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_16_WIDTH },
145531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_17_CHECKER_TYPE,
145532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_17_WIDTH },
145533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_18_CHECKER_TYPE,
145534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_18_WIDTH },
145535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_19_CHECKER_TYPE,
145536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_19_WIDTH },
145537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_20_CHECKER_TYPE,
145538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_20_WIDTH },
145539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_21_CHECKER_TYPE,
145540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_21_WIDTH },
145541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_22_CHECKER_TYPE,
145542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_22_WIDTH },
145543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_23_CHECKER_TYPE,
145544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_23_WIDTH },
145545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_24_CHECKER_TYPE,
145546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_24_WIDTH },
145547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_25_CHECKER_TYPE,
145548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_25_WIDTH },
145549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_26_CHECKER_TYPE,
145550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_26_WIDTH },
145551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_27_CHECKER_TYPE,
145552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_27_WIDTH },
145553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_28_CHECKER_TYPE,
145554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_28_WIDTH },
145555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_29_CHECKER_TYPE,
145556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_29_WIDTH },
145557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_30_CHECKER_TYPE,
145558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_30_WIDTH },
145559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_31_CHECKER_TYPE,
145560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_31_WIDTH },
145561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_32_CHECKER_TYPE,
145562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_32_WIDTH },
145563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_33_CHECKER_TYPE,
145564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_33_WIDTH },
145565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_34_CHECKER_TYPE,
145566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_34_WIDTH },
145567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_35_CHECKER_TYPE,
145568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_35_WIDTH },
145569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_36_CHECKER_TYPE,
145570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_36_WIDTH },
145571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_37_CHECKER_TYPE,
145572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_37_WIDTH },
145573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_38_CHECKER_TYPE,
145574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_38_WIDTH },
145575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_39_CHECKER_TYPE,
145576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_39_WIDTH },
145577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_40_CHECKER_TYPE,
145578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_40_WIDTH },
145579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_41_CHECKER_TYPE,
145580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_41_WIDTH },
145581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_42_CHECKER_TYPE,
145582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_42_WIDTH },
145583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_43_CHECKER_TYPE,
145584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_43_WIDTH },
145585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_44_CHECKER_TYPE,
145586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_44_WIDTH },
145587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_45_CHECKER_TYPE,
145588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_45_WIDTH },
145589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_46_CHECKER_TYPE,
145590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_46_WIDTH },
145591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_47_CHECKER_TYPE,
145592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_47_WIDTH },
145593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_48_CHECKER_TYPE,
145594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_48_WIDTH },
145595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_49_CHECKER_TYPE,
145596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_49_WIDTH },
145597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_50_CHECKER_TYPE,
145598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_50_WIDTH },
145599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_51_CHECKER_TYPE,
145600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_51_WIDTH },
145601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_52_CHECKER_TYPE,
145602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_52_WIDTH },
145603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_53_CHECKER_TYPE,
145604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_53_WIDTH },
145605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_54_CHECKER_TYPE,
145606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_54_WIDTH },
145607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_55_CHECKER_TYPE,
145608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_55_WIDTH },
145609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_56_CHECKER_TYPE,
145610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_56_WIDTH },
145611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_57_CHECKER_TYPE,
145612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_57_WIDTH },
145613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_58_CHECKER_TYPE,
145614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_58_WIDTH },
145615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_59_CHECKER_TYPE,
145616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_59_WIDTH },
145617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_60_CHECKER_TYPE,
145618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_60_WIDTH },
145619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_61_CHECKER_TYPE,
145620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_61_WIDTH },
145621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_62_CHECKER_TYPE,
145622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_62_WIDTH },
145623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_63_CHECKER_TYPE,
145624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_63_WIDTH },
145625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_64_CHECKER_TYPE,
145626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_64_WIDTH },
145627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_65_CHECKER_TYPE,
145628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_65_WIDTH },
145629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_66_CHECKER_TYPE,
145630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_66_WIDTH },
145631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_67_CHECKER_TYPE,
145632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_67_WIDTH },
145633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_68_CHECKER_TYPE,
145634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_68_WIDTH },
145635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_69_CHECKER_TYPE,
145636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_69_WIDTH },
145637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_70_CHECKER_TYPE,
145638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_70_WIDTH },
145639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_71_CHECKER_TYPE,
145640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_71_WIDTH },
145641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_72_CHECKER_TYPE,
145642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_72_WIDTH },
145643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_73_CHECKER_TYPE,
145644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_73_WIDTH },
145645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_74_CHECKER_TYPE,
145646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_74_WIDTH },
145647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_75_CHECKER_TYPE,
145648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_75_WIDTH },
145649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_76_CHECKER_TYPE,
145650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_76_WIDTH },
145651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_77_CHECKER_TYPE,
145652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_77_WIDTH },
145653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_78_CHECKER_TYPE,
145654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_78_WIDTH },
145655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_79_CHECKER_TYPE,
145656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_79_WIDTH },
145657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_80_CHECKER_TYPE,
145658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_80_WIDTH },
145659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_81_CHECKER_TYPE,
145660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_81_WIDTH },
145661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_82_CHECKER_TYPE,
145662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_82_WIDTH },
145663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_83_CHECKER_TYPE,
145664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_83_WIDTH },
145665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_84_CHECKER_TYPE,
145666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_84_WIDTH },
145667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_85_CHECKER_TYPE,
145668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_85_WIDTH },
145669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_86_CHECKER_TYPE,
145670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_86_WIDTH },
145671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_87_CHECKER_TYPE,
145672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_87_WIDTH },
145673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_88_CHECKER_TYPE,
145674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_88_WIDTH },
145675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_89_CHECKER_TYPE,
145676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_89_WIDTH },
145677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_90_CHECKER_TYPE,
145678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_90_WIDTH },
145679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_91_CHECKER_TYPE,
145680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_91_WIDTH },
145681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_92_CHECKER_TYPE,
145682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_92_WIDTH },
145683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_93_CHECKER_TYPE,
145684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_93_WIDTH },
145685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_94_CHECKER_TYPE,
145686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_94_WIDTH },
145687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_95_CHECKER_TYPE,
145688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_95_WIDTH },
145689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_96_CHECKER_TYPE,
145690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_96_WIDTH },
145691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_97_CHECKER_TYPE,
145692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_97_WIDTH },
145693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_98_CHECKER_TYPE,
145694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_98_WIDTH },
145695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_99_CHECKER_TYPE,
145696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_99_WIDTH },
145697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_100_CHECKER_TYPE,
145698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_100_WIDTH },
145699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_101_CHECKER_TYPE,
145700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_101_WIDTH },
145701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_102_CHECKER_TYPE,
145702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_102_WIDTH },
145703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_103_CHECKER_TYPE,
145704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_103_WIDTH },
145705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_104_CHECKER_TYPE,
145706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_104_WIDTH },
145707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_105_CHECKER_TYPE,
145708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_105_WIDTH },
145709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_106_CHECKER_TYPE,
145710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_106_WIDTH },
145711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_107_CHECKER_TYPE,
145712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_107_WIDTH },
145713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_108_CHECKER_TYPE,
145714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_108_WIDTH },
145715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_109_CHECKER_TYPE,
145716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_109_WIDTH },
145717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_110_CHECKER_TYPE,
145718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_110_WIDTH },
145719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_111_CHECKER_TYPE,
145720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_111_WIDTH },
145721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_112_CHECKER_TYPE,
145722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_112_WIDTH },
145723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_113_CHECKER_TYPE,
145724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_113_WIDTH },
145725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_114_CHECKER_TYPE,
145726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_114_WIDTH },
145727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_115_CHECKER_TYPE,
145728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_115_WIDTH },
145729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_116_CHECKER_TYPE,
145730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_116_WIDTH },
145731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_117_CHECKER_TYPE,
145732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_117_WIDTH },
145733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_118_CHECKER_TYPE,
145734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_118_WIDTH },
145735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_119_CHECKER_TYPE,
145736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_119_WIDTH },
145737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_120_CHECKER_TYPE,
145738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_120_WIDTH },
145739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_121_CHECKER_TYPE,
145740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_121_WIDTH },
145741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_122_CHECKER_TYPE,
145742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_122_WIDTH },
145743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_123_CHECKER_TYPE,
145744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_123_WIDTH },
145745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_124_CHECKER_TYPE,
145746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_124_WIDTH },
145747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_125_CHECKER_TYPE,
145748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_125_WIDTH },
145749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_126_CHECKER_TYPE,
145750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_126_WIDTH },
145751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_127_CHECKER_TYPE,
145752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_127_WIDTH },
145753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_128_CHECKER_TYPE,
145754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_128_WIDTH },
145755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_129_CHECKER_TYPE,
145756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_129_WIDTH },
145757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_130_CHECKER_TYPE,
145758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_130_WIDTH },
145759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_131_CHECKER_TYPE,
145760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_131_WIDTH },
145761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_132_CHECKER_TYPE,
145762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_132_WIDTH },
145763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_133_CHECKER_TYPE,
145764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_133_WIDTH },
145765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_134_CHECKER_TYPE,
145766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_134_WIDTH },
145767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_135_CHECKER_TYPE,
145768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_135_WIDTH },
145769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_136_CHECKER_TYPE,
145770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_136_WIDTH },
145771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_137_CHECKER_TYPE,
145772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_137_WIDTH },
145773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_138_CHECKER_TYPE,
145774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_138_WIDTH },
145775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_139_CHECKER_TYPE,
145776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_139_WIDTH },
145777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_140_CHECKER_TYPE,
145778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_140_WIDTH },
145779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_141_CHECKER_TYPE,
145780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_141_WIDTH },
145781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_142_CHECKER_TYPE,
145782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_142_WIDTH },
145783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_143_CHECKER_TYPE,
145784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_143_WIDTH },
145785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_144_CHECKER_TYPE,
145786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_144_WIDTH },
145787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_145_CHECKER_TYPE,
145788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_145_WIDTH },
145789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_146_CHECKER_TYPE,
145790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_146_WIDTH },
145791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_147_CHECKER_TYPE,
145792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_147_WIDTH },
145793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_148_CHECKER_TYPE,
145794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_148_WIDTH },
145795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_149_CHECKER_TYPE,
145796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_149_WIDTH },
145797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_150_CHECKER_TYPE,
145798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_150_WIDTH },
145799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_151_CHECKER_TYPE,
145800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_151_WIDTH },
145801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_152_CHECKER_TYPE,
145802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_152_WIDTH },
145803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_153_CHECKER_TYPE,
145804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_153_WIDTH },
145805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_154_CHECKER_TYPE,
145806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_154_WIDTH },
145807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_155_CHECKER_TYPE,
145808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_155_WIDTH },
145809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_156_CHECKER_TYPE,
145810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_156_WIDTH },
145811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_157_CHECKER_TYPE,
145812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_157_WIDTH },
145813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_158_CHECKER_TYPE,
145814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_158_WIDTH },
145815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_159_CHECKER_TYPE,
145816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_159_WIDTH },
145817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_160_CHECKER_TYPE,
145818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_160_WIDTH },
145819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_161_CHECKER_TYPE,
145820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_161_WIDTH },
145821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_162_CHECKER_TYPE,
145822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_162_WIDTH },
145823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_163_CHECKER_TYPE,
145824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_163_WIDTH },
145825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_164_CHECKER_TYPE,
145826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_164_WIDTH },
145827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_165_CHECKER_TYPE,
145828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_165_WIDTH },
145829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_166_CHECKER_TYPE,
145830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_166_WIDTH },
145831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_167_CHECKER_TYPE,
145832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_167_WIDTH },
145833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_168_CHECKER_TYPE,
145834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_168_WIDTH },
145835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_169_CHECKER_TYPE,
145836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_169_WIDTH },
145837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_170_CHECKER_TYPE,
145838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_170_WIDTH },
145839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_171_CHECKER_TYPE,
145840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_171_WIDTH },
145841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_172_CHECKER_TYPE,
145842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_172_WIDTH },
145843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_173_CHECKER_TYPE,
145844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_173_WIDTH },
145845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_174_CHECKER_TYPE,
145846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_174_WIDTH },
145847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_175_CHECKER_TYPE,
145848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_175_WIDTH },
145849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_176_CHECKER_TYPE,
145850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_176_WIDTH },
145851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_177_CHECKER_TYPE,
145852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_177_WIDTH },
145853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_178_CHECKER_TYPE,
145854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_178_WIDTH },
145855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_179_CHECKER_TYPE,
145856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_179_WIDTH },
145857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_180_CHECKER_TYPE,
145858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_180_WIDTH },
145859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_181_CHECKER_TYPE,
145860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_181_WIDTH },
145861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_182_CHECKER_TYPE,
145862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_182_WIDTH },
145863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_183_CHECKER_TYPE,
145864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_183_WIDTH },
145865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_184_CHECKER_TYPE,
145866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_184_WIDTH },
145867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_185_CHECKER_TYPE,
145868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_185_WIDTH },
145869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_186_CHECKER_TYPE,
145870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_186_WIDTH },
145871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_187_CHECKER_TYPE,
145872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_187_WIDTH },
145873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_188_CHECKER_TYPE,
145874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_188_WIDTH },
145875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_189_CHECKER_TYPE,
145876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_189_WIDTH },
145877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_190_CHECKER_TYPE,
145878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_190_WIDTH },
145879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_191_CHECKER_TYPE,
145880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_191_WIDTH },
145881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_192_CHECKER_TYPE,
145882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_192_WIDTH },
145883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_193_CHECKER_TYPE,
145884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_193_WIDTH },
145885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_194_CHECKER_TYPE,
145886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_194_WIDTH },
145887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_195_CHECKER_TYPE,
145888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_195_WIDTH },
145889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_196_CHECKER_TYPE,
145890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_196_WIDTH },
145891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_197_CHECKER_TYPE,
145892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_197_WIDTH },
145893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_198_CHECKER_TYPE,
145894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_198_WIDTH },
145895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_199_CHECKER_TYPE,
145896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_199_WIDTH },
145897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_200_CHECKER_TYPE,
145898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_200_WIDTH },
145899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_201_CHECKER_TYPE,
145900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_201_WIDTH },
145901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_202_CHECKER_TYPE,
145902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_202_WIDTH },
145903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_203_CHECKER_TYPE,
145904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_203_WIDTH },
145905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_204_CHECKER_TYPE,
145906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_204_WIDTH },
145907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_205_CHECKER_TYPE,
145908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_205_WIDTH },
145909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_206_CHECKER_TYPE,
145910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_206_WIDTH },
145911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_207_CHECKER_TYPE,
145912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_207_WIDTH },
145913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_208_CHECKER_TYPE,
145914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_208_WIDTH },
145915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_209_CHECKER_TYPE,
145916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_209_WIDTH },
145917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_210_CHECKER_TYPE,
145918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_210_WIDTH },
145919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_211_CHECKER_TYPE,
145920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_211_WIDTH },
145921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_212_CHECKER_TYPE,
145922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_212_WIDTH },
145923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_213_CHECKER_TYPE,
145924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_213_WIDTH },
145925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_214_CHECKER_TYPE,
145926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_214_WIDTH },
145927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_215_CHECKER_TYPE,
145928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_215_WIDTH },
145929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_216_CHECKER_TYPE,
145930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_216_WIDTH },
145931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_217_CHECKER_TYPE,
145932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_217_WIDTH },
145933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_218_CHECKER_TYPE,
145934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_218_WIDTH },
145935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_219_CHECKER_TYPE,
145936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_219_WIDTH },
145937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_220_CHECKER_TYPE,
145938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_220_WIDTH },
145939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_221_CHECKER_TYPE,
145940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_221_WIDTH },
145941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_222_CHECKER_TYPE,
145942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_222_WIDTH },
145943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_223_CHECKER_TYPE,
145944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_223_WIDTH },
145945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_224_CHECKER_TYPE,
145946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_224_WIDTH },
145947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_225_CHECKER_TYPE,
145948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_225_WIDTH },
145949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_226_CHECKER_TYPE,
145950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_226_WIDTH },
145951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_227_CHECKER_TYPE,
145952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_227_WIDTH },
145953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_228_CHECKER_TYPE,
145954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_228_WIDTH },
145955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_229_CHECKER_TYPE,
145956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_229_WIDTH },
145957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_230_CHECKER_TYPE,
145958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_230_WIDTH },
145959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_231_CHECKER_TYPE,
145960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_231_WIDTH },
145961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_232_CHECKER_TYPE,
145962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_232_WIDTH },
145963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_233_CHECKER_TYPE,
145964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_233_WIDTH },
145965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_234_CHECKER_TYPE,
145966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_234_WIDTH },
145967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_235_CHECKER_TYPE,
145968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_235_WIDTH },
145969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_236_CHECKER_TYPE,
145970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_236_WIDTH },
145971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_237_CHECKER_TYPE,
145972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_237_WIDTH },
145973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_238_CHECKER_TYPE,
145974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_238_WIDTH },
145975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_239_CHECKER_TYPE,
145976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_239_WIDTH },
145977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_240_CHECKER_TYPE,
145978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_240_WIDTH },
145979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_241_CHECKER_TYPE,
145980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_241_WIDTH },
145981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_242_CHECKER_TYPE,
145982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_242_WIDTH },
145983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_243_CHECKER_TYPE,
145984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_243_WIDTH },
145985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_244_CHECKER_TYPE,
145986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_244_WIDTH },
145987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_245_CHECKER_TYPE,
145988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_245_WIDTH },
145989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_246_CHECKER_TYPE,
145990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_246_WIDTH },
145991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_247_CHECKER_TYPE,
145992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_247_WIDTH },
145993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_248_CHECKER_TYPE,
145994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_248_WIDTH },
145995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_249_CHECKER_TYPE,
145996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_249_WIDTH },
145997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_250_CHECKER_TYPE,
145998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_250_WIDTH },
145999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_251_CHECKER_TYPE,
146000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_251_WIDTH },
146001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_252_CHECKER_TYPE,
146002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_252_WIDTH },
146003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_253_CHECKER_TYPE,
146004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_253_WIDTH },
146005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_254_CHECKER_TYPE,
146006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_254_WIDTH },
146007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_255_CHECKER_TYPE,
146008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_GROUP_255_WIDTH },
146009 };
146010 
146016 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS] =
146017 {
146018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_0_CHECKER_TYPE,
146019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_0_WIDTH },
146020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_1_CHECKER_TYPE,
146021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_1_WIDTH },
146022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_2_CHECKER_TYPE,
146023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_2_WIDTH },
146024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_3_CHECKER_TYPE,
146025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_3_WIDTH },
146026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_4_CHECKER_TYPE,
146027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_4_WIDTH },
146028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_5_CHECKER_TYPE,
146029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_5_WIDTH },
146030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_6_CHECKER_TYPE,
146031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_6_WIDTH },
146032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_7_CHECKER_TYPE,
146033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_7_WIDTH },
146034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_8_CHECKER_TYPE,
146035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_8_WIDTH },
146036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_9_CHECKER_TYPE,
146037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_9_WIDTH },
146038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_10_CHECKER_TYPE,
146039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_10_WIDTH },
146040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_11_CHECKER_TYPE,
146041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_11_WIDTH },
146042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_12_CHECKER_TYPE,
146043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_12_WIDTH },
146044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_13_CHECKER_TYPE,
146045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_13_WIDTH },
146046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_14_CHECKER_TYPE,
146047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_14_WIDTH },
146048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_15_CHECKER_TYPE,
146049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_15_WIDTH },
146050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_16_CHECKER_TYPE,
146051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_16_WIDTH },
146052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_17_CHECKER_TYPE,
146053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_17_WIDTH },
146054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_18_CHECKER_TYPE,
146055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_18_WIDTH },
146056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_19_CHECKER_TYPE,
146057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_19_WIDTH },
146058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_20_CHECKER_TYPE,
146059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_20_WIDTH },
146060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_21_CHECKER_TYPE,
146061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_21_WIDTH },
146062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_22_CHECKER_TYPE,
146063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_22_WIDTH },
146064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_23_CHECKER_TYPE,
146065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_23_WIDTH },
146066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_24_CHECKER_TYPE,
146067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_24_WIDTH },
146068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_25_CHECKER_TYPE,
146069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_25_WIDTH },
146070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_26_CHECKER_TYPE,
146071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_26_WIDTH },
146072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_27_CHECKER_TYPE,
146073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_27_WIDTH },
146074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_28_CHECKER_TYPE,
146075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_28_WIDTH },
146076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_29_CHECKER_TYPE,
146077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_29_WIDTH },
146078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_30_CHECKER_TYPE,
146079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_30_WIDTH },
146080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_31_CHECKER_TYPE,
146081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_31_WIDTH },
146082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_32_CHECKER_TYPE,
146083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_32_WIDTH },
146084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_33_CHECKER_TYPE,
146085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_33_WIDTH },
146086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_34_CHECKER_TYPE,
146087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_34_WIDTH },
146088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_35_CHECKER_TYPE,
146089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_35_WIDTH },
146090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_36_CHECKER_TYPE,
146091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_36_WIDTH },
146092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_37_CHECKER_TYPE,
146093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_37_WIDTH },
146094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_38_CHECKER_TYPE,
146095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_38_WIDTH },
146096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_39_CHECKER_TYPE,
146097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_39_WIDTH },
146098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_40_CHECKER_TYPE,
146099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_40_WIDTH },
146100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_41_CHECKER_TYPE,
146101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_41_WIDTH },
146102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_42_CHECKER_TYPE,
146103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_42_WIDTH },
146104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_43_CHECKER_TYPE,
146105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_43_WIDTH },
146106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_44_CHECKER_TYPE,
146107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_44_WIDTH },
146108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_45_CHECKER_TYPE,
146109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_45_WIDTH },
146110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_46_CHECKER_TYPE,
146111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_46_WIDTH },
146112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_47_CHECKER_TYPE,
146113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_47_WIDTH },
146114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_48_CHECKER_TYPE,
146115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_48_WIDTH },
146116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_49_CHECKER_TYPE,
146117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_49_WIDTH },
146118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_50_CHECKER_TYPE,
146119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_50_WIDTH },
146120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_51_CHECKER_TYPE,
146121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_51_WIDTH },
146122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_52_CHECKER_TYPE,
146123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_52_WIDTH },
146124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_53_CHECKER_TYPE,
146125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_53_WIDTH },
146126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_54_CHECKER_TYPE,
146127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_54_WIDTH },
146128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_55_CHECKER_TYPE,
146129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_55_WIDTH },
146130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_56_CHECKER_TYPE,
146131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_56_WIDTH },
146132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_57_CHECKER_TYPE,
146133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_57_WIDTH },
146134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_58_CHECKER_TYPE,
146135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_58_WIDTH },
146136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_59_CHECKER_TYPE,
146137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_59_WIDTH },
146138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_60_CHECKER_TYPE,
146139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_60_WIDTH },
146140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_61_CHECKER_TYPE,
146141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_61_WIDTH },
146142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_62_CHECKER_TYPE,
146143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_62_WIDTH },
146144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_63_CHECKER_TYPE,
146145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_63_WIDTH },
146146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_64_CHECKER_TYPE,
146147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_64_WIDTH },
146148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_65_CHECKER_TYPE,
146149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_65_WIDTH },
146150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_66_CHECKER_TYPE,
146151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_66_WIDTH },
146152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_67_CHECKER_TYPE,
146153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_67_WIDTH },
146154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_68_CHECKER_TYPE,
146155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_68_WIDTH },
146156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_69_CHECKER_TYPE,
146157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_69_WIDTH },
146158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_70_CHECKER_TYPE,
146159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_70_WIDTH },
146160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_71_CHECKER_TYPE,
146161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_71_WIDTH },
146162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_72_CHECKER_TYPE,
146163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_72_WIDTH },
146164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_73_CHECKER_TYPE,
146165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_73_WIDTH },
146166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_74_CHECKER_TYPE,
146167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_74_WIDTH },
146168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_75_CHECKER_TYPE,
146169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_75_WIDTH },
146170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_76_CHECKER_TYPE,
146171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_76_WIDTH },
146172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_77_CHECKER_TYPE,
146173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_77_WIDTH },
146174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_78_CHECKER_TYPE,
146175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_78_WIDTH },
146176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_79_CHECKER_TYPE,
146177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_79_WIDTH },
146178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_80_CHECKER_TYPE,
146179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_80_WIDTH },
146180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_81_CHECKER_TYPE,
146181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_81_WIDTH },
146182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_82_CHECKER_TYPE,
146183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_82_WIDTH },
146184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_83_CHECKER_TYPE,
146185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_83_WIDTH },
146186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_84_CHECKER_TYPE,
146187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_84_WIDTH },
146188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_85_CHECKER_TYPE,
146189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_85_WIDTH },
146190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_86_CHECKER_TYPE,
146191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_86_WIDTH },
146192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_87_CHECKER_TYPE,
146193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_87_WIDTH },
146194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_88_CHECKER_TYPE,
146195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_88_WIDTH },
146196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_89_CHECKER_TYPE,
146197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_89_WIDTH },
146198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_90_CHECKER_TYPE,
146199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_90_WIDTH },
146200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_91_CHECKER_TYPE,
146201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_91_WIDTH },
146202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_92_CHECKER_TYPE,
146203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_92_WIDTH },
146204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_93_CHECKER_TYPE,
146205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_93_WIDTH },
146206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_94_CHECKER_TYPE,
146207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_94_WIDTH },
146208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_95_CHECKER_TYPE,
146209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_95_WIDTH },
146210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_96_CHECKER_TYPE,
146211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_96_WIDTH },
146212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_97_CHECKER_TYPE,
146213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_97_WIDTH },
146214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_98_CHECKER_TYPE,
146215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_98_WIDTH },
146216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_99_CHECKER_TYPE,
146217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_99_WIDTH },
146218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_100_CHECKER_TYPE,
146219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_100_WIDTH },
146220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_101_CHECKER_TYPE,
146221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_101_WIDTH },
146222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_102_CHECKER_TYPE,
146223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_102_WIDTH },
146224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_103_CHECKER_TYPE,
146225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_103_WIDTH },
146226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_104_CHECKER_TYPE,
146227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_104_WIDTH },
146228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_105_CHECKER_TYPE,
146229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_105_WIDTH },
146230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_106_CHECKER_TYPE,
146231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_106_WIDTH },
146232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_107_CHECKER_TYPE,
146233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_107_WIDTH },
146234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_108_CHECKER_TYPE,
146235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_108_WIDTH },
146236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_109_CHECKER_TYPE,
146237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_109_WIDTH },
146238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_110_CHECKER_TYPE,
146239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_110_WIDTH },
146240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_111_CHECKER_TYPE,
146241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_111_WIDTH },
146242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_112_CHECKER_TYPE,
146243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_112_WIDTH },
146244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_113_CHECKER_TYPE,
146245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_113_WIDTH },
146246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_114_CHECKER_TYPE,
146247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_114_WIDTH },
146248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_115_CHECKER_TYPE,
146249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_115_WIDTH },
146250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_116_CHECKER_TYPE,
146251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_116_WIDTH },
146252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_117_CHECKER_TYPE,
146253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_117_WIDTH },
146254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_118_CHECKER_TYPE,
146255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_118_WIDTH },
146256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_119_CHECKER_TYPE,
146257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_119_WIDTH },
146258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_120_CHECKER_TYPE,
146259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_120_WIDTH },
146260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_121_CHECKER_TYPE,
146261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_121_WIDTH },
146262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_122_CHECKER_TYPE,
146263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_122_WIDTH },
146264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_123_CHECKER_TYPE,
146265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_123_WIDTH },
146266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_124_CHECKER_TYPE,
146267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_124_WIDTH },
146268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_125_CHECKER_TYPE,
146269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_125_WIDTH },
146270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_126_CHECKER_TYPE,
146271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_126_WIDTH },
146272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_127_CHECKER_TYPE,
146273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_127_WIDTH },
146274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_128_CHECKER_TYPE,
146275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_128_WIDTH },
146276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_129_CHECKER_TYPE,
146277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_129_WIDTH },
146278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_130_CHECKER_TYPE,
146279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_130_WIDTH },
146280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_131_CHECKER_TYPE,
146281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_131_WIDTH },
146282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_132_CHECKER_TYPE,
146283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_132_WIDTH },
146284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_133_CHECKER_TYPE,
146285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_133_WIDTH },
146286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_134_CHECKER_TYPE,
146287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_134_WIDTH },
146288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_135_CHECKER_TYPE,
146289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_135_WIDTH },
146290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_136_CHECKER_TYPE,
146291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_136_WIDTH },
146292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_137_CHECKER_TYPE,
146293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_137_WIDTH },
146294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_138_CHECKER_TYPE,
146295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_138_WIDTH },
146296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_139_CHECKER_TYPE,
146297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_139_WIDTH },
146298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_140_CHECKER_TYPE,
146299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_140_WIDTH },
146300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_141_CHECKER_TYPE,
146301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_141_WIDTH },
146302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_142_CHECKER_TYPE,
146303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_142_WIDTH },
146304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_143_CHECKER_TYPE,
146305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_143_WIDTH },
146306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_144_CHECKER_TYPE,
146307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_144_WIDTH },
146308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_145_CHECKER_TYPE,
146309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_145_WIDTH },
146310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_146_CHECKER_TYPE,
146311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_146_WIDTH },
146312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_147_CHECKER_TYPE,
146313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_147_WIDTH },
146314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_148_CHECKER_TYPE,
146315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_148_WIDTH },
146316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_149_CHECKER_TYPE,
146317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_149_WIDTH },
146318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_150_CHECKER_TYPE,
146319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_150_WIDTH },
146320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_151_CHECKER_TYPE,
146321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_151_WIDTH },
146322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_152_CHECKER_TYPE,
146323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_152_WIDTH },
146324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_153_CHECKER_TYPE,
146325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_153_WIDTH },
146326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_154_CHECKER_TYPE,
146327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_154_WIDTH },
146328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_155_CHECKER_TYPE,
146329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_155_WIDTH },
146330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_156_CHECKER_TYPE,
146331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_156_WIDTH },
146332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_157_CHECKER_TYPE,
146333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_157_WIDTH },
146334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_158_CHECKER_TYPE,
146335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_158_WIDTH },
146336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_159_CHECKER_TYPE,
146337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_159_WIDTH },
146338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_160_CHECKER_TYPE,
146339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_160_WIDTH },
146340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_161_CHECKER_TYPE,
146341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_161_WIDTH },
146342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_162_CHECKER_TYPE,
146343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_162_WIDTH },
146344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_163_CHECKER_TYPE,
146345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_163_WIDTH },
146346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_164_CHECKER_TYPE,
146347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_164_WIDTH },
146348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_165_CHECKER_TYPE,
146349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_165_WIDTH },
146350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_166_CHECKER_TYPE,
146351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_166_WIDTH },
146352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_167_CHECKER_TYPE,
146353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_167_WIDTH },
146354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_168_CHECKER_TYPE,
146355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_168_WIDTH },
146356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_169_CHECKER_TYPE,
146357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_169_WIDTH },
146358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_170_CHECKER_TYPE,
146359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_170_WIDTH },
146360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_171_CHECKER_TYPE,
146361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_171_WIDTH },
146362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_172_CHECKER_TYPE,
146363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_172_WIDTH },
146364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_173_CHECKER_TYPE,
146365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_173_WIDTH },
146366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_174_CHECKER_TYPE,
146367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_174_WIDTH },
146368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_175_CHECKER_TYPE,
146369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_175_WIDTH },
146370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_176_CHECKER_TYPE,
146371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_176_WIDTH },
146372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_177_CHECKER_TYPE,
146373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_177_WIDTH },
146374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_178_CHECKER_TYPE,
146375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_178_WIDTH },
146376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_179_CHECKER_TYPE,
146377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_179_WIDTH },
146378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_180_CHECKER_TYPE,
146379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_180_WIDTH },
146380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_181_CHECKER_TYPE,
146381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_181_WIDTH },
146382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_182_CHECKER_TYPE,
146383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_182_WIDTH },
146384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_183_CHECKER_TYPE,
146385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_183_WIDTH },
146386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_184_CHECKER_TYPE,
146387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_184_WIDTH },
146388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_185_CHECKER_TYPE,
146389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_185_WIDTH },
146390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_186_CHECKER_TYPE,
146391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_186_WIDTH },
146392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_187_CHECKER_TYPE,
146393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_187_WIDTH },
146394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_188_CHECKER_TYPE,
146395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_188_WIDTH },
146396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_189_CHECKER_TYPE,
146397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_189_WIDTH },
146398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_190_CHECKER_TYPE,
146399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_190_WIDTH },
146400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_191_CHECKER_TYPE,
146401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_191_WIDTH },
146402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_192_CHECKER_TYPE,
146403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_192_WIDTH },
146404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_193_CHECKER_TYPE,
146405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_193_WIDTH },
146406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_194_CHECKER_TYPE,
146407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_194_WIDTH },
146408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_195_CHECKER_TYPE,
146409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_195_WIDTH },
146410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_196_CHECKER_TYPE,
146411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_196_WIDTH },
146412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_197_CHECKER_TYPE,
146413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_197_WIDTH },
146414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_198_CHECKER_TYPE,
146415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_198_WIDTH },
146416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_199_CHECKER_TYPE,
146417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_199_WIDTH },
146418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_200_CHECKER_TYPE,
146419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_200_WIDTH },
146420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_201_CHECKER_TYPE,
146421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_201_WIDTH },
146422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_202_CHECKER_TYPE,
146423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_202_WIDTH },
146424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_203_CHECKER_TYPE,
146425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_203_WIDTH },
146426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_204_CHECKER_TYPE,
146427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_204_WIDTH },
146428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_205_CHECKER_TYPE,
146429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_205_WIDTH },
146430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_206_CHECKER_TYPE,
146431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_206_WIDTH },
146432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_207_CHECKER_TYPE,
146433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_207_WIDTH },
146434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_208_CHECKER_TYPE,
146435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_208_WIDTH },
146436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_209_CHECKER_TYPE,
146437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_209_WIDTH },
146438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_210_CHECKER_TYPE,
146439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_210_WIDTH },
146440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_211_CHECKER_TYPE,
146441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_211_WIDTH },
146442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_212_CHECKER_TYPE,
146443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_212_WIDTH },
146444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_213_CHECKER_TYPE,
146445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_213_WIDTH },
146446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_214_CHECKER_TYPE,
146447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_214_WIDTH },
146448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_215_CHECKER_TYPE,
146449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_215_WIDTH },
146450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_216_CHECKER_TYPE,
146451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_216_WIDTH },
146452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_217_CHECKER_TYPE,
146453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_217_WIDTH },
146454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_218_CHECKER_TYPE,
146455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_218_WIDTH },
146456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_219_CHECKER_TYPE,
146457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_219_WIDTH },
146458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_220_CHECKER_TYPE,
146459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_220_WIDTH },
146460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_221_CHECKER_TYPE,
146461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_221_WIDTH },
146462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_222_CHECKER_TYPE,
146463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_222_WIDTH },
146464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_223_CHECKER_TYPE,
146465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_223_WIDTH },
146466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_224_CHECKER_TYPE,
146467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_224_WIDTH },
146468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_225_CHECKER_TYPE,
146469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_225_WIDTH },
146470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_226_CHECKER_TYPE,
146471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_226_WIDTH },
146472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_227_CHECKER_TYPE,
146473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_227_WIDTH },
146474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_228_CHECKER_TYPE,
146475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_228_WIDTH },
146476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_229_CHECKER_TYPE,
146477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_229_WIDTH },
146478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_230_CHECKER_TYPE,
146479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_230_WIDTH },
146480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_231_CHECKER_TYPE,
146481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_231_WIDTH },
146482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_232_CHECKER_TYPE,
146483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_232_WIDTH },
146484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_233_CHECKER_TYPE,
146485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_233_WIDTH },
146486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_234_CHECKER_TYPE,
146487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_234_WIDTH },
146488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_235_CHECKER_TYPE,
146489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_235_WIDTH },
146490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_236_CHECKER_TYPE,
146491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_236_WIDTH },
146492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_237_CHECKER_TYPE,
146493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_237_WIDTH },
146494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_238_CHECKER_TYPE,
146495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_238_WIDTH },
146496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_239_CHECKER_TYPE,
146497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_239_WIDTH },
146498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_240_CHECKER_TYPE,
146499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_240_WIDTH },
146500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_241_CHECKER_TYPE,
146501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_241_WIDTH },
146502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_242_CHECKER_TYPE,
146503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_242_WIDTH },
146504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_243_CHECKER_TYPE,
146505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_243_WIDTH },
146506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_244_CHECKER_TYPE,
146507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_244_WIDTH },
146508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_245_CHECKER_TYPE,
146509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_245_WIDTH },
146510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_246_CHECKER_TYPE,
146511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_246_WIDTH },
146512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_247_CHECKER_TYPE,
146513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_247_WIDTH },
146514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_248_CHECKER_TYPE,
146515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_248_WIDTH },
146516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_249_CHECKER_TYPE,
146517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_249_WIDTH },
146518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_250_CHECKER_TYPE,
146519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_250_WIDTH },
146520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_251_CHECKER_TYPE,
146521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_251_WIDTH },
146522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_252_CHECKER_TYPE,
146523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_252_WIDTH },
146524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_253_CHECKER_TYPE,
146525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_253_WIDTH },
146526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_254_CHECKER_TYPE,
146527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_254_WIDTH },
146528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_255_CHECKER_TYPE,
146529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_GROUP_255_WIDTH },
146530 };
146531 
146537 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS] =
146538 {
146539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_0_CHECKER_TYPE,
146540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_0_WIDTH },
146541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_1_CHECKER_TYPE,
146542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_1_WIDTH },
146543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_2_CHECKER_TYPE,
146544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_2_WIDTH },
146545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_3_CHECKER_TYPE,
146546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_3_WIDTH },
146547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_4_CHECKER_TYPE,
146548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_4_WIDTH },
146549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_5_CHECKER_TYPE,
146550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_5_WIDTH },
146551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_6_CHECKER_TYPE,
146552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_6_WIDTH },
146553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_7_CHECKER_TYPE,
146554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_7_WIDTH },
146555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_8_CHECKER_TYPE,
146556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_8_WIDTH },
146557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_9_CHECKER_TYPE,
146558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_9_WIDTH },
146559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_10_CHECKER_TYPE,
146560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_10_WIDTH },
146561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_11_CHECKER_TYPE,
146562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_11_WIDTH },
146563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_12_CHECKER_TYPE,
146564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_12_WIDTH },
146565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_13_CHECKER_TYPE,
146566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_13_WIDTH },
146567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_14_CHECKER_TYPE,
146568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_14_WIDTH },
146569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_15_CHECKER_TYPE,
146570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_15_WIDTH },
146571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_16_CHECKER_TYPE,
146572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_16_WIDTH },
146573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_17_CHECKER_TYPE,
146574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_17_WIDTH },
146575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_18_CHECKER_TYPE,
146576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_18_WIDTH },
146577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_19_CHECKER_TYPE,
146578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_19_WIDTH },
146579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_20_CHECKER_TYPE,
146580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_20_WIDTH },
146581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_21_CHECKER_TYPE,
146582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_21_WIDTH },
146583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_22_CHECKER_TYPE,
146584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_22_WIDTH },
146585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_23_CHECKER_TYPE,
146586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_23_WIDTH },
146587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_24_CHECKER_TYPE,
146588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_24_WIDTH },
146589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_25_CHECKER_TYPE,
146590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_25_WIDTH },
146591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_26_CHECKER_TYPE,
146592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_26_WIDTH },
146593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_27_CHECKER_TYPE,
146594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_27_WIDTH },
146595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_28_CHECKER_TYPE,
146596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_28_WIDTH },
146597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_29_CHECKER_TYPE,
146598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_29_WIDTH },
146599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_30_CHECKER_TYPE,
146600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_30_WIDTH },
146601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_31_CHECKER_TYPE,
146602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_31_WIDTH },
146603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_32_CHECKER_TYPE,
146604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_32_WIDTH },
146605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_33_CHECKER_TYPE,
146606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_33_WIDTH },
146607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_34_CHECKER_TYPE,
146608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_34_WIDTH },
146609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_35_CHECKER_TYPE,
146610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_35_WIDTH },
146611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_36_CHECKER_TYPE,
146612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_36_WIDTH },
146613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_37_CHECKER_TYPE,
146614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_37_WIDTH },
146615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_38_CHECKER_TYPE,
146616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_38_WIDTH },
146617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_39_CHECKER_TYPE,
146618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_39_WIDTH },
146619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_40_CHECKER_TYPE,
146620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_40_WIDTH },
146621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_41_CHECKER_TYPE,
146622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_41_WIDTH },
146623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_42_CHECKER_TYPE,
146624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_42_WIDTH },
146625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_43_CHECKER_TYPE,
146626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_43_WIDTH },
146627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_44_CHECKER_TYPE,
146628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_44_WIDTH },
146629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_45_CHECKER_TYPE,
146630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_45_WIDTH },
146631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_46_CHECKER_TYPE,
146632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_46_WIDTH },
146633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_47_CHECKER_TYPE,
146634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_47_WIDTH },
146635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_48_CHECKER_TYPE,
146636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_48_WIDTH },
146637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_49_CHECKER_TYPE,
146638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_49_WIDTH },
146639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_50_CHECKER_TYPE,
146640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_50_WIDTH },
146641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_51_CHECKER_TYPE,
146642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_51_WIDTH },
146643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_52_CHECKER_TYPE,
146644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_52_WIDTH },
146645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_53_CHECKER_TYPE,
146646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_53_WIDTH },
146647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_54_CHECKER_TYPE,
146648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_54_WIDTH },
146649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_55_CHECKER_TYPE,
146650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_55_WIDTH },
146651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_56_CHECKER_TYPE,
146652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_56_WIDTH },
146653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_57_CHECKER_TYPE,
146654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_57_WIDTH },
146655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_58_CHECKER_TYPE,
146656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_58_WIDTH },
146657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_59_CHECKER_TYPE,
146658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_59_WIDTH },
146659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_60_CHECKER_TYPE,
146660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_60_WIDTH },
146661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_61_CHECKER_TYPE,
146662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_61_WIDTH },
146663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_62_CHECKER_TYPE,
146664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_62_WIDTH },
146665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_63_CHECKER_TYPE,
146666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_63_WIDTH },
146667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_64_CHECKER_TYPE,
146668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_64_WIDTH },
146669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_65_CHECKER_TYPE,
146670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_65_WIDTH },
146671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_66_CHECKER_TYPE,
146672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_66_WIDTH },
146673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_67_CHECKER_TYPE,
146674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_67_WIDTH },
146675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_68_CHECKER_TYPE,
146676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_68_WIDTH },
146677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_69_CHECKER_TYPE,
146678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_69_WIDTH },
146679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_70_CHECKER_TYPE,
146680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_70_WIDTH },
146681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_71_CHECKER_TYPE,
146682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_71_WIDTH },
146683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_72_CHECKER_TYPE,
146684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_72_WIDTH },
146685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_73_CHECKER_TYPE,
146686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_73_WIDTH },
146687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_74_CHECKER_TYPE,
146688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_74_WIDTH },
146689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_75_CHECKER_TYPE,
146690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_75_WIDTH },
146691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_76_CHECKER_TYPE,
146692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_76_WIDTH },
146693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_77_CHECKER_TYPE,
146694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_77_WIDTH },
146695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_78_CHECKER_TYPE,
146696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_78_WIDTH },
146697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_79_CHECKER_TYPE,
146698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_79_WIDTH },
146699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_80_CHECKER_TYPE,
146700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_80_WIDTH },
146701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_81_CHECKER_TYPE,
146702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_81_WIDTH },
146703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_82_CHECKER_TYPE,
146704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_82_WIDTH },
146705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_83_CHECKER_TYPE,
146706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_83_WIDTH },
146707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_84_CHECKER_TYPE,
146708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_84_WIDTH },
146709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_85_CHECKER_TYPE,
146710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_85_WIDTH },
146711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_86_CHECKER_TYPE,
146712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_86_WIDTH },
146713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_87_CHECKER_TYPE,
146714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_87_WIDTH },
146715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_88_CHECKER_TYPE,
146716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_88_WIDTH },
146717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_89_CHECKER_TYPE,
146718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_89_WIDTH },
146719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_90_CHECKER_TYPE,
146720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_90_WIDTH },
146721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_91_CHECKER_TYPE,
146722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_91_WIDTH },
146723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_92_CHECKER_TYPE,
146724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_92_WIDTH },
146725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_93_CHECKER_TYPE,
146726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_93_WIDTH },
146727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_94_CHECKER_TYPE,
146728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_94_WIDTH },
146729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_95_CHECKER_TYPE,
146730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_95_WIDTH },
146731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_96_CHECKER_TYPE,
146732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_96_WIDTH },
146733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_97_CHECKER_TYPE,
146734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_97_WIDTH },
146735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_98_CHECKER_TYPE,
146736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_98_WIDTH },
146737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_99_CHECKER_TYPE,
146738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_99_WIDTH },
146739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_100_CHECKER_TYPE,
146740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_100_WIDTH },
146741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_101_CHECKER_TYPE,
146742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_101_WIDTH },
146743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_102_CHECKER_TYPE,
146744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_102_WIDTH },
146745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_103_CHECKER_TYPE,
146746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_103_WIDTH },
146747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_104_CHECKER_TYPE,
146748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_104_WIDTH },
146749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_105_CHECKER_TYPE,
146750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_105_WIDTH },
146751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_106_CHECKER_TYPE,
146752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_106_WIDTH },
146753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_107_CHECKER_TYPE,
146754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_107_WIDTH },
146755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_108_CHECKER_TYPE,
146756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_108_WIDTH },
146757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_109_CHECKER_TYPE,
146758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_109_WIDTH },
146759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_110_CHECKER_TYPE,
146760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_110_WIDTH },
146761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_111_CHECKER_TYPE,
146762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_111_WIDTH },
146763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_112_CHECKER_TYPE,
146764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_112_WIDTH },
146765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_113_CHECKER_TYPE,
146766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_113_WIDTH },
146767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_114_CHECKER_TYPE,
146768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_114_WIDTH },
146769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_115_CHECKER_TYPE,
146770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_115_WIDTH },
146771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_116_CHECKER_TYPE,
146772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_116_WIDTH },
146773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_117_CHECKER_TYPE,
146774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_117_WIDTH },
146775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_118_CHECKER_TYPE,
146776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_118_WIDTH },
146777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_119_CHECKER_TYPE,
146778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_119_WIDTH },
146779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_120_CHECKER_TYPE,
146780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_120_WIDTH },
146781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_121_CHECKER_TYPE,
146782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_121_WIDTH },
146783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_122_CHECKER_TYPE,
146784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_122_WIDTH },
146785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_123_CHECKER_TYPE,
146786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_123_WIDTH },
146787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_124_CHECKER_TYPE,
146788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_124_WIDTH },
146789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_125_CHECKER_TYPE,
146790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_125_WIDTH },
146791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_126_CHECKER_TYPE,
146792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_126_WIDTH },
146793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_127_CHECKER_TYPE,
146794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_127_WIDTH },
146795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_128_CHECKER_TYPE,
146796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_128_WIDTH },
146797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_129_CHECKER_TYPE,
146798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_129_WIDTH },
146799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_130_CHECKER_TYPE,
146800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_130_WIDTH },
146801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_131_CHECKER_TYPE,
146802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_131_WIDTH },
146803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_132_CHECKER_TYPE,
146804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_132_WIDTH },
146805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_133_CHECKER_TYPE,
146806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_133_WIDTH },
146807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_134_CHECKER_TYPE,
146808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_134_WIDTH },
146809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_135_CHECKER_TYPE,
146810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_135_WIDTH },
146811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_136_CHECKER_TYPE,
146812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_136_WIDTH },
146813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_137_CHECKER_TYPE,
146814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_137_WIDTH },
146815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_138_CHECKER_TYPE,
146816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_138_WIDTH },
146817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_139_CHECKER_TYPE,
146818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_139_WIDTH },
146819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_140_CHECKER_TYPE,
146820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_140_WIDTH },
146821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_141_CHECKER_TYPE,
146822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_141_WIDTH },
146823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_142_CHECKER_TYPE,
146824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_142_WIDTH },
146825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_143_CHECKER_TYPE,
146826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_143_WIDTH },
146827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_144_CHECKER_TYPE,
146828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_144_WIDTH },
146829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_145_CHECKER_TYPE,
146830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_145_WIDTH },
146831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_146_CHECKER_TYPE,
146832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_146_WIDTH },
146833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_147_CHECKER_TYPE,
146834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_147_WIDTH },
146835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_148_CHECKER_TYPE,
146836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_148_WIDTH },
146837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_149_CHECKER_TYPE,
146838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_149_WIDTH },
146839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_150_CHECKER_TYPE,
146840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_150_WIDTH },
146841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_151_CHECKER_TYPE,
146842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_151_WIDTH },
146843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_152_CHECKER_TYPE,
146844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_152_WIDTH },
146845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_153_CHECKER_TYPE,
146846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_153_WIDTH },
146847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_154_CHECKER_TYPE,
146848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_154_WIDTH },
146849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_155_CHECKER_TYPE,
146850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_155_WIDTH },
146851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_156_CHECKER_TYPE,
146852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_156_WIDTH },
146853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_157_CHECKER_TYPE,
146854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_157_WIDTH },
146855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_158_CHECKER_TYPE,
146856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_158_WIDTH },
146857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_159_CHECKER_TYPE,
146858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_159_WIDTH },
146859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_160_CHECKER_TYPE,
146860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_160_WIDTH },
146861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_161_CHECKER_TYPE,
146862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_161_WIDTH },
146863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_162_CHECKER_TYPE,
146864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_162_WIDTH },
146865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_163_CHECKER_TYPE,
146866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_163_WIDTH },
146867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_164_CHECKER_TYPE,
146868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_164_WIDTH },
146869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_165_CHECKER_TYPE,
146870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_165_WIDTH },
146871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_166_CHECKER_TYPE,
146872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_166_WIDTH },
146873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_167_CHECKER_TYPE,
146874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_167_WIDTH },
146875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_168_CHECKER_TYPE,
146876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_168_WIDTH },
146877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_169_CHECKER_TYPE,
146878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_169_WIDTH },
146879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_170_CHECKER_TYPE,
146880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_170_WIDTH },
146881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_171_CHECKER_TYPE,
146882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_171_WIDTH },
146883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_172_CHECKER_TYPE,
146884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_172_WIDTH },
146885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_173_CHECKER_TYPE,
146886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_173_WIDTH },
146887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_174_CHECKER_TYPE,
146888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_174_WIDTH },
146889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_175_CHECKER_TYPE,
146890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_175_WIDTH },
146891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_176_CHECKER_TYPE,
146892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_176_WIDTH },
146893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_177_CHECKER_TYPE,
146894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_177_WIDTH },
146895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_178_CHECKER_TYPE,
146896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_178_WIDTH },
146897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_179_CHECKER_TYPE,
146898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_179_WIDTH },
146899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_180_CHECKER_TYPE,
146900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_180_WIDTH },
146901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_181_CHECKER_TYPE,
146902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_181_WIDTH },
146903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_182_CHECKER_TYPE,
146904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_182_WIDTH },
146905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_183_CHECKER_TYPE,
146906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_183_WIDTH },
146907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_184_CHECKER_TYPE,
146908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_184_WIDTH },
146909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_185_CHECKER_TYPE,
146910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_185_WIDTH },
146911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_186_CHECKER_TYPE,
146912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_186_WIDTH },
146913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_187_CHECKER_TYPE,
146914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_187_WIDTH },
146915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_188_CHECKER_TYPE,
146916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_188_WIDTH },
146917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_189_CHECKER_TYPE,
146918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_189_WIDTH },
146919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_190_CHECKER_TYPE,
146920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_190_WIDTH },
146921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_191_CHECKER_TYPE,
146922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_191_WIDTH },
146923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_192_CHECKER_TYPE,
146924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_192_WIDTH },
146925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_193_CHECKER_TYPE,
146926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_193_WIDTH },
146927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_194_CHECKER_TYPE,
146928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_194_WIDTH },
146929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_195_CHECKER_TYPE,
146930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_195_WIDTH },
146931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_196_CHECKER_TYPE,
146932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_196_WIDTH },
146933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_197_CHECKER_TYPE,
146934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_197_WIDTH },
146935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_198_CHECKER_TYPE,
146936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_198_WIDTH },
146937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_199_CHECKER_TYPE,
146938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_199_WIDTH },
146939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_200_CHECKER_TYPE,
146940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_200_WIDTH },
146941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_201_CHECKER_TYPE,
146942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_201_WIDTH },
146943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_202_CHECKER_TYPE,
146944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_202_WIDTH },
146945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_203_CHECKER_TYPE,
146946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_203_WIDTH },
146947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_204_CHECKER_TYPE,
146948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_204_WIDTH },
146949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_205_CHECKER_TYPE,
146950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_205_WIDTH },
146951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_206_CHECKER_TYPE,
146952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_206_WIDTH },
146953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_207_CHECKER_TYPE,
146954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_207_WIDTH },
146955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_208_CHECKER_TYPE,
146956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_208_WIDTH },
146957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_209_CHECKER_TYPE,
146958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_209_WIDTH },
146959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_210_CHECKER_TYPE,
146960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_210_WIDTH },
146961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_211_CHECKER_TYPE,
146962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_211_WIDTH },
146963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_212_CHECKER_TYPE,
146964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_212_WIDTH },
146965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_213_CHECKER_TYPE,
146966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_213_WIDTH },
146967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_214_CHECKER_TYPE,
146968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_214_WIDTH },
146969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_215_CHECKER_TYPE,
146970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_215_WIDTH },
146971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_216_CHECKER_TYPE,
146972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_216_WIDTH },
146973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_217_CHECKER_TYPE,
146974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_217_WIDTH },
146975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_218_CHECKER_TYPE,
146976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_218_WIDTH },
146977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_219_CHECKER_TYPE,
146978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_219_WIDTH },
146979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_220_CHECKER_TYPE,
146980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_220_WIDTH },
146981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_221_CHECKER_TYPE,
146982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_221_WIDTH },
146983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_222_CHECKER_TYPE,
146984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_222_WIDTH },
146985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_223_CHECKER_TYPE,
146986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_223_WIDTH },
146987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_224_CHECKER_TYPE,
146988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_224_WIDTH },
146989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_225_CHECKER_TYPE,
146990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_225_WIDTH },
146991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_226_CHECKER_TYPE,
146992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_226_WIDTH },
146993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_227_CHECKER_TYPE,
146994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_227_WIDTH },
146995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_228_CHECKER_TYPE,
146996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_228_WIDTH },
146997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_229_CHECKER_TYPE,
146998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_229_WIDTH },
146999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_230_CHECKER_TYPE,
147000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_230_WIDTH },
147001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_231_CHECKER_TYPE,
147002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_231_WIDTH },
147003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_232_CHECKER_TYPE,
147004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_232_WIDTH },
147005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_233_CHECKER_TYPE,
147006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_233_WIDTH },
147007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_234_CHECKER_TYPE,
147008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_234_WIDTH },
147009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_235_CHECKER_TYPE,
147010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_235_WIDTH },
147011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_236_CHECKER_TYPE,
147012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_236_WIDTH },
147013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_237_CHECKER_TYPE,
147014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_237_WIDTH },
147015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_238_CHECKER_TYPE,
147016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_238_WIDTH },
147017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_239_CHECKER_TYPE,
147018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_239_WIDTH },
147019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_240_CHECKER_TYPE,
147020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_240_WIDTH },
147021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_241_CHECKER_TYPE,
147022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_241_WIDTH },
147023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_242_CHECKER_TYPE,
147024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_242_WIDTH },
147025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_243_CHECKER_TYPE,
147026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_243_WIDTH },
147027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_244_CHECKER_TYPE,
147028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_244_WIDTH },
147029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_245_CHECKER_TYPE,
147030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_245_WIDTH },
147031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_246_CHECKER_TYPE,
147032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_246_WIDTH },
147033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_247_CHECKER_TYPE,
147034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_247_WIDTH },
147035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_248_CHECKER_TYPE,
147036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_248_WIDTH },
147037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_249_CHECKER_TYPE,
147038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_249_WIDTH },
147039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_250_CHECKER_TYPE,
147040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_250_WIDTH },
147041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_251_CHECKER_TYPE,
147042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_251_WIDTH },
147043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_252_CHECKER_TYPE,
147044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_252_WIDTH },
147045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_253_CHECKER_TYPE,
147046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_253_WIDTH },
147047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_254_CHECKER_TYPE,
147048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_254_WIDTH },
147049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_255_CHECKER_TYPE,
147050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_GROUP_255_WIDTH },
147051 };
147052 
147058 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS] =
147059 {
147060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_0_CHECKER_TYPE,
147061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_0_WIDTH },
147062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_1_CHECKER_TYPE,
147063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_1_WIDTH },
147064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_2_CHECKER_TYPE,
147065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_2_WIDTH },
147066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_3_CHECKER_TYPE,
147067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_3_WIDTH },
147068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_4_CHECKER_TYPE,
147069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_4_WIDTH },
147070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_5_CHECKER_TYPE,
147071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_5_WIDTH },
147072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_6_CHECKER_TYPE,
147073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_6_WIDTH },
147074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_7_CHECKER_TYPE,
147075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_7_WIDTH },
147076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_8_CHECKER_TYPE,
147077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_8_WIDTH },
147078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_9_CHECKER_TYPE,
147079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_9_WIDTH },
147080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_10_CHECKER_TYPE,
147081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_10_WIDTH },
147082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_11_CHECKER_TYPE,
147083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_11_WIDTH },
147084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_12_CHECKER_TYPE,
147085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_12_WIDTH },
147086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_13_CHECKER_TYPE,
147087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_13_WIDTH },
147088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_14_CHECKER_TYPE,
147089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_14_WIDTH },
147090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_15_CHECKER_TYPE,
147091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_15_WIDTH },
147092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_16_CHECKER_TYPE,
147093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_16_WIDTH },
147094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_17_CHECKER_TYPE,
147095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_17_WIDTH },
147096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_18_CHECKER_TYPE,
147097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_18_WIDTH },
147098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_19_CHECKER_TYPE,
147099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_19_WIDTH },
147100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_20_CHECKER_TYPE,
147101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_20_WIDTH },
147102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_21_CHECKER_TYPE,
147103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_21_WIDTH },
147104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_22_CHECKER_TYPE,
147105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_22_WIDTH },
147106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_23_CHECKER_TYPE,
147107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_23_WIDTH },
147108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_24_CHECKER_TYPE,
147109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_24_WIDTH },
147110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_25_CHECKER_TYPE,
147111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_25_WIDTH },
147112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_26_CHECKER_TYPE,
147113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_26_WIDTH },
147114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_27_CHECKER_TYPE,
147115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_27_WIDTH },
147116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_28_CHECKER_TYPE,
147117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_28_WIDTH },
147118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_29_CHECKER_TYPE,
147119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_29_WIDTH },
147120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_30_CHECKER_TYPE,
147121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_30_WIDTH },
147122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_31_CHECKER_TYPE,
147123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_31_WIDTH },
147124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_32_CHECKER_TYPE,
147125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_32_WIDTH },
147126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_33_CHECKER_TYPE,
147127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_33_WIDTH },
147128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_34_CHECKER_TYPE,
147129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_34_WIDTH },
147130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_35_CHECKER_TYPE,
147131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_35_WIDTH },
147132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_36_CHECKER_TYPE,
147133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_36_WIDTH },
147134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_37_CHECKER_TYPE,
147135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_37_WIDTH },
147136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_38_CHECKER_TYPE,
147137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_38_WIDTH },
147138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_39_CHECKER_TYPE,
147139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_39_WIDTH },
147140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_40_CHECKER_TYPE,
147141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_40_WIDTH },
147142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_41_CHECKER_TYPE,
147143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_41_WIDTH },
147144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_42_CHECKER_TYPE,
147145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_42_WIDTH },
147146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_43_CHECKER_TYPE,
147147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_43_WIDTH },
147148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_44_CHECKER_TYPE,
147149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_44_WIDTH },
147150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_45_CHECKER_TYPE,
147151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_45_WIDTH },
147152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_46_CHECKER_TYPE,
147153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_46_WIDTH },
147154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_47_CHECKER_TYPE,
147155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_47_WIDTH },
147156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_48_CHECKER_TYPE,
147157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_48_WIDTH },
147158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_49_CHECKER_TYPE,
147159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_49_WIDTH },
147160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_50_CHECKER_TYPE,
147161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_50_WIDTH },
147162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_51_CHECKER_TYPE,
147163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_51_WIDTH },
147164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_52_CHECKER_TYPE,
147165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_52_WIDTH },
147166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_53_CHECKER_TYPE,
147167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_53_WIDTH },
147168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_54_CHECKER_TYPE,
147169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_54_WIDTH },
147170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_55_CHECKER_TYPE,
147171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_55_WIDTH },
147172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_56_CHECKER_TYPE,
147173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_56_WIDTH },
147174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_57_CHECKER_TYPE,
147175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_57_WIDTH },
147176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_58_CHECKER_TYPE,
147177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_58_WIDTH },
147178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_59_CHECKER_TYPE,
147179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_59_WIDTH },
147180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_60_CHECKER_TYPE,
147181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_60_WIDTH },
147182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_61_CHECKER_TYPE,
147183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_61_WIDTH },
147184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_62_CHECKER_TYPE,
147185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_62_WIDTH },
147186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_63_CHECKER_TYPE,
147187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_63_WIDTH },
147188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_64_CHECKER_TYPE,
147189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_64_WIDTH },
147190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_65_CHECKER_TYPE,
147191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_65_WIDTH },
147192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_66_CHECKER_TYPE,
147193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_66_WIDTH },
147194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_67_CHECKER_TYPE,
147195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_67_WIDTH },
147196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_68_CHECKER_TYPE,
147197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_68_WIDTH },
147198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_69_CHECKER_TYPE,
147199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_69_WIDTH },
147200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_70_CHECKER_TYPE,
147201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_70_WIDTH },
147202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_71_CHECKER_TYPE,
147203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_71_WIDTH },
147204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_72_CHECKER_TYPE,
147205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_72_WIDTH },
147206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_73_CHECKER_TYPE,
147207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_73_WIDTH },
147208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_74_CHECKER_TYPE,
147209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_74_WIDTH },
147210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_75_CHECKER_TYPE,
147211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_75_WIDTH },
147212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_76_CHECKER_TYPE,
147213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_76_WIDTH },
147214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_77_CHECKER_TYPE,
147215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_77_WIDTH },
147216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_78_CHECKER_TYPE,
147217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_78_WIDTH },
147218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_79_CHECKER_TYPE,
147219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_79_WIDTH },
147220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_80_CHECKER_TYPE,
147221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_80_WIDTH },
147222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_81_CHECKER_TYPE,
147223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_81_WIDTH },
147224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_82_CHECKER_TYPE,
147225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_82_WIDTH },
147226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_83_CHECKER_TYPE,
147227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_83_WIDTH },
147228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_84_CHECKER_TYPE,
147229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_84_WIDTH },
147230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_85_CHECKER_TYPE,
147231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_85_WIDTH },
147232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_86_CHECKER_TYPE,
147233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_86_WIDTH },
147234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_87_CHECKER_TYPE,
147235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_87_WIDTH },
147236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_88_CHECKER_TYPE,
147237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_88_WIDTH },
147238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_89_CHECKER_TYPE,
147239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_89_WIDTH },
147240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_90_CHECKER_TYPE,
147241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_90_WIDTH },
147242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_91_CHECKER_TYPE,
147243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_91_WIDTH },
147244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_92_CHECKER_TYPE,
147245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_92_WIDTH },
147246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_93_CHECKER_TYPE,
147247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_93_WIDTH },
147248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_94_CHECKER_TYPE,
147249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_94_WIDTH },
147250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_95_CHECKER_TYPE,
147251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_95_WIDTH },
147252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_96_CHECKER_TYPE,
147253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_96_WIDTH },
147254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_97_CHECKER_TYPE,
147255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_97_WIDTH },
147256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_98_CHECKER_TYPE,
147257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_98_WIDTH },
147258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_99_CHECKER_TYPE,
147259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_99_WIDTH },
147260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_100_CHECKER_TYPE,
147261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_100_WIDTH },
147262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_101_CHECKER_TYPE,
147263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_101_WIDTH },
147264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_102_CHECKER_TYPE,
147265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_102_WIDTH },
147266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_103_CHECKER_TYPE,
147267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_103_WIDTH },
147268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_104_CHECKER_TYPE,
147269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_104_WIDTH },
147270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_105_CHECKER_TYPE,
147271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_105_WIDTH },
147272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_106_CHECKER_TYPE,
147273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_106_WIDTH },
147274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_107_CHECKER_TYPE,
147275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_107_WIDTH },
147276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_108_CHECKER_TYPE,
147277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_108_WIDTH },
147278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_109_CHECKER_TYPE,
147279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_109_WIDTH },
147280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_110_CHECKER_TYPE,
147281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_110_WIDTH },
147282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_111_CHECKER_TYPE,
147283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_111_WIDTH },
147284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_112_CHECKER_TYPE,
147285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_112_WIDTH },
147286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_113_CHECKER_TYPE,
147287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_113_WIDTH },
147288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_114_CHECKER_TYPE,
147289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_114_WIDTH },
147290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_115_CHECKER_TYPE,
147291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_115_WIDTH },
147292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_116_CHECKER_TYPE,
147293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_116_WIDTH },
147294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_117_CHECKER_TYPE,
147295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_117_WIDTH },
147296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_118_CHECKER_TYPE,
147297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_118_WIDTH },
147298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_119_CHECKER_TYPE,
147299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_119_WIDTH },
147300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_120_CHECKER_TYPE,
147301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_120_WIDTH },
147302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_121_CHECKER_TYPE,
147303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_121_WIDTH },
147304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_122_CHECKER_TYPE,
147305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_122_WIDTH },
147306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_123_CHECKER_TYPE,
147307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_123_WIDTH },
147308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_124_CHECKER_TYPE,
147309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_124_WIDTH },
147310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_125_CHECKER_TYPE,
147311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_125_WIDTH },
147312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_126_CHECKER_TYPE,
147313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_126_WIDTH },
147314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_127_CHECKER_TYPE,
147315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_127_WIDTH },
147316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_128_CHECKER_TYPE,
147317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_128_WIDTH },
147318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_129_CHECKER_TYPE,
147319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_129_WIDTH },
147320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_130_CHECKER_TYPE,
147321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_130_WIDTH },
147322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_131_CHECKER_TYPE,
147323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_131_WIDTH },
147324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_132_CHECKER_TYPE,
147325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_132_WIDTH },
147326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_133_CHECKER_TYPE,
147327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_133_WIDTH },
147328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_134_CHECKER_TYPE,
147329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_134_WIDTH },
147330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_135_CHECKER_TYPE,
147331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_135_WIDTH },
147332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_136_CHECKER_TYPE,
147333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_136_WIDTH },
147334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_137_CHECKER_TYPE,
147335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_137_WIDTH },
147336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_138_CHECKER_TYPE,
147337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_138_WIDTH },
147338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_139_CHECKER_TYPE,
147339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_139_WIDTH },
147340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_140_CHECKER_TYPE,
147341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_140_WIDTH },
147342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_141_CHECKER_TYPE,
147343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_141_WIDTH },
147344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_142_CHECKER_TYPE,
147345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_142_WIDTH },
147346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_143_CHECKER_TYPE,
147347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_143_WIDTH },
147348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_144_CHECKER_TYPE,
147349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_144_WIDTH },
147350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_145_CHECKER_TYPE,
147351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_145_WIDTH },
147352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_146_CHECKER_TYPE,
147353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_146_WIDTH },
147354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_147_CHECKER_TYPE,
147355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_147_WIDTH },
147356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_148_CHECKER_TYPE,
147357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_148_WIDTH },
147358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_149_CHECKER_TYPE,
147359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_149_WIDTH },
147360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_150_CHECKER_TYPE,
147361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_150_WIDTH },
147362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_151_CHECKER_TYPE,
147363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_151_WIDTH },
147364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_152_CHECKER_TYPE,
147365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_152_WIDTH },
147366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_153_CHECKER_TYPE,
147367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_153_WIDTH },
147368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_154_CHECKER_TYPE,
147369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_154_WIDTH },
147370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_155_CHECKER_TYPE,
147371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_155_WIDTH },
147372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_156_CHECKER_TYPE,
147373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_156_WIDTH },
147374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_157_CHECKER_TYPE,
147375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_157_WIDTH },
147376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_158_CHECKER_TYPE,
147377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_158_WIDTH },
147378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_159_CHECKER_TYPE,
147379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_159_WIDTH },
147380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_160_CHECKER_TYPE,
147381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_160_WIDTH },
147382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_161_CHECKER_TYPE,
147383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_161_WIDTH },
147384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_162_CHECKER_TYPE,
147385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_162_WIDTH },
147386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_163_CHECKER_TYPE,
147387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_163_WIDTH },
147388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_164_CHECKER_TYPE,
147389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_164_WIDTH },
147390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_165_CHECKER_TYPE,
147391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_165_WIDTH },
147392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_166_CHECKER_TYPE,
147393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_166_WIDTH },
147394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_167_CHECKER_TYPE,
147395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_167_WIDTH },
147396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_168_CHECKER_TYPE,
147397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_168_WIDTH },
147398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_169_CHECKER_TYPE,
147399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_169_WIDTH },
147400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_170_CHECKER_TYPE,
147401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_170_WIDTH },
147402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_171_CHECKER_TYPE,
147403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_171_WIDTH },
147404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_172_CHECKER_TYPE,
147405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_172_WIDTH },
147406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_173_CHECKER_TYPE,
147407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_173_WIDTH },
147408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_174_CHECKER_TYPE,
147409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_174_WIDTH },
147410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_175_CHECKER_TYPE,
147411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_175_WIDTH },
147412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_176_CHECKER_TYPE,
147413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_176_WIDTH },
147414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_177_CHECKER_TYPE,
147415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_177_WIDTH },
147416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_178_CHECKER_TYPE,
147417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_178_WIDTH },
147418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_179_CHECKER_TYPE,
147419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_179_WIDTH },
147420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_180_CHECKER_TYPE,
147421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_180_WIDTH },
147422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_181_CHECKER_TYPE,
147423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_181_WIDTH },
147424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_182_CHECKER_TYPE,
147425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_182_WIDTH },
147426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_183_CHECKER_TYPE,
147427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_183_WIDTH },
147428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_184_CHECKER_TYPE,
147429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_184_WIDTH },
147430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_185_CHECKER_TYPE,
147431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_185_WIDTH },
147432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_186_CHECKER_TYPE,
147433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_186_WIDTH },
147434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_187_CHECKER_TYPE,
147435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_187_WIDTH },
147436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_188_CHECKER_TYPE,
147437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_188_WIDTH },
147438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_189_CHECKER_TYPE,
147439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_189_WIDTH },
147440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_190_CHECKER_TYPE,
147441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_190_WIDTH },
147442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_191_CHECKER_TYPE,
147443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_191_WIDTH },
147444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_192_CHECKER_TYPE,
147445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_192_WIDTH },
147446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_193_CHECKER_TYPE,
147447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_193_WIDTH },
147448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_194_CHECKER_TYPE,
147449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_194_WIDTH },
147450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_195_CHECKER_TYPE,
147451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_195_WIDTH },
147452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_196_CHECKER_TYPE,
147453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_196_WIDTH },
147454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_197_CHECKER_TYPE,
147455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_197_WIDTH },
147456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_198_CHECKER_TYPE,
147457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_198_WIDTH },
147458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_199_CHECKER_TYPE,
147459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_199_WIDTH },
147460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_200_CHECKER_TYPE,
147461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_200_WIDTH },
147462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_201_CHECKER_TYPE,
147463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_201_WIDTH },
147464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_202_CHECKER_TYPE,
147465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_202_WIDTH },
147466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_203_CHECKER_TYPE,
147467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_203_WIDTH },
147468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_204_CHECKER_TYPE,
147469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_204_WIDTH },
147470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_205_CHECKER_TYPE,
147471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_205_WIDTH },
147472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_206_CHECKER_TYPE,
147473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_206_WIDTH },
147474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_207_CHECKER_TYPE,
147475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_207_WIDTH },
147476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_208_CHECKER_TYPE,
147477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_208_WIDTH },
147478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_209_CHECKER_TYPE,
147479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_209_WIDTH },
147480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_210_CHECKER_TYPE,
147481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_210_WIDTH },
147482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_211_CHECKER_TYPE,
147483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_211_WIDTH },
147484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_212_CHECKER_TYPE,
147485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_212_WIDTH },
147486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_213_CHECKER_TYPE,
147487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_213_WIDTH },
147488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_214_CHECKER_TYPE,
147489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_214_WIDTH },
147490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_215_CHECKER_TYPE,
147491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_215_WIDTH },
147492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_216_CHECKER_TYPE,
147493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_216_WIDTH },
147494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_217_CHECKER_TYPE,
147495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_217_WIDTH },
147496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_218_CHECKER_TYPE,
147497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_218_WIDTH },
147498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_219_CHECKER_TYPE,
147499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_219_WIDTH },
147500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_220_CHECKER_TYPE,
147501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_220_WIDTH },
147502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_221_CHECKER_TYPE,
147503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_221_WIDTH },
147504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_222_CHECKER_TYPE,
147505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_222_WIDTH },
147506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_223_CHECKER_TYPE,
147507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_223_WIDTH },
147508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_224_CHECKER_TYPE,
147509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_224_WIDTH },
147510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_225_CHECKER_TYPE,
147511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_225_WIDTH },
147512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_226_CHECKER_TYPE,
147513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_226_WIDTH },
147514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_227_CHECKER_TYPE,
147515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_227_WIDTH },
147516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_228_CHECKER_TYPE,
147517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_228_WIDTH },
147518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_229_CHECKER_TYPE,
147519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_229_WIDTH },
147520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_230_CHECKER_TYPE,
147521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_230_WIDTH },
147522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_231_CHECKER_TYPE,
147523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_231_WIDTH },
147524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_232_CHECKER_TYPE,
147525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_232_WIDTH },
147526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_233_CHECKER_TYPE,
147527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_233_WIDTH },
147528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_234_CHECKER_TYPE,
147529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_234_WIDTH },
147530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_235_CHECKER_TYPE,
147531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_235_WIDTH },
147532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_236_CHECKER_TYPE,
147533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_236_WIDTH },
147534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_237_CHECKER_TYPE,
147535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_237_WIDTH },
147536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_238_CHECKER_TYPE,
147537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_238_WIDTH },
147538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_239_CHECKER_TYPE,
147539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_239_WIDTH },
147540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_240_CHECKER_TYPE,
147541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_240_WIDTH },
147542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_241_CHECKER_TYPE,
147543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_241_WIDTH },
147544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_242_CHECKER_TYPE,
147545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_242_WIDTH },
147546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_243_CHECKER_TYPE,
147547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_243_WIDTH },
147548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_244_CHECKER_TYPE,
147549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_244_WIDTH },
147550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_245_CHECKER_TYPE,
147551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_245_WIDTH },
147552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_246_CHECKER_TYPE,
147553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_246_WIDTH },
147554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_247_CHECKER_TYPE,
147555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_247_WIDTH },
147556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_248_CHECKER_TYPE,
147557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_248_WIDTH },
147558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_249_CHECKER_TYPE,
147559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_249_WIDTH },
147560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_250_CHECKER_TYPE,
147561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_250_WIDTH },
147562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_251_CHECKER_TYPE,
147563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_251_WIDTH },
147564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_252_CHECKER_TYPE,
147565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_252_WIDTH },
147566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_253_CHECKER_TYPE,
147567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_253_WIDTH },
147568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_254_CHECKER_TYPE,
147569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_254_WIDTH },
147570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_255_CHECKER_TYPE,
147571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_GROUP_255_WIDTH },
147572 };
147573 
147579 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS] =
147580 {
147581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_0_CHECKER_TYPE,
147582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_0_WIDTH },
147583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_1_CHECKER_TYPE,
147584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_1_WIDTH },
147585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_2_CHECKER_TYPE,
147586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_2_WIDTH },
147587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_3_CHECKER_TYPE,
147588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_3_WIDTH },
147589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_4_CHECKER_TYPE,
147590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_4_WIDTH },
147591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_5_CHECKER_TYPE,
147592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_5_WIDTH },
147593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_6_CHECKER_TYPE,
147594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_6_WIDTH },
147595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_7_CHECKER_TYPE,
147596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_7_WIDTH },
147597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_8_CHECKER_TYPE,
147598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_8_WIDTH },
147599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_9_CHECKER_TYPE,
147600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_9_WIDTH },
147601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_10_CHECKER_TYPE,
147602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_10_WIDTH },
147603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_11_CHECKER_TYPE,
147604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_11_WIDTH },
147605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_12_CHECKER_TYPE,
147606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_12_WIDTH },
147607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_13_CHECKER_TYPE,
147608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_13_WIDTH },
147609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_14_CHECKER_TYPE,
147610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_14_WIDTH },
147611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_15_CHECKER_TYPE,
147612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_15_WIDTH },
147613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_16_CHECKER_TYPE,
147614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_16_WIDTH },
147615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_17_CHECKER_TYPE,
147616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_17_WIDTH },
147617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_18_CHECKER_TYPE,
147618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_18_WIDTH },
147619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_19_CHECKER_TYPE,
147620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_19_WIDTH },
147621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_20_CHECKER_TYPE,
147622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_20_WIDTH },
147623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_21_CHECKER_TYPE,
147624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_21_WIDTH },
147625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_22_CHECKER_TYPE,
147626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_22_WIDTH },
147627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_23_CHECKER_TYPE,
147628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_23_WIDTH },
147629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_24_CHECKER_TYPE,
147630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_24_WIDTH },
147631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_25_CHECKER_TYPE,
147632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_25_WIDTH },
147633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_26_CHECKER_TYPE,
147634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_26_WIDTH },
147635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_27_CHECKER_TYPE,
147636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_27_WIDTH },
147637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_28_CHECKER_TYPE,
147638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_28_WIDTH },
147639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_29_CHECKER_TYPE,
147640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_29_WIDTH },
147641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_30_CHECKER_TYPE,
147642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_30_WIDTH },
147643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_31_CHECKER_TYPE,
147644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_31_WIDTH },
147645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_32_CHECKER_TYPE,
147646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_32_WIDTH },
147647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_33_CHECKER_TYPE,
147648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_33_WIDTH },
147649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_34_CHECKER_TYPE,
147650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_34_WIDTH },
147651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_35_CHECKER_TYPE,
147652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_35_WIDTH },
147653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_36_CHECKER_TYPE,
147654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_36_WIDTH },
147655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_37_CHECKER_TYPE,
147656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_37_WIDTH },
147657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_38_CHECKER_TYPE,
147658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_38_WIDTH },
147659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_39_CHECKER_TYPE,
147660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_39_WIDTH },
147661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_40_CHECKER_TYPE,
147662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_40_WIDTH },
147663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_41_CHECKER_TYPE,
147664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_41_WIDTH },
147665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_42_CHECKER_TYPE,
147666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_42_WIDTH },
147667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_43_CHECKER_TYPE,
147668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_43_WIDTH },
147669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_44_CHECKER_TYPE,
147670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_44_WIDTH },
147671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_45_CHECKER_TYPE,
147672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_45_WIDTH },
147673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_46_CHECKER_TYPE,
147674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_46_WIDTH },
147675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_47_CHECKER_TYPE,
147676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_47_WIDTH },
147677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_48_CHECKER_TYPE,
147678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_48_WIDTH },
147679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_49_CHECKER_TYPE,
147680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_49_WIDTH },
147681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_50_CHECKER_TYPE,
147682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_50_WIDTH },
147683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_51_CHECKER_TYPE,
147684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_51_WIDTH },
147685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_52_CHECKER_TYPE,
147686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_52_WIDTH },
147687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_53_CHECKER_TYPE,
147688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_53_WIDTH },
147689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_54_CHECKER_TYPE,
147690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_54_WIDTH },
147691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_55_CHECKER_TYPE,
147692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_55_WIDTH },
147693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_56_CHECKER_TYPE,
147694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_56_WIDTH },
147695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_57_CHECKER_TYPE,
147696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_57_WIDTH },
147697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_58_CHECKER_TYPE,
147698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_58_WIDTH },
147699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_59_CHECKER_TYPE,
147700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_59_WIDTH },
147701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_60_CHECKER_TYPE,
147702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_60_WIDTH },
147703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_61_CHECKER_TYPE,
147704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_61_WIDTH },
147705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_62_CHECKER_TYPE,
147706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_62_WIDTH },
147707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_63_CHECKER_TYPE,
147708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_63_WIDTH },
147709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_64_CHECKER_TYPE,
147710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_64_WIDTH },
147711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_65_CHECKER_TYPE,
147712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_65_WIDTH },
147713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_66_CHECKER_TYPE,
147714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_66_WIDTH },
147715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_67_CHECKER_TYPE,
147716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_67_WIDTH },
147717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_68_CHECKER_TYPE,
147718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_68_WIDTH },
147719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_69_CHECKER_TYPE,
147720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_69_WIDTH },
147721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_70_CHECKER_TYPE,
147722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_70_WIDTH },
147723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_71_CHECKER_TYPE,
147724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_71_WIDTH },
147725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_72_CHECKER_TYPE,
147726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_72_WIDTH },
147727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_73_CHECKER_TYPE,
147728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_73_WIDTH },
147729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_74_CHECKER_TYPE,
147730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_74_WIDTH },
147731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_75_CHECKER_TYPE,
147732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_75_WIDTH },
147733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_76_CHECKER_TYPE,
147734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_76_WIDTH },
147735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_77_CHECKER_TYPE,
147736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_77_WIDTH },
147737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_78_CHECKER_TYPE,
147738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_78_WIDTH },
147739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_79_CHECKER_TYPE,
147740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_79_WIDTH },
147741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_80_CHECKER_TYPE,
147742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_80_WIDTH },
147743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_81_CHECKER_TYPE,
147744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_81_WIDTH },
147745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_82_CHECKER_TYPE,
147746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_82_WIDTH },
147747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_83_CHECKER_TYPE,
147748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_83_WIDTH },
147749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_84_CHECKER_TYPE,
147750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_84_WIDTH },
147751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_85_CHECKER_TYPE,
147752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_85_WIDTH },
147753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_86_CHECKER_TYPE,
147754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_86_WIDTH },
147755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_87_CHECKER_TYPE,
147756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_87_WIDTH },
147757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_88_CHECKER_TYPE,
147758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_88_WIDTH },
147759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_89_CHECKER_TYPE,
147760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_89_WIDTH },
147761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_90_CHECKER_TYPE,
147762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_90_WIDTH },
147763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_91_CHECKER_TYPE,
147764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_91_WIDTH },
147765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_92_CHECKER_TYPE,
147766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_92_WIDTH },
147767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_93_CHECKER_TYPE,
147768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_93_WIDTH },
147769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_94_CHECKER_TYPE,
147770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_94_WIDTH },
147771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_95_CHECKER_TYPE,
147772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_95_WIDTH },
147773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_96_CHECKER_TYPE,
147774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_96_WIDTH },
147775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_97_CHECKER_TYPE,
147776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_97_WIDTH },
147777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_98_CHECKER_TYPE,
147778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_98_WIDTH },
147779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_99_CHECKER_TYPE,
147780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_99_WIDTH },
147781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_100_CHECKER_TYPE,
147782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_100_WIDTH },
147783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_101_CHECKER_TYPE,
147784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_101_WIDTH },
147785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_102_CHECKER_TYPE,
147786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_102_WIDTH },
147787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_103_CHECKER_TYPE,
147788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_103_WIDTH },
147789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_104_CHECKER_TYPE,
147790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_104_WIDTH },
147791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_105_CHECKER_TYPE,
147792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_105_WIDTH },
147793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_106_CHECKER_TYPE,
147794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_106_WIDTH },
147795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_107_CHECKER_TYPE,
147796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_107_WIDTH },
147797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_108_CHECKER_TYPE,
147798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_108_WIDTH },
147799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_109_CHECKER_TYPE,
147800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_109_WIDTH },
147801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_110_CHECKER_TYPE,
147802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_110_WIDTH },
147803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_111_CHECKER_TYPE,
147804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_111_WIDTH },
147805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_112_CHECKER_TYPE,
147806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_112_WIDTH },
147807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_113_CHECKER_TYPE,
147808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_113_WIDTH },
147809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_114_CHECKER_TYPE,
147810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_114_WIDTH },
147811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_115_CHECKER_TYPE,
147812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_115_WIDTH },
147813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_116_CHECKER_TYPE,
147814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_116_WIDTH },
147815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_117_CHECKER_TYPE,
147816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_117_WIDTH },
147817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_118_CHECKER_TYPE,
147818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_118_WIDTH },
147819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_119_CHECKER_TYPE,
147820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_119_WIDTH },
147821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_120_CHECKER_TYPE,
147822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_120_WIDTH },
147823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_121_CHECKER_TYPE,
147824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_121_WIDTH },
147825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_122_CHECKER_TYPE,
147826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_122_WIDTH },
147827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_123_CHECKER_TYPE,
147828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_123_WIDTH },
147829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_124_CHECKER_TYPE,
147830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_124_WIDTH },
147831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_125_CHECKER_TYPE,
147832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_125_WIDTH },
147833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_126_CHECKER_TYPE,
147834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_126_WIDTH },
147835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_127_CHECKER_TYPE,
147836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_127_WIDTH },
147837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_128_CHECKER_TYPE,
147838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_128_WIDTH },
147839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_129_CHECKER_TYPE,
147840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_129_WIDTH },
147841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_130_CHECKER_TYPE,
147842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_130_WIDTH },
147843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_131_CHECKER_TYPE,
147844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_131_WIDTH },
147845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_132_CHECKER_TYPE,
147846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_132_WIDTH },
147847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_133_CHECKER_TYPE,
147848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_133_WIDTH },
147849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_134_CHECKER_TYPE,
147850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_134_WIDTH },
147851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_135_CHECKER_TYPE,
147852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_135_WIDTH },
147853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_136_CHECKER_TYPE,
147854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_136_WIDTH },
147855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_137_CHECKER_TYPE,
147856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_137_WIDTH },
147857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_138_CHECKER_TYPE,
147858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_138_WIDTH },
147859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_139_CHECKER_TYPE,
147860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_139_WIDTH },
147861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_140_CHECKER_TYPE,
147862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_140_WIDTH },
147863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_141_CHECKER_TYPE,
147864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_141_WIDTH },
147865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_142_CHECKER_TYPE,
147866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_142_WIDTH },
147867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_143_CHECKER_TYPE,
147868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_143_WIDTH },
147869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_144_CHECKER_TYPE,
147870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_144_WIDTH },
147871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_145_CHECKER_TYPE,
147872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_145_WIDTH },
147873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_146_CHECKER_TYPE,
147874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_146_WIDTH },
147875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_147_CHECKER_TYPE,
147876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_147_WIDTH },
147877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_148_CHECKER_TYPE,
147878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_148_WIDTH },
147879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_149_CHECKER_TYPE,
147880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_149_WIDTH },
147881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_150_CHECKER_TYPE,
147882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_150_WIDTH },
147883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_151_CHECKER_TYPE,
147884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_151_WIDTH },
147885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_152_CHECKER_TYPE,
147886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_152_WIDTH },
147887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_153_CHECKER_TYPE,
147888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_153_WIDTH },
147889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_154_CHECKER_TYPE,
147890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_154_WIDTH },
147891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_155_CHECKER_TYPE,
147892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_155_WIDTH },
147893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_156_CHECKER_TYPE,
147894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_156_WIDTH },
147895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_157_CHECKER_TYPE,
147896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_157_WIDTH },
147897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_158_CHECKER_TYPE,
147898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_158_WIDTH },
147899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_159_CHECKER_TYPE,
147900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_159_WIDTH },
147901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_160_CHECKER_TYPE,
147902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_160_WIDTH },
147903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_161_CHECKER_TYPE,
147904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_161_WIDTH },
147905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_162_CHECKER_TYPE,
147906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_162_WIDTH },
147907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_163_CHECKER_TYPE,
147908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_163_WIDTH },
147909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_164_CHECKER_TYPE,
147910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_164_WIDTH },
147911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_165_CHECKER_TYPE,
147912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_165_WIDTH },
147913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_166_CHECKER_TYPE,
147914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_166_WIDTH },
147915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_167_CHECKER_TYPE,
147916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_167_WIDTH },
147917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_168_CHECKER_TYPE,
147918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_168_WIDTH },
147919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_169_CHECKER_TYPE,
147920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_169_WIDTH },
147921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_170_CHECKER_TYPE,
147922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_170_WIDTH },
147923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_171_CHECKER_TYPE,
147924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_171_WIDTH },
147925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_172_CHECKER_TYPE,
147926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_172_WIDTH },
147927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_173_CHECKER_TYPE,
147928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_173_WIDTH },
147929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_174_CHECKER_TYPE,
147930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_174_WIDTH },
147931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_175_CHECKER_TYPE,
147932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_175_WIDTH },
147933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_176_CHECKER_TYPE,
147934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_176_WIDTH },
147935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_177_CHECKER_TYPE,
147936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_177_WIDTH },
147937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_178_CHECKER_TYPE,
147938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_178_WIDTH },
147939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_179_CHECKER_TYPE,
147940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_179_WIDTH },
147941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_180_CHECKER_TYPE,
147942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_180_WIDTH },
147943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_181_CHECKER_TYPE,
147944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_181_WIDTH },
147945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_182_CHECKER_TYPE,
147946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_182_WIDTH },
147947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_183_CHECKER_TYPE,
147948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_183_WIDTH },
147949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_184_CHECKER_TYPE,
147950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_184_WIDTH },
147951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_185_CHECKER_TYPE,
147952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_185_WIDTH },
147953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_186_CHECKER_TYPE,
147954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_186_WIDTH },
147955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_187_CHECKER_TYPE,
147956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_187_WIDTH },
147957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_188_CHECKER_TYPE,
147958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_188_WIDTH },
147959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_189_CHECKER_TYPE,
147960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_189_WIDTH },
147961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_190_CHECKER_TYPE,
147962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_190_WIDTH },
147963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_191_CHECKER_TYPE,
147964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_191_WIDTH },
147965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_192_CHECKER_TYPE,
147966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_192_WIDTH },
147967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_193_CHECKER_TYPE,
147968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_193_WIDTH },
147969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_194_CHECKER_TYPE,
147970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_194_WIDTH },
147971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_195_CHECKER_TYPE,
147972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_195_WIDTH },
147973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_196_CHECKER_TYPE,
147974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_196_WIDTH },
147975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_197_CHECKER_TYPE,
147976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_197_WIDTH },
147977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_198_CHECKER_TYPE,
147978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_198_WIDTH },
147979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_199_CHECKER_TYPE,
147980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_199_WIDTH },
147981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_200_CHECKER_TYPE,
147982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_200_WIDTH },
147983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_201_CHECKER_TYPE,
147984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_201_WIDTH },
147985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_202_CHECKER_TYPE,
147986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_202_WIDTH },
147987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_203_CHECKER_TYPE,
147988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_203_WIDTH },
147989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_204_CHECKER_TYPE,
147990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_204_WIDTH },
147991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_205_CHECKER_TYPE,
147992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_205_WIDTH },
147993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_206_CHECKER_TYPE,
147994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_206_WIDTH },
147995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_207_CHECKER_TYPE,
147996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_207_WIDTH },
147997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_208_CHECKER_TYPE,
147998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_208_WIDTH },
147999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_209_CHECKER_TYPE,
148000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_209_WIDTH },
148001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_210_CHECKER_TYPE,
148002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_210_WIDTH },
148003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_211_CHECKER_TYPE,
148004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_211_WIDTH },
148005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_212_CHECKER_TYPE,
148006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_212_WIDTH },
148007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_213_CHECKER_TYPE,
148008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_213_WIDTH },
148009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_214_CHECKER_TYPE,
148010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_214_WIDTH },
148011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_215_CHECKER_TYPE,
148012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_215_WIDTH },
148013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_216_CHECKER_TYPE,
148014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_216_WIDTH },
148015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_217_CHECKER_TYPE,
148016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_217_WIDTH },
148017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_218_CHECKER_TYPE,
148018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_218_WIDTH },
148019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_219_CHECKER_TYPE,
148020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_219_WIDTH },
148021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_220_CHECKER_TYPE,
148022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_220_WIDTH },
148023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_221_CHECKER_TYPE,
148024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_221_WIDTH },
148025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_222_CHECKER_TYPE,
148026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_222_WIDTH },
148027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_223_CHECKER_TYPE,
148028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_223_WIDTH },
148029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_224_CHECKER_TYPE,
148030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_224_WIDTH },
148031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_225_CHECKER_TYPE,
148032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_225_WIDTH },
148033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_226_CHECKER_TYPE,
148034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_226_WIDTH },
148035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_227_CHECKER_TYPE,
148036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_227_WIDTH },
148037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_228_CHECKER_TYPE,
148038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_228_WIDTH },
148039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_229_CHECKER_TYPE,
148040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_229_WIDTH },
148041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_230_CHECKER_TYPE,
148042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_230_WIDTH },
148043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_231_CHECKER_TYPE,
148044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_231_WIDTH },
148045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_232_CHECKER_TYPE,
148046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_232_WIDTH },
148047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_233_CHECKER_TYPE,
148048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_233_WIDTH },
148049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_234_CHECKER_TYPE,
148050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_234_WIDTH },
148051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_235_CHECKER_TYPE,
148052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_235_WIDTH },
148053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_236_CHECKER_TYPE,
148054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_236_WIDTH },
148055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_237_CHECKER_TYPE,
148056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_237_WIDTH },
148057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_238_CHECKER_TYPE,
148058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_238_WIDTH },
148059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_239_CHECKER_TYPE,
148060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_239_WIDTH },
148061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_240_CHECKER_TYPE,
148062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_240_WIDTH },
148063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_241_CHECKER_TYPE,
148064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_241_WIDTH },
148065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_242_CHECKER_TYPE,
148066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_242_WIDTH },
148067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_243_CHECKER_TYPE,
148068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_243_WIDTH },
148069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_244_CHECKER_TYPE,
148070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_244_WIDTH },
148071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_245_CHECKER_TYPE,
148072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_245_WIDTH },
148073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_246_CHECKER_TYPE,
148074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_246_WIDTH },
148075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_247_CHECKER_TYPE,
148076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_247_WIDTH },
148077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_248_CHECKER_TYPE,
148078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_248_WIDTH },
148079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_249_CHECKER_TYPE,
148080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_249_WIDTH },
148081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_250_CHECKER_TYPE,
148082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_250_WIDTH },
148083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_251_CHECKER_TYPE,
148084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_251_WIDTH },
148085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_252_CHECKER_TYPE,
148086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_252_WIDTH },
148087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_253_CHECKER_TYPE,
148088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_253_WIDTH },
148089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_254_CHECKER_TYPE,
148090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_254_WIDTH },
148091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_255_CHECKER_TYPE,
148092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_GROUP_255_WIDTH },
148093 };
148094 
148100 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS] =
148101 {
148102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_0_CHECKER_TYPE,
148103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_0_WIDTH },
148104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_1_CHECKER_TYPE,
148105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_1_WIDTH },
148106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_2_CHECKER_TYPE,
148107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_2_WIDTH },
148108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_3_CHECKER_TYPE,
148109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_3_WIDTH },
148110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_4_CHECKER_TYPE,
148111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_4_WIDTH },
148112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_5_CHECKER_TYPE,
148113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_5_WIDTH },
148114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_6_CHECKER_TYPE,
148115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_6_WIDTH },
148116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_7_CHECKER_TYPE,
148117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_7_WIDTH },
148118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_8_CHECKER_TYPE,
148119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_8_WIDTH },
148120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_9_CHECKER_TYPE,
148121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_9_WIDTH },
148122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_10_CHECKER_TYPE,
148123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_10_WIDTH },
148124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_11_CHECKER_TYPE,
148125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_11_WIDTH },
148126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_12_CHECKER_TYPE,
148127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_12_WIDTH },
148128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_13_CHECKER_TYPE,
148129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_13_WIDTH },
148130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_14_CHECKER_TYPE,
148131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_14_WIDTH },
148132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_15_CHECKER_TYPE,
148133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_15_WIDTH },
148134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_16_CHECKER_TYPE,
148135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_16_WIDTH },
148136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_17_CHECKER_TYPE,
148137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_17_WIDTH },
148138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_18_CHECKER_TYPE,
148139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_18_WIDTH },
148140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_19_CHECKER_TYPE,
148141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_19_WIDTH },
148142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_20_CHECKER_TYPE,
148143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_20_WIDTH },
148144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_21_CHECKER_TYPE,
148145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_21_WIDTH },
148146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_22_CHECKER_TYPE,
148147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_22_WIDTH },
148148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_23_CHECKER_TYPE,
148149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_23_WIDTH },
148150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_24_CHECKER_TYPE,
148151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_24_WIDTH },
148152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_25_CHECKER_TYPE,
148153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_25_WIDTH },
148154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_26_CHECKER_TYPE,
148155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_26_WIDTH },
148156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_27_CHECKER_TYPE,
148157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_27_WIDTH },
148158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_28_CHECKER_TYPE,
148159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_28_WIDTH },
148160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_29_CHECKER_TYPE,
148161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_29_WIDTH },
148162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_30_CHECKER_TYPE,
148163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_30_WIDTH },
148164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_31_CHECKER_TYPE,
148165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_31_WIDTH },
148166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_32_CHECKER_TYPE,
148167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_32_WIDTH },
148168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_33_CHECKER_TYPE,
148169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_33_WIDTH },
148170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_34_CHECKER_TYPE,
148171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_34_WIDTH },
148172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_35_CHECKER_TYPE,
148173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_35_WIDTH },
148174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_36_CHECKER_TYPE,
148175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_36_WIDTH },
148176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_37_CHECKER_TYPE,
148177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_37_WIDTH },
148178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_38_CHECKER_TYPE,
148179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_38_WIDTH },
148180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_39_CHECKER_TYPE,
148181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_39_WIDTH },
148182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_40_CHECKER_TYPE,
148183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_40_WIDTH },
148184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_41_CHECKER_TYPE,
148185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_41_WIDTH },
148186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_42_CHECKER_TYPE,
148187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_42_WIDTH },
148188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_43_CHECKER_TYPE,
148189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_43_WIDTH },
148190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_44_CHECKER_TYPE,
148191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_44_WIDTH },
148192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_45_CHECKER_TYPE,
148193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_45_WIDTH },
148194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_46_CHECKER_TYPE,
148195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_46_WIDTH },
148196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_47_CHECKER_TYPE,
148197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_47_WIDTH },
148198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_48_CHECKER_TYPE,
148199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_48_WIDTH },
148200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_49_CHECKER_TYPE,
148201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_49_WIDTH },
148202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_50_CHECKER_TYPE,
148203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_50_WIDTH },
148204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_51_CHECKER_TYPE,
148205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_51_WIDTH },
148206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_52_CHECKER_TYPE,
148207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_52_WIDTH },
148208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_53_CHECKER_TYPE,
148209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_53_WIDTH },
148210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_54_CHECKER_TYPE,
148211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_54_WIDTH },
148212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_55_CHECKER_TYPE,
148213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_55_WIDTH },
148214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_56_CHECKER_TYPE,
148215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_56_WIDTH },
148216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_57_CHECKER_TYPE,
148217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_57_WIDTH },
148218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_58_CHECKER_TYPE,
148219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_58_WIDTH },
148220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_59_CHECKER_TYPE,
148221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_59_WIDTH },
148222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_60_CHECKER_TYPE,
148223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_60_WIDTH },
148224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_61_CHECKER_TYPE,
148225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_61_WIDTH },
148226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_62_CHECKER_TYPE,
148227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_62_WIDTH },
148228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_63_CHECKER_TYPE,
148229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_63_WIDTH },
148230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_64_CHECKER_TYPE,
148231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_64_WIDTH },
148232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_65_CHECKER_TYPE,
148233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_65_WIDTH },
148234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_66_CHECKER_TYPE,
148235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_66_WIDTH },
148236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_67_CHECKER_TYPE,
148237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_67_WIDTH },
148238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_68_CHECKER_TYPE,
148239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_68_WIDTH },
148240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_69_CHECKER_TYPE,
148241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_69_WIDTH },
148242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_70_CHECKER_TYPE,
148243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_70_WIDTH },
148244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_71_CHECKER_TYPE,
148245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_71_WIDTH },
148246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_72_CHECKER_TYPE,
148247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_72_WIDTH },
148248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_73_CHECKER_TYPE,
148249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_73_WIDTH },
148250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_74_CHECKER_TYPE,
148251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_74_WIDTH },
148252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_75_CHECKER_TYPE,
148253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_75_WIDTH },
148254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_76_CHECKER_TYPE,
148255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_76_WIDTH },
148256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_77_CHECKER_TYPE,
148257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_77_WIDTH },
148258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_78_CHECKER_TYPE,
148259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_78_WIDTH },
148260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_79_CHECKER_TYPE,
148261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_79_WIDTH },
148262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_80_CHECKER_TYPE,
148263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_80_WIDTH },
148264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_81_CHECKER_TYPE,
148265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_81_WIDTH },
148266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_82_CHECKER_TYPE,
148267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_82_WIDTH },
148268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_83_CHECKER_TYPE,
148269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_83_WIDTH },
148270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_84_CHECKER_TYPE,
148271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_84_WIDTH },
148272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_85_CHECKER_TYPE,
148273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_85_WIDTH },
148274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_86_CHECKER_TYPE,
148275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_86_WIDTH },
148276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_87_CHECKER_TYPE,
148277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_87_WIDTH },
148278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_88_CHECKER_TYPE,
148279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_88_WIDTH },
148280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_89_CHECKER_TYPE,
148281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_89_WIDTH },
148282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_90_CHECKER_TYPE,
148283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_90_WIDTH },
148284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_91_CHECKER_TYPE,
148285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_91_WIDTH },
148286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_92_CHECKER_TYPE,
148287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_92_WIDTH },
148288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_93_CHECKER_TYPE,
148289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_93_WIDTH },
148290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_94_CHECKER_TYPE,
148291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_94_WIDTH },
148292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_95_CHECKER_TYPE,
148293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_95_WIDTH },
148294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_96_CHECKER_TYPE,
148295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_96_WIDTH },
148296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_97_CHECKER_TYPE,
148297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_97_WIDTH },
148298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_98_CHECKER_TYPE,
148299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_98_WIDTH },
148300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_99_CHECKER_TYPE,
148301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_99_WIDTH },
148302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_100_CHECKER_TYPE,
148303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_100_WIDTH },
148304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_101_CHECKER_TYPE,
148305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_101_WIDTH },
148306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_102_CHECKER_TYPE,
148307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_102_WIDTH },
148308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_103_CHECKER_TYPE,
148309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_103_WIDTH },
148310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_104_CHECKER_TYPE,
148311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_104_WIDTH },
148312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_105_CHECKER_TYPE,
148313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_105_WIDTH },
148314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_106_CHECKER_TYPE,
148315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_106_WIDTH },
148316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_107_CHECKER_TYPE,
148317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_107_WIDTH },
148318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_108_CHECKER_TYPE,
148319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_108_WIDTH },
148320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_109_CHECKER_TYPE,
148321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_109_WIDTH },
148322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_110_CHECKER_TYPE,
148323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_110_WIDTH },
148324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_111_CHECKER_TYPE,
148325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_111_WIDTH },
148326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_112_CHECKER_TYPE,
148327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_112_WIDTH },
148328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_113_CHECKER_TYPE,
148329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_113_WIDTH },
148330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_114_CHECKER_TYPE,
148331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_114_WIDTH },
148332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_115_CHECKER_TYPE,
148333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_115_WIDTH },
148334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_116_CHECKER_TYPE,
148335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_116_WIDTH },
148336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_117_CHECKER_TYPE,
148337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_117_WIDTH },
148338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_118_CHECKER_TYPE,
148339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_118_WIDTH },
148340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_119_CHECKER_TYPE,
148341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_119_WIDTH },
148342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_120_CHECKER_TYPE,
148343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_120_WIDTH },
148344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_121_CHECKER_TYPE,
148345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_121_WIDTH },
148346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_122_CHECKER_TYPE,
148347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_122_WIDTH },
148348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_123_CHECKER_TYPE,
148349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_123_WIDTH },
148350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_124_CHECKER_TYPE,
148351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_124_WIDTH },
148352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_125_CHECKER_TYPE,
148353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_125_WIDTH },
148354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_126_CHECKER_TYPE,
148355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_126_WIDTH },
148356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_127_CHECKER_TYPE,
148357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_127_WIDTH },
148358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_128_CHECKER_TYPE,
148359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_128_WIDTH },
148360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_129_CHECKER_TYPE,
148361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_129_WIDTH },
148362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_130_CHECKER_TYPE,
148363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_130_WIDTH },
148364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_131_CHECKER_TYPE,
148365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_131_WIDTH },
148366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_132_CHECKER_TYPE,
148367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_132_WIDTH },
148368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_133_CHECKER_TYPE,
148369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_133_WIDTH },
148370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_134_CHECKER_TYPE,
148371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_134_WIDTH },
148372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_135_CHECKER_TYPE,
148373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_135_WIDTH },
148374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_136_CHECKER_TYPE,
148375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_136_WIDTH },
148376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_137_CHECKER_TYPE,
148377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_137_WIDTH },
148378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_138_CHECKER_TYPE,
148379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_138_WIDTH },
148380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_139_CHECKER_TYPE,
148381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_139_WIDTH },
148382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_140_CHECKER_TYPE,
148383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_140_WIDTH },
148384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_141_CHECKER_TYPE,
148385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_141_WIDTH },
148386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_142_CHECKER_TYPE,
148387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_142_WIDTH },
148388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_143_CHECKER_TYPE,
148389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_143_WIDTH },
148390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_144_CHECKER_TYPE,
148391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_144_WIDTH },
148392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_145_CHECKER_TYPE,
148393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_145_WIDTH },
148394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_146_CHECKER_TYPE,
148395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_146_WIDTH },
148396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_147_CHECKER_TYPE,
148397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_147_WIDTH },
148398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_148_CHECKER_TYPE,
148399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_148_WIDTH },
148400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_149_CHECKER_TYPE,
148401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_149_WIDTH },
148402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_150_CHECKER_TYPE,
148403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_150_WIDTH },
148404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_151_CHECKER_TYPE,
148405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_151_WIDTH },
148406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_152_CHECKER_TYPE,
148407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_152_WIDTH },
148408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_153_CHECKER_TYPE,
148409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_153_WIDTH },
148410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_154_CHECKER_TYPE,
148411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_154_WIDTH },
148412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_155_CHECKER_TYPE,
148413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_155_WIDTH },
148414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_156_CHECKER_TYPE,
148415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_156_WIDTH },
148416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_157_CHECKER_TYPE,
148417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_157_WIDTH },
148418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_158_CHECKER_TYPE,
148419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_158_WIDTH },
148420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_159_CHECKER_TYPE,
148421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_159_WIDTH },
148422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_160_CHECKER_TYPE,
148423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_160_WIDTH },
148424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_161_CHECKER_TYPE,
148425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_161_WIDTH },
148426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_162_CHECKER_TYPE,
148427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_162_WIDTH },
148428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_163_CHECKER_TYPE,
148429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_163_WIDTH },
148430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_164_CHECKER_TYPE,
148431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_164_WIDTH },
148432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_165_CHECKER_TYPE,
148433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_165_WIDTH },
148434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_166_CHECKER_TYPE,
148435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_166_WIDTH },
148436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_167_CHECKER_TYPE,
148437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_167_WIDTH },
148438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_168_CHECKER_TYPE,
148439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_168_WIDTH },
148440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_169_CHECKER_TYPE,
148441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_169_WIDTH },
148442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_170_CHECKER_TYPE,
148443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_170_WIDTH },
148444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_171_CHECKER_TYPE,
148445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_171_WIDTH },
148446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_172_CHECKER_TYPE,
148447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_172_WIDTH },
148448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_173_CHECKER_TYPE,
148449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_173_WIDTH },
148450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_174_CHECKER_TYPE,
148451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_174_WIDTH },
148452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_175_CHECKER_TYPE,
148453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_175_WIDTH },
148454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_176_CHECKER_TYPE,
148455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_176_WIDTH },
148456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_177_CHECKER_TYPE,
148457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_177_WIDTH },
148458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_178_CHECKER_TYPE,
148459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_178_WIDTH },
148460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_179_CHECKER_TYPE,
148461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_179_WIDTH },
148462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_180_CHECKER_TYPE,
148463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_180_WIDTH },
148464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_181_CHECKER_TYPE,
148465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_181_WIDTH },
148466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_182_CHECKER_TYPE,
148467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_182_WIDTH },
148468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_183_CHECKER_TYPE,
148469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_183_WIDTH },
148470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_184_CHECKER_TYPE,
148471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_184_WIDTH },
148472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_185_CHECKER_TYPE,
148473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_185_WIDTH },
148474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_186_CHECKER_TYPE,
148475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_186_WIDTH },
148476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_187_CHECKER_TYPE,
148477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_187_WIDTH },
148478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_188_CHECKER_TYPE,
148479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_188_WIDTH },
148480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_189_CHECKER_TYPE,
148481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_189_WIDTH },
148482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_190_CHECKER_TYPE,
148483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_190_WIDTH },
148484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_191_CHECKER_TYPE,
148485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_191_WIDTH },
148486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_192_CHECKER_TYPE,
148487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_192_WIDTH },
148488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_193_CHECKER_TYPE,
148489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_193_WIDTH },
148490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_194_CHECKER_TYPE,
148491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_194_WIDTH },
148492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_195_CHECKER_TYPE,
148493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_195_WIDTH },
148494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_196_CHECKER_TYPE,
148495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_196_WIDTH },
148496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_197_CHECKER_TYPE,
148497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_197_WIDTH },
148498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_198_CHECKER_TYPE,
148499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_198_WIDTH },
148500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_199_CHECKER_TYPE,
148501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_199_WIDTH },
148502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_200_CHECKER_TYPE,
148503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_200_WIDTH },
148504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_201_CHECKER_TYPE,
148505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_201_WIDTH },
148506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_202_CHECKER_TYPE,
148507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_202_WIDTH },
148508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_203_CHECKER_TYPE,
148509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_203_WIDTH },
148510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_204_CHECKER_TYPE,
148511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_204_WIDTH },
148512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_205_CHECKER_TYPE,
148513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_205_WIDTH },
148514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_206_CHECKER_TYPE,
148515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_206_WIDTH },
148516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_207_CHECKER_TYPE,
148517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_207_WIDTH },
148518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_208_CHECKER_TYPE,
148519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_208_WIDTH },
148520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_209_CHECKER_TYPE,
148521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_209_WIDTH },
148522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_210_CHECKER_TYPE,
148523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_210_WIDTH },
148524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_211_CHECKER_TYPE,
148525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_211_WIDTH },
148526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_212_CHECKER_TYPE,
148527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_212_WIDTH },
148528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_213_CHECKER_TYPE,
148529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_213_WIDTH },
148530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_214_CHECKER_TYPE,
148531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_214_WIDTH },
148532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_215_CHECKER_TYPE,
148533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_215_WIDTH },
148534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_216_CHECKER_TYPE,
148535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_216_WIDTH },
148536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_217_CHECKER_TYPE,
148537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_217_WIDTH },
148538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_218_CHECKER_TYPE,
148539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_218_WIDTH },
148540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_219_CHECKER_TYPE,
148541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_219_WIDTH },
148542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_220_CHECKER_TYPE,
148543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_220_WIDTH },
148544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_221_CHECKER_TYPE,
148545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_221_WIDTH },
148546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_222_CHECKER_TYPE,
148547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_222_WIDTH },
148548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_223_CHECKER_TYPE,
148549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_223_WIDTH },
148550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_224_CHECKER_TYPE,
148551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_224_WIDTH },
148552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_225_CHECKER_TYPE,
148553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_225_WIDTH },
148554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_226_CHECKER_TYPE,
148555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_226_WIDTH },
148556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_227_CHECKER_TYPE,
148557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_227_WIDTH },
148558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_228_CHECKER_TYPE,
148559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_228_WIDTH },
148560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_229_CHECKER_TYPE,
148561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_229_WIDTH },
148562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_230_CHECKER_TYPE,
148563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_230_WIDTH },
148564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_231_CHECKER_TYPE,
148565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_231_WIDTH },
148566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_232_CHECKER_TYPE,
148567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_232_WIDTH },
148568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_233_CHECKER_TYPE,
148569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_233_WIDTH },
148570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_234_CHECKER_TYPE,
148571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_234_WIDTH },
148572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_235_CHECKER_TYPE,
148573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_235_WIDTH },
148574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_236_CHECKER_TYPE,
148575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_236_WIDTH },
148576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_237_CHECKER_TYPE,
148577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_237_WIDTH },
148578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_238_CHECKER_TYPE,
148579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_238_WIDTH },
148580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_239_CHECKER_TYPE,
148581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_239_WIDTH },
148582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_240_CHECKER_TYPE,
148583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_240_WIDTH },
148584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_241_CHECKER_TYPE,
148585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_241_WIDTH },
148586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_242_CHECKER_TYPE,
148587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_242_WIDTH },
148588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_243_CHECKER_TYPE,
148589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_243_WIDTH },
148590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_244_CHECKER_TYPE,
148591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_244_WIDTH },
148592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_245_CHECKER_TYPE,
148593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_245_WIDTH },
148594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_246_CHECKER_TYPE,
148595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_246_WIDTH },
148596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_247_CHECKER_TYPE,
148597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_247_WIDTH },
148598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_248_CHECKER_TYPE,
148599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_248_WIDTH },
148600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_249_CHECKER_TYPE,
148601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_249_WIDTH },
148602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_250_CHECKER_TYPE,
148603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_250_WIDTH },
148604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_251_CHECKER_TYPE,
148605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_251_WIDTH },
148606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_252_CHECKER_TYPE,
148607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_252_WIDTH },
148608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_253_CHECKER_TYPE,
148609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_253_WIDTH },
148610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_254_CHECKER_TYPE,
148611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_254_WIDTH },
148612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_255_CHECKER_TYPE,
148613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_GROUP_255_WIDTH },
148614 };
148615 
148621 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS] =
148622 {
148623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_0_CHECKER_TYPE,
148624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_0_WIDTH },
148625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_1_CHECKER_TYPE,
148626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_1_WIDTH },
148627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_2_CHECKER_TYPE,
148628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_2_WIDTH },
148629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_3_CHECKER_TYPE,
148630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_3_WIDTH },
148631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_4_CHECKER_TYPE,
148632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_4_WIDTH },
148633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_5_CHECKER_TYPE,
148634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_5_WIDTH },
148635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_6_CHECKER_TYPE,
148636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_6_WIDTH },
148637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_7_CHECKER_TYPE,
148638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_7_WIDTH },
148639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_8_CHECKER_TYPE,
148640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_8_WIDTH },
148641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_9_CHECKER_TYPE,
148642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_9_WIDTH },
148643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_10_CHECKER_TYPE,
148644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_10_WIDTH },
148645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_11_CHECKER_TYPE,
148646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_11_WIDTH },
148647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_12_CHECKER_TYPE,
148648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_12_WIDTH },
148649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_13_CHECKER_TYPE,
148650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_13_WIDTH },
148651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_14_CHECKER_TYPE,
148652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_14_WIDTH },
148653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_15_CHECKER_TYPE,
148654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_15_WIDTH },
148655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_16_CHECKER_TYPE,
148656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_16_WIDTH },
148657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_17_CHECKER_TYPE,
148658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_17_WIDTH },
148659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_18_CHECKER_TYPE,
148660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_18_WIDTH },
148661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_19_CHECKER_TYPE,
148662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_19_WIDTH },
148663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_20_CHECKER_TYPE,
148664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_20_WIDTH },
148665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_21_CHECKER_TYPE,
148666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_21_WIDTH },
148667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_22_CHECKER_TYPE,
148668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_22_WIDTH },
148669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_23_CHECKER_TYPE,
148670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_23_WIDTH },
148671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_24_CHECKER_TYPE,
148672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_24_WIDTH },
148673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_25_CHECKER_TYPE,
148674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_25_WIDTH },
148675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_26_CHECKER_TYPE,
148676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_26_WIDTH },
148677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_27_CHECKER_TYPE,
148678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_27_WIDTH },
148679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_28_CHECKER_TYPE,
148680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_28_WIDTH },
148681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_29_CHECKER_TYPE,
148682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_29_WIDTH },
148683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_30_CHECKER_TYPE,
148684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_30_WIDTH },
148685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_31_CHECKER_TYPE,
148686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_31_WIDTH },
148687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_32_CHECKER_TYPE,
148688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_32_WIDTH },
148689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_33_CHECKER_TYPE,
148690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_33_WIDTH },
148691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_34_CHECKER_TYPE,
148692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_34_WIDTH },
148693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_35_CHECKER_TYPE,
148694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_35_WIDTH },
148695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_36_CHECKER_TYPE,
148696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_36_WIDTH },
148697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_37_CHECKER_TYPE,
148698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_37_WIDTH },
148699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_38_CHECKER_TYPE,
148700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_38_WIDTH },
148701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_39_CHECKER_TYPE,
148702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_39_WIDTH },
148703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_40_CHECKER_TYPE,
148704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_40_WIDTH },
148705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_41_CHECKER_TYPE,
148706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_41_WIDTH },
148707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_42_CHECKER_TYPE,
148708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_42_WIDTH },
148709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_43_CHECKER_TYPE,
148710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_43_WIDTH },
148711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_44_CHECKER_TYPE,
148712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_44_WIDTH },
148713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_45_CHECKER_TYPE,
148714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_45_WIDTH },
148715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_46_CHECKER_TYPE,
148716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_46_WIDTH },
148717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_47_CHECKER_TYPE,
148718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_47_WIDTH },
148719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_48_CHECKER_TYPE,
148720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_48_WIDTH },
148721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_49_CHECKER_TYPE,
148722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_49_WIDTH },
148723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_50_CHECKER_TYPE,
148724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_50_WIDTH },
148725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_51_CHECKER_TYPE,
148726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_51_WIDTH },
148727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_52_CHECKER_TYPE,
148728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_52_WIDTH },
148729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_53_CHECKER_TYPE,
148730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_53_WIDTH },
148731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_54_CHECKER_TYPE,
148732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_54_WIDTH },
148733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_55_CHECKER_TYPE,
148734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_55_WIDTH },
148735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_56_CHECKER_TYPE,
148736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_56_WIDTH },
148737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_57_CHECKER_TYPE,
148738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_57_WIDTH },
148739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_58_CHECKER_TYPE,
148740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_58_WIDTH },
148741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_59_CHECKER_TYPE,
148742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_59_WIDTH },
148743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_60_CHECKER_TYPE,
148744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_60_WIDTH },
148745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_61_CHECKER_TYPE,
148746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_61_WIDTH },
148747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_62_CHECKER_TYPE,
148748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_62_WIDTH },
148749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_63_CHECKER_TYPE,
148750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_63_WIDTH },
148751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_64_CHECKER_TYPE,
148752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_64_WIDTH },
148753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_65_CHECKER_TYPE,
148754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_65_WIDTH },
148755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_66_CHECKER_TYPE,
148756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_66_WIDTH },
148757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_67_CHECKER_TYPE,
148758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_67_WIDTH },
148759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_68_CHECKER_TYPE,
148760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_68_WIDTH },
148761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_69_CHECKER_TYPE,
148762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_69_WIDTH },
148763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_70_CHECKER_TYPE,
148764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_70_WIDTH },
148765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_71_CHECKER_TYPE,
148766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_71_WIDTH },
148767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_72_CHECKER_TYPE,
148768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_72_WIDTH },
148769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_73_CHECKER_TYPE,
148770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_73_WIDTH },
148771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_74_CHECKER_TYPE,
148772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_74_WIDTH },
148773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_75_CHECKER_TYPE,
148774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_75_WIDTH },
148775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_76_CHECKER_TYPE,
148776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_76_WIDTH },
148777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_77_CHECKER_TYPE,
148778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_77_WIDTH },
148779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_78_CHECKER_TYPE,
148780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_78_WIDTH },
148781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_79_CHECKER_TYPE,
148782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_79_WIDTH },
148783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_80_CHECKER_TYPE,
148784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_80_WIDTH },
148785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_81_CHECKER_TYPE,
148786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_81_WIDTH },
148787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_82_CHECKER_TYPE,
148788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_82_WIDTH },
148789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_83_CHECKER_TYPE,
148790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_83_WIDTH },
148791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_84_CHECKER_TYPE,
148792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_84_WIDTH },
148793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_85_CHECKER_TYPE,
148794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_85_WIDTH },
148795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_86_CHECKER_TYPE,
148796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_86_WIDTH },
148797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_87_CHECKER_TYPE,
148798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_87_WIDTH },
148799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_88_CHECKER_TYPE,
148800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_88_WIDTH },
148801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_89_CHECKER_TYPE,
148802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_89_WIDTH },
148803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_90_CHECKER_TYPE,
148804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_90_WIDTH },
148805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_91_CHECKER_TYPE,
148806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_91_WIDTH },
148807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_92_CHECKER_TYPE,
148808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_92_WIDTH },
148809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_93_CHECKER_TYPE,
148810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_93_WIDTH },
148811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_94_CHECKER_TYPE,
148812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_94_WIDTH },
148813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_95_CHECKER_TYPE,
148814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_95_WIDTH },
148815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_96_CHECKER_TYPE,
148816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_96_WIDTH },
148817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_97_CHECKER_TYPE,
148818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_97_WIDTH },
148819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_98_CHECKER_TYPE,
148820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_98_WIDTH },
148821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_99_CHECKER_TYPE,
148822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_99_WIDTH },
148823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_100_CHECKER_TYPE,
148824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_100_WIDTH },
148825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_101_CHECKER_TYPE,
148826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_101_WIDTH },
148827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_102_CHECKER_TYPE,
148828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_102_WIDTH },
148829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_103_CHECKER_TYPE,
148830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_103_WIDTH },
148831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_104_CHECKER_TYPE,
148832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_104_WIDTH },
148833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_105_CHECKER_TYPE,
148834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_105_WIDTH },
148835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_106_CHECKER_TYPE,
148836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_106_WIDTH },
148837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_107_CHECKER_TYPE,
148838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_107_WIDTH },
148839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_108_CHECKER_TYPE,
148840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_108_WIDTH },
148841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_109_CHECKER_TYPE,
148842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_109_WIDTH },
148843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_110_CHECKER_TYPE,
148844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_110_WIDTH },
148845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_111_CHECKER_TYPE,
148846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_111_WIDTH },
148847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_112_CHECKER_TYPE,
148848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_112_WIDTH },
148849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_113_CHECKER_TYPE,
148850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_113_WIDTH },
148851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_114_CHECKER_TYPE,
148852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_114_WIDTH },
148853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_115_CHECKER_TYPE,
148854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_115_WIDTH },
148855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_116_CHECKER_TYPE,
148856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_116_WIDTH },
148857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_117_CHECKER_TYPE,
148858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_117_WIDTH },
148859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_118_CHECKER_TYPE,
148860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_118_WIDTH },
148861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_119_CHECKER_TYPE,
148862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_119_WIDTH },
148863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_120_CHECKER_TYPE,
148864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_120_WIDTH },
148865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_121_CHECKER_TYPE,
148866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_121_WIDTH },
148867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_122_CHECKER_TYPE,
148868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_122_WIDTH },
148869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_123_CHECKER_TYPE,
148870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_123_WIDTH },
148871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_124_CHECKER_TYPE,
148872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_124_WIDTH },
148873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_125_CHECKER_TYPE,
148874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_125_WIDTH },
148875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_126_CHECKER_TYPE,
148876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_126_WIDTH },
148877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_127_CHECKER_TYPE,
148878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_127_WIDTH },
148879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_128_CHECKER_TYPE,
148880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_128_WIDTH },
148881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_129_CHECKER_TYPE,
148882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_129_WIDTH },
148883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_130_CHECKER_TYPE,
148884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_130_WIDTH },
148885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_131_CHECKER_TYPE,
148886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_131_WIDTH },
148887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_132_CHECKER_TYPE,
148888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_132_WIDTH },
148889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_133_CHECKER_TYPE,
148890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_133_WIDTH },
148891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_134_CHECKER_TYPE,
148892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_134_WIDTH },
148893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_135_CHECKER_TYPE,
148894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_135_WIDTH },
148895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_136_CHECKER_TYPE,
148896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_136_WIDTH },
148897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_137_CHECKER_TYPE,
148898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_137_WIDTH },
148899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_138_CHECKER_TYPE,
148900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_138_WIDTH },
148901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_139_CHECKER_TYPE,
148902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_139_WIDTH },
148903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_140_CHECKER_TYPE,
148904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_140_WIDTH },
148905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_141_CHECKER_TYPE,
148906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_141_WIDTH },
148907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_142_CHECKER_TYPE,
148908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_142_WIDTH },
148909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_143_CHECKER_TYPE,
148910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_143_WIDTH },
148911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_144_CHECKER_TYPE,
148912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_144_WIDTH },
148913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_145_CHECKER_TYPE,
148914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_145_WIDTH },
148915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_146_CHECKER_TYPE,
148916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_146_WIDTH },
148917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_147_CHECKER_TYPE,
148918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_147_WIDTH },
148919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_148_CHECKER_TYPE,
148920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_148_WIDTH },
148921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_149_CHECKER_TYPE,
148922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_149_WIDTH },
148923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_150_CHECKER_TYPE,
148924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_150_WIDTH },
148925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_151_CHECKER_TYPE,
148926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_151_WIDTH },
148927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_152_CHECKER_TYPE,
148928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_152_WIDTH },
148929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_153_CHECKER_TYPE,
148930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_153_WIDTH },
148931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_154_CHECKER_TYPE,
148932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_154_WIDTH },
148933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_155_CHECKER_TYPE,
148934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_155_WIDTH },
148935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_156_CHECKER_TYPE,
148936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_156_WIDTH },
148937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_157_CHECKER_TYPE,
148938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_157_WIDTH },
148939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_158_CHECKER_TYPE,
148940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_158_WIDTH },
148941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_159_CHECKER_TYPE,
148942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_159_WIDTH },
148943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_160_CHECKER_TYPE,
148944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_160_WIDTH },
148945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_161_CHECKER_TYPE,
148946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_161_WIDTH },
148947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_162_CHECKER_TYPE,
148948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_162_WIDTH },
148949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_163_CHECKER_TYPE,
148950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_163_WIDTH },
148951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_164_CHECKER_TYPE,
148952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_164_WIDTH },
148953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_165_CHECKER_TYPE,
148954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_165_WIDTH },
148955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_166_CHECKER_TYPE,
148956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_166_WIDTH },
148957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_167_CHECKER_TYPE,
148958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_167_WIDTH },
148959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_168_CHECKER_TYPE,
148960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_168_WIDTH },
148961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_169_CHECKER_TYPE,
148962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_169_WIDTH },
148963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_170_CHECKER_TYPE,
148964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_170_WIDTH },
148965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_171_CHECKER_TYPE,
148966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_171_WIDTH },
148967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_172_CHECKER_TYPE,
148968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_172_WIDTH },
148969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_173_CHECKER_TYPE,
148970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_173_WIDTH },
148971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_174_CHECKER_TYPE,
148972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_174_WIDTH },
148973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_175_CHECKER_TYPE,
148974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_175_WIDTH },
148975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_176_CHECKER_TYPE,
148976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_176_WIDTH },
148977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_177_CHECKER_TYPE,
148978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_177_WIDTH },
148979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_178_CHECKER_TYPE,
148980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_178_WIDTH },
148981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_179_CHECKER_TYPE,
148982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_179_WIDTH },
148983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_180_CHECKER_TYPE,
148984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_180_WIDTH },
148985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_181_CHECKER_TYPE,
148986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_181_WIDTH },
148987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_182_CHECKER_TYPE,
148988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_182_WIDTH },
148989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_183_CHECKER_TYPE,
148990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_183_WIDTH },
148991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_184_CHECKER_TYPE,
148992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_184_WIDTH },
148993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_185_CHECKER_TYPE,
148994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_185_WIDTH },
148995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_186_CHECKER_TYPE,
148996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_186_WIDTH },
148997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_187_CHECKER_TYPE,
148998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_187_WIDTH },
148999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_188_CHECKER_TYPE,
149000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_188_WIDTH },
149001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_189_CHECKER_TYPE,
149002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_189_WIDTH },
149003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_190_CHECKER_TYPE,
149004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_190_WIDTH },
149005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_191_CHECKER_TYPE,
149006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_191_WIDTH },
149007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_192_CHECKER_TYPE,
149008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_192_WIDTH },
149009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_193_CHECKER_TYPE,
149010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_193_WIDTH },
149011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_194_CHECKER_TYPE,
149012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_194_WIDTH },
149013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_195_CHECKER_TYPE,
149014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_195_WIDTH },
149015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_196_CHECKER_TYPE,
149016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_196_WIDTH },
149017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_197_CHECKER_TYPE,
149018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_197_WIDTH },
149019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_198_CHECKER_TYPE,
149020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_198_WIDTH },
149021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_199_CHECKER_TYPE,
149022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_199_WIDTH },
149023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_200_CHECKER_TYPE,
149024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_200_WIDTH },
149025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_201_CHECKER_TYPE,
149026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_201_WIDTH },
149027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_202_CHECKER_TYPE,
149028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_202_WIDTH },
149029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_203_CHECKER_TYPE,
149030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_203_WIDTH },
149031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_204_CHECKER_TYPE,
149032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_204_WIDTH },
149033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_205_CHECKER_TYPE,
149034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_205_WIDTH },
149035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_206_CHECKER_TYPE,
149036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_206_WIDTH },
149037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_207_CHECKER_TYPE,
149038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_207_WIDTH },
149039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_208_CHECKER_TYPE,
149040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_208_WIDTH },
149041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_209_CHECKER_TYPE,
149042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_209_WIDTH },
149043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_210_CHECKER_TYPE,
149044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_210_WIDTH },
149045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_211_CHECKER_TYPE,
149046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_211_WIDTH },
149047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_212_CHECKER_TYPE,
149048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_212_WIDTH },
149049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_213_CHECKER_TYPE,
149050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_213_WIDTH },
149051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_214_CHECKER_TYPE,
149052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_214_WIDTH },
149053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_215_CHECKER_TYPE,
149054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_215_WIDTH },
149055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_216_CHECKER_TYPE,
149056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_216_WIDTH },
149057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_217_CHECKER_TYPE,
149058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_217_WIDTH },
149059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_218_CHECKER_TYPE,
149060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_218_WIDTH },
149061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_219_CHECKER_TYPE,
149062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_219_WIDTH },
149063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_220_CHECKER_TYPE,
149064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_220_WIDTH },
149065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_221_CHECKER_TYPE,
149066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_221_WIDTH },
149067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_222_CHECKER_TYPE,
149068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_222_WIDTH },
149069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_223_CHECKER_TYPE,
149070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_223_WIDTH },
149071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_224_CHECKER_TYPE,
149072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_224_WIDTH },
149073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_225_CHECKER_TYPE,
149074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_225_WIDTH },
149075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_226_CHECKER_TYPE,
149076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_226_WIDTH },
149077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_227_CHECKER_TYPE,
149078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_227_WIDTH },
149079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_228_CHECKER_TYPE,
149080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_228_WIDTH },
149081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_229_CHECKER_TYPE,
149082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_229_WIDTH },
149083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_230_CHECKER_TYPE,
149084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_230_WIDTH },
149085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_231_CHECKER_TYPE,
149086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_231_WIDTH },
149087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_232_CHECKER_TYPE,
149088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_232_WIDTH },
149089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_233_CHECKER_TYPE,
149090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_233_WIDTH },
149091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_234_CHECKER_TYPE,
149092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_234_WIDTH },
149093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_235_CHECKER_TYPE,
149094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_235_WIDTH },
149095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_236_CHECKER_TYPE,
149096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_236_WIDTH },
149097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_237_CHECKER_TYPE,
149098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_237_WIDTH },
149099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_238_CHECKER_TYPE,
149100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_238_WIDTH },
149101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_239_CHECKER_TYPE,
149102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_239_WIDTH },
149103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_240_CHECKER_TYPE,
149104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_240_WIDTH },
149105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_241_CHECKER_TYPE,
149106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_241_WIDTH },
149107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_242_CHECKER_TYPE,
149108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_242_WIDTH },
149109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_243_CHECKER_TYPE,
149110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_243_WIDTH },
149111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_244_CHECKER_TYPE,
149112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_244_WIDTH },
149113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_245_CHECKER_TYPE,
149114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_245_WIDTH },
149115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_246_CHECKER_TYPE,
149116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_246_WIDTH },
149117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_247_CHECKER_TYPE,
149118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_247_WIDTH },
149119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_248_CHECKER_TYPE,
149120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_248_WIDTH },
149121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_249_CHECKER_TYPE,
149122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_249_WIDTH },
149123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_250_CHECKER_TYPE,
149124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_250_WIDTH },
149125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_251_CHECKER_TYPE,
149126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_251_WIDTH },
149127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_252_CHECKER_TYPE,
149128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_252_WIDTH },
149129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_253_CHECKER_TYPE,
149130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_253_WIDTH },
149131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_254_CHECKER_TYPE,
149132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_254_WIDTH },
149133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_255_CHECKER_TYPE,
149134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_GROUP_255_WIDTH },
149135 };
149136 
149142 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS] =
149143 {
149144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_0_CHECKER_TYPE,
149145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_0_WIDTH },
149146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_1_CHECKER_TYPE,
149147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_1_WIDTH },
149148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_2_CHECKER_TYPE,
149149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_2_WIDTH },
149150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_3_CHECKER_TYPE,
149151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_3_WIDTH },
149152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_4_CHECKER_TYPE,
149153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_4_WIDTH },
149154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_5_CHECKER_TYPE,
149155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_5_WIDTH },
149156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_6_CHECKER_TYPE,
149157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_6_WIDTH },
149158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_7_CHECKER_TYPE,
149159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_7_WIDTH },
149160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_8_CHECKER_TYPE,
149161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_8_WIDTH },
149162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_9_CHECKER_TYPE,
149163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_9_WIDTH },
149164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_10_CHECKER_TYPE,
149165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_10_WIDTH },
149166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_11_CHECKER_TYPE,
149167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_11_WIDTH },
149168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_12_CHECKER_TYPE,
149169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_12_WIDTH },
149170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_13_CHECKER_TYPE,
149171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_13_WIDTH },
149172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_14_CHECKER_TYPE,
149173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_14_WIDTH },
149174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_15_CHECKER_TYPE,
149175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_15_WIDTH },
149176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_16_CHECKER_TYPE,
149177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_16_WIDTH },
149178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_17_CHECKER_TYPE,
149179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_17_WIDTH },
149180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_18_CHECKER_TYPE,
149181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_18_WIDTH },
149182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_19_CHECKER_TYPE,
149183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_19_WIDTH },
149184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_20_CHECKER_TYPE,
149185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_20_WIDTH },
149186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_21_CHECKER_TYPE,
149187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_21_WIDTH },
149188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_22_CHECKER_TYPE,
149189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_22_WIDTH },
149190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_23_CHECKER_TYPE,
149191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_23_WIDTH },
149192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_24_CHECKER_TYPE,
149193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_24_WIDTH },
149194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_25_CHECKER_TYPE,
149195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_25_WIDTH },
149196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_26_CHECKER_TYPE,
149197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_26_WIDTH },
149198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_27_CHECKER_TYPE,
149199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_27_WIDTH },
149200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_28_CHECKER_TYPE,
149201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_28_WIDTH },
149202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_29_CHECKER_TYPE,
149203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_29_WIDTH },
149204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_30_CHECKER_TYPE,
149205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_30_WIDTH },
149206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_31_CHECKER_TYPE,
149207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_31_WIDTH },
149208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_32_CHECKER_TYPE,
149209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_32_WIDTH },
149210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_33_CHECKER_TYPE,
149211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_33_WIDTH },
149212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_34_CHECKER_TYPE,
149213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_34_WIDTH },
149214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_35_CHECKER_TYPE,
149215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_35_WIDTH },
149216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_36_CHECKER_TYPE,
149217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_36_WIDTH },
149218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_37_CHECKER_TYPE,
149219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_37_WIDTH },
149220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_38_CHECKER_TYPE,
149221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_38_WIDTH },
149222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_39_CHECKER_TYPE,
149223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_39_WIDTH },
149224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_40_CHECKER_TYPE,
149225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_40_WIDTH },
149226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_41_CHECKER_TYPE,
149227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_41_WIDTH },
149228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_42_CHECKER_TYPE,
149229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_42_WIDTH },
149230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_43_CHECKER_TYPE,
149231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_43_WIDTH },
149232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_44_CHECKER_TYPE,
149233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_44_WIDTH },
149234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_45_CHECKER_TYPE,
149235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_45_WIDTH },
149236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_46_CHECKER_TYPE,
149237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_46_WIDTH },
149238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_47_CHECKER_TYPE,
149239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_47_WIDTH },
149240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_48_CHECKER_TYPE,
149241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_48_WIDTH },
149242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_49_CHECKER_TYPE,
149243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_49_WIDTH },
149244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_50_CHECKER_TYPE,
149245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_50_WIDTH },
149246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_51_CHECKER_TYPE,
149247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_51_WIDTH },
149248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_52_CHECKER_TYPE,
149249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_52_WIDTH },
149250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_53_CHECKER_TYPE,
149251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_53_WIDTH },
149252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_54_CHECKER_TYPE,
149253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_54_WIDTH },
149254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_55_CHECKER_TYPE,
149255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_55_WIDTH },
149256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_56_CHECKER_TYPE,
149257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_56_WIDTH },
149258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_57_CHECKER_TYPE,
149259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_57_WIDTH },
149260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_58_CHECKER_TYPE,
149261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_58_WIDTH },
149262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_59_CHECKER_TYPE,
149263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_59_WIDTH },
149264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_60_CHECKER_TYPE,
149265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_60_WIDTH },
149266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_61_CHECKER_TYPE,
149267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_61_WIDTH },
149268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_62_CHECKER_TYPE,
149269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_62_WIDTH },
149270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_63_CHECKER_TYPE,
149271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_63_WIDTH },
149272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_64_CHECKER_TYPE,
149273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_64_WIDTH },
149274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_65_CHECKER_TYPE,
149275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_65_WIDTH },
149276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_66_CHECKER_TYPE,
149277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_66_WIDTH },
149278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_67_CHECKER_TYPE,
149279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_67_WIDTH },
149280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_68_CHECKER_TYPE,
149281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_68_WIDTH },
149282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_69_CHECKER_TYPE,
149283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_69_WIDTH },
149284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_70_CHECKER_TYPE,
149285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_70_WIDTH },
149286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_71_CHECKER_TYPE,
149287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_71_WIDTH },
149288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_72_CHECKER_TYPE,
149289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_72_WIDTH },
149290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_73_CHECKER_TYPE,
149291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_73_WIDTH },
149292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_74_CHECKER_TYPE,
149293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_74_WIDTH },
149294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_75_CHECKER_TYPE,
149295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_75_WIDTH },
149296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_76_CHECKER_TYPE,
149297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_76_WIDTH },
149298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_77_CHECKER_TYPE,
149299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_77_WIDTH },
149300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_78_CHECKER_TYPE,
149301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_78_WIDTH },
149302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_79_CHECKER_TYPE,
149303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_79_WIDTH },
149304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_80_CHECKER_TYPE,
149305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_80_WIDTH },
149306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_81_CHECKER_TYPE,
149307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_81_WIDTH },
149308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_82_CHECKER_TYPE,
149309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_82_WIDTH },
149310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_83_CHECKER_TYPE,
149311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_83_WIDTH },
149312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_84_CHECKER_TYPE,
149313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_84_WIDTH },
149314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_85_CHECKER_TYPE,
149315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_85_WIDTH },
149316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_86_CHECKER_TYPE,
149317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_86_WIDTH },
149318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_87_CHECKER_TYPE,
149319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_87_WIDTH },
149320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_88_CHECKER_TYPE,
149321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_88_WIDTH },
149322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_89_CHECKER_TYPE,
149323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_89_WIDTH },
149324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_90_CHECKER_TYPE,
149325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_90_WIDTH },
149326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_91_CHECKER_TYPE,
149327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_91_WIDTH },
149328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_92_CHECKER_TYPE,
149329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_92_WIDTH },
149330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_93_CHECKER_TYPE,
149331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_93_WIDTH },
149332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_94_CHECKER_TYPE,
149333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_94_WIDTH },
149334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_95_CHECKER_TYPE,
149335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_95_WIDTH },
149336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_96_CHECKER_TYPE,
149337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_96_WIDTH },
149338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_97_CHECKER_TYPE,
149339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_97_WIDTH },
149340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_98_CHECKER_TYPE,
149341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_98_WIDTH },
149342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_99_CHECKER_TYPE,
149343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_99_WIDTH },
149344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_100_CHECKER_TYPE,
149345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_100_WIDTH },
149346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_101_CHECKER_TYPE,
149347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_101_WIDTH },
149348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_102_CHECKER_TYPE,
149349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_102_WIDTH },
149350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_103_CHECKER_TYPE,
149351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_103_WIDTH },
149352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_104_CHECKER_TYPE,
149353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_104_WIDTH },
149354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_105_CHECKER_TYPE,
149355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_105_WIDTH },
149356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_106_CHECKER_TYPE,
149357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_106_WIDTH },
149358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_107_CHECKER_TYPE,
149359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_107_WIDTH },
149360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_108_CHECKER_TYPE,
149361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_108_WIDTH },
149362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_109_CHECKER_TYPE,
149363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_109_WIDTH },
149364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_110_CHECKER_TYPE,
149365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_110_WIDTH },
149366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_111_CHECKER_TYPE,
149367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_111_WIDTH },
149368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_112_CHECKER_TYPE,
149369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_112_WIDTH },
149370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_113_CHECKER_TYPE,
149371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_113_WIDTH },
149372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_114_CHECKER_TYPE,
149373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_114_WIDTH },
149374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_115_CHECKER_TYPE,
149375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_115_WIDTH },
149376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_116_CHECKER_TYPE,
149377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_116_WIDTH },
149378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_117_CHECKER_TYPE,
149379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_117_WIDTH },
149380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_118_CHECKER_TYPE,
149381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_118_WIDTH },
149382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_119_CHECKER_TYPE,
149383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_119_WIDTH },
149384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_120_CHECKER_TYPE,
149385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_120_WIDTH },
149386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_121_CHECKER_TYPE,
149387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_121_WIDTH },
149388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_122_CHECKER_TYPE,
149389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_122_WIDTH },
149390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_123_CHECKER_TYPE,
149391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_123_WIDTH },
149392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_124_CHECKER_TYPE,
149393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_124_WIDTH },
149394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_125_CHECKER_TYPE,
149395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_125_WIDTH },
149396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_126_CHECKER_TYPE,
149397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_126_WIDTH },
149398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_127_CHECKER_TYPE,
149399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_127_WIDTH },
149400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_128_CHECKER_TYPE,
149401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_128_WIDTH },
149402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_129_CHECKER_TYPE,
149403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_129_WIDTH },
149404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_130_CHECKER_TYPE,
149405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_130_WIDTH },
149406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_131_CHECKER_TYPE,
149407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_131_WIDTH },
149408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_132_CHECKER_TYPE,
149409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_132_WIDTH },
149410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_133_CHECKER_TYPE,
149411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_133_WIDTH },
149412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_134_CHECKER_TYPE,
149413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_134_WIDTH },
149414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_135_CHECKER_TYPE,
149415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_135_WIDTH },
149416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_136_CHECKER_TYPE,
149417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_136_WIDTH },
149418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_137_CHECKER_TYPE,
149419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_137_WIDTH },
149420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_138_CHECKER_TYPE,
149421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_138_WIDTH },
149422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_139_CHECKER_TYPE,
149423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_139_WIDTH },
149424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_140_CHECKER_TYPE,
149425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_140_WIDTH },
149426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_141_CHECKER_TYPE,
149427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_141_WIDTH },
149428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_142_CHECKER_TYPE,
149429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_142_WIDTH },
149430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_143_CHECKER_TYPE,
149431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_143_WIDTH },
149432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_144_CHECKER_TYPE,
149433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_144_WIDTH },
149434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_145_CHECKER_TYPE,
149435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_145_WIDTH },
149436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_146_CHECKER_TYPE,
149437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_146_WIDTH },
149438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_147_CHECKER_TYPE,
149439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_147_WIDTH },
149440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_148_CHECKER_TYPE,
149441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_148_WIDTH },
149442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_149_CHECKER_TYPE,
149443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_149_WIDTH },
149444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_150_CHECKER_TYPE,
149445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_150_WIDTH },
149446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_151_CHECKER_TYPE,
149447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_151_WIDTH },
149448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_152_CHECKER_TYPE,
149449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_152_WIDTH },
149450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_153_CHECKER_TYPE,
149451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_153_WIDTH },
149452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_154_CHECKER_TYPE,
149453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_154_WIDTH },
149454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_155_CHECKER_TYPE,
149455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_155_WIDTH },
149456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_156_CHECKER_TYPE,
149457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_156_WIDTH },
149458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_157_CHECKER_TYPE,
149459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_157_WIDTH },
149460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_158_CHECKER_TYPE,
149461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_158_WIDTH },
149462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_159_CHECKER_TYPE,
149463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_159_WIDTH },
149464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_160_CHECKER_TYPE,
149465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_160_WIDTH },
149466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_161_CHECKER_TYPE,
149467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_161_WIDTH },
149468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_162_CHECKER_TYPE,
149469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_162_WIDTH },
149470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_163_CHECKER_TYPE,
149471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_163_WIDTH },
149472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_164_CHECKER_TYPE,
149473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_164_WIDTH },
149474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_165_CHECKER_TYPE,
149475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_165_WIDTH },
149476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_166_CHECKER_TYPE,
149477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_166_WIDTH },
149478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_167_CHECKER_TYPE,
149479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_167_WIDTH },
149480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_168_CHECKER_TYPE,
149481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_168_WIDTH },
149482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_169_CHECKER_TYPE,
149483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_169_WIDTH },
149484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_170_CHECKER_TYPE,
149485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_170_WIDTH },
149486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_171_CHECKER_TYPE,
149487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_171_WIDTH },
149488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_172_CHECKER_TYPE,
149489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_172_WIDTH },
149490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_173_CHECKER_TYPE,
149491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_173_WIDTH },
149492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_174_CHECKER_TYPE,
149493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_174_WIDTH },
149494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_175_CHECKER_TYPE,
149495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_175_WIDTH },
149496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_176_CHECKER_TYPE,
149497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_176_WIDTH },
149498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_177_CHECKER_TYPE,
149499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_177_WIDTH },
149500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_178_CHECKER_TYPE,
149501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_178_WIDTH },
149502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_179_CHECKER_TYPE,
149503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_179_WIDTH },
149504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_180_CHECKER_TYPE,
149505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_180_WIDTH },
149506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_181_CHECKER_TYPE,
149507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_181_WIDTH },
149508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_182_CHECKER_TYPE,
149509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_182_WIDTH },
149510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_183_CHECKER_TYPE,
149511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_183_WIDTH },
149512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_184_CHECKER_TYPE,
149513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_184_WIDTH },
149514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_185_CHECKER_TYPE,
149515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_185_WIDTH },
149516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_186_CHECKER_TYPE,
149517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_186_WIDTH },
149518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_187_CHECKER_TYPE,
149519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_187_WIDTH },
149520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_188_CHECKER_TYPE,
149521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_188_WIDTH },
149522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_189_CHECKER_TYPE,
149523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_189_WIDTH },
149524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_190_CHECKER_TYPE,
149525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_190_WIDTH },
149526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_191_CHECKER_TYPE,
149527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_191_WIDTH },
149528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_192_CHECKER_TYPE,
149529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_192_WIDTH },
149530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_193_CHECKER_TYPE,
149531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_193_WIDTH },
149532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_194_CHECKER_TYPE,
149533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_194_WIDTH },
149534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_195_CHECKER_TYPE,
149535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_195_WIDTH },
149536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_196_CHECKER_TYPE,
149537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_196_WIDTH },
149538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_197_CHECKER_TYPE,
149539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_197_WIDTH },
149540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_198_CHECKER_TYPE,
149541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_198_WIDTH },
149542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_199_CHECKER_TYPE,
149543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_199_WIDTH },
149544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_200_CHECKER_TYPE,
149545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_200_WIDTH },
149546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_201_CHECKER_TYPE,
149547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_201_WIDTH },
149548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_202_CHECKER_TYPE,
149549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_202_WIDTH },
149550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_203_CHECKER_TYPE,
149551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_203_WIDTH },
149552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_204_CHECKER_TYPE,
149553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_204_WIDTH },
149554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_205_CHECKER_TYPE,
149555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_205_WIDTH },
149556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_206_CHECKER_TYPE,
149557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_206_WIDTH },
149558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_207_CHECKER_TYPE,
149559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_207_WIDTH },
149560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_208_CHECKER_TYPE,
149561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_208_WIDTH },
149562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_209_CHECKER_TYPE,
149563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_209_WIDTH },
149564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_210_CHECKER_TYPE,
149565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_210_WIDTH },
149566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_211_CHECKER_TYPE,
149567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_211_WIDTH },
149568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_212_CHECKER_TYPE,
149569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_212_WIDTH },
149570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_213_CHECKER_TYPE,
149571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_213_WIDTH },
149572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_214_CHECKER_TYPE,
149573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_214_WIDTH },
149574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_215_CHECKER_TYPE,
149575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_215_WIDTH },
149576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_216_CHECKER_TYPE,
149577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_216_WIDTH },
149578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_217_CHECKER_TYPE,
149579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_217_WIDTH },
149580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_218_CHECKER_TYPE,
149581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_218_WIDTH },
149582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_219_CHECKER_TYPE,
149583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_219_WIDTH },
149584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_220_CHECKER_TYPE,
149585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_220_WIDTH },
149586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_221_CHECKER_TYPE,
149587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_221_WIDTH },
149588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_222_CHECKER_TYPE,
149589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_222_WIDTH },
149590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_223_CHECKER_TYPE,
149591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_223_WIDTH },
149592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_224_CHECKER_TYPE,
149593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_224_WIDTH },
149594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_225_CHECKER_TYPE,
149595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_225_WIDTH },
149596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_226_CHECKER_TYPE,
149597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_226_WIDTH },
149598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_227_CHECKER_TYPE,
149599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_227_WIDTH },
149600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_228_CHECKER_TYPE,
149601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_228_WIDTH },
149602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_229_CHECKER_TYPE,
149603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_229_WIDTH },
149604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_230_CHECKER_TYPE,
149605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_230_WIDTH },
149606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_231_CHECKER_TYPE,
149607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_231_WIDTH },
149608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_232_CHECKER_TYPE,
149609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_232_WIDTH },
149610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_233_CHECKER_TYPE,
149611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_233_WIDTH },
149612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_234_CHECKER_TYPE,
149613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_234_WIDTH },
149614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_235_CHECKER_TYPE,
149615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_235_WIDTH },
149616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_236_CHECKER_TYPE,
149617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_236_WIDTH },
149618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_237_CHECKER_TYPE,
149619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_237_WIDTH },
149620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_238_CHECKER_TYPE,
149621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_238_WIDTH },
149622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_239_CHECKER_TYPE,
149623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_239_WIDTH },
149624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_240_CHECKER_TYPE,
149625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_240_WIDTH },
149626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_241_CHECKER_TYPE,
149627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_241_WIDTH },
149628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_242_CHECKER_TYPE,
149629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_242_WIDTH },
149630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_243_CHECKER_TYPE,
149631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_243_WIDTH },
149632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_244_CHECKER_TYPE,
149633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_244_WIDTH },
149634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_245_CHECKER_TYPE,
149635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_245_WIDTH },
149636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_246_CHECKER_TYPE,
149637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_246_WIDTH },
149638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_247_CHECKER_TYPE,
149639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_247_WIDTH },
149640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_248_CHECKER_TYPE,
149641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_248_WIDTH },
149642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_249_CHECKER_TYPE,
149643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_249_WIDTH },
149644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_250_CHECKER_TYPE,
149645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_250_WIDTH },
149646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_251_CHECKER_TYPE,
149647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_251_WIDTH },
149648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_252_CHECKER_TYPE,
149649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_252_WIDTH },
149650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_253_CHECKER_TYPE,
149651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_253_WIDTH },
149652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_254_CHECKER_TYPE,
149653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_254_WIDTH },
149654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_255_CHECKER_TYPE,
149655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_GROUP_255_WIDTH },
149656 };
149657 
149663 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS] =
149664 {
149665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_0_CHECKER_TYPE,
149666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_0_WIDTH },
149667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_1_CHECKER_TYPE,
149668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_1_WIDTH },
149669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_2_CHECKER_TYPE,
149670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_2_WIDTH },
149671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_3_CHECKER_TYPE,
149672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_3_WIDTH },
149673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_4_CHECKER_TYPE,
149674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_4_WIDTH },
149675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_5_CHECKER_TYPE,
149676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_5_WIDTH },
149677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_6_CHECKER_TYPE,
149678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_6_WIDTH },
149679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_7_CHECKER_TYPE,
149680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_7_WIDTH },
149681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_8_CHECKER_TYPE,
149682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_8_WIDTH },
149683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_9_CHECKER_TYPE,
149684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_9_WIDTH },
149685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_10_CHECKER_TYPE,
149686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_10_WIDTH },
149687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_11_CHECKER_TYPE,
149688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_11_WIDTH },
149689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_12_CHECKER_TYPE,
149690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_12_WIDTH },
149691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_13_CHECKER_TYPE,
149692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_13_WIDTH },
149693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_14_CHECKER_TYPE,
149694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_14_WIDTH },
149695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_15_CHECKER_TYPE,
149696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_15_WIDTH },
149697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_16_CHECKER_TYPE,
149698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_16_WIDTH },
149699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_17_CHECKER_TYPE,
149700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_17_WIDTH },
149701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_18_CHECKER_TYPE,
149702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_18_WIDTH },
149703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_19_CHECKER_TYPE,
149704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_19_WIDTH },
149705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_20_CHECKER_TYPE,
149706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_20_WIDTH },
149707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_21_CHECKER_TYPE,
149708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_21_WIDTH },
149709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_22_CHECKER_TYPE,
149710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_22_WIDTH },
149711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_23_CHECKER_TYPE,
149712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_23_WIDTH },
149713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_24_CHECKER_TYPE,
149714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_24_WIDTH },
149715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_25_CHECKER_TYPE,
149716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_25_WIDTH },
149717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_26_CHECKER_TYPE,
149718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_26_WIDTH },
149719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_27_CHECKER_TYPE,
149720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_27_WIDTH },
149721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_28_CHECKER_TYPE,
149722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_28_WIDTH },
149723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_29_CHECKER_TYPE,
149724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_29_WIDTH },
149725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_30_CHECKER_TYPE,
149726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_30_WIDTH },
149727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_31_CHECKER_TYPE,
149728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_31_WIDTH },
149729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_32_CHECKER_TYPE,
149730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_32_WIDTH },
149731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_33_CHECKER_TYPE,
149732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_33_WIDTH },
149733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_34_CHECKER_TYPE,
149734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_34_WIDTH },
149735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_35_CHECKER_TYPE,
149736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_35_WIDTH },
149737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_36_CHECKER_TYPE,
149738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_36_WIDTH },
149739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_37_CHECKER_TYPE,
149740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_37_WIDTH },
149741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_38_CHECKER_TYPE,
149742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_38_WIDTH },
149743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_39_CHECKER_TYPE,
149744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_39_WIDTH },
149745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_40_CHECKER_TYPE,
149746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_40_WIDTH },
149747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_41_CHECKER_TYPE,
149748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_41_WIDTH },
149749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_42_CHECKER_TYPE,
149750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_42_WIDTH },
149751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_43_CHECKER_TYPE,
149752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_43_WIDTH },
149753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_44_CHECKER_TYPE,
149754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_44_WIDTH },
149755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_45_CHECKER_TYPE,
149756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_45_WIDTH },
149757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_46_CHECKER_TYPE,
149758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_46_WIDTH },
149759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_47_CHECKER_TYPE,
149760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_47_WIDTH },
149761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_48_CHECKER_TYPE,
149762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_48_WIDTH },
149763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_49_CHECKER_TYPE,
149764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_49_WIDTH },
149765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_50_CHECKER_TYPE,
149766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_50_WIDTH },
149767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_51_CHECKER_TYPE,
149768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_51_WIDTH },
149769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_52_CHECKER_TYPE,
149770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_52_WIDTH },
149771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_53_CHECKER_TYPE,
149772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_53_WIDTH },
149773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_54_CHECKER_TYPE,
149774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_54_WIDTH },
149775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_55_CHECKER_TYPE,
149776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_55_WIDTH },
149777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_56_CHECKER_TYPE,
149778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_56_WIDTH },
149779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_57_CHECKER_TYPE,
149780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_57_WIDTH },
149781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_58_CHECKER_TYPE,
149782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_58_WIDTH },
149783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_59_CHECKER_TYPE,
149784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_59_WIDTH },
149785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_60_CHECKER_TYPE,
149786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_60_WIDTH },
149787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_61_CHECKER_TYPE,
149788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_61_WIDTH },
149789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_62_CHECKER_TYPE,
149790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_62_WIDTH },
149791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_63_CHECKER_TYPE,
149792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_63_WIDTH },
149793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_64_CHECKER_TYPE,
149794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_64_WIDTH },
149795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_65_CHECKER_TYPE,
149796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_65_WIDTH },
149797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_66_CHECKER_TYPE,
149798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_66_WIDTH },
149799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_67_CHECKER_TYPE,
149800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_67_WIDTH },
149801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_68_CHECKER_TYPE,
149802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_68_WIDTH },
149803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_69_CHECKER_TYPE,
149804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_69_WIDTH },
149805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_70_CHECKER_TYPE,
149806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_70_WIDTH },
149807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_71_CHECKER_TYPE,
149808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_71_WIDTH },
149809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_72_CHECKER_TYPE,
149810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_72_WIDTH },
149811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_73_CHECKER_TYPE,
149812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_73_WIDTH },
149813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_74_CHECKER_TYPE,
149814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_74_WIDTH },
149815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_75_CHECKER_TYPE,
149816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_75_WIDTH },
149817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_76_CHECKER_TYPE,
149818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_76_WIDTH },
149819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_77_CHECKER_TYPE,
149820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_77_WIDTH },
149821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_78_CHECKER_TYPE,
149822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_78_WIDTH },
149823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_79_CHECKER_TYPE,
149824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_79_WIDTH },
149825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_80_CHECKER_TYPE,
149826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_80_WIDTH },
149827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_81_CHECKER_TYPE,
149828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_81_WIDTH },
149829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_82_CHECKER_TYPE,
149830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_82_WIDTH },
149831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_83_CHECKER_TYPE,
149832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_83_WIDTH },
149833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_84_CHECKER_TYPE,
149834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_84_WIDTH },
149835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_85_CHECKER_TYPE,
149836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_85_WIDTH },
149837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_86_CHECKER_TYPE,
149838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_86_WIDTH },
149839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_87_CHECKER_TYPE,
149840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_87_WIDTH },
149841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_88_CHECKER_TYPE,
149842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_88_WIDTH },
149843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_89_CHECKER_TYPE,
149844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_89_WIDTH },
149845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_90_CHECKER_TYPE,
149846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_90_WIDTH },
149847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_91_CHECKER_TYPE,
149848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_91_WIDTH },
149849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_92_CHECKER_TYPE,
149850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_92_WIDTH },
149851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_93_CHECKER_TYPE,
149852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_93_WIDTH },
149853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_94_CHECKER_TYPE,
149854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_94_WIDTH },
149855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_95_CHECKER_TYPE,
149856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_95_WIDTH },
149857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_96_CHECKER_TYPE,
149858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_96_WIDTH },
149859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_97_CHECKER_TYPE,
149860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_97_WIDTH },
149861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_98_CHECKER_TYPE,
149862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_98_WIDTH },
149863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_99_CHECKER_TYPE,
149864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_99_WIDTH },
149865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_100_CHECKER_TYPE,
149866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_100_WIDTH },
149867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_101_CHECKER_TYPE,
149868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_101_WIDTH },
149869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_102_CHECKER_TYPE,
149870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_102_WIDTH },
149871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_103_CHECKER_TYPE,
149872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_103_WIDTH },
149873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_104_CHECKER_TYPE,
149874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_104_WIDTH },
149875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_105_CHECKER_TYPE,
149876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_105_WIDTH },
149877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_106_CHECKER_TYPE,
149878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_106_WIDTH },
149879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_107_CHECKER_TYPE,
149880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_107_WIDTH },
149881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_108_CHECKER_TYPE,
149882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_108_WIDTH },
149883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_109_CHECKER_TYPE,
149884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_109_WIDTH },
149885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_110_CHECKER_TYPE,
149886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_110_WIDTH },
149887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_111_CHECKER_TYPE,
149888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_111_WIDTH },
149889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_112_CHECKER_TYPE,
149890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_112_WIDTH },
149891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_113_CHECKER_TYPE,
149892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_113_WIDTH },
149893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_114_CHECKER_TYPE,
149894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_114_WIDTH },
149895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_115_CHECKER_TYPE,
149896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_115_WIDTH },
149897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_116_CHECKER_TYPE,
149898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_116_WIDTH },
149899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_117_CHECKER_TYPE,
149900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_117_WIDTH },
149901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_118_CHECKER_TYPE,
149902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_118_WIDTH },
149903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_119_CHECKER_TYPE,
149904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_119_WIDTH },
149905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_120_CHECKER_TYPE,
149906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_120_WIDTH },
149907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_121_CHECKER_TYPE,
149908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_121_WIDTH },
149909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_122_CHECKER_TYPE,
149910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_122_WIDTH },
149911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_123_CHECKER_TYPE,
149912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_123_WIDTH },
149913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_124_CHECKER_TYPE,
149914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_124_WIDTH },
149915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_125_CHECKER_TYPE,
149916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_125_WIDTH },
149917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_126_CHECKER_TYPE,
149918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_126_WIDTH },
149919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_127_CHECKER_TYPE,
149920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_127_WIDTH },
149921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_128_CHECKER_TYPE,
149922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_128_WIDTH },
149923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_129_CHECKER_TYPE,
149924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_129_WIDTH },
149925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_130_CHECKER_TYPE,
149926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_130_WIDTH },
149927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_131_CHECKER_TYPE,
149928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_131_WIDTH },
149929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_132_CHECKER_TYPE,
149930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_132_WIDTH },
149931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_133_CHECKER_TYPE,
149932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_133_WIDTH },
149933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_134_CHECKER_TYPE,
149934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_134_WIDTH },
149935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_135_CHECKER_TYPE,
149936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_135_WIDTH },
149937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_136_CHECKER_TYPE,
149938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_136_WIDTH },
149939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_137_CHECKER_TYPE,
149940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_137_WIDTH },
149941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_138_CHECKER_TYPE,
149942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_138_WIDTH },
149943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_139_CHECKER_TYPE,
149944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_139_WIDTH },
149945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_140_CHECKER_TYPE,
149946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_140_WIDTH },
149947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_141_CHECKER_TYPE,
149948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_141_WIDTH },
149949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_142_CHECKER_TYPE,
149950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_142_WIDTH },
149951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_143_CHECKER_TYPE,
149952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_143_WIDTH },
149953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_144_CHECKER_TYPE,
149954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_144_WIDTH },
149955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_145_CHECKER_TYPE,
149956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_145_WIDTH },
149957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_146_CHECKER_TYPE,
149958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_146_WIDTH },
149959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_147_CHECKER_TYPE,
149960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_147_WIDTH },
149961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_148_CHECKER_TYPE,
149962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_148_WIDTH },
149963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_149_CHECKER_TYPE,
149964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_149_WIDTH },
149965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_150_CHECKER_TYPE,
149966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_150_WIDTH },
149967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_151_CHECKER_TYPE,
149968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_151_WIDTH },
149969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_152_CHECKER_TYPE,
149970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_152_WIDTH },
149971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_153_CHECKER_TYPE,
149972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_153_WIDTH },
149973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_154_CHECKER_TYPE,
149974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_154_WIDTH },
149975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_155_CHECKER_TYPE,
149976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_155_WIDTH },
149977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_156_CHECKER_TYPE,
149978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_156_WIDTH },
149979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_157_CHECKER_TYPE,
149980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_157_WIDTH },
149981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_158_CHECKER_TYPE,
149982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_158_WIDTH },
149983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_159_CHECKER_TYPE,
149984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_159_WIDTH },
149985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_160_CHECKER_TYPE,
149986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_160_WIDTH },
149987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_161_CHECKER_TYPE,
149988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_161_WIDTH },
149989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_162_CHECKER_TYPE,
149990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_162_WIDTH },
149991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_163_CHECKER_TYPE,
149992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_163_WIDTH },
149993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_164_CHECKER_TYPE,
149994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_164_WIDTH },
149995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_165_CHECKER_TYPE,
149996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_165_WIDTH },
149997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_166_CHECKER_TYPE,
149998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_166_WIDTH },
149999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_167_CHECKER_TYPE,
150000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_167_WIDTH },
150001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_168_CHECKER_TYPE,
150002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_168_WIDTH },
150003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_169_CHECKER_TYPE,
150004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_169_WIDTH },
150005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_170_CHECKER_TYPE,
150006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_170_WIDTH },
150007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_171_CHECKER_TYPE,
150008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_171_WIDTH },
150009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_172_CHECKER_TYPE,
150010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_172_WIDTH },
150011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_173_CHECKER_TYPE,
150012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_173_WIDTH },
150013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_174_CHECKER_TYPE,
150014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_174_WIDTH },
150015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_175_CHECKER_TYPE,
150016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_175_WIDTH },
150017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_176_CHECKER_TYPE,
150018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_176_WIDTH },
150019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_177_CHECKER_TYPE,
150020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_177_WIDTH },
150021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_178_CHECKER_TYPE,
150022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_178_WIDTH },
150023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_179_CHECKER_TYPE,
150024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_179_WIDTH },
150025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_180_CHECKER_TYPE,
150026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_180_WIDTH },
150027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_181_CHECKER_TYPE,
150028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_181_WIDTH },
150029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_182_CHECKER_TYPE,
150030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_182_WIDTH },
150031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_183_CHECKER_TYPE,
150032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_183_WIDTH },
150033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_184_CHECKER_TYPE,
150034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_184_WIDTH },
150035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_185_CHECKER_TYPE,
150036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_185_WIDTH },
150037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_186_CHECKER_TYPE,
150038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_186_WIDTH },
150039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_187_CHECKER_TYPE,
150040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_187_WIDTH },
150041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_188_CHECKER_TYPE,
150042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_188_WIDTH },
150043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_189_CHECKER_TYPE,
150044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_189_WIDTH },
150045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_190_CHECKER_TYPE,
150046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_190_WIDTH },
150047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_191_CHECKER_TYPE,
150048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_191_WIDTH },
150049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_192_CHECKER_TYPE,
150050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_192_WIDTH },
150051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_193_CHECKER_TYPE,
150052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_193_WIDTH },
150053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_194_CHECKER_TYPE,
150054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_194_WIDTH },
150055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_195_CHECKER_TYPE,
150056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_195_WIDTH },
150057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_196_CHECKER_TYPE,
150058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_196_WIDTH },
150059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_197_CHECKER_TYPE,
150060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_197_WIDTH },
150061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_198_CHECKER_TYPE,
150062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_198_WIDTH },
150063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_199_CHECKER_TYPE,
150064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_199_WIDTH },
150065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_200_CHECKER_TYPE,
150066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_200_WIDTH },
150067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_201_CHECKER_TYPE,
150068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_201_WIDTH },
150069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_202_CHECKER_TYPE,
150070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_202_WIDTH },
150071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_203_CHECKER_TYPE,
150072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_203_WIDTH },
150073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_204_CHECKER_TYPE,
150074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_204_WIDTH },
150075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_205_CHECKER_TYPE,
150076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_205_WIDTH },
150077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_206_CHECKER_TYPE,
150078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_206_WIDTH },
150079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_207_CHECKER_TYPE,
150080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_207_WIDTH },
150081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_208_CHECKER_TYPE,
150082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_208_WIDTH },
150083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_209_CHECKER_TYPE,
150084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_209_WIDTH },
150085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_210_CHECKER_TYPE,
150086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_210_WIDTH },
150087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_211_CHECKER_TYPE,
150088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_211_WIDTH },
150089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_212_CHECKER_TYPE,
150090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_212_WIDTH },
150091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_213_CHECKER_TYPE,
150092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_213_WIDTH },
150093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_214_CHECKER_TYPE,
150094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_214_WIDTH },
150095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_215_CHECKER_TYPE,
150096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_215_WIDTH },
150097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_216_CHECKER_TYPE,
150098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_216_WIDTH },
150099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_217_CHECKER_TYPE,
150100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_217_WIDTH },
150101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_218_CHECKER_TYPE,
150102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_218_WIDTH },
150103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_219_CHECKER_TYPE,
150104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_219_WIDTH },
150105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_220_CHECKER_TYPE,
150106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_220_WIDTH },
150107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_221_CHECKER_TYPE,
150108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_221_WIDTH },
150109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_222_CHECKER_TYPE,
150110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_222_WIDTH },
150111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_223_CHECKER_TYPE,
150112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_223_WIDTH },
150113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_224_CHECKER_TYPE,
150114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_224_WIDTH },
150115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_225_CHECKER_TYPE,
150116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_225_WIDTH },
150117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_226_CHECKER_TYPE,
150118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_226_WIDTH },
150119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_227_CHECKER_TYPE,
150120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_227_WIDTH },
150121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_228_CHECKER_TYPE,
150122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_228_WIDTH },
150123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_229_CHECKER_TYPE,
150124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_229_WIDTH },
150125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_230_CHECKER_TYPE,
150126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_230_WIDTH },
150127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_231_CHECKER_TYPE,
150128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_231_WIDTH },
150129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_232_CHECKER_TYPE,
150130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_232_WIDTH },
150131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_233_CHECKER_TYPE,
150132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_233_WIDTH },
150133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_234_CHECKER_TYPE,
150134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_234_WIDTH },
150135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_235_CHECKER_TYPE,
150136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_235_WIDTH },
150137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_236_CHECKER_TYPE,
150138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_236_WIDTH },
150139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_237_CHECKER_TYPE,
150140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_237_WIDTH },
150141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_238_CHECKER_TYPE,
150142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_238_WIDTH },
150143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_239_CHECKER_TYPE,
150144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_239_WIDTH },
150145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_240_CHECKER_TYPE,
150146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_240_WIDTH },
150147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_241_CHECKER_TYPE,
150148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_241_WIDTH },
150149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_242_CHECKER_TYPE,
150150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_242_WIDTH },
150151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_243_CHECKER_TYPE,
150152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_243_WIDTH },
150153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_244_CHECKER_TYPE,
150154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_244_WIDTH },
150155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_245_CHECKER_TYPE,
150156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_245_WIDTH },
150157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_246_CHECKER_TYPE,
150158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_246_WIDTH },
150159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_247_CHECKER_TYPE,
150160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_247_WIDTH },
150161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_248_CHECKER_TYPE,
150162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_248_WIDTH },
150163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_249_CHECKER_TYPE,
150164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_249_WIDTH },
150165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_250_CHECKER_TYPE,
150166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_250_WIDTH },
150167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_251_CHECKER_TYPE,
150168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_251_WIDTH },
150169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_252_CHECKER_TYPE,
150170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_252_WIDTH },
150171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_253_CHECKER_TYPE,
150172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_253_WIDTH },
150173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_254_CHECKER_TYPE,
150174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_254_WIDTH },
150175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_255_CHECKER_TYPE,
150176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_GROUP_255_WIDTH },
150177 };
150178 
150184 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS] =
150185 {
150186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_0_CHECKER_TYPE,
150187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_0_WIDTH },
150188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_1_CHECKER_TYPE,
150189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_1_WIDTH },
150190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_2_CHECKER_TYPE,
150191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_2_WIDTH },
150192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_3_CHECKER_TYPE,
150193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_3_WIDTH },
150194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_4_CHECKER_TYPE,
150195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_4_WIDTH },
150196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_5_CHECKER_TYPE,
150197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_5_WIDTH },
150198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_6_CHECKER_TYPE,
150199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_6_WIDTH },
150200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_7_CHECKER_TYPE,
150201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_7_WIDTH },
150202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_8_CHECKER_TYPE,
150203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_8_WIDTH },
150204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_9_CHECKER_TYPE,
150205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_9_WIDTH },
150206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_10_CHECKER_TYPE,
150207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_10_WIDTH },
150208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_11_CHECKER_TYPE,
150209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_11_WIDTH },
150210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_12_CHECKER_TYPE,
150211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_12_WIDTH },
150212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_13_CHECKER_TYPE,
150213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_13_WIDTH },
150214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_14_CHECKER_TYPE,
150215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_14_WIDTH },
150216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_15_CHECKER_TYPE,
150217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_15_WIDTH },
150218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_16_CHECKER_TYPE,
150219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_16_WIDTH },
150220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_17_CHECKER_TYPE,
150221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_17_WIDTH },
150222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_18_CHECKER_TYPE,
150223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_18_WIDTH },
150224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_19_CHECKER_TYPE,
150225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_19_WIDTH },
150226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_20_CHECKER_TYPE,
150227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_20_WIDTH },
150228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_21_CHECKER_TYPE,
150229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_21_WIDTH },
150230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_22_CHECKER_TYPE,
150231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_22_WIDTH },
150232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_23_CHECKER_TYPE,
150233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_23_WIDTH },
150234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_24_CHECKER_TYPE,
150235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_24_WIDTH },
150236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_25_CHECKER_TYPE,
150237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_25_WIDTH },
150238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_26_CHECKER_TYPE,
150239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_26_WIDTH },
150240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_27_CHECKER_TYPE,
150241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_27_WIDTH },
150242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_28_CHECKER_TYPE,
150243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_28_WIDTH },
150244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_29_CHECKER_TYPE,
150245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_29_WIDTH },
150246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_30_CHECKER_TYPE,
150247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_30_WIDTH },
150248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_31_CHECKER_TYPE,
150249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_31_WIDTH },
150250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_32_CHECKER_TYPE,
150251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_32_WIDTH },
150252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_33_CHECKER_TYPE,
150253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_33_WIDTH },
150254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_34_CHECKER_TYPE,
150255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_34_WIDTH },
150256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_35_CHECKER_TYPE,
150257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_35_WIDTH },
150258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_36_CHECKER_TYPE,
150259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_36_WIDTH },
150260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_37_CHECKER_TYPE,
150261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_37_WIDTH },
150262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_38_CHECKER_TYPE,
150263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_38_WIDTH },
150264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_39_CHECKER_TYPE,
150265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_39_WIDTH },
150266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_40_CHECKER_TYPE,
150267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_40_WIDTH },
150268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_41_CHECKER_TYPE,
150269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_41_WIDTH },
150270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_42_CHECKER_TYPE,
150271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_42_WIDTH },
150272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_43_CHECKER_TYPE,
150273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_43_WIDTH },
150274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_44_CHECKER_TYPE,
150275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_44_WIDTH },
150276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_45_CHECKER_TYPE,
150277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_45_WIDTH },
150278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_46_CHECKER_TYPE,
150279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_46_WIDTH },
150280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_47_CHECKER_TYPE,
150281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_47_WIDTH },
150282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_48_CHECKER_TYPE,
150283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_48_WIDTH },
150284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_49_CHECKER_TYPE,
150285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_49_WIDTH },
150286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_50_CHECKER_TYPE,
150287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_50_WIDTH },
150288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_51_CHECKER_TYPE,
150289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_51_WIDTH },
150290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_52_CHECKER_TYPE,
150291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_52_WIDTH },
150292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_53_CHECKER_TYPE,
150293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_53_WIDTH },
150294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_54_CHECKER_TYPE,
150295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_54_WIDTH },
150296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_55_CHECKER_TYPE,
150297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_55_WIDTH },
150298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_56_CHECKER_TYPE,
150299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_56_WIDTH },
150300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_57_CHECKER_TYPE,
150301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_57_WIDTH },
150302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_58_CHECKER_TYPE,
150303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_58_WIDTH },
150304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_59_CHECKER_TYPE,
150305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_59_WIDTH },
150306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_60_CHECKER_TYPE,
150307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_60_WIDTH },
150308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_61_CHECKER_TYPE,
150309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_61_WIDTH },
150310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_62_CHECKER_TYPE,
150311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_62_WIDTH },
150312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_63_CHECKER_TYPE,
150313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_63_WIDTH },
150314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_64_CHECKER_TYPE,
150315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_64_WIDTH },
150316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_65_CHECKER_TYPE,
150317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_65_WIDTH },
150318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_66_CHECKER_TYPE,
150319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_66_WIDTH },
150320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_67_CHECKER_TYPE,
150321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_67_WIDTH },
150322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_68_CHECKER_TYPE,
150323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_68_WIDTH },
150324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_69_CHECKER_TYPE,
150325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_69_WIDTH },
150326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_70_CHECKER_TYPE,
150327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_70_WIDTH },
150328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_71_CHECKER_TYPE,
150329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_71_WIDTH },
150330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_72_CHECKER_TYPE,
150331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_72_WIDTH },
150332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_73_CHECKER_TYPE,
150333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_73_WIDTH },
150334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_74_CHECKER_TYPE,
150335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_74_WIDTH },
150336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_75_CHECKER_TYPE,
150337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_75_WIDTH },
150338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_76_CHECKER_TYPE,
150339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_76_WIDTH },
150340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_77_CHECKER_TYPE,
150341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_77_WIDTH },
150342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_78_CHECKER_TYPE,
150343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_78_WIDTH },
150344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_79_CHECKER_TYPE,
150345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_79_WIDTH },
150346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_80_CHECKER_TYPE,
150347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_80_WIDTH },
150348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_81_CHECKER_TYPE,
150349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_81_WIDTH },
150350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_82_CHECKER_TYPE,
150351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_82_WIDTH },
150352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_83_CHECKER_TYPE,
150353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_83_WIDTH },
150354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_84_CHECKER_TYPE,
150355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_84_WIDTH },
150356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_85_CHECKER_TYPE,
150357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_85_WIDTH },
150358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_86_CHECKER_TYPE,
150359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_86_WIDTH },
150360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_87_CHECKER_TYPE,
150361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_87_WIDTH },
150362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_88_CHECKER_TYPE,
150363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_88_WIDTH },
150364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_89_CHECKER_TYPE,
150365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_89_WIDTH },
150366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_90_CHECKER_TYPE,
150367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_90_WIDTH },
150368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_91_CHECKER_TYPE,
150369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_91_WIDTH },
150370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_92_CHECKER_TYPE,
150371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_92_WIDTH },
150372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_93_CHECKER_TYPE,
150373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_93_WIDTH },
150374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_94_CHECKER_TYPE,
150375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_94_WIDTH },
150376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_95_CHECKER_TYPE,
150377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_95_WIDTH },
150378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_96_CHECKER_TYPE,
150379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_96_WIDTH },
150380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_97_CHECKER_TYPE,
150381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_97_WIDTH },
150382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_98_CHECKER_TYPE,
150383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_98_WIDTH },
150384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_99_CHECKER_TYPE,
150385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_99_WIDTH },
150386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_100_CHECKER_TYPE,
150387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_100_WIDTH },
150388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_101_CHECKER_TYPE,
150389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_101_WIDTH },
150390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_102_CHECKER_TYPE,
150391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_102_WIDTH },
150392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_103_CHECKER_TYPE,
150393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_103_WIDTH },
150394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_104_CHECKER_TYPE,
150395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_104_WIDTH },
150396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_105_CHECKER_TYPE,
150397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_105_WIDTH },
150398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_106_CHECKER_TYPE,
150399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_106_WIDTH },
150400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_107_CHECKER_TYPE,
150401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_107_WIDTH },
150402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_108_CHECKER_TYPE,
150403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_108_WIDTH },
150404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_109_CHECKER_TYPE,
150405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_109_WIDTH },
150406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_110_CHECKER_TYPE,
150407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_110_WIDTH },
150408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_111_CHECKER_TYPE,
150409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_111_WIDTH },
150410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_112_CHECKER_TYPE,
150411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_112_WIDTH },
150412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_113_CHECKER_TYPE,
150413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_113_WIDTH },
150414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_114_CHECKER_TYPE,
150415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_114_WIDTH },
150416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_115_CHECKER_TYPE,
150417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_115_WIDTH },
150418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_116_CHECKER_TYPE,
150419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_116_WIDTH },
150420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_117_CHECKER_TYPE,
150421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_117_WIDTH },
150422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_118_CHECKER_TYPE,
150423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_118_WIDTH },
150424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_119_CHECKER_TYPE,
150425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_119_WIDTH },
150426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_120_CHECKER_TYPE,
150427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_120_WIDTH },
150428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_121_CHECKER_TYPE,
150429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_121_WIDTH },
150430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_122_CHECKER_TYPE,
150431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_122_WIDTH },
150432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_123_CHECKER_TYPE,
150433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_123_WIDTH },
150434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_124_CHECKER_TYPE,
150435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_124_WIDTH },
150436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_125_CHECKER_TYPE,
150437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_125_WIDTH },
150438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_126_CHECKER_TYPE,
150439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_126_WIDTH },
150440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_127_CHECKER_TYPE,
150441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_127_WIDTH },
150442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_128_CHECKER_TYPE,
150443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_128_WIDTH },
150444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_129_CHECKER_TYPE,
150445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_129_WIDTH },
150446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_130_CHECKER_TYPE,
150447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_130_WIDTH },
150448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_131_CHECKER_TYPE,
150449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_131_WIDTH },
150450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_132_CHECKER_TYPE,
150451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_132_WIDTH },
150452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_133_CHECKER_TYPE,
150453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_133_WIDTH },
150454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_134_CHECKER_TYPE,
150455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_134_WIDTH },
150456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_135_CHECKER_TYPE,
150457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_135_WIDTH },
150458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_136_CHECKER_TYPE,
150459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_136_WIDTH },
150460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_137_CHECKER_TYPE,
150461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_137_WIDTH },
150462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_138_CHECKER_TYPE,
150463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_138_WIDTH },
150464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_139_CHECKER_TYPE,
150465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_139_WIDTH },
150466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_140_CHECKER_TYPE,
150467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_140_WIDTH },
150468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_141_CHECKER_TYPE,
150469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_141_WIDTH },
150470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_142_CHECKER_TYPE,
150471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_142_WIDTH },
150472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_143_CHECKER_TYPE,
150473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_143_WIDTH },
150474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_144_CHECKER_TYPE,
150475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_144_WIDTH },
150476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_145_CHECKER_TYPE,
150477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_145_WIDTH },
150478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_146_CHECKER_TYPE,
150479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_146_WIDTH },
150480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_147_CHECKER_TYPE,
150481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_147_WIDTH },
150482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_148_CHECKER_TYPE,
150483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_148_WIDTH },
150484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_149_CHECKER_TYPE,
150485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_149_WIDTH },
150486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_150_CHECKER_TYPE,
150487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_150_WIDTH },
150488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_151_CHECKER_TYPE,
150489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_151_WIDTH },
150490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_152_CHECKER_TYPE,
150491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_152_WIDTH },
150492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_153_CHECKER_TYPE,
150493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_153_WIDTH },
150494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_154_CHECKER_TYPE,
150495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_154_WIDTH },
150496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_155_CHECKER_TYPE,
150497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_155_WIDTH },
150498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_156_CHECKER_TYPE,
150499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_156_WIDTH },
150500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_157_CHECKER_TYPE,
150501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_157_WIDTH },
150502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_158_CHECKER_TYPE,
150503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_158_WIDTH },
150504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_159_CHECKER_TYPE,
150505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_159_WIDTH },
150506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_160_CHECKER_TYPE,
150507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_160_WIDTH },
150508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_161_CHECKER_TYPE,
150509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_161_WIDTH },
150510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_162_CHECKER_TYPE,
150511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_162_WIDTH },
150512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_163_CHECKER_TYPE,
150513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_163_WIDTH },
150514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_164_CHECKER_TYPE,
150515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_164_WIDTH },
150516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_165_CHECKER_TYPE,
150517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_165_WIDTH },
150518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_166_CHECKER_TYPE,
150519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_166_WIDTH },
150520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_167_CHECKER_TYPE,
150521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_167_WIDTH },
150522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_168_CHECKER_TYPE,
150523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_168_WIDTH },
150524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_169_CHECKER_TYPE,
150525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_169_WIDTH },
150526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_170_CHECKER_TYPE,
150527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_170_WIDTH },
150528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_171_CHECKER_TYPE,
150529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_171_WIDTH },
150530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_172_CHECKER_TYPE,
150531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_172_WIDTH },
150532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_173_CHECKER_TYPE,
150533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_173_WIDTH },
150534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_174_CHECKER_TYPE,
150535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_174_WIDTH },
150536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_175_CHECKER_TYPE,
150537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_175_WIDTH },
150538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_176_CHECKER_TYPE,
150539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_176_WIDTH },
150540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_177_CHECKER_TYPE,
150541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_177_WIDTH },
150542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_178_CHECKER_TYPE,
150543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_178_WIDTH },
150544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_179_CHECKER_TYPE,
150545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_179_WIDTH },
150546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_180_CHECKER_TYPE,
150547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_180_WIDTH },
150548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_181_CHECKER_TYPE,
150549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_181_WIDTH },
150550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_182_CHECKER_TYPE,
150551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_182_WIDTH },
150552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_183_CHECKER_TYPE,
150553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_183_WIDTH },
150554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_184_CHECKER_TYPE,
150555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_184_WIDTH },
150556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_185_CHECKER_TYPE,
150557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_185_WIDTH },
150558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_186_CHECKER_TYPE,
150559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_186_WIDTH },
150560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_187_CHECKER_TYPE,
150561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_187_WIDTH },
150562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_188_CHECKER_TYPE,
150563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_188_WIDTH },
150564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_189_CHECKER_TYPE,
150565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_189_WIDTH },
150566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_190_CHECKER_TYPE,
150567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_190_WIDTH },
150568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_191_CHECKER_TYPE,
150569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_191_WIDTH },
150570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_192_CHECKER_TYPE,
150571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_192_WIDTH },
150572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_193_CHECKER_TYPE,
150573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_193_WIDTH },
150574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_194_CHECKER_TYPE,
150575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_194_WIDTH },
150576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_195_CHECKER_TYPE,
150577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_195_WIDTH },
150578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_196_CHECKER_TYPE,
150579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_196_WIDTH },
150580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_197_CHECKER_TYPE,
150581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_197_WIDTH },
150582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_198_CHECKER_TYPE,
150583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_198_WIDTH },
150584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_199_CHECKER_TYPE,
150585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_199_WIDTH },
150586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_200_CHECKER_TYPE,
150587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_200_WIDTH },
150588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_201_CHECKER_TYPE,
150589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_201_WIDTH },
150590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_202_CHECKER_TYPE,
150591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_202_WIDTH },
150592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_203_CHECKER_TYPE,
150593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_203_WIDTH },
150594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_204_CHECKER_TYPE,
150595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_204_WIDTH },
150596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_205_CHECKER_TYPE,
150597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_205_WIDTH },
150598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_206_CHECKER_TYPE,
150599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_206_WIDTH },
150600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_207_CHECKER_TYPE,
150601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_207_WIDTH },
150602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_208_CHECKER_TYPE,
150603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_208_WIDTH },
150604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_209_CHECKER_TYPE,
150605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_209_WIDTH },
150606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_210_CHECKER_TYPE,
150607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_210_WIDTH },
150608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_211_CHECKER_TYPE,
150609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_211_WIDTH },
150610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_212_CHECKER_TYPE,
150611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_212_WIDTH },
150612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_213_CHECKER_TYPE,
150613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_213_WIDTH },
150614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_214_CHECKER_TYPE,
150615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_214_WIDTH },
150616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_215_CHECKER_TYPE,
150617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_215_WIDTH },
150618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_216_CHECKER_TYPE,
150619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_216_WIDTH },
150620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_217_CHECKER_TYPE,
150621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_217_WIDTH },
150622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_218_CHECKER_TYPE,
150623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_218_WIDTH },
150624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_219_CHECKER_TYPE,
150625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_219_WIDTH },
150626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_220_CHECKER_TYPE,
150627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_220_WIDTH },
150628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_221_CHECKER_TYPE,
150629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_221_WIDTH },
150630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_222_CHECKER_TYPE,
150631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_222_WIDTH },
150632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_223_CHECKER_TYPE,
150633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_223_WIDTH },
150634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_224_CHECKER_TYPE,
150635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_224_WIDTH },
150636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_225_CHECKER_TYPE,
150637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_225_WIDTH },
150638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_226_CHECKER_TYPE,
150639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_226_WIDTH },
150640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_227_CHECKER_TYPE,
150641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_227_WIDTH },
150642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_228_CHECKER_TYPE,
150643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_228_WIDTH },
150644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_229_CHECKER_TYPE,
150645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_229_WIDTH },
150646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_230_CHECKER_TYPE,
150647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_230_WIDTH },
150648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_231_CHECKER_TYPE,
150649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_231_WIDTH },
150650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_232_CHECKER_TYPE,
150651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_232_WIDTH },
150652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_233_CHECKER_TYPE,
150653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_233_WIDTH },
150654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_234_CHECKER_TYPE,
150655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_234_WIDTH },
150656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_235_CHECKER_TYPE,
150657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_235_WIDTH },
150658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_236_CHECKER_TYPE,
150659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_236_WIDTH },
150660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_237_CHECKER_TYPE,
150661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_237_WIDTH },
150662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_238_CHECKER_TYPE,
150663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_238_WIDTH },
150664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_239_CHECKER_TYPE,
150665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_239_WIDTH },
150666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_240_CHECKER_TYPE,
150667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_240_WIDTH },
150668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_241_CHECKER_TYPE,
150669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_241_WIDTH },
150670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_242_CHECKER_TYPE,
150671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_242_WIDTH },
150672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_243_CHECKER_TYPE,
150673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_243_WIDTH },
150674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_244_CHECKER_TYPE,
150675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_244_WIDTH },
150676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_245_CHECKER_TYPE,
150677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_245_WIDTH },
150678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_246_CHECKER_TYPE,
150679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_246_WIDTH },
150680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_247_CHECKER_TYPE,
150681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_247_WIDTH },
150682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_248_CHECKER_TYPE,
150683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_248_WIDTH },
150684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_249_CHECKER_TYPE,
150685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_249_WIDTH },
150686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_250_CHECKER_TYPE,
150687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_250_WIDTH },
150688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_251_CHECKER_TYPE,
150689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_251_WIDTH },
150690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_252_CHECKER_TYPE,
150691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_252_WIDTH },
150692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_253_CHECKER_TYPE,
150693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_253_WIDTH },
150694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_254_CHECKER_TYPE,
150695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_254_WIDTH },
150696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_255_CHECKER_TYPE,
150697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_GROUP_255_WIDTH },
150698 };
150699 
150705 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS] =
150706 {
150707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_0_CHECKER_TYPE,
150708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_0_WIDTH },
150709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_1_CHECKER_TYPE,
150710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_1_WIDTH },
150711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_2_CHECKER_TYPE,
150712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_2_WIDTH },
150713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_3_CHECKER_TYPE,
150714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_3_WIDTH },
150715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_4_CHECKER_TYPE,
150716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_4_WIDTH },
150717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_5_CHECKER_TYPE,
150718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_5_WIDTH },
150719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_6_CHECKER_TYPE,
150720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_6_WIDTH },
150721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_7_CHECKER_TYPE,
150722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_7_WIDTH },
150723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_8_CHECKER_TYPE,
150724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_8_WIDTH },
150725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_9_CHECKER_TYPE,
150726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_9_WIDTH },
150727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_10_CHECKER_TYPE,
150728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_10_WIDTH },
150729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_11_CHECKER_TYPE,
150730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_11_WIDTH },
150731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_12_CHECKER_TYPE,
150732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_12_WIDTH },
150733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_13_CHECKER_TYPE,
150734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_13_WIDTH },
150735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_14_CHECKER_TYPE,
150736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_14_WIDTH },
150737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_15_CHECKER_TYPE,
150738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_15_WIDTH },
150739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_16_CHECKER_TYPE,
150740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_16_WIDTH },
150741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_17_CHECKER_TYPE,
150742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_17_WIDTH },
150743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_18_CHECKER_TYPE,
150744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_18_WIDTH },
150745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_19_CHECKER_TYPE,
150746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_19_WIDTH },
150747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_20_CHECKER_TYPE,
150748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_20_WIDTH },
150749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_21_CHECKER_TYPE,
150750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_21_WIDTH },
150751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_22_CHECKER_TYPE,
150752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_22_WIDTH },
150753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_23_CHECKER_TYPE,
150754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_23_WIDTH },
150755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_24_CHECKER_TYPE,
150756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_24_WIDTH },
150757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_25_CHECKER_TYPE,
150758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_25_WIDTH },
150759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_26_CHECKER_TYPE,
150760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_26_WIDTH },
150761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_27_CHECKER_TYPE,
150762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_27_WIDTH },
150763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_28_CHECKER_TYPE,
150764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_28_WIDTH },
150765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_29_CHECKER_TYPE,
150766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_29_WIDTH },
150767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_30_CHECKER_TYPE,
150768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_30_WIDTH },
150769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_31_CHECKER_TYPE,
150770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_31_WIDTH },
150771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_32_CHECKER_TYPE,
150772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_32_WIDTH },
150773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_33_CHECKER_TYPE,
150774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_33_WIDTH },
150775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_34_CHECKER_TYPE,
150776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_34_WIDTH },
150777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_35_CHECKER_TYPE,
150778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_35_WIDTH },
150779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_36_CHECKER_TYPE,
150780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_36_WIDTH },
150781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_37_CHECKER_TYPE,
150782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_37_WIDTH },
150783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_38_CHECKER_TYPE,
150784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_38_WIDTH },
150785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_39_CHECKER_TYPE,
150786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_39_WIDTH },
150787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_40_CHECKER_TYPE,
150788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_40_WIDTH },
150789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_41_CHECKER_TYPE,
150790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_41_WIDTH },
150791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_42_CHECKER_TYPE,
150792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_42_WIDTH },
150793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_43_CHECKER_TYPE,
150794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_43_WIDTH },
150795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_44_CHECKER_TYPE,
150796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_44_WIDTH },
150797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_45_CHECKER_TYPE,
150798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_45_WIDTH },
150799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_46_CHECKER_TYPE,
150800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_46_WIDTH },
150801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_47_CHECKER_TYPE,
150802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_47_WIDTH },
150803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_48_CHECKER_TYPE,
150804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_48_WIDTH },
150805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_49_CHECKER_TYPE,
150806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_49_WIDTH },
150807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_50_CHECKER_TYPE,
150808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_50_WIDTH },
150809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_51_CHECKER_TYPE,
150810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_51_WIDTH },
150811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_52_CHECKER_TYPE,
150812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_52_WIDTH },
150813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_53_CHECKER_TYPE,
150814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_53_WIDTH },
150815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_54_CHECKER_TYPE,
150816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_54_WIDTH },
150817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_55_CHECKER_TYPE,
150818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_55_WIDTH },
150819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_56_CHECKER_TYPE,
150820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_56_WIDTH },
150821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_57_CHECKER_TYPE,
150822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_57_WIDTH },
150823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_58_CHECKER_TYPE,
150824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_58_WIDTH },
150825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_59_CHECKER_TYPE,
150826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_59_WIDTH },
150827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_60_CHECKER_TYPE,
150828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_60_WIDTH },
150829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_61_CHECKER_TYPE,
150830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_61_WIDTH },
150831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_62_CHECKER_TYPE,
150832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_62_WIDTH },
150833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_63_CHECKER_TYPE,
150834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_63_WIDTH },
150835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_64_CHECKER_TYPE,
150836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_64_WIDTH },
150837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_65_CHECKER_TYPE,
150838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_65_WIDTH },
150839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_66_CHECKER_TYPE,
150840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_66_WIDTH },
150841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_67_CHECKER_TYPE,
150842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_67_WIDTH },
150843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_68_CHECKER_TYPE,
150844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_68_WIDTH },
150845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_69_CHECKER_TYPE,
150846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_69_WIDTH },
150847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_70_CHECKER_TYPE,
150848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_70_WIDTH },
150849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_71_CHECKER_TYPE,
150850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_71_WIDTH },
150851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_72_CHECKER_TYPE,
150852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_72_WIDTH },
150853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_73_CHECKER_TYPE,
150854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_73_WIDTH },
150855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_74_CHECKER_TYPE,
150856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_74_WIDTH },
150857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_75_CHECKER_TYPE,
150858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_75_WIDTH },
150859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_76_CHECKER_TYPE,
150860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_76_WIDTH },
150861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_77_CHECKER_TYPE,
150862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_77_WIDTH },
150863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_78_CHECKER_TYPE,
150864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_78_WIDTH },
150865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_79_CHECKER_TYPE,
150866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_79_WIDTH },
150867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_80_CHECKER_TYPE,
150868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_80_WIDTH },
150869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_81_CHECKER_TYPE,
150870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_81_WIDTH },
150871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_82_CHECKER_TYPE,
150872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_82_WIDTH },
150873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_83_CHECKER_TYPE,
150874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_83_WIDTH },
150875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_84_CHECKER_TYPE,
150876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_84_WIDTH },
150877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_85_CHECKER_TYPE,
150878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_85_WIDTH },
150879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_86_CHECKER_TYPE,
150880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_86_WIDTH },
150881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_87_CHECKER_TYPE,
150882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_87_WIDTH },
150883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_88_CHECKER_TYPE,
150884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_88_WIDTH },
150885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_89_CHECKER_TYPE,
150886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_89_WIDTH },
150887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_90_CHECKER_TYPE,
150888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_90_WIDTH },
150889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_91_CHECKER_TYPE,
150890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_91_WIDTH },
150891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_92_CHECKER_TYPE,
150892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_92_WIDTH },
150893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_93_CHECKER_TYPE,
150894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_93_WIDTH },
150895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_94_CHECKER_TYPE,
150896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_94_WIDTH },
150897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_95_CHECKER_TYPE,
150898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_95_WIDTH },
150899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_96_CHECKER_TYPE,
150900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_96_WIDTH },
150901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_97_CHECKER_TYPE,
150902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_97_WIDTH },
150903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_98_CHECKER_TYPE,
150904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_98_WIDTH },
150905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_99_CHECKER_TYPE,
150906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_99_WIDTH },
150907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_100_CHECKER_TYPE,
150908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_100_WIDTH },
150909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_101_CHECKER_TYPE,
150910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_101_WIDTH },
150911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_102_CHECKER_TYPE,
150912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_102_WIDTH },
150913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_103_CHECKER_TYPE,
150914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_103_WIDTH },
150915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_104_CHECKER_TYPE,
150916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_104_WIDTH },
150917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_105_CHECKER_TYPE,
150918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_105_WIDTH },
150919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_106_CHECKER_TYPE,
150920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_106_WIDTH },
150921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_107_CHECKER_TYPE,
150922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_107_WIDTH },
150923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_108_CHECKER_TYPE,
150924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_108_WIDTH },
150925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_109_CHECKER_TYPE,
150926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_109_WIDTH },
150927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_110_CHECKER_TYPE,
150928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_110_WIDTH },
150929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_111_CHECKER_TYPE,
150930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_111_WIDTH },
150931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_112_CHECKER_TYPE,
150932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_112_WIDTH },
150933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_113_CHECKER_TYPE,
150934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_113_WIDTH },
150935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_114_CHECKER_TYPE,
150936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_114_WIDTH },
150937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_115_CHECKER_TYPE,
150938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_115_WIDTH },
150939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_116_CHECKER_TYPE,
150940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_116_WIDTH },
150941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_117_CHECKER_TYPE,
150942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_117_WIDTH },
150943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_118_CHECKER_TYPE,
150944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_118_WIDTH },
150945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_119_CHECKER_TYPE,
150946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_119_WIDTH },
150947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_120_CHECKER_TYPE,
150948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_120_WIDTH },
150949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_121_CHECKER_TYPE,
150950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_121_WIDTH },
150951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_122_CHECKER_TYPE,
150952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_122_WIDTH },
150953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_123_CHECKER_TYPE,
150954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_123_WIDTH },
150955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_124_CHECKER_TYPE,
150956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_124_WIDTH },
150957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_125_CHECKER_TYPE,
150958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_125_WIDTH },
150959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_126_CHECKER_TYPE,
150960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_126_WIDTH },
150961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_127_CHECKER_TYPE,
150962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_127_WIDTH },
150963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_128_CHECKER_TYPE,
150964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_128_WIDTH },
150965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_129_CHECKER_TYPE,
150966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_129_WIDTH },
150967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_130_CHECKER_TYPE,
150968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_130_WIDTH },
150969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_131_CHECKER_TYPE,
150970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_131_WIDTH },
150971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_132_CHECKER_TYPE,
150972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_132_WIDTH },
150973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_133_CHECKER_TYPE,
150974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_133_WIDTH },
150975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_134_CHECKER_TYPE,
150976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_134_WIDTH },
150977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_135_CHECKER_TYPE,
150978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_135_WIDTH },
150979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_136_CHECKER_TYPE,
150980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_136_WIDTH },
150981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_137_CHECKER_TYPE,
150982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_137_WIDTH },
150983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_138_CHECKER_TYPE,
150984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_138_WIDTH },
150985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_139_CHECKER_TYPE,
150986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_139_WIDTH },
150987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_140_CHECKER_TYPE,
150988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_140_WIDTH },
150989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_141_CHECKER_TYPE,
150990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_141_WIDTH },
150991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_142_CHECKER_TYPE,
150992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_142_WIDTH },
150993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_143_CHECKER_TYPE,
150994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_143_WIDTH },
150995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_144_CHECKER_TYPE,
150996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_144_WIDTH },
150997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_145_CHECKER_TYPE,
150998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_145_WIDTH },
150999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_146_CHECKER_TYPE,
151000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_146_WIDTH },
151001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_147_CHECKER_TYPE,
151002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_147_WIDTH },
151003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_148_CHECKER_TYPE,
151004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_148_WIDTH },
151005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_149_CHECKER_TYPE,
151006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_149_WIDTH },
151007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_150_CHECKER_TYPE,
151008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_150_WIDTH },
151009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_151_CHECKER_TYPE,
151010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_151_WIDTH },
151011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_152_CHECKER_TYPE,
151012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_152_WIDTH },
151013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_153_CHECKER_TYPE,
151014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_153_WIDTH },
151015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_154_CHECKER_TYPE,
151016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_154_WIDTH },
151017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_155_CHECKER_TYPE,
151018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_155_WIDTH },
151019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_156_CHECKER_TYPE,
151020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_156_WIDTH },
151021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_157_CHECKER_TYPE,
151022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_157_WIDTH },
151023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_158_CHECKER_TYPE,
151024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_158_WIDTH },
151025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_159_CHECKER_TYPE,
151026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_159_WIDTH },
151027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_160_CHECKER_TYPE,
151028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_160_WIDTH },
151029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_161_CHECKER_TYPE,
151030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_161_WIDTH },
151031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_162_CHECKER_TYPE,
151032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_162_WIDTH },
151033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_163_CHECKER_TYPE,
151034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_163_WIDTH },
151035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_164_CHECKER_TYPE,
151036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_164_WIDTH },
151037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_165_CHECKER_TYPE,
151038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_165_WIDTH },
151039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_166_CHECKER_TYPE,
151040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_166_WIDTH },
151041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_167_CHECKER_TYPE,
151042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_167_WIDTH },
151043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_168_CHECKER_TYPE,
151044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_168_WIDTH },
151045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_169_CHECKER_TYPE,
151046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_169_WIDTH },
151047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_170_CHECKER_TYPE,
151048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_170_WIDTH },
151049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_171_CHECKER_TYPE,
151050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_171_WIDTH },
151051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_172_CHECKER_TYPE,
151052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_172_WIDTH },
151053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_173_CHECKER_TYPE,
151054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_173_WIDTH },
151055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_174_CHECKER_TYPE,
151056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_174_WIDTH },
151057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_175_CHECKER_TYPE,
151058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_175_WIDTH },
151059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_176_CHECKER_TYPE,
151060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_176_WIDTH },
151061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_177_CHECKER_TYPE,
151062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_177_WIDTH },
151063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_178_CHECKER_TYPE,
151064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_178_WIDTH },
151065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_179_CHECKER_TYPE,
151066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_179_WIDTH },
151067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_180_CHECKER_TYPE,
151068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_180_WIDTH },
151069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_181_CHECKER_TYPE,
151070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_181_WIDTH },
151071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_182_CHECKER_TYPE,
151072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_182_WIDTH },
151073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_183_CHECKER_TYPE,
151074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_183_WIDTH },
151075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_184_CHECKER_TYPE,
151076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_184_WIDTH },
151077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_185_CHECKER_TYPE,
151078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_185_WIDTH },
151079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_186_CHECKER_TYPE,
151080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_186_WIDTH },
151081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_187_CHECKER_TYPE,
151082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_187_WIDTH },
151083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_188_CHECKER_TYPE,
151084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_188_WIDTH },
151085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_189_CHECKER_TYPE,
151086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_189_WIDTH },
151087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_190_CHECKER_TYPE,
151088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_190_WIDTH },
151089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_191_CHECKER_TYPE,
151090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_191_WIDTH },
151091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_192_CHECKER_TYPE,
151092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_192_WIDTH },
151093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_193_CHECKER_TYPE,
151094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_193_WIDTH },
151095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_194_CHECKER_TYPE,
151096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_194_WIDTH },
151097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_195_CHECKER_TYPE,
151098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_195_WIDTH },
151099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_196_CHECKER_TYPE,
151100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_196_WIDTH },
151101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_197_CHECKER_TYPE,
151102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_197_WIDTH },
151103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_198_CHECKER_TYPE,
151104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_198_WIDTH },
151105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_199_CHECKER_TYPE,
151106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_199_WIDTH },
151107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_200_CHECKER_TYPE,
151108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_200_WIDTH },
151109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_201_CHECKER_TYPE,
151110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_201_WIDTH },
151111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_202_CHECKER_TYPE,
151112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_202_WIDTH },
151113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_203_CHECKER_TYPE,
151114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_203_WIDTH },
151115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_204_CHECKER_TYPE,
151116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_204_WIDTH },
151117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_205_CHECKER_TYPE,
151118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_205_WIDTH },
151119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_206_CHECKER_TYPE,
151120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_206_WIDTH },
151121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_207_CHECKER_TYPE,
151122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_207_WIDTH },
151123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_208_CHECKER_TYPE,
151124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_208_WIDTH },
151125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_209_CHECKER_TYPE,
151126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_209_WIDTH },
151127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_210_CHECKER_TYPE,
151128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_210_WIDTH },
151129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_211_CHECKER_TYPE,
151130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_211_WIDTH },
151131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_212_CHECKER_TYPE,
151132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_212_WIDTH },
151133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_213_CHECKER_TYPE,
151134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_213_WIDTH },
151135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_214_CHECKER_TYPE,
151136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_214_WIDTH },
151137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_215_CHECKER_TYPE,
151138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_215_WIDTH },
151139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_216_CHECKER_TYPE,
151140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_216_WIDTH },
151141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_217_CHECKER_TYPE,
151142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_217_WIDTH },
151143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_218_CHECKER_TYPE,
151144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_218_WIDTH },
151145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_219_CHECKER_TYPE,
151146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_219_WIDTH },
151147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_220_CHECKER_TYPE,
151148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_220_WIDTH },
151149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_221_CHECKER_TYPE,
151150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_221_WIDTH },
151151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_222_CHECKER_TYPE,
151152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_222_WIDTH },
151153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_223_CHECKER_TYPE,
151154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_223_WIDTH },
151155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_224_CHECKER_TYPE,
151156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_224_WIDTH },
151157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_225_CHECKER_TYPE,
151158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_225_WIDTH },
151159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_226_CHECKER_TYPE,
151160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_226_WIDTH },
151161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_227_CHECKER_TYPE,
151162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_227_WIDTH },
151163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_228_CHECKER_TYPE,
151164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_228_WIDTH },
151165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_229_CHECKER_TYPE,
151166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_229_WIDTH },
151167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_230_CHECKER_TYPE,
151168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_230_WIDTH },
151169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_231_CHECKER_TYPE,
151170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_231_WIDTH },
151171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_232_CHECKER_TYPE,
151172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_232_WIDTH },
151173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_233_CHECKER_TYPE,
151174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_233_WIDTH },
151175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_234_CHECKER_TYPE,
151176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_234_WIDTH },
151177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_235_CHECKER_TYPE,
151178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_235_WIDTH },
151179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_236_CHECKER_TYPE,
151180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_236_WIDTH },
151181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_237_CHECKER_TYPE,
151182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_237_WIDTH },
151183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_238_CHECKER_TYPE,
151184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_238_WIDTH },
151185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_239_CHECKER_TYPE,
151186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_239_WIDTH },
151187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_240_CHECKER_TYPE,
151188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_240_WIDTH },
151189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_241_CHECKER_TYPE,
151190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_241_WIDTH },
151191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_242_CHECKER_TYPE,
151192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_242_WIDTH },
151193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_243_CHECKER_TYPE,
151194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_243_WIDTH },
151195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_244_CHECKER_TYPE,
151196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_244_WIDTH },
151197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_245_CHECKER_TYPE,
151198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_245_WIDTH },
151199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_246_CHECKER_TYPE,
151200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_246_WIDTH },
151201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_247_CHECKER_TYPE,
151202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_247_WIDTH },
151203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_248_CHECKER_TYPE,
151204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_248_WIDTH },
151205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_249_CHECKER_TYPE,
151206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_249_WIDTH },
151207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_250_CHECKER_TYPE,
151208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_250_WIDTH },
151209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_251_CHECKER_TYPE,
151210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_251_WIDTH },
151211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_252_CHECKER_TYPE,
151212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_252_WIDTH },
151213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_253_CHECKER_TYPE,
151214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_253_WIDTH },
151215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_254_CHECKER_TYPE,
151216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_254_WIDTH },
151217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_255_CHECKER_TYPE,
151218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_GROUP_255_WIDTH },
151219 };
151220 
151226 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS] =
151227 {
151228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_0_CHECKER_TYPE,
151229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_0_WIDTH },
151230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_1_CHECKER_TYPE,
151231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_1_WIDTH },
151232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_2_CHECKER_TYPE,
151233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_2_WIDTH },
151234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_3_CHECKER_TYPE,
151235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_3_WIDTH },
151236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_4_CHECKER_TYPE,
151237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_4_WIDTH },
151238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_5_CHECKER_TYPE,
151239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_5_WIDTH },
151240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_6_CHECKER_TYPE,
151241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_6_WIDTH },
151242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_7_CHECKER_TYPE,
151243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_7_WIDTH },
151244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_8_CHECKER_TYPE,
151245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_8_WIDTH },
151246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_9_CHECKER_TYPE,
151247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_9_WIDTH },
151248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_10_CHECKER_TYPE,
151249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_10_WIDTH },
151250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_11_CHECKER_TYPE,
151251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_11_WIDTH },
151252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_12_CHECKER_TYPE,
151253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_12_WIDTH },
151254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_13_CHECKER_TYPE,
151255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_13_WIDTH },
151256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_14_CHECKER_TYPE,
151257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_14_WIDTH },
151258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_15_CHECKER_TYPE,
151259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_15_WIDTH },
151260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_16_CHECKER_TYPE,
151261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_16_WIDTH },
151262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_17_CHECKER_TYPE,
151263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_17_WIDTH },
151264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_18_CHECKER_TYPE,
151265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_18_WIDTH },
151266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_19_CHECKER_TYPE,
151267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_19_WIDTH },
151268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_20_CHECKER_TYPE,
151269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_20_WIDTH },
151270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_21_CHECKER_TYPE,
151271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_21_WIDTH },
151272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_22_CHECKER_TYPE,
151273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_22_WIDTH },
151274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_23_CHECKER_TYPE,
151275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_23_WIDTH },
151276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_24_CHECKER_TYPE,
151277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_24_WIDTH },
151278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_25_CHECKER_TYPE,
151279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_25_WIDTH },
151280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_26_CHECKER_TYPE,
151281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_26_WIDTH },
151282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_27_CHECKER_TYPE,
151283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_27_WIDTH },
151284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_28_CHECKER_TYPE,
151285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_28_WIDTH },
151286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_29_CHECKER_TYPE,
151287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_29_WIDTH },
151288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_30_CHECKER_TYPE,
151289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_30_WIDTH },
151290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_31_CHECKER_TYPE,
151291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_31_WIDTH },
151292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_32_CHECKER_TYPE,
151293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_32_WIDTH },
151294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_33_CHECKER_TYPE,
151295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_33_WIDTH },
151296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_34_CHECKER_TYPE,
151297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_34_WIDTH },
151298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_35_CHECKER_TYPE,
151299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_35_WIDTH },
151300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_36_CHECKER_TYPE,
151301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_36_WIDTH },
151302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_37_CHECKER_TYPE,
151303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_37_WIDTH },
151304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_38_CHECKER_TYPE,
151305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_38_WIDTH },
151306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_39_CHECKER_TYPE,
151307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_39_WIDTH },
151308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_40_CHECKER_TYPE,
151309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_40_WIDTH },
151310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_41_CHECKER_TYPE,
151311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_41_WIDTH },
151312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_42_CHECKER_TYPE,
151313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_42_WIDTH },
151314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_43_CHECKER_TYPE,
151315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_43_WIDTH },
151316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_44_CHECKER_TYPE,
151317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_44_WIDTH },
151318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_45_CHECKER_TYPE,
151319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_45_WIDTH },
151320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_46_CHECKER_TYPE,
151321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_46_WIDTH },
151322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_47_CHECKER_TYPE,
151323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_47_WIDTH },
151324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_48_CHECKER_TYPE,
151325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_48_WIDTH },
151326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_49_CHECKER_TYPE,
151327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_49_WIDTH },
151328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_50_CHECKER_TYPE,
151329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_50_WIDTH },
151330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_51_CHECKER_TYPE,
151331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_51_WIDTH },
151332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_52_CHECKER_TYPE,
151333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_52_WIDTH },
151334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_53_CHECKER_TYPE,
151335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_53_WIDTH },
151336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_54_CHECKER_TYPE,
151337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_54_WIDTH },
151338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_55_CHECKER_TYPE,
151339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_55_WIDTH },
151340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_56_CHECKER_TYPE,
151341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_56_WIDTH },
151342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_57_CHECKER_TYPE,
151343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_57_WIDTH },
151344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_58_CHECKER_TYPE,
151345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_58_WIDTH },
151346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_59_CHECKER_TYPE,
151347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_59_WIDTH },
151348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_60_CHECKER_TYPE,
151349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_60_WIDTH },
151350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_61_CHECKER_TYPE,
151351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_61_WIDTH },
151352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_62_CHECKER_TYPE,
151353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_62_WIDTH },
151354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_63_CHECKER_TYPE,
151355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_63_WIDTH },
151356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_64_CHECKER_TYPE,
151357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_64_WIDTH },
151358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_65_CHECKER_TYPE,
151359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_65_WIDTH },
151360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_66_CHECKER_TYPE,
151361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_66_WIDTH },
151362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_67_CHECKER_TYPE,
151363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_67_WIDTH },
151364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_68_CHECKER_TYPE,
151365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_68_WIDTH },
151366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_69_CHECKER_TYPE,
151367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_69_WIDTH },
151368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_70_CHECKER_TYPE,
151369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_70_WIDTH },
151370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_71_CHECKER_TYPE,
151371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_71_WIDTH },
151372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_72_CHECKER_TYPE,
151373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_72_WIDTH },
151374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_73_CHECKER_TYPE,
151375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_73_WIDTH },
151376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_74_CHECKER_TYPE,
151377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_74_WIDTH },
151378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_75_CHECKER_TYPE,
151379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_75_WIDTH },
151380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_76_CHECKER_TYPE,
151381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_76_WIDTH },
151382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_77_CHECKER_TYPE,
151383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_77_WIDTH },
151384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_78_CHECKER_TYPE,
151385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_78_WIDTH },
151386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_79_CHECKER_TYPE,
151387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_79_WIDTH },
151388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_80_CHECKER_TYPE,
151389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_80_WIDTH },
151390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_81_CHECKER_TYPE,
151391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_81_WIDTH },
151392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_82_CHECKER_TYPE,
151393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_82_WIDTH },
151394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_83_CHECKER_TYPE,
151395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_83_WIDTH },
151396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_84_CHECKER_TYPE,
151397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_84_WIDTH },
151398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_85_CHECKER_TYPE,
151399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_85_WIDTH },
151400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_86_CHECKER_TYPE,
151401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_86_WIDTH },
151402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_87_CHECKER_TYPE,
151403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_87_WIDTH },
151404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_88_CHECKER_TYPE,
151405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_88_WIDTH },
151406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_89_CHECKER_TYPE,
151407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_89_WIDTH },
151408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_90_CHECKER_TYPE,
151409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_90_WIDTH },
151410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_91_CHECKER_TYPE,
151411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_91_WIDTH },
151412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_92_CHECKER_TYPE,
151413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_92_WIDTH },
151414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_93_CHECKER_TYPE,
151415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_93_WIDTH },
151416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_94_CHECKER_TYPE,
151417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_94_WIDTH },
151418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_95_CHECKER_TYPE,
151419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_95_WIDTH },
151420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_96_CHECKER_TYPE,
151421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_96_WIDTH },
151422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_97_CHECKER_TYPE,
151423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_97_WIDTH },
151424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_98_CHECKER_TYPE,
151425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_98_WIDTH },
151426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_99_CHECKER_TYPE,
151427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_99_WIDTH },
151428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_100_CHECKER_TYPE,
151429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_100_WIDTH },
151430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_101_CHECKER_TYPE,
151431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_101_WIDTH },
151432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_102_CHECKER_TYPE,
151433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_102_WIDTH },
151434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_103_CHECKER_TYPE,
151435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_103_WIDTH },
151436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_104_CHECKER_TYPE,
151437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_104_WIDTH },
151438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_105_CHECKER_TYPE,
151439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_105_WIDTH },
151440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_106_CHECKER_TYPE,
151441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_106_WIDTH },
151442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_107_CHECKER_TYPE,
151443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_107_WIDTH },
151444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_108_CHECKER_TYPE,
151445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_108_WIDTH },
151446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_109_CHECKER_TYPE,
151447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_109_WIDTH },
151448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_110_CHECKER_TYPE,
151449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_110_WIDTH },
151450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_111_CHECKER_TYPE,
151451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_111_WIDTH },
151452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_112_CHECKER_TYPE,
151453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_112_WIDTH },
151454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_113_CHECKER_TYPE,
151455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_113_WIDTH },
151456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_114_CHECKER_TYPE,
151457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_114_WIDTH },
151458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_115_CHECKER_TYPE,
151459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_115_WIDTH },
151460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_116_CHECKER_TYPE,
151461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_116_WIDTH },
151462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_117_CHECKER_TYPE,
151463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_117_WIDTH },
151464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_118_CHECKER_TYPE,
151465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_118_WIDTH },
151466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_119_CHECKER_TYPE,
151467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_119_WIDTH },
151468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_120_CHECKER_TYPE,
151469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_120_WIDTH },
151470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_121_CHECKER_TYPE,
151471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_121_WIDTH },
151472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_122_CHECKER_TYPE,
151473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_122_WIDTH },
151474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_123_CHECKER_TYPE,
151475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_123_WIDTH },
151476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_124_CHECKER_TYPE,
151477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_124_WIDTH },
151478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_125_CHECKER_TYPE,
151479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_125_WIDTH },
151480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_126_CHECKER_TYPE,
151481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_126_WIDTH },
151482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_127_CHECKER_TYPE,
151483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_127_WIDTH },
151484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_128_CHECKER_TYPE,
151485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_128_WIDTH },
151486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_129_CHECKER_TYPE,
151487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_129_WIDTH },
151488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_130_CHECKER_TYPE,
151489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_130_WIDTH },
151490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_131_CHECKER_TYPE,
151491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_131_WIDTH },
151492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_132_CHECKER_TYPE,
151493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_132_WIDTH },
151494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_133_CHECKER_TYPE,
151495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_133_WIDTH },
151496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_134_CHECKER_TYPE,
151497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_134_WIDTH },
151498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_135_CHECKER_TYPE,
151499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_135_WIDTH },
151500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_136_CHECKER_TYPE,
151501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_136_WIDTH },
151502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_137_CHECKER_TYPE,
151503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_137_WIDTH },
151504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_138_CHECKER_TYPE,
151505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_138_WIDTH },
151506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_139_CHECKER_TYPE,
151507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_139_WIDTH },
151508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_140_CHECKER_TYPE,
151509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_140_WIDTH },
151510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_141_CHECKER_TYPE,
151511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_141_WIDTH },
151512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_142_CHECKER_TYPE,
151513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_142_WIDTH },
151514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_143_CHECKER_TYPE,
151515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_143_WIDTH },
151516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_144_CHECKER_TYPE,
151517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_144_WIDTH },
151518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_145_CHECKER_TYPE,
151519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_145_WIDTH },
151520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_146_CHECKER_TYPE,
151521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_146_WIDTH },
151522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_147_CHECKER_TYPE,
151523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_147_WIDTH },
151524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_148_CHECKER_TYPE,
151525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_148_WIDTH },
151526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_149_CHECKER_TYPE,
151527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_149_WIDTH },
151528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_150_CHECKER_TYPE,
151529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_150_WIDTH },
151530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_151_CHECKER_TYPE,
151531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_151_WIDTH },
151532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_152_CHECKER_TYPE,
151533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_152_WIDTH },
151534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_153_CHECKER_TYPE,
151535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_153_WIDTH },
151536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_154_CHECKER_TYPE,
151537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_154_WIDTH },
151538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_155_CHECKER_TYPE,
151539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_155_WIDTH },
151540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_156_CHECKER_TYPE,
151541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_156_WIDTH },
151542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_157_CHECKER_TYPE,
151543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_157_WIDTH },
151544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_158_CHECKER_TYPE,
151545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_158_WIDTH },
151546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_159_CHECKER_TYPE,
151547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_159_WIDTH },
151548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_160_CHECKER_TYPE,
151549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_160_WIDTH },
151550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_161_CHECKER_TYPE,
151551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_161_WIDTH },
151552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_162_CHECKER_TYPE,
151553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_162_WIDTH },
151554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_163_CHECKER_TYPE,
151555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_163_WIDTH },
151556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_164_CHECKER_TYPE,
151557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_164_WIDTH },
151558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_165_CHECKER_TYPE,
151559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_165_WIDTH },
151560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_166_CHECKER_TYPE,
151561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_166_WIDTH },
151562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_167_CHECKER_TYPE,
151563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_167_WIDTH },
151564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_168_CHECKER_TYPE,
151565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_168_WIDTH },
151566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_169_CHECKER_TYPE,
151567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_169_WIDTH },
151568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_170_CHECKER_TYPE,
151569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_170_WIDTH },
151570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_171_CHECKER_TYPE,
151571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_171_WIDTH },
151572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_172_CHECKER_TYPE,
151573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_172_WIDTH },
151574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_173_CHECKER_TYPE,
151575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_173_WIDTH },
151576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_174_CHECKER_TYPE,
151577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_174_WIDTH },
151578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_175_CHECKER_TYPE,
151579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_175_WIDTH },
151580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_176_CHECKER_TYPE,
151581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_176_WIDTH },
151582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_177_CHECKER_TYPE,
151583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_177_WIDTH },
151584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_178_CHECKER_TYPE,
151585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_178_WIDTH },
151586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_179_CHECKER_TYPE,
151587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_179_WIDTH },
151588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_180_CHECKER_TYPE,
151589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_180_WIDTH },
151590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_181_CHECKER_TYPE,
151591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_181_WIDTH },
151592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_182_CHECKER_TYPE,
151593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_182_WIDTH },
151594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_183_CHECKER_TYPE,
151595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_183_WIDTH },
151596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_184_CHECKER_TYPE,
151597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_184_WIDTH },
151598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_185_CHECKER_TYPE,
151599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_185_WIDTH },
151600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_186_CHECKER_TYPE,
151601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_186_WIDTH },
151602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_187_CHECKER_TYPE,
151603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_187_WIDTH },
151604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_188_CHECKER_TYPE,
151605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_188_WIDTH },
151606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_189_CHECKER_TYPE,
151607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_189_WIDTH },
151608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_190_CHECKER_TYPE,
151609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_190_WIDTH },
151610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_191_CHECKER_TYPE,
151611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_191_WIDTH },
151612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_192_CHECKER_TYPE,
151613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_192_WIDTH },
151614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_193_CHECKER_TYPE,
151615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_193_WIDTH },
151616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_194_CHECKER_TYPE,
151617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_194_WIDTH },
151618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_195_CHECKER_TYPE,
151619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_195_WIDTH },
151620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_196_CHECKER_TYPE,
151621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_196_WIDTH },
151622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_197_CHECKER_TYPE,
151623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_197_WIDTH },
151624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_198_CHECKER_TYPE,
151625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_198_WIDTH },
151626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_199_CHECKER_TYPE,
151627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_199_WIDTH },
151628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_200_CHECKER_TYPE,
151629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_200_WIDTH },
151630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_201_CHECKER_TYPE,
151631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_201_WIDTH },
151632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_202_CHECKER_TYPE,
151633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_202_WIDTH },
151634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_203_CHECKER_TYPE,
151635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_203_WIDTH },
151636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_204_CHECKER_TYPE,
151637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_204_WIDTH },
151638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_205_CHECKER_TYPE,
151639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_205_WIDTH },
151640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_206_CHECKER_TYPE,
151641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_206_WIDTH },
151642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_207_CHECKER_TYPE,
151643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_207_WIDTH },
151644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_208_CHECKER_TYPE,
151645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_208_WIDTH },
151646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_209_CHECKER_TYPE,
151647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_209_WIDTH },
151648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_210_CHECKER_TYPE,
151649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_210_WIDTH },
151650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_211_CHECKER_TYPE,
151651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_211_WIDTH },
151652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_212_CHECKER_TYPE,
151653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_212_WIDTH },
151654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_213_CHECKER_TYPE,
151655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_213_WIDTH },
151656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_214_CHECKER_TYPE,
151657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_214_WIDTH },
151658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_215_CHECKER_TYPE,
151659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_215_WIDTH },
151660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_216_CHECKER_TYPE,
151661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_216_WIDTH },
151662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_217_CHECKER_TYPE,
151663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_217_WIDTH },
151664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_218_CHECKER_TYPE,
151665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_218_WIDTH },
151666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_219_CHECKER_TYPE,
151667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_219_WIDTH },
151668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_220_CHECKER_TYPE,
151669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_220_WIDTH },
151670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_221_CHECKER_TYPE,
151671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_221_WIDTH },
151672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_222_CHECKER_TYPE,
151673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_222_WIDTH },
151674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_223_CHECKER_TYPE,
151675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_223_WIDTH },
151676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_224_CHECKER_TYPE,
151677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_224_WIDTH },
151678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_225_CHECKER_TYPE,
151679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_225_WIDTH },
151680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_226_CHECKER_TYPE,
151681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_226_WIDTH },
151682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_227_CHECKER_TYPE,
151683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_227_WIDTH },
151684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_228_CHECKER_TYPE,
151685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_228_WIDTH },
151686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_229_CHECKER_TYPE,
151687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_229_WIDTH },
151688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_230_CHECKER_TYPE,
151689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_230_WIDTH },
151690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_231_CHECKER_TYPE,
151691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_231_WIDTH },
151692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_232_CHECKER_TYPE,
151693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_232_WIDTH },
151694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_233_CHECKER_TYPE,
151695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_233_WIDTH },
151696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_234_CHECKER_TYPE,
151697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_234_WIDTH },
151698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_235_CHECKER_TYPE,
151699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_235_WIDTH },
151700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_236_CHECKER_TYPE,
151701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_236_WIDTH },
151702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_237_CHECKER_TYPE,
151703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_237_WIDTH },
151704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_238_CHECKER_TYPE,
151705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_238_WIDTH },
151706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_239_CHECKER_TYPE,
151707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_239_WIDTH },
151708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_240_CHECKER_TYPE,
151709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_240_WIDTH },
151710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_241_CHECKER_TYPE,
151711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_241_WIDTH },
151712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_242_CHECKER_TYPE,
151713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_242_WIDTH },
151714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_243_CHECKER_TYPE,
151715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_243_WIDTH },
151716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_244_CHECKER_TYPE,
151717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_244_WIDTH },
151718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_245_CHECKER_TYPE,
151719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_245_WIDTH },
151720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_246_CHECKER_TYPE,
151721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_246_WIDTH },
151722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_247_CHECKER_TYPE,
151723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_247_WIDTH },
151724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_248_CHECKER_TYPE,
151725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_248_WIDTH },
151726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_249_CHECKER_TYPE,
151727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_249_WIDTH },
151728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_250_CHECKER_TYPE,
151729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_250_WIDTH },
151730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_251_CHECKER_TYPE,
151731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_251_WIDTH },
151732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_252_CHECKER_TYPE,
151733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_252_WIDTH },
151734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_253_CHECKER_TYPE,
151735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_253_WIDTH },
151736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_254_CHECKER_TYPE,
151737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_254_WIDTH },
151738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_255_CHECKER_TYPE,
151739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_GROUP_255_WIDTH },
151740 };
151741 
151747 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_MAX_NUM_CHECKERS] =
151748 {
151749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_0_CHECKER_TYPE,
151750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_0_WIDTH },
151751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_1_CHECKER_TYPE,
151752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_1_WIDTH },
151753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_2_CHECKER_TYPE,
151754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_2_WIDTH },
151755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_3_CHECKER_TYPE,
151756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_3_WIDTH },
151757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_4_CHECKER_TYPE,
151758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_4_WIDTH },
151759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_5_CHECKER_TYPE,
151760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_5_WIDTH },
151761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_6_CHECKER_TYPE,
151762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_6_WIDTH },
151763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_7_CHECKER_TYPE,
151764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_7_WIDTH },
151765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_8_CHECKER_TYPE,
151766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_8_WIDTH },
151767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_9_CHECKER_TYPE,
151768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_9_WIDTH },
151769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_10_CHECKER_TYPE,
151770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_10_WIDTH },
151771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_11_CHECKER_TYPE,
151772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_11_WIDTH },
151773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_12_CHECKER_TYPE,
151774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_12_WIDTH },
151775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_13_CHECKER_TYPE,
151776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_13_WIDTH },
151777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_14_CHECKER_TYPE,
151778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_14_WIDTH },
151779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_15_CHECKER_TYPE,
151780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_15_WIDTH },
151781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_16_CHECKER_TYPE,
151782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_16_WIDTH },
151783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_17_CHECKER_TYPE,
151784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_17_WIDTH },
151785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_18_CHECKER_TYPE,
151786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_18_WIDTH },
151787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_19_CHECKER_TYPE,
151788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_19_WIDTH },
151789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_20_CHECKER_TYPE,
151790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_20_WIDTH },
151791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_21_CHECKER_TYPE,
151792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_21_WIDTH },
151793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_22_CHECKER_TYPE,
151794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_22_WIDTH },
151795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_23_CHECKER_TYPE,
151796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_23_WIDTH },
151797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_24_CHECKER_TYPE,
151798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_24_WIDTH },
151799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_25_CHECKER_TYPE,
151800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_25_WIDTH },
151801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_26_CHECKER_TYPE,
151802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_26_WIDTH },
151803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_27_CHECKER_TYPE,
151804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_27_WIDTH },
151805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_28_CHECKER_TYPE,
151806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_28_WIDTH },
151807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_29_CHECKER_TYPE,
151808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_29_WIDTH },
151809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_30_CHECKER_TYPE,
151810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_30_WIDTH },
151811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_31_CHECKER_TYPE,
151812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_31_WIDTH },
151813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_32_CHECKER_TYPE,
151814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_32_WIDTH },
151815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_33_CHECKER_TYPE,
151816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_33_WIDTH },
151817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_34_CHECKER_TYPE,
151818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_34_WIDTH },
151819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_35_CHECKER_TYPE,
151820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_35_WIDTH },
151821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_36_CHECKER_TYPE,
151822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_36_WIDTH },
151823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_37_CHECKER_TYPE,
151824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_37_WIDTH },
151825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_38_CHECKER_TYPE,
151826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_38_WIDTH },
151827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_39_CHECKER_TYPE,
151828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_39_WIDTH },
151829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_40_CHECKER_TYPE,
151830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_40_WIDTH },
151831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_41_CHECKER_TYPE,
151832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_41_WIDTH },
151833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_42_CHECKER_TYPE,
151834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_42_WIDTH },
151835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_43_CHECKER_TYPE,
151836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_43_WIDTH },
151837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_44_CHECKER_TYPE,
151838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_44_WIDTH },
151839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_45_CHECKER_TYPE,
151840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_45_WIDTH },
151841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_46_CHECKER_TYPE,
151842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_46_WIDTH },
151843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_47_CHECKER_TYPE,
151844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_47_WIDTH },
151845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_48_CHECKER_TYPE,
151846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_48_WIDTH },
151847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_49_CHECKER_TYPE,
151848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_49_WIDTH },
151849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_50_CHECKER_TYPE,
151850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_50_WIDTH },
151851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_51_CHECKER_TYPE,
151852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_51_WIDTH },
151853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_52_CHECKER_TYPE,
151854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_52_WIDTH },
151855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_53_CHECKER_TYPE,
151856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_53_WIDTH },
151857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_54_CHECKER_TYPE,
151858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_54_WIDTH },
151859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_55_CHECKER_TYPE,
151860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_55_WIDTH },
151861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_56_CHECKER_TYPE,
151862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_56_WIDTH },
151863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_57_CHECKER_TYPE,
151864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_57_WIDTH },
151865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_58_CHECKER_TYPE,
151866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_58_WIDTH },
151867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_59_CHECKER_TYPE,
151868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_59_WIDTH },
151869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_60_CHECKER_TYPE,
151870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_60_WIDTH },
151871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_61_CHECKER_TYPE,
151872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_61_WIDTH },
151873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_62_CHECKER_TYPE,
151874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_62_WIDTH },
151875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_63_CHECKER_TYPE,
151876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_63_WIDTH },
151877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_64_CHECKER_TYPE,
151878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_64_WIDTH },
151879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_65_CHECKER_TYPE,
151880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_65_WIDTH },
151881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_66_CHECKER_TYPE,
151882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_66_WIDTH },
151883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_67_CHECKER_TYPE,
151884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_67_WIDTH },
151885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_68_CHECKER_TYPE,
151886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_68_WIDTH },
151887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_69_CHECKER_TYPE,
151888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_69_WIDTH },
151889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_70_CHECKER_TYPE,
151890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_70_WIDTH },
151891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_71_CHECKER_TYPE,
151892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_71_WIDTH },
151893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_72_CHECKER_TYPE,
151894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_72_WIDTH },
151895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_73_CHECKER_TYPE,
151896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_73_WIDTH },
151897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_74_CHECKER_TYPE,
151898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_74_WIDTH },
151899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_75_CHECKER_TYPE,
151900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_75_WIDTH },
151901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_76_CHECKER_TYPE,
151902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_76_WIDTH },
151903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_77_CHECKER_TYPE,
151904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_77_WIDTH },
151905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_78_CHECKER_TYPE,
151906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_78_WIDTH },
151907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_79_CHECKER_TYPE,
151908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_79_WIDTH },
151909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_80_CHECKER_TYPE,
151910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_80_WIDTH },
151911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_81_CHECKER_TYPE,
151912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_81_WIDTH },
151913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_82_CHECKER_TYPE,
151914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_82_WIDTH },
151915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_83_CHECKER_TYPE,
151916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_83_WIDTH },
151917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_84_CHECKER_TYPE,
151918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_84_WIDTH },
151919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_85_CHECKER_TYPE,
151920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_85_WIDTH },
151921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_86_CHECKER_TYPE,
151922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_86_WIDTH },
151923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_87_CHECKER_TYPE,
151924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_87_WIDTH },
151925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_88_CHECKER_TYPE,
151926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_88_WIDTH },
151927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_89_CHECKER_TYPE,
151928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_89_WIDTH },
151929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_90_CHECKER_TYPE,
151930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_90_WIDTH },
151931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_91_CHECKER_TYPE,
151932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_91_WIDTH },
151933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_92_CHECKER_TYPE,
151934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_92_WIDTH },
151935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_93_CHECKER_TYPE,
151936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_93_WIDTH },
151937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_94_CHECKER_TYPE,
151938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_94_WIDTH },
151939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_95_CHECKER_TYPE,
151940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_95_WIDTH },
151941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_96_CHECKER_TYPE,
151942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_96_WIDTH },
151943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_97_CHECKER_TYPE,
151944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_97_WIDTH },
151945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_98_CHECKER_TYPE,
151946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_98_WIDTH },
151947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_99_CHECKER_TYPE,
151948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_99_WIDTH },
151949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_100_CHECKER_TYPE,
151950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_100_WIDTH },
151951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_101_CHECKER_TYPE,
151952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_101_WIDTH },
151953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_102_CHECKER_TYPE,
151954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_102_WIDTH },
151955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_103_CHECKER_TYPE,
151956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_103_WIDTH },
151957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_104_CHECKER_TYPE,
151958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_104_WIDTH },
151959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_105_CHECKER_TYPE,
151960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_105_WIDTH },
151961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_106_CHECKER_TYPE,
151962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_106_WIDTH },
151963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_107_CHECKER_TYPE,
151964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_107_WIDTH },
151965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_108_CHECKER_TYPE,
151966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_108_WIDTH },
151967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_109_CHECKER_TYPE,
151968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_109_WIDTH },
151969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_110_CHECKER_TYPE,
151970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_110_WIDTH },
151971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_111_CHECKER_TYPE,
151972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_111_WIDTH },
151973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_112_CHECKER_TYPE,
151974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_112_WIDTH },
151975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_113_CHECKER_TYPE,
151976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_113_WIDTH },
151977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_114_CHECKER_TYPE,
151978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_114_WIDTH },
151979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_115_CHECKER_TYPE,
151980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_115_WIDTH },
151981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_116_CHECKER_TYPE,
151982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_116_WIDTH },
151983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_117_CHECKER_TYPE,
151984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_117_WIDTH },
151985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_118_CHECKER_TYPE,
151986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_118_WIDTH },
151987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_119_CHECKER_TYPE,
151988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_119_WIDTH },
151989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_120_CHECKER_TYPE,
151990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_120_WIDTH },
151991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_121_CHECKER_TYPE,
151992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_121_WIDTH },
151993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_122_CHECKER_TYPE,
151994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_122_WIDTH },
151995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_123_CHECKER_TYPE,
151996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_123_WIDTH },
151997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_124_CHECKER_TYPE,
151998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_124_WIDTH },
151999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_125_CHECKER_TYPE,
152000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_125_WIDTH },
152001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_126_CHECKER_TYPE,
152002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_126_WIDTH },
152003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_127_CHECKER_TYPE,
152004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_127_WIDTH },
152005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_128_CHECKER_TYPE,
152006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_128_WIDTH },
152007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_129_CHECKER_TYPE,
152008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_129_WIDTH },
152009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_130_CHECKER_TYPE,
152010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_130_WIDTH },
152011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_131_CHECKER_TYPE,
152012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_131_WIDTH },
152013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_132_CHECKER_TYPE,
152014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_132_WIDTH },
152015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_133_CHECKER_TYPE,
152016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_133_WIDTH },
152017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_134_CHECKER_TYPE,
152018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_134_WIDTH },
152019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_135_CHECKER_TYPE,
152020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_135_WIDTH },
152021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_136_CHECKER_TYPE,
152022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_136_WIDTH },
152023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_137_CHECKER_TYPE,
152024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_137_WIDTH },
152025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_138_CHECKER_TYPE,
152026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_138_WIDTH },
152027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_139_CHECKER_TYPE,
152028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_139_WIDTH },
152029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_140_CHECKER_TYPE,
152030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_140_WIDTH },
152031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_141_CHECKER_TYPE,
152032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_141_WIDTH },
152033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_142_CHECKER_TYPE,
152034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_142_WIDTH },
152035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_143_CHECKER_TYPE,
152036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_143_WIDTH },
152037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_144_CHECKER_TYPE,
152038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_144_WIDTH },
152039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_145_CHECKER_TYPE,
152040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_145_WIDTH },
152041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_146_CHECKER_TYPE,
152042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_146_WIDTH },
152043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_147_CHECKER_TYPE,
152044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_147_WIDTH },
152045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_148_CHECKER_TYPE,
152046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_148_WIDTH },
152047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_149_CHECKER_TYPE,
152048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_149_WIDTH },
152049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_150_CHECKER_TYPE,
152050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_150_WIDTH },
152051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_151_CHECKER_TYPE,
152052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_151_WIDTH },
152053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_152_CHECKER_TYPE,
152054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_152_WIDTH },
152055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_153_CHECKER_TYPE,
152056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_153_WIDTH },
152057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_154_CHECKER_TYPE,
152058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_154_WIDTH },
152059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_155_CHECKER_TYPE,
152060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_155_WIDTH },
152061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_156_CHECKER_TYPE,
152062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_156_WIDTH },
152063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_157_CHECKER_TYPE,
152064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_157_WIDTH },
152065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_158_CHECKER_TYPE,
152066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_158_WIDTH },
152067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_159_CHECKER_TYPE,
152068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_159_WIDTH },
152069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_160_CHECKER_TYPE,
152070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_160_WIDTH },
152071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_161_CHECKER_TYPE,
152072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_161_WIDTH },
152073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_162_CHECKER_TYPE,
152074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_162_WIDTH },
152075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_163_CHECKER_TYPE,
152076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_163_WIDTH },
152077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_164_CHECKER_TYPE,
152078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_164_WIDTH },
152079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_165_CHECKER_TYPE,
152080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_165_WIDTH },
152081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_166_CHECKER_TYPE,
152082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_166_WIDTH },
152083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_167_CHECKER_TYPE,
152084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_167_WIDTH },
152085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_168_CHECKER_TYPE,
152086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_168_WIDTH },
152087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_169_CHECKER_TYPE,
152088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_169_WIDTH },
152089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_170_CHECKER_TYPE,
152090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_170_WIDTH },
152091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_171_CHECKER_TYPE,
152092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_171_WIDTH },
152093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_172_CHECKER_TYPE,
152094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_172_WIDTH },
152095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_173_CHECKER_TYPE,
152096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_173_WIDTH },
152097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_174_CHECKER_TYPE,
152098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_174_WIDTH },
152099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_175_CHECKER_TYPE,
152100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_175_WIDTH },
152101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_176_CHECKER_TYPE,
152102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_176_WIDTH },
152103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_177_CHECKER_TYPE,
152104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_177_WIDTH },
152105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_178_CHECKER_TYPE,
152106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_178_WIDTH },
152107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_179_CHECKER_TYPE,
152108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_179_WIDTH },
152109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_180_CHECKER_TYPE,
152110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_180_WIDTH },
152111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_181_CHECKER_TYPE,
152112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_181_WIDTH },
152113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_182_CHECKER_TYPE,
152114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_182_WIDTH },
152115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_183_CHECKER_TYPE,
152116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_183_WIDTH },
152117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_184_CHECKER_TYPE,
152118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_184_WIDTH },
152119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_185_CHECKER_TYPE,
152120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_185_WIDTH },
152121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_186_CHECKER_TYPE,
152122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_186_WIDTH },
152123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_187_CHECKER_TYPE,
152124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_187_WIDTH },
152125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_188_CHECKER_TYPE,
152126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_188_WIDTH },
152127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_189_CHECKER_TYPE,
152128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_189_WIDTH },
152129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_190_CHECKER_TYPE,
152130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_190_WIDTH },
152131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_191_CHECKER_TYPE,
152132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_191_WIDTH },
152133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_192_CHECKER_TYPE,
152134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_192_WIDTH },
152135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_193_CHECKER_TYPE,
152136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_193_WIDTH },
152137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_194_CHECKER_TYPE,
152138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_194_WIDTH },
152139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_195_CHECKER_TYPE,
152140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_195_WIDTH },
152141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_196_CHECKER_TYPE,
152142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_196_WIDTH },
152143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_197_CHECKER_TYPE,
152144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_197_WIDTH },
152145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_198_CHECKER_TYPE,
152146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_198_WIDTH },
152147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_199_CHECKER_TYPE,
152148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_199_WIDTH },
152149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_200_CHECKER_TYPE,
152150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_200_WIDTH },
152151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_201_CHECKER_TYPE,
152152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_201_WIDTH },
152153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_202_CHECKER_TYPE,
152154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_202_WIDTH },
152155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_203_CHECKER_TYPE,
152156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_203_WIDTH },
152157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_204_CHECKER_TYPE,
152158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_204_WIDTH },
152159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_205_CHECKER_TYPE,
152160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_205_WIDTH },
152161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_206_CHECKER_TYPE,
152162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_206_WIDTH },
152163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_207_CHECKER_TYPE,
152164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_207_WIDTH },
152165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_208_CHECKER_TYPE,
152166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_208_WIDTH },
152167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_209_CHECKER_TYPE,
152168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_209_WIDTH },
152169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_210_CHECKER_TYPE,
152170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_210_WIDTH },
152171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_211_CHECKER_TYPE,
152172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_211_WIDTH },
152173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_212_CHECKER_TYPE,
152174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_212_WIDTH },
152175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_213_CHECKER_TYPE,
152176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_213_WIDTH },
152177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_214_CHECKER_TYPE,
152178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_214_WIDTH },
152179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_215_CHECKER_TYPE,
152180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_215_WIDTH },
152181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_216_CHECKER_TYPE,
152182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_216_WIDTH },
152183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_217_CHECKER_TYPE,
152184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_217_WIDTH },
152185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_218_CHECKER_TYPE,
152186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_218_WIDTH },
152187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_219_CHECKER_TYPE,
152188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_219_WIDTH },
152189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_220_CHECKER_TYPE,
152190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_220_WIDTH },
152191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_221_CHECKER_TYPE,
152192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_221_WIDTH },
152193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_222_CHECKER_TYPE,
152194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_222_WIDTH },
152195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_223_CHECKER_TYPE,
152196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_223_WIDTH },
152197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_224_CHECKER_TYPE,
152198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_224_WIDTH },
152199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_225_CHECKER_TYPE,
152200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_225_WIDTH },
152201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_226_CHECKER_TYPE,
152202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_226_WIDTH },
152203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_227_CHECKER_TYPE,
152204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_227_WIDTH },
152205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_228_CHECKER_TYPE,
152206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_228_WIDTH },
152207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_229_CHECKER_TYPE,
152208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_229_WIDTH },
152209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_230_CHECKER_TYPE,
152210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_230_WIDTH },
152211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_231_CHECKER_TYPE,
152212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_231_WIDTH },
152213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_232_CHECKER_TYPE,
152214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_232_WIDTH },
152215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_233_CHECKER_TYPE,
152216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_233_WIDTH },
152217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_234_CHECKER_TYPE,
152218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_234_WIDTH },
152219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_235_CHECKER_TYPE,
152220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_235_WIDTH },
152221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_236_CHECKER_TYPE,
152222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_236_WIDTH },
152223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_237_CHECKER_TYPE,
152224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_237_WIDTH },
152225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_238_CHECKER_TYPE,
152226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_238_WIDTH },
152227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_239_CHECKER_TYPE,
152228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_239_WIDTH },
152229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_240_CHECKER_TYPE,
152230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_240_WIDTH },
152231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_241_CHECKER_TYPE,
152232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_241_WIDTH },
152233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_242_CHECKER_TYPE,
152234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_242_WIDTH },
152235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_243_CHECKER_TYPE,
152236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_243_WIDTH },
152237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_244_CHECKER_TYPE,
152238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_244_WIDTH },
152239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_245_CHECKER_TYPE,
152240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_245_WIDTH },
152241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_246_CHECKER_TYPE,
152242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_246_WIDTH },
152243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_247_CHECKER_TYPE,
152244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_247_WIDTH },
152245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_248_CHECKER_TYPE,
152246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_248_WIDTH },
152247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_249_CHECKER_TYPE,
152248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_249_WIDTH },
152249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_250_CHECKER_TYPE,
152250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_250_WIDTH },
152251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_251_CHECKER_TYPE,
152252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_251_WIDTH },
152253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_252_CHECKER_TYPE,
152254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_252_WIDTH },
152255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_253_CHECKER_TYPE,
152256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_253_WIDTH },
152257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_254_CHECKER_TYPE,
152258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_254_WIDTH },
152259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_255_CHECKER_TYPE,
152260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_GROUP_255_WIDTH },
152261 };
152262 
152268 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_MAX_NUM_CHECKERS] =
152269 {
152270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_0_CHECKER_TYPE,
152271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_0_WIDTH },
152272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_1_CHECKER_TYPE,
152273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_1_WIDTH },
152274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_2_CHECKER_TYPE,
152275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_2_WIDTH },
152276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_3_CHECKER_TYPE,
152277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_3_WIDTH },
152278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_4_CHECKER_TYPE,
152279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_4_WIDTH },
152280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_5_CHECKER_TYPE,
152281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_5_WIDTH },
152282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_6_CHECKER_TYPE,
152283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_6_WIDTH },
152284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_7_CHECKER_TYPE,
152285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_7_WIDTH },
152286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_8_CHECKER_TYPE,
152287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_8_WIDTH },
152288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_9_CHECKER_TYPE,
152289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_9_WIDTH },
152290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_10_CHECKER_TYPE,
152291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_10_WIDTH },
152292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_11_CHECKER_TYPE,
152293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_11_WIDTH },
152294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_12_CHECKER_TYPE,
152295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_12_WIDTH },
152296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_13_CHECKER_TYPE,
152297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_13_WIDTH },
152298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_14_CHECKER_TYPE,
152299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_14_WIDTH },
152300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_15_CHECKER_TYPE,
152301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_15_WIDTH },
152302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_16_CHECKER_TYPE,
152303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_16_WIDTH },
152304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_17_CHECKER_TYPE,
152305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_17_WIDTH },
152306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_18_CHECKER_TYPE,
152307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_18_WIDTH },
152308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_19_CHECKER_TYPE,
152309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_19_WIDTH },
152310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_20_CHECKER_TYPE,
152311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_20_WIDTH },
152312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_21_CHECKER_TYPE,
152313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_21_WIDTH },
152314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_22_CHECKER_TYPE,
152315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_22_WIDTH },
152316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_23_CHECKER_TYPE,
152317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_23_WIDTH },
152318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_24_CHECKER_TYPE,
152319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_24_WIDTH },
152320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_25_CHECKER_TYPE,
152321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_25_WIDTH },
152322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_26_CHECKER_TYPE,
152323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_26_WIDTH },
152324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_27_CHECKER_TYPE,
152325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_27_WIDTH },
152326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_28_CHECKER_TYPE,
152327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_28_WIDTH },
152328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_29_CHECKER_TYPE,
152329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_29_WIDTH },
152330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_30_CHECKER_TYPE,
152331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_30_WIDTH },
152332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_31_CHECKER_TYPE,
152333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_31_WIDTH },
152334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_32_CHECKER_TYPE,
152335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_32_WIDTH },
152336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_33_CHECKER_TYPE,
152337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_33_WIDTH },
152338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_34_CHECKER_TYPE,
152339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_34_WIDTH },
152340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_35_CHECKER_TYPE,
152341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_35_WIDTH },
152342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_36_CHECKER_TYPE,
152343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_36_WIDTH },
152344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_37_CHECKER_TYPE,
152345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_37_WIDTH },
152346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_38_CHECKER_TYPE,
152347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_38_WIDTH },
152348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_39_CHECKER_TYPE,
152349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_39_WIDTH },
152350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_40_CHECKER_TYPE,
152351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_40_WIDTH },
152352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_41_CHECKER_TYPE,
152353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_41_WIDTH },
152354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_42_CHECKER_TYPE,
152355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_42_WIDTH },
152356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_43_CHECKER_TYPE,
152357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_43_WIDTH },
152358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_44_CHECKER_TYPE,
152359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_44_WIDTH },
152360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_45_CHECKER_TYPE,
152361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_45_WIDTH },
152362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_46_CHECKER_TYPE,
152363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_46_WIDTH },
152364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_47_CHECKER_TYPE,
152365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_47_WIDTH },
152366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_48_CHECKER_TYPE,
152367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_48_WIDTH },
152368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_49_CHECKER_TYPE,
152369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_49_WIDTH },
152370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_50_CHECKER_TYPE,
152371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_50_WIDTH },
152372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_51_CHECKER_TYPE,
152373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_51_WIDTH },
152374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_52_CHECKER_TYPE,
152375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_52_WIDTH },
152376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_53_CHECKER_TYPE,
152377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_53_WIDTH },
152378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_54_CHECKER_TYPE,
152379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_54_WIDTH },
152380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_55_CHECKER_TYPE,
152381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_55_WIDTH },
152382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_56_CHECKER_TYPE,
152383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_56_WIDTH },
152384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_57_CHECKER_TYPE,
152385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_57_WIDTH },
152386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_58_CHECKER_TYPE,
152387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_58_WIDTH },
152388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_59_CHECKER_TYPE,
152389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_59_WIDTH },
152390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_60_CHECKER_TYPE,
152391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_60_WIDTH },
152392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_61_CHECKER_TYPE,
152393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_61_WIDTH },
152394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_62_CHECKER_TYPE,
152395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_62_WIDTH },
152396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_63_CHECKER_TYPE,
152397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_63_WIDTH },
152398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_64_CHECKER_TYPE,
152399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_64_WIDTH },
152400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_65_CHECKER_TYPE,
152401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_65_WIDTH },
152402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_66_CHECKER_TYPE,
152403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_66_WIDTH },
152404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_67_CHECKER_TYPE,
152405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_67_WIDTH },
152406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_68_CHECKER_TYPE,
152407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_68_WIDTH },
152408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_69_CHECKER_TYPE,
152409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_69_WIDTH },
152410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_70_CHECKER_TYPE,
152411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_70_WIDTH },
152412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_71_CHECKER_TYPE,
152413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_71_WIDTH },
152414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_72_CHECKER_TYPE,
152415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_72_WIDTH },
152416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_73_CHECKER_TYPE,
152417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_73_WIDTH },
152418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_74_CHECKER_TYPE,
152419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_74_WIDTH },
152420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_75_CHECKER_TYPE,
152421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_75_WIDTH },
152422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_76_CHECKER_TYPE,
152423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_76_WIDTH },
152424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_77_CHECKER_TYPE,
152425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_77_WIDTH },
152426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_78_CHECKER_TYPE,
152427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_78_WIDTH },
152428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_79_CHECKER_TYPE,
152429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_79_WIDTH },
152430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_80_CHECKER_TYPE,
152431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_80_WIDTH },
152432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_81_CHECKER_TYPE,
152433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_81_WIDTH },
152434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_82_CHECKER_TYPE,
152435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_82_WIDTH },
152436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_83_CHECKER_TYPE,
152437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_83_WIDTH },
152438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_84_CHECKER_TYPE,
152439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_84_WIDTH },
152440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_85_CHECKER_TYPE,
152441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_85_WIDTH },
152442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_86_CHECKER_TYPE,
152443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_86_WIDTH },
152444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_87_CHECKER_TYPE,
152445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_87_WIDTH },
152446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_88_CHECKER_TYPE,
152447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_88_WIDTH },
152448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_89_CHECKER_TYPE,
152449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_89_WIDTH },
152450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_90_CHECKER_TYPE,
152451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_90_WIDTH },
152452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_91_CHECKER_TYPE,
152453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_91_WIDTH },
152454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_92_CHECKER_TYPE,
152455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_92_WIDTH },
152456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_93_CHECKER_TYPE,
152457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_93_WIDTH },
152458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_94_CHECKER_TYPE,
152459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_94_WIDTH },
152460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_95_CHECKER_TYPE,
152461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_95_WIDTH },
152462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_96_CHECKER_TYPE,
152463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_96_WIDTH },
152464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_97_CHECKER_TYPE,
152465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_97_WIDTH },
152466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_98_CHECKER_TYPE,
152467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_98_WIDTH },
152468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_99_CHECKER_TYPE,
152469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_99_WIDTH },
152470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_100_CHECKER_TYPE,
152471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_100_WIDTH },
152472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_101_CHECKER_TYPE,
152473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_101_WIDTH },
152474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_102_CHECKER_TYPE,
152475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_102_WIDTH },
152476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_103_CHECKER_TYPE,
152477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_103_WIDTH },
152478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_104_CHECKER_TYPE,
152479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_104_WIDTH },
152480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_105_CHECKER_TYPE,
152481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_105_WIDTH },
152482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_106_CHECKER_TYPE,
152483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_106_WIDTH },
152484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_107_CHECKER_TYPE,
152485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_107_WIDTH },
152486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_108_CHECKER_TYPE,
152487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_108_WIDTH },
152488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_109_CHECKER_TYPE,
152489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_109_WIDTH },
152490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_110_CHECKER_TYPE,
152491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_110_WIDTH },
152492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_111_CHECKER_TYPE,
152493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_111_WIDTH },
152494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_112_CHECKER_TYPE,
152495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_112_WIDTH },
152496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_113_CHECKER_TYPE,
152497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_113_WIDTH },
152498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_114_CHECKER_TYPE,
152499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_114_WIDTH },
152500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_115_CHECKER_TYPE,
152501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_115_WIDTH },
152502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_116_CHECKER_TYPE,
152503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_116_WIDTH },
152504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_117_CHECKER_TYPE,
152505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_117_WIDTH },
152506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_118_CHECKER_TYPE,
152507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_118_WIDTH },
152508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_119_CHECKER_TYPE,
152509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_119_WIDTH },
152510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_120_CHECKER_TYPE,
152511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_120_WIDTH },
152512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_121_CHECKER_TYPE,
152513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_121_WIDTH },
152514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_122_CHECKER_TYPE,
152515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_122_WIDTH },
152516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_123_CHECKER_TYPE,
152517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_123_WIDTH },
152518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_124_CHECKER_TYPE,
152519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_124_WIDTH },
152520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_125_CHECKER_TYPE,
152521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_125_WIDTH },
152522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_126_CHECKER_TYPE,
152523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_126_WIDTH },
152524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_127_CHECKER_TYPE,
152525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_127_WIDTH },
152526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_128_CHECKER_TYPE,
152527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_128_WIDTH },
152528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_129_CHECKER_TYPE,
152529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_129_WIDTH },
152530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_130_CHECKER_TYPE,
152531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_130_WIDTH },
152532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_131_CHECKER_TYPE,
152533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_131_WIDTH },
152534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_132_CHECKER_TYPE,
152535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_132_WIDTH },
152536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_133_CHECKER_TYPE,
152537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_133_WIDTH },
152538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_134_CHECKER_TYPE,
152539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_134_WIDTH },
152540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_135_CHECKER_TYPE,
152541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_135_WIDTH },
152542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_136_CHECKER_TYPE,
152543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_136_WIDTH },
152544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_137_CHECKER_TYPE,
152545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_137_WIDTH },
152546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_138_CHECKER_TYPE,
152547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_138_WIDTH },
152548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_139_CHECKER_TYPE,
152549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_139_WIDTH },
152550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_140_CHECKER_TYPE,
152551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_140_WIDTH },
152552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_141_CHECKER_TYPE,
152553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_141_WIDTH },
152554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_142_CHECKER_TYPE,
152555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_142_WIDTH },
152556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_143_CHECKER_TYPE,
152557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_143_WIDTH },
152558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_144_CHECKER_TYPE,
152559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_144_WIDTH },
152560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_145_CHECKER_TYPE,
152561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_145_WIDTH },
152562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_146_CHECKER_TYPE,
152563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_146_WIDTH },
152564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_147_CHECKER_TYPE,
152565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_147_WIDTH },
152566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_148_CHECKER_TYPE,
152567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_148_WIDTH },
152568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_149_CHECKER_TYPE,
152569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_149_WIDTH },
152570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_150_CHECKER_TYPE,
152571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_150_WIDTH },
152572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_151_CHECKER_TYPE,
152573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_151_WIDTH },
152574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_152_CHECKER_TYPE,
152575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_152_WIDTH },
152576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_153_CHECKER_TYPE,
152577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_153_WIDTH },
152578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_154_CHECKER_TYPE,
152579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_154_WIDTH },
152580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_155_CHECKER_TYPE,
152581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_155_WIDTH },
152582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_156_CHECKER_TYPE,
152583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_156_WIDTH },
152584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_157_CHECKER_TYPE,
152585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_157_WIDTH },
152586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_158_CHECKER_TYPE,
152587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_158_WIDTH },
152588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_159_CHECKER_TYPE,
152589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_159_WIDTH },
152590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_160_CHECKER_TYPE,
152591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_160_WIDTH },
152592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_161_CHECKER_TYPE,
152593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_161_WIDTH },
152594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_162_CHECKER_TYPE,
152595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_162_WIDTH },
152596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_163_CHECKER_TYPE,
152597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_163_WIDTH },
152598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_164_CHECKER_TYPE,
152599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_164_WIDTH },
152600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_165_CHECKER_TYPE,
152601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_165_WIDTH },
152602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_166_CHECKER_TYPE,
152603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_166_WIDTH },
152604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_167_CHECKER_TYPE,
152605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_167_WIDTH },
152606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_168_CHECKER_TYPE,
152607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_168_WIDTH },
152608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_169_CHECKER_TYPE,
152609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_169_WIDTH },
152610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_170_CHECKER_TYPE,
152611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_170_WIDTH },
152612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_171_CHECKER_TYPE,
152613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_171_WIDTH },
152614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_172_CHECKER_TYPE,
152615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_172_WIDTH },
152616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_173_CHECKER_TYPE,
152617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_173_WIDTH },
152618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_174_CHECKER_TYPE,
152619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_174_WIDTH },
152620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_175_CHECKER_TYPE,
152621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_175_WIDTH },
152622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_176_CHECKER_TYPE,
152623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_176_WIDTH },
152624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_177_CHECKER_TYPE,
152625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_177_WIDTH },
152626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_178_CHECKER_TYPE,
152627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_178_WIDTH },
152628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_179_CHECKER_TYPE,
152629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_179_WIDTH },
152630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_180_CHECKER_TYPE,
152631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_180_WIDTH },
152632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_181_CHECKER_TYPE,
152633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_181_WIDTH },
152634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_182_CHECKER_TYPE,
152635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_182_WIDTH },
152636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_183_CHECKER_TYPE,
152637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_183_WIDTH },
152638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_184_CHECKER_TYPE,
152639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_184_WIDTH },
152640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_185_CHECKER_TYPE,
152641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_185_WIDTH },
152642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_186_CHECKER_TYPE,
152643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_186_WIDTH },
152644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_187_CHECKER_TYPE,
152645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_187_WIDTH },
152646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_188_CHECKER_TYPE,
152647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_188_WIDTH },
152648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_189_CHECKER_TYPE,
152649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_189_WIDTH },
152650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_190_CHECKER_TYPE,
152651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_190_WIDTH },
152652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_191_CHECKER_TYPE,
152653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_191_WIDTH },
152654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_192_CHECKER_TYPE,
152655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_192_WIDTH },
152656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_193_CHECKER_TYPE,
152657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_193_WIDTH },
152658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_194_CHECKER_TYPE,
152659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_194_WIDTH },
152660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_195_CHECKER_TYPE,
152661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_195_WIDTH },
152662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_196_CHECKER_TYPE,
152663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_196_WIDTH },
152664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_197_CHECKER_TYPE,
152665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_197_WIDTH },
152666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_198_CHECKER_TYPE,
152667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_198_WIDTH },
152668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_199_CHECKER_TYPE,
152669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_199_WIDTH },
152670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_200_CHECKER_TYPE,
152671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_200_WIDTH },
152672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_201_CHECKER_TYPE,
152673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_201_WIDTH },
152674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_202_CHECKER_TYPE,
152675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_202_WIDTH },
152676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_203_CHECKER_TYPE,
152677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_203_WIDTH },
152678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_204_CHECKER_TYPE,
152679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_204_WIDTH },
152680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_205_CHECKER_TYPE,
152681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_205_WIDTH },
152682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_206_CHECKER_TYPE,
152683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_206_WIDTH },
152684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_207_CHECKER_TYPE,
152685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_207_WIDTH },
152686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_208_CHECKER_TYPE,
152687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_208_WIDTH },
152688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_209_CHECKER_TYPE,
152689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_209_WIDTH },
152690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_210_CHECKER_TYPE,
152691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_210_WIDTH },
152692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_211_CHECKER_TYPE,
152693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_211_WIDTH },
152694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_212_CHECKER_TYPE,
152695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_212_WIDTH },
152696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_213_CHECKER_TYPE,
152697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_213_WIDTH },
152698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_214_CHECKER_TYPE,
152699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_214_WIDTH },
152700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_215_CHECKER_TYPE,
152701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_215_WIDTH },
152702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_216_CHECKER_TYPE,
152703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_216_WIDTH },
152704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_217_CHECKER_TYPE,
152705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_217_WIDTH },
152706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_218_CHECKER_TYPE,
152707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_218_WIDTH },
152708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_219_CHECKER_TYPE,
152709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_219_WIDTH },
152710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_220_CHECKER_TYPE,
152711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_220_WIDTH },
152712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_221_CHECKER_TYPE,
152713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_221_WIDTH },
152714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_222_CHECKER_TYPE,
152715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_222_WIDTH },
152716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_223_CHECKER_TYPE,
152717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_223_WIDTH },
152718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_224_CHECKER_TYPE,
152719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_224_WIDTH },
152720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_225_CHECKER_TYPE,
152721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_225_WIDTH },
152722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_226_CHECKER_TYPE,
152723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_226_WIDTH },
152724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_227_CHECKER_TYPE,
152725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_227_WIDTH },
152726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_228_CHECKER_TYPE,
152727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_228_WIDTH },
152728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_229_CHECKER_TYPE,
152729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_229_WIDTH },
152730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_230_CHECKER_TYPE,
152731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_230_WIDTH },
152732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_231_CHECKER_TYPE,
152733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_231_WIDTH },
152734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_232_CHECKER_TYPE,
152735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_232_WIDTH },
152736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_233_CHECKER_TYPE,
152737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_233_WIDTH },
152738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_234_CHECKER_TYPE,
152739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_234_WIDTH },
152740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_235_CHECKER_TYPE,
152741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_235_WIDTH },
152742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_236_CHECKER_TYPE,
152743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_236_WIDTH },
152744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_237_CHECKER_TYPE,
152745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_237_WIDTH },
152746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_238_CHECKER_TYPE,
152747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_238_WIDTH },
152748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_239_CHECKER_TYPE,
152749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_239_WIDTH },
152750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_240_CHECKER_TYPE,
152751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_240_WIDTH },
152752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_241_CHECKER_TYPE,
152753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_241_WIDTH },
152754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_242_CHECKER_TYPE,
152755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_242_WIDTH },
152756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_243_CHECKER_TYPE,
152757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_243_WIDTH },
152758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_244_CHECKER_TYPE,
152759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_244_WIDTH },
152760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_245_CHECKER_TYPE,
152761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_245_WIDTH },
152762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_246_CHECKER_TYPE,
152763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_246_WIDTH },
152764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_247_CHECKER_TYPE,
152765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_247_WIDTH },
152766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_248_CHECKER_TYPE,
152767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_248_WIDTH },
152768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_249_CHECKER_TYPE,
152769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_249_WIDTH },
152770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_250_CHECKER_TYPE,
152771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_250_WIDTH },
152772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_251_CHECKER_TYPE,
152773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_251_WIDTH },
152774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_252_CHECKER_TYPE,
152775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_252_WIDTH },
152776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_253_CHECKER_TYPE,
152777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_253_WIDTH },
152778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_254_CHECKER_TYPE,
152779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_254_WIDTH },
152780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_255_CHECKER_TYPE,
152781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_GROUP_255_WIDTH },
152782 };
152783 
152789 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_MAX_NUM_CHECKERS] =
152790 {
152791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_0_CHECKER_TYPE,
152792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_0_WIDTH },
152793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_1_CHECKER_TYPE,
152794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_1_WIDTH },
152795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_2_CHECKER_TYPE,
152796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_2_WIDTH },
152797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_3_CHECKER_TYPE,
152798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_3_WIDTH },
152799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_4_CHECKER_TYPE,
152800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_4_WIDTH },
152801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_5_CHECKER_TYPE,
152802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_5_WIDTH },
152803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_6_CHECKER_TYPE,
152804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_6_WIDTH },
152805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_7_CHECKER_TYPE,
152806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_7_WIDTH },
152807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_8_CHECKER_TYPE,
152808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_8_WIDTH },
152809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_9_CHECKER_TYPE,
152810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_9_WIDTH },
152811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_10_CHECKER_TYPE,
152812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_10_WIDTH },
152813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_11_CHECKER_TYPE,
152814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_11_WIDTH },
152815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_12_CHECKER_TYPE,
152816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_12_WIDTH },
152817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_13_CHECKER_TYPE,
152818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_13_WIDTH },
152819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_14_CHECKER_TYPE,
152820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_14_WIDTH },
152821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_15_CHECKER_TYPE,
152822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_15_WIDTH },
152823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_16_CHECKER_TYPE,
152824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_16_WIDTH },
152825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_17_CHECKER_TYPE,
152826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_17_WIDTH },
152827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_18_CHECKER_TYPE,
152828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_18_WIDTH },
152829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_19_CHECKER_TYPE,
152830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_19_WIDTH },
152831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_20_CHECKER_TYPE,
152832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_20_WIDTH },
152833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_21_CHECKER_TYPE,
152834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_21_WIDTH },
152835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_22_CHECKER_TYPE,
152836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_22_WIDTH },
152837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_23_CHECKER_TYPE,
152838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_23_WIDTH },
152839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_24_CHECKER_TYPE,
152840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_24_WIDTH },
152841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_25_CHECKER_TYPE,
152842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_25_WIDTH },
152843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_26_CHECKER_TYPE,
152844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_26_WIDTH },
152845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_27_CHECKER_TYPE,
152846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_27_WIDTH },
152847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_28_CHECKER_TYPE,
152848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_28_WIDTH },
152849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_29_CHECKER_TYPE,
152850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_29_WIDTH },
152851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_30_CHECKER_TYPE,
152852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_30_WIDTH },
152853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_31_CHECKER_TYPE,
152854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_31_WIDTH },
152855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_32_CHECKER_TYPE,
152856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_32_WIDTH },
152857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_33_CHECKER_TYPE,
152858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_33_WIDTH },
152859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_34_CHECKER_TYPE,
152860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_34_WIDTH },
152861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_35_CHECKER_TYPE,
152862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_35_WIDTH },
152863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_36_CHECKER_TYPE,
152864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_36_WIDTH },
152865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_37_CHECKER_TYPE,
152866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_37_WIDTH },
152867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_38_CHECKER_TYPE,
152868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_38_WIDTH },
152869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_39_CHECKER_TYPE,
152870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_39_WIDTH },
152871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_40_CHECKER_TYPE,
152872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_40_WIDTH },
152873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_41_CHECKER_TYPE,
152874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_41_WIDTH },
152875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_42_CHECKER_TYPE,
152876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_42_WIDTH },
152877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_43_CHECKER_TYPE,
152878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_43_WIDTH },
152879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_44_CHECKER_TYPE,
152880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_44_WIDTH },
152881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_45_CHECKER_TYPE,
152882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_45_WIDTH },
152883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_46_CHECKER_TYPE,
152884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_46_WIDTH },
152885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_47_CHECKER_TYPE,
152886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_47_WIDTH },
152887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_48_CHECKER_TYPE,
152888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_48_WIDTH },
152889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_49_CHECKER_TYPE,
152890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_49_WIDTH },
152891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_50_CHECKER_TYPE,
152892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_50_WIDTH },
152893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_51_CHECKER_TYPE,
152894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_51_WIDTH },
152895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_52_CHECKER_TYPE,
152896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_52_WIDTH },
152897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_53_CHECKER_TYPE,
152898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_53_WIDTH },
152899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_54_CHECKER_TYPE,
152900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_54_WIDTH },
152901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_55_CHECKER_TYPE,
152902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_55_WIDTH },
152903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_56_CHECKER_TYPE,
152904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_56_WIDTH },
152905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_57_CHECKER_TYPE,
152906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_57_WIDTH },
152907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_58_CHECKER_TYPE,
152908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_58_WIDTH },
152909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_59_CHECKER_TYPE,
152910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_59_WIDTH },
152911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_60_CHECKER_TYPE,
152912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_60_WIDTH },
152913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_61_CHECKER_TYPE,
152914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_61_WIDTH },
152915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_62_CHECKER_TYPE,
152916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_62_WIDTH },
152917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_63_CHECKER_TYPE,
152918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_63_WIDTH },
152919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_64_CHECKER_TYPE,
152920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_64_WIDTH },
152921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_65_CHECKER_TYPE,
152922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_65_WIDTH },
152923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_66_CHECKER_TYPE,
152924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_66_WIDTH },
152925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_67_CHECKER_TYPE,
152926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_67_WIDTH },
152927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_68_CHECKER_TYPE,
152928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_68_WIDTH },
152929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_69_CHECKER_TYPE,
152930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_69_WIDTH },
152931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_70_CHECKER_TYPE,
152932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_70_WIDTH },
152933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_71_CHECKER_TYPE,
152934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_71_WIDTH },
152935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_72_CHECKER_TYPE,
152936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_72_WIDTH },
152937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_73_CHECKER_TYPE,
152938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_73_WIDTH },
152939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_74_CHECKER_TYPE,
152940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_74_WIDTH },
152941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_75_CHECKER_TYPE,
152942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_75_WIDTH },
152943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_76_CHECKER_TYPE,
152944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_76_WIDTH },
152945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_77_CHECKER_TYPE,
152946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_77_WIDTH },
152947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_78_CHECKER_TYPE,
152948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_78_WIDTH },
152949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_79_CHECKER_TYPE,
152950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_79_WIDTH },
152951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_80_CHECKER_TYPE,
152952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_80_WIDTH },
152953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_81_CHECKER_TYPE,
152954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_81_WIDTH },
152955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_82_CHECKER_TYPE,
152956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_82_WIDTH },
152957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_83_CHECKER_TYPE,
152958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_83_WIDTH },
152959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_84_CHECKER_TYPE,
152960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_84_WIDTH },
152961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_85_CHECKER_TYPE,
152962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_85_WIDTH },
152963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_86_CHECKER_TYPE,
152964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_86_WIDTH },
152965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_87_CHECKER_TYPE,
152966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_87_WIDTH },
152967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_88_CHECKER_TYPE,
152968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_88_WIDTH },
152969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_89_CHECKER_TYPE,
152970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_89_WIDTH },
152971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_90_CHECKER_TYPE,
152972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_90_WIDTH },
152973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_91_CHECKER_TYPE,
152974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_91_WIDTH },
152975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_92_CHECKER_TYPE,
152976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_92_WIDTH },
152977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_93_CHECKER_TYPE,
152978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_93_WIDTH },
152979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_94_CHECKER_TYPE,
152980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_94_WIDTH },
152981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_95_CHECKER_TYPE,
152982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_95_WIDTH },
152983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_96_CHECKER_TYPE,
152984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_96_WIDTH },
152985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_97_CHECKER_TYPE,
152986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_97_WIDTH },
152987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_98_CHECKER_TYPE,
152988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_98_WIDTH },
152989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_99_CHECKER_TYPE,
152990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_99_WIDTH },
152991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_100_CHECKER_TYPE,
152992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_100_WIDTH },
152993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_101_CHECKER_TYPE,
152994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_101_WIDTH },
152995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_102_CHECKER_TYPE,
152996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_102_WIDTH },
152997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_103_CHECKER_TYPE,
152998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_103_WIDTH },
152999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_104_CHECKER_TYPE,
153000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_104_WIDTH },
153001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_105_CHECKER_TYPE,
153002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_105_WIDTH },
153003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_106_CHECKER_TYPE,
153004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_106_WIDTH },
153005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_107_CHECKER_TYPE,
153006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_107_WIDTH },
153007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_108_CHECKER_TYPE,
153008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_108_WIDTH },
153009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_109_CHECKER_TYPE,
153010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_109_WIDTH },
153011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_110_CHECKER_TYPE,
153012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_110_WIDTH },
153013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_111_CHECKER_TYPE,
153014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_111_WIDTH },
153015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_112_CHECKER_TYPE,
153016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_112_WIDTH },
153017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_113_CHECKER_TYPE,
153018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_113_WIDTH },
153019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_114_CHECKER_TYPE,
153020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_114_WIDTH },
153021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_115_CHECKER_TYPE,
153022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_115_WIDTH },
153023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_116_CHECKER_TYPE,
153024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_116_WIDTH },
153025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_117_CHECKER_TYPE,
153026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_117_WIDTH },
153027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_118_CHECKER_TYPE,
153028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_118_WIDTH },
153029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_119_CHECKER_TYPE,
153030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_119_WIDTH },
153031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_120_CHECKER_TYPE,
153032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_120_WIDTH },
153033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_121_CHECKER_TYPE,
153034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_121_WIDTH },
153035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_122_CHECKER_TYPE,
153036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_122_WIDTH },
153037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_123_CHECKER_TYPE,
153038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_123_WIDTH },
153039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_124_CHECKER_TYPE,
153040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_124_WIDTH },
153041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_125_CHECKER_TYPE,
153042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_125_WIDTH },
153043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_126_CHECKER_TYPE,
153044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_126_WIDTH },
153045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_127_CHECKER_TYPE,
153046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_127_WIDTH },
153047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_128_CHECKER_TYPE,
153048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_128_WIDTH },
153049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_129_CHECKER_TYPE,
153050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_129_WIDTH },
153051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_130_CHECKER_TYPE,
153052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_130_WIDTH },
153053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_131_CHECKER_TYPE,
153054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_131_WIDTH },
153055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_132_CHECKER_TYPE,
153056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_132_WIDTH },
153057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_133_CHECKER_TYPE,
153058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_133_WIDTH },
153059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_134_CHECKER_TYPE,
153060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_134_WIDTH },
153061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_135_CHECKER_TYPE,
153062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_135_WIDTH },
153063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_136_CHECKER_TYPE,
153064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_136_WIDTH },
153065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_137_CHECKER_TYPE,
153066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_137_WIDTH },
153067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_138_CHECKER_TYPE,
153068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_138_WIDTH },
153069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_139_CHECKER_TYPE,
153070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_139_WIDTH },
153071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_140_CHECKER_TYPE,
153072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_140_WIDTH },
153073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_141_CHECKER_TYPE,
153074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_141_WIDTH },
153075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_142_CHECKER_TYPE,
153076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_142_WIDTH },
153077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_143_CHECKER_TYPE,
153078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_143_WIDTH },
153079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_144_CHECKER_TYPE,
153080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_144_WIDTH },
153081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_145_CHECKER_TYPE,
153082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_145_WIDTH },
153083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_146_CHECKER_TYPE,
153084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_146_WIDTH },
153085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_147_CHECKER_TYPE,
153086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_147_WIDTH },
153087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_148_CHECKER_TYPE,
153088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_148_WIDTH },
153089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_149_CHECKER_TYPE,
153090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_149_WIDTH },
153091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_150_CHECKER_TYPE,
153092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_150_WIDTH },
153093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_151_CHECKER_TYPE,
153094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_151_WIDTH },
153095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_152_CHECKER_TYPE,
153096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_152_WIDTH },
153097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_153_CHECKER_TYPE,
153098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_153_WIDTH },
153099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_154_CHECKER_TYPE,
153100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_154_WIDTH },
153101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_155_CHECKER_TYPE,
153102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_155_WIDTH },
153103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_156_CHECKER_TYPE,
153104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_156_WIDTH },
153105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_157_CHECKER_TYPE,
153106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_157_WIDTH },
153107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_158_CHECKER_TYPE,
153108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_158_WIDTH },
153109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_159_CHECKER_TYPE,
153110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_159_WIDTH },
153111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_160_CHECKER_TYPE,
153112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_160_WIDTH },
153113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_161_CHECKER_TYPE,
153114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_161_WIDTH },
153115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_162_CHECKER_TYPE,
153116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_162_WIDTH },
153117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_163_CHECKER_TYPE,
153118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_163_WIDTH },
153119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_164_CHECKER_TYPE,
153120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_164_WIDTH },
153121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_165_CHECKER_TYPE,
153122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_165_WIDTH },
153123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_166_CHECKER_TYPE,
153124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_166_WIDTH },
153125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_167_CHECKER_TYPE,
153126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_167_WIDTH },
153127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_168_CHECKER_TYPE,
153128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_168_WIDTH },
153129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_169_CHECKER_TYPE,
153130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_169_WIDTH },
153131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_170_CHECKER_TYPE,
153132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_170_WIDTH },
153133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_171_CHECKER_TYPE,
153134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_171_WIDTH },
153135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_172_CHECKER_TYPE,
153136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_172_WIDTH },
153137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_173_CHECKER_TYPE,
153138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_173_WIDTH },
153139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_174_CHECKER_TYPE,
153140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_174_WIDTH },
153141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_175_CHECKER_TYPE,
153142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_175_WIDTH },
153143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_176_CHECKER_TYPE,
153144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_176_WIDTH },
153145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_177_CHECKER_TYPE,
153146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_177_WIDTH },
153147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_178_CHECKER_TYPE,
153148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_178_WIDTH },
153149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_179_CHECKER_TYPE,
153150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_179_WIDTH },
153151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_180_CHECKER_TYPE,
153152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_180_WIDTH },
153153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_181_CHECKER_TYPE,
153154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_181_WIDTH },
153155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_182_CHECKER_TYPE,
153156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_182_WIDTH },
153157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_183_CHECKER_TYPE,
153158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_183_WIDTH },
153159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_184_CHECKER_TYPE,
153160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_184_WIDTH },
153161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_185_CHECKER_TYPE,
153162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_185_WIDTH },
153163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_186_CHECKER_TYPE,
153164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_186_WIDTH },
153165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_187_CHECKER_TYPE,
153166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_187_WIDTH },
153167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_188_CHECKER_TYPE,
153168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_188_WIDTH },
153169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_189_CHECKER_TYPE,
153170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_189_WIDTH },
153171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_190_CHECKER_TYPE,
153172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_190_WIDTH },
153173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_191_CHECKER_TYPE,
153174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_191_WIDTH },
153175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_192_CHECKER_TYPE,
153176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_192_WIDTH },
153177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_193_CHECKER_TYPE,
153178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_193_WIDTH },
153179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_194_CHECKER_TYPE,
153180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_194_WIDTH },
153181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_195_CHECKER_TYPE,
153182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_195_WIDTH },
153183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_196_CHECKER_TYPE,
153184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_196_WIDTH },
153185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_197_CHECKER_TYPE,
153186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_197_WIDTH },
153187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_198_CHECKER_TYPE,
153188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_198_WIDTH },
153189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_199_CHECKER_TYPE,
153190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_199_WIDTH },
153191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_200_CHECKER_TYPE,
153192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_200_WIDTH },
153193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_201_CHECKER_TYPE,
153194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_201_WIDTH },
153195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_202_CHECKER_TYPE,
153196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_202_WIDTH },
153197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_203_CHECKER_TYPE,
153198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_203_WIDTH },
153199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_204_CHECKER_TYPE,
153200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_204_WIDTH },
153201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_205_CHECKER_TYPE,
153202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_205_WIDTH },
153203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_206_CHECKER_TYPE,
153204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_206_WIDTH },
153205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_207_CHECKER_TYPE,
153206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_207_WIDTH },
153207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_208_CHECKER_TYPE,
153208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_208_WIDTH },
153209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_209_CHECKER_TYPE,
153210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_209_WIDTH },
153211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_210_CHECKER_TYPE,
153212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_210_WIDTH },
153213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_211_CHECKER_TYPE,
153214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_211_WIDTH },
153215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_212_CHECKER_TYPE,
153216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_212_WIDTH },
153217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_213_CHECKER_TYPE,
153218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_213_WIDTH },
153219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_214_CHECKER_TYPE,
153220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_214_WIDTH },
153221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_215_CHECKER_TYPE,
153222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_215_WIDTH },
153223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_216_CHECKER_TYPE,
153224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_216_WIDTH },
153225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_217_CHECKER_TYPE,
153226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_217_WIDTH },
153227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_218_CHECKER_TYPE,
153228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_218_WIDTH },
153229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_219_CHECKER_TYPE,
153230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_219_WIDTH },
153231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_220_CHECKER_TYPE,
153232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_220_WIDTH },
153233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_221_CHECKER_TYPE,
153234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_221_WIDTH },
153235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_222_CHECKER_TYPE,
153236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_222_WIDTH },
153237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_223_CHECKER_TYPE,
153238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_223_WIDTH },
153239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_224_CHECKER_TYPE,
153240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_224_WIDTH },
153241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_225_CHECKER_TYPE,
153242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_225_WIDTH },
153243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_226_CHECKER_TYPE,
153244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_226_WIDTH },
153245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_227_CHECKER_TYPE,
153246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_227_WIDTH },
153247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_228_CHECKER_TYPE,
153248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_228_WIDTH },
153249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_229_CHECKER_TYPE,
153250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_229_WIDTH },
153251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_230_CHECKER_TYPE,
153252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_230_WIDTH },
153253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_231_CHECKER_TYPE,
153254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_231_WIDTH },
153255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_232_CHECKER_TYPE,
153256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_232_WIDTH },
153257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_233_CHECKER_TYPE,
153258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_233_WIDTH },
153259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_234_CHECKER_TYPE,
153260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_234_WIDTH },
153261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_235_CHECKER_TYPE,
153262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_235_WIDTH },
153263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_236_CHECKER_TYPE,
153264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_236_WIDTH },
153265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_237_CHECKER_TYPE,
153266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_237_WIDTH },
153267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_238_CHECKER_TYPE,
153268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_238_WIDTH },
153269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_239_CHECKER_TYPE,
153270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_239_WIDTH },
153271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_240_CHECKER_TYPE,
153272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_240_WIDTH },
153273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_241_CHECKER_TYPE,
153274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_241_WIDTH },
153275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_242_CHECKER_TYPE,
153276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_242_WIDTH },
153277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_243_CHECKER_TYPE,
153278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_243_WIDTH },
153279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_244_CHECKER_TYPE,
153280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_244_WIDTH },
153281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_245_CHECKER_TYPE,
153282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_245_WIDTH },
153283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_246_CHECKER_TYPE,
153284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_246_WIDTH },
153285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_247_CHECKER_TYPE,
153286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_247_WIDTH },
153287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_248_CHECKER_TYPE,
153288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_248_WIDTH },
153289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_249_CHECKER_TYPE,
153290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_249_WIDTH },
153291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_250_CHECKER_TYPE,
153292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_250_WIDTH },
153293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_251_CHECKER_TYPE,
153294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_251_WIDTH },
153295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_252_CHECKER_TYPE,
153296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_252_WIDTH },
153297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_253_CHECKER_TYPE,
153298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_253_WIDTH },
153299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_254_CHECKER_TYPE,
153300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_254_WIDTH },
153301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_255_CHECKER_TYPE,
153302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_GROUP_255_WIDTH },
153303 };
153304 
153310 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_MAX_NUM_CHECKERS] =
153311 {
153312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_0_CHECKER_TYPE,
153313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_0_WIDTH },
153314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_1_CHECKER_TYPE,
153315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_1_WIDTH },
153316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_2_CHECKER_TYPE,
153317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_2_WIDTH },
153318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_3_CHECKER_TYPE,
153319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_3_WIDTH },
153320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_4_CHECKER_TYPE,
153321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_4_WIDTH },
153322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_5_CHECKER_TYPE,
153323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_5_WIDTH },
153324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_6_CHECKER_TYPE,
153325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_6_WIDTH },
153326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_7_CHECKER_TYPE,
153327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_7_WIDTH },
153328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_8_CHECKER_TYPE,
153329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_8_WIDTH },
153330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_9_CHECKER_TYPE,
153331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_9_WIDTH },
153332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_10_CHECKER_TYPE,
153333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_10_WIDTH },
153334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_11_CHECKER_TYPE,
153335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_11_WIDTH },
153336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_12_CHECKER_TYPE,
153337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_12_WIDTH },
153338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_13_CHECKER_TYPE,
153339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_13_WIDTH },
153340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_14_CHECKER_TYPE,
153341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_14_WIDTH },
153342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_15_CHECKER_TYPE,
153343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_15_WIDTH },
153344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_16_CHECKER_TYPE,
153345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_16_WIDTH },
153346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_17_CHECKER_TYPE,
153347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_17_WIDTH },
153348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_18_CHECKER_TYPE,
153349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_18_WIDTH },
153350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_19_CHECKER_TYPE,
153351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_19_WIDTH },
153352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_20_CHECKER_TYPE,
153353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_20_WIDTH },
153354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_21_CHECKER_TYPE,
153355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_21_WIDTH },
153356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_22_CHECKER_TYPE,
153357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_22_WIDTH },
153358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_23_CHECKER_TYPE,
153359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_23_WIDTH },
153360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_24_CHECKER_TYPE,
153361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_24_WIDTH },
153362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_25_CHECKER_TYPE,
153363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_25_WIDTH },
153364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_26_CHECKER_TYPE,
153365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_26_WIDTH },
153366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_27_CHECKER_TYPE,
153367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_27_WIDTH },
153368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_28_CHECKER_TYPE,
153369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_28_WIDTH },
153370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_29_CHECKER_TYPE,
153371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_29_WIDTH },
153372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_30_CHECKER_TYPE,
153373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_30_WIDTH },
153374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_31_CHECKER_TYPE,
153375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_31_WIDTH },
153376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_32_CHECKER_TYPE,
153377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_32_WIDTH },
153378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_33_CHECKER_TYPE,
153379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_33_WIDTH },
153380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_34_CHECKER_TYPE,
153381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_34_WIDTH },
153382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_35_CHECKER_TYPE,
153383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_35_WIDTH },
153384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_36_CHECKER_TYPE,
153385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_36_WIDTH },
153386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_37_CHECKER_TYPE,
153387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_37_WIDTH },
153388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_38_CHECKER_TYPE,
153389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_38_WIDTH },
153390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_39_CHECKER_TYPE,
153391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_39_WIDTH },
153392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_40_CHECKER_TYPE,
153393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_40_WIDTH },
153394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_41_CHECKER_TYPE,
153395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_41_WIDTH },
153396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_42_CHECKER_TYPE,
153397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_42_WIDTH },
153398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_43_CHECKER_TYPE,
153399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_43_WIDTH },
153400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_44_CHECKER_TYPE,
153401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_44_WIDTH },
153402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_45_CHECKER_TYPE,
153403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_45_WIDTH },
153404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_46_CHECKER_TYPE,
153405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_46_WIDTH },
153406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_47_CHECKER_TYPE,
153407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_47_WIDTH },
153408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_48_CHECKER_TYPE,
153409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_48_WIDTH },
153410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_49_CHECKER_TYPE,
153411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_49_WIDTH },
153412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_50_CHECKER_TYPE,
153413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_50_WIDTH },
153414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_51_CHECKER_TYPE,
153415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_51_WIDTH },
153416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_52_CHECKER_TYPE,
153417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_52_WIDTH },
153418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_53_CHECKER_TYPE,
153419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_53_WIDTH },
153420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_54_CHECKER_TYPE,
153421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_54_WIDTH },
153422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_55_CHECKER_TYPE,
153423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_55_WIDTH },
153424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_56_CHECKER_TYPE,
153425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_56_WIDTH },
153426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_57_CHECKER_TYPE,
153427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_57_WIDTH },
153428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_58_CHECKER_TYPE,
153429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_58_WIDTH },
153430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_59_CHECKER_TYPE,
153431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_59_WIDTH },
153432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_60_CHECKER_TYPE,
153433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_60_WIDTH },
153434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_61_CHECKER_TYPE,
153435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_61_WIDTH },
153436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_62_CHECKER_TYPE,
153437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_62_WIDTH },
153438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_63_CHECKER_TYPE,
153439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_63_WIDTH },
153440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_64_CHECKER_TYPE,
153441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_64_WIDTH },
153442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_65_CHECKER_TYPE,
153443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_65_WIDTH },
153444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_66_CHECKER_TYPE,
153445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_66_WIDTH },
153446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_67_CHECKER_TYPE,
153447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_67_WIDTH },
153448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_68_CHECKER_TYPE,
153449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_68_WIDTH },
153450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_69_CHECKER_TYPE,
153451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_69_WIDTH },
153452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_70_CHECKER_TYPE,
153453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_70_WIDTH },
153454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_71_CHECKER_TYPE,
153455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_71_WIDTH },
153456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_72_CHECKER_TYPE,
153457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_72_WIDTH },
153458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_73_CHECKER_TYPE,
153459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_73_WIDTH },
153460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_74_CHECKER_TYPE,
153461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_74_WIDTH },
153462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_75_CHECKER_TYPE,
153463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_75_WIDTH },
153464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_76_CHECKER_TYPE,
153465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_76_WIDTH },
153466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_77_CHECKER_TYPE,
153467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_77_WIDTH },
153468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_78_CHECKER_TYPE,
153469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_78_WIDTH },
153470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_79_CHECKER_TYPE,
153471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_79_WIDTH },
153472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_80_CHECKER_TYPE,
153473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_80_WIDTH },
153474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_81_CHECKER_TYPE,
153475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_81_WIDTH },
153476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_82_CHECKER_TYPE,
153477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_82_WIDTH },
153478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_83_CHECKER_TYPE,
153479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_83_WIDTH },
153480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_84_CHECKER_TYPE,
153481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_84_WIDTH },
153482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_85_CHECKER_TYPE,
153483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_85_WIDTH },
153484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_86_CHECKER_TYPE,
153485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_86_WIDTH },
153486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_87_CHECKER_TYPE,
153487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_87_WIDTH },
153488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_88_CHECKER_TYPE,
153489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_88_WIDTH },
153490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_89_CHECKER_TYPE,
153491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_89_WIDTH },
153492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_90_CHECKER_TYPE,
153493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_90_WIDTH },
153494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_91_CHECKER_TYPE,
153495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_91_WIDTH },
153496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_92_CHECKER_TYPE,
153497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_92_WIDTH },
153498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_93_CHECKER_TYPE,
153499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_93_WIDTH },
153500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_94_CHECKER_TYPE,
153501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_94_WIDTH },
153502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_95_CHECKER_TYPE,
153503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_95_WIDTH },
153504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_96_CHECKER_TYPE,
153505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_96_WIDTH },
153506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_97_CHECKER_TYPE,
153507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_97_WIDTH },
153508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_98_CHECKER_TYPE,
153509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_98_WIDTH },
153510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_99_CHECKER_TYPE,
153511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_99_WIDTH },
153512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_100_CHECKER_TYPE,
153513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_100_WIDTH },
153514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_101_CHECKER_TYPE,
153515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_101_WIDTH },
153516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_102_CHECKER_TYPE,
153517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_102_WIDTH },
153518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_103_CHECKER_TYPE,
153519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_103_WIDTH },
153520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_104_CHECKER_TYPE,
153521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_104_WIDTH },
153522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_105_CHECKER_TYPE,
153523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_105_WIDTH },
153524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_106_CHECKER_TYPE,
153525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_106_WIDTH },
153526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_107_CHECKER_TYPE,
153527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_107_WIDTH },
153528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_108_CHECKER_TYPE,
153529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_108_WIDTH },
153530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_109_CHECKER_TYPE,
153531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_109_WIDTH },
153532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_110_CHECKER_TYPE,
153533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_110_WIDTH },
153534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_111_CHECKER_TYPE,
153535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_111_WIDTH },
153536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_112_CHECKER_TYPE,
153537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_112_WIDTH },
153538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_113_CHECKER_TYPE,
153539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_113_WIDTH },
153540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_114_CHECKER_TYPE,
153541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_114_WIDTH },
153542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_115_CHECKER_TYPE,
153543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_115_WIDTH },
153544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_116_CHECKER_TYPE,
153545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_116_WIDTH },
153546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_117_CHECKER_TYPE,
153547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_117_WIDTH },
153548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_118_CHECKER_TYPE,
153549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_118_WIDTH },
153550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_119_CHECKER_TYPE,
153551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_119_WIDTH },
153552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_120_CHECKER_TYPE,
153553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_120_WIDTH },
153554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_121_CHECKER_TYPE,
153555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_121_WIDTH },
153556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_122_CHECKER_TYPE,
153557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_122_WIDTH },
153558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_123_CHECKER_TYPE,
153559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_123_WIDTH },
153560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_124_CHECKER_TYPE,
153561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_124_WIDTH },
153562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_125_CHECKER_TYPE,
153563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_125_WIDTH },
153564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_126_CHECKER_TYPE,
153565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_126_WIDTH },
153566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_127_CHECKER_TYPE,
153567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_127_WIDTH },
153568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_128_CHECKER_TYPE,
153569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_128_WIDTH },
153570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_129_CHECKER_TYPE,
153571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_129_WIDTH },
153572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_130_CHECKER_TYPE,
153573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_130_WIDTH },
153574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_131_CHECKER_TYPE,
153575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_131_WIDTH },
153576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_132_CHECKER_TYPE,
153577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_132_WIDTH },
153578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_133_CHECKER_TYPE,
153579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_133_WIDTH },
153580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_134_CHECKER_TYPE,
153581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_134_WIDTH },
153582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_135_CHECKER_TYPE,
153583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_135_WIDTH },
153584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_136_CHECKER_TYPE,
153585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_136_WIDTH },
153586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_137_CHECKER_TYPE,
153587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_137_WIDTH },
153588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_138_CHECKER_TYPE,
153589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_138_WIDTH },
153590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_139_CHECKER_TYPE,
153591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_139_WIDTH },
153592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_140_CHECKER_TYPE,
153593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_140_WIDTH },
153594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_141_CHECKER_TYPE,
153595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_141_WIDTH },
153596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_142_CHECKER_TYPE,
153597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_142_WIDTH },
153598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_143_CHECKER_TYPE,
153599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_143_WIDTH },
153600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_144_CHECKER_TYPE,
153601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_144_WIDTH },
153602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_145_CHECKER_TYPE,
153603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_145_WIDTH },
153604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_146_CHECKER_TYPE,
153605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_146_WIDTH },
153606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_147_CHECKER_TYPE,
153607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_147_WIDTH },
153608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_148_CHECKER_TYPE,
153609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_148_WIDTH },
153610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_149_CHECKER_TYPE,
153611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_149_WIDTH },
153612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_150_CHECKER_TYPE,
153613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_150_WIDTH },
153614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_151_CHECKER_TYPE,
153615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_151_WIDTH },
153616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_152_CHECKER_TYPE,
153617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_152_WIDTH },
153618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_153_CHECKER_TYPE,
153619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_153_WIDTH },
153620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_154_CHECKER_TYPE,
153621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_154_WIDTH },
153622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_155_CHECKER_TYPE,
153623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_155_WIDTH },
153624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_156_CHECKER_TYPE,
153625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_156_WIDTH },
153626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_157_CHECKER_TYPE,
153627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_157_WIDTH },
153628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_158_CHECKER_TYPE,
153629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_158_WIDTH },
153630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_159_CHECKER_TYPE,
153631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_159_WIDTH },
153632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_160_CHECKER_TYPE,
153633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_160_WIDTH },
153634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_161_CHECKER_TYPE,
153635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_161_WIDTH },
153636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_162_CHECKER_TYPE,
153637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_162_WIDTH },
153638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_163_CHECKER_TYPE,
153639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_163_WIDTH },
153640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_164_CHECKER_TYPE,
153641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_164_WIDTH },
153642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_165_CHECKER_TYPE,
153643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_165_WIDTH },
153644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_166_CHECKER_TYPE,
153645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_166_WIDTH },
153646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_167_CHECKER_TYPE,
153647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_167_WIDTH },
153648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_168_CHECKER_TYPE,
153649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_168_WIDTH },
153650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_169_CHECKER_TYPE,
153651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_169_WIDTH },
153652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_170_CHECKER_TYPE,
153653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_170_WIDTH },
153654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_171_CHECKER_TYPE,
153655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_171_WIDTH },
153656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_172_CHECKER_TYPE,
153657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_172_WIDTH },
153658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_173_CHECKER_TYPE,
153659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_173_WIDTH },
153660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_174_CHECKER_TYPE,
153661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_174_WIDTH },
153662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_175_CHECKER_TYPE,
153663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_175_WIDTH },
153664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_176_CHECKER_TYPE,
153665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_176_WIDTH },
153666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_177_CHECKER_TYPE,
153667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_177_WIDTH },
153668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_178_CHECKER_TYPE,
153669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_178_WIDTH },
153670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_179_CHECKER_TYPE,
153671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_179_WIDTH },
153672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_180_CHECKER_TYPE,
153673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_180_WIDTH },
153674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_181_CHECKER_TYPE,
153675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_181_WIDTH },
153676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_182_CHECKER_TYPE,
153677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_182_WIDTH },
153678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_183_CHECKER_TYPE,
153679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_183_WIDTH },
153680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_184_CHECKER_TYPE,
153681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_184_WIDTH },
153682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_185_CHECKER_TYPE,
153683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_185_WIDTH },
153684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_186_CHECKER_TYPE,
153685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_186_WIDTH },
153686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_187_CHECKER_TYPE,
153687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_187_WIDTH },
153688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_188_CHECKER_TYPE,
153689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_188_WIDTH },
153690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_189_CHECKER_TYPE,
153691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_189_WIDTH },
153692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_190_CHECKER_TYPE,
153693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_190_WIDTH },
153694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_191_CHECKER_TYPE,
153695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_191_WIDTH },
153696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_192_CHECKER_TYPE,
153697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_192_WIDTH },
153698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_193_CHECKER_TYPE,
153699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_193_WIDTH },
153700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_194_CHECKER_TYPE,
153701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_194_WIDTH },
153702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_195_CHECKER_TYPE,
153703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_195_WIDTH },
153704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_196_CHECKER_TYPE,
153705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_196_WIDTH },
153706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_197_CHECKER_TYPE,
153707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_197_WIDTH },
153708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_198_CHECKER_TYPE,
153709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_198_WIDTH },
153710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_199_CHECKER_TYPE,
153711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_199_WIDTH },
153712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_200_CHECKER_TYPE,
153713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_200_WIDTH },
153714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_201_CHECKER_TYPE,
153715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_201_WIDTH },
153716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_202_CHECKER_TYPE,
153717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_202_WIDTH },
153718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_203_CHECKER_TYPE,
153719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_203_WIDTH },
153720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_204_CHECKER_TYPE,
153721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_204_WIDTH },
153722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_205_CHECKER_TYPE,
153723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_205_WIDTH },
153724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_206_CHECKER_TYPE,
153725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_206_WIDTH },
153726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_207_CHECKER_TYPE,
153727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_207_WIDTH },
153728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_208_CHECKER_TYPE,
153729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_208_WIDTH },
153730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_209_CHECKER_TYPE,
153731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_209_WIDTH },
153732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_210_CHECKER_TYPE,
153733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_210_WIDTH },
153734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_211_CHECKER_TYPE,
153735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_211_WIDTH },
153736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_212_CHECKER_TYPE,
153737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_212_WIDTH },
153738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_213_CHECKER_TYPE,
153739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_213_WIDTH },
153740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_214_CHECKER_TYPE,
153741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_214_WIDTH },
153742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_215_CHECKER_TYPE,
153743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_215_WIDTH },
153744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_216_CHECKER_TYPE,
153745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_216_WIDTH },
153746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_217_CHECKER_TYPE,
153747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_217_WIDTH },
153748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_218_CHECKER_TYPE,
153749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_218_WIDTH },
153750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_219_CHECKER_TYPE,
153751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_219_WIDTH },
153752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_220_CHECKER_TYPE,
153753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_220_WIDTH },
153754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_221_CHECKER_TYPE,
153755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_221_WIDTH },
153756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_222_CHECKER_TYPE,
153757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_222_WIDTH },
153758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_223_CHECKER_TYPE,
153759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_223_WIDTH },
153760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_224_CHECKER_TYPE,
153761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_224_WIDTH },
153762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_225_CHECKER_TYPE,
153763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_225_WIDTH },
153764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_226_CHECKER_TYPE,
153765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_226_WIDTH },
153766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_227_CHECKER_TYPE,
153767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_227_WIDTH },
153768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_228_CHECKER_TYPE,
153769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_228_WIDTH },
153770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_229_CHECKER_TYPE,
153771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_229_WIDTH },
153772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_230_CHECKER_TYPE,
153773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_230_WIDTH },
153774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_231_CHECKER_TYPE,
153775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_231_WIDTH },
153776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_232_CHECKER_TYPE,
153777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_232_WIDTH },
153778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_233_CHECKER_TYPE,
153779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_233_WIDTH },
153780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_234_CHECKER_TYPE,
153781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_234_WIDTH },
153782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_235_CHECKER_TYPE,
153783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_235_WIDTH },
153784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_236_CHECKER_TYPE,
153785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_236_WIDTH },
153786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_237_CHECKER_TYPE,
153787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_237_WIDTH },
153788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_238_CHECKER_TYPE,
153789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_238_WIDTH },
153790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_239_CHECKER_TYPE,
153791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_239_WIDTH },
153792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_240_CHECKER_TYPE,
153793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_240_WIDTH },
153794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_241_CHECKER_TYPE,
153795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_241_WIDTH },
153796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_242_CHECKER_TYPE,
153797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_242_WIDTH },
153798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_243_CHECKER_TYPE,
153799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_243_WIDTH },
153800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_244_CHECKER_TYPE,
153801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_244_WIDTH },
153802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_245_CHECKER_TYPE,
153803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_245_WIDTH },
153804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_246_CHECKER_TYPE,
153805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_246_WIDTH },
153806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_247_CHECKER_TYPE,
153807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_247_WIDTH },
153808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_248_CHECKER_TYPE,
153809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_248_WIDTH },
153810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_249_CHECKER_TYPE,
153811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_249_WIDTH },
153812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_250_CHECKER_TYPE,
153813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_250_WIDTH },
153814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_251_CHECKER_TYPE,
153815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_251_WIDTH },
153816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_252_CHECKER_TYPE,
153817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_252_WIDTH },
153818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_253_CHECKER_TYPE,
153819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_253_WIDTH },
153820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_254_CHECKER_TYPE,
153821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_254_WIDTH },
153822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_255_CHECKER_TYPE,
153823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_GROUP_255_WIDTH },
153824 };
153825 
153831 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_MAX_NUM_CHECKERS] =
153832 {
153833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_0_CHECKER_TYPE,
153834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_0_WIDTH },
153835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_1_CHECKER_TYPE,
153836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_1_WIDTH },
153837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_2_CHECKER_TYPE,
153838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_2_WIDTH },
153839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_3_CHECKER_TYPE,
153840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_3_WIDTH },
153841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_4_CHECKER_TYPE,
153842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_4_WIDTH },
153843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_5_CHECKER_TYPE,
153844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_5_WIDTH },
153845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_6_CHECKER_TYPE,
153846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_6_WIDTH },
153847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_7_CHECKER_TYPE,
153848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_7_WIDTH },
153849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_8_CHECKER_TYPE,
153850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_8_WIDTH },
153851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_9_CHECKER_TYPE,
153852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_9_WIDTH },
153853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_10_CHECKER_TYPE,
153854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_10_WIDTH },
153855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_11_CHECKER_TYPE,
153856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_11_WIDTH },
153857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_12_CHECKER_TYPE,
153858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_12_WIDTH },
153859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_13_CHECKER_TYPE,
153860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_13_WIDTH },
153861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_14_CHECKER_TYPE,
153862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_14_WIDTH },
153863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_15_CHECKER_TYPE,
153864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_15_WIDTH },
153865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_16_CHECKER_TYPE,
153866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_16_WIDTH },
153867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_17_CHECKER_TYPE,
153868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_17_WIDTH },
153869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_18_CHECKER_TYPE,
153870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_18_WIDTH },
153871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_19_CHECKER_TYPE,
153872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_19_WIDTH },
153873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_20_CHECKER_TYPE,
153874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_20_WIDTH },
153875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_21_CHECKER_TYPE,
153876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_21_WIDTH },
153877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_22_CHECKER_TYPE,
153878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_22_WIDTH },
153879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_23_CHECKER_TYPE,
153880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_23_WIDTH },
153881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_24_CHECKER_TYPE,
153882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_24_WIDTH },
153883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_25_CHECKER_TYPE,
153884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_25_WIDTH },
153885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_26_CHECKER_TYPE,
153886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_26_WIDTH },
153887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_27_CHECKER_TYPE,
153888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_27_WIDTH },
153889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_28_CHECKER_TYPE,
153890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_28_WIDTH },
153891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_29_CHECKER_TYPE,
153892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_29_WIDTH },
153893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_30_CHECKER_TYPE,
153894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_30_WIDTH },
153895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_31_CHECKER_TYPE,
153896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_31_WIDTH },
153897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_32_CHECKER_TYPE,
153898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_32_WIDTH },
153899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_33_CHECKER_TYPE,
153900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_33_WIDTH },
153901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_34_CHECKER_TYPE,
153902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_34_WIDTH },
153903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_35_CHECKER_TYPE,
153904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_35_WIDTH },
153905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_36_CHECKER_TYPE,
153906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_36_WIDTH },
153907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_37_CHECKER_TYPE,
153908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_37_WIDTH },
153909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_38_CHECKER_TYPE,
153910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_38_WIDTH },
153911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_39_CHECKER_TYPE,
153912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_39_WIDTH },
153913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_40_CHECKER_TYPE,
153914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_40_WIDTH },
153915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_41_CHECKER_TYPE,
153916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_41_WIDTH },
153917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_42_CHECKER_TYPE,
153918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_42_WIDTH },
153919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_43_CHECKER_TYPE,
153920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_43_WIDTH },
153921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_44_CHECKER_TYPE,
153922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_44_WIDTH },
153923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_45_CHECKER_TYPE,
153924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_45_WIDTH },
153925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_46_CHECKER_TYPE,
153926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_46_WIDTH },
153927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_47_CHECKER_TYPE,
153928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_47_WIDTH },
153929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_48_CHECKER_TYPE,
153930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_48_WIDTH },
153931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_49_CHECKER_TYPE,
153932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_49_WIDTH },
153933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_50_CHECKER_TYPE,
153934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_50_WIDTH },
153935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_51_CHECKER_TYPE,
153936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_51_WIDTH },
153937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_52_CHECKER_TYPE,
153938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_52_WIDTH },
153939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_53_CHECKER_TYPE,
153940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_53_WIDTH },
153941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_54_CHECKER_TYPE,
153942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_54_WIDTH },
153943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_55_CHECKER_TYPE,
153944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_55_WIDTH },
153945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_56_CHECKER_TYPE,
153946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_56_WIDTH },
153947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_57_CHECKER_TYPE,
153948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_57_WIDTH },
153949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_58_CHECKER_TYPE,
153950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_58_WIDTH },
153951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_59_CHECKER_TYPE,
153952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_59_WIDTH },
153953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_60_CHECKER_TYPE,
153954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_60_WIDTH },
153955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_61_CHECKER_TYPE,
153956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_61_WIDTH },
153957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_62_CHECKER_TYPE,
153958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_62_WIDTH },
153959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_63_CHECKER_TYPE,
153960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_63_WIDTH },
153961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_64_CHECKER_TYPE,
153962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_64_WIDTH },
153963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_65_CHECKER_TYPE,
153964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_65_WIDTH },
153965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_66_CHECKER_TYPE,
153966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_66_WIDTH },
153967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_67_CHECKER_TYPE,
153968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_67_WIDTH },
153969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_68_CHECKER_TYPE,
153970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_68_WIDTH },
153971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_69_CHECKER_TYPE,
153972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_69_WIDTH },
153973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_70_CHECKER_TYPE,
153974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_70_WIDTH },
153975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_71_CHECKER_TYPE,
153976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_71_WIDTH },
153977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_72_CHECKER_TYPE,
153978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_72_WIDTH },
153979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_73_CHECKER_TYPE,
153980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_73_WIDTH },
153981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_74_CHECKER_TYPE,
153982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_74_WIDTH },
153983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_75_CHECKER_TYPE,
153984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_75_WIDTH },
153985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_76_CHECKER_TYPE,
153986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_76_WIDTH },
153987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_77_CHECKER_TYPE,
153988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_77_WIDTH },
153989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_78_CHECKER_TYPE,
153990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_78_WIDTH },
153991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_79_CHECKER_TYPE,
153992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_79_WIDTH },
153993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_80_CHECKER_TYPE,
153994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_80_WIDTH },
153995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_81_CHECKER_TYPE,
153996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_81_WIDTH },
153997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_82_CHECKER_TYPE,
153998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_82_WIDTH },
153999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_83_CHECKER_TYPE,
154000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_83_WIDTH },
154001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_84_CHECKER_TYPE,
154002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_84_WIDTH },
154003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_85_CHECKER_TYPE,
154004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_85_WIDTH },
154005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_86_CHECKER_TYPE,
154006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_86_WIDTH },
154007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_87_CHECKER_TYPE,
154008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_87_WIDTH },
154009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_88_CHECKER_TYPE,
154010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_88_WIDTH },
154011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_89_CHECKER_TYPE,
154012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_89_WIDTH },
154013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_90_CHECKER_TYPE,
154014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_90_WIDTH },
154015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_91_CHECKER_TYPE,
154016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_91_WIDTH },
154017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_92_CHECKER_TYPE,
154018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_92_WIDTH },
154019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_93_CHECKER_TYPE,
154020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_93_WIDTH },
154021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_94_CHECKER_TYPE,
154022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_94_WIDTH },
154023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_95_CHECKER_TYPE,
154024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_95_WIDTH },
154025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_96_CHECKER_TYPE,
154026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_96_WIDTH },
154027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_97_CHECKER_TYPE,
154028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_97_WIDTH },
154029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_98_CHECKER_TYPE,
154030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_98_WIDTH },
154031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_99_CHECKER_TYPE,
154032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_99_WIDTH },
154033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_100_CHECKER_TYPE,
154034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_100_WIDTH },
154035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_101_CHECKER_TYPE,
154036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_101_WIDTH },
154037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_102_CHECKER_TYPE,
154038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_102_WIDTH },
154039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_103_CHECKER_TYPE,
154040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_103_WIDTH },
154041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_104_CHECKER_TYPE,
154042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_104_WIDTH },
154043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_105_CHECKER_TYPE,
154044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_105_WIDTH },
154045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_106_CHECKER_TYPE,
154046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_106_WIDTH },
154047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_107_CHECKER_TYPE,
154048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_107_WIDTH },
154049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_108_CHECKER_TYPE,
154050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_108_WIDTH },
154051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_109_CHECKER_TYPE,
154052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_109_WIDTH },
154053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_110_CHECKER_TYPE,
154054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_110_WIDTH },
154055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_111_CHECKER_TYPE,
154056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_111_WIDTH },
154057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_112_CHECKER_TYPE,
154058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_112_WIDTH },
154059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_113_CHECKER_TYPE,
154060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_113_WIDTH },
154061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_114_CHECKER_TYPE,
154062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_114_WIDTH },
154063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_115_CHECKER_TYPE,
154064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_115_WIDTH },
154065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_116_CHECKER_TYPE,
154066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_116_WIDTH },
154067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_117_CHECKER_TYPE,
154068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_117_WIDTH },
154069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_118_CHECKER_TYPE,
154070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_118_WIDTH },
154071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_119_CHECKER_TYPE,
154072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_119_WIDTH },
154073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_120_CHECKER_TYPE,
154074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_120_WIDTH },
154075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_121_CHECKER_TYPE,
154076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_121_WIDTH },
154077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_122_CHECKER_TYPE,
154078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_122_WIDTH },
154079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_123_CHECKER_TYPE,
154080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_123_WIDTH },
154081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_124_CHECKER_TYPE,
154082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_124_WIDTH },
154083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_125_CHECKER_TYPE,
154084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_125_WIDTH },
154085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_126_CHECKER_TYPE,
154086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_126_WIDTH },
154087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_127_CHECKER_TYPE,
154088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_127_WIDTH },
154089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_128_CHECKER_TYPE,
154090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_128_WIDTH },
154091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_129_CHECKER_TYPE,
154092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_129_WIDTH },
154093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_130_CHECKER_TYPE,
154094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_130_WIDTH },
154095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_131_CHECKER_TYPE,
154096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_131_WIDTH },
154097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_132_CHECKER_TYPE,
154098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_132_WIDTH },
154099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_133_CHECKER_TYPE,
154100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_133_WIDTH },
154101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_134_CHECKER_TYPE,
154102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_134_WIDTH },
154103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_135_CHECKER_TYPE,
154104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_135_WIDTH },
154105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_136_CHECKER_TYPE,
154106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_136_WIDTH },
154107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_137_CHECKER_TYPE,
154108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_137_WIDTH },
154109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_138_CHECKER_TYPE,
154110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_138_WIDTH },
154111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_139_CHECKER_TYPE,
154112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_139_WIDTH },
154113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_140_CHECKER_TYPE,
154114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_140_WIDTH },
154115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_141_CHECKER_TYPE,
154116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_141_WIDTH },
154117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_142_CHECKER_TYPE,
154118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_142_WIDTH },
154119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_143_CHECKER_TYPE,
154120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_143_WIDTH },
154121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_144_CHECKER_TYPE,
154122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_144_WIDTH },
154123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_145_CHECKER_TYPE,
154124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_145_WIDTH },
154125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_146_CHECKER_TYPE,
154126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_146_WIDTH },
154127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_147_CHECKER_TYPE,
154128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_147_WIDTH },
154129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_148_CHECKER_TYPE,
154130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_148_WIDTH },
154131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_149_CHECKER_TYPE,
154132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_149_WIDTH },
154133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_150_CHECKER_TYPE,
154134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_150_WIDTH },
154135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_151_CHECKER_TYPE,
154136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_151_WIDTH },
154137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_152_CHECKER_TYPE,
154138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_152_WIDTH },
154139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_153_CHECKER_TYPE,
154140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_153_WIDTH },
154141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_154_CHECKER_TYPE,
154142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_154_WIDTH },
154143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_155_CHECKER_TYPE,
154144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_155_WIDTH },
154145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_156_CHECKER_TYPE,
154146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_156_WIDTH },
154147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_157_CHECKER_TYPE,
154148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_157_WIDTH },
154149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_158_CHECKER_TYPE,
154150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_158_WIDTH },
154151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_159_CHECKER_TYPE,
154152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_159_WIDTH },
154153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_160_CHECKER_TYPE,
154154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_160_WIDTH },
154155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_161_CHECKER_TYPE,
154156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_161_WIDTH },
154157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_162_CHECKER_TYPE,
154158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_162_WIDTH },
154159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_163_CHECKER_TYPE,
154160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_163_WIDTH },
154161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_164_CHECKER_TYPE,
154162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_164_WIDTH },
154163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_165_CHECKER_TYPE,
154164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_165_WIDTH },
154165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_166_CHECKER_TYPE,
154166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_166_WIDTH },
154167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_167_CHECKER_TYPE,
154168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_167_WIDTH },
154169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_168_CHECKER_TYPE,
154170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_168_WIDTH },
154171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_169_CHECKER_TYPE,
154172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_169_WIDTH },
154173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_170_CHECKER_TYPE,
154174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_170_WIDTH },
154175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_171_CHECKER_TYPE,
154176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_171_WIDTH },
154177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_172_CHECKER_TYPE,
154178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_172_WIDTH },
154179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_173_CHECKER_TYPE,
154180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_173_WIDTH },
154181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_174_CHECKER_TYPE,
154182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_174_WIDTH },
154183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_175_CHECKER_TYPE,
154184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_175_WIDTH },
154185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_176_CHECKER_TYPE,
154186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_176_WIDTH },
154187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_177_CHECKER_TYPE,
154188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_177_WIDTH },
154189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_178_CHECKER_TYPE,
154190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_178_WIDTH },
154191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_179_CHECKER_TYPE,
154192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_179_WIDTH },
154193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_180_CHECKER_TYPE,
154194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_180_WIDTH },
154195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_181_CHECKER_TYPE,
154196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_181_WIDTH },
154197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_182_CHECKER_TYPE,
154198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_182_WIDTH },
154199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_183_CHECKER_TYPE,
154200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_183_WIDTH },
154201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_184_CHECKER_TYPE,
154202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_184_WIDTH },
154203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_185_CHECKER_TYPE,
154204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_185_WIDTH },
154205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_186_CHECKER_TYPE,
154206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_186_WIDTH },
154207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_187_CHECKER_TYPE,
154208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_187_WIDTH },
154209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_188_CHECKER_TYPE,
154210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_188_WIDTH },
154211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_189_CHECKER_TYPE,
154212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_189_WIDTH },
154213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_190_CHECKER_TYPE,
154214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_190_WIDTH },
154215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_191_CHECKER_TYPE,
154216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_191_WIDTH },
154217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_192_CHECKER_TYPE,
154218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_192_WIDTH },
154219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_193_CHECKER_TYPE,
154220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_193_WIDTH },
154221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_194_CHECKER_TYPE,
154222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_194_WIDTH },
154223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_195_CHECKER_TYPE,
154224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_195_WIDTH },
154225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_196_CHECKER_TYPE,
154226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_196_WIDTH },
154227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_197_CHECKER_TYPE,
154228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_197_WIDTH },
154229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_198_CHECKER_TYPE,
154230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_198_WIDTH },
154231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_199_CHECKER_TYPE,
154232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_199_WIDTH },
154233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_200_CHECKER_TYPE,
154234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_200_WIDTH },
154235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_201_CHECKER_TYPE,
154236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_201_WIDTH },
154237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_202_CHECKER_TYPE,
154238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_202_WIDTH },
154239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_203_CHECKER_TYPE,
154240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_203_WIDTH },
154241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_204_CHECKER_TYPE,
154242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_204_WIDTH },
154243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_205_CHECKER_TYPE,
154244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_205_WIDTH },
154245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_206_CHECKER_TYPE,
154246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_206_WIDTH },
154247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_207_CHECKER_TYPE,
154248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_207_WIDTH },
154249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_208_CHECKER_TYPE,
154250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_208_WIDTH },
154251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_209_CHECKER_TYPE,
154252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_209_WIDTH },
154253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_210_CHECKER_TYPE,
154254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_210_WIDTH },
154255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_211_CHECKER_TYPE,
154256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_211_WIDTH },
154257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_212_CHECKER_TYPE,
154258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_212_WIDTH },
154259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_213_CHECKER_TYPE,
154260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_213_WIDTH },
154261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_214_CHECKER_TYPE,
154262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_214_WIDTH },
154263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_215_CHECKER_TYPE,
154264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_215_WIDTH },
154265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_216_CHECKER_TYPE,
154266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_216_WIDTH },
154267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_217_CHECKER_TYPE,
154268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_217_WIDTH },
154269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_218_CHECKER_TYPE,
154270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_218_WIDTH },
154271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_219_CHECKER_TYPE,
154272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_219_WIDTH },
154273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_220_CHECKER_TYPE,
154274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_220_WIDTH },
154275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_221_CHECKER_TYPE,
154276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_221_WIDTH },
154277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_222_CHECKER_TYPE,
154278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_222_WIDTH },
154279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_223_CHECKER_TYPE,
154280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_223_WIDTH },
154281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_224_CHECKER_TYPE,
154282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_224_WIDTH },
154283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_225_CHECKER_TYPE,
154284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_225_WIDTH },
154285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_226_CHECKER_TYPE,
154286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_226_WIDTH },
154287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_227_CHECKER_TYPE,
154288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_227_WIDTH },
154289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_228_CHECKER_TYPE,
154290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_228_WIDTH },
154291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_229_CHECKER_TYPE,
154292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_229_WIDTH },
154293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_230_CHECKER_TYPE,
154294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_230_WIDTH },
154295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_231_CHECKER_TYPE,
154296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_231_WIDTH },
154297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_232_CHECKER_TYPE,
154298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_232_WIDTH },
154299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_233_CHECKER_TYPE,
154300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_233_WIDTH },
154301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_234_CHECKER_TYPE,
154302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_234_WIDTH },
154303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_235_CHECKER_TYPE,
154304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_235_WIDTH },
154305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_236_CHECKER_TYPE,
154306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_236_WIDTH },
154307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_237_CHECKER_TYPE,
154308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_237_WIDTH },
154309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_238_CHECKER_TYPE,
154310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_238_WIDTH },
154311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_239_CHECKER_TYPE,
154312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_239_WIDTH },
154313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_240_CHECKER_TYPE,
154314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_240_WIDTH },
154315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_241_CHECKER_TYPE,
154316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_241_WIDTH },
154317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_242_CHECKER_TYPE,
154318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_242_WIDTH },
154319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_243_CHECKER_TYPE,
154320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_243_WIDTH },
154321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_244_CHECKER_TYPE,
154322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_244_WIDTH },
154323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_245_CHECKER_TYPE,
154324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_245_WIDTH },
154325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_246_CHECKER_TYPE,
154326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_246_WIDTH },
154327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_247_CHECKER_TYPE,
154328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_247_WIDTH },
154329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_248_CHECKER_TYPE,
154330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_248_WIDTH },
154331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_249_CHECKER_TYPE,
154332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_249_WIDTH },
154333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_250_CHECKER_TYPE,
154334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_250_WIDTH },
154335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_251_CHECKER_TYPE,
154336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_251_WIDTH },
154337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_252_CHECKER_TYPE,
154338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_252_WIDTH },
154339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_253_CHECKER_TYPE,
154340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_253_WIDTH },
154341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_254_CHECKER_TYPE,
154342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_254_WIDTH },
154343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_255_CHECKER_TYPE,
154344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_GROUP_255_WIDTH },
154345 };
154346 
154352 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_MAX_NUM_CHECKERS] =
154353 {
154354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_0_CHECKER_TYPE,
154355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_0_WIDTH },
154356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_1_CHECKER_TYPE,
154357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_1_WIDTH },
154358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_2_CHECKER_TYPE,
154359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_2_WIDTH },
154360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_3_CHECKER_TYPE,
154361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_3_WIDTH },
154362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_4_CHECKER_TYPE,
154363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_4_WIDTH },
154364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_5_CHECKER_TYPE,
154365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_5_WIDTH },
154366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_6_CHECKER_TYPE,
154367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_6_WIDTH },
154368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_7_CHECKER_TYPE,
154369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_7_WIDTH },
154370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_8_CHECKER_TYPE,
154371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_8_WIDTH },
154372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_9_CHECKER_TYPE,
154373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_9_WIDTH },
154374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_10_CHECKER_TYPE,
154375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_10_WIDTH },
154376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_11_CHECKER_TYPE,
154377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_11_WIDTH },
154378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_12_CHECKER_TYPE,
154379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_12_WIDTH },
154380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_13_CHECKER_TYPE,
154381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_13_WIDTH },
154382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_14_CHECKER_TYPE,
154383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_14_WIDTH },
154384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_15_CHECKER_TYPE,
154385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_15_WIDTH },
154386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_16_CHECKER_TYPE,
154387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_16_WIDTH },
154388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_17_CHECKER_TYPE,
154389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_17_WIDTH },
154390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_18_CHECKER_TYPE,
154391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_18_WIDTH },
154392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_19_CHECKER_TYPE,
154393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_19_WIDTH },
154394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_20_CHECKER_TYPE,
154395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_20_WIDTH },
154396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_21_CHECKER_TYPE,
154397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_21_WIDTH },
154398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_22_CHECKER_TYPE,
154399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_22_WIDTH },
154400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_23_CHECKER_TYPE,
154401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_23_WIDTH },
154402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_24_CHECKER_TYPE,
154403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_24_WIDTH },
154404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_25_CHECKER_TYPE,
154405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_25_WIDTH },
154406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_26_CHECKER_TYPE,
154407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_26_WIDTH },
154408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_27_CHECKER_TYPE,
154409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_27_WIDTH },
154410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_28_CHECKER_TYPE,
154411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_28_WIDTH },
154412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_29_CHECKER_TYPE,
154413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_29_WIDTH },
154414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_30_CHECKER_TYPE,
154415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_30_WIDTH },
154416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_31_CHECKER_TYPE,
154417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_31_WIDTH },
154418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_32_CHECKER_TYPE,
154419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_32_WIDTH },
154420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_33_CHECKER_TYPE,
154421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_33_WIDTH },
154422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_34_CHECKER_TYPE,
154423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_34_WIDTH },
154424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_35_CHECKER_TYPE,
154425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_35_WIDTH },
154426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_36_CHECKER_TYPE,
154427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_36_WIDTH },
154428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_37_CHECKER_TYPE,
154429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_37_WIDTH },
154430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_38_CHECKER_TYPE,
154431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_38_WIDTH },
154432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_39_CHECKER_TYPE,
154433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_39_WIDTH },
154434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_40_CHECKER_TYPE,
154435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_40_WIDTH },
154436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_41_CHECKER_TYPE,
154437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_41_WIDTH },
154438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_42_CHECKER_TYPE,
154439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_42_WIDTH },
154440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_43_CHECKER_TYPE,
154441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_43_WIDTH },
154442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_44_CHECKER_TYPE,
154443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_44_WIDTH },
154444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_45_CHECKER_TYPE,
154445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_45_WIDTH },
154446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_46_CHECKER_TYPE,
154447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_46_WIDTH },
154448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_47_CHECKER_TYPE,
154449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_47_WIDTH },
154450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_48_CHECKER_TYPE,
154451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_48_WIDTH },
154452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_49_CHECKER_TYPE,
154453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_49_WIDTH },
154454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_50_CHECKER_TYPE,
154455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_50_WIDTH },
154456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_51_CHECKER_TYPE,
154457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_51_WIDTH },
154458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_52_CHECKER_TYPE,
154459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_52_WIDTH },
154460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_53_CHECKER_TYPE,
154461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_53_WIDTH },
154462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_54_CHECKER_TYPE,
154463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_54_WIDTH },
154464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_55_CHECKER_TYPE,
154465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_55_WIDTH },
154466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_56_CHECKER_TYPE,
154467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_56_WIDTH },
154468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_57_CHECKER_TYPE,
154469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_57_WIDTH },
154470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_58_CHECKER_TYPE,
154471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_58_WIDTH },
154472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_59_CHECKER_TYPE,
154473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_59_WIDTH },
154474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_60_CHECKER_TYPE,
154475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_60_WIDTH },
154476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_61_CHECKER_TYPE,
154477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_61_WIDTH },
154478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_62_CHECKER_TYPE,
154479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_62_WIDTH },
154480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_63_CHECKER_TYPE,
154481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_63_WIDTH },
154482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_64_CHECKER_TYPE,
154483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_64_WIDTH },
154484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_65_CHECKER_TYPE,
154485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_65_WIDTH },
154486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_66_CHECKER_TYPE,
154487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_66_WIDTH },
154488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_67_CHECKER_TYPE,
154489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_67_WIDTH },
154490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_68_CHECKER_TYPE,
154491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_68_WIDTH },
154492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_69_CHECKER_TYPE,
154493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_69_WIDTH },
154494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_70_CHECKER_TYPE,
154495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_70_WIDTH },
154496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_71_CHECKER_TYPE,
154497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_71_WIDTH },
154498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_72_CHECKER_TYPE,
154499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_72_WIDTH },
154500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_73_CHECKER_TYPE,
154501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_73_WIDTH },
154502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_74_CHECKER_TYPE,
154503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_74_WIDTH },
154504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_75_CHECKER_TYPE,
154505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_75_WIDTH },
154506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_76_CHECKER_TYPE,
154507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_76_WIDTH },
154508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_77_CHECKER_TYPE,
154509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_77_WIDTH },
154510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_78_CHECKER_TYPE,
154511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_78_WIDTH },
154512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_79_CHECKER_TYPE,
154513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_79_WIDTH },
154514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_80_CHECKER_TYPE,
154515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_80_WIDTH },
154516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_81_CHECKER_TYPE,
154517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_81_WIDTH },
154518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_82_CHECKER_TYPE,
154519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_82_WIDTH },
154520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_83_CHECKER_TYPE,
154521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_83_WIDTH },
154522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_84_CHECKER_TYPE,
154523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_84_WIDTH },
154524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_85_CHECKER_TYPE,
154525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_85_WIDTH },
154526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_86_CHECKER_TYPE,
154527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_86_WIDTH },
154528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_87_CHECKER_TYPE,
154529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_87_WIDTH },
154530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_88_CHECKER_TYPE,
154531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_88_WIDTH },
154532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_89_CHECKER_TYPE,
154533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_89_WIDTH },
154534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_90_CHECKER_TYPE,
154535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_90_WIDTH },
154536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_91_CHECKER_TYPE,
154537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_91_WIDTH },
154538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_92_CHECKER_TYPE,
154539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_92_WIDTH },
154540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_93_CHECKER_TYPE,
154541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_93_WIDTH },
154542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_94_CHECKER_TYPE,
154543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_94_WIDTH },
154544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_95_CHECKER_TYPE,
154545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_95_WIDTH },
154546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_96_CHECKER_TYPE,
154547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_96_WIDTH },
154548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_97_CHECKER_TYPE,
154549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_97_WIDTH },
154550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_98_CHECKER_TYPE,
154551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_98_WIDTH },
154552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_99_CHECKER_TYPE,
154553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_99_WIDTH },
154554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_100_CHECKER_TYPE,
154555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_100_WIDTH },
154556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_101_CHECKER_TYPE,
154557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_101_WIDTH },
154558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_102_CHECKER_TYPE,
154559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_102_WIDTH },
154560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_103_CHECKER_TYPE,
154561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_103_WIDTH },
154562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_104_CHECKER_TYPE,
154563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_104_WIDTH },
154564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_105_CHECKER_TYPE,
154565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_105_WIDTH },
154566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_106_CHECKER_TYPE,
154567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_106_WIDTH },
154568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_107_CHECKER_TYPE,
154569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_107_WIDTH },
154570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_108_CHECKER_TYPE,
154571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_108_WIDTH },
154572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_109_CHECKER_TYPE,
154573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_109_WIDTH },
154574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_110_CHECKER_TYPE,
154575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_110_WIDTH },
154576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_111_CHECKER_TYPE,
154577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_111_WIDTH },
154578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_112_CHECKER_TYPE,
154579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_112_WIDTH },
154580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_113_CHECKER_TYPE,
154581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_113_WIDTH },
154582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_114_CHECKER_TYPE,
154583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_114_WIDTH },
154584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_115_CHECKER_TYPE,
154585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_115_WIDTH },
154586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_116_CHECKER_TYPE,
154587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_116_WIDTH },
154588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_117_CHECKER_TYPE,
154589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_117_WIDTH },
154590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_118_CHECKER_TYPE,
154591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_118_WIDTH },
154592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_119_CHECKER_TYPE,
154593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_119_WIDTH },
154594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_120_CHECKER_TYPE,
154595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_120_WIDTH },
154596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_121_CHECKER_TYPE,
154597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_121_WIDTH },
154598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_122_CHECKER_TYPE,
154599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_122_WIDTH },
154600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_123_CHECKER_TYPE,
154601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_123_WIDTH },
154602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_124_CHECKER_TYPE,
154603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_124_WIDTH },
154604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_125_CHECKER_TYPE,
154605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_125_WIDTH },
154606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_126_CHECKER_TYPE,
154607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_126_WIDTH },
154608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_127_CHECKER_TYPE,
154609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_127_WIDTH },
154610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_128_CHECKER_TYPE,
154611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_128_WIDTH },
154612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_129_CHECKER_TYPE,
154613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_129_WIDTH },
154614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_130_CHECKER_TYPE,
154615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_130_WIDTH },
154616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_131_CHECKER_TYPE,
154617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_131_WIDTH },
154618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_132_CHECKER_TYPE,
154619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_132_WIDTH },
154620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_133_CHECKER_TYPE,
154621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_133_WIDTH },
154622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_134_CHECKER_TYPE,
154623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_134_WIDTH },
154624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_135_CHECKER_TYPE,
154625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_135_WIDTH },
154626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_136_CHECKER_TYPE,
154627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_136_WIDTH },
154628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_137_CHECKER_TYPE,
154629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_137_WIDTH },
154630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_138_CHECKER_TYPE,
154631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_138_WIDTH },
154632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_139_CHECKER_TYPE,
154633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_139_WIDTH },
154634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_140_CHECKER_TYPE,
154635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_140_WIDTH },
154636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_141_CHECKER_TYPE,
154637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_141_WIDTH },
154638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_142_CHECKER_TYPE,
154639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_142_WIDTH },
154640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_143_CHECKER_TYPE,
154641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_143_WIDTH },
154642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_144_CHECKER_TYPE,
154643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_144_WIDTH },
154644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_145_CHECKER_TYPE,
154645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_145_WIDTH },
154646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_146_CHECKER_TYPE,
154647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_146_WIDTH },
154648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_147_CHECKER_TYPE,
154649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_147_WIDTH },
154650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_148_CHECKER_TYPE,
154651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_148_WIDTH },
154652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_149_CHECKER_TYPE,
154653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_149_WIDTH },
154654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_150_CHECKER_TYPE,
154655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_150_WIDTH },
154656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_151_CHECKER_TYPE,
154657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_151_WIDTH },
154658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_152_CHECKER_TYPE,
154659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_152_WIDTH },
154660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_153_CHECKER_TYPE,
154661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_153_WIDTH },
154662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_154_CHECKER_TYPE,
154663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_154_WIDTH },
154664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_155_CHECKER_TYPE,
154665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_155_WIDTH },
154666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_156_CHECKER_TYPE,
154667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_156_WIDTH },
154668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_157_CHECKER_TYPE,
154669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_157_WIDTH },
154670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_158_CHECKER_TYPE,
154671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_158_WIDTH },
154672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_159_CHECKER_TYPE,
154673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_159_WIDTH },
154674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_160_CHECKER_TYPE,
154675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_160_WIDTH },
154676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_161_CHECKER_TYPE,
154677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_161_WIDTH },
154678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_162_CHECKER_TYPE,
154679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_162_WIDTH },
154680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_163_CHECKER_TYPE,
154681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_163_WIDTH },
154682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_164_CHECKER_TYPE,
154683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_164_WIDTH },
154684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_165_CHECKER_TYPE,
154685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_165_WIDTH },
154686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_166_CHECKER_TYPE,
154687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_166_WIDTH },
154688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_167_CHECKER_TYPE,
154689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_167_WIDTH },
154690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_168_CHECKER_TYPE,
154691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_168_WIDTH },
154692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_169_CHECKER_TYPE,
154693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_169_WIDTH },
154694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_170_CHECKER_TYPE,
154695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_170_WIDTH },
154696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_171_CHECKER_TYPE,
154697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_171_WIDTH },
154698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_172_CHECKER_TYPE,
154699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_172_WIDTH },
154700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_173_CHECKER_TYPE,
154701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_173_WIDTH },
154702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_174_CHECKER_TYPE,
154703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_174_WIDTH },
154704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_175_CHECKER_TYPE,
154705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_175_WIDTH },
154706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_176_CHECKER_TYPE,
154707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_176_WIDTH },
154708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_177_CHECKER_TYPE,
154709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_177_WIDTH },
154710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_178_CHECKER_TYPE,
154711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_178_WIDTH },
154712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_179_CHECKER_TYPE,
154713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_179_WIDTH },
154714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_180_CHECKER_TYPE,
154715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_180_WIDTH },
154716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_181_CHECKER_TYPE,
154717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_181_WIDTH },
154718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_182_CHECKER_TYPE,
154719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_182_WIDTH },
154720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_183_CHECKER_TYPE,
154721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_183_WIDTH },
154722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_184_CHECKER_TYPE,
154723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_184_WIDTH },
154724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_185_CHECKER_TYPE,
154725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_185_WIDTH },
154726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_186_CHECKER_TYPE,
154727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_186_WIDTH },
154728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_187_CHECKER_TYPE,
154729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_187_WIDTH },
154730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_188_CHECKER_TYPE,
154731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_188_WIDTH },
154732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_189_CHECKER_TYPE,
154733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_189_WIDTH },
154734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_190_CHECKER_TYPE,
154735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_190_WIDTH },
154736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_191_CHECKER_TYPE,
154737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_191_WIDTH },
154738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_192_CHECKER_TYPE,
154739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_192_WIDTH },
154740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_193_CHECKER_TYPE,
154741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_193_WIDTH },
154742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_194_CHECKER_TYPE,
154743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_194_WIDTH },
154744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_195_CHECKER_TYPE,
154745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_195_WIDTH },
154746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_196_CHECKER_TYPE,
154747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_196_WIDTH },
154748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_197_CHECKER_TYPE,
154749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_197_WIDTH },
154750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_198_CHECKER_TYPE,
154751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_198_WIDTH },
154752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_199_CHECKER_TYPE,
154753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_199_WIDTH },
154754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_200_CHECKER_TYPE,
154755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_200_WIDTH },
154756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_201_CHECKER_TYPE,
154757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_201_WIDTH },
154758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_202_CHECKER_TYPE,
154759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_202_WIDTH },
154760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_203_CHECKER_TYPE,
154761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_203_WIDTH },
154762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_204_CHECKER_TYPE,
154763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_204_WIDTH },
154764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_205_CHECKER_TYPE,
154765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_205_WIDTH },
154766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_206_CHECKER_TYPE,
154767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_206_WIDTH },
154768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_207_CHECKER_TYPE,
154769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_207_WIDTH },
154770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_208_CHECKER_TYPE,
154771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_208_WIDTH },
154772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_209_CHECKER_TYPE,
154773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_209_WIDTH },
154774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_210_CHECKER_TYPE,
154775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_210_WIDTH },
154776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_211_CHECKER_TYPE,
154777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_211_WIDTH },
154778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_212_CHECKER_TYPE,
154779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_212_WIDTH },
154780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_213_CHECKER_TYPE,
154781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_213_WIDTH },
154782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_214_CHECKER_TYPE,
154783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_214_WIDTH },
154784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_215_CHECKER_TYPE,
154785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_215_WIDTH },
154786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_216_CHECKER_TYPE,
154787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_216_WIDTH },
154788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_217_CHECKER_TYPE,
154789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_217_WIDTH },
154790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_218_CHECKER_TYPE,
154791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_218_WIDTH },
154792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_219_CHECKER_TYPE,
154793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_219_WIDTH },
154794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_220_CHECKER_TYPE,
154795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_220_WIDTH },
154796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_221_CHECKER_TYPE,
154797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_221_WIDTH },
154798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_222_CHECKER_TYPE,
154799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_222_WIDTH },
154800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_223_CHECKER_TYPE,
154801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_223_WIDTH },
154802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_224_CHECKER_TYPE,
154803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_224_WIDTH },
154804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_225_CHECKER_TYPE,
154805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_225_WIDTH },
154806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_226_CHECKER_TYPE,
154807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_226_WIDTH },
154808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_227_CHECKER_TYPE,
154809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_227_WIDTH },
154810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_228_CHECKER_TYPE,
154811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_228_WIDTH },
154812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_229_CHECKER_TYPE,
154813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_229_WIDTH },
154814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_230_CHECKER_TYPE,
154815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_230_WIDTH },
154816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_231_CHECKER_TYPE,
154817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_231_WIDTH },
154818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_232_CHECKER_TYPE,
154819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_232_WIDTH },
154820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_233_CHECKER_TYPE,
154821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_233_WIDTH },
154822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_234_CHECKER_TYPE,
154823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_234_WIDTH },
154824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_235_CHECKER_TYPE,
154825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_235_WIDTH },
154826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_236_CHECKER_TYPE,
154827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_236_WIDTH },
154828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_237_CHECKER_TYPE,
154829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_237_WIDTH },
154830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_238_CHECKER_TYPE,
154831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_238_WIDTH },
154832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_239_CHECKER_TYPE,
154833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_239_WIDTH },
154834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_240_CHECKER_TYPE,
154835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_240_WIDTH },
154836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_241_CHECKER_TYPE,
154837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_241_WIDTH },
154838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_242_CHECKER_TYPE,
154839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_242_WIDTH },
154840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_243_CHECKER_TYPE,
154841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_243_WIDTH },
154842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_244_CHECKER_TYPE,
154843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_244_WIDTH },
154844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_245_CHECKER_TYPE,
154845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_245_WIDTH },
154846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_246_CHECKER_TYPE,
154847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_246_WIDTH },
154848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_247_CHECKER_TYPE,
154849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_247_WIDTH },
154850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_248_CHECKER_TYPE,
154851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_248_WIDTH },
154852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_249_CHECKER_TYPE,
154853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_249_WIDTH },
154854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_250_CHECKER_TYPE,
154855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_250_WIDTH },
154856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_251_CHECKER_TYPE,
154857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_251_WIDTH },
154858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_252_CHECKER_TYPE,
154859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_252_WIDTH },
154860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_253_CHECKER_TYPE,
154861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_253_WIDTH },
154862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_254_CHECKER_TYPE,
154863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_254_WIDTH },
154864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_255_CHECKER_TYPE,
154865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_GROUP_255_WIDTH },
154866 };
154867 
154873 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_MAX_NUM_CHECKERS] =
154874 {
154875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_0_CHECKER_TYPE,
154876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_0_WIDTH },
154877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_1_CHECKER_TYPE,
154878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_1_WIDTH },
154879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_2_CHECKER_TYPE,
154880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_2_WIDTH },
154881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_3_CHECKER_TYPE,
154882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_3_WIDTH },
154883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_4_CHECKER_TYPE,
154884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_4_WIDTH },
154885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_5_CHECKER_TYPE,
154886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_5_WIDTH },
154887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_6_CHECKER_TYPE,
154888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_6_WIDTH },
154889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_7_CHECKER_TYPE,
154890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_7_WIDTH },
154891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_8_CHECKER_TYPE,
154892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_8_WIDTH },
154893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_9_CHECKER_TYPE,
154894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_9_WIDTH },
154895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_10_CHECKER_TYPE,
154896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_10_WIDTH },
154897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_11_CHECKER_TYPE,
154898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_11_WIDTH },
154899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_12_CHECKER_TYPE,
154900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_12_WIDTH },
154901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_13_CHECKER_TYPE,
154902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_13_WIDTH },
154903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_14_CHECKER_TYPE,
154904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_14_WIDTH },
154905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_15_CHECKER_TYPE,
154906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_15_WIDTH },
154907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_16_CHECKER_TYPE,
154908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_16_WIDTH },
154909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_17_CHECKER_TYPE,
154910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_17_WIDTH },
154911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_18_CHECKER_TYPE,
154912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_18_WIDTH },
154913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_19_CHECKER_TYPE,
154914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_19_WIDTH },
154915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_20_CHECKER_TYPE,
154916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_20_WIDTH },
154917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_21_CHECKER_TYPE,
154918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_21_WIDTH },
154919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_22_CHECKER_TYPE,
154920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_22_WIDTH },
154921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_23_CHECKER_TYPE,
154922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_23_WIDTH },
154923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_24_CHECKER_TYPE,
154924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_24_WIDTH },
154925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_25_CHECKER_TYPE,
154926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_25_WIDTH },
154927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_26_CHECKER_TYPE,
154928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_26_WIDTH },
154929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_27_CHECKER_TYPE,
154930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_27_WIDTH },
154931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_28_CHECKER_TYPE,
154932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_28_WIDTH },
154933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_29_CHECKER_TYPE,
154934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_29_WIDTH },
154935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_30_CHECKER_TYPE,
154936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_30_WIDTH },
154937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_31_CHECKER_TYPE,
154938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_31_WIDTH },
154939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_32_CHECKER_TYPE,
154940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_32_WIDTH },
154941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_33_CHECKER_TYPE,
154942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_33_WIDTH },
154943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_34_CHECKER_TYPE,
154944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_34_WIDTH },
154945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_35_CHECKER_TYPE,
154946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_35_WIDTH },
154947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_36_CHECKER_TYPE,
154948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_36_WIDTH },
154949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_37_CHECKER_TYPE,
154950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_37_WIDTH },
154951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_38_CHECKER_TYPE,
154952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_38_WIDTH },
154953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_39_CHECKER_TYPE,
154954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_39_WIDTH },
154955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_40_CHECKER_TYPE,
154956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_40_WIDTH },
154957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_41_CHECKER_TYPE,
154958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_41_WIDTH },
154959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_42_CHECKER_TYPE,
154960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_42_WIDTH },
154961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_43_CHECKER_TYPE,
154962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_43_WIDTH },
154963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_44_CHECKER_TYPE,
154964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_44_WIDTH },
154965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_45_CHECKER_TYPE,
154966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_45_WIDTH },
154967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_46_CHECKER_TYPE,
154968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_46_WIDTH },
154969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_47_CHECKER_TYPE,
154970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_47_WIDTH },
154971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_48_CHECKER_TYPE,
154972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_48_WIDTH },
154973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_49_CHECKER_TYPE,
154974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_49_WIDTH },
154975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_50_CHECKER_TYPE,
154976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_50_WIDTH },
154977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_51_CHECKER_TYPE,
154978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_51_WIDTH },
154979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_52_CHECKER_TYPE,
154980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_52_WIDTH },
154981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_53_CHECKER_TYPE,
154982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_53_WIDTH },
154983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_54_CHECKER_TYPE,
154984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_54_WIDTH },
154985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_55_CHECKER_TYPE,
154986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_55_WIDTH },
154987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_56_CHECKER_TYPE,
154988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_56_WIDTH },
154989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_57_CHECKER_TYPE,
154990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_57_WIDTH },
154991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_58_CHECKER_TYPE,
154992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_58_WIDTH },
154993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_59_CHECKER_TYPE,
154994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_59_WIDTH },
154995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_60_CHECKER_TYPE,
154996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_60_WIDTH },
154997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_61_CHECKER_TYPE,
154998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_61_WIDTH },
154999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_62_CHECKER_TYPE,
155000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_62_WIDTH },
155001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_63_CHECKER_TYPE,
155002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_63_WIDTH },
155003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_64_CHECKER_TYPE,
155004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_64_WIDTH },
155005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_65_CHECKER_TYPE,
155006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_65_WIDTH },
155007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_66_CHECKER_TYPE,
155008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_66_WIDTH },
155009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_67_CHECKER_TYPE,
155010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_67_WIDTH },
155011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_68_CHECKER_TYPE,
155012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_68_WIDTH },
155013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_69_CHECKER_TYPE,
155014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_69_WIDTH },
155015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_70_CHECKER_TYPE,
155016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_70_WIDTH },
155017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_71_CHECKER_TYPE,
155018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_71_WIDTH },
155019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_72_CHECKER_TYPE,
155020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_72_WIDTH },
155021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_73_CHECKER_TYPE,
155022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_73_WIDTH },
155023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_74_CHECKER_TYPE,
155024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_74_WIDTH },
155025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_75_CHECKER_TYPE,
155026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_75_WIDTH },
155027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_76_CHECKER_TYPE,
155028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_76_WIDTH },
155029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_77_CHECKER_TYPE,
155030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_77_WIDTH },
155031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_78_CHECKER_TYPE,
155032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_78_WIDTH },
155033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_79_CHECKER_TYPE,
155034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_79_WIDTH },
155035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_80_CHECKER_TYPE,
155036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_80_WIDTH },
155037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_81_CHECKER_TYPE,
155038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_81_WIDTH },
155039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_82_CHECKER_TYPE,
155040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_82_WIDTH },
155041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_83_CHECKER_TYPE,
155042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_83_WIDTH },
155043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_84_CHECKER_TYPE,
155044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_84_WIDTH },
155045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_85_CHECKER_TYPE,
155046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_85_WIDTH },
155047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_86_CHECKER_TYPE,
155048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_86_WIDTH },
155049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_87_CHECKER_TYPE,
155050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_87_WIDTH },
155051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_88_CHECKER_TYPE,
155052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_88_WIDTH },
155053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_89_CHECKER_TYPE,
155054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_89_WIDTH },
155055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_90_CHECKER_TYPE,
155056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_90_WIDTH },
155057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_91_CHECKER_TYPE,
155058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_91_WIDTH },
155059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_92_CHECKER_TYPE,
155060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_92_WIDTH },
155061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_93_CHECKER_TYPE,
155062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_93_WIDTH },
155063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_94_CHECKER_TYPE,
155064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_94_WIDTH },
155065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_95_CHECKER_TYPE,
155066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_95_WIDTH },
155067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_96_CHECKER_TYPE,
155068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_96_WIDTH },
155069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_97_CHECKER_TYPE,
155070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_97_WIDTH },
155071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_98_CHECKER_TYPE,
155072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_98_WIDTH },
155073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_99_CHECKER_TYPE,
155074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_99_WIDTH },
155075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_100_CHECKER_TYPE,
155076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_100_WIDTH },
155077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_101_CHECKER_TYPE,
155078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_101_WIDTH },
155079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_102_CHECKER_TYPE,
155080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_102_WIDTH },
155081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_103_CHECKER_TYPE,
155082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_103_WIDTH },
155083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_104_CHECKER_TYPE,
155084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_104_WIDTH },
155085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_105_CHECKER_TYPE,
155086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_105_WIDTH },
155087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_106_CHECKER_TYPE,
155088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_106_WIDTH },
155089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_107_CHECKER_TYPE,
155090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_107_WIDTH },
155091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_108_CHECKER_TYPE,
155092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_108_WIDTH },
155093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_109_CHECKER_TYPE,
155094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_109_WIDTH },
155095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_110_CHECKER_TYPE,
155096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_110_WIDTH },
155097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_111_CHECKER_TYPE,
155098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_111_WIDTH },
155099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_112_CHECKER_TYPE,
155100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_112_WIDTH },
155101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_113_CHECKER_TYPE,
155102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_113_WIDTH },
155103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_114_CHECKER_TYPE,
155104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_114_WIDTH },
155105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_115_CHECKER_TYPE,
155106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_115_WIDTH },
155107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_116_CHECKER_TYPE,
155108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_116_WIDTH },
155109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_117_CHECKER_TYPE,
155110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_117_WIDTH },
155111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_118_CHECKER_TYPE,
155112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_118_WIDTH },
155113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_119_CHECKER_TYPE,
155114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_119_WIDTH },
155115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_120_CHECKER_TYPE,
155116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_120_WIDTH },
155117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_121_CHECKER_TYPE,
155118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_121_WIDTH },
155119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_122_CHECKER_TYPE,
155120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_122_WIDTH },
155121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_123_CHECKER_TYPE,
155122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_123_WIDTH },
155123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_124_CHECKER_TYPE,
155124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_124_WIDTH },
155125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_125_CHECKER_TYPE,
155126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_125_WIDTH },
155127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_126_CHECKER_TYPE,
155128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_126_WIDTH },
155129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_127_CHECKER_TYPE,
155130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_127_WIDTH },
155131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_128_CHECKER_TYPE,
155132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_128_WIDTH },
155133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_129_CHECKER_TYPE,
155134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_129_WIDTH },
155135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_130_CHECKER_TYPE,
155136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_130_WIDTH },
155137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_131_CHECKER_TYPE,
155138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_131_WIDTH },
155139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_132_CHECKER_TYPE,
155140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_132_WIDTH },
155141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_133_CHECKER_TYPE,
155142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_133_WIDTH },
155143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_134_CHECKER_TYPE,
155144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_134_WIDTH },
155145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_135_CHECKER_TYPE,
155146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_135_WIDTH },
155147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_136_CHECKER_TYPE,
155148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_136_WIDTH },
155149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_137_CHECKER_TYPE,
155150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_137_WIDTH },
155151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_138_CHECKER_TYPE,
155152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_138_WIDTH },
155153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_139_CHECKER_TYPE,
155154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_139_WIDTH },
155155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_140_CHECKER_TYPE,
155156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_140_WIDTH },
155157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_141_CHECKER_TYPE,
155158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_141_WIDTH },
155159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_142_CHECKER_TYPE,
155160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_142_WIDTH },
155161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_143_CHECKER_TYPE,
155162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_143_WIDTH },
155163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_144_CHECKER_TYPE,
155164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_144_WIDTH },
155165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_145_CHECKER_TYPE,
155166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_145_WIDTH },
155167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_146_CHECKER_TYPE,
155168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_146_WIDTH },
155169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_147_CHECKER_TYPE,
155170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_147_WIDTH },
155171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_148_CHECKER_TYPE,
155172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_148_WIDTH },
155173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_149_CHECKER_TYPE,
155174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_149_WIDTH },
155175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_150_CHECKER_TYPE,
155176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_150_WIDTH },
155177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_151_CHECKER_TYPE,
155178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_151_WIDTH },
155179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_152_CHECKER_TYPE,
155180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_152_WIDTH },
155181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_153_CHECKER_TYPE,
155182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_153_WIDTH },
155183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_154_CHECKER_TYPE,
155184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_154_WIDTH },
155185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_155_CHECKER_TYPE,
155186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_155_WIDTH },
155187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_156_CHECKER_TYPE,
155188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_156_WIDTH },
155189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_157_CHECKER_TYPE,
155190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_157_WIDTH },
155191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_158_CHECKER_TYPE,
155192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_158_WIDTH },
155193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_159_CHECKER_TYPE,
155194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_159_WIDTH },
155195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_160_CHECKER_TYPE,
155196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_160_WIDTH },
155197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_161_CHECKER_TYPE,
155198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_161_WIDTH },
155199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_162_CHECKER_TYPE,
155200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_162_WIDTH },
155201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_163_CHECKER_TYPE,
155202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_163_WIDTH },
155203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_164_CHECKER_TYPE,
155204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_164_WIDTH },
155205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_165_CHECKER_TYPE,
155206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_165_WIDTH },
155207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_166_CHECKER_TYPE,
155208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_166_WIDTH },
155209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_167_CHECKER_TYPE,
155210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_167_WIDTH },
155211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_168_CHECKER_TYPE,
155212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_168_WIDTH },
155213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_169_CHECKER_TYPE,
155214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_169_WIDTH },
155215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_170_CHECKER_TYPE,
155216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_170_WIDTH },
155217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_171_CHECKER_TYPE,
155218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_171_WIDTH },
155219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_172_CHECKER_TYPE,
155220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_172_WIDTH },
155221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_173_CHECKER_TYPE,
155222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_173_WIDTH },
155223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_174_CHECKER_TYPE,
155224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_174_WIDTH },
155225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_175_CHECKER_TYPE,
155226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_175_WIDTH },
155227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_176_CHECKER_TYPE,
155228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_176_WIDTH },
155229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_177_CHECKER_TYPE,
155230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_177_WIDTH },
155231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_178_CHECKER_TYPE,
155232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_178_WIDTH },
155233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_179_CHECKER_TYPE,
155234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_179_WIDTH },
155235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_180_CHECKER_TYPE,
155236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_180_WIDTH },
155237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_181_CHECKER_TYPE,
155238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_181_WIDTH },
155239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_182_CHECKER_TYPE,
155240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_182_WIDTH },
155241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_183_CHECKER_TYPE,
155242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_183_WIDTH },
155243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_184_CHECKER_TYPE,
155244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_184_WIDTH },
155245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_185_CHECKER_TYPE,
155246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_185_WIDTH },
155247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_186_CHECKER_TYPE,
155248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_186_WIDTH },
155249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_187_CHECKER_TYPE,
155250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_187_WIDTH },
155251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_188_CHECKER_TYPE,
155252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_188_WIDTH },
155253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_189_CHECKER_TYPE,
155254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_189_WIDTH },
155255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_190_CHECKER_TYPE,
155256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_190_WIDTH },
155257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_191_CHECKER_TYPE,
155258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_191_WIDTH },
155259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_192_CHECKER_TYPE,
155260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_192_WIDTH },
155261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_193_CHECKER_TYPE,
155262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_193_WIDTH },
155263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_194_CHECKER_TYPE,
155264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_194_WIDTH },
155265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_195_CHECKER_TYPE,
155266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_195_WIDTH },
155267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_196_CHECKER_TYPE,
155268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_196_WIDTH },
155269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_197_CHECKER_TYPE,
155270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_197_WIDTH },
155271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_198_CHECKER_TYPE,
155272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_198_WIDTH },
155273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_199_CHECKER_TYPE,
155274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_199_WIDTH },
155275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_200_CHECKER_TYPE,
155276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_200_WIDTH },
155277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_201_CHECKER_TYPE,
155278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_201_WIDTH },
155279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_202_CHECKER_TYPE,
155280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_202_WIDTH },
155281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_203_CHECKER_TYPE,
155282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_203_WIDTH },
155283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_204_CHECKER_TYPE,
155284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_204_WIDTH },
155285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_205_CHECKER_TYPE,
155286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_205_WIDTH },
155287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_206_CHECKER_TYPE,
155288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_206_WIDTH },
155289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_207_CHECKER_TYPE,
155290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_207_WIDTH },
155291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_208_CHECKER_TYPE,
155292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_208_WIDTH },
155293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_209_CHECKER_TYPE,
155294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_209_WIDTH },
155295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_210_CHECKER_TYPE,
155296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_210_WIDTH },
155297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_211_CHECKER_TYPE,
155298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_211_WIDTH },
155299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_212_CHECKER_TYPE,
155300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_212_WIDTH },
155301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_213_CHECKER_TYPE,
155302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_213_WIDTH },
155303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_214_CHECKER_TYPE,
155304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_214_WIDTH },
155305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_215_CHECKER_TYPE,
155306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_215_WIDTH },
155307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_216_CHECKER_TYPE,
155308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_216_WIDTH },
155309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_217_CHECKER_TYPE,
155310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_217_WIDTH },
155311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_218_CHECKER_TYPE,
155312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_218_WIDTH },
155313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_219_CHECKER_TYPE,
155314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_219_WIDTH },
155315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_220_CHECKER_TYPE,
155316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_220_WIDTH },
155317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_221_CHECKER_TYPE,
155318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_221_WIDTH },
155319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_222_CHECKER_TYPE,
155320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_222_WIDTH },
155321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_223_CHECKER_TYPE,
155322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_223_WIDTH },
155323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_224_CHECKER_TYPE,
155324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_224_WIDTH },
155325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_225_CHECKER_TYPE,
155326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_225_WIDTH },
155327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_226_CHECKER_TYPE,
155328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_226_WIDTH },
155329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_227_CHECKER_TYPE,
155330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_227_WIDTH },
155331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_228_CHECKER_TYPE,
155332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_228_WIDTH },
155333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_229_CHECKER_TYPE,
155334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_229_WIDTH },
155335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_230_CHECKER_TYPE,
155336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_230_WIDTH },
155337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_231_CHECKER_TYPE,
155338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_231_WIDTH },
155339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_232_CHECKER_TYPE,
155340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_232_WIDTH },
155341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_233_CHECKER_TYPE,
155342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_233_WIDTH },
155343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_234_CHECKER_TYPE,
155344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_234_WIDTH },
155345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_235_CHECKER_TYPE,
155346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_235_WIDTH },
155347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_236_CHECKER_TYPE,
155348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_236_WIDTH },
155349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_237_CHECKER_TYPE,
155350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_237_WIDTH },
155351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_238_CHECKER_TYPE,
155352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_238_WIDTH },
155353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_239_CHECKER_TYPE,
155354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_239_WIDTH },
155355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_240_CHECKER_TYPE,
155356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_240_WIDTH },
155357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_241_CHECKER_TYPE,
155358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_241_WIDTH },
155359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_242_CHECKER_TYPE,
155360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_242_WIDTH },
155361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_243_CHECKER_TYPE,
155362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_243_WIDTH },
155363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_244_CHECKER_TYPE,
155364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_244_WIDTH },
155365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_245_CHECKER_TYPE,
155366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_245_WIDTH },
155367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_246_CHECKER_TYPE,
155368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_246_WIDTH },
155369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_247_CHECKER_TYPE,
155370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_247_WIDTH },
155371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_248_CHECKER_TYPE,
155372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_248_WIDTH },
155373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_249_CHECKER_TYPE,
155374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_249_WIDTH },
155375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_250_CHECKER_TYPE,
155376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_250_WIDTH },
155377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_251_CHECKER_TYPE,
155378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_251_WIDTH },
155379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_252_CHECKER_TYPE,
155380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_252_WIDTH },
155381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_253_CHECKER_TYPE,
155382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_253_WIDTH },
155383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_254_CHECKER_TYPE,
155384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_254_WIDTH },
155385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_255_CHECKER_TYPE,
155386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_GROUP_255_WIDTH },
155387 };
155388 
155394 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_MAX_NUM_CHECKERS] =
155395 {
155396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_0_CHECKER_TYPE,
155397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_0_WIDTH },
155398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_1_CHECKER_TYPE,
155399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_1_WIDTH },
155400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_2_CHECKER_TYPE,
155401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_2_WIDTH },
155402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_3_CHECKER_TYPE,
155403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_3_WIDTH },
155404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_4_CHECKER_TYPE,
155405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_4_WIDTH },
155406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_5_CHECKER_TYPE,
155407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_5_WIDTH },
155408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_6_CHECKER_TYPE,
155409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_6_WIDTH },
155410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_7_CHECKER_TYPE,
155411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_7_WIDTH },
155412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_8_CHECKER_TYPE,
155413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_8_WIDTH },
155414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_9_CHECKER_TYPE,
155415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_9_WIDTH },
155416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_10_CHECKER_TYPE,
155417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_10_WIDTH },
155418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_11_CHECKER_TYPE,
155419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_11_WIDTH },
155420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_12_CHECKER_TYPE,
155421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_12_WIDTH },
155422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_13_CHECKER_TYPE,
155423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_13_WIDTH },
155424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_14_CHECKER_TYPE,
155425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_14_WIDTH },
155426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_15_CHECKER_TYPE,
155427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_15_WIDTH },
155428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_16_CHECKER_TYPE,
155429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_16_WIDTH },
155430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_17_CHECKER_TYPE,
155431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_17_WIDTH },
155432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_18_CHECKER_TYPE,
155433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_18_WIDTH },
155434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_19_CHECKER_TYPE,
155435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_19_WIDTH },
155436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_20_CHECKER_TYPE,
155437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_20_WIDTH },
155438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_21_CHECKER_TYPE,
155439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_21_WIDTH },
155440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_22_CHECKER_TYPE,
155441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_22_WIDTH },
155442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_23_CHECKER_TYPE,
155443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_23_WIDTH },
155444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_24_CHECKER_TYPE,
155445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_24_WIDTH },
155446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_25_CHECKER_TYPE,
155447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_25_WIDTH },
155448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_26_CHECKER_TYPE,
155449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_26_WIDTH },
155450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_27_CHECKER_TYPE,
155451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_27_WIDTH },
155452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_28_CHECKER_TYPE,
155453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_28_WIDTH },
155454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_29_CHECKER_TYPE,
155455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_29_WIDTH },
155456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_30_CHECKER_TYPE,
155457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_30_WIDTH },
155458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_31_CHECKER_TYPE,
155459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_31_WIDTH },
155460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_32_CHECKER_TYPE,
155461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_32_WIDTH },
155462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_33_CHECKER_TYPE,
155463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_33_WIDTH },
155464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_34_CHECKER_TYPE,
155465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_34_WIDTH },
155466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_35_CHECKER_TYPE,
155467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_35_WIDTH },
155468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_36_CHECKER_TYPE,
155469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_36_WIDTH },
155470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_37_CHECKER_TYPE,
155471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_37_WIDTH },
155472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_38_CHECKER_TYPE,
155473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_38_WIDTH },
155474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_39_CHECKER_TYPE,
155475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_39_WIDTH },
155476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_40_CHECKER_TYPE,
155477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_40_WIDTH },
155478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_41_CHECKER_TYPE,
155479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_41_WIDTH },
155480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_42_CHECKER_TYPE,
155481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_42_WIDTH },
155482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_43_CHECKER_TYPE,
155483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_43_WIDTH },
155484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_44_CHECKER_TYPE,
155485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_44_WIDTH },
155486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_45_CHECKER_TYPE,
155487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_45_WIDTH },
155488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_46_CHECKER_TYPE,
155489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_46_WIDTH },
155490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_47_CHECKER_TYPE,
155491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_47_WIDTH },
155492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_48_CHECKER_TYPE,
155493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_48_WIDTH },
155494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_49_CHECKER_TYPE,
155495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_49_WIDTH },
155496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_50_CHECKER_TYPE,
155497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_50_WIDTH },
155498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_51_CHECKER_TYPE,
155499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_51_WIDTH },
155500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_52_CHECKER_TYPE,
155501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_52_WIDTH },
155502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_53_CHECKER_TYPE,
155503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_53_WIDTH },
155504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_54_CHECKER_TYPE,
155505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_54_WIDTH },
155506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_55_CHECKER_TYPE,
155507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_55_WIDTH },
155508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_56_CHECKER_TYPE,
155509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_56_WIDTH },
155510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_57_CHECKER_TYPE,
155511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_57_WIDTH },
155512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_58_CHECKER_TYPE,
155513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_58_WIDTH },
155514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_59_CHECKER_TYPE,
155515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_59_WIDTH },
155516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_60_CHECKER_TYPE,
155517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_60_WIDTH },
155518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_61_CHECKER_TYPE,
155519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_61_WIDTH },
155520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_62_CHECKER_TYPE,
155521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_62_WIDTH },
155522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_63_CHECKER_TYPE,
155523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_63_WIDTH },
155524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_64_CHECKER_TYPE,
155525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_64_WIDTH },
155526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_65_CHECKER_TYPE,
155527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_65_WIDTH },
155528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_66_CHECKER_TYPE,
155529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_66_WIDTH },
155530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_67_CHECKER_TYPE,
155531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_67_WIDTH },
155532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_68_CHECKER_TYPE,
155533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_68_WIDTH },
155534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_69_CHECKER_TYPE,
155535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_69_WIDTH },
155536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_70_CHECKER_TYPE,
155537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_70_WIDTH },
155538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_71_CHECKER_TYPE,
155539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_71_WIDTH },
155540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_72_CHECKER_TYPE,
155541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_72_WIDTH },
155542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_73_CHECKER_TYPE,
155543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_73_WIDTH },
155544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_74_CHECKER_TYPE,
155545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_74_WIDTH },
155546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_75_CHECKER_TYPE,
155547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_75_WIDTH },
155548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_76_CHECKER_TYPE,
155549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_76_WIDTH },
155550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_77_CHECKER_TYPE,
155551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_77_WIDTH },
155552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_78_CHECKER_TYPE,
155553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_78_WIDTH },
155554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_79_CHECKER_TYPE,
155555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_79_WIDTH },
155556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_80_CHECKER_TYPE,
155557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_80_WIDTH },
155558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_81_CHECKER_TYPE,
155559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_81_WIDTH },
155560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_82_CHECKER_TYPE,
155561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_82_WIDTH },
155562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_83_CHECKER_TYPE,
155563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_83_WIDTH },
155564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_84_CHECKER_TYPE,
155565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_84_WIDTH },
155566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_85_CHECKER_TYPE,
155567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_85_WIDTH },
155568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_86_CHECKER_TYPE,
155569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_86_WIDTH },
155570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_87_CHECKER_TYPE,
155571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_87_WIDTH },
155572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_88_CHECKER_TYPE,
155573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_88_WIDTH },
155574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_89_CHECKER_TYPE,
155575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_89_WIDTH },
155576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_90_CHECKER_TYPE,
155577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_90_WIDTH },
155578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_91_CHECKER_TYPE,
155579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_91_WIDTH },
155580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_92_CHECKER_TYPE,
155581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_92_WIDTH },
155582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_93_CHECKER_TYPE,
155583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_93_WIDTH },
155584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_94_CHECKER_TYPE,
155585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_94_WIDTH },
155586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_95_CHECKER_TYPE,
155587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_95_WIDTH },
155588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_96_CHECKER_TYPE,
155589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_96_WIDTH },
155590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_97_CHECKER_TYPE,
155591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_97_WIDTH },
155592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_98_CHECKER_TYPE,
155593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_98_WIDTH },
155594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_99_CHECKER_TYPE,
155595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_99_WIDTH },
155596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_100_CHECKER_TYPE,
155597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_100_WIDTH },
155598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_101_CHECKER_TYPE,
155599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_101_WIDTH },
155600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_102_CHECKER_TYPE,
155601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_102_WIDTH },
155602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_103_CHECKER_TYPE,
155603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_103_WIDTH },
155604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_104_CHECKER_TYPE,
155605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_104_WIDTH },
155606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_105_CHECKER_TYPE,
155607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_105_WIDTH },
155608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_106_CHECKER_TYPE,
155609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_106_WIDTH },
155610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_107_CHECKER_TYPE,
155611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_107_WIDTH },
155612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_108_CHECKER_TYPE,
155613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_108_WIDTH },
155614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_109_CHECKER_TYPE,
155615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_109_WIDTH },
155616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_110_CHECKER_TYPE,
155617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_110_WIDTH },
155618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_111_CHECKER_TYPE,
155619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_111_WIDTH },
155620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_112_CHECKER_TYPE,
155621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_112_WIDTH },
155622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_113_CHECKER_TYPE,
155623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_113_WIDTH },
155624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_114_CHECKER_TYPE,
155625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_114_WIDTH },
155626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_115_CHECKER_TYPE,
155627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_115_WIDTH },
155628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_116_CHECKER_TYPE,
155629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_116_WIDTH },
155630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_117_CHECKER_TYPE,
155631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_117_WIDTH },
155632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_118_CHECKER_TYPE,
155633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_118_WIDTH },
155634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_119_CHECKER_TYPE,
155635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_119_WIDTH },
155636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_120_CHECKER_TYPE,
155637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_120_WIDTH },
155638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_121_CHECKER_TYPE,
155639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_121_WIDTH },
155640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_122_CHECKER_TYPE,
155641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_122_WIDTH },
155642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_123_CHECKER_TYPE,
155643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_123_WIDTH },
155644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_124_CHECKER_TYPE,
155645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_124_WIDTH },
155646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_125_CHECKER_TYPE,
155647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_125_WIDTH },
155648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_126_CHECKER_TYPE,
155649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_126_WIDTH },
155650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_127_CHECKER_TYPE,
155651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_127_WIDTH },
155652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_128_CHECKER_TYPE,
155653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_128_WIDTH },
155654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_129_CHECKER_TYPE,
155655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_129_WIDTH },
155656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_130_CHECKER_TYPE,
155657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_130_WIDTH },
155658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_131_CHECKER_TYPE,
155659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_131_WIDTH },
155660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_132_CHECKER_TYPE,
155661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_132_WIDTH },
155662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_133_CHECKER_TYPE,
155663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_133_WIDTH },
155664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_134_CHECKER_TYPE,
155665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_134_WIDTH },
155666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_135_CHECKER_TYPE,
155667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_135_WIDTH },
155668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_136_CHECKER_TYPE,
155669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_136_WIDTH },
155670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_137_CHECKER_TYPE,
155671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_137_WIDTH },
155672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_138_CHECKER_TYPE,
155673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_138_WIDTH },
155674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_139_CHECKER_TYPE,
155675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_139_WIDTH },
155676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_140_CHECKER_TYPE,
155677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_140_WIDTH },
155678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_141_CHECKER_TYPE,
155679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_141_WIDTH },
155680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_142_CHECKER_TYPE,
155681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_142_WIDTH },
155682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_143_CHECKER_TYPE,
155683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_143_WIDTH },
155684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_144_CHECKER_TYPE,
155685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_144_WIDTH },
155686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_145_CHECKER_TYPE,
155687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_145_WIDTH },
155688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_146_CHECKER_TYPE,
155689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_146_WIDTH },
155690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_147_CHECKER_TYPE,
155691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_147_WIDTH },
155692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_148_CHECKER_TYPE,
155693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_148_WIDTH },
155694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_149_CHECKER_TYPE,
155695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_149_WIDTH },
155696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_150_CHECKER_TYPE,
155697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_150_WIDTH },
155698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_151_CHECKER_TYPE,
155699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_151_WIDTH },
155700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_152_CHECKER_TYPE,
155701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_152_WIDTH },
155702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_153_CHECKER_TYPE,
155703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_153_WIDTH },
155704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_154_CHECKER_TYPE,
155705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_154_WIDTH },
155706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_155_CHECKER_TYPE,
155707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_155_WIDTH },
155708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_156_CHECKER_TYPE,
155709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_156_WIDTH },
155710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_157_CHECKER_TYPE,
155711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_157_WIDTH },
155712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_158_CHECKER_TYPE,
155713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_158_WIDTH },
155714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_159_CHECKER_TYPE,
155715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_159_WIDTH },
155716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_160_CHECKER_TYPE,
155717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_160_WIDTH },
155718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_161_CHECKER_TYPE,
155719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_161_WIDTH },
155720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_162_CHECKER_TYPE,
155721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_162_WIDTH },
155722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_163_CHECKER_TYPE,
155723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_163_WIDTH },
155724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_164_CHECKER_TYPE,
155725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_164_WIDTH },
155726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_165_CHECKER_TYPE,
155727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_165_WIDTH },
155728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_166_CHECKER_TYPE,
155729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_166_WIDTH },
155730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_167_CHECKER_TYPE,
155731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_167_WIDTH },
155732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_168_CHECKER_TYPE,
155733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_168_WIDTH },
155734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_169_CHECKER_TYPE,
155735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_169_WIDTH },
155736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_170_CHECKER_TYPE,
155737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_170_WIDTH },
155738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_171_CHECKER_TYPE,
155739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_171_WIDTH },
155740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_172_CHECKER_TYPE,
155741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_172_WIDTH },
155742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_173_CHECKER_TYPE,
155743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_173_WIDTH },
155744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_174_CHECKER_TYPE,
155745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_174_WIDTH },
155746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_175_CHECKER_TYPE,
155747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_175_WIDTH },
155748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_176_CHECKER_TYPE,
155749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_176_WIDTH },
155750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_177_CHECKER_TYPE,
155751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_177_WIDTH },
155752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_178_CHECKER_TYPE,
155753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_178_WIDTH },
155754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_179_CHECKER_TYPE,
155755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_179_WIDTH },
155756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_180_CHECKER_TYPE,
155757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_180_WIDTH },
155758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_181_CHECKER_TYPE,
155759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_181_WIDTH },
155760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_182_CHECKER_TYPE,
155761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_182_WIDTH },
155762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_183_CHECKER_TYPE,
155763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_183_WIDTH },
155764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_184_CHECKER_TYPE,
155765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_184_WIDTH },
155766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_185_CHECKER_TYPE,
155767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_185_WIDTH },
155768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_186_CHECKER_TYPE,
155769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_186_WIDTH },
155770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_187_CHECKER_TYPE,
155771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_187_WIDTH },
155772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_188_CHECKER_TYPE,
155773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_188_WIDTH },
155774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_189_CHECKER_TYPE,
155775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_189_WIDTH },
155776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_190_CHECKER_TYPE,
155777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_190_WIDTH },
155778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_191_CHECKER_TYPE,
155779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_191_WIDTH },
155780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_192_CHECKER_TYPE,
155781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_192_WIDTH },
155782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_193_CHECKER_TYPE,
155783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_193_WIDTH },
155784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_194_CHECKER_TYPE,
155785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_194_WIDTH },
155786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_195_CHECKER_TYPE,
155787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_195_WIDTH },
155788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_196_CHECKER_TYPE,
155789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_196_WIDTH },
155790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_197_CHECKER_TYPE,
155791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_197_WIDTH },
155792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_198_CHECKER_TYPE,
155793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_198_WIDTH },
155794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_199_CHECKER_TYPE,
155795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_199_WIDTH },
155796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_200_CHECKER_TYPE,
155797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_200_WIDTH },
155798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_201_CHECKER_TYPE,
155799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_201_WIDTH },
155800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_202_CHECKER_TYPE,
155801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_202_WIDTH },
155802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_203_CHECKER_TYPE,
155803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_203_WIDTH },
155804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_204_CHECKER_TYPE,
155805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_204_WIDTH },
155806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_205_CHECKER_TYPE,
155807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_205_WIDTH },
155808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_206_CHECKER_TYPE,
155809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_206_WIDTH },
155810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_207_CHECKER_TYPE,
155811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_207_WIDTH },
155812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_208_CHECKER_TYPE,
155813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_208_WIDTH },
155814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_209_CHECKER_TYPE,
155815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_209_WIDTH },
155816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_210_CHECKER_TYPE,
155817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_210_WIDTH },
155818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_211_CHECKER_TYPE,
155819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_211_WIDTH },
155820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_212_CHECKER_TYPE,
155821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_212_WIDTH },
155822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_213_CHECKER_TYPE,
155823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_213_WIDTH },
155824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_214_CHECKER_TYPE,
155825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_214_WIDTH },
155826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_215_CHECKER_TYPE,
155827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_215_WIDTH },
155828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_216_CHECKER_TYPE,
155829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_216_WIDTH },
155830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_217_CHECKER_TYPE,
155831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_217_WIDTH },
155832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_218_CHECKER_TYPE,
155833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_218_WIDTH },
155834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_219_CHECKER_TYPE,
155835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_219_WIDTH },
155836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_220_CHECKER_TYPE,
155837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_220_WIDTH },
155838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_221_CHECKER_TYPE,
155839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_221_WIDTH },
155840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_222_CHECKER_TYPE,
155841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_222_WIDTH },
155842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_223_CHECKER_TYPE,
155843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_223_WIDTH },
155844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_224_CHECKER_TYPE,
155845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_224_WIDTH },
155846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_225_CHECKER_TYPE,
155847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_225_WIDTH },
155848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_226_CHECKER_TYPE,
155849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_226_WIDTH },
155850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_227_CHECKER_TYPE,
155851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_227_WIDTH },
155852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_228_CHECKER_TYPE,
155853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_228_WIDTH },
155854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_229_CHECKER_TYPE,
155855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_229_WIDTH },
155856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_230_CHECKER_TYPE,
155857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_230_WIDTH },
155858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_231_CHECKER_TYPE,
155859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_231_WIDTH },
155860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_232_CHECKER_TYPE,
155861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_232_WIDTH },
155862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_233_CHECKER_TYPE,
155863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_233_WIDTH },
155864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_234_CHECKER_TYPE,
155865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_234_WIDTH },
155866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_235_CHECKER_TYPE,
155867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_235_WIDTH },
155868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_236_CHECKER_TYPE,
155869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_236_WIDTH },
155870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_237_CHECKER_TYPE,
155871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_237_WIDTH },
155872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_238_CHECKER_TYPE,
155873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_238_WIDTH },
155874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_239_CHECKER_TYPE,
155875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_239_WIDTH },
155876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_240_CHECKER_TYPE,
155877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_240_WIDTH },
155878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_241_CHECKER_TYPE,
155879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_241_WIDTH },
155880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_242_CHECKER_TYPE,
155881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_242_WIDTH },
155882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_243_CHECKER_TYPE,
155883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_243_WIDTH },
155884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_244_CHECKER_TYPE,
155885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_244_WIDTH },
155886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_245_CHECKER_TYPE,
155887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_245_WIDTH },
155888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_246_CHECKER_TYPE,
155889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_246_WIDTH },
155890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_247_CHECKER_TYPE,
155891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_247_WIDTH },
155892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_248_CHECKER_TYPE,
155893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_248_WIDTH },
155894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_249_CHECKER_TYPE,
155895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_249_WIDTH },
155896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_250_CHECKER_TYPE,
155897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_250_WIDTH },
155898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_251_CHECKER_TYPE,
155899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_251_WIDTH },
155900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_252_CHECKER_TYPE,
155901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_252_WIDTH },
155902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_253_CHECKER_TYPE,
155903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_253_WIDTH },
155904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_254_CHECKER_TYPE,
155905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_254_WIDTH },
155906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_255_CHECKER_TYPE,
155907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_GROUP_255_WIDTH },
155908 };
155909 
155915 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_MAX_NUM_CHECKERS] =
155916 {
155917  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_0_CHECKER_TYPE,
155918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_0_WIDTH },
155919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_1_CHECKER_TYPE,
155920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_1_WIDTH },
155921  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_2_CHECKER_TYPE,
155922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_2_WIDTH },
155923  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_3_CHECKER_TYPE,
155924  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_3_WIDTH },
155925  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_4_CHECKER_TYPE,
155926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_4_WIDTH },
155927  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_5_CHECKER_TYPE,
155928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_5_WIDTH },
155929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_6_CHECKER_TYPE,
155930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_6_WIDTH },
155931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_7_CHECKER_TYPE,
155932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_7_WIDTH },
155933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_8_CHECKER_TYPE,
155934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_8_WIDTH },
155935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_9_CHECKER_TYPE,
155936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_9_WIDTH },
155937  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_10_CHECKER_TYPE,
155938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_10_WIDTH },
155939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_11_CHECKER_TYPE,
155940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_11_WIDTH },
155941  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_12_CHECKER_TYPE,
155942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_12_WIDTH },
155943  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_13_CHECKER_TYPE,
155944  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_13_WIDTH },
155945  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_14_CHECKER_TYPE,
155946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_14_WIDTH },
155947  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_15_CHECKER_TYPE,
155948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_15_WIDTH },
155949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_16_CHECKER_TYPE,
155950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_16_WIDTH },
155951  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_17_CHECKER_TYPE,
155952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_17_WIDTH },
155953  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_18_CHECKER_TYPE,
155954  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_18_WIDTH },
155955  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_19_CHECKER_TYPE,
155956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_19_WIDTH },
155957  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_20_CHECKER_TYPE,
155958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_20_WIDTH },
155959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_21_CHECKER_TYPE,
155960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_21_WIDTH },
155961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_22_CHECKER_TYPE,
155962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_22_WIDTH },
155963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_23_CHECKER_TYPE,
155964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_23_WIDTH },
155965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_24_CHECKER_TYPE,
155966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_24_WIDTH },
155967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_25_CHECKER_TYPE,
155968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_25_WIDTH },
155969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_26_CHECKER_TYPE,
155970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_26_WIDTH },
155971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_27_CHECKER_TYPE,
155972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_27_WIDTH },
155973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_28_CHECKER_TYPE,
155974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_28_WIDTH },
155975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_29_CHECKER_TYPE,
155976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_29_WIDTH },
155977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_30_CHECKER_TYPE,
155978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_30_WIDTH },
155979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_31_CHECKER_TYPE,
155980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_31_WIDTH },
155981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_32_CHECKER_TYPE,
155982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_32_WIDTH },
155983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_33_CHECKER_TYPE,
155984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_33_WIDTH },
155985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_34_CHECKER_TYPE,
155986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_34_WIDTH },
155987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_35_CHECKER_TYPE,
155988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_35_WIDTH },
155989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_36_CHECKER_TYPE,
155990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_36_WIDTH },
155991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_37_CHECKER_TYPE,
155992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_37_WIDTH },
155993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_38_CHECKER_TYPE,
155994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_38_WIDTH },
155995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_39_CHECKER_TYPE,
155996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_39_WIDTH },
155997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_40_CHECKER_TYPE,
155998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_40_WIDTH },
155999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_41_CHECKER_TYPE,
156000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_41_WIDTH },
156001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_42_CHECKER_TYPE,
156002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_42_WIDTH },
156003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_43_CHECKER_TYPE,
156004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_43_WIDTH },
156005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_44_CHECKER_TYPE,
156006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_44_WIDTH },
156007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_45_CHECKER_TYPE,
156008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_45_WIDTH },
156009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_46_CHECKER_TYPE,
156010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_46_WIDTH },
156011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_47_CHECKER_TYPE,
156012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_47_WIDTH },
156013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_48_CHECKER_TYPE,
156014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_48_WIDTH },
156015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_49_CHECKER_TYPE,
156016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_49_WIDTH },
156017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_50_CHECKER_TYPE,
156018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_50_WIDTH },
156019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_51_CHECKER_TYPE,
156020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_51_WIDTH },
156021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_52_CHECKER_TYPE,
156022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_52_WIDTH },
156023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_53_CHECKER_TYPE,
156024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_53_WIDTH },
156025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_54_CHECKER_TYPE,
156026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_54_WIDTH },
156027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_55_CHECKER_TYPE,
156028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_55_WIDTH },
156029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_56_CHECKER_TYPE,
156030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_56_WIDTH },
156031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_57_CHECKER_TYPE,
156032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_57_WIDTH },
156033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_58_CHECKER_TYPE,
156034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_58_WIDTH },
156035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_59_CHECKER_TYPE,
156036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_59_WIDTH },
156037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_60_CHECKER_TYPE,
156038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_60_WIDTH },
156039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_61_CHECKER_TYPE,
156040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_61_WIDTH },
156041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_62_CHECKER_TYPE,
156042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_62_WIDTH },
156043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_63_CHECKER_TYPE,
156044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_63_WIDTH },
156045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_64_CHECKER_TYPE,
156046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_64_WIDTH },
156047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_65_CHECKER_TYPE,
156048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_65_WIDTH },
156049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_66_CHECKER_TYPE,
156050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_66_WIDTH },
156051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_67_CHECKER_TYPE,
156052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_67_WIDTH },
156053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_68_CHECKER_TYPE,
156054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_68_WIDTH },
156055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_69_CHECKER_TYPE,
156056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_69_WIDTH },
156057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_70_CHECKER_TYPE,
156058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_70_WIDTH },
156059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_71_CHECKER_TYPE,
156060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_71_WIDTH },
156061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_72_CHECKER_TYPE,
156062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_72_WIDTH },
156063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_73_CHECKER_TYPE,
156064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_73_WIDTH },
156065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_74_CHECKER_TYPE,
156066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_74_WIDTH },
156067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_75_CHECKER_TYPE,
156068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_75_WIDTH },
156069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_76_CHECKER_TYPE,
156070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_76_WIDTH },
156071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_77_CHECKER_TYPE,
156072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_77_WIDTH },
156073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_78_CHECKER_TYPE,
156074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_78_WIDTH },
156075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_79_CHECKER_TYPE,
156076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_79_WIDTH },
156077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_80_CHECKER_TYPE,
156078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_80_WIDTH },
156079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_81_CHECKER_TYPE,
156080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_81_WIDTH },
156081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_82_CHECKER_TYPE,
156082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_82_WIDTH },
156083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_83_CHECKER_TYPE,
156084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_83_WIDTH },
156085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_84_CHECKER_TYPE,
156086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_84_WIDTH },
156087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_85_CHECKER_TYPE,
156088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_85_WIDTH },
156089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_86_CHECKER_TYPE,
156090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_86_WIDTH },
156091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_87_CHECKER_TYPE,
156092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_87_WIDTH },
156093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_88_CHECKER_TYPE,
156094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_88_WIDTH },
156095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_89_CHECKER_TYPE,
156096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_89_WIDTH },
156097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_90_CHECKER_TYPE,
156098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_90_WIDTH },
156099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_91_CHECKER_TYPE,
156100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_91_WIDTH },
156101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_92_CHECKER_TYPE,
156102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_92_WIDTH },
156103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_93_CHECKER_TYPE,
156104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_93_WIDTH },
156105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_94_CHECKER_TYPE,
156106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_94_WIDTH },
156107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_95_CHECKER_TYPE,
156108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_95_WIDTH },
156109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_96_CHECKER_TYPE,
156110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_96_WIDTH },
156111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_97_CHECKER_TYPE,
156112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_97_WIDTH },
156113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_98_CHECKER_TYPE,
156114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_98_WIDTH },
156115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_99_CHECKER_TYPE,
156116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_99_WIDTH },
156117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_100_CHECKER_TYPE,
156118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_100_WIDTH },
156119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_101_CHECKER_TYPE,
156120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_101_WIDTH },
156121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_102_CHECKER_TYPE,
156122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_102_WIDTH },
156123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_103_CHECKER_TYPE,
156124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_103_WIDTH },
156125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_104_CHECKER_TYPE,
156126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_104_WIDTH },
156127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_105_CHECKER_TYPE,
156128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_105_WIDTH },
156129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_106_CHECKER_TYPE,
156130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_106_WIDTH },
156131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_107_CHECKER_TYPE,
156132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_107_WIDTH },
156133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_108_CHECKER_TYPE,
156134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_108_WIDTH },
156135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_109_CHECKER_TYPE,
156136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_109_WIDTH },
156137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_110_CHECKER_TYPE,
156138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_110_WIDTH },
156139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_111_CHECKER_TYPE,
156140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_111_WIDTH },
156141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_112_CHECKER_TYPE,
156142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_112_WIDTH },
156143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_113_CHECKER_TYPE,
156144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_113_WIDTH },
156145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_114_CHECKER_TYPE,
156146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_114_WIDTH },
156147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_115_CHECKER_TYPE,
156148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_115_WIDTH },
156149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_116_CHECKER_TYPE,
156150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_116_WIDTH },
156151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_117_CHECKER_TYPE,
156152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_117_WIDTH },
156153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_118_CHECKER_TYPE,
156154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_118_WIDTH },
156155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_119_CHECKER_TYPE,
156156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_119_WIDTH },
156157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_120_CHECKER_TYPE,
156158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_120_WIDTH },
156159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_121_CHECKER_TYPE,
156160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_121_WIDTH },
156161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_122_CHECKER_TYPE,
156162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_122_WIDTH },
156163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_123_CHECKER_TYPE,
156164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_123_WIDTH },
156165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_124_CHECKER_TYPE,
156166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_124_WIDTH },
156167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_125_CHECKER_TYPE,
156168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_125_WIDTH },
156169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_126_CHECKER_TYPE,
156170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_126_WIDTH },
156171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_127_CHECKER_TYPE,
156172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_127_WIDTH },
156173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_128_CHECKER_TYPE,
156174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_128_WIDTH },
156175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_129_CHECKER_TYPE,
156176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_129_WIDTH },
156177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_130_CHECKER_TYPE,
156178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_130_WIDTH },
156179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_131_CHECKER_TYPE,
156180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_131_WIDTH },
156181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_132_CHECKER_TYPE,
156182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_132_WIDTH },
156183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_133_CHECKER_TYPE,
156184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_133_WIDTH },
156185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_134_CHECKER_TYPE,
156186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_134_WIDTH },
156187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_135_CHECKER_TYPE,
156188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_135_WIDTH },
156189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_136_CHECKER_TYPE,
156190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_136_WIDTH },
156191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_137_CHECKER_TYPE,
156192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_137_WIDTH },
156193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_138_CHECKER_TYPE,
156194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_138_WIDTH },
156195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_139_CHECKER_TYPE,
156196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_139_WIDTH },
156197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_140_CHECKER_TYPE,
156198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_140_WIDTH },
156199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_141_CHECKER_TYPE,
156200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_141_WIDTH },
156201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_142_CHECKER_TYPE,
156202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_142_WIDTH },
156203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_143_CHECKER_TYPE,
156204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_143_WIDTH },
156205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_144_CHECKER_TYPE,
156206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_144_WIDTH },
156207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_145_CHECKER_TYPE,
156208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_145_WIDTH },
156209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_146_CHECKER_TYPE,
156210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_146_WIDTH },
156211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_147_CHECKER_TYPE,
156212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_147_WIDTH },
156213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_148_CHECKER_TYPE,
156214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_148_WIDTH },
156215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_149_CHECKER_TYPE,
156216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_149_WIDTH },
156217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_150_CHECKER_TYPE,
156218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_150_WIDTH },
156219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_151_CHECKER_TYPE,
156220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_151_WIDTH },
156221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_152_CHECKER_TYPE,
156222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_152_WIDTH },
156223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_153_CHECKER_TYPE,
156224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_153_WIDTH },
156225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_154_CHECKER_TYPE,
156226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_154_WIDTH },
156227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_155_CHECKER_TYPE,
156228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_155_WIDTH },
156229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_156_CHECKER_TYPE,
156230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_156_WIDTH },
156231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_157_CHECKER_TYPE,
156232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_157_WIDTH },
156233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_158_CHECKER_TYPE,
156234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_158_WIDTH },
156235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_159_CHECKER_TYPE,
156236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_159_WIDTH },
156237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_160_CHECKER_TYPE,
156238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_160_WIDTH },
156239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_161_CHECKER_TYPE,
156240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_161_WIDTH },
156241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_162_CHECKER_TYPE,
156242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_162_WIDTH },
156243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_163_CHECKER_TYPE,
156244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_163_WIDTH },
156245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_164_CHECKER_TYPE,
156246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_164_WIDTH },
156247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_165_CHECKER_TYPE,
156248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_165_WIDTH },
156249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_166_CHECKER_TYPE,
156250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_166_WIDTH },
156251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_167_CHECKER_TYPE,
156252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_167_WIDTH },
156253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_168_CHECKER_TYPE,
156254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_168_WIDTH },
156255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_169_CHECKER_TYPE,
156256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_169_WIDTH },
156257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_170_CHECKER_TYPE,
156258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_170_WIDTH },
156259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_171_CHECKER_TYPE,
156260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_171_WIDTH },
156261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_172_CHECKER_TYPE,
156262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_172_WIDTH },
156263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_173_CHECKER_TYPE,
156264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_173_WIDTH },
156265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_174_CHECKER_TYPE,
156266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_174_WIDTH },
156267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_175_CHECKER_TYPE,
156268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_175_WIDTH },
156269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_176_CHECKER_TYPE,
156270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_176_WIDTH },
156271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_177_CHECKER_TYPE,
156272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_177_WIDTH },
156273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_178_CHECKER_TYPE,
156274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_178_WIDTH },
156275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_179_CHECKER_TYPE,
156276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_179_WIDTH },
156277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_180_CHECKER_TYPE,
156278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_180_WIDTH },
156279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_181_CHECKER_TYPE,
156280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_181_WIDTH },
156281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_182_CHECKER_TYPE,
156282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_182_WIDTH },
156283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_183_CHECKER_TYPE,
156284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_183_WIDTH },
156285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_184_CHECKER_TYPE,
156286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_184_WIDTH },
156287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_185_CHECKER_TYPE,
156288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_185_WIDTH },
156289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_186_CHECKER_TYPE,
156290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_186_WIDTH },
156291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_187_CHECKER_TYPE,
156292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_187_WIDTH },
156293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_188_CHECKER_TYPE,
156294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_188_WIDTH },
156295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_189_CHECKER_TYPE,
156296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_189_WIDTH },
156297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_190_CHECKER_TYPE,
156298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_190_WIDTH },
156299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_191_CHECKER_TYPE,
156300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_191_WIDTH },
156301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_192_CHECKER_TYPE,
156302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_192_WIDTH },
156303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_193_CHECKER_TYPE,
156304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_193_WIDTH },
156305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_194_CHECKER_TYPE,
156306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_194_WIDTH },
156307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_195_CHECKER_TYPE,
156308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_195_WIDTH },
156309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_196_CHECKER_TYPE,
156310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_196_WIDTH },
156311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_197_CHECKER_TYPE,
156312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_197_WIDTH },
156313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_198_CHECKER_TYPE,
156314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_198_WIDTH },
156315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_199_CHECKER_TYPE,
156316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_199_WIDTH },
156317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_200_CHECKER_TYPE,
156318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_200_WIDTH },
156319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_201_CHECKER_TYPE,
156320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_201_WIDTH },
156321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_202_CHECKER_TYPE,
156322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_202_WIDTH },
156323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_203_CHECKER_TYPE,
156324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_203_WIDTH },
156325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_204_CHECKER_TYPE,
156326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_204_WIDTH },
156327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_205_CHECKER_TYPE,
156328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_205_WIDTH },
156329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_206_CHECKER_TYPE,
156330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_206_WIDTH },
156331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_207_CHECKER_TYPE,
156332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_207_WIDTH },
156333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_208_CHECKER_TYPE,
156334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_208_WIDTH },
156335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_209_CHECKER_TYPE,
156336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_209_WIDTH },
156337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_210_CHECKER_TYPE,
156338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_210_WIDTH },
156339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_211_CHECKER_TYPE,
156340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_211_WIDTH },
156341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_212_CHECKER_TYPE,
156342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_212_WIDTH },
156343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_213_CHECKER_TYPE,
156344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_213_WIDTH },
156345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_214_CHECKER_TYPE,
156346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_214_WIDTH },
156347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_215_CHECKER_TYPE,
156348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_215_WIDTH },
156349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_216_CHECKER_TYPE,
156350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_216_WIDTH },
156351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_217_CHECKER_TYPE,
156352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_217_WIDTH },
156353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_218_CHECKER_TYPE,
156354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_218_WIDTH },
156355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_219_CHECKER_TYPE,
156356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_219_WIDTH },
156357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_220_CHECKER_TYPE,
156358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_220_WIDTH },
156359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_221_CHECKER_TYPE,
156360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_221_WIDTH },
156361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_222_CHECKER_TYPE,
156362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_222_WIDTH },
156363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_223_CHECKER_TYPE,
156364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_223_WIDTH },
156365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_224_CHECKER_TYPE,
156366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_224_WIDTH },
156367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_225_CHECKER_TYPE,
156368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_225_WIDTH },
156369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_226_CHECKER_TYPE,
156370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_226_WIDTH },
156371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_227_CHECKER_TYPE,
156372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_227_WIDTH },
156373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_228_CHECKER_TYPE,
156374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_228_WIDTH },
156375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_229_CHECKER_TYPE,
156376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_229_WIDTH },
156377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_230_CHECKER_TYPE,
156378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_230_WIDTH },
156379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_231_CHECKER_TYPE,
156380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_231_WIDTH },
156381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_232_CHECKER_TYPE,
156382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_232_WIDTH },
156383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_233_CHECKER_TYPE,
156384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_233_WIDTH },
156385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_234_CHECKER_TYPE,
156386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_234_WIDTH },
156387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_235_CHECKER_TYPE,
156388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_235_WIDTH },
156389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_236_CHECKER_TYPE,
156390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_236_WIDTH },
156391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_237_CHECKER_TYPE,
156392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_237_WIDTH },
156393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_238_CHECKER_TYPE,
156394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_238_WIDTH },
156395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_239_CHECKER_TYPE,
156396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_239_WIDTH },
156397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_240_CHECKER_TYPE,
156398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_240_WIDTH },
156399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_241_CHECKER_TYPE,
156400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_241_WIDTH },
156401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_242_CHECKER_TYPE,
156402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_242_WIDTH },
156403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_243_CHECKER_TYPE,
156404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_243_WIDTH },
156405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_244_CHECKER_TYPE,
156406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_244_WIDTH },
156407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_245_CHECKER_TYPE,
156408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_245_WIDTH },
156409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_246_CHECKER_TYPE,
156410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_246_WIDTH },
156411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_247_CHECKER_TYPE,
156412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_247_WIDTH },
156413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_248_CHECKER_TYPE,
156414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_248_WIDTH },
156415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_249_CHECKER_TYPE,
156416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_249_WIDTH },
156417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_250_CHECKER_TYPE,
156418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_250_WIDTH },
156419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_251_CHECKER_TYPE,
156420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_251_WIDTH },
156421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_252_CHECKER_TYPE,
156422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_252_WIDTH },
156423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_253_CHECKER_TYPE,
156424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_253_WIDTH },
156425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_254_CHECKER_TYPE,
156426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_254_WIDTH },
156427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_255_CHECKER_TYPE,
156428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_GROUP_255_WIDTH },
156429 };
156430 
156436 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_MAX_NUM_CHECKERS] =
156437 {
156438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_0_CHECKER_TYPE,
156439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_0_WIDTH },
156440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_1_CHECKER_TYPE,
156441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_1_WIDTH },
156442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_2_CHECKER_TYPE,
156443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_2_WIDTH },
156444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_3_CHECKER_TYPE,
156445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_3_WIDTH },
156446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_4_CHECKER_TYPE,
156447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_4_WIDTH },
156448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_5_CHECKER_TYPE,
156449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_5_WIDTH },
156450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_6_CHECKER_TYPE,
156451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_6_WIDTH },
156452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_7_CHECKER_TYPE,
156453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_7_WIDTH },
156454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_8_CHECKER_TYPE,
156455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_8_WIDTH },
156456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_9_CHECKER_TYPE,
156457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_9_WIDTH },
156458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_10_CHECKER_TYPE,
156459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_10_WIDTH },
156460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_11_CHECKER_TYPE,
156461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_11_WIDTH },
156462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_12_CHECKER_TYPE,
156463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_12_WIDTH },
156464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_13_CHECKER_TYPE,
156465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_13_WIDTH },
156466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_14_CHECKER_TYPE,
156467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_14_WIDTH },
156468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_15_CHECKER_TYPE,
156469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_15_WIDTH },
156470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_16_CHECKER_TYPE,
156471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_16_WIDTH },
156472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_17_CHECKER_TYPE,
156473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_17_WIDTH },
156474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_18_CHECKER_TYPE,
156475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_18_WIDTH },
156476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_19_CHECKER_TYPE,
156477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_19_WIDTH },
156478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_20_CHECKER_TYPE,
156479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_20_WIDTH },
156480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_21_CHECKER_TYPE,
156481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_21_WIDTH },
156482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_22_CHECKER_TYPE,
156483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_22_WIDTH },
156484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_23_CHECKER_TYPE,
156485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_23_WIDTH },
156486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_24_CHECKER_TYPE,
156487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_24_WIDTH },
156488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_25_CHECKER_TYPE,
156489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_25_WIDTH },
156490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_26_CHECKER_TYPE,
156491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_26_WIDTH },
156492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_27_CHECKER_TYPE,
156493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_27_WIDTH },
156494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_28_CHECKER_TYPE,
156495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_28_WIDTH },
156496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_29_CHECKER_TYPE,
156497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_29_WIDTH },
156498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_30_CHECKER_TYPE,
156499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_30_WIDTH },
156500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_31_CHECKER_TYPE,
156501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_31_WIDTH },
156502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_32_CHECKER_TYPE,
156503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_32_WIDTH },
156504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_33_CHECKER_TYPE,
156505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_33_WIDTH },
156506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_34_CHECKER_TYPE,
156507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_34_WIDTH },
156508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_35_CHECKER_TYPE,
156509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_35_WIDTH },
156510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_36_CHECKER_TYPE,
156511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_36_WIDTH },
156512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_37_CHECKER_TYPE,
156513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_37_WIDTH },
156514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_38_CHECKER_TYPE,
156515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_38_WIDTH },
156516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_39_CHECKER_TYPE,
156517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_39_WIDTH },
156518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_40_CHECKER_TYPE,
156519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_40_WIDTH },
156520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_41_CHECKER_TYPE,
156521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_41_WIDTH },
156522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_42_CHECKER_TYPE,
156523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_42_WIDTH },
156524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_43_CHECKER_TYPE,
156525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_43_WIDTH },
156526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_44_CHECKER_TYPE,
156527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_44_WIDTH },
156528  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_45_CHECKER_TYPE,
156529  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_45_WIDTH },
156530  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_46_CHECKER_TYPE,
156531  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_46_WIDTH },
156532  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_47_CHECKER_TYPE,
156533  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_47_WIDTH },
156534  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_48_CHECKER_TYPE,
156535  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_48_WIDTH },
156536  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_49_CHECKER_TYPE,
156537  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_49_WIDTH },
156538  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_50_CHECKER_TYPE,
156539  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_50_WIDTH },
156540  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_51_CHECKER_TYPE,
156541  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_51_WIDTH },
156542  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_52_CHECKER_TYPE,
156543  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_52_WIDTH },
156544  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_53_CHECKER_TYPE,
156545  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_53_WIDTH },
156546  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_54_CHECKER_TYPE,
156547  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_54_WIDTH },
156548  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_55_CHECKER_TYPE,
156549  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_55_WIDTH },
156550  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_56_CHECKER_TYPE,
156551  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_56_WIDTH },
156552  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_57_CHECKER_TYPE,
156553  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_57_WIDTH },
156554  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_58_CHECKER_TYPE,
156555  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_58_WIDTH },
156556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_59_CHECKER_TYPE,
156557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_59_WIDTH },
156558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_60_CHECKER_TYPE,
156559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_60_WIDTH },
156560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_61_CHECKER_TYPE,
156561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_61_WIDTH },
156562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_62_CHECKER_TYPE,
156563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_62_WIDTH },
156564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_63_CHECKER_TYPE,
156565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_63_WIDTH },
156566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_64_CHECKER_TYPE,
156567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_64_WIDTH },
156568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_65_CHECKER_TYPE,
156569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_65_WIDTH },
156570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_66_CHECKER_TYPE,
156571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_66_WIDTH },
156572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_67_CHECKER_TYPE,
156573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_67_WIDTH },
156574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_68_CHECKER_TYPE,
156575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_68_WIDTH },
156576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_69_CHECKER_TYPE,
156577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_69_WIDTH },
156578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_70_CHECKER_TYPE,
156579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_70_WIDTH },
156580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_71_CHECKER_TYPE,
156581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_71_WIDTH },
156582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_72_CHECKER_TYPE,
156583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_72_WIDTH },
156584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_73_CHECKER_TYPE,
156585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_73_WIDTH },
156586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_74_CHECKER_TYPE,
156587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_74_WIDTH },
156588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_75_CHECKER_TYPE,
156589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_75_WIDTH },
156590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_76_CHECKER_TYPE,
156591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_76_WIDTH },
156592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_77_CHECKER_TYPE,
156593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_77_WIDTH },
156594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_78_CHECKER_TYPE,
156595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_78_WIDTH },
156596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_79_CHECKER_TYPE,
156597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_79_WIDTH },
156598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_80_CHECKER_TYPE,
156599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_80_WIDTH },
156600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_81_CHECKER_TYPE,
156601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_81_WIDTH },
156602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_82_CHECKER_TYPE,
156603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_82_WIDTH },
156604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_83_CHECKER_TYPE,
156605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_83_WIDTH },
156606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_84_CHECKER_TYPE,
156607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_84_WIDTH },
156608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_85_CHECKER_TYPE,
156609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_85_WIDTH },
156610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_86_CHECKER_TYPE,
156611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_86_WIDTH },
156612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_87_CHECKER_TYPE,
156613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_87_WIDTH },
156614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_88_CHECKER_TYPE,
156615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_88_WIDTH },
156616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_89_CHECKER_TYPE,
156617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_89_WIDTH },
156618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_90_CHECKER_TYPE,
156619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_90_WIDTH },
156620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_91_CHECKER_TYPE,
156621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_91_WIDTH },
156622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_92_CHECKER_TYPE,
156623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_92_WIDTH },
156624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_93_CHECKER_TYPE,
156625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_93_WIDTH },
156626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_94_CHECKER_TYPE,
156627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_94_WIDTH },
156628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_95_CHECKER_TYPE,
156629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_95_WIDTH },
156630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_96_CHECKER_TYPE,
156631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_96_WIDTH },
156632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_97_CHECKER_TYPE,
156633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_97_WIDTH },
156634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_98_CHECKER_TYPE,
156635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_98_WIDTH },
156636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_99_CHECKER_TYPE,
156637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_99_WIDTH },
156638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_100_CHECKER_TYPE,
156639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_100_WIDTH },
156640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_101_CHECKER_TYPE,
156641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_101_WIDTH },
156642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_102_CHECKER_TYPE,
156643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_102_WIDTH },
156644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_103_CHECKER_TYPE,
156645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_103_WIDTH },
156646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_104_CHECKER_TYPE,
156647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_104_WIDTH },
156648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_105_CHECKER_TYPE,
156649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_105_WIDTH },
156650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_106_CHECKER_TYPE,
156651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_106_WIDTH },
156652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_107_CHECKER_TYPE,
156653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_107_WIDTH },
156654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_108_CHECKER_TYPE,
156655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_108_WIDTH },
156656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_109_CHECKER_TYPE,
156657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_109_WIDTH },
156658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_110_CHECKER_TYPE,
156659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_110_WIDTH },
156660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_111_CHECKER_TYPE,
156661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_111_WIDTH },
156662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_112_CHECKER_TYPE,
156663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_112_WIDTH },
156664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_113_CHECKER_TYPE,
156665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_113_WIDTH },
156666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_114_CHECKER_TYPE,
156667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_114_WIDTH },
156668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_115_CHECKER_TYPE,
156669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_115_WIDTH },
156670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_116_CHECKER_TYPE,
156671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_116_WIDTH },
156672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_117_CHECKER_TYPE,
156673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_117_WIDTH },
156674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_118_CHECKER_TYPE,
156675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_118_WIDTH },
156676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_119_CHECKER_TYPE,
156677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_119_WIDTH },
156678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_120_CHECKER_TYPE,
156679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_120_WIDTH },
156680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_121_CHECKER_TYPE,
156681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_121_WIDTH },
156682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_122_CHECKER_TYPE,
156683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_122_WIDTH },
156684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_123_CHECKER_TYPE,
156685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_123_WIDTH },
156686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_124_CHECKER_TYPE,
156687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_124_WIDTH },
156688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_125_CHECKER_TYPE,
156689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_125_WIDTH },
156690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_126_CHECKER_TYPE,
156691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_126_WIDTH },
156692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_127_CHECKER_TYPE,
156693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_127_WIDTH },
156694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_128_CHECKER_TYPE,
156695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_128_WIDTH },
156696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_129_CHECKER_TYPE,
156697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_129_WIDTH },
156698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_130_CHECKER_TYPE,
156699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_130_WIDTH },
156700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_131_CHECKER_TYPE,
156701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_131_WIDTH },
156702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_132_CHECKER_TYPE,
156703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_132_WIDTH },
156704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_133_CHECKER_TYPE,
156705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_133_WIDTH },
156706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_134_CHECKER_TYPE,
156707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_134_WIDTH },
156708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_135_CHECKER_TYPE,
156709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_135_WIDTH },
156710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_136_CHECKER_TYPE,
156711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_136_WIDTH },
156712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_137_CHECKER_TYPE,
156713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_137_WIDTH },
156714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_138_CHECKER_TYPE,
156715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_138_WIDTH },
156716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_139_CHECKER_TYPE,
156717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_139_WIDTH },
156718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_140_CHECKER_TYPE,
156719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_140_WIDTH },
156720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_141_CHECKER_TYPE,
156721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_141_WIDTH },
156722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_142_CHECKER_TYPE,
156723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_142_WIDTH },
156724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_143_CHECKER_TYPE,
156725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_143_WIDTH },
156726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_144_CHECKER_TYPE,
156727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_144_WIDTH },
156728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_145_CHECKER_TYPE,
156729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_145_WIDTH },
156730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_146_CHECKER_TYPE,
156731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_146_WIDTH },
156732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_147_CHECKER_TYPE,
156733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_147_WIDTH },
156734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_148_CHECKER_TYPE,
156735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_148_WIDTH },
156736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_149_CHECKER_TYPE,
156737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_149_WIDTH },
156738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_150_CHECKER_TYPE,
156739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_150_WIDTH },
156740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_151_CHECKER_TYPE,
156741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_151_WIDTH },
156742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_152_CHECKER_TYPE,
156743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_152_WIDTH },
156744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_153_CHECKER_TYPE,
156745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_153_WIDTH },
156746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_154_CHECKER_TYPE,
156747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_154_WIDTH },
156748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_155_CHECKER_TYPE,
156749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_155_WIDTH },
156750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_156_CHECKER_TYPE,
156751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_156_WIDTH },
156752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_157_CHECKER_TYPE,
156753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_157_WIDTH },
156754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_158_CHECKER_TYPE,
156755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_158_WIDTH },
156756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_159_CHECKER_TYPE,
156757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_159_WIDTH },
156758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_160_CHECKER_TYPE,
156759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_160_WIDTH },
156760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_161_CHECKER_TYPE,
156761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_161_WIDTH },
156762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_162_CHECKER_TYPE,
156763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_162_WIDTH },
156764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_163_CHECKER_TYPE,
156765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_163_WIDTH },
156766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_164_CHECKER_TYPE,
156767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_164_WIDTH },
156768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_165_CHECKER_TYPE,
156769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_165_WIDTH },
156770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_166_CHECKER_TYPE,
156771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_166_WIDTH },
156772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_167_CHECKER_TYPE,
156773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_167_WIDTH },
156774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_168_CHECKER_TYPE,
156775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_168_WIDTH },
156776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_169_CHECKER_TYPE,
156777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_169_WIDTH },
156778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_170_CHECKER_TYPE,
156779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_170_WIDTH },
156780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_171_CHECKER_TYPE,
156781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_171_WIDTH },
156782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_172_CHECKER_TYPE,
156783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_172_WIDTH },
156784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_173_CHECKER_TYPE,
156785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_173_WIDTH },
156786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_174_CHECKER_TYPE,
156787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_174_WIDTH },
156788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_175_CHECKER_TYPE,
156789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_175_WIDTH },
156790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_176_CHECKER_TYPE,
156791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_176_WIDTH },
156792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_177_CHECKER_TYPE,
156793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_177_WIDTH },
156794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_178_CHECKER_TYPE,
156795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_178_WIDTH },
156796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_179_CHECKER_TYPE,
156797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_179_WIDTH },
156798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_180_CHECKER_TYPE,
156799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_180_WIDTH },
156800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_181_CHECKER_TYPE,
156801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_181_WIDTH },
156802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_182_CHECKER_TYPE,
156803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_182_WIDTH },
156804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_183_CHECKER_TYPE,
156805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_183_WIDTH },
156806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_184_CHECKER_TYPE,
156807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_184_WIDTH },
156808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_185_CHECKER_TYPE,
156809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_185_WIDTH },
156810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_186_CHECKER_TYPE,
156811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_186_WIDTH },
156812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_187_CHECKER_TYPE,
156813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_187_WIDTH },
156814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_188_CHECKER_TYPE,
156815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_188_WIDTH },
156816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_189_CHECKER_TYPE,
156817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_189_WIDTH },
156818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_190_CHECKER_TYPE,
156819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_190_WIDTH },
156820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_191_CHECKER_TYPE,
156821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_191_WIDTH },
156822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_192_CHECKER_TYPE,
156823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_192_WIDTH },
156824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_193_CHECKER_TYPE,
156825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_193_WIDTH },
156826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_194_CHECKER_TYPE,
156827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_194_WIDTH },
156828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_195_CHECKER_TYPE,
156829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_195_WIDTH },
156830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_196_CHECKER_TYPE,
156831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_196_WIDTH },
156832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_197_CHECKER_TYPE,
156833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_197_WIDTH },
156834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_198_CHECKER_TYPE,
156835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_198_WIDTH },
156836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_199_CHECKER_TYPE,
156837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_199_WIDTH },
156838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_200_CHECKER_TYPE,
156839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_200_WIDTH },
156840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_201_CHECKER_TYPE,
156841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_201_WIDTH },
156842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_202_CHECKER_TYPE,
156843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_202_WIDTH },
156844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_203_CHECKER_TYPE,
156845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_203_WIDTH },
156846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_204_CHECKER_TYPE,
156847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_204_WIDTH },
156848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_205_CHECKER_TYPE,
156849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_205_WIDTH },
156850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_206_CHECKER_TYPE,
156851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_206_WIDTH },
156852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_207_CHECKER_TYPE,
156853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_207_WIDTH },
156854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_208_CHECKER_TYPE,
156855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_208_WIDTH },
156856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_209_CHECKER_TYPE,
156857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_209_WIDTH },
156858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_210_CHECKER_TYPE,
156859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_210_WIDTH },
156860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_211_CHECKER_TYPE,
156861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_211_WIDTH },
156862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_212_CHECKER_TYPE,
156863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_212_WIDTH },
156864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_213_CHECKER_TYPE,
156865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_213_WIDTH },
156866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_214_CHECKER_TYPE,
156867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_214_WIDTH },
156868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_215_CHECKER_TYPE,
156869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_215_WIDTH },
156870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_216_CHECKER_TYPE,
156871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_216_WIDTH },
156872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_217_CHECKER_TYPE,
156873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_217_WIDTH },
156874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_218_CHECKER_TYPE,
156875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_218_WIDTH },
156876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_219_CHECKER_TYPE,
156877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_219_WIDTH },
156878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_220_CHECKER_TYPE,
156879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_220_WIDTH },
156880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_221_CHECKER_TYPE,
156881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_221_WIDTH },
156882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_222_CHECKER_TYPE,
156883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_222_WIDTH },
156884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_223_CHECKER_TYPE,
156885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_223_WIDTH },
156886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_224_CHECKER_TYPE,
156887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_224_WIDTH },
156888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_225_CHECKER_TYPE,
156889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_225_WIDTH },
156890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_226_CHECKER_TYPE,
156891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_226_WIDTH },
156892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_227_CHECKER_TYPE,
156893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_227_WIDTH },
156894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_228_CHECKER_TYPE,
156895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_228_WIDTH },
156896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_229_CHECKER_TYPE,
156897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_229_WIDTH },
156898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_230_CHECKER_TYPE,
156899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_230_WIDTH },
156900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_231_CHECKER_TYPE,
156901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_231_WIDTH },
156902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_232_CHECKER_TYPE,
156903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_232_WIDTH },
156904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_233_CHECKER_TYPE,
156905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_233_WIDTH },
156906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_234_CHECKER_TYPE,
156907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_234_WIDTH },
156908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_235_CHECKER_TYPE,
156909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_235_WIDTH },
156910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_236_CHECKER_TYPE,
156911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_236_WIDTH },
156912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_237_CHECKER_TYPE,
156913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_237_WIDTH },
156914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_238_CHECKER_TYPE,
156915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_238_WIDTH },
156916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_239_CHECKER_TYPE,
156917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_239_WIDTH },
156918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_240_CHECKER_TYPE,
156919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_240_WIDTH },
156920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_241_CHECKER_TYPE,
156921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_241_WIDTH },
156922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_242_CHECKER_TYPE,
156923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_242_WIDTH },
156924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_243_CHECKER_TYPE,
156925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_243_WIDTH },
156926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_244_CHECKER_TYPE,
156927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_244_WIDTH },
156928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_245_CHECKER_TYPE,
156929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_245_WIDTH },
156930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_246_CHECKER_TYPE,
156931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_246_WIDTH },
156932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_247_CHECKER_TYPE,
156933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_247_WIDTH },
156934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_248_CHECKER_TYPE,
156935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_248_WIDTH },
156936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_249_CHECKER_TYPE,
156937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_249_WIDTH },
156938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_250_CHECKER_TYPE,
156939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_250_WIDTH },
156940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_251_CHECKER_TYPE,
156941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_251_WIDTH },
156942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_252_CHECKER_TYPE,
156943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_252_WIDTH },
156944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_253_CHECKER_TYPE,
156945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_253_WIDTH },
156946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_254_CHECKER_TYPE,
156947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_254_WIDTH },
156948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_255_CHECKER_TYPE,
156949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_GROUP_255_WIDTH },
156950 };
156951 
156957 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_MAX_NUM_CHECKERS] =
156958 {
156959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_0_CHECKER_TYPE,
156960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_0_WIDTH },
156961  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_1_CHECKER_TYPE,
156962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_1_WIDTH },
156963  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_2_CHECKER_TYPE,
156964  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_2_WIDTH },
156965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_3_CHECKER_TYPE,
156966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_3_WIDTH },
156967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_4_CHECKER_TYPE,
156968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_4_WIDTH },
156969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_5_CHECKER_TYPE,
156970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_5_WIDTH },
156971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_6_CHECKER_TYPE,
156972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_6_WIDTH },
156973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_7_CHECKER_TYPE,
156974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_7_WIDTH },
156975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_8_CHECKER_TYPE,
156976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_8_WIDTH },
156977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_9_CHECKER_TYPE,
156978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_9_WIDTH },
156979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_10_CHECKER_TYPE,
156980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_10_WIDTH },
156981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_11_CHECKER_TYPE,
156982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_11_WIDTH },
156983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_12_CHECKER_TYPE,
156984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_12_WIDTH },
156985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_13_CHECKER_TYPE,
156986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_13_WIDTH },
156987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_14_CHECKER_TYPE,
156988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_14_WIDTH },
156989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_15_CHECKER_TYPE,
156990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_15_WIDTH },
156991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_16_CHECKER_TYPE,
156992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_16_WIDTH },
156993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_17_CHECKER_TYPE,
156994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_17_WIDTH },
156995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_18_CHECKER_TYPE,
156996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_18_WIDTH },
156997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_19_CHECKER_TYPE,
156998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_19_WIDTH },
156999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_20_CHECKER_TYPE,
157000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_20_WIDTH },
157001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_21_CHECKER_TYPE,
157002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_21_WIDTH },
157003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_22_CHECKER_TYPE,
157004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_22_WIDTH },
157005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_23_CHECKER_TYPE,
157006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_23_WIDTH },
157007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_24_CHECKER_TYPE,
157008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_24_WIDTH },
157009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_25_CHECKER_TYPE,
157010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_25_WIDTH },
157011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_26_CHECKER_TYPE,
157012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_26_WIDTH },
157013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_27_CHECKER_TYPE,
157014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_27_WIDTH },
157015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_28_CHECKER_TYPE,
157016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_28_WIDTH },
157017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_29_CHECKER_TYPE,
157018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_29_WIDTH },
157019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_30_CHECKER_TYPE,
157020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_30_WIDTH },
157021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_31_CHECKER_TYPE,
157022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_31_WIDTH },
157023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_32_CHECKER_TYPE,
157024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_32_WIDTH },
157025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_33_CHECKER_TYPE,
157026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_33_WIDTH },
157027  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_34_CHECKER_TYPE,
157028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_34_WIDTH },
157029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_35_CHECKER_TYPE,
157030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_35_WIDTH },
157031  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_36_CHECKER_TYPE,
157032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_36_WIDTH },
157033  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_37_CHECKER_TYPE,
157034  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_37_WIDTH },
157035  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_38_CHECKER_TYPE,
157036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_38_WIDTH },
157037  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_39_CHECKER_TYPE,
157038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_39_WIDTH },
157039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_40_CHECKER_TYPE,
157040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_40_WIDTH },
157041  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_41_CHECKER_TYPE,
157042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_41_WIDTH },
157043  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_42_CHECKER_TYPE,
157044  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_42_WIDTH },
157045  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_43_CHECKER_TYPE,
157046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_43_WIDTH },
157047  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_44_CHECKER_TYPE,
157048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_44_WIDTH },
157049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_45_CHECKER_TYPE,
157050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_45_WIDTH },
157051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_46_CHECKER_TYPE,
157052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_46_WIDTH },
157053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_47_CHECKER_TYPE,
157054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_47_WIDTH },
157055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_48_CHECKER_TYPE,
157056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_48_WIDTH },
157057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_49_CHECKER_TYPE,
157058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_49_WIDTH },
157059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_50_CHECKER_TYPE,
157060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_50_WIDTH },
157061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_51_CHECKER_TYPE,
157062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_51_WIDTH },
157063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_52_CHECKER_TYPE,
157064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_52_WIDTH },
157065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_53_CHECKER_TYPE,
157066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_53_WIDTH },
157067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_54_CHECKER_TYPE,
157068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_54_WIDTH },
157069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_55_CHECKER_TYPE,
157070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_55_WIDTH },
157071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_56_CHECKER_TYPE,
157072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_56_WIDTH },
157073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_57_CHECKER_TYPE,
157074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_57_WIDTH },
157075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_58_CHECKER_TYPE,
157076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_58_WIDTH },
157077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_59_CHECKER_TYPE,
157078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_59_WIDTH },
157079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_60_CHECKER_TYPE,
157080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_60_WIDTH },
157081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_61_CHECKER_TYPE,
157082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_61_WIDTH },
157083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_62_CHECKER_TYPE,
157084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_62_WIDTH },
157085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_63_CHECKER_TYPE,
157086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_63_WIDTH },
157087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_64_CHECKER_TYPE,
157088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_64_WIDTH },
157089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_65_CHECKER_TYPE,
157090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_65_WIDTH },
157091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_66_CHECKER_TYPE,
157092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_66_WIDTH },
157093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_67_CHECKER_TYPE,
157094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_67_WIDTH },
157095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_68_CHECKER_TYPE,
157096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_68_WIDTH },
157097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_69_CHECKER_TYPE,
157098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_69_WIDTH },
157099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_70_CHECKER_TYPE,
157100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_70_WIDTH },
157101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_71_CHECKER_TYPE,
157102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_71_WIDTH },
157103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_72_CHECKER_TYPE,
157104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_72_WIDTH },
157105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_73_CHECKER_TYPE,
157106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_73_WIDTH },
157107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_74_CHECKER_TYPE,
157108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_74_WIDTH },
157109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_75_CHECKER_TYPE,
157110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_75_WIDTH },
157111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_76_CHECKER_TYPE,
157112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_76_WIDTH },
157113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_77_CHECKER_TYPE,
157114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_77_WIDTH },
157115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_78_CHECKER_TYPE,
157116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_78_WIDTH },
157117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_79_CHECKER_TYPE,
157118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_79_WIDTH },
157119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_80_CHECKER_TYPE,
157120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_80_WIDTH },
157121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_81_CHECKER_TYPE,
157122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_81_WIDTH },
157123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_82_CHECKER_TYPE,
157124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_82_WIDTH },
157125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_83_CHECKER_TYPE,
157126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_83_WIDTH },
157127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_84_CHECKER_TYPE,
157128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_84_WIDTH },
157129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_85_CHECKER_TYPE,
157130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_85_WIDTH },
157131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_86_CHECKER_TYPE,
157132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_86_WIDTH },
157133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_87_CHECKER_TYPE,
157134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_87_WIDTH },
157135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_88_CHECKER_TYPE,
157136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_88_WIDTH },
157137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_89_CHECKER_TYPE,
157138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_89_WIDTH },
157139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_90_CHECKER_TYPE,
157140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_90_WIDTH },
157141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_91_CHECKER_TYPE,
157142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_91_WIDTH },
157143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_92_CHECKER_TYPE,
157144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_92_WIDTH },
157145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_93_CHECKER_TYPE,
157146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_93_WIDTH },
157147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_94_CHECKER_TYPE,
157148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_94_WIDTH },
157149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_95_CHECKER_TYPE,
157150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_95_WIDTH },
157151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_96_CHECKER_TYPE,
157152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_96_WIDTH },
157153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_97_CHECKER_TYPE,
157154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_97_WIDTH },
157155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_98_CHECKER_TYPE,
157156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_98_WIDTH },
157157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_99_CHECKER_TYPE,
157158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_99_WIDTH },
157159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_100_CHECKER_TYPE,
157160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_100_WIDTH },
157161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_101_CHECKER_TYPE,
157162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_101_WIDTH },
157163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_102_CHECKER_TYPE,
157164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_102_WIDTH },
157165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_103_CHECKER_TYPE,
157166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_103_WIDTH },
157167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_104_CHECKER_TYPE,
157168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_104_WIDTH },
157169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_105_CHECKER_TYPE,
157170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_105_WIDTH },
157171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_106_CHECKER_TYPE,
157172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_106_WIDTH },
157173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_107_CHECKER_TYPE,
157174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_107_WIDTH },
157175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_108_CHECKER_TYPE,
157176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_108_WIDTH },
157177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_109_CHECKER_TYPE,
157178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_109_WIDTH },
157179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_110_CHECKER_TYPE,
157180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_110_WIDTH },
157181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_111_CHECKER_TYPE,
157182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_111_WIDTH },
157183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_112_CHECKER_TYPE,
157184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_112_WIDTH },
157185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_113_CHECKER_TYPE,
157186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_113_WIDTH },
157187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_114_CHECKER_TYPE,
157188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_114_WIDTH },
157189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_115_CHECKER_TYPE,
157190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_115_WIDTH },
157191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_116_CHECKER_TYPE,
157192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_116_WIDTH },
157193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_117_CHECKER_TYPE,
157194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_117_WIDTH },
157195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_118_CHECKER_TYPE,
157196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_118_WIDTH },
157197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_119_CHECKER_TYPE,
157198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_119_WIDTH },
157199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_120_CHECKER_TYPE,
157200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_120_WIDTH },
157201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_121_CHECKER_TYPE,
157202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_121_WIDTH },
157203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_122_CHECKER_TYPE,
157204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_122_WIDTH },
157205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_123_CHECKER_TYPE,
157206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_123_WIDTH },
157207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_124_CHECKER_TYPE,
157208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_124_WIDTH },
157209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_125_CHECKER_TYPE,
157210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_125_WIDTH },
157211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_126_CHECKER_TYPE,
157212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_126_WIDTH },
157213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_127_CHECKER_TYPE,
157214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_127_WIDTH },
157215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_128_CHECKER_TYPE,
157216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_128_WIDTH },
157217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_129_CHECKER_TYPE,
157218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_129_WIDTH },
157219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_130_CHECKER_TYPE,
157220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_130_WIDTH },
157221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_131_CHECKER_TYPE,
157222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_131_WIDTH },
157223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_132_CHECKER_TYPE,
157224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_132_WIDTH },
157225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_133_CHECKER_TYPE,
157226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_133_WIDTH },
157227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_134_CHECKER_TYPE,
157228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_134_WIDTH },
157229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_135_CHECKER_TYPE,
157230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_135_WIDTH },
157231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_136_CHECKER_TYPE,
157232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_136_WIDTH },
157233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_137_CHECKER_TYPE,
157234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_137_WIDTH },
157235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_138_CHECKER_TYPE,
157236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_138_WIDTH },
157237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_139_CHECKER_TYPE,
157238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_139_WIDTH },
157239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_140_CHECKER_TYPE,
157240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_140_WIDTH },
157241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_141_CHECKER_TYPE,
157242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_141_WIDTH },
157243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_142_CHECKER_TYPE,
157244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_142_WIDTH },
157245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_143_CHECKER_TYPE,
157246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_143_WIDTH },
157247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_144_CHECKER_TYPE,
157248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_144_WIDTH },
157249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_145_CHECKER_TYPE,
157250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_145_WIDTH },
157251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_146_CHECKER_TYPE,
157252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_146_WIDTH },
157253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_147_CHECKER_TYPE,
157254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_147_WIDTH },
157255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_148_CHECKER_TYPE,
157256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_148_WIDTH },
157257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_149_CHECKER_TYPE,
157258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_149_WIDTH },
157259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_150_CHECKER_TYPE,
157260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_150_WIDTH },
157261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_151_CHECKER_TYPE,
157262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_151_WIDTH },
157263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_152_CHECKER_TYPE,
157264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_152_WIDTH },
157265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_153_CHECKER_TYPE,
157266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_153_WIDTH },
157267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_154_CHECKER_TYPE,
157268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_154_WIDTH },
157269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_155_CHECKER_TYPE,
157270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_155_WIDTH },
157271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_156_CHECKER_TYPE,
157272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_156_WIDTH },
157273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_157_CHECKER_TYPE,
157274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_157_WIDTH },
157275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_158_CHECKER_TYPE,
157276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_158_WIDTH },
157277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_159_CHECKER_TYPE,
157278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_159_WIDTH },
157279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_160_CHECKER_TYPE,
157280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_160_WIDTH },
157281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_161_CHECKER_TYPE,
157282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_161_WIDTH },
157283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_162_CHECKER_TYPE,
157284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_162_WIDTH },
157285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_163_CHECKER_TYPE,
157286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_163_WIDTH },
157287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_164_CHECKER_TYPE,
157288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_164_WIDTH },
157289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_165_CHECKER_TYPE,
157290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_165_WIDTH },
157291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_166_CHECKER_TYPE,
157292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_166_WIDTH },
157293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_167_CHECKER_TYPE,
157294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_167_WIDTH },
157295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_168_CHECKER_TYPE,
157296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_168_WIDTH },
157297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_169_CHECKER_TYPE,
157298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_169_WIDTH },
157299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_170_CHECKER_TYPE,
157300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_170_WIDTH },
157301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_171_CHECKER_TYPE,
157302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_171_WIDTH },
157303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_172_CHECKER_TYPE,
157304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_172_WIDTH },
157305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_173_CHECKER_TYPE,
157306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_173_WIDTH },
157307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_174_CHECKER_TYPE,
157308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_174_WIDTH },
157309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_175_CHECKER_TYPE,
157310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_175_WIDTH },
157311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_176_CHECKER_TYPE,
157312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_176_WIDTH },
157313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_177_CHECKER_TYPE,
157314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_177_WIDTH },
157315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_178_CHECKER_TYPE,
157316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_178_WIDTH },
157317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_179_CHECKER_TYPE,
157318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_179_WIDTH },
157319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_180_CHECKER_TYPE,
157320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_180_WIDTH },
157321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_181_CHECKER_TYPE,
157322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_181_WIDTH },
157323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_182_CHECKER_TYPE,
157324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_182_WIDTH },
157325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_183_CHECKER_TYPE,
157326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_183_WIDTH },
157327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_184_CHECKER_TYPE,
157328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_184_WIDTH },
157329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_185_CHECKER_TYPE,
157330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_185_WIDTH },
157331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_186_CHECKER_TYPE,
157332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_186_WIDTH },
157333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_187_CHECKER_TYPE,
157334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_187_WIDTH },
157335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_188_CHECKER_TYPE,
157336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_188_WIDTH },
157337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_189_CHECKER_TYPE,
157338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_189_WIDTH },
157339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_190_CHECKER_TYPE,
157340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_190_WIDTH },
157341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_191_CHECKER_TYPE,
157342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_191_WIDTH },
157343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_192_CHECKER_TYPE,
157344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_192_WIDTH },
157345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_193_CHECKER_TYPE,
157346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_193_WIDTH },
157347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_194_CHECKER_TYPE,
157348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_194_WIDTH },
157349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_195_CHECKER_TYPE,
157350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_195_WIDTH },
157351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_196_CHECKER_TYPE,
157352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_196_WIDTH },
157353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_197_CHECKER_TYPE,
157354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_197_WIDTH },
157355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_198_CHECKER_TYPE,
157356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_198_WIDTH },
157357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_199_CHECKER_TYPE,
157358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_199_WIDTH },
157359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_200_CHECKER_TYPE,
157360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_200_WIDTH },
157361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_201_CHECKER_TYPE,
157362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_201_WIDTH },
157363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_202_CHECKER_TYPE,
157364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_202_WIDTH },
157365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_203_CHECKER_TYPE,
157366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_203_WIDTH },
157367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_204_CHECKER_TYPE,
157368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_204_WIDTH },
157369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_205_CHECKER_TYPE,
157370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_205_WIDTH },
157371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_206_CHECKER_TYPE,
157372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_206_WIDTH },
157373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_207_CHECKER_TYPE,
157374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_207_WIDTH },
157375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_208_CHECKER_TYPE,
157376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_208_WIDTH },
157377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_209_CHECKER_TYPE,
157378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_GROUP_209_WIDTH },
157379 };
157380 
157386 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
157387 {
157388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
157389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
157390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
157391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
157392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
157393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
157394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
157395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
157396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
157397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
157398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
157399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
157400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
157401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
157402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
157403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
157404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
157405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
157406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
157407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
157408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
157409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
157410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
157411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
157412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
157413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
157414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
157415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
157416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
157417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
157418 };
157419 
157425 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
157426 {
157427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
157428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
157429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
157430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
157431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
157432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
157433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
157434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
157435 };
157436 
157442 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
157443 {
157444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
157445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
157446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
157447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
157448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
157449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
157450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
157451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
157452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
157453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
157454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
157455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
157456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
157457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
157458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
157459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
157460  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
157461  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
157462  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
157463  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
157464  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
157465  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
157466  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
157467  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
157468  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
157469  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
157470  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
157471  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
157472  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
157473  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
157474  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
157475  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
157476  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
157477  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
157478  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
157479  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
157480  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
157481  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
157482  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
157483  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
157484  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
157485  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
157486  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
157487  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
157488  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
157489  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
157490  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
157491  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
157492  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
157493  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
157494  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
157495  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
157496  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
157497  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
157498  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
157499  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
157500  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
157501  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
157502  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
157503  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
157504  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
157505  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
157506  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
157507  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
157508  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
157509  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
157510  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
157511  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
157512  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
157513  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
157514  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
157515  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
157516  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
157517  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
157518  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
157519  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
157520  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
157521  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
157522  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
157523  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
157524  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
157525  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
157526  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
157527  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
157528 };
157529 
157535 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
157536 {
157537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
157538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
157539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
157540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
157541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
157542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
157543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
157544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
157545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
157546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
157547 };
157548 
157554 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
157555 {
157556  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
157557  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
157558  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
157559  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
157560  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
157561  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
157562  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
157563  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
157564  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
157565  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
157566  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
157567  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
157568  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
157569  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
157570  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
157571  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
157572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
157573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
157574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
157575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
157576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
157577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
157578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
157579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
157580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
157581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
157582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
157583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
157584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
157585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
157586 };
157587 
157593 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
157594 {
157595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
157596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
157597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
157598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
157599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
157600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
157601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
157602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
157603 };
157604 
157610 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
157611 {
157612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
157613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
157614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
157615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
157616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
157617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
157618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
157619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
157620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
157621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
157622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
157623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
157624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
157625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
157626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
157627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
157628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
157629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
157630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
157631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
157632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
157633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
157634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
157635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
157636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
157637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
157638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
157639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
157640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
157641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
157642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
157643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
157644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
157645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
157646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
157647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
157648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
157649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
157650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
157651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
157652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
157653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
157654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
157655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
157656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
157657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
157658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
157659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
157660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
157661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
157662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
157663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
157664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
157665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
157666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
157667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
157668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
157669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
157670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
157671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
157672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
157673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
157674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
157675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
157676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
157677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
157678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
157679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
157680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
157681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
157682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
157683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
157684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
157685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
157686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
157687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
157688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
157689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
157690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
157691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
157692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
157693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
157694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
157695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
157696 };
157697 
157703 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_MAX_NUM_CHECKERS] =
157704 {
157705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_0_CHECKER_TYPE,
157706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_0_WIDTH },
157707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_1_CHECKER_TYPE,
157708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_1_WIDTH },
157709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_2_CHECKER_TYPE,
157710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_2_WIDTH },
157711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_3_CHECKER_TYPE,
157712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_3_WIDTH },
157713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_4_CHECKER_TYPE,
157714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_4_WIDTH },
157715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_5_CHECKER_TYPE,
157716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_5_WIDTH },
157717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_6_CHECKER_TYPE,
157718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_6_WIDTH },
157719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_7_CHECKER_TYPE,
157720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_7_WIDTH },
157721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_8_CHECKER_TYPE,
157722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_8_WIDTH },
157723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_9_CHECKER_TYPE,
157724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_9_WIDTH },
157725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_10_CHECKER_TYPE,
157726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_10_WIDTH },
157727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_11_CHECKER_TYPE,
157728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_11_WIDTH },
157729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_12_CHECKER_TYPE,
157730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_12_WIDTH },
157731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_13_CHECKER_TYPE,
157732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_13_WIDTH },
157733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_14_CHECKER_TYPE,
157734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_14_WIDTH },
157735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_15_CHECKER_TYPE,
157736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_15_WIDTH },
157737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_16_CHECKER_TYPE,
157738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_16_WIDTH },
157739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_17_CHECKER_TYPE,
157740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_17_WIDTH },
157741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_18_CHECKER_TYPE,
157742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_18_WIDTH },
157743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_19_CHECKER_TYPE,
157744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_19_WIDTH },
157745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_20_CHECKER_TYPE,
157746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_20_WIDTH },
157747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_21_CHECKER_TYPE,
157748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_21_WIDTH },
157749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_22_CHECKER_TYPE,
157750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_22_WIDTH },
157751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_23_CHECKER_TYPE,
157752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_23_WIDTH },
157753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_24_CHECKER_TYPE,
157754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_24_WIDTH },
157755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_25_CHECKER_TYPE,
157756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_25_WIDTH },
157757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_26_CHECKER_TYPE,
157758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_26_WIDTH },
157759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_27_CHECKER_TYPE,
157760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_27_WIDTH },
157761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_28_CHECKER_TYPE,
157762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_28_WIDTH },
157763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_29_CHECKER_TYPE,
157764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_29_WIDTH },
157765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_30_CHECKER_TYPE,
157766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_30_WIDTH },
157767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_31_CHECKER_TYPE,
157768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_31_WIDTH },
157769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_32_CHECKER_TYPE,
157770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_32_WIDTH },
157771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_33_CHECKER_TYPE,
157772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_33_WIDTH },
157773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_34_CHECKER_TYPE,
157774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_34_WIDTH },
157775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_35_CHECKER_TYPE,
157776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_35_WIDTH },
157777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_36_CHECKER_TYPE,
157778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_36_WIDTH },
157779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_37_CHECKER_TYPE,
157780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_37_WIDTH },
157781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_38_CHECKER_TYPE,
157782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_38_WIDTH },
157783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_39_CHECKER_TYPE,
157784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_39_WIDTH },
157785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_40_CHECKER_TYPE,
157786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_40_WIDTH },
157787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_41_CHECKER_TYPE,
157788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_41_WIDTH },
157789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_42_CHECKER_TYPE,
157790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_42_WIDTH },
157791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_43_CHECKER_TYPE,
157792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_43_WIDTH },
157793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_44_CHECKER_TYPE,
157794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_44_WIDTH },
157795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_45_CHECKER_TYPE,
157796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_45_WIDTH },
157797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_46_CHECKER_TYPE,
157798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_46_WIDTH },
157799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_47_CHECKER_TYPE,
157800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_47_WIDTH },
157801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_48_CHECKER_TYPE,
157802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_48_WIDTH },
157803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_49_CHECKER_TYPE,
157804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_49_WIDTH },
157805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_50_CHECKER_TYPE,
157806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_50_WIDTH },
157807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_51_CHECKER_TYPE,
157808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_51_WIDTH },
157809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_52_CHECKER_TYPE,
157810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_52_WIDTH },
157811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_53_CHECKER_TYPE,
157812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_53_WIDTH },
157813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_54_CHECKER_TYPE,
157814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_54_WIDTH },
157815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_55_CHECKER_TYPE,
157816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_55_WIDTH },
157817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_56_CHECKER_TYPE,
157818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_56_WIDTH },
157819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_57_CHECKER_TYPE,
157820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_57_WIDTH },
157821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_58_CHECKER_TYPE,
157822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_58_WIDTH },
157823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_59_CHECKER_TYPE,
157824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_59_WIDTH },
157825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_60_CHECKER_TYPE,
157826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_60_WIDTH },
157827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_61_CHECKER_TYPE,
157828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_61_WIDTH },
157829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_62_CHECKER_TYPE,
157830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_62_WIDTH },
157831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_63_CHECKER_TYPE,
157832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_63_WIDTH },
157833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_64_CHECKER_TYPE,
157834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_64_WIDTH },
157835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_65_CHECKER_TYPE,
157836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_65_WIDTH },
157837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_66_CHECKER_TYPE,
157838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_66_WIDTH },
157839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_67_CHECKER_TYPE,
157840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_67_WIDTH },
157841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_68_CHECKER_TYPE,
157842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_68_WIDTH },
157843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_69_CHECKER_TYPE,
157844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_69_WIDTH },
157845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_70_CHECKER_TYPE,
157846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_70_WIDTH },
157847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_71_CHECKER_TYPE,
157848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_71_WIDTH },
157849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_72_CHECKER_TYPE,
157850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_72_WIDTH },
157851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_73_CHECKER_TYPE,
157852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_73_WIDTH },
157853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_74_CHECKER_TYPE,
157854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_74_WIDTH },
157855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_75_CHECKER_TYPE,
157856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_75_WIDTH },
157857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_76_CHECKER_TYPE,
157858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_76_WIDTH },
157859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_77_CHECKER_TYPE,
157860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_77_WIDTH },
157861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_78_CHECKER_TYPE,
157862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_78_WIDTH },
157863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_79_CHECKER_TYPE,
157864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_79_WIDTH },
157865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_80_CHECKER_TYPE,
157866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_80_WIDTH },
157867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_81_CHECKER_TYPE,
157868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_81_WIDTH },
157869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_82_CHECKER_TYPE,
157870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_82_WIDTH },
157871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_83_CHECKER_TYPE,
157872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_83_WIDTH },
157873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_84_CHECKER_TYPE,
157874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_GROUP_84_WIDTH },
157875 };
157876 
157882 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_MAX_NUM_CHECKERS] =
157883 {
157884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_0_CHECKER_TYPE,
157885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_0_WIDTH },
157886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_1_CHECKER_TYPE,
157887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_1_WIDTH },
157888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_2_CHECKER_TYPE,
157889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_2_WIDTH },
157890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_3_CHECKER_TYPE,
157891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_3_WIDTH },
157892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_4_CHECKER_TYPE,
157893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_4_WIDTH },
157894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_5_CHECKER_TYPE,
157895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_5_WIDTH },
157896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_6_CHECKER_TYPE,
157897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_6_WIDTH },
157898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_7_CHECKER_TYPE,
157899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_7_WIDTH },
157900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_8_CHECKER_TYPE,
157901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_8_WIDTH },
157902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_9_CHECKER_TYPE,
157903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_9_WIDTH },
157904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_10_CHECKER_TYPE,
157905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_10_WIDTH },
157906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_11_CHECKER_TYPE,
157907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_11_WIDTH },
157908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_12_CHECKER_TYPE,
157909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_12_WIDTH },
157910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_13_CHECKER_TYPE,
157911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_13_WIDTH },
157912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_14_CHECKER_TYPE,
157913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_14_WIDTH },
157914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_15_CHECKER_TYPE,
157915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_15_WIDTH },
157916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_16_CHECKER_TYPE,
157917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_16_WIDTH },
157918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_17_CHECKER_TYPE,
157919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_17_WIDTH },
157920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_18_CHECKER_TYPE,
157921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_18_WIDTH },
157922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_19_CHECKER_TYPE,
157923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_19_WIDTH },
157924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_20_CHECKER_TYPE,
157925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_20_WIDTH },
157926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_21_CHECKER_TYPE,
157927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_21_WIDTH },
157928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_22_CHECKER_TYPE,
157929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_22_WIDTH },
157930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_23_CHECKER_TYPE,
157931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_23_WIDTH },
157932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_24_CHECKER_TYPE,
157933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_24_WIDTH },
157934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_25_CHECKER_TYPE,
157935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_25_WIDTH },
157936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_26_CHECKER_TYPE,
157937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_26_WIDTH },
157938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_27_CHECKER_TYPE,
157939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_27_WIDTH },
157940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_28_CHECKER_TYPE,
157941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_28_WIDTH },
157942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_29_CHECKER_TYPE,
157943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_29_WIDTH },
157944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_30_CHECKER_TYPE,
157945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_30_WIDTH },
157946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_31_CHECKER_TYPE,
157947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_31_WIDTH },
157948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_32_CHECKER_TYPE,
157949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_32_WIDTH },
157950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_33_CHECKER_TYPE,
157951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_33_WIDTH },
157952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_34_CHECKER_TYPE,
157953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_34_WIDTH },
157954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_35_CHECKER_TYPE,
157955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_35_WIDTH },
157956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_36_CHECKER_TYPE,
157957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_36_WIDTH },
157958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_37_CHECKER_TYPE,
157959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_37_WIDTH },
157960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_38_CHECKER_TYPE,
157961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_38_WIDTH },
157962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_39_CHECKER_TYPE,
157963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_39_WIDTH },
157964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_40_CHECKER_TYPE,
157965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_40_WIDTH },
157966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_41_CHECKER_TYPE,
157967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_41_WIDTH },
157968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_42_CHECKER_TYPE,
157969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_42_WIDTH },
157970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_43_CHECKER_TYPE,
157971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_43_WIDTH },
157972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_44_CHECKER_TYPE,
157973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_44_WIDTH },
157974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_45_CHECKER_TYPE,
157975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_45_WIDTH },
157976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_46_CHECKER_TYPE,
157977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_46_WIDTH },
157978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_47_CHECKER_TYPE,
157979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_47_WIDTH },
157980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_48_CHECKER_TYPE,
157981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_48_WIDTH },
157982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_49_CHECKER_TYPE,
157983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_49_WIDTH },
157984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_50_CHECKER_TYPE,
157985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_50_WIDTH },
157986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_51_CHECKER_TYPE,
157987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_51_WIDTH },
157988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_52_CHECKER_TYPE,
157989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_52_WIDTH },
157990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_53_CHECKER_TYPE,
157991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_53_WIDTH },
157992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_54_CHECKER_TYPE,
157993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_54_WIDTH },
157994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_55_CHECKER_TYPE,
157995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_55_WIDTH },
157996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_56_CHECKER_TYPE,
157997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_56_WIDTH },
157998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_57_CHECKER_TYPE,
157999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_57_WIDTH },
158000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_58_CHECKER_TYPE,
158001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_58_WIDTH },
158002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_59_CHECKER_TYPE,
158003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_59_WIDTH },
158004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_60_CHECKER_TYPE,
158005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_60_WIDTH },
158006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_61_CHECKER_TYPE,
158007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_61_WIDTH },
158008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_62_CHECKER_TYPE,
158009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_62_WIDTH },
158010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_63_CHECKER_TYPE,
158011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_63_WIDTH },
158012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_64_CHECKER_TYPE,
158013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_64_WIDTH },
158014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_65_CHECKER_TYPE,
158015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_65_WIDTH },
158016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_66_CHECKER_TYPE,
158017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_66_WIDTH },
158018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_67_CHECKER_TYPE,
158019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_67_WIDTH },
158020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_68_CHECKER_TYPE,
158021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_68_WIDTH },
158022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_69_CHECKER_TYPE,
158023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_69_WIDTH },
158024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_70_CHECKER_TYPE,
158025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_70_WIDTH },
158026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_71_CHECKER_TYPE,
158027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_71_WIDTH },
158028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_72_CHECKER_TYPE,
158029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_72_WIDTH },
158030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_73_CHECKER_TYPE,
158031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_73_WIDTH },
158032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_74_CHECKER_TYPE,
158033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_74_WIDTH },
158034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_75_CHECKER_TYPE,
158035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_75_WIDTH },
158036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_76_CHECKER_TYPE,
158037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_76_WIDTH },
158038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_77_CHECKER_TYPE,
158039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_77_WIDTH },
158040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_78_CHECKER_TYPE,
158041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_78_WIDTH },
158042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_79_CHECKER_TYPE,
158043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_79_WIDTH },
158044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_80_CHECKER_TYPE,
158045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_80_WIDTH },
158046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_81_CHECKER_TYPE,
158047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_81_WIDTH },
158048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_82_CHECKER_TYPE,
158049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_82_WIDTH },
158050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_83_CHECKER_TYPE,
158051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_83_WIDTH },
158052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_84_CHECKER_TYPE,
158053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_84_WIDTH },
158054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_85_CHECKER_TYPE,
158055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_85_WIDTH },
158056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_86_CHECKER_TYPE,
158057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_86_WIDTH },
158058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_87_CHECKER_TYPE,
158059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_87_WIDTH },
158060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_88_CHECKER_TYPE,
158061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_88_WIDTH },
158062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_89_CHECKER_TYPE,
158063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_89_WIDTH },
158064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_90_CHECKER_TYPE,
158065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_90_WIDTH },
158066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_91_CHECKER_TYPE,
158067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_91_WIDTH },
158068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_92_CHECKER_TYPE,
158069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_92_WIDTH },
158070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_93_CHECKER_TYPE,
158071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_93_WIDTH },
158072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_94_CHECKER_TYPE,
158073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_94_WIDTH },
158074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_95_CHECKER_TYPE,
158075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_95_WIDTH },
158076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_96_CHECKER_TYPE,
158077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_96_WIDTH },
158078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_97_CHECKER_TYPE,
158079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_97_WIDTH },
158080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_98_CHECKER_TYPE,
158081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_98_WIDTH },
158082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_99_CHECKER_TYPE,
158083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_99_WIDTH },
158084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_100_CHECKER_TYPE,
158085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_100_WIDTH },
158086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_101_CHECKER_TYPE,
158087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_101_WIDTH },
158088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_102_CHECKER_TYPE,
158089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_102_WIDTH },
158090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_103_CHECKER_TYPE,
158091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_103_WIDTH },
158092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_104_CHECKER_TYPE,
158093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_104_WIDTH },
158094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_105_CHECKER_TYPE,
158095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_105_WIDTH },
158096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_106_CHECKER_TYPE,
158097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_106_WIDTH },
158098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_107_CHECKER_TYPE,
158099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_107_WIDTH },
158100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_108_CHECKER_TYPE,
158101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_108_WIDTH },
158102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_109_CHECKER_TYPE,
158103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_109_WIDTH },
158104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_110_CHECKER_TYPE,
158105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_110_WIDTH },
158106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_111_CHECKER_TYPE,
158107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_111_WIDTH },
158108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_112_CHECKER_TYPE,
158109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_112_WIDTH },
158110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_113_CHECKER_TYPE,
158111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_113_WIDTH },
158112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_114_CHECKER_TYPE,
158113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_114_WIDTH },
158114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_115_CHECKER_TYPE,
158115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_115_WIDTH },
158116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_116_CHECKER_TYPE,
158117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_116_WIDTH },
158118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_117_CHECKER_TYPE,
158119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_117_WIDTH },
158120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_118_CHECKER_TYPE,
158121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_118_WIDTH },
158122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_119_CHECKER_TYPE,
158123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_119_WIDTH },
158124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_120_CHECKER_TYPE,
158125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_120_WIDTH },
158126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_121_CHECKER_TYPE,
158127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_121_WIDTH },
158128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_122_CHECKER_TYPE,
158129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_122_WIDTH },
158130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_123_CHECKER_TYPE,
158131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_123_WIDTH },
158132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_124_CHECKER_TYPE,
158133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_124_WIDTH },
158134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_125_CHECKER_TYPE,
158135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_125_WIDTH },
158136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_126_CHECKER_TYPE,
158137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_126_WIDTH },
158138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_127_CHECKER_TYPE,
158139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_127_WIDTH },
158140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_128_CHECKER_TYPE,
158141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_128_WIDTH },
158142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_129_CHECKER_TYPE,
158143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_129_WIDTH },
158144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_130_CHECKER_TYPE,
158145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_130_WIDTH },
158146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_131_CHECKER_TYPE,
158147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_131_WIDTH },
158148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_132_CHECKER_TYPE,
158149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_132_WIDTH },
158150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_133_CHECKER_TYPE,
158151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_133_WIDTH },
158152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_134_CHECKER_TYPE,
158153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_134_WIDTH },
158154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_135_CHECKER_TYPE,
158155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_135_WIDTH },
158156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_136_CHECKER_TYPE,
158157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_136_WIDTH },
158158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_137_CHECKER_TYPE,
158159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_137_WIDTH },
158160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_138_CHECKER_TYPE,
158161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_138_WIDTH },
158162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_139_CHECKER_TYPE,
158163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_139_WIDTH },
158164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_140_CHECKER_TYPE,
158165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_140_WIDTH },
158166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_141_CHECKER_TYPE,
158167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_141_WIDTH },
158168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_142_CHECKER_TYPE,
158169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_142_WIDTH },
158170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_143_CHECKER_TYPE,
158171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_143_WIDTH },
158172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_144_CHECKER_TYPE,
158173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_144_WIDTH },
158174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_145_CHECKER_TYPE,
158175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_145_WIDTH },
158176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_146_CHECKER_TYPE,
158177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_146_WIDTH },
158178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_147_CHECKER_TYPE,
158179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_147_WIDTH },
158180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_148_CHECKER_TYPE,
158181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_148_WIDTH },
158182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_149_CHECKER_TYPE,
158183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_149_WIDTH },
158184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_150_CHECKER_TYPE,
158185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_150_WIDTH },
158186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_151_CHECKER_TYPE,
158187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_151_WIDTH },
158188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_152_CHECKER_TYPE,
158189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_152_WIDTH },
158190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_153_CHECKER_TYPE,
158191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_153_WIDTH },
158192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_154_CHECKER_TYPE,
158193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_154_WIDTH },
158194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_155_CHECKER_TYPE,
158195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_155_WIDTH },
158196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_156_CHECKER_TYPE,
158197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_156_WIDTH },
158198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_157_CHECKER_TYPE,
158199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_157_WIDTH },
158200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_158_CHECKER_TYPE,
158201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_158_WIDTH },
158202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_159_CHECKER_TYPE,
158203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_159_WIDTH },
158204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_160_CHECKER_TYPE,
158205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_160_WIDTH },
158206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_161_CHECKER_TYPE,
158207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_161_WIDTH },
158208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_162_CHECKER_TYPE,
158209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_162_WIDTH },
158210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_163_CHECKER_TYPE,
158211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_163_WIDTH },
158212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_164_CHECKER_TYPE,
158213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_164_WIDTH },
158214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_165_CHECKER_TYPE,
158215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_165_WIDTH },
158216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_166_CHECKER_TYPE,
158217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_166_WIDTH },
158218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_167_CHECKER_TYPE,
158219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_167_WIDTH },
158220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_168_CHECKER_TYPE,
158221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_168_WIDTH },
158222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_169_CHECKER_TYPE,
158223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_169_WIDTH },
158224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_170_CHECKER_TYPE,
158225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_170_WIDTH },
158226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_171_CHECKER_TYPE,
158227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_171_WIDTH },
158228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_172_CHECKER_TYPE,
158229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_172_WIDTH },
158230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_173_CHECKER_TYPE,
158231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_173_WIDTH },
158232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_174_CHECKER_TYPE,
158233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_174_WIDTH },
158234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_175_CHECKER_TYPE,
158235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_175_WIDTH },
158236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_176_CHECKER_TYPE,
158237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_176_WIDTH },
158238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_177_CHECKER_TYPE,
158239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_177_WIDTH },
158240  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_178_CHECKER_TYPE,
158241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_178_WIDTH },
158242  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_179_CHECKER_TYPE,
158243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_179_WIDTH },
158244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_180_CHECKER_TYPE,
158245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_180_WIDTH },
158246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_181_CHECKER_TYPE,
158247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_181_WIDTH },
158248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_182_CHECKER_TYPE,
158249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_182_WIDTH },
158250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_183_CHECKER_TYPE,
158251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_183_WIDTH },
158252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_184_CHECKER_TYPE,
158253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_184_WIDTH },
158254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_185_CHECKER_TYPE,
158255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_185_WIDTH },
158256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_186_CHECKER_TYPE,
158257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_186_WIDTH },
158258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_187_CHECKER_TYPE,
158259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_187_WIDTH },
158260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_188_CHECKER_TYPE,
158261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_188_WIDTH },
158262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_189_CHECKER_TYPE,
158263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_189_WIDTH },
158264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_190_CHECKER_TYPE,
158265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_190_WIDTH },
158266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_191_CHECKER_TYPE,
158267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_191_WIDTH },
158268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_192_CHECKER_TYPE,
158269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_192_WIDTH },
158270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_193_CHECKER_TYPE,
158271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_193_WIDTH },
158272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_194_CHECKER_TYPE,
158273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_194_WIDTH },
158274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_195_CHECKER_TYPE,
158275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_195_WIDTH },
158276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_196_CHECKER_TYPE,
158277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_196_WIDTH },
158278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_197_CHECKER_TYPE,
158279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_197_WIDTH },
158280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_198_CHECKER_TYPE,
158281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_198_WIDTH },
158282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_199_CHECKER_TYPE,
158283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_199_WIDTH },
158284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_200_CHECKER_TYPE,
158285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_200_WIDTH },
158286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_201_CHECKER_TYPE,
158287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_201_WIDTH },
158288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_202_CHECKER_TYPE,
158289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_202_WIDTH },
158290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_203_CHECKER_TYPE,
158291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_203_WIDTH },
158292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_204_CHECKER_TYPE,
158293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_204_WIDTH },
158294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_205_CHECKER_TYPE,
158295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_205_WIDTH },
158296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_206_CHECKER_TYPE,
158297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_206_WIDTH },
158298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_207_CHECKER_TYPE,
158299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_207_WIDTH },
158300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_208_CHECKER_TYPE,
158301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_208_WIDTH },
158302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_209_CHECKER_TYPE,
158303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_209_WIDTH },
158304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_210_CHECKER_TYPE,
158305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_210_WIDTH },
158306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_211_CHECKER_TYPE,
158307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_211_WIDTH },
158308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_212_CHECKER_TYPE,
158309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_212_WIDTH },
158310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_213_CHECKER_TYPE,
158311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_213_WIDTH },
158312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_214_CHECKER_TYPE,
158313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_214_WIDTH },
158314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_215_CHECKER_TYPE,
158315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_215_WIDTH },
158316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_216_CHECKER_TYPE,
158317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_216_WIDTH },
158318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_217_CHECKER_TYPE,
158319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_217_WIDTH },
158320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_218_CHECKER_TYPE,
158321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_218_WIDTH },
158322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_219_CHECKER_TYPE,
158323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_219_WIDTH },
158324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_220_CHECKER_TYPE,
158325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_220_WIDTH },
158326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_221_CHECKER_TYPE,
158327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_221_WIDTH },
158328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_222_CHECKER_TYPE,
158329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_222_WIDTH },
158330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_223_CHECKER_TYPE,
158331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_223_WIDTH },
158332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_224_CHECKER_TYPE,
158333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_224_WIDTH },
158334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_225_CHECKER_TYPE,
158335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_225_WIDTH },
158336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_226_CHECKER_TYPE,
158337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_226_WIDTH },
158338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_227_CHECKER_TYPE,
158339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_227_WIDTH },
158340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_228_CHECKER_TYPE,
158341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_228_WIDTH },
158342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_229_CHECKER_TYPE,
158343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_229_WIDTH },
158344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_230_CHECKER_TYPE,
158345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_230_WIDTH },
158346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_231_CHECKER_TYPE,
158347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_231_WIDTH },
158348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_232_CHECKER_TYPE,
158349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_232_WIDTH },
158350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_233_CHECKER_TYPE,
158351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_233_WIDTH },
158352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_234_CHECKER_TYPE,
158353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_234_WIDTH },
158354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_235_CHECKER_TYPE,
158355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_235_WIDTH },
158356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_236_CHECKER_TYPE,
158357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_236_WIDTH },
158358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_237_CHECKER_TYPE,
158359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_237_WIDTH },
158360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_238_CHECKER_TYPE,
158361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_238_WIDTH },
158362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_239_CHECKER_TYPE,
158363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_239_WIDTH },
158364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_240_CHECKER_TYPE,
158365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_240_WIDTH },
158366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_241_CHECKER_TYPE,
158367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_241_WIDTH },
158368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_242_CHECKER_TYPE,
158369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_242_WIDTH },
158370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_243_CHECKER_TYPE,
158371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_243_WIDTH },
158372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_244_CHECKER_TYPE,
158373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_244_WIDTH },
158374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_245_CHECKER_TYPE,
158375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_245_WIDTH },
158376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_246_CHECKER_TYPE,
158377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_246_WIDTH },
158378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_247_CHECKER_TYPE,
158379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_247_WIDTH },
158380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_248_CHECKER_TYPE,
158381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_248_WIDTH },
158382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_249_CHECKER_TYPE,
158383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_249_WIDTH },
158384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_250_CHECKER_TYPE,
158385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_250_WIDTH },
158386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_251_CHECKER_TYPE,
158387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_251_WIDTH },
158388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_252_CHECKER_TYPE,
158389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_252_WIDTH },
158390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_253_CHECKER_TYPE,
158391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_253_WIDTH },
158392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_254_CHECKER_TYPE,
158393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_254_WIDTH },
158394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_255_CHECKER_TYPE,
158395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_GROUP_255_WIDTH },
158396 };
158397 
158403 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_MAX_NUM_CHECKERS] =
158404 {
158405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_0_CHECKER_TYPE,
158406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_0_WIDTH },
158407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_1_CHECKER_TYPE,
158408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_1_WIDTH },
158409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_2_CHECKER_TYPE,
158410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_2_WIDTH },
158411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_3_CHECKER_TYPE,
158412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_3_WIDTH },
158413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_4_CHECKER_TYPE,
158414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_4_WIDTH },
158415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_5_CHECKER_TYPE,
158416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_5_WIDTH },
158417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_6_CHECKER_TYPE,
158418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_6_WIDTH },
158419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_7_CHECKER_TYPE,
158420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_7_WIDTH },
158421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_8_CHECKER_TYPE,
158422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_8_WIDTH },
158423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_9_CHECKER_TYPE,
158424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_9_WIDTH },
158425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_10_CHECKER_TYPE,
158426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_10_WIDTH },
158427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_11_CHECKER_TYPE,
158428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_11_WIDTH },
158429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_12_CHECKER_TYPE,
158430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_12_WIDTH },
158431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_13_CHECKER_TYPE,
158432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_13_WIDTH },
158433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_14_CHECKER_TYPE,
158434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_14_WIDTH },
158435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_15_CHECKER_TYPE,
158436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_15_WIDTH },
158437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_16_CHECKER_TYPE,
158438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_16_WIDTH },
158439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_17_CHECKER_TYPE,
158440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_17_WIDTH },
158441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_18_CHECKER_TYPE,
158442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_18_WIDTH },
158443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_19_CHECKER_TYPE,
158444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_19_WIDTH },
158445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_20_CHECKER_TYPE,
158446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_20_WIDTH },
158447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_21_CHECKER_TYPE,
158448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_21_WIDTH },
158449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_22_CHECKER_TYPE,
158450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_22_WIDTH },
158451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_23_CHECKER_TYPE,
158452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_23_WIDTH },
158453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_24_CHECKER_TYPE,
158454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_24_WIDTH },
158455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_25_CHECKER_TYPE,
158456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_25_WIDTH },
158457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_26_CHECKER_TYPE,
158458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_26_WIDTH },
158459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_27_CHECKER_TYPE,
158460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_27_WIDTH },
158461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_28_CHECKER_TYPE,
158462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_28_WIDTH },
158463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_29_CHECKER_TYPE,
158464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_29_WIDTH },
158465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_30_CHECKER_TYPE,
158466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_30_WIDTH },
158467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_31_CHECKER_TYPE,
158468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_31_WIDTH },
158469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_32_CHECKER_TYPE,
158470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_32_WIDTH },
158471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_33_CHECKER_TYPE,
158472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_33_WIDTH },
158473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_34_CHECKER_TYPE,
158474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_34_WIDTH },
158475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_35_CHECKER_TYPE,
158476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_35_WIDTH },
158477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_36_CHECKER_TYPE,
158478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_36_WIDTH },
158479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_37_CHECKER_TYPE,
158480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_37_WIDTH },
158481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_38_CHECKER_TYPE,
158482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_38_WIDTH },
158483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_39_CHECKER_TYPE,
158484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_39_WIDTH },
158485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_40_CHECKER_TYPE,
158486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_40_WIDTH },
158487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_41_CHECKER_TYPE,
158488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_41_WIDTH },
158489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_42_CHECKER_TYPE,
158490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_42_WIDTH },
158491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_43_CHECKER_TYPE,
158492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_43_WIDTH },
158493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_44_CHECKER_TYPE,
158494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_44_WIDTH },
158495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_45_CHECKER_TYPE,
158496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_45_WIDTH },
158497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_46_CHECKER_TYPE,
158498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_46_WIDTH },
158499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_47_CHECKER_TYPE,
158500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_47_WIDTH },
158501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_48_CHECKER_TYPE,
158502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_48_WIDTH },
158503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_49_CHECKER_TYPE,
158504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_49_WIDTH },
158505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_50_CHECKER_TYPE,
158506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_50_WIDTH },
158507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_51_CHECKER_TYPE,
158508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_51_WIDTH },
158509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_52_CHECKER_TYPE,
158510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_52_WIDTH },
158511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_53_CHECKER_TYPE,
158512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_53_WIDTH },
158513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_54_CHECKER_TYPE,
158514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_54_WIDTH },
158515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_55_CHECKER_TYPE,
158516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_55_WIDTH },
158517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_56_CHECKER_TYPE,
158518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_56_WIDTH },
158519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_57_CHECKER_TYPE,
158520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_57_WIDTH },
158521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_58_CHECKER_TYPE,
158522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_58_WIDTH },
158523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_59_CHECKER_TYPE,
158524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_59_WIDTH },
158525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_60_CHECKER_TYPE,
158526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_60_WIDTH },
158527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_61_CHECKER_TYPE,
158528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_61_WIDTH },
158529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_62_CHECKER_TYPE,
158530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_62_WIDTH },
158531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_63_CHECKER_TYPE,
158532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_63_WIDTH },
158533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_64_CHECKER_TYPE,
158534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_64_WIDTH },
158535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_65_CHECKER_TYPE,
158536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_65_WIDTH },
158537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_66_CHECKER_TYPE,
158538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_66_WIDTH },
158539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_67_CHECKER_TYPE,
158540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_67_WIDTH },
158541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_68_CHECKER_TYPE,
158542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_68_WIDTH },
158543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_69_CHECKER_TYPE,
158544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_69_WIDTH },
158545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_70_CHECKER_TYPE,
158546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_70_WIDTH },
158547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_71_CHECKER_TYPE,
158548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_71_WIDTH },
158549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_72_CHECKER_TYPE,
158550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_72_WIDTH },
158551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_73_CHECKER_TYPE,
158552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_73_WIDTH },
158553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_74_CHECKER_TYPE,
158554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_74_WIDTH },
158555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_75_CHECKER_TYPE,
158556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_75_WIDTH },
158557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_76_CHECKER_TYPE,
158558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_76_WIDTH },
158559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_77_CHECKER_TYPE,
158560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_77_WIDTH },
158561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_78_CHECKER_TYPE,
158562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_78_WIDTH },
158563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_79_CHECKER_TYPE,
158564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_79_WIDTH },
158565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_80_CHECKER_TYPE,
158566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_80_WIDTH },
158567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_81_CHECKER_TYPE,
158568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_81_WIDTH },
158569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_82_CHECKER_TYPE,
158570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_82_WIDTH },
158571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_83_CHECKER_TYPE,
158572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_83_WIDTH },
158573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_84_CHECKER_TYPE,
158574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_84_WIDTH },
158575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_85_CHECKER_TYPE,
158576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_85_WIDTH },
158577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_86_CHECKER_TYPE,
158578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_86_WIDTH },
158579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_87_CHECKER_TYPE,
158580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_87_WIDTH },
158581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_88_CHECKER_TYPE,
158582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_88_WIDTH },
158583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_89_CHECKER_TYPE,
158584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_89_WIDTH },
158585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_90_CHECKER_TYPE,
158586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_90_WIDTH },
158587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_91_CHECKER_TYPE,
158588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_91_WIDTH },
158589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_92_CHECKER_TYPE,
158590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_92_WIDTH },
158591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_93_CHECKER_TYPE,
158592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_93_WIDTH },
158593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_94_CHECKER_TYPE,
158594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_94_WIDTH },
158595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_95_CHECKER_TYPE,
158596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_95_WIDTH },
158597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_96_CHECKER_TYPE,
158598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_96_WIDTH },
158599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_97_CHECKER_TYPE,
158600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_97_WIDTH },
158601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_98_CHECKER_TYPE,
158602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_98_WIDTH },
158603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_99_CHECKER_TYPE,
158604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_99_WIDTH },
158605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_100_CHECKER_TYPE,
158606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_100_WIDTH },
158607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_101_CHECKER_TYPE,
158608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_101_WIDTH },
158609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_102_CHECKER_TYPE,
158610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_102_WIDTH },
158611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_103_CHECKER_TYPE,
158612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_103_WIDTH },
158613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_104_CHECKER_TYPE,
158614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_104_WIDTH },
158615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_105_CHECKER_TYPE,
158616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_105_WIDTH },
158617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_106_CHECKER_TYPE,
158618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_106_WIDTH },
158619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_107_CHECKER_TYPE,
158620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_107_WIDTH },
158621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_108_CHECKER_TYPE,
158622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_108_WIDTH },
158623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_109_CHECKER_TYPE,
158624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_109_WIDTH },
158625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_110_CHECKER_TYPE,
158626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_110_WIDTH },
158627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_111_CHECKER_TYPE,
158628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_111_WIDTH },
158629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_112_CHECKER_TYPE,
158630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_112_WIDTH },
158631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_113_CHECKER_TYPE,
158632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_113_WIDTH },
158633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_114_CHECKER_TYPE,
158634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_114_WIDTH },
158635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_115_CHECKER_TYPE,
158636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_115_WIDTH },
158637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_116_CHECKER_TYPE,
158638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_116_WIDTH },
158639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_117_CHECKER_TYPE,
158640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_117_WIDTH },
158641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_118_CHECKER_TYPE,
158642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_118_WIDTH },
158643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_119_CHECKER_TYPE,
158644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_119_WIDTH },
158645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_120_CHECKER_TYPE,
158646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_120_WIDTH },
158647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_121_CHECKER_TYPE,
158648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_121_WIDTH },
158649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_122_CHECKER_TYPE,
158650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_122_WIDTH },
158651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_123_CHECKER_TYPE,
158652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_123_WIDTH },
158653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_124_CHECKER_TYPE,
158654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_124_WIDTH },
158655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_125_CHECKER_TYPE,
158656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_125_WIDTH },
158657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_126_CHECKER_TYPE,
158658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_126_WIDTH },
158659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_127_CHECKER_TYPE,
158660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_127_WIDTH },
158661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_128_CHECKER_TYPE,
158662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_128_WIDTH },
158663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_129_CHECKER_TYPE,
158664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_129_WIDTH },
158665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_130_CHECKER_TYPE,
158666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_130_WIDTH },
158667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_131_CHECKER_TYPE,
158668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_131_WIDTH },
158669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_132_CHECKER_TYPE,
158670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_132_WIDTH },
158671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_133_CHECKER_TYPE,
158672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_133_WIDTH },
158673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_134_CHECKER_TYPE,
158674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_134_WIDTH },
158675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_135_CHECKER_TYPE,
158676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_135_WIDTH },
158677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_136_CHECKER_TYPE,
158678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_136_WIDTH },
158679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_137_CHECKER_TYPE,
158680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_137_WIDTH },
158681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_138_CHECKER_TYPE,
158682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_138_WIDTH },
158683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_139_CHECKER_TYPE,
158684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_139_WIDTH },
158685  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_140_CHECKER_TYPE,
158686  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_140_WIDTH },
158687  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_141_CHECKER_TYPE,
158688  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_141_WIDTH },
158689  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_142_CHECKER_TYPE,
158690  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_142_WIDTH },
158691  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_143_CHECKER_TYPE,
158692  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_143_WIDTH },
158693  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_144_CHECKER_TYPE,
158694  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_144_WIDTH },
158695  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_145_CHECKER_TYPE,
158696  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_145_WIDTH },
158697  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_146_CHECKER_TYPE,
158698  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_146_WIDTH },
158699  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_147_CHECKER_TYPE,
158700  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_147_WIDTH },
158701  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_148_CHECKER_TYPE,
158702  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_148_WIDTH },
158703  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_149_CHECKER_TYPE,
158704  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_149_WIDTH },
158705  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_150_CHECKER_TYPE,
158706  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_150_WIDTH },
158707  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_151_CHECKER_TYPE,
158708  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_151_WIDTH },
158709  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_152_CHECKER_TYPE,
158710  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_152_WIDTH },
158711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_153_CHECKER_TYPE,
158712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_153_WIDTH },
158713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_154_CHECKER_TYPE,
158714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_154_WIDTH },
158715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_155_CHECKER_TYPE,
158716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_155_WIDTH },
158717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_156_CHECKER_TYPE,
158718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_156_WIDTH },
158719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_157_CHECKER_TYPE,
158720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_157_WIDTH },
158721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_158_CHECKER_TYPE,
158722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_158_WIDTH },
158723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_159_CHECKER_TYPE,
158724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_159_WIDTH },
158725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_160_CHECKER_TYPE,
158726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_160_WIDTH },
158727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_161_CHECKER_TYPE,
158728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_161_WIDTH },
158729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_162_CHECKER_TYPE,
158730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_162_WIDTH },
158731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_163_CHECKER_TYPE,
158732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_163_WIDTH },
158733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_164_CHECKER_TYPE,
158734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_164_WIDTH },
158735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_165_CHECKER_TYPE,
158736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_165_WIDTH },
158737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_166_CHECKER_TYPE,
158738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_166_WIDTH },
158739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_167_CHECKER_TYPE,
158740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_167_WIDTH },
158741  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_168_CHECKER_TYPE,
158742  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_168_WIDTH },
158743  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_169_CHECKER_TYPE,
158744  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_169_WIDTH },
158745  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_170_CHECKER_TYPE,
158746  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_170_WIDTH },
158747  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_171_CHECKER_TYPE,
158748  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_171_WIDTH },
158749  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_172_CHECKER_TYPE,
158750  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_172_WIDTH },
158751  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_173_CHECKER_TYPE,
158752  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_173_WIDTH },
158753  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_174_CHECKER_TYPE,
158754  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_174_WIDTH },
158755  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_175_CHECKER_TYPE,
158756  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_175_WIDTH },
158757  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_176_CHECKER_TYPE,
158758  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_176_WIDTH },
158759  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_177_CHECKER_TYPE,
158760  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_177_WIDTH },
158761  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_178_CHECKER_TYPE,
158762  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_178_WIDTH },
158763  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_179_CHECKER_TYPE,
158764  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_179_WIDTH },
158765  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_180_CHECKER_TYPE,
158766  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_180_WIDTH },
158767  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_181_CHECKER_TYPE,
158768  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_181_WIDTH },
158769  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_182_CHECKER_TYPE,
158770  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_182_WIDTH },
158771  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_183_CHECKER_TYPE,
158772  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_183_WIDTH },
158773  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_184_CHECKER_TYPE,
158774  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_184_WIDTH },
158775  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_185_CHECKER_TYPE,
158776  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_185_WIDTH },
158777  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_186_CHECKER_TYPE,
158778  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_186_WIDTH },
158779  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_187_CHECKER_TYPE,
158780  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_187_WIDTH },
158781  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_188_CHECKER_TYPE,
158782  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_188_WIDTH },
158783  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_189_CHECKER_TYPE,
158784  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_189_WIDTH },
158785  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_190_CHECKER_TYPE,
158786  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_190_WIDTH },
158787  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_191_CHECKER_TYPE,
158788  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_191_WIDTH },
158789  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_192_CHECKER_TYPE,
158790  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_192_WIDTH },
158791  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_193_CHECKER_TYPE,
158792  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_193_WIDTH },
158793  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_194_CHECKER_TYPE,
158794  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_194_WIDTH },
158795  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_195_CHECKER_TYPE,
158796  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_195_WIDTH },
158797  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_196_CHECKER_TYPE,
158798  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_196_WIDTH },
158799  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_197_CHECKER_TYPE,
158800  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_197_WIDTH },
158801  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_198_CHECKER_TYPE,
158802  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_198_WIDTH },
158803  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_199_CHECKER_TYPE,
158804  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_199_WIDTH },
158805  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_200_CHECKER_TYPE,
158806  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_200_WIDTH },
158807  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_201_CHECKER_TYPE,
158808  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_201_WIDTH },
158809  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_202_CHECKER_TYPE,
158810  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_202_WIDTH },
158811  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_203_CHECKER_TYPE,
158812  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_203_WIDTH },
158813  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_204_CHECKER_TYPE,
158814  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_204_WIDTH },
158815  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_205_CHECKER_TYPE,
158816  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_205_WIDTH },
158817  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_206_CHECKER_TYPE,
158818  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_206_WIDTH },
158819  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_207_CHECKER_TYPE,
158820  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_207_WIDTH },
158821  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_208_CHECKER_TYPE,
158822  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_208_WIDTH },
158823  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_209_CHECKER_TYPE,
158824  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_209_WIDTH },
158825  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_210_CHECKER_TYPE,
158826  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_210_WIDTH },
158827  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_211_CHECKER_TYPE,
158828  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_211_WIDTH },
158829  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_212_CHECKER_TYPE,
158830  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_212_WIDTH },
158831  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_213_CHECKER_TYPE,
158832  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_213_WIDTH },
158833  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_214_CHECKER_TYPE,
158834  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_214_WIDTH },
158835  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_215_CHECKER_TYPE,
158836  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_215_WIDTH },
158837  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_216_CHECKER_TYPE,
158838  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_216_WIDTH },
158839  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_217_CHECKER_TYPE,
158840  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_217_WIDTH },
158841  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_218_CHECKER_TYPE,
158842  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_218_WIDTH },
158843  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_219_CHECKER_TYPE,
158844  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_219_WIDTH },
158845  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_220_CHECKER_TYPE,
158846  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_220_WIDTH },
158847  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_221_CHECKER_TYPE,
158848  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_221_WIDTH },
158849  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_222_CHECKER_TYPE,
158850  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_222_WIDTH },
158851  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_223_CHECKER_TYPE,
158852  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_223_WIDTH },
158853  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_224_CHECKER_TYPE,
158854  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_224_WIDTH },
158855  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_225_CHECKER_TYPE,
158856  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_225_WIDTH },
158857  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_226_CHECKER_TYPE,
158858  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_226_WIDTH },
158859  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_227_CHECKER_TYPE,
158860  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_227_WIDTH },
158861  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_228_CHECKER_TYPE,
158862  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_228_WIDTH },
158863  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_229_CHECKER_TYPE,
158864  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_229_WIDTH },
158865  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_230_CHECKER_TYPE,
158866  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_230_WIDTH },
158867  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_231_CHECKER_TYPE,
158868  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_231_WIDTH },
158869  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_232_CHECKER_TYPE,
158870  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_232_WIDTH },
158871  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_233_CHECKER_TYPE,
158872  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_233_WIDTH },
158873  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_234_CHECKER_TYPE,
158874  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_234_WIDTH },
158875  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_235_CHECKER_TYPE,
158876  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_235_WIDTH },
158877  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_236_CHECKER_TYPE,
158878  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_236_WIDTH },
158879  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_237_CHECKER_TYPE,
158880  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_237_WIDTH },
158881  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_238_CHECKER_TYPE,
158882  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_238_WIDTH },
158883  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_239_CHECKER_TYPE,
158884  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_239_WIDTH },
158885  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_240_CHECKER_TYPE,
158886  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_240_WIDTH },
158887  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_241_CHECKER_TYPE,
158888  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_241_WIDTH },
158889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_242_CHECKER_TYPE,
158890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_242_WIDTH },
158891  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_243_CHECKER_TYPE,
158892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_243_WIDTH },
158893  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_244_CHECKER_TYPE,
158894  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_244_WIDTH },
158895  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_245_CHECKER_TYPE,
158896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_245_WIDTH },
158897  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_246_CHECKER_TYPE,
158898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_246_WIDTH },
158899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_247_CHECKER_TYPE,
158900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_247_WIDTH },
158901  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_248_CHECKER_TYPE,
158902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_248_WIDTH },
158903  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_249_CHECKER_TYPE,
158904  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_249_WIDTH },
158905  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_250_CHECKER_TYPE,
158906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_250_WIDTH },
158907  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_251_CHECKER_TYPE,
158908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_251_WIDTH },
158909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_252_CHECKER_TYPE,
158910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_252_WIDTH },
158911  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_253_CHECKER_TYPE,
158912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_253_WIDTH },
158913  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_254_CHECKER_TYPE,
158914  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_254_WIDTH },
158915  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_255_CHECKER_TYPE,
158916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_GROUP_255_WIDTH },
158917 };
158918 
158924 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_MAX_NUM_CHECKERS] =
158925 {
158926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_0_CHECKER_TYPE,
158927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_0_WIDTH },
158928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_1_CHECKER_TYPE,
158929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_1_WIDTH },
158930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_2_CHECKER_TYPE,
158931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_2_WIDTH },
158932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_3_CHECKER_TYPE,
158933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_3_WIDTH },
158934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_4_CHECKER_TYPE,
158935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_4_WIDTH },
158936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_5_CHECKER_TYPE,
158937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_5_WIDTH },
158938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_6_CHECKER_TYPE,
158939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_6_WIDTH },
158940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_7_CHECKER_TYPE,
158941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_7_WIDTH },
158942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_8_CHECKER_TYPE,
158943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_8_WIDTH },
158944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_9_CHECKER_TYPE,
158945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_9_WIDTH },
158946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_10_CHECKER_TYPE,
158947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_10_WIDTH },
158948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_11_CHECKER_TYPE,
158949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_11_WIDTH },
158950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_12_CHECKER_TYPE,
158951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_12_WIDTH },
158952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_13_CHECKER_TYPE,
158953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_13_WIDTH },
158954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_14_CHECKER_TYPE,
158955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_14_WIDTH },
158956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_15_CHECKER_TYPE,
158957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_15_WIDTH },
158958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_16_CHECKER_TYPE,
158959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_16_WIDTH },
158960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_17_CHECKER_TYPE,
158961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_17_WIDTH },
158962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_18_CHECKER_TYPE,
158963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_18_WIDTH },
158964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_19_CHECKER_TYPE,
158965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_19_WIDTH },
158966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_20_CHECKER_TYPE,
158967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_20_WIDTH },
158968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_21_CHECKER_TYPE,
158969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_21_WIDTH },
158970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_22_CHECKER_TYPE,
158971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_22_WIDTH },
158972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_23_CHECKER_TYPE,
158973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_23_WIDTH },
158974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_24_CHECKER_TYPE,
158975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_24_WIDTH },
158976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_25_CHECKER_TYPE,
158977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_25_WIDTH },
158978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_26_CHECKER_TYPE,
158979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_26_WIDTH },
158980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_27_CHECKER_TYPE,
158981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_27_WIDTH },
158982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_28_CHECKER_TYPE,
158983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_28_WIDTH },
158984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_29_CHECKER_TYPE,
158985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_29_WIDTH },
158986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_30_CHECKER_TYPE,
158987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_30_WIDTH },
158988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_31_CHECKER_TYPE,
158989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_31_WIDTH },
158990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_32_CHECKER_TYPE,
158991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_32_WIDTH },
158992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_33_CHECKER_TYPE,
158993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_33_WIDTH },
158994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_34_CHECKER_TYPE,
158995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_34_WIDTH },
158996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_35_CHECKER_TYPE,
158997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_35_WIDTH },
158998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_36_CHECKER_TYPE,
158999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_36_WIDTH },
159000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_37_CHECKER_TYPE,
159001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_37_WIDTH },
159002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_38_CHECKER_TYPE,
159003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_38_WIDTH },
159004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_39_CHECKER_TYPE,
159005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_39_WIDTH },
159006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_40_CHECKER_TYPE,
159007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_40_WIDTH },
159008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_41_CHECKER_TYPE,
159009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_41_WIDTH },
159010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_42_CHECKER_TYPE,
159011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_42_WIDTH },
159012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_43_CHECKER_TYPE,
159013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_43_WIDTH },
159014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_44_CHECKER_TYPE,
159015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_44_WIDTH },
159016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_45_CHECKER_TYPE,
159017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_45_WIDTH },
159018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_46_CHECKER_TYPE,
159019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_46_WIDTH },
159020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_47_CHECKER_TYPE,
159021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_47_WIDTH },
159022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_48_CHECKER_TYPE,
159023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_48_WIDTH },
159024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_49_CHECKER_TYPE,
159025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_49_WIDTH },
159026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_50_CHECKER_TYPE,
159027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_50_WIDTH },
159028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_51_CHECKER_TYPE,
159029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_51_WIDTH },
159030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_52_CHECKER_TYPE,
159031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_52_WIDTH },
159032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_53_CHECKER_TYPE,
159033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_53_WIDTH },
159034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_54_CHECKER_TYPE,
159035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_54_WIDTH },
159036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_55_CHECKER_TYPE,
159037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_55_WIDTH },
159038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_56_CHECKER_TYPE,
159039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_56_WIDTH },
159040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_57_CHECKER_TYPE,
159041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_GROUP_57_WIDTH },
159042 };
159043 
159049 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS] =
159050 {
159051  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_0_CHECKER_TYPE,
159052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_0_WIDTH },
159053  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_1_CHECKER_TYPE,
159054  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_1_WIDTH },
159055  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_2_CHECKER_TYPE,
159056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_2_WIDTH },
159057  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_3_CHECKER_TYPE,
159058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_3_WIDTH },
159059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_4_CHECKER_TYPE,
159060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_4_WIDTH },
159061  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_5_CHECKER_TYPE,
159062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_5_WIDTH },
159063  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_6_CHECKER_TYPE,
159064  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_6_WIDTH },
159065  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_7_CHECKER_TYPE,
159066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_7_WIDTH },
159067  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_8_CHECKER_TYPE,
159068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_8_WIDTH },
159069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_9_CHECKER_TYPE,
159070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_9_WIDTH },
159071  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_10_CHECKER_TYPE,
159072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_10_WIDTH },
159073  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_11_CHECKER_TYPE,
159074  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_11_WIDTH },
159075  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_12_CHECKER_TYPE,
159076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_12_WIDTH },
159077  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_13_CHECKER_TYPE,
159078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_13_WIDTH },
159079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_14_CHECKER_TYPE,
159080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_14_WIDTH },
159081  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_15_CHECKER_TYPE,
159082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_15_WIDTH },
159083  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_16_CHECKER_TYPE,
159084  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_16_WIDTH },
159085  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_17_CHECKER_TYPE,
159086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_17_WIDTH },
159087  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_18_CHECKER_TYPE,
159088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_18_WIDTH },
159089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_19_CHECKER_TYPE,
159090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_19_WIDTH },
159091  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_20_CHECKER_TYPE,
159092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_20_WIDTH },
159093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_21_CHECKER_TYPE,
159094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_21_WIDTH },
159095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_22_CHECKER_TYPE,
159096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_22_WIDTH },
159097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_23_CHECKER_TYPE,
159098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_23_WIDTH },
159099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_24_CHECKER_TYPE,
159100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_24_WIDTH },
159101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_25_CHECKER_TYPE,
159102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_25_WIDTH },
159103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_26_CHECKER_TYPE,
159104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_26_WIDTH },
159105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_27_CHECKER_TYPE,
159106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_27_WIDTH },
159107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_28_CHECKER_TYPE,
159108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_28_WIDTH },
159109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_29_CHECKER_TYPE,
159110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_29_WIDTH },
159111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_30_CHECKER_TYPE,
159112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_30_WIDTH },
159113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_31_CHECKER_TYPE,
159114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_31_WIDTH },
159115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_32_CHECKER_TYPE,
159116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_32_WIDTH },
159117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_33_CHECKER_TYPE,
159118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_33_WIDTH },
159119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_34_CHECKER_TYPE,
159120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_34_WIDTH },
159121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_35_CHECKER_TYPE,
159122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_35_WIDTH },
159123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_36_CHECKER_TYPE,
159124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_36_WIDTH },
159125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_37_CHECKER_TYPE,
159126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_37_WIDTH },
159127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_38_CHECKER_TYPE,
159128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_38_WIDTH },
159129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_39_CHECKER_TYPE,
159130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_39_WIDTH },
159131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_40_CHECKER_TYPE,
159132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_40_WIDTH },
159133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_41_CHECKER_TYPE,
159134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_41_WIDTH },
159135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_42_CHECKER_TYPE,
159136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_42_WIDTH },
159137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_43_CHECKER_TYPE,
159138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_43_WIDTH },
159139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_44_CHECKER_TYPE,
159140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_44_WIDTH },
159141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_45_CHECKER_TYPE,
159142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_45_WIDTH },
159143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_46_CHECKER_TYPE,
159144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_46_WIDTH },
159145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_47_CHECKER_TYPE,
159146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_47_WIDTH },
159147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_48_CHECKER_TYPE,
159148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_48_WIDTH },
159149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_49_CHECKER_TYPE,
159150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_49_WIDTH },
159151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_50_CHECKER_TYPE,
159152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_50_WIDTH },
159153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_51_CHECKER_TYPE,
159154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_51_WIDTH },
159155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_52_CHECKER_TYPE,
159156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_52_WIDTH },
159157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_53_CHECKER_TYPE,
159158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_53_WIDTH },
159159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_54_CHECKER_TYPE,
159160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_54_WIDTH },
159161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_55_CHECKER_TYPE,
159162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_55_WIDTH },
159163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_56_CHECKER_TYPE,
159164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_56_WIDTH },
159165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_57_CHECKER_TYPE,
159166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_57_WIDTH },
159167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_58_CHECKER_TYPE,
159168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_58_WIDTH },
159169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_59_CHECKER_TYPE,
159170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_59_WIDTH },
159171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_60_CHECKER_TYPE,
159172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_60_WIDTH },
159173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_61_CHECKER_TYPE,
159174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_61_WIDTH },
159175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_62_CHECKER_TYPE,
159176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_62_WIDTH },
159177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_63_CHECKER_TYPE,
159178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_63_WIDTH },
159179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_64_CHECKER_TYPE,
159180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_64_WIDTH },
159181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_65_CHECKER_TYPE,
159182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_65_WIDTH },
159183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_66_CHECKER_TYPE,
159184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_66_WIDTH },
159185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_67_CHECKER_TYPE,
159186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_67_WIDTH },
159187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_68_CHECKER_TYPE,
159188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_68_WIDTH },
159189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_69_CHECKER_TYPE,
159190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_69_WIDTH },
159191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_70_CHECKER_TYPE,
159192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_70_WIDTH },
159193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_71_CHECKER_TYPE,
159194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_71_WIDTH },
159195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_72_CHECKER_TYPE,
159196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_72_WIDTH },
159197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_73_CHECKER_TYPE,
159198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_73_WIDTH },
159199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_74_CHECKER_TYPE,
159200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_74_WIDTH },
159201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_75_CHECKER_TYPE,
159202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_75_WIDTH },
159203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_76_CHECKER_TYPE,
159204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_76_WIDTH },
159205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_77_CHECKER_TYPE,
159206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_77_WIDTH },
159207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_78_CHECKER_TYPE,
159208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_78_WIDTH },
159209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_79_CHECKER_TYPE,
159210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_79_WIDTH },
159211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_80_CHECKER_TYPE,
159212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_80_WIDTH },
159213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_81_CHECKER_TYPE,
159214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_81_WIDTH },
159215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_82_CHECKER_TYPE,
159216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_82_WIDTH },
159217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_83_CHECKER_TYPE,
159218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_83_WIDTH },
159219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_84_CHECKER_TYPE,
159220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_84_WIDTH },
159221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_85_CHECKER_TYPE,
159222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_85_WIDTH },
159223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_86_CHECKER_TYPE,
159224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_86_WIDTH },
159225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_87_CHECKER_TYPE,
159226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_87_WIDTH },
159227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_88_CHECKER_TYPE,
159228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_88_WIDTH },
159229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_89_CHECKER_TYPE,
159230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_89_WIDTH },
159231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_90_CHECKER_TYPE,
159232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_90_WIDTH },
159233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_91_CHECKER_TYPE,
159234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_91_WIDTH },
159235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_92_CHECKER_TYPE,
159236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_92_WIDTH },
159237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_93_CHECKER_TYPE,
159238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_93_WIDTH },
159239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_94_CHECKER_TYPE,
159240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_94_WIDTH },
159241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_95_CHECKER_TYPE,
159242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_95_WIDTH },
159243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_96_CHECKER_TYPE,
159244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_96_WIDTH },
159245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_97_CHECKER_TYPE,
159246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_97_WIDTH },
159247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_98_CHECKER_TYPE,
159248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_98_WIDTH },
159249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_99_CHECKER_TYPE,
159250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_99_WIDTH },
159251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_100_CHECKER_TYPE,
159252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_100_WIDTH },
159253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_101_CHECKER_TYPE,
159254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_101_WIDTH },
159255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_102_CHECKER_TYPE,
159256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_102_WIDTH },
159257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_103_CHECKER_TYPE,
159258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_103_WIDTH },
159259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_104_CHECKER_TYPE,
159260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_104_WIDTH },
159261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_105_CHECKER_TYPE,
159262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_105_WIDTH },
159263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_106_CHECKER_TYPE,
159264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_106_WIDTH },
159265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_107_CHECKER_TYPE,
159266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_107_WIDTH },
159267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_108_CHECKER_TYPE,
159268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_108_WIDTH },
159269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_109_CHECKER_TYPE,
159270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_109_WIDTH },
159271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_110_CHECKER_TYPE,
159272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_110_WIDTH },
159273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_111_CHECKER_TYPE,
159274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_111_WIDTH },
159275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_112_CHECKER_TYPE,
159276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_112_WIDTH },
159277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_113_CHECKER_TYPE,
159278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_113_WIDTH },
159279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_114_CHECKER_TYPE,
159280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_114_WIDTH },
159281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_115_CHECKER_TYPE,
159282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_115_WIDTH },
159283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_116_CHECKER_TYPE,
159284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_116_WIDTH },
159285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_117_CHECKER_TYPE,
159286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_117_WIDTH },
159287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_118_CHECKER_TYPE,
159288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_118_WIDTH },
159289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_119_CHECKER_TYPE,
159290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_119_WIDTH },
159291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_120_CHECKER_TYPE,
159292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_120_WIDTH },
159293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_121_CHECKER_TYPE,
159294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_121_WIDTH },
159295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_122_CHECKER_TYPE,
159296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_122_WIDTH },
159297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_123_CHECKER_TYPE,
159298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_123_WIDTH },
159299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_124_CHECKER_TYPE,
159300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_124_WIDTH },
159301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_125_CHECKER_TYPE,
159302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_125_WIDTH },
159303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_126_CHECKER_TYPE,
159304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_126_WIDTH },
159305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_127_CHECKER_TYPE,
159306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_127_WIDTH },
159307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_128_CHECKER_TYPE,
159308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_128_WIDTH },
159309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_129_CHECKER_TYPE,
159310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_129_WIDTH },
159311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_130_CHECKER_TYPE,
159312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_130_WIDTH },
159313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_131_CHECKER_TYPE,
159314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_131_WIDTH },
159315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_132_CHECKER_TYPE,
159316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_132_WIDTH },
159317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_133_CHECKER_TYPE,
159318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_133_WIDTH },
159319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_134_CHECKER_TYPE,
159320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_134_WIDTH },
159321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_135_CHECKER_TYPE,
159322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_135_WIDTH },
159323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_136_CHECKER_TYPE,
159324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_136_WIDTH },
159325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_137_CHECKER_TYPE,
159326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_137_WIDTH },
159327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_138_CHECKER_TYPE,
159328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_138_WIDTH },
159329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_139_CHECKER_TYPE,
159330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_139_WIDTH },
159331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_140_CHECKER_TYPE,
159332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_140_WIDTH },
159333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_141_CHECKER_TYPE,
159334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_141_WIDTH },
159335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_142_CHECKER_TYPE,
159336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_142_WIDTH },
159337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_143_CHECKER_TYPE,
159338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_143_WIDTH },
159339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_144_CHECKER_TYPE,
159340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_144_WIDTH },
159341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_145_CHECKER_TYPE,
159342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_145_WIDTH },
159343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_146_CHECKER_TYPE,
159344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_146_WIDTH },
159345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_147_CHECKER_TYPE,
159346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_147_WIDTH },
159347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_148_CHECKER_TYPE,
159348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_148_WIDTH },
159349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_149_CHECKER_TYPE,
159350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_149_WIDTH },
159351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_150_CHECKER_TYPE,
159352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_150_WIDTH },
159353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_151_CHECKER_TYPE,
159354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_151_WIDTH },
159355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_152_CHECKER_TYPE,
159356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_152_WIDTH },
159357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_153_CHECKER_TYPE,
159358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_153_WIDTH },
159359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_154_CHECKER_TYPE,
159360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_154_WIDTH },
159361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_155_CHECKER_TYPE,
159362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_155_WIDTH },
159363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_156_CHECKER_TYPE,
159364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_156_WIDTH },
159365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_157_CHECKER_TYPE,
159366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_157_WIDTH },
159367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_158_CHECKER_TYPE,
159368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_158_WIDTH },
159369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_159_CHECKER_TYPE,
159370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_159_WIDTH },
159371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_160_CHECKER_TYPE,
159372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_160_WIDTH },
159373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_161_CHECKER_TYPE,
159374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_161_WIDTH },
159375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_162_CHECKER_TYPE,
159376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_162_WIDTH },
159377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_163_CHECKER_TYPE,
159378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_163_WIDTH },
159379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_164_CHECKER_TYPE,
159380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_164_WIDTH },
159381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_165_CHECKER_TYPE,
159382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_165_WIDTH },
159383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_166_CHECKER_TYPE,
159384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_166_WIDTH },
159385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_167_CHECKER_TYPE,
159386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_167_WIDTH },
159387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_168_CHECKER_TYPE,
159388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_168_WIDTH },
159389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_169_CHECKER_TYPE,
159390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_169_WIDTH },
159391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_170_CHECKER_TYPE,
159392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_170_WIDTH },
159393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_171_CHECKER_TYPE,
159394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_171_WIDTH },
159395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_172_CHECKER_TYPE,
159396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_172_WIDTH },
159397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_173_CHECKER_TYPE,
159398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_173_WIDTH },
159399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_174_CHECKER_TYPE,
159400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_174_WIDTH },
159401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_175_CHECKER_TYPE,
159402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_175_WIDTH },
159403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_176_CHECKER_TYPE,
159404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_176_WIDTH },
159405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_177_CHECKER_TYPE,
159406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_177_WIDTH },
159407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_178_CHECKER_TYPE,
159408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_178_WIDTH },
159409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_179_CHECKER_TYPE,
159410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_179_WIDTH },
159411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_180_CHECKER_TYPE,
159412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_180_WIDTH },
159413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_181_CHECKER_TYPE,
159414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_181_WIDTH },
159415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_182_CHECKER_TYPE,
159416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_182_WIDTH },
159417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_183_CHECKER_TYPE,
159418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_183_WIDTH },
159419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_184_CHECKER_TYPE,
159420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_184_WIDTH },
159421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_185_CHECKER_TYPE,
159422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_185_WIDTH },
159423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_186_CHECKER_TYPE,
159424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_186_WIDTH },
159425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_187_CHECKER_TYPE,
159426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_187_WIDTH },
159427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_188_CHECKER_TYPE,
159428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_188_WIDTH },
159429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_189_CHECKER_TYPE,
159430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_189_WIDTH },
159431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_190_CHECKER_TYPE,
159432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_190_WIDTH },
159433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_191_CHECKER_TYPE,
159434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_191_WIDTH },
159435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_192_CHECKER_TYPE,
159436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_192_WIDTH },
159437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_193_CHECKER_TYPE,
159438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_193_WIDTH },
159439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_194_CHECKER_TYPE,
159440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_194_WIDTH },
159441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_195_CHECKER_TYPE,
159442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_195_WIDTH },
159443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_196_CHECKER_TYPE,
159444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_196_WIDTH },
159445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_197_CHECKER_TYPE,
159446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_197_WIDTH },
159447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_198_CHECKER_TYPE,
159448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_198_WIDTH },
159449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_199_CHECKER_TYPE,
159450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_199_WIDTH },
159451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_200_CHECKER_TYPE,
159452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_200_WIDTH },
159453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_201_CHECKER_TYPE,
159454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_201_WIDTH },
159455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_202_CHECKER_TYPE,
159456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_202_WIDTH },
159457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_203_CHECKER_TYPE,
159458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_203_WIDTH },
159459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_204_CHECKER_TYPE,
159460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_204_WIDTH },
159461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_205_CHECKER_TYPE,
159462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_205_WIDTH },
159463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_206_CHECKER_TYPE,
159464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_206_WIDTH },
159465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_207_CHECKER_TYPE,
159466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_207_WIDTH },
159467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_208_CHECKER_TYPE,
159468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_208_WIDTH },
159469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_209_CHECKER_TYPE,
159470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_209_WIDTH },
159471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_210_CHECKER_TYPE,
159472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_210_WIDTH },
159473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_211_CHECKER_TYPE,
159474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_211_WIDTH },
159475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_212_CHECKER_TYPE,
159476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_212_WIDTH },
159477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_213_CHECKER_TYPE,
159478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_213_WIDTH },
159479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_214_CHECKER_TYPE,
159480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_214_WIDTH },
159481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_215_CHECKER_TYPE,
159482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_215_WIDTH },
159483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_216_CHECKER_TYPE,
159484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_216_WIDTH },
159485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_217_CHECKER_TYPE,
159486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_217_WIDTH },
159487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_218_CHECKER_TYPE,
159488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_218_WIDTH },
159489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_219_CHECKER_TYPE,
159490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_219_WIDTH },
159491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_220_CHECKER_TYPE,
159492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_220_WIDTH },
159493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_221_CHECKER_TYPE,
159494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_221_WIDTH },
159495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_222_CHECKER_TYPE,
159496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_222_WIDTH },
159497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_223_CHECKER_TYPE,
159498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_223_WIDTH },
159499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_224_CHECKER_TYPE,
159500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_224_WIDTH },
159501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_225_CHECKER_TYPE,
159502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_225_WIDTH },
159503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_226_CHECKER_TYPE,
159504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_226_WIDTH },
159505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_227_CHECKER_TYPE,
159506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_227_WIDTH },
159507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_228_CHECKER_TYPE,
159508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_228_WIDTH },
159509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_229_CHECKER_TYPE,
159510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_229_WIDTH },
159511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_230_CHECKER_TYPE,
159512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_230_WIDTH },
159513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_231_CHECKER_TYPE,
159514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_231_WIDTH },
159515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_232_CHECKER_TYPE,
159516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_232_WIDTH },
159517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_233_CHECKER_TYPE,
159518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_233_WIDTH },
159519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_234_CHECKER_TYPE,
159520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_234_WIDTH },
159521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_235_CHECKER_TYPE,
159522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_235_WIDTH },
159523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_236_CHECKER_TYPE,
159524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_236_WIDTH },
159525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_237_CHECKER_TYPE,
159526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_237_WIDTH },
159527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_238_CHECKER_TYPE,
159528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_238_WIDTH },
159529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_239_CHECKER_TYPE,
159530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_239_WIDTH },
159531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_240_CHECKER_TYPE,
159532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_240_WIDTH },
159533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_241_CHECKER_TYPE,
159534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_241_WIDTH },
159535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_242_CHECKER_TYPE,
159536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_242_WIDTH },
159537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_243_CHECKER_TYPE,
159538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_243_WIDTH },
159539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_244_CHECKER_TYPE,
159540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_244_WIDTH },
159541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_245_CHECKER_TYPE,
159542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_245_WIDTH },
159543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_246_CHECKER_TYPE,
159544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_246_WIDTH },
159545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_247_CHECKER_TYPE,
159546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_247_WIDTH },
159547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_248_CHECKER_TYPE,
159548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_248_WIDTH },
159549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_249_CHECKER_TYPE,
159550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_249_WIDTH },
159551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_250_CHECKER_TYPE,
159552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_250_WIDTH },
159553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_251_CHECKER_TYPE,
159554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_251_WIDTH },
159555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_252_CHECKER_TYPE,
159556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_252_WIDTH },
159557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_253_CHECKER_TYPE,
159558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_253_WIDTH },
159559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_254_CHECKER_TYPE,
159560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_254_WIDTH },
159561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_255_CHECKER_TYPE,
159562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_GROUP_255_WIDTH },
159563 };
159564 
159570 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS] =
159571 {
159572  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_0_CHECKER_TYPE,
159573  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_0_WIDTH },
159574  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_1_CHECKER_TYPE,
159575  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_1_WIDTH },
159576  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_2_CHECKER_TYPE,
159577  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_2_WIDTH },
159578  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_3_CHECKER_TYPE,
159579  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_3_WIDTH },
159580  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_4_CHECKER_TYPE,
159581  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_4_WIDTH },
159582  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_5_CHECKER_TYPE,
159583  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_5_WIDTH },
159584  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_6_CHECKER_TYPE,
159585  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_6_WIDTH },
159586  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_7_CHECKER_TYPE,
159587  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_7_WIDTH },
159588  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_8_CHECKER_TYPE,
159589  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_8_WIDTH },
159590  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_9_CHECKER_TYPE,
159591  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_9_WIDTH },
159592  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_10_CHECKER_TYPE,
159593  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_10_WIDTH },
159594  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_11_CHECKER_TYPE,
159595  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_11_WIDTH },
159596  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_12_CHECKER_TYPE,
159597  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_12_WIDTH },
159598  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_13_CHECKER_TYPE,
159599  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_13_WIDTH },
159600  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_14_CHECKER_TYPE,
159601  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_14_WIDTH },
159602  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_15_CHECKER_TYPE,
159603  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_15_WIDTH },
159604  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_16_CHECKER_TYPE,
159605  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_16_WIDTH },
159606  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_17_CHECKER_TYPE,
159607  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_17_WIDTH },
159608  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_18_CHECKER_TYPE,
159609  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_18_WIDTH },
159610  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_19_CHECKER_TYPE,
159611  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_19_WIDTH },
159612  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_20_CHECKER_TYPE,
159613  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_20_WIDTH },
159614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_21_CHECKER_TYPE,
159615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_21_WIDTH },
159616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_22_CHECKER_TYPE,
159617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_22_WIDTH },
159618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_23_CHECKER_TYPE,
159619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_23_WIDTH },
159620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_24_CHECKER_TYPE,
159621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_24_WIDTH },
159622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_25_CHECKER_TYPE,
159623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_25_WIDTH },
159624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_26_CHECKER_TYPE,
159625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_26_WIDTH },
159626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_27_CHECKER_TYPE,
159627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_27_WIDTH },
159628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_28_CHECKER_TYPE,
159629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_28_WIDTH },
159630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_29_CHECKER_TYPE,
159631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_29_WIDTH },
159632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_30_CHECKER_TYPE,
159633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_30_WIDTH },
159634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_31_CHECKER_TYPE,
159635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_31_WIDTH },
159636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_32_CHECKER_TYPE,
159637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_32_WIDTH },
159638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_33_CHECKER_TYPE,
159639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_33_WIDTH },
159640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_34_CHECKER_TYPE,
159641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_34_WIDTH },
159642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_35_CHECKER_TYPE,
159643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_35_WIDTH },
159644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_36_CHECKER_TYPE,
159645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_36_WIDTH },
159646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_37_CHECKER_TYPE,
159647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_37_WIDTH },
159648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_38_CHECKER_TYPE,
159649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_38_WIDTH },
159650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_39_CHECKER_TYPE,
159651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_39_WIDTH },
159652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_40_CHECKER_TYPE,
159653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_40_WIDTH },
159654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_41_CHECKER_TYPE,
159655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_41_WIDTH },
159656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_42_CHECKER_TYPE,
159657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_42_WIDTH },
159658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_43_CHECKER_TYPE,
159659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_43_WIDTH },
159660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_44_CHECKER_TYPE,
159661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_44_WIDTH },
159662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_45_CHECKER_TYPE,
159663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_45_WIDTH },
159664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_46_CHECKER_TYPE,
159665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_46_WIDTH },
159666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_47_CHECKER_TYPE,
159667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_47_WIDTH },
159668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_48_CHECKER_TYPE,
159669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_48_WIDTH },
159670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_49_CHECKER_TYPE,
159671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_49_WIDTH },
159672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_50_CHECKER_TYPE,
159673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_50_WIDTH },
159674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_51_CHECKER_TYPE,
159675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_51_WIDTH },
159676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_52_CHECKER_TYPE,
159677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_52_WIDTH },
159678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_53_CHECKER_TYPE,
159679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_53_WIDTH },
159680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_54_CHECKER_TYPE,
159681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_54_WIDTH },
159682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_55_CHECKER_TYPE,
159683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_55_WIDTH },
159684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_56_CHECKER_TYPE,
159685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_56_WIDTH },
159686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_57_CHECKER_TYPE,
159687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_57_WIDTH },
159688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_58_CHECKER_TYPE,
159689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_58_WIDTH },
159690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_59_CHECKER_TYPE,
159691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_59_WIDTH },
159692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_60_CHECKER_TYPE,
159693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_60_WIDTH },
159694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_61_CHECKER_TYPE,
159695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_61_WIDTH },
159696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_62_CHECKER_TYPE,
159697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_62_WIDTH },
159698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_63_CHECKER_TYPE,
159699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_63_WIDTH },
159700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_64_CHECKER_TYPE,
159701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_64_WIDTH },
159702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_65_CHECKER_TYPE,
159703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_65_WIDTH },
159704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_66_CHECKER_TYPE,
159705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_66_WIDTH },
159706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_67_CHECKER_TYPE,
159707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_67_WIDTH },
159708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_68_CHECKER_TYPE,
159709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_68_WIDTH },
159710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_69_CHECKER_TYPE,
159711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_69_WIDTH },
159712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_70_CHECKER_TYPE,
159713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_70_WIDTH },
159714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_71_CHECKER_TYPE,
159715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_71_WIDTH },
159716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_72_CHECKER_TYPE,
159717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_72_WIDTH },
159718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_73_CHECKER_TYPE,
159719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_73_WIDTH },
159720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_74_CHECKER_TYPE,
159721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_74_WIDTH },
159722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_75_CHECKER_TYPE,
159723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_75_WIDTH },
159724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_76_CHECKER_TYPE,
159725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_76_WIDTH },
159726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_77_CHECKER_TYPE,
159727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_77_WIDTH },
159728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_78_CHECKER_TYPE,
159729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_78_WIDTH },
159730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_79_CHECKER_TYPE,
159731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_79_WIDTH },
159732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_80_CHECKER_TYPE,
159733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_80_WIDTH },
159734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_81_CHECKER_TYPE,
159735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_81_WIDTH },
159736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_82_CHECKER_TYPE,
159737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_82_WIDTH },
159738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_83_CHECKER_TYPE,
159739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_83_WIDTH },
159740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_84_CHECKER_TYPE,
159741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_84_WIDTH },
159742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_85_CHECKER_TYPE,
159743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_85_WIDTH },
159744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_86_CHECKER_TYPE,
159745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_86_WIDTH },
159746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_87_CHECKER_TYPE,
159747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_87_WIDTH },
159748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_88_CHECKER_TYPE,
159749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_88_WIDTH },
159750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_89_CHECKER_TYPE,
159751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_89_WIDTH },
159752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_90_CHECKER_TYPE,
159753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_90_WIDTH },
159754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_91_CHECKER_TYPE,
159755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_91_WIDTH },
159756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_92_CHECKER_TYPE,
159757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_92_WIDTH },
159758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_93_CHECKER_TYPE,
159759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_93_WIDTH },
159760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_94_CHECKER_TYPE,
159761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_94_WIDTH },
159762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_95_CHECKER_TYPE,
159763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_95_WIDTH },
159764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_96_CHECKER_TYPE,
159765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_96_WIDTH },
159766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_97_CHECKER_TYPE,
159767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_97_WIDTH },
159768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_98_CHECKER_TYPE,
159769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_98_WIDTH },
159770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_99_CHECKER_TYPE,
159771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_99_WIDTH },
159772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_100_CHECKER_TYPE,
159773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_100_WIDTH },
159774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_101_CHECKER_TYPE,
159775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_101_WIDTH },
159776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_102_CHECKER_TYPE,
159777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_102_WIDTH },
159778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_103_CHECKER_TYPE,
159779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_103_WIDTH },
159780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_104_CHECKER_TYPE,
159781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_104_WIDTH },
159782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_105_CHECKER_TYPE,
159783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_105_WIDTH },
159784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_106_CHECKER_TYPE,
159785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_106_WIDTH },
159786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_107_CHECKER_TYPE,
159787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_107_WIDTH },
159788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_108_CHECKER_TYPE,
159789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_108_WIDTH },
159790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_109_CHECKER_TYPE,
159791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_109_WIDTH },
159792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_110_CHECKER_TYPE,
159793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_110_WIDTH },
159794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_111_CHECKER_TYPE,
159795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_111_WIDTH },
159796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_112_CHECKER_TYPE,
159797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_112_WIDTH },
159798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_113_CHECKER_TYPE,
159799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_113_WIDTH },
159800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_114_CHECKER_TYPE,
159801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_114_WIDTH },
159802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_115_CHECKER_TYPE,
159803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_115_WIDTH },
159804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_116_CHECKER_TYPE,
159805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_116_WIDTH },
159806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_117_CHECKER_TYPE,
159807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_117_WIDTH },
159808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_118_CHECKER_TYPE,
159809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_118_WIDTH },
159810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_119_CHECKER_TYPE,
159811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_119_WIDTH },
159812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_120_CHECKER_TYPE,
159813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_120_WIDTH },
159814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_121_CHECKER_TYPE,
159815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_121_WIDTH },
159816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_122_CHECKER_TYPE,
159817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_122_WIDTH },
159818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_123_CHECKER_TYPE,
159819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_123_WIDTH },
159820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_124_CHECKER_TYPE,
159821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_124_WIDTH },
159822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_125_CHECKER_TYPE,
159823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_125_WIDTH },
159824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_126_CHECKER_TYPE,
159825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_126_WIDTH },
159826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_127_CHECKER_TYPE,
159827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_127_WIDTH },
159828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_128_CHECKER_TYPE,
159829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_128_WIDTH },
159830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_129_CHECKER_TYPE,
159831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_129_WIDTH },
159832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_130_CHECKER_TYPE,
159833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_130_WIDTH },
159834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_131_CHECKER_TYPE,
159835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_131_WIDTH },
159836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_132_CHECKER_TYPE,
159837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_132_WIDTH },
159838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_133_CHECKER_TYPE,
159839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_133_WIDTH },
159840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_134_CHECKER_TYPE,
159841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_134_WIDTH },
159842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_135_CHECKER_TYPE,
159843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_135_WIDTH },
159844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_136_CHECKER_TYPE,
159845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_136_WIDTH },
159846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_137_CHECKER_TYPE,
159847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_137_WIDTH },
159848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_138_CHECKER_TYPE,
159849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_138_WIDTH },
159850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_139_CHECKER_TYPE,
159851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_139_WIDTH },
159852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_140_CHECKER_TYPE,
159853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_140_WIDTH },
159854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_141_CHECKER_TYPE,
159855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_141_WIDTH },
159856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_142_CHECKER_TYPE,
159857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_142_WIDTH },
159858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_143_CHECKER_TYPE,
159859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_143_WIDTH },
159860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_144_CHECKER_TYPE,
159861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_144_WIDTH },
159862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_145_CHECKER_TYPE,
159863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_145_WIDTH },
159864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_146_CHECKER_TYPE,
159865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_146_WIDTH },
159866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_147_CHECKER_TYPE,
159867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_147_WIDTH },
159868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_148_CHECKER_TYPE,
159869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_148_WIDTH },
159870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_149_CHECKER_TYPE,
159871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_149_WIDTH },
159872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_150_CHECKER_TYPE,
159873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_150_WIDTH },
159874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_151_CHECKER_TYPE,
159875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_151_WIDTH },
159876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_152_CHECKER_TYPE,
159877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_152_WIDTH },
159878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_153_CHECKER_TYPE,
159879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_153_WIDTH },
159880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_154_CHECKER_TYPE,
159881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_154_WIDTH },
159882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_155_CHECKER_TYPE,
159883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_155_WIDTH },
159884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_156_CHECKER_TYPE,
159885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_156_WIDTH },
159886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_157_CHECKER_TYPE,
159887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_157_WIDTH },
159888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_158_CHECKER_TYPE,
159889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_158_WIDTH },
159890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_159_CHECKER_TYPE,
159891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_159_WIDTH },
159892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_160_CHECKER_TYPE,
159893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_160_WIDTH },
159894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_161_CHECKER_TYPE,
159895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_161_WIDTH },
159896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_162_CHECKER_TYPE,
159897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_162_WIDTH },
159898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_163_CHECKER_TYPE,
159899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_163_WIDTH },
159900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_164_CHECKER_TYPE,
159901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_164_WIDTH },
159902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_165_CHECKER_TYPE,
159903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_165_WIDTH },
159904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_166_CHECKER_TYPE,
159905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_166_WIDTH },
159906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_167_CHECKER_TYPE,
159907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_167_WIDTH },
159908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_168_CHECKER_TYPE,
159909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_168_WIDTH },
159910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_169_CHECKER_TYPE,
159911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_169_WIDTH },
159912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_170_CHECKER_TYPE,
159913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_170_WIDTH },
159914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_171_CHECKER_TYPE,
159915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_171_WIDTH },
159916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_172_CHECKER_TYPE,
159917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_172_WIDTH },
159918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_173_CHECKER_TYPE,
159919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_173_WIDTH },
159920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_174_CHECKER_TYPE,
159921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_174_WIDTH },
159922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_175_CHECKER_TYPE,
159923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_175_WIDTH },
159924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_176_CHECKER_TYPE,
159925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_176_WIDTH },
159926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_177_CHECKER_TYPE,
159927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_177_WIDTH },
159928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_178_CHECKER_TYPE,
159929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_178_WIDTH },
159930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_179_CHECKER_TYPE,
159931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_179_WIDTH },
159932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_180_CHECKER_TYPE,
159933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_180_WIDTH },
159934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_181_CHECKER_TYPE,
159935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_181_WIDTH },
159936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_182_CHECKER_TYPE,
159937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_182_WIDTH },
159938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_183_CHECKER_TYPE,
159939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_183_WIDTH },
159940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_184_CHECKER_TYPE,
159941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_184_WIDTH },
159942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_185_CHECKER_TYPE,
159943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_185_WIDTH },
159944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_186_CHECKER_TYPE,
159945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_186_WIDTH },
159946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_187_CHECKER_TYPE,
159947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_187_WIDTH },
159948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_188_CHECKER_TYPE,
159949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_188_WIDTH },
159950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_189_CHECKER_TYPE,
159951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_189_WIDTH },
159952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_190_CHECKER_TYPE,
159953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_190_WIDTH },
159954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_191_CHECKER_TYPE,
159955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_191_WIDTH },
159956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_192_CHECKER_TYPE,
159957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_192_WIDTH },
159958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_193_CHECKER_TYPE,
159959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_193_WIDTH },
159960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_194_CHECKER_TYPE,
159961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_194_WIDTH },
159962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_195_CHECKER_TYPE,
159963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_195_WIDTH },
159964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_196_CHECKER_TYPE,
159965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_196_WIDTH },
159966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_197_CHECKER_TYPE,
159967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_197_WIDTH },
159968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_198_CHECKER_TYPE,
159969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_198_WIDTH },
159970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_199_CHECKER_TYPE,
159971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_199_WIDTH },
159972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_200_CHECKER_TYPE,
159973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_200_WIDTH },
159974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_201_CHECKER_TYPE,
159975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_201_WIDTH },
159976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_202_CHECKER_TYPE,
159977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_202_WIDTH },
159978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_203_CHECKER_TYPE,
159979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_203_WIDTH },
159980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_204_CHECKER_TYPE,
159981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_204_WIDTH },
159982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_205_CHECKER_TYPE,
159983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_205_WIDTH },
159984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_206_CHECKER_TYPE,
159985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_206_WIDTH },
159986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_207_CHECKER_TYPE,
159987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_207_WIDTH },
159988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_208_CHECKER_TYPE,
159989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_208_WIDTH },
159990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_209_CHECKER_TYPE,
159991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_209_WIDTH },
159992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_210_CHECKER_TYPE,
159993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_210_WIDTH },
159994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_211_CHECKER_TYPE,
159995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_211_WIDTH },
159996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_212_CHECKER_TYPE,
159997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_212_WIDTH },
159998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_213_CHECKER_TYPE,
159999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_213_WIDTH },
160000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_214_CHECKER_TYPE,
160001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_214_WIDTH },
160002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_215_CHECKER_TYPE,
160003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_215_WIDTH },
160004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_216_CHECKER_TYPE,
160005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_216_WIDTH },
160006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_217_CHECKER_TYPE,
160007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_217_WIDTH },
160008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_218_CHECKER_TYPE,
160009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_218_WIDTH },
160010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_219_CHECKER_TYPE,
160011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_219_WIDTH },
160012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_220_CHECKER_TYPE,
160013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_220_WIDTH },
160014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_221_CHECKER_TYPE,
160015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_221_WIDTH },
160016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_222_CHECKER_TYPE,
160017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_222_WIDTH },
160018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_223_CHECKER_TYPE,
160019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_223_WIDTH },
160020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_224_CHECKER_TYPE,
160021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_224_WIDTH },
160022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_225_CHECKER_TYPE,
160023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_225_WIDTH },
160024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_226_CHECKER_TYPE,
160025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_226_WIDTH },
160026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_227_CHECKER_TYPE,
160027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_227_WIDTH },
160028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_228_CHECKER_TYPE,
160029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_228_WIDTH },
160030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_229_CHECKER_TYPE,
160031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_229_WIDTH },
160032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_230_CHECKER_TYPE,
160033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_230_WIDTH },
160034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_231_CHECKER_TYPE,
160035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_231_WIDTH },
160036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_232_CHECKER_TYPE,
160037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_232_WIDTH },
160038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_233_CHECKER_TYPE,
160039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_233_WIDTH },
160040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_234_CHECKER_TYPE,
160041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_234_WIDTH },
160042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_235_CHECKER_TYPE,
160043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_235_WIDTH },
160044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_236_CHECKER_TYPE,
160045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_236_WIDTH },
160046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_237_CHECKER_TYPE,
160047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_237_WIDTH },
160048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_238_CHECKER_TYPE,
160049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_238_WIDTH },
160050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_239_CHECKER_TYPE,
160051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_239_WIDTH },
160052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_240_CHECKER_TYPE,
160053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_240_WIDTH },
160054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_241_CHECKER_TYPE,
160055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_241_WIDTH },
160056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_242_CHECKER_TYPE,
160057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_242_WIDTH },
160058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_243_CHECKER_TYPE,
160059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_243_WIDTH },
160060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_244_CHECKER_TYPE,
160061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_244_WIDTH },
160062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_245_CHECKER_TYPE,
160063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_245_WIDTH },
160064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_246_CHECKER_TYPE,
160065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_246_WIDTH },
160066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_247_CHECKER_TYPE,
160067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_247_WIDTH },
160068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_248_CHECKER_TYPE,
160069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_248_WIDTH },
160070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_249_CHECKER_TYPE,
160071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_249_WIDTH },
160072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_250_CHECKER_TYPE,
160073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_250_WIDTH },
160074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_251_CHECKER_TYPE,
160075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_251_WIDTH },
160076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_252_CHECKER_TYPE,
160077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_252_WIDTH },
160078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_253_CHECKER_TYPE,
160079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_253_WIDTH },
160080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_254_CHECKER_TYPE,
160081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_254_WIDTH },
160082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_255_CHECKER_TYPE,
160083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_GROUP_255_WIDTH },
160084 };
160085 
160091 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_MAX_NUM_CHECKERS] =
160092 {
160093  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_0_CHECKER_TYPE,
160094  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_0_WIDTH },
160095  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_1_CHECKER_TYPE,
160096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_1_WIDTH },
160097  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_2_CHECKER_TYPE,
160098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_2_WIDTH },
160099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_3_CHECKER_TYPE,
160100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_3_WIDTH },
160101  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_4_CHECKER_TYPE,
160102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_4_WIDTH },
160103  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_5_CHECKER_TYPE,
160104  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_5_WIDTH },
160105  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_6_CHECKER_TYPE,
160106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_6_WIDTH },
160107  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_7_CHECKER_TYPE,
160108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_7_WIDTH },
160109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_8_CHECKER_TYPE,
160110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_8_WIDTH },
160111  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_9_CHECKER_TYPE,
160112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_9_WIDTH },
160113  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_10_CHECKER_TYPE,
160114  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_10_WIDTH },
160115  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_11_CHECKER_TYPE,
160116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_11_WIDTH },
160117  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_12_CHECKER_TYPE,
160118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_12_WIDTH },
160119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_13_CHECKER_TYPE,
160120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_13_WIDTH },
160121  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_14_CHECKER_TYPE,
160122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_14_WIDTH },
160123  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_15_CHECKER_TYPE,
160124  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_15_WIDTH },
160125  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_16_CHECKER_TYPE,
160126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_16_WIDTH },
160127  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_17_CHECKER_TYPE,
160128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_17_WIDTH },
160129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_18_CHECKER_TYPE,
160130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_18_WIDTH },
160131  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_19_CHECKER_TYPE,
160132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_19_WIDTH },
160133  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_20_CHECKER_TYPE,
160134  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_20_WIDTH },
160135  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_21_CHECKER_TYPE,
160136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_21_WIDTH },
160137  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_22_CHECKER_TYPE,
160138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_22_WIDTH },
160139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_23_CHECKER_TYPE,
160140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_23_WIDTH },
160141  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_24_CHECKER_TYPE,
160142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_24_WIDTH },
160143  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_25_CHECKER_TYPE,
160144  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_25_WIDTH },
160145  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_26_CHECKER_TYPE,
160146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_26_WIDTH },
160147  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_27_CHECKER_TYPE,
160148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_27_WIDTH },
160149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_28_CHECKER_TYPE,
160150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_28_WIDTH },
160151  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_29_CHECKER_TYPE,
160152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_29_WIDTH },
160153  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_30_CHECKER_TYPE,
160154  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_30_WIDTH },
160155  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_31_CHECKER_TYPE,
160156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_31_WIDTH },
160157  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_32_CHECKER_TYPE,
160158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_32_WIDTH },
160159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_33_CHECKER_TYPE,
160160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_33_WIDTH },
160161  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_34_CHECKER_TYPE,
160162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_34_WIDTH },
160163  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_35_CHECKER_TYPE,
160164  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_35_WIDTH },
160165  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_36_CHECKER_TYPE,
160166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_36_WIDTH },
160167  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_37_CHECKER_TYPE,
160168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_37_WIDTH },
160169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_38_CHECKER_TYPE,
160170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_38_WIDTH },
160171  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_39_CHECKER_TYPE,
160172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_39_WIDTH },
160173  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_40_CHECKER_TYPE,
160174  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_40_WIDTH },
160175  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_41_CHECKER_TYPE,
160176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_41_WIDTH },
160177  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_42_CHECKER_TYPE,
160178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_42_WIDTH },
160179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_43_CHECKER_TYPE,
160180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_43_WIDTH },
160181  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_44_CHECKER_TYPE,
160182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_44_WIDTH },
160183  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_45_CHECKER_TYPE,
160184  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_45_WIDTH },
160185  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_46_CHECKER_TYPE,
160186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_46_WIDTH },
160187  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_47_CHECKER_TYPE,
160188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_47_WIDTH },
160189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_48_CHECKER_TYPE,
160190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_48_WIDTH },
160191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_49_CHECKER_TYPE,
160192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_49_WIDTH },
160193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_50_CHECKER_TYPE,
160194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_50_WIDTH },
160195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_51_CHECKER_TYPE,
160196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_51_WIDTH },
160197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_52_CHECKER_TYPE,
160198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_52_WIDTH },
160199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_53_CHECKER_TYPE,
160200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_53_WIDTH },
160201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_54_CHECKER_TYPE,
160202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_54_WIDTH },
160203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_55_CHECKER_TYPE,
160204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_55_WIDTH },
160205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_56_CHECKER_TYPE,
160206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_56_WIDTH },
160207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_57_CHECKER_TYPE,
160208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_57_WIDTH },
160209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_58_CHECKER_TYPE,
160210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_58_WIDTH },
160211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_59_CHECKER_TYPE,
160212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_59_WIDTH },
160213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_60_CHECKER_TYPE,
160214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_60_WIDTH },
160215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_61_CHECKER_TYPE,
160216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_61_WIDTH },
160217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_62_CHECKER_TYPE,
160218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_62_WIDTH },
160219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_63_CHECKER_TYPE,
160220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_63_WIDTH },
160221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_64_CHECKER_TYPE,
160222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_64_WIDTH },
160223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_65_CHECKER_TYPE,
160224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_65_WIDTH },
160225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_66_CHECKER_TYPE,
160226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_66_WIDTH },
160227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_67_CHECKER_TYPE,
160228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_67_WIDTH },
160229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_68_CHECKER_TYPE,
160230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_68_WIDTH },
160231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_69_CHECKER_TYPE,
160232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_69_WIDTH },
160233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_70_CHECKER_TYPE,
160234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_70_WIDTH },
160235  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_71_CHECKER_TYPE,
160236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_71_WIDTH },
160237  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_72_CHECKER_TYPE,
160238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_72_WIDTH },
160239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_73_CHECKER_TYPE,
160240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_73_WIDTH },
160241  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_74_CHECKER_TYPE,
160242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_74_WIDTH },
160243  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_75_CHECKER_TYPE,
160244  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_75_WIDTH },
160245  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_76_CHECKER_TYPE,
160246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_76_WIDTH },
160247  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_77_CHECKER_TYPE,
160248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_77_WIDTH },
160249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_78_CHECKER_TYPE,
160250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_78_WIDTH },
160251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_79_CHECKER_TYPE,
160252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_79_WIDTH },
160253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_80_CHECKER_TYPE,
160254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_80_WIDTH },
160255  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_81_CHECKER_TYPE,
160256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_81_WIDTH },
160257  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_82_CHECKER_TYPE,
160258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_82_WIDTH },
160259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_83_CHECKER_TYPE,
160260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_83_WIDTH },
160261  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_84_CHECKER_TYPE,
160262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_84_WIDTH },
160263  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_85_CHECKER_TYPE,
160264  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_85_WIDTH },
160265  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_86_CHECKER_TYPE,
160266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_86_WIDTH },
160267  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_87_CHECKER_TYPE,
160268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_87_WIDTH },
160269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_88_CHECKER_TYPE,
160270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_88_WIDTH },
160271  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_89_CHECKER_TYPE,
160272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_89_WIDTH },
160273  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_90_CHECKER_TYPE,
160274  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_90_WIDTH },
160275  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_91_CHECKER_TYPE,
160276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_91_WIDTH },
160277  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_92_CHECKER_TYPE,
160278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_92_WIDTH },
160279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_93_CHECKER_TYPE,
160280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_93_WIDTH },
160281  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_94_CHECKER_TYPE,
160282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_94_WIDTH },
160283  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_95_CHECKER_TYPE,
160284  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_95_WIDTH },
160285  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_96_CHECKER_TYPE,
160286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_96_WIDTH },
160287  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_97_CHECKER_TYPE,
160288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_97_WIDTH },
160289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_98_CHECKER_TYPE,
160290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_98_WIDTH },
160291  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_99_CHECKER_TYPE,
160292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_99_WIDTH },
160293  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_100_CHECKER_TYPE,
160294  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_100_WIDTH },
160295  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_101_CHECKER_TYPE,
160296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_101_WIDTH },
160297  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_102_CHECKER_TYPE,
160298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_102_WIDTH },
160299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_103_CHECKER_TYPE,
160300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_103_WIDTH },
160301  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_104_CHECKER_TYPE,
160302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_104_WIDTH },
160303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_105_CHECKER_TYPE,
160304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_105_WIDTH },
160305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_106_CHECKER_TYPE,
160306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_106_WIDTH },
160307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_107_CHECKER_TYPE,
160308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_107_WIDTH },
160309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_108_CHECKER_TYPE,
160310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_108_WIDTH },
160311  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_109_CHECKER_TYPE,
160312  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_109_WIDTH },
160313  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_110_CHECKER_TYPE,
160314  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_110_WIDTH },
160315  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_111_CHECKER_TYPE,
160316  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_111_WIDTH },
160317  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_112_CHECKER_TYPE,
160318  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_112_WIDTH },
160319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_113_CHECKER_TYPE,
160320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_113_WIDTH },
160321  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_114_CHECKER_TYPE,
160322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_114_WIDTH },
160323  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_115_CHECKER_TYPE,
160324  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_115_WIDTH },
160325  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_116_CHECKER_TYPE,
160326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_116_WIDTH },
160327  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_117_CHECKER_TYPE,
160328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_117_WIDTH },
160329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_118_CHECKER_TYPE,
160330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_118_WIDTH },
160331  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_119_CHECKER_TYPE,
160332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_119_WIDTH },
160333  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_120_CHECKER_TYPE,
160334  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_120_WIDTH },
160335  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_121_CHECKER_TYPE,
160336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_121_WIDTH },
160337  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_122_CHECKER_TYPE,
160338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_122_WIDTH },
160339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_123_CHECKER_TYPE,
160340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_123_WIDTH },
160341  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_124_CHECKER_TYPE,
160342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_124_WIDTH },
160343  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_125_CHECKER_TYPE,
160344  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_125_WIDTH },
160345  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_126_CHECKER_TYPE,
160346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_126_WIDTH },
160347  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_127_CHECKER_TYPE,
160348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_127_WIDTH },
160349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_128_CHECKER_TYPE,
160350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_128_WIDTH },
160351  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_129_CHECKER_TYPE,
160352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_129_WIDTH },
160353  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_130_CHECKER_TYPE,
160354  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_130_WIDTH },
160355  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_131_CHECKER_TYPE,
160356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_131_WIDTH },
160357  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_132_CHECKER_TYPE,
160358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_132_WIDTH },
160359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_133_CHECKER_TYPE,
160360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_133_WIDTH },
160361  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_134_CHECKER_TYPE,
160362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_134_WIDTH },
160363  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_135_CHECKER_TYPE,
160364  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_135_WIDTH },
160365  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_136_CHECKER_TYPE,
160366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_136_WIDTH },
160367  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_137_CHECKER_TYPE,
160368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_137_WIDTH },
160369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_138_CHECKER_TYPE,
160370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_138_WIDTH },
160371  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_139_CHECKER_TYPE,
160372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_139_WIDTH },
160373  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_140_CHECKER_TYPE,
160374  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_140_WIDTH },
160375  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_141_CHECKER_TYPE,
160376  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_141_WIDTH },
160377  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_142_CHECKER_TYPE,
160378  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_142_WIDTH },
160379  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_143_CHECKER_TYPE,
160380  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_143_WIDTH },
160381  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_144_CHECKER_TYPE,
160382  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_144_WIDTH },
160383  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_145_CHECKER_TYPE,
160384  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_145_WIDTH },
160385  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_146_CHECKER_TYPE,
160386  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_146_WIDTH },
160387  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_147_CHECKER_TYPE,
160388  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_147_WIDTH },
160389  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_148_CHECKER_TYPE,
160390  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_148_WIDTH },
160391  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_149_CHECKER_TYPE,
160392  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_149_WIDTH },
160393  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_150_CHECKER_TYPE,
160394  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_150_WIDTH },
160395  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_151_CHECKER_TYPE,
160396  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_151_WIDTH },
160397  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_152_CHECKER_TYPE,
160398  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_152_WIDTH },
160399  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_153_CHECKER_TYPE,
160400  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_153_WIDTH },
160401  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_154_CHECKER_TYPE,
160402  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_154_WIDTH },
160403  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_155_CHECKER_TYPE,
160404  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_155_WIDTH },
160405  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_156_CHECKER_TYPE,
160406  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_156_WIDTH },
160407  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_157_CHECKER_TYPE,
160408  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_157_WIDTH },
160409  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_158_CHECKER_TYPE,
160410  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_158_WIDTH },
160411  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_159_CHECKER_TYPE,
160412  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_159_WIDTH },
160413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_160_CHECKER_TYPE,
160414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_160_WIDTH },
160415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_161_CHECKER_TYPE,
160416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_161_WIDTH },
160417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_162_CHECKER_TYPE,
160418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_162_WIDTH },
160419  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_163_CHECKER_TYPE,
160420  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_163_WIDTH },
160421  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_164_CHECKER_TYPE,
160422  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_164_WIDTH },
160423  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_165_CHECKER_TYPE,
160424  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_165_WIDTH },
160425  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_166_CHECKER_TYPE,
160426  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_166_WIDTH },
160427  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_167_CHECKER_TYPE,
160428  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_167_WIDTH },
160429  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_168_CHECKER_TYPE,
160430  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_168_WIDTH },
160431  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_169_CHECKER_TYPE,
160432  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_169_WIDTH },
160433  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_170_CHECKER_TYPE,
160434  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_170_WIDTH },
160435  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_171_CHECKER_TYPE,
160436  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_171_WIDTH },
160437  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_172_CHECKER_TYPE,
160438  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_172_WIDTH },
160439  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_173_CHECKER_TYPE,
160440  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_173_WIDTH },
160441  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_174_CHECKER_TYPE,
160442  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_174_WIDTH },
160443  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_175_CHECKER_TYPE,
160444  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_175_WIDTH },
160445  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_176_CHECKER_TYPE,
160446  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_176_WIDTH },
160447  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_177_CHECKER_TYPE,
160448  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_177_WIDTH },
160449  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_178_CHECKER_TYPE,
160450  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_178_WIDTH },
160451  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_179_CHECKER_TYPE,
160452  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_179_WIDTH },
160453  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_180_CHECKER_TYPE,
160454  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_180_WIDTH },
160455  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_181_CHECKER_TYPE,
160456  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_181_WIDTH },
160457  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_182_CHECKER_TYPE,
160458  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_182_WIDTH },
160459  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_183_CHECKER_TYPE,
160460  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_183_WIDTH },
160461  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_184_CHECKER_TYPE,
160462  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_184_WIDTH },
160463  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_185_CHECKER_TYPE,
160464  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_185_WIDTH },
160465  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_186_CHECKER_TYPE,
160466  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_186_WIDTH },
160467  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_187_CHECKER_TYPE,
160468  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_187_WIDTH },
160469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_188_CHECKER_TYPE,
160470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_188_WIDTH },
160471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_189_CHECKER_TYPE,
160472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_189_WIDTH },
160473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_190_CHECKER_TYPE,
160474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_190_WIDTH },
160475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_191_CHECKER_TYPE,
160476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_191_WIDTH },
160477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_192_CHECKER_TYPE,
160478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_192_WIDTH },
160479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_193_CHECKER_TYPE,
160480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_193_WIDTH },
160481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_194_CHECKER_TYPE,
160482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_194_WIDTH },
160483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_195_CHECKER_TYPE,
160484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_195_WIDTH },
160485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_196_CHECKER_TYPE,
160486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_196_WIDTH },
160487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_197_CHECKER_TYPE,
160488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_197_WIDTH },
160489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_198_CHECKER_TYPE,
160490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_198_WIDTH },
160491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_199_CHECKER_TYPE,
160492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_199_WIDTH },
160493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_200_CHECKER_TYPE,
160494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_200_WIDTH },
160495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_201_CHECKER_TYPE,
160496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_201_WIDTH },
160497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_202_CHECKER_TYPE,
160498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_202_WIDTH },
160499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_203_CHECKER_TYPE,
160500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_203_WIDTH },
160501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_204_CHECKER_TYPE,
160502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_204_WIDTH },
160503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_205_CHECKER_TYPE,
160504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_205_WIDTH },
160505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_206_CHECKER_TYPE,
160506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_206_WIDTH },
160507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_207_CHECKER_TYPE,
160508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_207_WIDTH },
160509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_208_CHECKER_TYPE,
160510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_208_WIDTH },
160511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_209_CHECKER_TYPE,
160512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_209_WIDTH },
160513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_210_CHECKER_TYPE,
160514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_210_WIDTH },
160515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_211_CHECKER_TYPE,
160516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_211_WIDTH },
160517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_212_CHECKER_TYPE,
160518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_212_WIDTH },
160519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_213_CHECKER_TYPE,
160520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_213_WIDTH },
160521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_214_CHECKER_TYPE,
160522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_214_WIDTH },
160523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_215_CHECKER_TYPE,
160524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_215_WIDTH },
160525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_216_CHECKER_TYPE,
160526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_216_WIDTH },
160527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_217_CHECKER_TYPE,
160528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_217_WIDTH },
160529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_218_CHECKER_TYPE,
160530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_218_WIDTH },
160531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_219_CHECKER_TYPE,
160532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_219_WIDTH },
160533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_220_CHECKER_TYPE,
160534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_220_WIDTH },
160535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_221_CHECKER_TYPE,
160536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_221_WIDTH },
160537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_222_CHECKER_TYPE,
160538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_222_WIDTH },
160539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_223_CHECKER_TYPE,
160540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_223_WIDTH },
160541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_224_CHECKER_TYPE,
160542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_224_WIDTH },
160543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_225_CHECKER_TYPE,
160544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_225_WIDTH },
160545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_226_CHECKER_TYPE,
160546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_226_WIDTH },
160547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_227_CHECKER_TYPE,
160548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_227_WIDTH },
160549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_228_CHECKER_TYPE,
160550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_228_WIDTH },
160551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_229_CHECKER_TYPE,
160552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_229_WIDTH },
160553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_230_CHECKER_TYPE,
160554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_230_WIDTH },
160555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_231_CHECKER_TYPE,
160556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_231_WIDTH },
160557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_232_CHECKER_TYPE,
160558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_232_WIDTH },
160559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_233_CHECKER_TYPE,
160560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_233_WIDTH },
160561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_234_CHECKER_TYPE,
160562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_234_WIDTH },
160563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_235_CHECKER_TYPE,
160564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_235_WIDTH },
160565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_236_CHECKER_TYPE,
160566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_236_WIDTH },
160567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_237_CHECKER_TYPE,
160568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_237_WIDTH },
160569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_238_CHECKER_TYPE,
160570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_238_WIDTH },
160571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_239_CHECKER_TYPE,
160572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_239_WIDTH },
160573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_240_CHECKER_TYPE,
160574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_240_WIDTH },
160575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_241_CHECKER_TYPE,
160576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_241_WIDTH },
160577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_242_CHECKER_TYPE,
160578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_242_WIDTH },
160579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_243_CHECKER_TYPE,
160580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_243_WIDTH },
160581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_244_CHECKER_TYPE,
160582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_244_WIDTH },
160583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_245_CHECKER_TYPE,
160584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_245_WIDTH },
160585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_246_CHECKER_TYPE,
160586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_246_WIDTH },
160587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_247_CHECKER_TYPE,
160588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_247_WIDTH },
160589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_248_CHECKER_TYPE,
160590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_248_WIDTH },
160591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_249_CHECKER_TYPE,
160592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_249_WIDTH },
160593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_250_CHECKER_TYPE,
160594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_250_WIDTH },
160595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_251_CHECKER_TYPE,
160596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_251_WIDTH },
160597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_252_CHECKER_TYPE,
160598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_252_WIDTH },
160599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_253_CHECKER_TYPE,
160600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_253_WIDTH },
160601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_254_CHECKER_TYPE,
160602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_254_WIDTH },
160603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_255_CHECKER_TYPE,
160604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_GROUP_255_WIDTH },
160605 };
160606 
160612 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_MAX_NUM_CHECKERS] =
160613 {
160614  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_0_CHECKER_TYPE,
160615  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_0_WIDTH },
160616  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_1_CHECKER_TYPE,
160617  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_1_WIDTH },
160618  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_2_CHECKER_TYPE,
160619  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_2_WIDTH },
160620  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_3_CHECKER_TYPE,
160621  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_3_WIDTH },
160622  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_4_CHECKER_TYPE,
160623  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_4_WIDTH },
160624  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_5_CHECKER_TYPE,
160625  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_5_WIDTH },
160626  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_6_CHECKER_TYPE,
160627  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_6_WIDTH },
160628  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_7_CHECKER_TYPE,
160629  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_7_WIDTH },
160630  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_8_CHECKER_TYPE,
160631  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_8_WIDTH },
160632  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_9_CHECKER_TYPE,
160633  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_9_WIDTH },
160634  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_10_CHECKER_TYPE,
160635  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_10_WIDTH },
160636  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_11_CHECKER_TYPE,
160637  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_11_WIDTH },
160638  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_12_CHECKER_TYPE,
160639  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_12_WIDTH },
160640  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_13_CHECKER_TYPE,
160641  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_13_WIDTH },
160642  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_14_CHECKER_TYPE,
160643  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_14_WIDTH },
160644  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_15_CHECKER_TYPE,
160645  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_15_WIDTH },
160646  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_16_CHECKER_TYPE,
160647  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_16_WIDTH },
160648  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_17_CHECKER_TYPE,
160649  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_17_WIDTH },
160650  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_18_CHECKER_TYPE,
160651  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_18_WIDTH },
160652  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_19_CHECKER_TYPE,
160653  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_19_WIDTH },
160654  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_20_CHECKER_TYPE,
160655  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_20_WIDTH },
160656  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_21_CHECKER_TYPE,
160657  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_21_WIDTH },
160658  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_22_CHECKER_TYPE,
160659  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_22_WIDTH },
160660  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_23_CHECKER_TYPE,
160661  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_23_WIDTH },
160662  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_24_CHECKER_TYPE,
160663  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_24_WIDTH },
160664  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_25_CHECKER_TYPE,
160665  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_25_WIDTH },
160666  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_26_CHECKER_TYPE,
160667  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_26_WIDTH },
160668  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_27_CHECKER_TYPE,
160669  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_27_WIDTH },
160670  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_28_CHECKER_TYPE,
160671  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_28_WIDTH },
160672  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_29_CHECKER_TYPE,
160673  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_29_WIDTH },
160674  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_30_CHECKER_TYPE,
160675  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_30_WIDTH },
160676  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_31_CHECKER_TYPE,
160677  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_31_WIDTH },
160678  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_32_CHECKER_TYPE,
160679  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_32_WIDTH },
160680  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_33_CHECKER_TYPE,
160681  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_33_WIDTH },
160682  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_34_CHECKER_TYPE,
160683  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_34_WIDTH },
160684  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_35_CHECKER_TYPE,
160685  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_35_WIDTH },
160686  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_36_CHECKER_TYPE,
160687  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_36_WIDTH },
160688  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_37_CHECKER_TYPE,
160689  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_37_WIDTH },
160690  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_38_CHECKER_TYPE,
160691  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_38_WIDTH },
160692  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_39_CHECKER_TYPE,
160693  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_39_WIDTH },
160694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_40_CHECKER_TYPE,
160695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_40_WIDTH },
160696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_41_CHECKER_TYPE,
160697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_41_WIDTH },
160698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_42_CHECKER_TYPE,
160699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_42_WIDTH },
160700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_43_CHECKER_TYPE,
160701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_43_WIDTH },
160702  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_44_CHECKER_TYPE,
160703  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_44_WIDTH },
160704  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_45_CHECKER_TYPE,
160705  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_45_WIDTH },
160706  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_46_CHECKER_TYPE,
160707  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_46_WIDTH },
160708  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_47_CHECKER_TYPE,
160709  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_47_WIDTH },
160710  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_48_CHECKER_TYPE,
160711  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_48_WIDTH },
160712  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_49_CHECKER_TYPE,
160713  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_49_WIDTH },
160714  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_50_CHECKER_TYPE,
160715  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_50_WIDTH },
160716  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_51_CHECKER_TYPE,
160717  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_51_WIDTH },
160718  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_52_CHECKER_TYPE,
160719  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_52_WIDTH },
160720  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_53_CHECKER_TYPE,
160721  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_53_WIDTH },
160722  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_54_CHECKER_TYPE,
160723  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_54_WIDTH },
160724  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_55_CHECKER_TYPE,
160725  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_55_WIDTH },
160726  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_56_CHECKER_TYPE,
160727  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_56_WIDTH },
160728  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_57_CHECKER_TYPE,
160729  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_57_WIDTH },
160730  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_58_CHECKER_TYPE,
160731  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_58_WIDTH },
160732  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_59_CHECKER_TYPE,
160733  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_59_WIDTH },
160734  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_60_CHECKER_TYPE,
160735  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_60_WIDTH },
160736  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_61_CHECKER_TYPE,
160737  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_61_WIDTH },
160738  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_62_CHECKER_TYPE,
160739  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_62_WIDTH },
160740  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_63_CHECKER_TYPE,
160741  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_63_WIDTH },
160742  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_64_CHECKER_TYPE,
160743  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_64_WIDTH },
160744  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_65_CHECKER_TYPE,
160745  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_65_WIDTH },
160746  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_66_CHECKER_TYPE,
160747  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_66_WIDTH },
160748  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_67_CHECKER_TYPE,
160749  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_67_WIDTH },
160750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_68_CHECKER_TYPE,
160751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_68_WIDTH },
160752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_69_CHECKER_TYPE,
160753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_69_WIDTH },
160754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_70_CHECKER_TYPE,
160755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_70_WIDTH },
160756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_71_CHECKER_TYPE,
160757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_71_WIDTH },
160758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_72_CHECKER_TYPE,
160759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_72_WIDTH },
160760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_73_CHECKER_TYPE,
160761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_73_WIDTH },
160762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_74_CHECKER_TYPE,
160763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_74_WIDTH },
160764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_75_CHECKER_TYPE,
160765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_75_WIDTH },
160766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_76_CHECKER_TYPE,
160767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_76_WIDTH },
160768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_77_CHECKER_TYPE,
160769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_77_WIDTH },
160770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_78_CHECKER_TYPE,
160771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_78_WIDTH },
160772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_79_CHECKER_TYPE,
160773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_79_WIDTH },
160774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_80_CHECKER_TYPE,
160775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_80_WIDTH },
160776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_81_CHECKER_TYPE,
160777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_81_WIDTH },
160778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_82_CHECKER_TYPE,
160779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_82_WIDTH },
160780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_83_CHECKER_TYPE,
160781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_83_WIDTH },
160782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_84_CHECKER_TYPE,
160783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_84_WIDTH },
160784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_85_CHECKER_TYPE,
160785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_85_WIDTH },
160786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_86_CHECKER_TYPE,
160787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_86_WIDTH },
160788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_87_CHECKER_TYPE,
160789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_87_WIDTH },
160790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_88_CHECKER_TYPE,
160791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_88_WIDTH },
160792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_89_CHECKER_TYPE,
160793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_89_WIDTH },
160794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_90_CHECKER_TYPE,
160795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_90_WIDTH },
160796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_91_CHECKER_TYPE,
160797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_91_WIDTH },
160798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_92_CHECKER_TYPE,
160799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_92_WIDTH },
160800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_93_CHECKER_TYPE,
160801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_93_WIDTH },
160802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_94_CHECKER_TYPE,
160803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_94_WIDTH },
160804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_95_CHECKER_TYPE,
160805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_95_WIDTH },
160806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_96_CHECKER_TYPE,
160807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_96_WIDTH },
160808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_97_CHECKER_TYPE,
160809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_97_WIDTH },
160810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_98_CHECKER_TYPE,
160811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_98_WIDTH },
160812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_99_CHECKER_TYPE,
160813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_99_WIDTH },
160814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_100_CHECKER_TYPE,
160815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_100_WIDTH },
160816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_101_CHECKER_TYPE,
160817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_101_WIDTH },
160818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_102_CHECKER_TYPE,
160819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_102_WIDTH },
160820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_103_CHECKER_TYPE,
160821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_103_WIDTH },
160822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_104_CHECKER_TYPE,
160823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_104_WIDTH },
160824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_105_CHECKER_TYPE,
160825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_105_WIDTH },
160826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_106_CHECKER_TYPE,
160827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_106_WIDTH },
160828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_107_CHECKER_TYPE,
160829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_107_WIDTH },
160830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_108_CHECKER_TYPE,
160831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_108_WIDTH },
160832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_109_CHECKER_TYPE,
160833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_109_WIDTH },
160834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_110_CHECKER_TYPE,
160835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_110_WIDTH },
160836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_111_CHECKER_TYPE,
160837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_111_WIDTH },
160838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_112_CHECKER_TYPE,
160839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_112_WIDTH },
160840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_113_CHECKER_TYPE,
160841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_113_WIDTH },
160842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_114_CHECKER_TYPE,
160843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_114_WIDTH },
160844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_115_CHECKER_TYPE,
160845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_115_WIDTH },
160846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_116_CHECKER_TYPE,
160847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_116_WIDTH },
160848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_117_CHECKER_TYPE,
160849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_117_WIDTH },
160850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_118_CHECKER_TYPE,
160851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_118_WIDTH },
160852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_119_CHECKER_TYPE,
160853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_119_WIDTH },
160854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_120_CHECKER_TYPE,
160855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_120_WIDTH },
160856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_121_CHECKER_TYPE,
160857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_121_WIDTH },
160858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_122_CHECKER_TYPE,
160859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_122_WIDTH },
160860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_123_CHECKER_TYPE,
160861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_123_WIDTH },
160862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_124_CHECKER_TYPE,
160863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_124_WIDTH },
160864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_125_CHECKER_TYPE,
160865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_125_WIDTH },
160866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_126_CHECKER_TYPE,
160867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_126_WIDTH },
160868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_127_CHECKER_TYPE,
160869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_127_WIDTH },
160870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_128_CHECKER_TYPE,
160871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_128_WIDTH },
160872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_129_CHECKER_TYPE,
160873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_129_WIDTH },
160874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_130_CHECKER_TYPE,
160875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_130_WIDTH },
160876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_131_CHECKER_TYPE,
160877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_131_WIDTH },
160878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_132_CHECKER_TYPE,
160879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_132_WIDTH },
160880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_133_CHECKER_TYPE,
160881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_133_WIDTH },
160882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_134_CHECKER_TYPE,
160883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_134_WIDTH },
160884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_135_CHECKER_TYPE,
160885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_135_WIDTH },
160886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_136_CHECKER_TYPE,
160887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_136_WIDTH },
160888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_137_CHECKER_TYPE,
160889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_137_WIDTH },
160890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_138_CHECKER_TYPE,
160891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_138_WIDTH },
160892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_139_CHECKER_TYPE,
160893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_139_WIDTH },
160894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_140_CHECKER_TYPE,
160895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_140_WIDTH },
160896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_141_CHECKER_TYPE,
160897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_141_WIDTH },
160898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_142_CHECKER_TYPE,
160899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_142_WIDTH },
160900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_143_CHECKER_TYPE,
160901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_143_WIDTH },
160902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_144_CHECKER_TYPE,
160903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_144_WIDTH },
160904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_145_CHECKER_TYPE,
160905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_145_WIDTH },
160906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_146_CHECKER_TYPE,
160907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_146_WIDTH },
160908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_147_CHECKER_TYPE,
160909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_147_WIDTH },
160910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_148_CHECKER_TYPE,
160911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_148_WIDTH },
160912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_149_CHECKER_TYPE,
160913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_149_WIDTH },
160914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_150_CHECKER_TYPE,
160915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_150_WIDTH },
160916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_151_CHECKER_TYPE,
160917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_151_WIDTH },
160918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_152_CHECKER_TYPE,
160919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_152_WIDTH },
160920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_153_CHECKER_TYPE,
160921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_GROUP_153_WIDTH },
160922 };
160923 
160929 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
160930 {
160931  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
160932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
160933  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
160934  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
160935  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
160936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
160937 };
160938 
160944 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
160945 {
160946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
160947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
160948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
160949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
160950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
160951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
160952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
160953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
160954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
160955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
160956 };
160957 
160963 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS] =
160964 {
160965  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_0_CHECKER_TYPE,
160966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_0_WIDTH },
160967  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_1_CHECKER_TYPE,
160968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_1_WIDTH },
160969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_2_CHECKER_TYPE,
160970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_2_WIDTH },
160971  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_3_CHECKER_TYPE,
160972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_3_WIDTH },
160973  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_4_CHECKER_TYPE,
160974  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_4_WIDTH },
160975  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_5_CHECKER_TYPE,
160976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_5_WIDTH },
160977  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_6_CHECKER_TYPE,
160978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_6_WIDTH },
160979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_7_CHECKER_TYPE,
160980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_7_WIDTH },
160981  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_8_CHECKER_TYPE,
160982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_8_WIDTH },
160983  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_9_CHECKER_TYPE,
160984  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_9_WIDTH },
160985  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_10_CHECKER_TYPE,
160986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_10_WIDTH },
160987  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_11_CHECKER_TYPE,
160988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_11_WIDTH },
160989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_12_CHECKER_TYPE,
160990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_12_WIDTH },
160991  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_13_CHECKER_TYPE,
160992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_13_WIDTH },
160993  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_14_CHECKER_TYPE,
160994  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_14_WIDTH },
160995  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_15_CHECKER_TYPE,
160996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_15_WIDTH },
160997  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_16_CHECKER_TYPE,
160998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_16_WIDTH },
160999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_17_CHECKER_TYPE,
161000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_17_WIDTH },
161001  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_18_CHECKER_TYPE,
161002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_18_WIDTH },
161003  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_19_CHECKER_TYPE,
161004  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_19_WIDTH },
161005  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_20_CHECKER_TYPE,
161006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_20_WIDTH },
161007  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_21_CHECKER_TYPE,
161008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_21_WIDTH },
161009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_22_CHECKER_TYPE,
161010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_22_WIDTH },
161011  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_23_CHECKER_TYPE,
161012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_23_WIDTH },
161013  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_24_CHECKER_TYPE,
161014  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_24_WIDTH },
161015  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_25_CHECKER_TYPE,
161016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_25_WIDTH },
161017  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_26_CHECKER_TYPE,
161018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_26_WIDTH },
161019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_27_CHECKER_TYPE,
161020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_27_WIDTH },
161021  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_28_CHECKER_TYPE,
161022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_28_WIDTH },
161023  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_29_CHECKER_TYPE,
161024  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_29_WIDTH },
161025  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_30_CHECKER_TYPE,
161026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_GROUP_30_WIDTH },
161027 };
161028 
161034 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_MAX_NUM_CHECKERS] =
161035 {
161036  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_0_CHECKER_TYPE,
161037  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_0_WIDTH },
161038  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_1_CHECKER_TYPE,
161039  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_1_WIDTH },
161040  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_2_CHECKER_TYPE,
161041  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_2_WIDTH },
161042  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_3_CHECKER_TYPE,
161043  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_3_WIDTH },
161044  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_4_CHECKER_TYPE,
161045  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_4_WIDTH },
161046  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_5_CHECKER_TYPE,
161047  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_5_WIDTH },
161048  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_6_CHECKER_TYPE,
161049  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_6_WIDTH },
161050  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_7_CHECKER_TYPE,
161051  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_7_WIDTH },
161052  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_8_CHECKER_TYPE,
161053  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_8_WIDTH },
161054  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_9_CHECKER_TYPE,
161055  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_9_WIDTH },
161056  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_10_CHECKER_TYPE,
161057  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_10_WIDTH },
161058  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_11_CHECKER_TYPE,
161059  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_11_WIDTH },
161060  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_12_CHECKER_TYPE,
161061  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_12_WIDTH },
161062  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_13_CHECKER_TYPE,
161063  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_13_WIDTH },
161064  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_14_CHECKER_TYPE,
161065  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_14_WIDTH },
161066  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_15_CHECKER_TYPE,
161067  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_15_WIDTH },
161068  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_16_CHECKER_TYPE,
161069  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_16_WIDTH },
161070  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_17_CHECKER_TYPE,
161071  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_17_WIDTH },
161072  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_18_CHECKER_TYPE,
161073  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_18_WIDTH },
161074  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_19_CHECKER_TYPE,
161075  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_19_WIDTH },
161076  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_20_CHECKER_TYPE,
161077  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_20_WIDTH },
161078  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_21_CHECKER_TYPE,
161079  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_21_WIDTH },
161080  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_22_CHECKER_TYPE,
161081  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_22_WIDTH },
161082  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_23_CHECKER_TYPE,
161083  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_23_WIDTH },
161084  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_24_CHECKER_TYPE,
161085  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_24_WIDTH },
161086  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_25_CHECKER_TYPE,
161087  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_25_WIDTH },
161088  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_26_CHECKER_TYPE,
161089  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_26_WIDTH },
161090  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_27_CHECKER_TYPE,
161091  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_27_WIDTH },
161092  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_28_CHECKER_TYPE,
161093  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_28_WIDTH },
161094  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_29_CHECKER_TYPE,
161095  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_29_WIDTH },
161096  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_30_CHECKER_TYPE,
161097  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_30_WIDTH },
161098  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_31_CHECKER_TYPE,
161099  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_31_WIDTH },
161100  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_32_CHECKER_TYPE,
161101  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_32_WIDTH },
161102  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_33_CHECKER_TYPE,
161103  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_33_WIDTH },
161104  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_34_CHECKER_TYPE,
161105  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_34_WIDTH },
161106  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_35_CHECKER_TYPE,
161107  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_35_WIDTH },
161108  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_36_CHECKER_TYPE,
161109  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_36_WIDTH },
161110  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_37_CHECKER_TYPE,
161111  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_37_WIDTH },
161112  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_38_CHECKER_TYPE,
161113  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_38_WIDTH },
161114  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_39_CHECKER_TYPE,
161115  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_39_WIDTH },
161116  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_40_CHECKER_TYPE,
161117  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_40_WIDTH },
161118  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_41_CHECKER_TYPE,
161119  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_41_WIDTH },
161120  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_42_CHECKER_TYPE,
161121  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_42_WIDTH },
161122  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_43_CHECKER_TYPE,
161123  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_43_WIDTH },
161124  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_44_CHECKER_TYPE,
161125  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_44_WIDTH },
161126  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_45_CHECKER_TYPE,
161127  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_45_WIDTH },
161128  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_46_CHECKER_TYPE,
161129  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_46_WIDTH },
161130  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_47_CHECKER_TYPE,
161131  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_47_WIDTH },
161132  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_48_CHECKER_TYPE,
161133  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_48_WIDTH },
161134  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_49_CHECKER_TYPE,
161135  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_49_WIDTH },
161136  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_50_CHECKER_TYPE,
161137  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_50_WIDTH },
161138  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_51_CHECKER_TYPE,
161139  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_51_WIDTH },
161140  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_52_CHECKER_TYPE,
161141  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_52_WIDTH },
161142  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_53_CHECKER_TYPE,
161143  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_53_WIDTH },
161144  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_54_CHECKER_TYPE,
161145  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_54_WIDTH },
161146  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_55_CHECKER_TYPE,
161147  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_55_WIDTH },
161148  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_56_CHECKER_TYPE,
161149  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_56_WIDTH },
161150  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_57_CHECKER_TYPE,
161151  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_57_WIDTH },
161152  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_58_CHECKER_TYPE,
161153  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_58_WIDTH },
161154  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_59_CHECKER_TYPE,
161155  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_59_WIDTH },
161156  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_60_CHECKER_TYPE,
161157  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_60_WIDTH },
161158  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_61_CHECKER_TYPE,
161159  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_61_WIDTH },
161160  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_62_CHECKER_TYPE,
161161  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_62_WIDTH },
161162  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_63_CHECKER_TYPE,
161163  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_63_WIDTH },
161164  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_64_CHECKER_TYPE,
161165  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_64_WIDTH },
161166  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_65_CHECKER_TYPE,
161167  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_65_WIDTH },
161168  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_66_CHECKER_TYPE,
161169  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_66_WIDTH },
161170  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_67_CHECKER_TYPE,
161171  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_67_WIDTH },
161172  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_68_CHECKER_TYPE,
161173  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_68_WIDTH },
161174  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_69_CHECKER_TYPE,
161175  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_69_WIDTH },
161176  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_70_CHECKER_TYPE,
161177  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_70_WIDTH },
161178  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_71_CHECKER_TYPE,
161179  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_71_WIDTH },
161180  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_72_CHECKER_TYPE,
161181  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_GROUP_72_WIDTH },
161182 };
161183 
161189 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
161190 {
161191  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
161192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
161193  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
161194  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
161195  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
161196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
161197  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
161198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
161199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
161200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
161201  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
161202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
161203  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
161204  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
161205  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
161206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
161207  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
161208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
161209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
161210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
161211  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
161212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
161213  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
161214  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
161215  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
161216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
161217  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
161218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
161219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
161220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
161221  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
161222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
161223  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
161224  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
161225  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
161226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
161227  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
161228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
161229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
161230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
161231  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
161232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
161233  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
161234  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
161235 };
161236 
161242 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
161243 {
161244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
161245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
161246  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
161247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
161248  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
161249  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
161250  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
161251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
161252  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
161253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
161254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
161255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
161256  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
161257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
161258  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
161259  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
161260  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
161261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
161262  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
161263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
161264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
161265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
161266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
161267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
161268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
161269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
161270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
161271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
161272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
161273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
161274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
161275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
161276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
161277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
161278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
161279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
161280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
161281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
161282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
161283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
161284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
161285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
161286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
161287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
161288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
161289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
161290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
161291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
161292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
161293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
161294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
161295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
161296  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
161297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
161298  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
161299  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
161300  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
161301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
161302  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
161303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
161304  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
161305  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
161306  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
161307  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
161308  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
161309  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
161310  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
161311  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
161312  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
161313  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
161314  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
161315  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
161316  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
161317  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
161318  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
161319  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
161320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
161321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
161322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
161323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
161324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
161325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
161326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
161327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
161328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
161329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
161330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
161331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
161332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
161333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
161334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
161335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
161336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
161337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
161338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
161339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
161340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
161341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
161342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
161343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
161344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
161345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
161346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
161347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
161348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
161349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
161350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
161351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
161352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
161353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
161354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
161355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
161356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
161357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
161358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
161359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
161360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
161361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
161362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
161363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
161364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
161365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
161366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
161367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
161368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
161369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
161370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
161371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
161372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
161373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
161374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
161375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
161376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
161377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
161378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
161379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
161380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
161381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
161382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
161383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
161384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
161385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
161386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
161387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
161388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
161389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
161390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
161391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
161392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
161393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
161394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
161395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
161396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
161397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
161398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
161399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
161400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
161401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
161402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
161403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
161404  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
161405  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
161406  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
161407  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
161408  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
161409  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
161410  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
161411  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
161412  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
161413  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
161414  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
161415  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
161416  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
161417  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
161418  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
161419  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
161420  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
161421  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
161422  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
161423  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
161424  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
161425  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
161426  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
161427  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
161428  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
161429  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
161430  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
161431  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
161432  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
161433  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
161434  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
161435  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
161436  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
161437  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
161438  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
161439  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
161440  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
161441  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
161442  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
161443  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
161444  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
161445  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
161446  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
161447  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
161448  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
161449  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
161450  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
161451  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
161452  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
161453  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
161454  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
161455  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
161456  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
161457  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
161458  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
161459  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
161460 };
161461 
161467 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
161468 {
161469  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
161470  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
161471  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
161472  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
161473  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
161474  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
161475  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
161476  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
161477  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
161478  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
161479  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
161480  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
161481  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
161482  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
161483  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
161484  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
161485  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
161486  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
161487  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
161488  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
161489  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
161490  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
161491  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
161492  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
161493  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
161494  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
161495  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
161496  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
161497  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
161498  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
161499  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
161500  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
161501  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
161502  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
161503  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
161504  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
161505  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
161506  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
161507  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
161508  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
161509  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
161510  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
161511  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
161512  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
161513  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
161514  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
161515  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
161516  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
161517  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
161518  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
161519  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
161520  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
161521  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
161522  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
161523  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
161524  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
161525  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
161526  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
161527  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
161528  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
161529  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
161530  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
161531  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
161532  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
161533  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
161534  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
161535  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
161536  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
161537  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
161538  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
161539  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
161540  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
161541  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
161542  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
161543  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
161544  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
161545  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
161546  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
161547  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
161548  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
161549  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
161550  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
161551  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
161552  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
161553  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
161554  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
161555  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
161556  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
161557  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
161558  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
161559  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
161560  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
161561  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
161562  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
161563  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
161564  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
161565  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
161566  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
161567  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
161568  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
161569  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
161570  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
161571  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
161572  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
161573  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
161574  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
161575  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
161576  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
161577  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
161578  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
161579  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
161580  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
161581  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
161582  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
161583  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
161584  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
161585  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
161586  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
161587  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
161588  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
161589  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
161590  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
161591  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
161592  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
161593  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
161594  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
161595  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
161596  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
161597  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
161598  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
161599  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
161600  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
161601  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
161602  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
161603  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
161604  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
161605  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
161606  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
161607  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
161608  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
161609  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
161610  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
161611  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
161612  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
161613  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
161614  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
161615  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
161616  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
161617  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
161618  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
161619  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
161620  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
161621  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
161622  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
161623  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
161624  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
161625  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
161626  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
161627  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
161628  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
161629  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
161630  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
161631  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
161632  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
161633  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
161634  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
161635  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
161636  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
161637  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
161638  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
161639  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
161640  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
161641  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
161642  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
161643  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
161644  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
161645  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
161646  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
161647  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
161648  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
161649  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
161650  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
161651  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
161652  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
161653  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
161654  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
161655  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
161656  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
161657  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
161658  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
161659  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
161660  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
161661  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
161662  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
161663  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
161664  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
161665  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
161666  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
161667  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
161668  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
161669  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
161670  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
161671  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
161672  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
161673  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
161674  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
161675  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
161676  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
161677  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
161678  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
161679  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
161680  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
161681  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
161682  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
161683  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
161684  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
161685 };
161686 
161692 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
161693 {
161694  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
161695  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
161696  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
161697  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
161698  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
161699  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
161700  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
161701  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
161702 };
161703 
161709 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
161710 {
161711  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
161712  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
161713  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
161714  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
161715  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
161716  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
161717  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
161718  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
161719  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
161720  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
161721  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
161722  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
161723  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
161724  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
161725  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
161726  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
161727  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
161728  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
161729  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
161730  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
161731  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
161732  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
161733  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
161734  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
161735  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
161736  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
161737  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
161738  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
161739  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
161740  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
161741 };
161742 
161748 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
161749 {
161750  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
161751  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
161752  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
161753  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
161754  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
161755  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
161756  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
161757  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
161758  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
161759  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
161760  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
161761  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
161762  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
161763  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
161764  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
161765  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
161766  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
161767  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
161768  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
161769  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
161770  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
161771  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
161772  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
161773  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
161774  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
161775  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
161776  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
161777  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
161778  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
161779  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
161780  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
161781  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
161782  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
161783  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
161784  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
161785  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
161786  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
161787  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
161788  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
161789  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
161790  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
161791  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
161792  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
161793  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
161794  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
161795  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
161796  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
161797  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
161798  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
161799  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
161800  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
161801  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
161802  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
161803  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
161804  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
161805  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
161806  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
161807  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
161808  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
161809  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
161810  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
161811  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
161812  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
161813  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
161814  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
161815  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
161816  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
161817  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
161818  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
161819  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
161820  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
161821  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
161822  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
161823  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
161824  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
161825  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
161826  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
161827  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
161828  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
161829  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
161830  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
161831  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
161832  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
161833  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
161834  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
161835  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
161836  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
161837  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
161838  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
161839  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
161840  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
161841  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
161842  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
161843  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
161844  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
161845  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
161846  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
161847  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
161848  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
161849  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
161850  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
161851  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
161852  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
161853  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
161854  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
161855  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
161856  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
161857  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
161858  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
161859  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
161860  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
161861  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
161862  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
161863  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
161864  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
161865  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
161866  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
161867  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
161868  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
161869  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
161870  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
161871  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
161872  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
161873  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
161874  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
161875  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
161876  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
161877  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
161878  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
161879  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
161880  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
161881  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
161882  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
161883  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
161884  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
161885  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
161886  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
161887  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
161888  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
161889  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
161890  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
161891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
161892  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
161893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
161894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
161895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
161896  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
161897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
161898  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
161899  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
161900  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
161901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
161902  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
161903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
161904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
161905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
161906  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
161907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
161908  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
161909  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
161910  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
161911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
161912  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
161913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
161914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
161915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
161916  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
161917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
161918  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
161919  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
161920  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
161921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
161922  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
161923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
161924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
161925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
161926  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
161927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
161928  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
161929  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
161930  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
161931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
161932  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
161933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
161934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
161935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
161936  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
161937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
161938  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
161939  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
161940  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
161941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
161942  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
161943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
161944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
161945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
161946  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
161947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
161948  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
161949  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
161950  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
161951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
161952  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
161953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
161954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
161955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
161956  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
161957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
161958  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
161959  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
161960  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
161961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
161962  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
161963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
161964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
161965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
161966  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
161967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
161968  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
161969  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
161970  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
161971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
161972  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
161973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
161974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
161975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
161976  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
161977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
161978  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
161979  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
161980  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
161981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
161982  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
161983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
161984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
161985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
161986  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
161987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
161988  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
161989  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
161990  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
161991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
161992  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
161993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
161994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
161995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
161996  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
161997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
161998  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
161999  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
162000  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
162001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
162002  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
162003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
162004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
162005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
162006  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
162007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
162008  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
162009  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
162010  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
162011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
162012  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
162013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
162014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
162015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
162016  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_133_CHECKER_TYPE,
162017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
162018  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_134_CHECKER_TYPE,
162019  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
162020  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_135_CHECKER_TYPE,
162021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
162022  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_136_CHECKER_TYPE,
162023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
162024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_137_CHECKER_TYPE,
162025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
162026  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_138_CHECKER_TYPE,
162027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
162028  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_139_CHECKER_TYPE,
162029  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
162030  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_140_CHECKER_TYPE,
162031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
162032  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_141_CHECKER_TYPE,
162033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
162034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_142_CHECKER_TYPE,
162035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
162036  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_143_CHECKER_TYPE,
162037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
162038  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_144_CHECKER_TYPE,
162039  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
162040  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_145_CHECKER_TYPE,
162041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
162042  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_146_CHECKER_TYPE,
162043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
162044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_147_CHECKER_TYPE,
162045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
162046  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_148_CHECKER_TYPE,
162047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
162048  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_149_CHECKER_TYPE,
162049  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
162050  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_150_CHECKER_TYPE,
162051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
162052  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_151_CHECKER_TYPE,
162053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
162054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_152_CHECKER_TYPE,
162055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
162056  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_153_CHECKER_TYPE,
162057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
162058  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_154_CHECKER_TYPE,
162059  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
162060  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_155_CHECKER_TYPE,
162061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
162062  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_156_CHECKER_TYPE,
162063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
162064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_157_CHECKER_TYPE,
162065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
162066  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_158_CHECKER_TYPE,
162067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
162068  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_159_CHECKER_TYPE,
162069  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
162070  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_160_CHECKER_TYPE,
162071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
162072  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_161_CHECKER_TYPE,
162073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
162074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_162_CHECKER_TYPE,
162075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
162076  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_163_CHECKER_TYPE,
162077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
162078  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_164_CHECKER_TYPE,
162079  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
162080  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_165_CHECKER_TYPE,
162081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
162082  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_166_CHECKER_TYPE,
162083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_166_WIDTH },
162084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_167_CHECKER_TYPE,
162085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_167_WIDTH },
162086  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_168_CHECKER_TYPE,
162087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_168_WIDTH },
162088  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_169_CHECKER_TYPE,
162089  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_169_WIDTH },
162090  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_170_CHECKER_TYPE,
162091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_170_WIDTH },
162092  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_171_CHECKER_TYPE,
162093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_171_WIDTH },
162094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_172_CHECKER_TYPE,
162095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_172_WIDTH },
162096  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_173_CHECKER_TYPE,
162097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_173_WIDTH },
162098  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_174_CHECKER_TYPE,
162099  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_174_WIDTH },
162100  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_175_CHECKER_TYPE,
162101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_175_WIDTH },
162102  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_176_CHECKER_TYPE,
162103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_176_WIDTH },
162104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_177_CHECKER_TYPE,
162105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_177_WIDTH },
162106  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_178_CHECKER_TYPE,
162107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_178_WIDTH },
162108  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_179_CHECKER_TYPE,
162109  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_179_WIDTH },
162110  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_180_CHECKER_TYPE,
162111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_180_WIDTH },
162112  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_181_CHECKER_TYPE,
162113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_181_WIDTH },
162114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_182_CHECKER_TYPE,
162115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_182_WIDTH },
162116  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_183_CHECKER_TYPE,
162117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_183_WIDTH },
162118  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_184_CHECKER_TYPE,
162119  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_184_WIDTH },
162120  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_185_CHECKER_TYPE,
162121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_185_WIDTH },
162122  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_186_CHECKER_TYPE,
162123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_186_WIDTH },
162124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_187_CHECKER_TYPE,
162125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_187_WIDTH },
162126  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_188_CHECKER_TYPE,
162127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_188_WIDTH },
162128  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_189_CHECKER_TYPE,
162129  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_189_WIDTH },
162130  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_190_CHECKER_TYPE,
162131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_190_WIDTH },
162132  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_191_CHECKER_TYPE,
162133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_191_WIDTH },
162134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_192_CHECKER_TYPE,
162135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_192_WIDTH },
162136  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_193_CHECKER_TYPE,
162137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_193_WIDTH },
162138  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_194_CHECKER_TYPE,
162139  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_194_WIDTH },
162140  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_195_CHECKER_TYPE,
162141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_195_WIDTH },
162142  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_196_CHECKER_TYPE,
162143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_196_WIDTH },
162144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_197_CHECKER_TYPE,
162145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_197_WIDTH },
162146  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_198_CHECKER_TYPE,
162147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_198_WIDTH },
162148  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_199_CHECKER_TYPE,
162149  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_199_WIDTH },
162150  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_200_CHECKER_TYPE,
162151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_200_WIDTH },
162152  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_201_CHECKER_TYPE,
162153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_201_WIDTH },
162154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_202_CHECKER_TYPE,
162155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_202_WIDTH },
162156  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_203_CHECKER_TYPE,
162157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_203_WIDTH },
162158  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_204_CHECKER_TYPE,
162159  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_204_WIDTH },
162160  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_205_CHECKER_TYPE,
162161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_205_WIDTH },
162162  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_206_CHECKER_TYPE,
162163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_206_WIDTH },
162164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_207_CHECKER_TYPE,
162165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_207_WIDTH },
162166  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_208_CHECKER_TYPE,
162167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_208_WIDTH },
162168  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_209_CHECKER_TYPE,
162169  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_209_WIDTH },
162170  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_210_CHECKER_TYPE,
162171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_210_WIDTH },
162172  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_211_CHECKER_TYPE,
162173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_211_WIDTH },
162174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_212_CHECKER_TYPE,
162175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_212_WIDTH },
162176  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_213_CHECKER_TYPE,
162177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_213_WIDTH },
162178  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_214_CHECKER_TYPE,
162179  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_214_WIDTH },
162180  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_215_CHECKER_TYPE,
162181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_215_WIDTH },
162182  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_216_CHECKER_TYPE,
162183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_216_WIDTH },
162184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_217_CHECKER_TYPE,
162185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_217_WIDTH },
162186  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_218_CHECKER_TYPE,
162187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_218_WIDTH },
162188  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_219_CHECKER_TYPE,
162189  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_219_WIDTH },
162190  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_220_CHECKER_TYPE,
162191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_220_WIDTH },
162192  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_221_CHECKER_TYPE,
162193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_221_WIDTH },
162194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_222_CHECKER_TYPE,
162195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_222_WIDTH },
162196  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_223_CHECKER_TYPE,
162197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_223_WIDTH },
162198  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_224_CHECKER_TYPE,
162199  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_224_WIDTH },
162200  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_225_CHECKER_TYPE,
162201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_225_WIDTH },
162202  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_226_CHECKER_TYPE,
162203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_226_WIDTH },
162204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_227_CHECKER_TYPE,
162205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_227_WIDTH },
162206  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_228_CHECKER_TYPE,
162207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_228_WIDTH },
162208  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_229_CHECKER_TYPE,
162209  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_229_WIDTH },
162210  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_230_CHECKER_TYPE,
162211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_230_WIDTH },
162212  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_231_CHECKER_TYPE,
162213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_231_WIDTH },
162214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_232_CHECKER_TYPE,
162215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_232_WIDTH },
162216  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_233_CHECKER_TYPE,
162217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_233_WIDTH },
162218  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_234_CHECKER_TYPE,
162219  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_234_WIDTH },
162220  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_235_CHECKER_TYPE,
162221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_235_WIDTH },
162222  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_236_CHECKER_TYPE,
162223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_236_WIDTH },
162224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_237_CHECKER_TYPE,
162225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_237_WIDTH },
162226  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_238_CHECKER_TYPE,
162227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_238_WIDTH },
162228  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_239_CHECKER_TYPE,
162229  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_239_WIDTH },
162230  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_240_CHECKER_TYPE,
162231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_240_WIDTH },
162232  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_241_CHECKER_TYPE,
162233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_241_WIDTH },
162234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_242_CHECKER_TYPE,
162235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_242_WIDTH },
162236  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_243_CHECKER_TYPE,
162237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_243_WIDTH },
162238  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_244_CHECKER_TYPE,
162239  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_244_WIDTH },
162240 };
162241 
162247 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
162248 {
162249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
162250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
162251  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
162252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
162253  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
162254  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
162255 };
162256 
162262 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
162263 {
162264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
162265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
162266  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
162267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
162268  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
162269  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
162270  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
162271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
162272  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
162273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
162274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
162275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
162276  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
162277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
162278  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
162279  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
162280  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
162281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
162282  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
162283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
162284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
162285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
162286  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
162287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
162288  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
162289  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
162290  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
162291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
162292  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
162293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
162294 };
162295 
162301 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
162302 {
162303  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
162304  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
162305  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
162306  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
162307  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
162308  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
162309  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
162310  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
162311 };
162312 
162318 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
162319 {
162320  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
162321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
162322  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
162323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
162324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
162325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
162326  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
162327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
162328  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
162329  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
162330  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
162331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
162332  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
162333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
162334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
162335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
162336  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
162337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
162338  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
162339  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
162340  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
162341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
162342  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
162343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
162344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
162345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
162346  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
162347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
162348  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
162349  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
162350  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
162351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
162352  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
162353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
162354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
162355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
162356  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
162357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
162358  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
162359  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
162360  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
162361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
162362  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
162363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
162364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
162365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
162366  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
162367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
162368  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
162369  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
162370  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
162371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
162372  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
162373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
162374  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
162375  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
162376  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
162377  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
162378  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
162379  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
162380  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
162381  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
162382  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
162383  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
162384  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
162385  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
162386  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
162387  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
162388  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
162389  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
162390  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
162391  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
162392  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
162393  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
162394  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
162395  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
162396  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
162397  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
162398  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
162399  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
162400  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
162401  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
162402  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
162403  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
162404 };
162405 
162411 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
162412 {
162413  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
162414  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_0_WIDTH },
162415  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
162416  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_1_WIDTH },
162417  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
162418  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_GROUP_2_WIDTH },
162419 };
162420 
162426 static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_MAX_NUM_CHECKERS] =
162427 {
162428  { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_0_CHECKER_TYPE,
162429  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_0_WIDTH },
162430  { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_1_CHECKER_TYPE,
162431  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_1_WIDTH },
162432  { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_2_CHECKER_TYPE,
162433  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_2_WIDTH },
162434  { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_3_CHECKER_TYPE,
162435  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_3_WIDTH },
162436  { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_4_CHECKER_TYPE,
162437  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_4_WIDTH },
162438  { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_5_CHECKER_TYPE,
162439  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_GROUP_5_WIDTH },
162440 };
162441 
162446 static const SDL_MemConfig_t SDL_VPAC0_VISS_ECC_AGGR_MemEntries[SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
162447 {
162448  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_ID, 0u,
162449  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_SIZE, 4u,
162450  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
162451  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_ID, 0u,
162452  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_SIZE, 4u,
162453  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
162454  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_ID, 0u,
162455  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_SIZE, 4u,
162456  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
162457  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_ID, 0u,
162458  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_SIZE, 4u,
162459  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
162460  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_ID, 0u,
162461  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_SIZE, 4u,
162462  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
162463  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_ID, 0u,
162464  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_SIZE, 4u,
162465  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
162466  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
162467  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
162468  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
162469  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_ID, 0u,
162470  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_SIZE, 4u,
162471  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
162472  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
162473  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
162474  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
162475  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_ID, 0u,
162476  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_SIZE, 4u,
162477  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
162478  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_ID, 0u,
162479  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_SIZE, 4u,
162480  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_ROW_WIDTH, ((bool)false) },
162481  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_ID, 0u,
162482  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_SIZE, 4u,
162483  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_ROW_WIDTH, ((bool)false) },
162484  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_ID, 0u,
162485  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_SIZE, 4u,
162486  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_ROW_WIDTH, ((bool)false) },
162487  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_ID, 0u,
162488  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_SIZE, 4u,
162489  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_ROW_WIDTH, ((bool)false) },
162490  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_ID, 0u,
162491  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_SIZE, 4u,
162492  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_ROW_WIDTH, ((bool)false) },
162493  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_ID, 0u,
162494  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_SIZE, 4u,
162495  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_ROW_WIDTH, ((bool)false) },
162496  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_ID, 0u,
162497  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_SIZE, 4u,
162498  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_ROW_WIDTH, ((bool)false) },
162499  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_ID, 0u,
162500  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_SIZE, 4u,
162501  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_ROW_WIDTH, ((bool)false) },
162502  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_ID, 0u,
162503  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_SIZE, 4u,
162504  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_ROW_WIDTH, ((bool)false) },
162505  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_ID, 0u,
162506  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_SIZE, 4u,
162507  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_ROW_WIDTH, ((bool)false) },
162508  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_ID, 0u,
162509  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_SIZE, 4u,
162510  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
162511  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_ID, 0u,
162512  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_SIZE, 4u,
162513  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
162514  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_ID, 0u,
162515  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_SIZE, 4u,
162516  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
162517  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_ID, 0u,
162518  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_SIZE, 4u,
162519  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
162520  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_ID, 0u,
162521  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_SIZE, 4u,
162522  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
162523  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_ID, 0u,
162524  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_SIZE, 4u,
162525  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
162526  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_ID, 0u,
162527  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_SIZE, 4u,
162528  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
162529  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_ID, 0u,
162530  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_SIZE, 4u,
162531  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
162532  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_ID, 0u,
162533  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_SIZE, 4u,
162534  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
162535  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_ID, 0u,
162536  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_SIZE, 4u,
162537  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
162538  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_ID, 0u,
162539  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_SIZE, 4u,
162540  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
162541  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_ID, 0u,
162542  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_SIZE, 4u,
162543  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
162544  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_ID, 0u,
162545  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_SIZE, 4u,
162546  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_ROW_WIDTH, ((bool)false) },
162547  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_ID, 0u,
162548  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_SIZE, 4u,
162549  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_ROW_WIDTH, ((bool)false) },
162550  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_ID, 0u,
162551  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_SIZE, 4u,
162552  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_ROW_WIDTH, ((bool)false) },
162553  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_ID, 0u,
162554  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_SIZE, 4u,
162555  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_ROW_WIDTH, ((bool)false) },
162556  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_ID, 0u,
162557  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_SIZE, 4u,
162558  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_ROW_WIDTH, ((bool)false) },
162559  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_ID, 0u,
162560  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_SIZE, 4u,
162561  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_ROW_WIDTH, ((bool)false) },
162562 };
162563 
162568 static const SDL_MemConfig_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
162569 {
162570  { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x27A8000u,
162571  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
162572  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
162573 };
162574 
162580 static const SDL_GrpChkConfig_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
162581 {
162582  { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
162583  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
162584 };
162585 
162590 static const SDL_MemConfig_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
162591 {
162592  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_ID, 0u,
162593  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_SIZE, 4u,
162594  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_ROW_WIDTH, ((bool)false) },
162595  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_ID, 0u,
162596  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_SIZE, 4u,
162597  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_ROW_WIDTH, ((bool)false) },
162598  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_ID, 0u,
162599  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
162600  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)false) },
162601  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
162602  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
162603  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
162604  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
162605  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
162606  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
162607  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
162608  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 4u,
162609  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)false) },
162610  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
162611  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
162612  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)false) },
162613  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
162614  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
162615  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)false) },
162616  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
162617  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 4u,
162618  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)false) },
162619  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
162620  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 4u,
162621  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)false) },
162622  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
162623  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 4u,
162624  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)false) },
162625  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
162626  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 4u,
162627  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)false) },
162628 };
162629 
162634 static const SDL_MemConfig_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
162635 {
162636  { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x2788000u,
162637  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
162638  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
162639 };
162640 
162646 static const SDL_GrpChkConfig_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS] =
162647 {
162648  { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
162649  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
162650 };
162651 
162656 static const SDL_MemConfig_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
162657 {
162658  { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID, 0u,
162659  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_SIZE, 4u,
162660  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ROW_WIDTH, ((bool)false) },
162661 };
162662 
162667 static const SDL_MemConfig_t SDL_MCU_FSS0_0_MemEntries[SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES] =
162668 {
162669  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_RAM_ID, 0u,
162670  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_RAM_SIZE, 4u,
162671  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_ROW_WIDTH, ((bool)false) },
162672  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_RAM_ID, 0u,
162673  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_RAM_SIZE, 4u,
162674  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_ROW_WIDTH, ((bool)false) },
162675  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_RAM_ID, 0u,
162676  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_RAM_SIZE, 4u,
162677  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_ROW_WIDTH, ((bool)false) },
162678  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_RAM_ID, 0u,
162679  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_RAM_SIZE, 4u,
162680  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_ROW_WIDTH, ((bool)false) },
162681  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_RAM_ID, 0u,
162682  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_RAM_SIZE, 4u,
162683  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_ROW_WIDTH, ((bool)false) },
162684  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_RAM_ID, 0u,
162685  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_RAM_SIZE, 4u,
162686  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_ROW_WIDTH, ((bool)false) },
162687  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RX_FIFO_RAM_ID, 0u,
162688  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RX_FIFO_RAM_SIZE, 4u,
162689  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RX_FIFO_ROW_WIDTH, ((bool)false) },
162690  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_RAM_ID, 0u,
162691  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_RAM_SIZE, 4u,
162692  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_ROW_WIDTH, ((bool)false) },
162693  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_RAM_ID, 0u,
162694  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_RAM_SIZE, 4u,
162695  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_ROW_WIDTH, ((bool)false) },
162696  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_RAM_ID, 0u,
162697  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_RAM_SIZE, 4u,
162698  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_ROW_WIDTH, ((bool)false) },
162699  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_RAM_ID, 0u,
162700  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_RAM_SIZE, 4u,
162701  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_ROW_WIDTH, ((bool)false) },
162702  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_RAM_ID, 0u,
162703  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_RAM_SIZE, 4u,
162704  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_ROW_WIDTH, ((bool)false) },
162705  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_RAM_ID, 0u,
162706  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_RAM_SIZE, 4u,
162707  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_ROW_WIDTH, ((bool)false) },
162708  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AR_FIFO_RAM_ID, 0u,
162709  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AR_FIFO_RAM_SIZE, 4u,
162710  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AR_FIFO_ROW_WIDTH, ((bool)false) },
162711  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_RAM_ID, 0u,
162712  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_RAM_SIZE, 4u,
162713  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_ROW_WIDTH, ((bool)false) },
162714 };
162715 
162720 static const SDL_MemConfig_t SDL_MCU_FSS0_1_MemEntries[SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES] =
162721 {
162722  { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
162723  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
162724  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
162725 };
162726 
162731 static const SDL_MemConfig_t SDL_MCU_FSS0_2_MemEntries[SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES] =
162732 {
162733  { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
162734  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
162735  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
162736 };
162737 
162742 static const SDL_MemConfig_t SDL_MCU_CPSW0_0_MemEntries[SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES] =
162743 {
162744  { SDL_MCU_CPSW0_P1_RX_FIFO_RAM_ID, 0u,
162745  SDL_MCU_CPSW0_P1_RX_FIFO_RAM_SIZE, 4u,
162746  SDL_MCU_CPSW0_P1_RX_FIFO_ROW_WIDTH, ((bool)false) },
162747  { SDL_MCU_CPSW0_P1_TX_FIFO_RAM_ID, 0u,
162748  SDL_MCU_CPSW0_P1_TX_FIFO_RAM_SIZE, 4u,
162749  SDL_MCU_CPSW0_P1_TX_FIFO_ROW_WIDTH, ((bool)false) },
162750  { SDL_MCU_CPSW0_EST_RAM_RAM_ID, 0u,
162751  SDL_MCU_CPSW0_EST_RAM_RAM_SIZE, 4u,
162752  SDL_MCU_CPSW0_EST_RAM_ROW_WIDTH, ((bool)false) },
162753 };
162754 
162759 static const SDL_MemConfig_t SDL_WKUP_DMSC0_0_MemEntries[SDL_WKUP_DMSC0_0_RAM_IDS_TOTAL_ENTRIES] =
162760 {
162761  { SDL_WKUP_DMSC0_IRAM_RAMECC_RAM_ID, 0u,
162762  SDL_WKUP_DMSC0_IRAM_RAMECC_RAM_SIZE, 4u,
162763  SDL_WKUP_DMSC0_IRAM_RAMECC_ROW_WIDTH, ((bool)false) },
162764  { SDL_WKUP_DMSC0_IDRAM0_RAMECC_RAM_ID, 0u,
162765  SDL_WKUP_DMSC0_IDRAM0_RAMECC_RAM_SIZE, 4u,
162766  SDL_WKUP_DMSC0_IDRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
162767  { SDL_WKUP_DMSC0_IDRAM1_RAMECC_RAM_ID, 0u,
162768  SDL_WKUP_DMSC0_IDRAM1_RAMECC_RAM_SIZE, 4u,
162769  SDL_WKUP_DMSC0_IDRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
162770  { SDL_WKUP_DMSC0_IM_RAMECC_RAM_ID, 0u,
162771  SDL_WKUP_DMSC0_IM_RAMECC_RAM_SIZE, 4u,
162772  SDL_WKUP_DMSC0_IM_RAMECC_ROW_WIDTH, ((bool)false) },
162773  { SDL_WKUP_DMSC0_SR_RAMECC_RAM_ID, 0u,
162774  SDL_WKUP_DMSC0_SR_RAMECC_RAM_SIZE, 4u,
162775  SDL_WKUP_DMSC0_SR_RAMECC_ROW_WIDTH, ((bool)false) },
162776 };
162777 
162783 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IRAM_BUSECC_groupEntries[SDL_WKUP_DMSC0_IRAM_BUSECC_MAX_NUM_CHECKERS] =
162784 {
162785  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_0_CHECKER_TYPE,
162786  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_0_WIDTH },
162787  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_1_CHECKER_TYPE,
162788  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_1_WIDTH },
162789  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_2_CHECKER_TYPE,
162790  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_2_WIDTH },
162791  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_3_CHECKER_TYPE,
162792  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_3_WIDTH },
162793  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_4_CHECKER_TYPE,
162794  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_4_WIDTH },
162795  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_5_CHECKER_TYPE,
162796  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_5_WIDTH },
162797  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_6_CHECKER_TYPE,
162798  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_6_WIDTH },
162799  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_7_CHECKER_TYPE,
162800  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_7_WIDTH },
162801  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_8_CHECKER_TYPE,
162802  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_8_WIDTH },
162803  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_9_CHECKER_TYPE,
162804  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_9_WIDTH },
162805  { SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_10_CHECKER_TYPE,
162806  SDL_WKUP_DMSC0_IRAM_BUSECC_GROUP_10_WIDTH },
162807 };
162808 
162814 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IDRAM0_BUSECC_groupEntries[SDL_WKUP_DMSC0_IDRAM0_BUSECC_MAX_NUM_CHECKERS] =
162815 {
162816  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
162817  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_0_WIDTH },
162818  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
162819  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_1_WIDTH },
162820  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
162821  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_2_WIDTH },
162822  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
162823  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_3_WIDTH },
162824  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
162825  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_4_WIDTH },
162826  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
162827  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_5_WIDTH },
162828  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
162829  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_6_WIDTH },
162830  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
162831  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_7_WIDTH },
162832  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
162833  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_8_WIDTH },
162834  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
162835  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_9_WIDTH },
162836  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
162837  SDL_WKUP_DMSC0_IDRAM0_BUSECC_GROUP_10_WIDTH },
162838 };
162839 
162845 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IDRAM1_BUSECC_groupEntries[SDL_WKUP_DMSC0_IDRAM1_BUSECC_MAX_NUM_CHECKERS] =
162846 {
162847  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
162848  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_0_WIDTH },
162849  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
162850  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_1_WIDTH },
162851  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
162852  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_2_WIDTH },
162853  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
162854  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_3_WIDTH },
162855  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
162856  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_4_WIDTH },
162857  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
162858  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_5_WIDTH },
162859  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
162860  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_6_WIDTH },
162861  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
162862  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_7_WIDTH },
162863  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
162864  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_8_WIDTH },
162865  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
162866  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_9_WIDTH },
162867  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
162868  SDL_WKUP_DMSC0_IDRAM1_BUSECC_GROUP_10_WIDTH },
162869 };
162870 
162876 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_groupEntries[SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_MAX_NUM_CHECKERS] =
162877 {
162878  { SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
162879  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_0_WIDTH },
162880  { SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
162881  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_1_WIDTH },
162882  { SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
162883  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_2_WIDTH },
162884  { SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
162885  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_3_WIDTH },
162886  { SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
162887  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_4_WIDTH },
162888  { SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
162889  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_GROUP_5_WIDTH },
162890 };
162891 
162897 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
162898 {
162899  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
162900  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
162901  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
162902  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
162903  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
162904  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
162905  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
162906  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
162907  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
162908  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
162909  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
162910  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
162911  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
162912  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
162913  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
162914  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
162915  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
162916  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
162917  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
162918  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
162919  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
162920  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
162921  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
162922  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
162923  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
162924  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
162925  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
162926  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
162927  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
162928  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
162929  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
162930  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
162931  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
162932  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
162933  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
162934  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
162935  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
162936  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
162937  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
162938  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
162939  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
162940  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
162941  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
162942  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
162943  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
162944  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
162945  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
162946  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
162947  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
162948  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
162949  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
162950  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
162951  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
162952  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
162953  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
162954  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
162955  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
162956  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
162957  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
162958  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
162959  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
162960  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
162961  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
162962  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
162963  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
162964  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
162965  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
162966  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
162967  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
162968  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
162969  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
162970  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
162971  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
162972  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
162973  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
162974  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
162975  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
162976  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
162977  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
162978  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
162979  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
162980  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
162981  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
162982  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
162983  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
162984  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
162985  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
162986  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
162987  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
162988  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
162989  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
162990  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
162991  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
162992  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
162993  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
162994  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
162995  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
162996  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
162997  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
162998  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
162999  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
163000  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
163001  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
163002  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
163003  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
163004  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
163005  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
163006  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
163007  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
163008  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
163009  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
163010  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
163011  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
163012  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
163013  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
163014  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
163015  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
163016  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
163017  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
163018  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
163019  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
163020  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
163021  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
163022  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
163023  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
163024  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
163025  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
163026  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
163027  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
163028  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
163029  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
163030  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
163031  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
163032  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
163033  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
163034  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
163035  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
163036  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
163037  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
163038  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
163039  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
163040  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
163041  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
163042  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
163043  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
163044  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
163045  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
163046  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
163047  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
163048  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
163049  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
163050  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
163051  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
163052  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
163053  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
163054  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
163055  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
163056  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
163057  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
163058  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
163059  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
163060  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
163061  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
163062  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
163063  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
163064  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
163065  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
163066  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
163067  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
163068  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
163069  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
163070  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
163071  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
163072  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
163073  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
163074  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
163075  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
163076  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
163077  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
163078  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
163079  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
163080  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
163081  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
163082  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
163083  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
163084  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
163085  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
163086  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
163087  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
163088  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
163089  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
163090  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
163091  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
163092  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
163093  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
163094  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
163095  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
163096  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
163097  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
163098  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
163099  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
163100  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
163101  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
163102  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
163103  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
163104  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
163105  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
163106  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
163107  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
163108  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
163109  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
163110  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
163111  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
163112  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
163113  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
163114  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
163115  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
163116  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
163117  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
163118  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
163119  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
163120  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
163121  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
163122  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
163123  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
163124  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
163125  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
163126  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
163127  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
163128  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
163129  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
163130  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
163131  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
163132  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
163133  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
163134  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
163135  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
163136  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
163137  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
163138  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
163139  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
163140  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
163141  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
163142  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
163143  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
163144  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
163145  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
163146  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
163147  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
163148  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
163149  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
163150  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
163151  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
163152  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
163153  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
163154  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
163155  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
163156  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
163157  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
163158  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
163159  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
163160  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
163161  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
163162  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
163163  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
163164  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
163165  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
163166  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
163167  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
163168  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
163169  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
163170  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
163171  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
163172  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
163173  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
163174  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
163175  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
163176  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
163177  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
163178  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
163179  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
163180  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
163181  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
163182  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
163183  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
163184  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
163185  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
163186  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
163187  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
163188  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
163189  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
163190  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
163191  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
163192  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
163193  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
163194  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
163195  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
163196  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
163197  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
163198  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
163199  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
163200  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
163201  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
163202  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
163203  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
163204  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
163205  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
163206  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
163207  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
163208  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
163209  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
163210  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
163211  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
163212  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
163213  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
163214  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
163215  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
163216  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
163217  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
163218  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
163219  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
163220  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
163221  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
163222  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
163223  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
163224  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
163225  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
163226  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
163227  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
163228  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
163229  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
163230  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
163231  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
163232  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
163233  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
163234  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
163235  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
163236  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
163237  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
163238  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
163239  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
163240  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
163241  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
163242  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
163243  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
163244  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
163245  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
163246  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
163247  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
163248  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
163249  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
163250  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
163251  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
163252  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
163253  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
163254  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
163255  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
163256  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
163257  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
163258  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
163259  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
163260  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
163261  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
163262  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
163263  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
163264  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
163265  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
163266  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
163267  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
163268  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
163269  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
163270  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
163271  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
163272  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
163273  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
163274  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
163275  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
163276  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
163277  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
163278  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
163279  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
163280  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
163281  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
163282  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
163283  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
163284  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
163285  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
163286  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
163287  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
163288  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
163289  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
163290  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
163291  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
163292  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
163293  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
163294  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
163295  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
163296  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
163297  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
163298  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
163299  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
163300  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
163301  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
163302  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
163303  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
163304  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
163305  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
163306  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
163307  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
163308  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
163309  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
163310  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
163311  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
163312  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
163313  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
163314  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
163315  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
163316  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
163317  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
163318  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
163319  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
163320  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
163321  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
163322  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
163323  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
163324  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
163325  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
163326  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
163327  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
163328  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
163329  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
163330  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
163331  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
163332  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
163333  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
163334  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
163335  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
163336  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
163337  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
163338  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
163339  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
163340  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
163341  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
163342  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
163343  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
163344  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
163345  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
163346  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
163347  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
163348  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
163349  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
163350  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
163351  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
163352  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
163353  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
163354  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
163355  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
163356  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
163357  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
163358  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
163359  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
163360  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
163361  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
163362  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
163363  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
163364  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
163365  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
163366  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
163367  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
163368  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
163369  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
163370  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
163371  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
163372  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
163373  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
163374  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
163375  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
163376  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
163377  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
163378  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
163379  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
163380  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
163381  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
163382  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
163383  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
163384  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
163385  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
163386  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
163387  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
163388  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
163389  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
163390  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
163391  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
163392  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
163393  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
163394  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
163395  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
163396  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
163397  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
163398  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
163399  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
163400  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
163401  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
163402  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
163403  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
163404  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
163405  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
163406  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
163407  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
163408  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
163409  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
163410  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
163411 };
163412 
163418 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
163419 {
163420  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
163421  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
163422  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
163423  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
163424  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
163425  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
163426  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
163427  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
163428  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
163429  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
163430  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
163431  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
163432  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
163433  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
163434  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
163435  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
163436  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
163437  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
163438  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
163439  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
163440  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
163441  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
163442  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
163443  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
163444  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
163445  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
163446  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
163447  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
163448  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
163449  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
163450  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
163451  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
163452  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
163453  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
163454  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
163455  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
163456  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
163457  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
163458  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
163459  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
163460 };
163461 
163467 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
163468 {
163469  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
163470  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
163471  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
163472  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
163473  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
163474  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
163475  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
163476  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
163477  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
163478  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
163479  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
163480  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
163481  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
163482  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
163483  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
163484  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
163485  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
163486  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
163487  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
163488  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
163489  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
163490  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
163491  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
163492  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
163493  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
163494  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
163495  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
163496  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
163497  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
163498  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
163499  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
163500  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
163501  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
163502  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
163503  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
163504  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
163505  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
163506  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
163507  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
163508  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
163509  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
163510  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
163511  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
163512  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
163513  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
163514  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
163515  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
163516  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
163517  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
163518  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
163519  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
163520  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
163521  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
163522  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
163523  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
163524  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
163525  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
163526  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
163527  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
163528  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
163529  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
163530  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
163531  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
163532  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
163533  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
163534  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
163535  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
163536  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
163537  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
163538  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
163539  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
163540  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
163541  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
163542  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
163543  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
163544  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
163545  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
163546  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
163547  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
163548  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
163549  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
163550  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
163551  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
163552  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
163553  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
163554  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
163555  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
163556  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
163557  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
163558  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
163559  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
163560  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
163561  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
163562  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
163563  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
163564  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
163565  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
163566  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
163567  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
163568  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
163569  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
163570  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
163571  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
163572  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
163573  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
163574  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
163575  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
163576  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
163577  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
163578  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
163579  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
163580  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
163581  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
163582  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
163583  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
163584  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
163585  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
163586  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
163587  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
163588  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
163589  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
163590  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
163591  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
163592  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
163593  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
163594  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
163595  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
163596  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
163597  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
163598  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
163599  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
163600  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
163601  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
163602  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
163603  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
163604  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
163605  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
163606  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
163607  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
163608  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
163609  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
163610  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
163611  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
163612  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
163613  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
163614  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
163615  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
163616  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
163617  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
163618  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
163619  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
163620  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
163621  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
163622  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
163623  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
163624  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
163625  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
163626  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
163627  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
163628  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
163629  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
163630  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
163631  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
163632  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
163633  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
163634  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
163635  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
163636  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
163637  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
163638  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
163639  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
163640  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
163641  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
163642  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
163643  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
163644  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
163645  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
163646  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
163647  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
163648  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
163649  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
163650  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
163651  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
163652  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
163653  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
163654  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
163655  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
163656  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
163657  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
163658  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
163659  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
163660  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
163661  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
163662  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
163663  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
163664  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
163665  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
163666  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
163667  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
163668  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
163669  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
163670  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
163671  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
163672  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
163673  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
163674  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
163675  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
163676  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
163677  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
163678  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
163679  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
163680  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
163681  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
163682  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
163683  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
163684  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
163685  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
163686  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
163687  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
163688  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
163689  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
163690  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
163691  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
163692  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
163693  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
163694  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
163695  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
163696  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
163697  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
163698  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
163699  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
163700  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
163701  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
163702  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
163703  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
163704  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
163705  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
163706  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
163707  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
163708  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
163709  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
163710  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
163711  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
163712  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
163713  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
163714  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
163715  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
163716  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
163717  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
163718  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
163719  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
163720  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
163721  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
163722  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
163723  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
163724  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
163725  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
163726  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
163727  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
163728  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
163729  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
163730  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
163731  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
163732  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
163733  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
163734  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
163735  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
163736  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
163737  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
163738  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
163739  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
163740  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
163741  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
163742  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
163743  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
163744  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
163745  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
163746  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
163747  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
163748  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
163749  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
163750  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
163751  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
163752  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
163753  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
163754  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
163755  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
163756  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
163757  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
163758  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
163759  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
163760  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
163761  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
163762  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
163763  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
163764  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
163765  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
163766  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
163767  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
163768  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
163769  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
163770  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
163771  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
163772  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
163773  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
163774  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
163775  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
163776  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
163777  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
163778  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
163779  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
163780  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
163781  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
163782  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
163783  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
163784  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
163785  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
163786  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
163787  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
163788  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
163789  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
163790  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
163791  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
163792  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
163793  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
163794  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
163795  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
163796  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
163797  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
163798  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
163799  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
163800  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
163801  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
163802  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
163803  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
163804  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
163805  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
163806  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
163807  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
163808  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
163809  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
163810  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
163811  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
163812  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
163813  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
163814  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
163815  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
163816  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
163817  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
163818  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
163819  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
163820  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
163821  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
163822  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
163823  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
163824  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
163825  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
163826  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
163827  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
163828  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
163829  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
163830  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
163831  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
163832  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
163833  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
163834  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
163835  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
163836  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
163837  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
163838  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
163839  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
163840  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
163841  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
163842  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
163843  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
163844  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
163845  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
163846  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
163847  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
163848  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
163849  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
163850  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
163851  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
163852  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
163853  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
163854  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
163855  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
163856  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
163857  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
163858  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
163859  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
163860  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
163861  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
163862  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
163863  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
163864  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
163865  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
163866  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
163867  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
163868  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
163869  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
163870  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
163871  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
163872  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
163873  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
163874  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
163875  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
163876  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
163877  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
163878  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
163879  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
163880  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
163881  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
163882  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
163883  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
163884  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
163885  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
163886  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
163887  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
163888  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
163889  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
163890  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
163891  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
163892  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
163893  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
163894  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
163895  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
163896  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
163897  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
163898  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
163899  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
163900  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
163901  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
163902  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
163903  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
163904  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
163905  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
163906  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
163907  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
163908  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
163909  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
163910  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
163911  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
163912  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
163913  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
163914  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
163915  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
163916  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
163917  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
163918  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
163919  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
163920  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
163921  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
163922  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
163923  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
163924  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
163925  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
163926  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
163927  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
163928  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
163929  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
163930  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
163931  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
163932  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
163933  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
163934  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
163935  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
163936  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
163937  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
163938  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
163939  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
163940  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
163941  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
163942  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
163943  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
163944  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
163945  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
163946  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
163947  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
163948  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
163949  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
163950  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
163951  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
163952  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
163953  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
163954  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
163955  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
163956  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
163957  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
163958  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
163959  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
163960  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
163961  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
163962  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
163963  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
163964  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
163965  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
163966  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
163967  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
163968  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
163969  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
163970  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
163971  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
163972  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
163973  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
163974  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
163975  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
163976  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
163977  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
163978  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
163979  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
163980  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
163981 };
163982 
163988 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
163989 {
163990  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
163991  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
163992  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
163993  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
163994  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
163995  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
163996  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
163997  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
163998  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
163999  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
164000  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
164001  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
164002  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
164003  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
164004  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
164005  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
164006  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
164007  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
164008  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
164009  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
164010  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
164011  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
164012  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
164013  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
164014  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
164015  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
164016  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
164017  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
164018  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
164019  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
164020  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
164021  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
164022  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
164023  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
164024  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
164025  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
164026  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
164027  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
164028  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
164029  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
164030  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
164031  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
164032  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
164033  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
164034  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
164035  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
164036  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
164037  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
164038  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
164039  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
164040  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
164041  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
164042  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
164043  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
164044  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
164045  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
164046  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
164047  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
164048  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
164049  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
164050  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
164051  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
164052  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
164053  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
164054  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
164055  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
164056  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
164057  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
164058  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
164059  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
164060  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
164061  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
164062  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
164063  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
164064  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
164065  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
164066  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
164067  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
164068  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
164069  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
164070  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
164071  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
164072  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
164073  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
164074  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
164075  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
164076  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
164077  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
164078  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
164079  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
164080  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
164081  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
164082  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
164083  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
164084  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
164085  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
164086  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
164087  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
164088  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
164089  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
164090  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
164091  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
164092  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
164093  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
164094  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
164095  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
164096  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
164097  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
164098  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
164099  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
164100  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
164101  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
164102  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
164103  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
164104  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
164105  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
164106  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
164107  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
164108  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
164109  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
164110  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
164111  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
164112  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
164113  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
164114  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
164115  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
164116  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
164117  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
164118  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
164119  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
164120  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
164121  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
164122  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
164123  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
164124  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
164125  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
164126  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
164127  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
164128  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
164129  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
164130  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
164131  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
164132  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
164133  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
164134  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
164135  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
164136  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
164137  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
164138  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
164139  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
164140  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
164141  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
164142  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
164143  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
164144  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
164145  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
164146  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
164147  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
164148  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
164149  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
164150  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
164151  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
164152  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
164153  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
164154  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
164155  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
164156  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
164157  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
164158  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
164159  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
164160  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
164161  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
164162  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
164163  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
164164  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
164165  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
164166  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
164167  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
164168  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
164169  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
164170  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
164171  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
164172  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
164173  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
164174  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
164175  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
164176  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
164177  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
164178  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
164179  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
164180  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
164181  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
164182  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
164183  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
164184  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
164185  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
164186  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
164187  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
164188  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
164189  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
164190  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
164191  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
164192  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
164193  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
164194  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
164195  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
164196  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
164197  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
164198  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
164199  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
164200  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
164201  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
164202  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
164203  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
164204  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
164205  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
164206  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
164207  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
164208  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
164209  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
164210  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
164211  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
164212  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
164213  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
164214  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
164215  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
164216  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
164217  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
164218  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
164219  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
164220  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
164221  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
164222  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
164223  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
164224  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
164225  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
164226  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
164227  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
164228  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
164229  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
164230  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
164231  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
164232  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
164233  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
164234  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
164235  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
164236  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
164237  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
164238  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
164239  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
164240  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
164241  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
164242  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
164243  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
164244  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
164245  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
164246  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
164247  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
164248  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
164249  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
164250  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
164251  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
164252  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
164253  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
164254  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
164255  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
164256  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
164257  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
164258  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
164259  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
164260  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
164261  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
164262  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
164263  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
164264  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
164265  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
164266  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
164267  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
164268  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
164269  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
164270  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
164271  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
164272  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
164273  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
164274  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
164275  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
164276  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
164277  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
164278  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
164279  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
164280  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
164281  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
164282  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
164283  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
164284  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
164285  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
164286  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
164287  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
164288  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
164289  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
164290  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
164291  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
164292  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
164293  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
164294  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
164295  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
164296  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
164297  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
164298  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
164299  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
164300  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
164301  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
164302  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
164303  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
164304  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
164305  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
164306  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
164307  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
164308  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
164309  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
164310  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
164311  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
164312  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
164313  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
164314  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
164315  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
164316  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
164317  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
164318  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
164319  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
164320  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
164321  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
164322  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
164323  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
164324  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
164325  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
164326  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
164327  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
164328  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
164329  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
164330  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
164331  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
164332  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
164333  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
164334  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
164335  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
164336  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
164337  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
164338  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
164339  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
164340  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
164341  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
164342  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
164343  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
164344  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
164345  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
164346  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
164347  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
164348  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
164349  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
164350  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
164351  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
164352  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
164353  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
164354  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
164355  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
164356  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
164357  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
164358  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
164359  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
164360  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
164361  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
164362  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
164363  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
164364  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
164365  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
164366  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
164367  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
164368  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
164369  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
164370  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
164371  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
164372  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
164373  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
164374  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
164375  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
164376  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
164377  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
164378  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
164379  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
164380  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
164381  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
164382  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
164383  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
164384  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
164385  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
164386  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
164387  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
164388  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
164389  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
164390  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
164391  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
164392  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
164393  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
164394  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
164395  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
164396  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
164397  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
164398  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
164399  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
164400  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
164401  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
164402  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
164403  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
164404  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
164405  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
164406  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
164407  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
164408  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
164409  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
164410  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
164411  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
164412  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
164413  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
164414  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
164415  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
164416  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
164417  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
164418  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
164419  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
164420  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
164421  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
164422  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
164423  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
164424  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
164425  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
164426  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
164427  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
164428  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
164429  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
164430  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
164431  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
164432  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
164433  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
164434  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
164435  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
164436  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
164437  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
164438  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
164439  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
164440  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
164441  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
164442  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
164443  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
164444  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
164445  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
164446  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
164447  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
164448  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
164449  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
164450  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
164451  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
164452  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
164453  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
164454  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
164455  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
164456  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
164457  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
164458  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
164459  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
164460  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
164461  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
164462  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
164463  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
164464  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
164465  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
164466  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
164467  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
164468  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
164469  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
164470  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
164471  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
164472  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
164473  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
164474  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
164475  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
164476  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
164477  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
164478  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
164479  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
164480  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
164481  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
164482  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
164483  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
164484  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
164485  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
164486  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
164487  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
164488  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
164489  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
164490  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
164491  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
164492  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
164493  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
164494  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
164495  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
164496  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
164497  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
164498  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
164499  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
164500  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
164501  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
164502 };
164503 
164509 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS] =
164510 {
164511  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
164512  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
164513  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
164514  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
164515  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
164516  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
164517  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
164518  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
164519  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
164520  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
164521  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
164522  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
164523  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
164524  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
164525  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
164526  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
164527  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
164528  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
164529  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
164530  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
164531  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
164532  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
164533  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
164534  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
164535  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
164536  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
164537  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
164538  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
164539  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
164540  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
164541  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
164542  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
164543  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
164544  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
164545  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
164546  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
164547  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
164548  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
164549  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
164550  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
164551  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
164552  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
164553  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
164554  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
164555  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
164556  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
164557  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
164558  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
164559  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
164560  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
164561  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
164562  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
164563  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
164564  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
164565  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
164566  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
164567  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
164568  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
164569  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
164570  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
164571  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
164572  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
164573  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
164574  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
164575  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
164576  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
164577  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
164578  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
164579  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
164580  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
164581  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
164582  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
164583  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
164584  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
164585  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
164586  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
164587  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
164588  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
164589  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
164590  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
164591  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
164592  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
164593  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
164594  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
164595  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
164596  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
164597  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
164598  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
164599  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
164600  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
164601  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
164602  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
164603  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
164604  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
164605  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
164606  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
164607  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
164608  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
164609  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
164610  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
164611  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
164612  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
164613  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
164614  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
164615  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
164616  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
164617  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
164618  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
164619  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
164620  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
164621  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
164622  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
164623  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
164624  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
164625  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
164626  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
164627  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
164628  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
164629  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
164630  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
164631  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
164632  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
164633  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
164634  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
164635  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
164636  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
164637  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
164638  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
164639  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
164640  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
164641  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
164642  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
164643  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
164644  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
164645  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
164646  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
164647  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
164648  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
164649  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
164650  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
164651  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
164652  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
164653  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
164654  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
164655  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
164656  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
164657  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
164658  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
164659  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
164660  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
164661  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
164662  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
164663  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
164664  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
164665  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
164666  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
164667  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
164668  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
164669  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
164670  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
164671  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
164672  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
164673  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
164674  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
164675  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
164676  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
164677  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
164678  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
164679  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
164680  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
164681  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
164682  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
164683  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
164684  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
164685  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
164686  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
164687  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
164688  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
164689  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
164690  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
164691  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
164692  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
164693  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
164694  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
164695  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
164696  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
164697  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
164698  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
164699  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
164700  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
164701  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
164702  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
164703  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
164704  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
164705  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
164706  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
164707  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
164708  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
164709  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
164710  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
164711  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
164712  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
164713  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
164714  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
164715  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
164716  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
164717  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
164718  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
164719  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
164720  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
164721  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
164722  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
164723  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
164724  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
164725  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
164726  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
164727  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
164728  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
164729  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
164730  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
164731  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
164732  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
164733  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
164734  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
164735  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
164736  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
164737  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
164738  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
164739  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
164740  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
164741  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
164742  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
164743  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
164744  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
164745  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
164746  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
164747  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
164748  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
164749  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
164750  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
164751  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
164752  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
164753  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
164754  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
164755  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
164756  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
164757  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
164758  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
164759  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
164760  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
164761  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
164762  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
164763  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
164764  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
164765  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
164766  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
164767  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
164768  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
164769  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
164770  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
164771  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
164772  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
164773  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
164774  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
164775  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_CHECKER_TYPE,
164776  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_132_WIDTH },
164777  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_CHECKER_TYPE,
164778  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_133_WIDTH },
164779  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_CHECKER_TYPE,
164780  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_134_WIDTH },
164781  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_CHECKER_TYPE,
164782  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_135_WIDTH },
164783  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_CHECKER_TYPE,
164784  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_136_WIDTH },
164785  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_CHECKER_TYPE,
164786  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_137_WIDTH },
164787  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_CHECKER_TYPE,
164788  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_138_WIDTH },
164789  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_CHECKER_TYPE,
164790  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_139_WIDTH },
164791  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_CHECKER_TYPE,
164792  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_140_WIDTH },
164793  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_CHECKER_TYPE,
164794  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_141_WIDTH },
164795  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_CHECKER_TYPE,
164796  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_142_WIDTH },
164797  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_CHECKER_TYPE,
164798  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_143_WIDTH },
164799  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_CHECKER_TYPE,
164800  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_144_WIDTH },
164801  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_CHECKER_TYPE,
164802  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_145_WIDTH },
164803  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_CHECKER_TYPE,
164804  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_146_WIDTH },
164805  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_CHECKER_TYPE,
164806  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_147_WIDTH },
164807  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_CHECKER_TYPE,
164808  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_148_WIDTH },
164809  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_CHECKER_TYPE,
164810  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_149_WIDTH },
164811  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_CHECKER_TYPE,
164812  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_150_WIDTH },
164813  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_CHECKER_TYPE,
164814  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_151_WIDTH },
164815  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_CHECKER_TYPE,
164816  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_152_WIDTH },
164817  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_CHECKER_TYPE,
164818  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_153_WIDTH },
164819  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_CHECKER_TYPE,
164820  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_154_WIDTH },
164821  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_CHECKER_TYPE,
164822  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_155_WIDTH },
164823  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_CHECKER_TYPE,
164824  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_156_WIDTH },
164825  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_CHECKER_TYPE,
164826  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_157_WIDTH },
164827  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_CHECKER_TYPE,
164828  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_158_WIDTH },
164829  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_CHECKER_TYPE,
164830  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_159_WIDTH },
164831  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_CHECKER_TYPE,
164832  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_160_WIDTH },
164833  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_CHECKER_TYPE,
164834  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_161_WIDTH },
164835  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_CHECKER_TYPE,
164836  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_162_WIDTH },
164837  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_CHECKER_TYPE,
164838  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_163_WIDTH },
164839  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_CHECKER_TYPE,
164840  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_164_WIDTH },
164841  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_CHECKER_TYPE,
164842  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_165_WIDTH },
164843  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_CHECKER_TYPE,
164844  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_166_WIDTH },
164845  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_CHECKER_TYPE,
164846  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_167_WIDTH },
164847  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_CHECKER_TYPE,
164848  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_168_WIDTH },
164849  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_CHECKER_TYPE,
164850  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_169_WIDTH },
164851  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_CHECKER_TYPE,
164852  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_170_WIDTH },
164853  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_CHECKER_TYPE,
164854  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_171_WIDTH },
164855  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_CHECKER_TYPE,
164856  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_172_WIDTH },
164857  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_CHECKER_TYPE,
164858  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_173_WIDTH },
164859  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_CHECKER_TYPE,
164860  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_174_WIDTH },
164861  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_CHECKER_TYPE,
164862  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_175_WIDTH },
164863  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_CHECKER_TYPE,
164864  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_176_WIDTH },
164865  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_CHECKER_TYPE,
164866  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_177_WIDTH },
164867  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_CHECKER_TYPE,
164868  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_178_WIDTH },
164869  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_CHECKER_TYPE,
164870  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_179_WIDTH },
164871  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_CHECKER_TYPE,
164872  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_180_WIDTH },
164873  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_CHECKER_TYPE,
164874  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_181_WIDTH },
164875  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_CHECKER_TYPE,
164876  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_182_WIDTH },
164877  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_CHECKER_TYPE,
164878  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_183_WIDTH },
164879  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_CHECKER_TYPE,
164880  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_184_WIDTH },
164881  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_CHECKER_TYPE,
164882  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_185_WIDTH },
164883  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_CHECKER_TYPE,
164884  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_186_WIDTH },
164885  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_CHECKER_TYPE,
164886  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_187_WIDTH },
164887  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_CHECKER_TYPE,
164888  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_188_WIDTH },
164889  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_CHECKER_TYPE,
164890  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_189_WIDTH },
164891  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_CHECKER_TYPE,
164892  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_190_WIDTH },
164893  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_CHECKER_TYPE,
164894  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_191_WIDTH },
164895  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_CHECKER_TYPE,
164896  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_192_WIDTH },
164897  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_CHECKER_TYPE,
164898  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_193_WIDTH },
164899  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_CHECKER_TYPE,
164900  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_194_WIDTH },
164901  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_CHECKER_TYPE,
164902  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_195_WIDTH },
164903  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_CHECKER_TYPE,
164904  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_196_WIDTH },
164905  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_CHECKER_TYPE,
164906  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_197_WIDTH },
164907  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_CHECKER_TYPE,
164908  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_198_WIDTH },
164909  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_CHECKER_TYPE,
164910  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_199_WIDTH },
164911  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_CHECKER_TYPE,
164912  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_200_WIDTH },
164913  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_CHECKER_TYPE,
164914  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_201_WIDTH },
164915  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_CHECKER_TYPE,
164916  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_202_WIDTH },
164917  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_CHECKER_TYPE,
164918  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_203_WIDTH },
164919  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_CHECKER_TYPE,
164920  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_204_WIDTH },
164921  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_CHECKER_TYPE,
164922  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_205_WIDTH },
164923  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_CHECKER_TYPE,
164924  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_206_WIDTH },
164925  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_CHECKER_TYPE,
164926  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_207_WIDTH },
164927  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_CHECKER_TYPE,
164928  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_208_WIDTH },
164929  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_CHECKER_TYPE,
164930  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_209_WIDTH },
164931  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_CHECKER_TYPE,
164932  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_210_WIDTH },
164933  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_CHECKER_TYPE,
164934  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_211_WIDTH },
164935  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_CHECKER_TYPE,
164936  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_212_WIDTH },
164937  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_CHECKER_TYPE,
164938  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_213_WIDTH },
164939  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_CHECKER_TYPE,
164940  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_214_WIDTH },
164941  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_CHECKER_TYPE,
164942  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_215_WIDTH },
164943  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_CHECKER_TYPE,
164944  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_216_WIDTH },
164945  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_CHECKER_TYPE,
164946  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_217_WIDTH },
164947  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_CHECKER_TYPE,
164948  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_218_WIDTH },
164949  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_CHECKER_TYPE,
164950  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_219_WIDTH },
164951  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_CHECKER_TYPE,
164952  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_220_WIDTH },
164953  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_CHECKER_TYPE,
164954  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_221_WIDTH },
164955  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_CHECKER_TYPE,
164956  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_222_WIDTH },
164957  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_CHECKER_TYPE,
164958  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_223_WIDTH },
164959  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_CHECKER_TYPE,
164960  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_224_WIDTH },
164961  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_CHECKER_TYPE,
164962  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_225_WIDTH },
164963  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_CHECKER_TYPE,
164964  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_226_WIDTH },
164965  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_CHECKER_TYPE,
164966  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_227_WIDTH },
164967  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_CHECKER_TYPE,
164968  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_228_WIDTH },
164969  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_CHECKER_TYPE,
164970  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_229_WIDTH },
164971  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_CHECKER_TYPE,
164972  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_230_WIDTH },
164973  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_CHECKER_TYPE,
164974  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_231_WIDTH },
164975  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_CHECKER_TYPE,
164976  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_232_WIDTH },
164977  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_CHECKER_TYPE,
164978  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_233_WIDTH },
164979  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_CHECKER_TYPE,
164980  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_234_WIDTH },
164981  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_CHECKER_TYPE,
164982  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_235_WIDTH },
164983  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_CHECKER_TYPE,
164984  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_236_WIDTH },
164985  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_CHECKER_TYPE,
164986  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_237_WIDTH },
164987  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_CHECKER_TYPE,
164988  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_238_WIDTH },
164989  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_CHECKER_TYPE,
164990  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_239_WIDTH },
164991  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_CHECKER_TYPE,
164992  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_240_WIDTH },
164993  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_CHECKER_TYPE,
164994  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_241_WIDTH },
164995  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_CHECKER_TYPE,
164996  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_242_WIDTH },
164997  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_CHECKER_TYPE,
164998  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_243_WIDTH },
164999  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_CHECKER_TYPE,
165000  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_244_WIDTH },
165001  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_CHECKER_TYPE,
165002  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_245_WIDTH },
165003  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_CHECKER_TYPE,
165004  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_246_WIDTH },
165005  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_CHECKER_TYPE,
165006  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_247_WIDTH },
165007  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_CHECKER_TYPE,
165008  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_248_WIDTH },
165009  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_CHECKER_TYPE,
165010  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_249_WIDTH },
165011  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_CHECKER_TYPE,
165012  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_250_WIDTH },
165013  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_CHECKER_TYPE,
165014  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_251_WIDTH },
165015  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_CHECKER_TYPE,
165016  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_252_WIDTH },
165017  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_CHECKER_TYPE,
165018  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_253_WIDTH },
165019  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_CHECKER_TYPE,
165020  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_254_WIDTH },
165021  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_CHECKER_TYPE,
165022  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_GROUP_255_WIDTH },
165023 };
165024 
165030 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS] =
165031 {
165032  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_CHECKER_TYPE,
165033  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_0_WIDTH },
165034  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_CHECKER_TYPE,
165035  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_1_WIDTH },
165036  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_CHECKER_TYPE,
165037  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_2_WIDTH },
165038  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_CHECKER_TYPE,
165039  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_3_WIDTH },
165040  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_CHECKER_TYPE,
165041  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_4_WIDTH },
165042  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_CHECKER_TYPE,
165043  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_5_WIDTH },
165044  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_CHECKER_TYPE,
165045  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_6_WIDTH },
165046  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_CHECKER_TYPE,
165047  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_7_WIDTH },
165048  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_CHECKER_TYPE,
165049  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_8_WIDTH },
165050  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_CHECKER_TYPE,
165051  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_9_WIDTH },
165052  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_CHECKER_TYPE,
165053  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_10_WIDTH },
165054  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_CHECKER_TYPE,
165055  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_11_WIDTH },
165056  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_CHECKER_TYPE,
165057  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_12_WIDTH },
165058  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_CHECKER_TYPE,
165059  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_13_WIDTH },
165060  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_CHECKER_TYPE,
165061  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_14_WIDTH },
165062  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_CHECKER_TYPE,
165063  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_15_WIDTH },
165064  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_CHECKER_TYPE,
165065  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_16_WIDTH },
165066  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_CHECKER_TYPE,
165067  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_17_WIDTH },
165068  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_CHECKER_TYPE,
165069  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_18_WIDTH },
165070  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_CHECKER_TYPE,
165071  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_19_WIDTH },
165072  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_CHECKER_TYPE,
165073  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_20_WIDTH },
165074  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_CHECKER_TYPE,
165075  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_21_WIDTH },
165076  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_CHECKER_TYPE,
165077  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_22_WIDTH },
165078  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_CHECKER_TYPE,
165079  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_23_WIDTH },
165080  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_CHECKER_TYPE,
165081  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_24_WIDTH },
165082  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_CHECKER_TYPE,
165083  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_25_WIDTH },
165084  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_CHECKER_TYPE,
165085  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_26_WIDTH },
165086  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_CHECKER_TYPE,
165087  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_27_WIDTH },
165088  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_CHECKER_TYPE,
165089  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_28_WIDTH },
165090  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_CHECKER_TYPE,
165091  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_29_WIDTH },
165092  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_CHECKER_TYPE,
165093  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_30_WIDTH },
165094  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_CHECKER_TYPE,
165095  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_31_WIDTH },
165096  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_CHECKER_TYPE,
165097  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_32_WIDTH },
165098  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_CHECKER_TYPE,
165099  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_33_WIDTH },
165100  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_CHECKER_TYPE,
165101  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_34_WIDTH },
165102  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_CHECKER_TYPE,
165103  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_35_WIDTH },
165104  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_CHECKER_TYPE,
165105  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_36_WIDTH },
165106  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_CHECKER_TYPE,
165107  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_37_WIDTH },
165108  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_CHECKER_TYPE,
165109  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_38_WIDTH },
165110  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_CHECKER_TYPE,
165111  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_39_WIDTH },
165112  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_CHECKER_TYPE,
165113  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_40_WIDTH },
165114  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_CHECKER_TYPE,
165115  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_41_WIDTH },
165116  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_CHECKER_TYPE,
165117  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_42_WIDTH },
165118  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_CHECKER_TYPE,
165119  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_43_WIDTH },
165120  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_CHECKER_TYPE,
165121  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_44_WIDTH },
165122  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_CHECKER_TYPE,
165123  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_45_WIDTH },
165124  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_CHECKER_TYPE,
165125  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_46_WIDTH },
165126  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_CHECKER_TYPE,
165127  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_47_WIDTH },
165128  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_CHECKER_TYPE,
165129  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_48_WIDTH },
165130  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_CHECKER_TYPE,
165131  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_49_WIDTH },
165132  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_CHECKER_TYPE,
165133  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_50_WIDTH },
165134  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_CHECKER_TYPE,
165135  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_51_WIDTH },
165136  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_CHECKER_TYPE,
165137  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_52_WIDTH },
165138  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_CHECKER_TYPE,
165139  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_53_WIDTH },
165140  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_CHECKER_TYPE,
165141  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_54_WIDTH },
165142  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_CHECKER_TYPE,
165143  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_55_WIDTH },
165144  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_CHECKER_TYPE,
165145  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_56_WIDTH },
165146  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_CHECKER_TYPE,
165147  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_57_WIDTH },
165148  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_CHECKER_TYPE,
165149  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_58_WIDTH },
165150  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_CHECKER_TYPE,
165151  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_59_WIDTH },
165152  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_CHECKER_TYPE,
165153  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_60_WIDTH },
165154  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_CHECKER_TYPE,
165155  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_61_WIDTH },
165156  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_CHECKER_TYPE,
165157  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_62_WIDTH },
165158  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_CHECKER_TYPE,
165159  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_63_WIDTH },
165160  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_CHECKER_TYPE,
165161  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_64_WIDTH },
165162  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_CHECKER_TYPE,
165163  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_65_WIDTH },
165164  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_CHECKER_TYPE,
165165  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_66_WIDTH },
165166  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_CHECKER_TYPE,
165167  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_67_WIDTH },
165168  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_CHECKER_TYPE,
165169  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_68_WIDTH },
165170  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_CHECKER_TYPE,
165171  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_69_WIDTH },
165172  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_CHECKER_TYPE,
165173  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_70_WIDTH },
165174  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_CHECKER_TYPE,
165175  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_71_WIDTH },
165176  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_CHECKER_TYPE,
165177  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_72_WIDTH },
165178  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_CHECKER_TYPE,
165179  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_73_WIDTH },
165180  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_CHECKER_TYPE,
165181  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_74_WIDTH },
165182  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_CHECKER_TYPE,
165183  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_75_WIDTH },
165184  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_CHECKER_TYPE,
165185  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_76_WIDTH },
165186  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_CHECKER_TYPE,
165187  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_77_WIDTH },
165188  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_CHECKER_TYPE,
165189  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_78_WIDTH },
165190  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_CHECKER_TYPE,
165191  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_79_WIDTH },
165192  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_CHECKER_TYPE,
165193  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_80_WIDTH },
165194  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_CHECKER_TYPE,
165195  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_81_WIDTH },
165196  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_CHECKER_TYPE,
165197  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_82_WIDTH },
165198  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_CHECKER_TYPE,
165199  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_83_WIDTH },
165200  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_CHECKER_TYPE,
165201  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_84_WIDTH },
165202  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_CHECKER_TYPE,
165203  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_85_WIDTH },
165204  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_CHECKER_TYPE,
165205  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_86_WIDTH },
165206  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_CHECKER_TYPE,
165207  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_87_WIDTH },
165208  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_CHECKER_TYPE,
165209  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_88_WIDTH },
165210  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_CHECKER_TYPE,
165211  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_89_WIDTH },
165212  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_CHECKER_TYPE,
165213  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_90_WIDTH },
165214  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_CHECKER_TYPE,
165215  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_91_WIDTH },
165216  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_CHECKER_TYPE,
165217  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_92_WIDTH },
165218  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_CHECKER_TYPE,
165219  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_93_WIDTH },
165220  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_CHECKER_TYPE,
165221  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_94_WIDTH },
165222  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_CHECKER_TYPE,
165223  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_95_WIDTH },
165224  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_CHECKER_TYPE,
165225  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_96_WIDTH },
165226  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_CHECKER_TYPE,
165227  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_97_WIDTH },
165228  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_CHECKER_TYPE,
165229  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_98_WIDTH },
165230  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_CHECKER_TYPE,
165231  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_99_WIDTH },
165232  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_CHECKER_TYPE,
165233  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_100_WIDTH },
165234  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_CHECKER_TYPE,
165235  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_101_WIDTH },
165236  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_CHECKER_TYPE,
165237  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_102_WIDTH },
165238  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_CHECKER_TYPE,
165239  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_103_WIDTH },
165240  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_CHECKER_TYPE,
165241  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_104_WIDTH },
165242  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_CHECKER_TYPE,
165243  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_105_WIDTH },
165244  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_CHECKER_TYPE,
165245  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_106_WIDTH },
165246  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_CHECKER_TYPE,
165247  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_107_WIDTH },
165248  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_CHECKER_TYPE,
165249  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_108_WIDTH },
165250  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_CHECKER_TYPE,
165251  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_109_WIDTH },
165252  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_CHECKER_TYPE,
165253  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_110_WIDTH },
165254  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_CHECKER_TYPE,
165255  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_111_WIDTH },
165256  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_CHECKER_TYPE,
165257  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_112_WIDTH },
165258  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_CHECKER_TYPE,
165259  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_113_WIDTH },
165260  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_CHECKER_TYPE,
165261  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_114_WIDTH },
165262  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_CHECKER_TYPE,
165263  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_115_WIDTH },
165264  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_CHECKER_TYPE,
165265  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_116_WIDTH },
165266  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_CHECKER_TYPE,
165267  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_117_WIDTH },
165268  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_CHECKER_TYPE,
165269  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_118_WIDTH },
165270  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_CHECKER_TYPE,
165271  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_119_WIDTH },
165272  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_CHECKER_TYPE,
165273  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_120_WIDTH },
165274  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_CHECKER_TYPE,
165275  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_121_WIDTH },
165276  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_CHECKER_TYPE,
165277  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_122_WIDTH },
165278  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_CHECKER_TYPE,
165279  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_123_WIDTH },
165280  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_CHECKER_TYPE,
165281  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_124_WIDTH },
165282  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_CHECKER_TYPE,
165283  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_125_WIDTH },
165284  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_CHECKER_TYPE,
165285  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_126_WIDTH },
165286  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_CHECKER_TYPE,
165287  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_127_WIDTH },
165288  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_CHECKER_TYPE,
165289  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_128_WIDTH },
165290  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_CHECKER_TYPE,
165291  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_129_WIDTH },
165292  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_CHECKER_TYPE,
165293  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_130_WIDTH },
165294  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_CHECKER_TYPE,
165295  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_131_WIDTH },
165296  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_CHECKER_TYPE,
165297  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_132_WIDTH },
165298  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_CHECKER_TYPE,
165299  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_133_WIDTH },
165300  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_CHECKER_TYPE,
165301  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_134_WIDTH },
165302  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_CHECKER_TYPE,
165303  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_135_WIDTH },
165304  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_CHECKER_TYPE,
165305  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_136_WIDTH },
165306  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_CHECKER_TYPE,
165307  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_137_WIDTH },
165308  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_CHECKER_TYPE,
165309  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_138_WIDTH },
165310  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_CHECKER_TYPE,
165311  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_139_WIDTH },
165312  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_CHECKER_TYPE,
165313  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_140_WIDTH },
165314  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_CHECKER_TYPE,
165315  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_141_WIDTH },
165316  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_CHECKER_TYPE,
165317  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_142_WIDTH },
165318  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_CHECKER_TYPE,
165319  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_143_WIDTH },
165320  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_CHECKER_TYPE,
165321  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_144_WIDTH },
165322  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_CHECKER_TYPE,
165323  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_145_WIDTH },
165324  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_CHECKER_TYPE,
165325  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_146_WIDTH },
165326  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_CHECKER_TYPE,
165327  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_147_WIDTH },
165328  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_CHECKER_TYPE,
165329  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_148_WIDTH },
165330  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_CHECKER_TYPE,
165331  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_149_WIDTH },
165332  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_CHECKER_TYPE,
165333  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_150_WIDTH },
165334  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_CHECKER_TYPE,
165335  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_151_WIDTH },
165336  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_CHECKER_TYPE,
165337  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_152_WIDTH },
165338  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_CHECKER_TYPE,
165339  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_153_WIDTH },
165340  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_CHECKER_TYPE,
165341  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_154_WIDTH },
165342  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_CHECKER_TYPE,
165343  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_155_WIDTH },
165344  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_CHECKER_TYPE,
165345  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_156_WIDTH },
165346  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_CHECKER_TYPE,
165347  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_157_WIDTH },
165348  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_CHECKER_TYPE,
165349  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_158_WIDTH },
165350  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_CHECKER_TYPE,
165351  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_159_WIDTH },
165352  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_CHECKER_TYPE,
165353  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_160_WIDTH },
165354  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_CHECKER_TYPE,
165355  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_161_WIDTH },
165356  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_CHECKER_TYPE,
165357  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_162_WIDTH },
165358  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_CHECKER_TYPE,
165359  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_163_WIDTH },
165360  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_CHECKER_TYPE,
165361  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_164_WIDTH },
165362  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_CHECKER_TYPE,
165363  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_165_WIDTH },
165364  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_CHECKER_TYPE,
165365  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_166_WIDTH },
165366  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_CHECKER_TYPE,
165367  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_167_WIDTH },
165368  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_CHECKER_TYPE,
165369  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_168_WIDTH },
165370  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_CHECKER_TYPE,
165371  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_169_WIDTH },
165372  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_CHECKER_TYPE,
165373  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_170_WIDTH },
165374  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_CHECKER_TYPE,
165375  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_171_WIDTH },
165376  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_CHECKER_TYPE,
165377  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_172_WIDTH },
165378  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_CHECKER_TYPE,
165379  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_173_WIDTH },
165380  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_CHECKER_TYPE,
165381  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_174_WIDTH },
165382  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_CHECKER_TYPE,
165383  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_175_WIDTH },
165384  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_CHECKER_TYPE,
165385  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_176_WIDTH },
165386  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_CHECKER_TYPE,
165387  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_177_WIDTH },
165388  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_CHECKER_TYPE,
165389  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_178_WIDTH },
165390  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_CHECKER_TYPE,
165391  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_179_WIDTH },
165392  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_CHECKER_TYPE,
165393  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_180_WIDTH },
165394  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_CHECKER_TYPE,
165395  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_181_WIDTH },
165396  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_CHECKER_TYPE,
165397  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_182_WIDTH },
165398  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_CHECKER_TYPE,
165399  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_183_WIDTH },
165400  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_CHECKER_TYPE,
165401  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_184_WIDTH },
165402  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_CHECKER_TYPE,
165403  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_185_WIDTH },
165404  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_CHECKER_TYPE,
165405  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_186_WIDTH },
165406  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_CHECKER_TYPE,
165407  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_187_WIDTH },
165408  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_CHECKER_TYPE,
165409  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_188_WIDTH },
165410  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_CHECKER_TYPE,
165411  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_189_WIDTH },
165412  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_CHECKER_TYPE,
165413  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_190_WIDTH },
165414  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_CHECKER_TYPE,
165415  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_191_WIDTH },
165416  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_CHECKER_TYPE,
165417  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_192_WIDTH },
165418  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_CHECKER_TYPE,
165419  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_193_WIDTH },
165420  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_CHECKER_TYPE,
165421  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_194_WIDTH },
165422  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_CHECKER_TYPE,
165423  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_195_WIDTH },
165424  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_CHECKER_TYPE,
165425  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_196_WIDTH },
165426  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_CHECKER_TYPE,
165427  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_197_WIDTH },
165428  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_CHECKER_TYPE,
165429  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_198_WIDTH },
165430  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_CHECKER_TYPE,
165431  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_199_WIDTH },
165432  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_CHECKER_TYPE,
165433  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_200_WIDTH },
165434  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_CHECKER_TYPE,
165435  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_201_WIDTH },
165436  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_CHECKER_TYPE,
165437  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_202_WIDTH },
165438  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_CHECKER_TYPE,
165439  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_203_WIDTH },
165440  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_CHECKER_TYPE,
165441  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_204_WIDTH },
165442  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_CHECKER_TYPE,
165443  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_205_WIDTH },
165444  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_CHECKER_TYPE,
165445  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_206_WIDTH },
165446  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_CHECKER_TYPE,
165447  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_207_WIDTH },
165448  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_CHECKER_TYPE,
165449  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_208_WIDTH },
165450  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_CHECKER_TYPE,
165451  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_209_WIDTH },
165452  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_CHECKER_TYPE,
165453  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_210_WIDTH },
165454  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_CHECKER_TYPE,
165455  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_211_WIDTH },
165456  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_CHECKER_TYPE,
165457  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_212_WIDTH },
165458  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_CHECKER_TYPE,
165459  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_213_WIDTH },
165460  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_CHECKER_TYPE,
165461  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_214_WIDTH },
165462  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_CHECKER_TYPE,
165463  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_215_WIDTH },
165464  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_CHECKER_TYPE,
165465  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_216_WIDTH },
165466  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_CHECKER_TYPE,
165467  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_217_WIDTH },
165468  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_CHECKER_TYPE,
165469  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_218_WIDTH },
165470  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_CHECKER_TYPE,
165471  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_219_WIDTH },
165472  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_CHECKER_TYPE,
165473  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_220_WIDTH },
165474  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_CHECKER_TYPE,
165475  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_221_WIDTH },
165476  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_CHECKER_TYPE,
165477  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_222_WIDTH },
165478  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_CHECKER_TYPE,
165479  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_223_WIDTH },
165480  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_CHECKER_TYPE,
165481  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_224_WIDTH },
165482  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_CHECKER_TYPE,
165483  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_225_WIDTH },
165484  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_CHECKER_TYPE,
165485  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_226_WIDTH },
165486  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_CHECKER_TYPE,
165487  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_227_WIDTH },
165488  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_CHECKER_TYPE,
165489  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_228_WIDTH },
165490  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_CHECKER_TYPE,
165491  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_229_WIDTH },
165492  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_CHECKER_TYPE,
165493  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_230_WIDTH },
165494  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_CHECKER_TYPE,
165495  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_231_WIDTH },
165496  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_CHECKER_TYPE,
165497  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_232_WIDTH },
165498  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_CHECKER_TYPE,
165499  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_233_WIDTH },
165500  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_CHECKER_TYPE,
165501  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_234_WIDTH },
165502  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_CHECKER_TYPE,
165503  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_235_WIDTH },
165504  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_CHECKER_TYPE,
165505  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_236_WIDTH },
165506  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_CHECKER_TYPE,
165507  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_237_WIDTH },
165508  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_CHECKER_TYPE,
165509  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_238_WIDTH },
165510  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_CHECKER_TYPE,
165511  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_239_WIDTH },
165512  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_CHECKER_TYPE,
165513  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_240_WIDTH },
165514  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_CHECKER_TYPE,
165515  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_241_WIDTH },
165516  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_CHECKER_TYPE,
165517  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_242_WIDTH },
165518  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_CHECKER_TYPE,
165519  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_243_WIDTH },
165520  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_CHECKER_TYPE,
165521  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_244_WIDTH },
165522  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_CHECKER_TYPE,
165523  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_245_WIDTH },
165524  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_CHECKER_TYPE,
165525  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_246_WIDTH },
165526  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_CHECKER_TYPE,
165527  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_247_WIDTH },
165528  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_CHECKER_TYPE,
165529  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_248_WIDTH },
165530  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_CHECKER_TYPE,
165531  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_249_WIDTH },
165532  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_CHECKER_TYPE,
165533  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_250_WIDTH },
165534  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_CHECKER_TYPE,
165535  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_251_WIDTH },
165536  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_CHECKER_TYPE,
165537  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_252_WIDTH },
165538  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_CHECKER_TYPE,
165539  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_253_WIDTH },
165540  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_CHECKER_TYPE,
165541  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_254_WIDTH },
165542  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_CHECKER_TYPE,
165543  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_GROUP_255_WIDTH },
165544 };
165545 
165551 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS] =
165552 {
165553  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_CHECKER_TYPE,
165554  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_0_WIDTH },
165555  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_CHECKER_TYPE,
165556  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_1_WIDTH },
165557  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_CHECKER_TYPE,
165558  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_2_WIDTH },
165559  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_CHECKER_TYPE,
165560  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_3_WIDTH },
165561  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_CHECKER_TYPE,
165562  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_4_WIDTH },
165563  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_CHECKER_TYPE,
165564  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_5_WIDTH },
165565  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_CHECKER_TYPE,
165566  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_6_WIDTH },
165567  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_CHECKER_TYPE,
165568  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_7_WIDTH },
165569  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_CHECKER_TYPE,
165570  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_8_WIDTH },
165571  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_CHECKER_TYPE,
165572  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_9_WIDTH },
165573  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_CHECKER_TYPE,
165574  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_10_WIDTH },
165575  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_CHECKER_TYPE,
165576  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_11_WIDTH },
165577  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_CHECKER_TYPE,
165578  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_12_WIDTH },
165579  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_CHECKER_TYPE,
165580  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_13_WIDTH },
165581  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_CHECKER_TYPE,
165582  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_14_WIDTH },
165583  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_CHECKER_TYPE,
165584  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_15_WIDTH },
165585  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_CHECKER_TYPE,
165586  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_16_WIDTH },
165587  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_CHECKER_TYPE,
165588  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_17_WIDTH },
165589  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_CHECKER_TYPE,
165590  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_18_WIDTH },
165591  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_CHECKER_TYPE,
165592  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_19_WIDTH },
165593  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_CHECKER_TYPE,
165594  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_20_WIDTH },
165595  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_CHECKER_TYPE,
165596  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_21_WIDTH },
165597  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_CHECKER_TYPE,
165598  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_22_WIDTH },
165599  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_CHECKER_TYPE,
165600  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_23_WIDTH },
165601  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_CHECKER_TYPE,
165602  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_24_WIDTH },
165603  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_CHECKER_TYPE,
165604  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_25_WIDTH },
165605  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_CHECKER_TYPE,
165606  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_26_WIDTH },
165607  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_CHECKER_TYPE,
165608  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_27_WIDTH },
165609  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_CHECKER_TYPE,
165610  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_28_WIDTH },
165611  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_CHECKER_TYPE,
165612  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_29_WIDTH },
165613  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_CHECKER_TYPE,
165614  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_30_WIDTH },
165615  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_CHECKER_TYPE,
165616  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_31_WIDTH },
165617  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_CHECKER_TYPE,
165618  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_32_WIDTH },
165619  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_CHECKER_TYPE,
165620  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_33_WIDTH },
165621  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_CHECKER_TYPE,
165622  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_34_WIDTH },
165623  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_CHECKER_TYPE,
165624  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_35_WIDTH },
165625  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_CHECKER_TYPE,
165626  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_36_WIDTH },
165627  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_CHECKER_TYPE,
165628  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_37_WIDTH },
165629  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_CHECKER_TYPE,
165630  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_38_WIDTH },
165631  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_CHECKER_TYPE,
165632  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_39_WIDTH },
165633  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_CHECKER_TYPE,
165634  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_40_WIDTH },
165635  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_CHECKER_TYPE,
165636  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_41_WIDTH },
165637  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_CHECKER_TYPE,
165638  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_42_WIDTH },
165639  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_CHECKER_TYPE,
165640  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_43_WIDTH },
165641  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_CHECKER_TYPE,
165642  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_44_WIDTH },
165643  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_CHECKER_TYPE,
165644  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_45_WIDTH },
165645  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_CHECKER_TYPE,
165646  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_46_WIDTH },
165647  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_CHECKER_TYPE,
165648  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_47_WIDTH },
165649  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_CHECKER_TYPE,
165650  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_48_WIDTH },
165651  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_CHECKER_TYPE,
165652  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_49_WIDTH },
165653  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_CHECKER_TYPE,
165654  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_50_WIDTH },
165655  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_CHECKER_TYPE,
165656  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_51_WIDTH },
165657  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_CHECKER_TYPE,
165658  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_52_WIDTH },
165659  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_CHECKER_TYPE,
165660  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_53_WIDTH },
165661  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_CHECKER_TYPE,
165662  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_54_WIDTH },
165663  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_CHECKER_TYPE,
165664  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_55_WIDTH },
165665  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_CHECKER_TYPE,
165666  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_56_WIDTH },
165667  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_CHECKER_TYPE,
165668  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_57_WIDTH },
165669  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_CHECKER_TYPE,
165670  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_58_WIDTH },
165671  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_CHECKER_TYPE,
165672  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_59_WIDTH },
165673  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_CHECKER_TYPE,
165674  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_60_WIDTH },
165675  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_CHECKER_TYPE,
165676  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_61_WIDTH },
165677  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_CHECKER_TYPE,
165678  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_62_WIDTH },
165679  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_CHECKER_TYPE,
165680  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_63_WIDTH },
165681  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_CHECKER_TYPE,
165682  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_64_WIDTH },
165683  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_CHECKER_TYPE,
165684  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_65_WIDTH },
165685  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_CHECKER_TYPE,
165686  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_66_WIDTH },
165687  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_CHECKER_TYPE,
165688  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_67_WIDTH },
165689  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_CHECKER_TYPE,
165690  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_68_WIDTH },
165691  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_CHECKER_TYPE,
165692  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_69_WIDTH },
165693  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_CHECKER_TYPE,
165694  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_70_WIDTH },
165695  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_CHECKER_TYPE,
165696  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_71_WIDTH },
165697  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_CHECKER_TYPE,
165698  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_72_WIDTH },
165699  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_CHECKER_TYPE,
165700  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_73_WIDTH },
165701  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_CHECKER_TYPE,
165702  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_74_WIDTH },
165703  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_CHECKER_TYPE,
165704  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_75_WIDTH },
165705  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_CHECKER_TYPE,
165706  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_76_WIDTH },
165707  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_CHECKER_TYPE,
165708  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_77_WIDTH },
165709  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_CHECKER_TYPE,
165710  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_78_WIDTH },
165711  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_CHECKER_TYPE,
165712  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_79_WIDTH },
165713  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_CHECKER_TYPE,
165714  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_80_WIDTH },
165715  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_CHECKER_TYPE,
165716  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_81_WIDTH },
165717  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_CHECKER_TYPE,
165718  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_82_WIDTH },
165719  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_CHECKER_TYPE,
165720  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_83_WIDTH },
165721  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_CHECKER_TYPE,
165722  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_84_WIDTH },
165723  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_CHECKER_TYPE,
165724  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_85_WIDTH },
165725  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_CHECKER_TYPE,
165726  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_86_WIDTH },
165727  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_CHECKER_TYPE,
165728  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_87_WIDTH },
165729  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_CHECKER_TYPE,
165730  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_88_WIDTH },
165731  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_CHECKER_TYPE,
165732  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_89_WIDTH },
165733  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_CHECKER_TYPE,
165734  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_90_WIDTH },
165735  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_CHECKER_TYPE,
165736  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_91_WIDTH },
165737  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_CHECKER_TYPE,
165738  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_92_WIDTH },
165739  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_CHECKER_TYPE,
165740  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_93_WIDTH },
165741  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_CHECKER_TYPE,
165742  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_94_WIDTH },
165743  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_CHECKER_TYPE,
165744  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_95_WIDTH },
165745  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_CHECKER_TYPE,
165746  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_96_WIDTH },
165747  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_CHECKER_TYPE,
165748  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_97_WIDTH },
165749  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_CHECKER_TYPE,
165750  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_98_WIDTH },
165751  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_CHECKER_TYPE,
165752  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_99_WIDTH },
165753  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_CHECKER_TYPE,
165754  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_100_WIDTH },
165755  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_CHECKER_TYPE,
165756  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_101_WIDTH },
165757  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_CHECKER_TYPE,
165758  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_102_WIDTH },
165759  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_CHECKER_TYPE,
165760  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_103_WIDTH },
165761  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_CHECKER_TYPE,
165762  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_104_WIDTH },
165763  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_CHECKER_TYPE,
165764  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_105_WIDTH },
165765  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_CHECKER_TYPE,
165766  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_106_WIDTH },
165767  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_CHECKER_TYPE,
165768  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_107_WIDTH },
165769  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_CHECKER_TYPE,
165770  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_108_WIDTH },
165771  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_CHECKER_TYPE,
165772  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_109_WIDTH },
165773  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_CHECKER_TYPE,
165774  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_110_WIDTH },
165775  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_CHECKER_TYPE,
165776  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_111_WIDTH },
165777  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_CHECKER_TYPE,
165778  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_112_WIDTH },
165779  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_CHECKER_TYPE,
165780  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_113_WIDTH },
165781  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_CHECKER_TYPE,
165782  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_114_WIDTH },
165783  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_CHECKER_TYPE,
165784  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_115_WIDTH },
165785  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_CHECKER_TYPE,
165786  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_116_WIDTH },
165787  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_CHECKER_TYPE,
165788  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_117_WIDTH },
165789  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_CHECKER_TYPE,
165790  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_118_WIDTH },
165791  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_CHECKER_TYPE,
165792  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_119_WIDTH },
165793  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_CHECKER_TYPE,
165794  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_120_WIDTH },
165795  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_CHECKER_TYPE,
165796  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_121_WIDTH },
165797  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_CHECKER_TYPE,
165798  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_122_WIDTH },
165799  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_CHECKER_TYPE,
165800  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_123_WIDTH },
165801  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_CHECKER_TYPE,
165802  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_124_WIDTH },
165803  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_CHECKER_TYPE,
165804  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_125_WIDTH },
165805  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_CHECKER_TYPE,
165806  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_126_WIDTH },
165807  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_CHECKER_TYPE,
165808  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_127_WIDTH },
165809  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_CHECKER_TYPE,
165810  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_128_WIDTH },
165811  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_CHECKER_TYPE,
165812  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_129_WIDTH },
165813  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_CHECKER_TYPE,
165814  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_130_WIDTH },
165815  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_CHECKER_TYPE,
165816  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_131_WIDTH },
165817  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_CHECKER_TYPE,
165818  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_132_WIDTH },
165819  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_CHECKER_TYPE,
165820  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_133_WIDTH },
165821  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_CHECKER_TYPE,
165822  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_134_WIDTH },
165823  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_CHECKER_TYPE,
165824  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_135_WIDTH },
165825  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_CHECKER_TYPE,
165826  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_136_WIDTH },
165827  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_CHECKER_TYPE,
165828  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_137_WIDTH },
165829  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_CHECKER_TYPE,
165830  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_138_WIDTH },
165831  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_CHECKER_TYPE,
165832  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_139_WIDTH },
165833  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_CHECKER_TYPE,
165834  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_140_WIDTH },
165835  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_CHECKER_TYPE,
165836  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_141_WIDTH },
165837  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_CHECKER_TYPE,
165838  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_142_WIDTH },
165839  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_CHECKER_TYPE,
165840  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_143_WIDTH },
165841  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_CHECKER_TYPE,
165842  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_144_WIDTH },
165843  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_CHECKER_TYPE,
165844  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_145_WIDTH },
165845  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_CHECKER_TYPE,
165846  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_146_WIDTH },
165847  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_CHECKER_TYPE,
165848  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_147_WIDTH },
165849  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_CHECKER_TYPE,
165850  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_148_WIDTH },
165851  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_CHECKER_TYPE,
165852  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_149_WIDTH },
165853  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_CHECKER_TYPE,
165854  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_150_WIDTH },
165855  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_CHECKER_TYPE,
165856  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_151_WIDTH },
165857  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_CHECKER_TYPE,
165858  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_152_WIDTH },
165859  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_CHECKER_TYPE,
165860  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_153_WIDTH },
165861  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_CHECKER_TYPE,
165862  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_154_WIDTH },
165863  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_CHECKER_TYPE,
165864  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_155_WIDTH },
165865  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_CHECKER_TYPE,
165866  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_156_WIDTH },
165867  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_CHECKER_TYPE,
165868  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_157_WIDTH },
165869  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_CHECKER_TYPE,
165870  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_158_WIDTH },
165871  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_CHECKER_TYPE,
165872  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_159_WIDTH },
165873  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_CHECKER_TYPE,
165874  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_160_WIDTH },
165875  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_CHECKER_TYPE,
165876  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_161_WIDTH },
165877  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_CHECKER_TYPE,
165878  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_162_WIDTH },
165879  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_CHECKER_TYPE,
165880  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_163_WIDTH },
165881  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_CHECKER_TYPE,
165882  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_164_WIDTH },
165883  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_CHECKER_TYPE,
165884  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_165_WIDTH },
165885  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_CHECKER_TYPE,
165886  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_166_WIDTH },
165887  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_CHECKER_TYPE,
165888  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_167_WIDTH },
165889  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_CHECKER_TYPE,
165890  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_168_WIDTH },
165891  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_CHECKER_TYPE,
165892  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_169_WIDTH },
165893  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_CHECKER_TYPE,
165894  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_170_WIDTH },
165895  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_CHECKER_TYPE,
165896  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_171_WIDTH },
165897  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_CHECKER_TYPE,
165898  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_172_WIDTH },
165899  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_CHECKER_TYPE,
165900  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_173_WIDTH },
165901  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_CHECKER_TYPE,
165902  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_174_WIDTH },
165903  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_CHECKER_TYPE,
165904  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_175_WIDTH },
165905  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_CHECKER_TYPE,
165906  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_176_WIDTH },
165907  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_CHECKER_TYPE,
165908  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_177_WIDTH },
165909  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_CHECKER_TYPE,
165910  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_178_WIDTH },
165911  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_CHECKER_TYPE,
165912  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_179_WIDTH },
165913  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_CHECKER_TYPE,
165914  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_180_WIDTH },
165915  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_CHECKER_TYPE,
165916  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_181_WIDTH },
165917  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_CHECKER_TYPE,
165918  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_182_WIDTH },
165919  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_CHECKER_TYPE,
165920  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_183_WIDTH },
165921  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_CHECKER_TYPE,
165922  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_184_WIDTH },
165923  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_CHECKER_TYPE,
165924  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_185_WIDTH },
165925  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_CHECKER_TYPE,
165926  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_186_WIDTH },
165927  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_CHECKER_TYPE,
165928  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_187_WIDTH },
165929  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_CHECKER_TYPE,
165930  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_188_WIDTH },
165931  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_CHECKER_TYPE,
165932  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_189_WIDTH },
165933  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_CHECKER_TYPE,
165934  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_190_WIDTH },
165935  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_CHECKER_TYPE,
165936  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_191_WIDTH },
165937  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_CHECKER_TYPE,
165938  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_192_WIDTH },
165939  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_CHECKER_TYPE,
165940  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_193_WIDTH },
165941  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_CHECKER_TYPE,
165942  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_194_WIDTH },
165943  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_CHECKER_TYPE,
165944  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_195_WIDTH },
165945  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_CHECKER_TYPE,
165946  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_196_WIDTH },
165947  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_CHECKER_TYPE,
165948  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_197_WIDTH },
165949  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_CHECKER_TYPE,
165950  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_198_WIDTH },
165951  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_CHECKER_TYPE,
165952  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_199_WIDTH },
165953  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_CHECKER_TYPE,
165954  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_200_WIDTH },
165955  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_CHECKER_TYPE,
165956  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_201_WIDTH },
165957  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_CHECKER_TYPE,
165958  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_202_WIDTH },
165959  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_CHECKER_TYPE,
165960  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_203_WIDTH },
165961  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_CHECKER_TYPE,
165962  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_204_WIDTH },
165963  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_CHECKER_TYPE,
165964  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_205_WIDTH },
165965  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_CHECKER_TYPE,
165966  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_206_WIDTH },
165967  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_CHECKER_TYPE,
165968  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_207_WIDTH },
165969  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_CHECKER_TYPE,
165970  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_208_WIDTH },
165971  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_CHECKER_TYPE,
165972  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_209_WIDTH },
165973  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_CHECKER_TYPE,
165974  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_210_WIDTH },
165975  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_CHECKER_TYPE,
165976  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_211_WIDTH },
165977  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_CHECKER_TYPE,
165978  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_212_WIDTH },
165979  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_CHECKER_TYPE,
165980  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_213_WIDTH },
165981  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_CHECKER_TYPE,
165982  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_214_WIDTH },
165983  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_CHECKER_TYPE,
165984  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_215_WIDTH },
165985  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_CHECKER_TYPE,
165986  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_216_WIDTH },
165987  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_CHECKER_TYPE,
165988  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_217_WIDTH },
165989  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_CHECKER_TYPE,
165990  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_218_WIDTH },
165991  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_CHECKER_TYPE,
165992  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_219_WIDTH },
165993  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_CHECKER_TYPE,
165994  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_220_WIDTH },
165995  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_CHECKER_TYPE,
165996  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_221_WIDTH },
165997  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_CHECKER_TYPE,
165998  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_222_WIDTH },
165999  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_CHECKER_TYPE,
166000  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_223_WIDTH },
166001  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_CHECKER_TYPE,
166002  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_224_WIDTH },
166003  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_CHECKER_TYPE,
166004  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_225_WIDTH },
166005  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_CHECKER_TYPE,
166006  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_226_WIDTH },
166007  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_CHECKER_TYPE,
166008  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_227_WIDTH },
166009  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_CHECKER_TYPE,
166010  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_228_WIDTH },
166011  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_CHECKER_TYPE,
166012  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_229_WIDTH },
166013  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_CHECKER_TYPE,
166014  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_230_WIDTH },
166015  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_CHECKER_TYPE,
166016  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_231_WIDTH },
166017  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_CHECKER_TYPE,
166018  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_232_WIDTH },
166019  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_CHECKER_TYPE,
166020  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_233_WIDTH },
166021  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_CHECKER_TYPE,
166022  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_234_WIDTH },
166023  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_CHECKER_TYPE,
166024  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_235_WIDTH },
166025  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_CHECKER_TYPE,
166026  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_236_WIDTH },
166027  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_CHECKER_TYPE,
166028  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_237_WIDTH },
166029  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_CHECKER_TYPE,
166030  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_238_WIDTH },
166031  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_CHECKER_TYPE,
166032  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_239_WIDTH },
166033  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_CHECKER_TYPE,
166034  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_240_WIDTH },
166035  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_CHECKER_TYPE,
166036  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_241_WIDTH },
166037  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_CHECKER_TYPE,
166038  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_242_WIDTH },
166039  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_CHECKER_TYPE,
166040  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_243_WIDTH },
166041  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_CHECKER_TYPE,
166042  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_244_WIDTH },
166043  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_CHECKER_TYPE,
166044  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_245_WIDTH },
166045  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_CHECKER_TYPE,
166046  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_246_WIDTH },
166047  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_CHECKER_TYPE,
166048  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_247_WIDTH },
166049  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_CHECKER_TYPE,
166050  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_248_WIDTH },
166051  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_CHECKER_TYPE,
166052  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_249_WIDTH },
166053  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_CHECKER_TYPE,
166054  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_250_WIDTH },
166055  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_CHECKER_TYPE,
166056  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_251_WIDTH },
166057  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_CHECKER_TYPE,
166058  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_252_WIDTH },
166059  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_CHECKER_TYPE,
166060  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_253_WIDTH },
166061  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_CHECKER_TYPE,
166062  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_254_WIDTH },
166063  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_CHECKER_TYPE,
166064  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_GROUP_255_WIDTH },
166065 };
166066 
166072 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS] =
166073 {
166074  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_CHECKER_TYPE,
166075  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_0_WIDTH },
166076  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_CHECKER_TYPE,
166077  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_1_WIDTH },
166078  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_CHECKER_TYPE,
166079  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_2_WIDTH },
166080  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_CHECKER_TYPE,
166081  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_3_WIDTH },
166082  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_CHECKER_TYPE,
166083  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_4_WIDTH },
166084  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_CHECKER_TYPE,
166085  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_5_WIDTH },
166086  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_CHECKER_TYPE,
166087  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_6_WIDTH },
166088  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_CHECKER_TYPE,
166089  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_7_WIDTH },
166090  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_CHECKER_TYPE,
166091  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_8_WIDTH },
166092  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_CHECKER_TYPE,
166093  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_9_WIDTH },
166094  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_CHECKER_TYPE,
166095  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_10_WIDTH },
166096  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_CHECKER_TYPE,
166097  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_11_WIDTH },
166098  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_CHECKER_TYPE,
166099  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_12_WIDTH },
166100  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_CHECKER_TYPE,
166101  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_13_WIDTH },
166102  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_CHECKER_TYPE,
166103  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_14_WIDTH },
166104  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_CHECKER_TYPE,
166105  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_15_WIDTH },
166106  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_CHECKER_TYPE,
166107  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_16_WIDTH },
166108  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_CHECKER_TYPE,
166109  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_17_WIDTH },
166110  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_CHECKER_TYPE,
166111  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_18_WIDTH },
166112  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_CHECKER_TYPE,
166113  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_19_WIDTH },
166114  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_CHECKER_TYPE,
166115  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_20_WIDTH },
166116  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_CHECKER_TYPE,
166117  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_21_WIDTH },
166118  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_CHECKER_TYPE,
166119  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_22_WIDTH },
166120  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_CHECKER_TYPE,
166121  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_23_WIDTH },
166122  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_CHECKER_TYPE,
166123  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_24_WIDTH },
166124  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_CHECKER_TYPE,
166125  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_25_WIDTH },
166126  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_CHECKER_TYPE,
166127  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_26_WIDTH },
166128  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_CHECKER_TYPE,
166129  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_27_WIDTH },
166130  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_CHECKER_TYPE,
166131  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_28_WIDTH },
166132  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_CHECKER_TYPE,
166133  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_29_WIDTH },
166134  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_CHECKER_TYPE,
166135  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_30_WIDTH },
166136  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_CHECKER_TYPE,
166137  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_31_WIDTH },
166138  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_CHECKER_TYPE,
166139  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_32_WIDTH },
166140  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_CHECKER_TYPE,
166141  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_33_WIDTH },
166142  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_CHECKER_TYPE,
166143  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_34_WIDTH },
166144  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_CHECKER_TYPE,
166145  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_35_WIDTH },
166146  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_CHECKER_TYPE,
166147  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_36_WIDTH },
166148  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_CHECKER_TYPE,
166149  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_37_WIDTH },
166150  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_CHECKER_TYPE,
166151  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_38_WIDTH },
166152  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_CHECKER_TYPE,
166153  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_39_WIDTH },
166154  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_CHECKER_TYPE,
166155  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_40_WIDTH },
166156  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_CHECKER_TYPE,
166157  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_41_WIDTH },
166158  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_CHECKER_TYPE,
166159  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_42_WIDTH },
166160  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_CHECKER_TYPE,
166161  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_43_WIDTH },
166162  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_CHECKER_TYPE,
166163  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_44_WIDTH },
166164  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_CHECKER_TYPE,
166165  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_45_WIDTH },
166166  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_CHECKER_TYPE,
166167  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_46_WIDTH },
166168  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_CHECKER_TYPE,
166169  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_47_WIDTH },
166170  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_CHECKER_TYPE,
166171  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_48_WIDTH },
166172  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_CHECKER_TYPE,
166173  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_49_WIDTH },
166174  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_CHECKER_TYPE,
166175  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_50_WIDTH },
166176  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_CHECKER_TYPE,
166177  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_51_WIDTH },
166178  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_CHECKER_TYPE,
166179  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_52_WIDTH },
166180  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_CHECKER_TYPE,
166181  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_53_WIDTH },
166182  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_CHECKER_TYPE,
166183  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_54_WIDTH },
166184  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_CHECKER_TYPE,
166185  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_55_WIDTH },
166186  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_CHECKER_TYPE,
166187  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_56_WIDTH },
166188  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_CHECKER_TYPE,
166189  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_57_WIDTH },
166190  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_CHECKER_TYPE,
166191  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_58_WIDTH },
166192  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_CHECKER_TYPE,
166193  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_59_WIDTH },
166194  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_CHECKER_TYPE,
166195  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_60_WIDTH },
166196  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_CHECKER_TYPE,
166197  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_61_WIDTH },
166198  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_CHECKER_TYPE,
166199  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_62_WIDTH },
166200  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_CHECKER_TYPE,
166201  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_63_WIDTH },
166202  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_CHECKER_TYPE,
166203  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_64_WIDTH },
166204  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_CHECKER_TYPE,
166205  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_65_WIDTH },
166206  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_CHECKER_TYPE,
166207  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_66_WIDTH },
166208  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_CHECKER_TYPE,
166209  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_67_WIDTH },
166210  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_CHECKER_TYPE,
166211  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_68_WIDTH },
166212  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_CHECKER_TYPE,
166213  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_69_WIDTH },
166214  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_CHECKER_TYPE,
166215  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_70_WIDTH },
166216  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_CHECKER_TYPE,
166217  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_71_WIDTH },
166218  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_CHECKER_TYPE,
166219  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_72_WIDTH },
166220  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_CHECKER_TYPE,
166221  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_73_WIDTH },
166222  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_CHECKER_TYPE,
166223  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_74_WIDTH },
166224  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_CHECKER_TYPE,
166225  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_75_WIDTH },
166226  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_CHECKER_TYPE,
166227  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_76_WIDTH },
166228  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_CHECKER_TYPE,
166229  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_77_WIDTH },
166230  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_CHECKER_TYPE,
166231  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_78_WIDTH },
166232  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_CHECKER_TYPE,
166233  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_79_WIDTH },
166234  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_CHECKER_TYPE,
166235  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_80_WIDTH },
166236  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_CHECKER_TYPE,
166237  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_81_WIDTH },
166238  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_CHECKER_TYPE,
166239  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_82_WIDTH },
166240  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_CHECKER_TYPE,
166241  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_83_WIDTH },
166242  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_CHECKER_TYPE,
166243  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_84_WIDTH },
166244  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_CHECKER_TYPE,
166245  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_85_WIDTH },
166246  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_CHECKER_TYPE,
166247  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_86_WIDTH },
166248  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_CHECKER_TYPE,
166249  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_87_WIDTH },
166250  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_CHECKER_TYPE,
166251  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_88_WIDTH },
166252  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_CHECKER_TYPE,
166253  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_89_WIDTH },
166254  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_CHECKER_TYPE,
166255  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_90_WIDTH },
166256  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_CHECKER_TYPE,
166257  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_91_WIDTH },
166258  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_CHECKER_TYPE,
166259  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_92_WIDTH },
166260  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_CHECKER_TYPE,
166261  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_93_WIDTH },
166262  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_CHECKER_TYPE,
166263  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_94_WIDTH },
166264  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_CHECKER_TYPE,
166265  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_95_WIDTH },
166266  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_CHECKER_TYPE,
166267  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_96_WIDTH },
166268  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_CHECKER_TYPE,
166269  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_97_WIDTH },
166270  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_CHECKER_TYPE,
166271  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_98_WIDTH },
166272  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_CHECKER_TYPE,
166273  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_99_WIDTH },
166274  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_CHECKER_TYPE,
166275  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_100_WIDTH },
166276  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_CHECKER_TYPE,
166277  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_101_WIDTH },
166278  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_CHECKER_TYPE,
166279  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_102_WIDTH },
166280  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_CHECKER_TYPE,
166281  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_103_WIDTH },
166282  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_CHECKER_TYPE,
166283  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_104_WIDTH },
166284  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_CHECKER_TYPE,
166285  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_105_WIDTH },
166286  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_CHECKER_TYPE,
166287  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_106_WIDTH },
166288  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_CHECKER_TYPE,
166289  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_107_WIDTH },
166290  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_CHECKER_TYPE,
166291  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_108_WIDTH },
166292  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_CHECKER_TYPE,
166293  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_109_WIDTH },
166294  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_CHECKER_TYPE,
166295  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_110_WIDTH },
166296  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_CHECKER_TYPE,
166297  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_111_WIDTH },
166298  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_CHECKER_TYPE,
166299  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_112_WIDTH },
166300  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_CHECKER_TYPE,
166301  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_113_WIDTH },
166302  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_CHECKER_TYPE,
166303  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_114_WIDTH },
166304  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_CHECKER_TYPE,
166305  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_115_WIDTH },
166306  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_CHECKER_TYPE,
166307  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_116_WIDTH },
166308  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_CHECKER_TYPE,
166309  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_117_WIDTH },
166310  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_CHECKER_TYPE,
166311  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_118_WIDTH },
166312  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_CHECKER_TYPE,
166313  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_119_WIDTH },
166314  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_CHECKER_TYPE,
166315  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_120_WIDTH },
166316  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_CHECKER_TYPE,
166317  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_121_WIDTH },
166318  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_CHECKER_TYPE,
166319  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_122_WIDTH },
166320  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_CHECKER_TYPE,
166321  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_123_WIDTH },
166322  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_CHECKER_TYPE,
166323  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_124_WIDTH },
166324  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_CHECKER_TYPE,
166325  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_125_WIDTH },
166326  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_CHECKER_TYPE,
166327  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_126_WIDTH },
166328  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_CHECKER_TYPE,
166329  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_127_WIDTH },
166330  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_CHECKER_TYPE,
166331  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_128_WIDTH },
166332  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_CHECKER_TYPE,
166333  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_129_WIDTH },
166334  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_CHECKER_TYPE,
166335  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_130_WIDTH },
166336  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_CHECKER_TYPE,
166337  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_131_WIDTH },
166338  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_CHECKER_TYPE,
166339  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_132_WIDTH },
166340  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_CHECKER_TYPE,
166341  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_133_WIDTH },
166342  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_CHECKER_TYPE,
166343  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_134_WIDTH },
166344  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_CHECKER_TYPE,
166345  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_135_WIDTH },
166346  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_CHECKER_TYPE,
166347  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_136_WIDTH },
166348  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_CHECKER_TYPE,
166349  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_137_WIDTH },
166350  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_CHECKER_TYPE,
166351  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_138_WIDTH },
166352  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_CHECKER_TYPE,
166353  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_139_WIDTH },
166354  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_CHECKER_TYPE,
166355  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_140_WIDTH },
166356  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_CHECKER_TYPE,
166357  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_141_WIDTH },
166358  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_CHECKER_TYPE,
166359  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_142_WIDTH },
166360  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_CHECKER_TYPE,
166361  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_143_WIDTH },
166362  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_CHECKER_TYPE,
166363  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_144_WIDTH },
166364  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_CHECKER_TYPE,
166365  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_145_WIDTH },
166366  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_CHECKER_TYPE,
166367  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_146_WIDTH },
166368  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_CHECKER_TYPE,
166369  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_147_WIDTH },
166370  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_CHECKER_TYPE,
166371  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_148_WIDTH },
166372  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_CHECKER_TYPE,
166373  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_149_WIDTH },
166374  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_CHECKER_TYPE,
166375  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_150_WIDTH },
166376  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_CHECKER_TYPE,
166377  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_151_WIDTH },
166378  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_CHECKER_TYPE,
166379  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_152_WIDTH },
166380  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_CHECKER_TYPE,
166381  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_153_WIDTH },
166382  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_CHECKER_TYPE,
166383  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_154_WIDTH },
166384  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_CHECKER_TYPE,
166385  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_155_WIDTH },
166386  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_CHECKER_TYPE,
166387  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_156_WIDTH },
166388  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_CHECKER_TYPE,
166389  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_157_WIDTH },
166390  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_CHECKER_TYPE,
166391  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_158_WIDTH },
166392  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_CHECKER_TYPE,
166393  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_159_WIDTH },
166394  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_CHECKER_TYPE,
166395  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_160_WIDTH },
166396  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_CHECKER_TYPE,
166397  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_161_WIDTH },
166398  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_CHECKER_TYPE,
166399  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_162_WIDTH },
166400  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_CHECKER_TYPE,
166401  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_163_WIDTH },
166402  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_CHECKER_TYPE,
166403  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_164_WIDTH },
166404  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_CHECKER_TYPE,
166405  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_165_WIDTH },
166406  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_CHECKER_TYPE,
166407  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_166_WIDTH },
166408  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_CHECKER_TYPE,
166409  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_167_WIDTH },
166410  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_CHECKER_TYPE,
166411  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_168_WIDTH },
166412  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_CHECKER_TYPE,
166413  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_169_WIDTH },
166414  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_CHECKER_TYPE,
166415  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_170_WIDTH },
166416  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_CHECKER_TYPE,
166417  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_171_WIDTH },
166418  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_CHECKER_TYPE,
166419  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_172_WIDTH },
166420  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_CHECKER_TYPE,
166421  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_173_WIDTH },
166422  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_CHECKER_TYPE,
166423  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_174_WIDTH },
166424  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_CHECKER_TYPE,
166425  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_175_WIDTH },
166426  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_CHECKER_TYPE,
166427  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_176_WIDTH },
166428  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_CHECKER_TYPE,
166429  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_177_WIDTH },
166430  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_CHECKER_TYPE,
166431  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_178_WIDTH },
166432  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_CHECKER_TYPE,
166433  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_179_WIDTH },
166434  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_CHECKER_TYPE,
166435  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_180_WIDTH },
166436  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_CHECKER_TYPE,
166437  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_181_WIDTH },
166438  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_CHECKER_TYPE,
166439  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_182_WIDTH },
166440  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_CHECKER_TYPE,
166441  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_183_WIDTH },
166442  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_CHECKER_TYPE,
166443  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_184_WIDTH },
166444  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_CHECKER_TYPE,
166445  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_185_WIDTH },
166446  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_CHECKER_TYPE,
166447  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_186_WIDTH },
166448  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_CHECKER_TYPE,
166449  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_187_WIDTH },
166450  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_CHECKER_TYPE,
166451  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_188_WIDTH },
166452  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_CHECKER_TYPE,
166453  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_189_WIDTH },
166454  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_CHECKER_TYPE,
166455  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_190_WIDTH },
166456  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_CHECKER_TYPE,
166457  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_191_WIDTH },
166458  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_CHECKER_TYPE,
166459  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_192_WIDTH },
166460  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_CHECKER_TYPE,
166461  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_193_WIDTH },
166462  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_CHECKER_TYPE,
166463  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_194_WIDTH },
166464  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_CHECKER_TYPE,
166465  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_195_WIDTH },
166466  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_CHECKER_TYPE,
166467  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_196_WIDTH },
166468  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_CHECKER_TYPE,
166469  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_197_WIDTH },
166470  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_CHECKER_TYPE,
166471  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_198_WIDTH },
166472  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_CHECKER_TYPE,
166473  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_199_WIDTH },
166474  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_CHECKER_TYPE,
166475  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_200_WIDTH },
166476  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_CHECKER_TYPE,
166477  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_201_WIDTH },
166478  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_CHECKER_TYPE,
166479  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_202_WIDTH },
166480  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_CHECKER_TYPE,
166481  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_203_WIDTH },
166482  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_CHECKER_TYPE,
166483  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_204_WIDTH },
166484  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_CHECKER_TYPE,
166485  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_205_WIDTH },
166486  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_CHECKER_TYPE,
166487  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_206_WIDTH },
166488  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_CHECKER_TYPE,
166489  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_207_WIDTH },
166490  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_CHECKER_TYPE,
166491  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_208_WIDTH },
166492  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_CHECKER_TYPE,
166493  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_209_WIDTH },
166494  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_CHECKER_TYPE,
166495  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_210_WIDTH },
166496  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_CHECKER_TYPE,
166497  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_211_WIDTH },
166498  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_CHECKER_TYPE,
166499  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_212_WIDTH },
166500  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_CHECKER_TYPE,
166501  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_213_WIDTH },
166502  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_CHECKER_TYPE,
166503  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_214_WIDTH },
166504  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_CHECKER_TYPE,
166505  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_215_WIDTH },
166506  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_CHECKER_TYPE,
166507  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_216_WIDTH },
166508  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_CHECKER_TYPE,
166509  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_217_WIDTH },
166510  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_CHECKER_TYPE,
166511  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_218_WIDTH },
166512  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_CHECKER_TYPE,
166513  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_219_WIDTH },
166514  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_CHECKER_TYPE,
166515  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_220_WIDTH },
166516  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_CHECKER_TYPE,
166517  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_221_WIDTH },
166518  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_CHECKER_TYPE,
166519  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_222_WIDTH },
166520  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_CHECKER_TYPE,
166521  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_223_WIDTH },
166522  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_CHECKER_TYPE,
166523  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_224_WIDTH },
166524  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_CHECKER_TYPE,
166525  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_225_WIDTH },
166526  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_CHECKER_TYPE,
166527  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_226_WIDTH },
166528  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_CHECKER_TYPE,
166529  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_227_WIDTH },
166530  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_CHECKER_TYPE,
166531  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_228_WIDTH },
166532  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_CHECKER_TYPE,
166533  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_229_WIDTH },
166534  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_CHECKER_TYPE,
166535  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_230_WIDTH },
166536  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_CHECKER_TYPE,
166537  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_231_WIDTH },
166538  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_CHECKER_TYPE,
166539  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_232_WIDTH },
166540  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_CHECKER_TYPE,
166541  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_233_WIDTH },
166542  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_CHECKER_TYPE,
166543  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_234_WIDTH },
166544  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_CHECKER_TYPE,
166545  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_235_WIDTH },
166546  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_CHECKER_TYPE,
166547  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_236_WIDTH },
166548  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_CHECKER_TYPE,
166549  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_237_WIDTH },
166550  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_CHECKER_TYPE,
166551  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_238_WIDTH },
166552  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_CHECKER_TYPE,
166553  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_239_WIDTH },
166554  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_CHECKER_TYPE,
166555  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_240_WIDTH },
166556  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_CHECKER_TYPE,
166557  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_241_WIDTH },
166558  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_CHECKER_TYPE,
166559  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_242_WIDTH },
166560  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_CHECKER_TYPE,
166561  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_243_WIDTH },
166562  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_CHECKER_TYPE,
166563  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_244_WIDTH },
166564  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_CHECKER_TYPE,
166565  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_245_WIDTH },
166566  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_CHECKER_TYPE,
166567  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_246_WIDTH },
166568  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_CHECKER_TYPE,
166569  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_247_WIDTH },
166570  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_CHECKER_TYPE,
166571  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_248_WIDTH },
166572  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_CHECKER_TYPE,
166573  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_249_WIDTH },
166574  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_CHECKER_TYPE,
166575  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_250_WIDTH },
166576  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_CHECKER_TYPE,
166577  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_251_WIDTH },
166578  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_CHECKER_TYPE,
166579  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_252_WIDTH },
166580  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_CHECKER_TYPE,
166581  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_253_WIDTH },
166582  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_CHECKER_TYPE,
166583  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_254_WIDTH },
166584  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_CHECKER_TYPE,
166585  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_GROUP_255_WIDTH },
166586 };
166587 
166593 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS] =
166594 {
166595  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_CHECKER_TYPE,
166596  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_0_WIDTH },
166597  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_CHECKER_TYPE,
166598  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_1_WIDTH },
166599  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_CHECKER_TYPE,
166600  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_2_WIDTH },
166601  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_CHECKER_TYPE,
166602  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_3_WIDTH },
166603  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_CHECKER_TYPE,
166604  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_4_WIDTH },
166605  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_CHECKER_TYPE,
166606  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_5_WIDTH },
166607  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_CHECKER_TYPE,
166608  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_6_WIDTH },
166609  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_CHECKER_TYPE,
166610  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_7_WIDTH },
166611  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_CHECKER_TYPE,
166612  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_8_WIDTH },
166613  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_CHECKER_TYPE,
166614  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_9_WIDTH },
166615  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_CHECKER_TYPE,
166616  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_10_WIDTH },
166617  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_CHECKER_TYPE,
166618  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_11_WIDTH },
166619  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_CHECKER_TYPE,
166620  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_12_WIDTH },
166621  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_CHECKER_TYPE,
166622  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_13_WIDTH },
166623  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_CHECKER_TYPE,
166624  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_14_WIDTH },
166625  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_CHECKER_TYPE,
166626  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_15_WIDTH },
166627  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_CHECKER_TYPE,
166628  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_16_WIDTH },
166629  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_CHECKER_TYPE,
166630  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_17_WIDTH },
166631  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_CHECKER_TYPE,
166632  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_18_WIDTH },
166633  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_CHECKER_TYPE,
166634  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_19_WIDTH },
166635  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_CHECKER_TYPE,
166636  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_20_WIDTH },
166637  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_CHECKER_TYPE,
166638  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_21_WIDTH },
166639  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_CHECKER_TYPE,
166640  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_22_WIDTH },
166641  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_CHECKER_TYPE,
166642  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_23_WIDTH },
166643  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_CHECKER_TYPE,
166644  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_24_WIDTH },
166645  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_CHECKER_TYPE,
166646  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_25_WIDTH },
166647  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_CHECKER_TYPE,
166648  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_26_WIDTH },
166649  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_CHECKER_TYPE,
166650  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_27_WIDTH },
166651  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_CHECKER_TYPE,
166652  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_28_WIDTH },
166653  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_CHECKER_TYPE,
166654  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_29_WIDTH },
166655  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_CHECKER_TYPE,
166656  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_30_WIDTH },
166657  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_CHECKER_TYPE,
166658  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_31_WIDTH },
166659  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_CHECKER_TYPE,
166660  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_32_WIDTH },
166661  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_CHECKER_TYPE,
166662  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_33_WIDTH },
166663  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_CHECKER_TYPE,
166664  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_34_WIDTH },
166665  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_CHECKER_TYPE,
166666  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_35_WIDTH },
166667  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_CHECKER_TYPE,
166668  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_36_WIDTH },
166669  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_CHECKER_TYPE,
166670  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_37_WIDTH },
166671  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_CHECKER_TYPE,
166672  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_38_WIDTH },
166673  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_CHECKER_TYPE,
166674  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_39_WIDTH },
166675  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_CHECKER_TYPE,
166676  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_40_WIDTH },
166677  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_CHECKER_TYPE,
166678  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_41_WIDTH },
166679  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_CHECKER_TYPE,
166680  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_42_WIDTH },
166681  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_CHECKER_TYPE,
166682  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_43_WIDTH },
166683  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_CHECKER_TYPE,
166684  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_44_WIDTH },
166685  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_CHECKER_TYPE,
166686  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_45_WIDTH },
166687  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_CHECKER_TYPE,
166688  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_46_WIDTH },
166689  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_CHECKER_TYPE,
166690  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_47_WIDTH },
166691  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_CHECKER_TYPE,
166692  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_48_WIDTH },
166693  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_CHECKER_TYPE,
166694  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_49_WIDTH },
166695  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_CHECKER_TYPE,
166696  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_50_WIDTH },
166697  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_CHECKER_TYPE,
166698  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_51_WIDTH },
166699  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_CHECKER_TYPE,
166700  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_52_WIDTH },
166701  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_CHECKER_TYPE,
166702  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_53_WIDTH },
166703  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_CHECKER_TYPE,
166704  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_54_WIDTH },
166705  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_CHECKER_TYPE,
166706  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_55_WIDTH },
166707  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_CHECKER_TYPE,
166708  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_56_WIDTH },
166709  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_CHECKER_TYPE,
166710  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_57_WIDTH },
166711  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_CHECKER_TYPE,
166712  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_58_WIDTH },
166713  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_CHECKER_TYPE,
166714  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_59_WIDTH },
166715  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_CHECKER_TYPE,
166716  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_60_WIDTH },
166717  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_CHECKER_TYPE,
166718  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_61_WIDTH },
166719  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_CHECKER_TYPE,
166720  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_62_WIDTH },
166721  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_CHECKER_TYPE,
166722  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_63_WIDTH },
166723  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_CHECKER_TYPE,
166724  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_64_WIDTH },
166725  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_CHECKER_TYPE,
166726  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_65_WIDTH },
166727  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_CHECKER_TYPE,
166728  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_66_WIDTH },
166729  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_CHECKER_TYPE,
166730  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_67_WIDTH },
166731  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_CHECKER_TYPE,
166732  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_68_WIDTH },
166733  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_CHECKER_TYPE,
166734  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_69_WIDTH },
166735  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_CHECKER_TYPE,
166736  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_70_WIDTH },
166737  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_CHECKER_TYPE,
166738  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_71_WIDTH },
166739  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_CHECKER_TYPE,
166740  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_72_WIDTH },
166741  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_CHECKER_TYPE,
166742  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_73_WIDTH },
166743  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_CHECKER_TYPE,
166744  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_74_WIDTH },
166745  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_CHECKER_TYPE,
166746  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_75_WIDTH },
166747  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_CHECKER_TYPE,
166748  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_76_WIDTH },
166749  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_CHECKER_TYPE,
166750  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_77_WIDTH },
166751  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_CHECKER_TYPE,
166752  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_78_WIDTH },
166753  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_CHECKER_TYPE,
166754  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_79_WIDTH },
166755  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_CHECKER_TYPE,
166756  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_80_WIDTH },
166757  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_CHECKER_TYPE,
166758  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_81_WIDTH },
166759  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_CHECKER_TYPE,
166760  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_82_WIDTH },
166761  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_CHECKER_TYPE,
166762  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_83_WIDTH },
166763  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_CHECKER_TYPE,
166764  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_84_WIDTH },
166765  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_CHECKER_TYPE,
166766  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_85_WIDTH },
166767  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_CHECKER_TYPE,
166768  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_86_WIDTH },
166769  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_CHECKER_TYPE,
166770  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_87_WIDTH },
166771  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_CHECKER_TYPE,
166772  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_88_WIDTH },
166773  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_CHECKER_TYPE,
166774  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_89_WIDTH },
166775  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_CHECKER_TYPE,
166776  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_90_WIDTH },
166777  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_CHECKER_TYPE,
166778  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_91_WIDTH },
166779  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_CHECKER_TYPE,
166780  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_92_WIDTH },
166781  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_CHECKER_TYPE,
166782  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_93_WIDTH },
166783  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_CHECKER_TYPE,
166784  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_94_WIDTH },
166785  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_CHECKER_TYPE,
166786  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_95_WIDTH },
166787  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_CHECKER_TYPE,
166788  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_96_WIDTH },
166789  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_CHECKER_TYPE,
166790  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_97_WIDTH },
166791  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_CHECKER_TYPE,
166792  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_98_WIDTH },
166793  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_CHECKER_TYPE,
166794  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_99_WIDTH },
166795  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_CHECKER_TYPE,
166796  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_100_WIDTH },
166797  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_CHECKER_TYPE,
166798  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_101_WIDTH },
166799  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_CHECKER_TYPE,
166800  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_102_WIDTH },
166801  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_CHECKER_TYPE,
166802  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_103_WIDTH },
166803  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_CHECKER_TYPE,
166804  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_104_WIDTH },
166805  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_CHECKER_TYPE,
166806  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_105_WIDTH },
166807  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_CHECKER_TYPE,
166808  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_106_WIDTH },
166809  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_CHECKER_TYPE,
166810  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_107_WIDTH },
166811  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_CHECKER_TYPE,
166812  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_108_WIDTH },
166813  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_CHECKER_TYPE,
166814  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_109_WIDTH },
166815  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_CHECKER_TYPE,
166816  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_110_WIDTH },
166817  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_CHECKER_TYPE,
166818  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_111_WIDTH },
166819  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_CHECKER_TYPE,
166820  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_112_WIDTH },
166821  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_CHECKER_TYPE,
166822  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_113_WIDTH },
166823  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_CHECKER_TYPE,
166824  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_114_WIDTH },
166825  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_CHECKER_TYPE,
166826  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_115_WIDTH },
166827  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_CHECKER_TYPE,
166828  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_116_WIDTH },
166829  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_CHECKER_TYPE,
166830  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_117_WIDTH },
166831  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_CHECKER_TYPE,
166832  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_118_WIDTH },
166833  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_CHECKER_TYPE,
166834  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_119_WIDTH },
166835  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_CHECKER_TYPE,
166836  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_120_WIDTH },
166837  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_CHECKER_TYPE,
166838  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_121_WIDTH },
166839  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_CHECKER_TYPE,
166840  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_122_WIDTH },
166841  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_CHECKER_TYPE,
166842  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_123_WIDTH },
166843  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_CHECKER_TYPE,
166844  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_124_WIDTH },
166845  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_CHECKER_TYPE,
166846  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_125_WIDTH },
166847  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_CHECKER_TYPE,
166848  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_126_WIDTH },
166849  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_CHECKER_TYPE,
166850  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_127_WIDTH },
166851  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_CHECKER_TYPE,
166852  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_128_WIDTH },
166853  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_CHECKER_TYPE,
166854  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_129_WIDTH },
166855  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_CHECKER_TYPE,
166856  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_130_WIDTH },
166857  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_CHECKER_TYPE,
166858  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_131_WIDTH },
166859  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_CHECKER_TYPE,
166860  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_132_WIDTH },
166861  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_CHECKER_TYPE,
166862  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_133_WIDTH },
166863  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_CHECKER_TYPE,
166864  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_134_WIDTH },
166865  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_CHECKER_TYPE,
166866  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_135_WIDTH },
166867  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_CHECKER_TYPE,
166868  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_136_WIDTH },
166869  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_CHECKER_TYPE,
166870  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_137_WIDTH },
166871  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_CHECKER_TYPE,
166872  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_138_WIDTH },
166873  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_CHECKER_TYPE,
166874  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_139_WIDTH },
166875  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_CHECKER_TYPE,
166876  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_140_WIDTH },
166877  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_CHECKER_TYPE,
166878  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_141_WIDTH },
166879  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_CHECKER_TYPE,
166880  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_142_WIDTH },
166881  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_CHECKER_TYPE,
166882  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_143_WIDTH },
166883  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_CHECKER_TYPE,
166884  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_144_WIDTH },
166885  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_CHECKER_TYPE,
166886  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_145_WIDTH },
166887  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_CHECKER_TYPE,
166888  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_146_WIDTH },
166889  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_CHECKER_TYPE,
166890  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_147_WIDTH },
166891  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_CHECKER_TYPE,
166892  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_148_WIDTH },
166893  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_CHECKER_TYPE,
166894  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_149_WIDTH },
166895  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_CHECKER_TYPE,
166896  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_150_WIDTH },
166897  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_CHECKER_TYPE,
166898  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_151_WIDTH },
166899  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_CHECKER_TYPE,
166900  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_152_WIDTH },
166901  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_CHECKER_TYPE,
166902  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_153_WIDTH },
166903  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_CHECKER_TYPE,
166904  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_154_WIDTH },
166905  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_CHECKER_TYPE,
166906  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_155_WIDTH },
166907  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_CHECKER_TYPE,
166908  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_156_WIDTH },
166909  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_CHECKER_TYPE,
166910  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_157_WIDTH },
166911  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_CHECKER_TYPE,
166912  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_158_WIDTH },
166913  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_CHECKER_TYPE,
166914  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_159_WIDTH },
166915  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_CHECKER_TYPE,
166916  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_160_WIDTH },
166917  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_CHECKER_TYPE,
166918  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_161_WIDTH },
166919  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_CHECKER_TYPE,
166920  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_162_WIDTH },
166921  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_CHECKER_TYPE,
166922  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_163_WIDTH },
166923  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_CHECKER_TYPE,
166924  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_164_WIDTH },
166925  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_CHECKER_TYPE,
166926  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_165_WIDTH },
166927  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_CHECKER_TYPE,
166928  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_166_WIDTH },
166929  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_CHECKER_TYPE,
166930  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_167_WIDTH },
166931  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_CHECKER_TYPE,
166932  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_168_WIDTH },
166933  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_CHECKER_TYPE,
166934  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_169_WIDTH },
166935  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_CHECKER_TYPE,
166936  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_170_WIDTH },
166937  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_CHECKER_TYPE,
166938  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_171_WIDTH },
166939  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_CHECKER_TYPE,
166940  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_172_WIDTH },
166941  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_CHECKER_TYPE,
166942  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_173_WIDTH },
166943  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_CHECKER_TYPE,
166944  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_174_WIDTH },
166945  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_CHECKER_TYPE,
166946  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_175_WIDTH },
166947  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_CHECKER_TYPE,
166948  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_176_WIDTH },
166949  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_CHECKER_TYPE,
166950  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_177_WIDTH },
166951  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_CHECKER_TYPE,
166952  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_178_WIDTH },
166953  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_CHECKER_TYPE,
166954  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_179_WIDTH },
166955  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_CHECKER_TYPE,
166956  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_180_WIDTH },
166957  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_CHECKER_TYPE,
166958  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_181_WIDTH },
166959  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_CHECKER_TYPE,
166960  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_182_WIDTH },
166961  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_CHECKER_TYPE,
166962  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_183_WIDTH },
166963  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_CHECKER_TYPE,
166964  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_184_WIDTH },
166965  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_CHECKER_TYPE,
166966  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_185_WIDTH },
166967  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_CHECKER_TYPE,
166968  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_186_WIDTH },
166969  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_CHECKER_TYPE,
166970  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_187_WIDTH },
166971  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_CHECKER_TYPE,
166972  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_188_WIDTH },
166973  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_CHECKER_TYPE,
166974  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_189_WIDTH },
166975  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_CHECKER_TYPE,
166976  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_190_WIDTH },
166977  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_CHECKER_TYPE,
166978  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_191_WIDTH },
166979  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_CHECKER_TYPE,
166980  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_192_WIDTH },
166981  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_CHECKER_TYPE,
166982  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_193_WIDTH },
166983  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_CHECKER_TYPE,
166984  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_194_WIDTH },
166985  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_CHECKER_TYPE,
166986  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_195_WIDTH },
166987  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_CHECKER_TYPE,
166988  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_196_WIDTH },
166989  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_CHECKER_TYPE,
166990  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_197_WIDTH },
166991  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_CHECKER_TYPE,
166992  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_198_WIDTH },
166993  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_CHECKER_TYPE,
166994  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_199_WIDTH },
166995  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_CHECKER_TYPE,
166996  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_200_WIDTH },
166997  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_CHECKER_TYPE,
166998  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_201_WIDTH },
166999  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_CHECKER_TYPE,
167000  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_202_WIDTH },
167001  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_CHECKER_TYPE,
167002  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_203_WIDTH },
167003  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_CHECKER_TYPE,
167004  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_204_WIDTH },
167005  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_CHECKER_TYPE,
167006  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_205_WIDTH },
167007  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_CHECKER_TYPE,
167008  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_206_WIDTH },
167009  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_CHECKER_TYPE,
167010  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_207_WIDTH },
167011  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_CHECKER_TYPE,
167012  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_208_WIDTH },
167013  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_CHECKER_TYPE,
167014  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_209_WIDTH },
167015  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_CHECKER_TYPE,
167016  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_210_WIDTH },
167017  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_CHECKER_TYPE,
167018  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_211_WIDTH },
167019  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_CHECKER_TYPE,
167020  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_212_WIDTH },
167021  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_CHECKER_TYPE,
167022  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_213_WIDTH },
167023  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_CHECKER_TYPE,
167024  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_214_WIDTH },
167025  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_CHECKER_TYPE,
167026  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_215_WIDTH },
167027  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_CHECKER_TYPE,
167028  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_216_WIDTH },
167029  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_CHECKER_TYPE,
167030  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_217_WIDTH },
167031  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_CHECKER_TYPE,
167032  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_218_WIDTH },
167033  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_CHECKER_TYPE,
167034  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_219_WIDTH },
167035  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_CHECKER_TYPE,
167036  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_220_WIDTH },
167037  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_CHECKER_TYPE,
167038  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_221_WIDTH },
167039  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_CHECKER_TYPE,
167040  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_222_WIDTH },
167041  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_CHECKER_TYPE,
167042  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_223_WIDTH },
167043  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_CHECKER_TYPE,
167044  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_224_WIDTH },
167045  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_CHECKER_TYPE,
167046  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_225_WIDTH },
167047  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_CHECKER_TYPE,
167048  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_226_WIDTH },
167049  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_CHECKER_TYPE,
167050  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_227_WIDTH },
167051  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_CHECKER_TYPE,
167052  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_228_WIDTH },
167053  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_CHECKER_TYPE,
167054  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_229_WIDTH },
167055  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_CHECKER_TYPE,
167056  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_230_WIDTH },
167057  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_CHECKER_TYPE,
167058  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_231_WIDTH },
167059  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_CHECKER_TYPE,
167060  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_232_WIDTH },
167061  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_CHECKER_TYPE,
167062  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_233_WIDTH },
167063  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_CHECKER_TYPE,
167064  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_234_WIDTH },
167065  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_CHECKER_TYPE,
167066  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_235_WIDTH },
167067  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_CHECKER_TYPE,
167068  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_236_WIDTH },
167069  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_CHECKER_TYPE,
167070  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_237_WIDTH },
167071  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_CHECKER_TYPE,
167072  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_238_WIDTH },
167073  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_CHECKER_TYPE,
167074  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_239_WIDTH },
167075  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_CHECKER_TYPE,
167076  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_240_WIDTH },
167077  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_CHECKER_TYPE,
167078  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_241_WIDTH },
167079  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_CHECKER_TYPE,
167080  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_242_WIDTH },
167081  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_CHECKER_TYPE,
167082  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_243_WIDTH },
167083  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_CHECKER_TYPE,
167084  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_244_WIDTH },
167085  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_CHECKER_TYPE,
167086  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_245_WIDTH },
167087  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_CHECKER_TYPE,
167088  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_246_WIDTH },
167089  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_CHECKER_TYPE,
167090  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_247_WIDTH },
167091  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_CHECKER_TYPE,
167092  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_248_WIDTH },
167093  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_CHECKER_TYPE,
167094  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_249_WIDTH },
167095  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_CHECKER_TYPE,
167096  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_250_WIDTH },
167097  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_CHECKER_TYPE,
167098  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_251_WIDTH },
167099  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_CHECKER_TYPE,
167100  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_252_WIDTH },
167101  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_CHECKER_TYPE,
167102  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_253_WIDTH },
167103  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_CHECKER_TYPE,
167104  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_254_WIDTH },
167105  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_CHECKER_TYPE,
167106  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_GROUP_255_WIDTH },
167107 };
167108 
167114 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS] =
167115 {
167116  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_CHECKER_TYPE,
167117  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_0_WIDTH },
167118  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_CHECKER_TYPE,
167119  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_1_WIDTH },
167120  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_CHECKER_TYPE,
167121  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_2_WIDTH },
167122  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_CHECKER_TYPE,
167123  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_3_WIDTH },
167124  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_CHECKER_TYPE,
167125  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_4_WIDTH },
167126  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_CHECKER_TYPE,
167127  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_5_WIDTH },
167128  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_CHECKER_TYPE,
167129  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_6_WIDTH },
167130  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_CHECKER_TYPE,
167131  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_7_WIDTH },
167132  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_CHECKER_TYPE,
167133  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_8_WIDTH },
167134  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_CHECKER_TYPE,
167135  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_9_WIDTH },
167136  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_CHECKER_TYPE,
167137  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_10_WIDTH },
167138  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_CHECKER_TYPE,
167139  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_11_WIDTH },
167140  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_CHECKER_TYPE,
167141  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_12_WIDTH },
167142  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_CHECKER_TYPE,
167143  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_13_WIDTH },
167144  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_CHECKER_TYPE,
167145  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_14_WIDTH },
167146  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_CHECKER_TYPE,
167147  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_15_WIDTH },
167148  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_CHECKER_TYPE,
167149  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_16_WIDTH },
167150  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_CHECKER_TYPE,
167151  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_17_WIDTH },
167152  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_CHECKER_TYPE,
167153  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_18_WIDTH },
167154  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_CHECKER_TYPE,
167155  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_19_WIDTH },
167156  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_CHECKER_TYPE,
167157  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_20_WIDTH },
167158  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_CHECKER_TYPE,
167159  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_21_WIDTH },
167160  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_CHECKER_TYPE,
167161  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_22_WIDTH },
167162  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_CHECKER_TYPE,
167163  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_23_WIDTH },
167164  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_CHECKER_TYPE,
167165  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_24_WIDTH },
167166  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_CHECKER_TYPE,
167167  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_25_WIDTH },
167168  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_CHECKER_TYPE,
167169  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_26_WIDTH },
167170  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_CHECKER_TYPE,
167171  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_27_WIDTH },
167172  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_CHECKER_TYPE,
167173  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_28_WIDTH },
167174  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_CHECKER_TYPE,
167175  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_29_WIDTH },
167176  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_CHECKER_TYPE,
167177  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_30_WIDTH },
167178  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_CHECKER_TYPE,
167179  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_31_WIDTH },
167180  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_CHECKER_TYPE,
167181  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_32_WIDTH },
167182  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_CHECKER_TYPE,
167183  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_33_WIDTH },
167184  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_CHECKER_TYPE,
167185  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_34_WIDTH },
167186  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_CHECKER_TYPE,
167187  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_35_WIDTH },
167188  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_CHECKER_TYPE,
167189  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_36_WIDTH },
167190  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_CHECKER_TYPE,
167191  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_37_WIDTH },
167192  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_CHECKER_TYPE,
167193  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_38_WIDTH },
167194  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_CHECKER_TYPE,
167195  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_39_WIDTH },
167196  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_CHECKER_TYPE,
167197  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_40_WIDTH },
167198  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_CHECKER_TYPE,
167199  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_41_WIDTH },
167200  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_CHECKER_TYPE,
167201  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_42_WIDTH },
167202  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_CHECKER_TYPE,
167203  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_43_WIDTH },
167204  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_CHECKER_TYPE,
167205  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_44_WIDTH },
167206  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_CHECKER_TYPE,
167207  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_45_WIDTH },
167208  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_CHECKER_TYPE,
167209  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_46_WIDTH },
167210  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_CHECKER_TYPE,
167211  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_47_WIDTH },
167212  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_CHECKER_TYPE,
167213  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_48_WIDTH },
167214  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_CHECKER_TYPE,
167215  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_49_WIDTH },
167216  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_CHECKER_TYPE,
167217  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_50_WIDTH },
167218  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_CHECKER_TYPE,
167219  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_51_WIDTH },
167220  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_CHECKER_TYPE,
167221  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_52_WIDTH },
167222  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_CHECKER_TYPE,
167223  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_53_WIDTH },
167224  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_CHECKER_TYPE,
167225  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_54_WIDTH },
167226  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_CHECKER_TYPE,
167227  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_55_WIDTH },
167228  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_CHECKER_TYPE,
167229  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_56_WIDTH },
167230  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_CHECKER_TYPE,
167231  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_57_WIDTH },
167232  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_CHECKER_TYPE,
167233  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_58_WIDTH },
167234  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_CHECKER_TYPE,
167235  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_59_WIDTH },
167236  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_CHECKER_TYPE,
167237  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_60_WIDTH },
167238  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_CHECKER_TYPE,
167239  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_61_WIDTH },
167240  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_CHECKER_TYPE,
167241  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_62_WIDTH },
167242  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_CHECKER_TYPE,
167243  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_63_WIDTH },
167244  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_CHECKER_TYPE,
167245  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_64_WIDTH },
167246  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_CHECKER_TYPE,
167247  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_65_WIDTH },
167248  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_CHECKER_TYPE,
167249  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_66_WIDTH },
167250  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_CHECKER_TYPE,
167251  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_67_WIDTH },
167252  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_CHECKER_TYPE,
167253  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_68_WIDTH },
167254  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_CHECKER_TYPE,
167255  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_69_WIDTH },
167256  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_CHECKER_TYPE,
167257  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_70_WIDTH },
167258  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_CHECKER_TYPE,
167259  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_71_WIDTH },
167260  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_CHECKER_TYPE,
167261  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_72_WIDTH },
167262  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_CHECKER_TYPE,
167263  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_73_WIDTH },
167264  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_CHECKER_TYPE,
167265  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_74_WIDTH },
167266  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_CHECKER_TYPE,
167267  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_75_WIDTH },
167268  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_CHECKER_TYPE,
167269  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_76_WIDTH },
167270  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_CHECKER_TYPE,
167271  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_77_WIDTH },
167272  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_CHECKER_TYPE,
167273  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_78_WIDTH },
167274  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_CHECKER_TYPE,
167275  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_79_WIDTH },
167276  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_CHECKER_TYPE,
167277  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_80_WIDTH },
167278  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_CHECKER_TYPE,
167279  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_81_WIDTH },
167280  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_CHECKER_TYPE,
167281  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_82_WIDTH },
167282  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_CHECKER_TYPE,
167283  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_83_WIDTH },
167284  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_CHECKER_TYPE,
167285  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_84_WIDTH },
167286  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_CHECKER_TYPE,
167287  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_85_WIDTH },
167288  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_CHECKER_TYPE,
167289  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_86_WIDTH },
167290  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_CHECKER_TYPE,
167291  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_87_WIDTH },
167292  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_CHECKER_TYPE,
167293  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_88_WIDTH },
167294  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_CHECKER_TYPE,
167295  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_89_WIDTH },
167296  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_CHECKER_TYPE,
167297  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_90_WIDTH },
167298  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_CHECKER_TYPE,
167299  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_91_WIDTH },
167300  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_CHECKER_TYPE,
167301  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_92_WIDTH },
167302  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_CHECKER_TYPE,
167303  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_93_WIDTH },
167304  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_CHECKER_TYPE,
167305  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_94_WIDTH },
167306  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_CHECKER_TYPE,
167307  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_95_WIDTH },
167308  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_CHECKER_TYPE,
167309  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_96_WIDTH },
167310  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_CHECKER_TYPE,
167311  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_97_WIDTH },
167312  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_CHECKER_TYPE,
167313  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_98_WIDTH },
167314  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_CHECKER_TYPE,
167315  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_99_WIDTH },
167316  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_CHECKER_TYPE,
167317  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_100_WIDTH },
167318  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_CHECKER_TYPE,
167319  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_101_WIDTH },
167320  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_102_CHECKER_TYPE,
167321  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_102_WIDTH },
167322  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_103_CHECKER_TYPE,
167323  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_103_WIDTH },
167324  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_104_CHECKER_TYPE,
167325  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_104_WIDTH },
167326  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_105_CHECKER_TYPE,
167327  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_105_WIDTH },
167328  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_106_CHECKER_TYPE,
167329  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_106_WIDTH },
167330  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_107_CHECKER_TYPE,
167331  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_107_WIDTH },
167332  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_108_CHECKER_TYPE,
167333  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_108_WIDTH },
167334  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_109_CHECKER_TYPE,
167335  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_109_WIDTH },
167336  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_110_CHECKER_TYPE,
167337  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_110_WIDTH },
167338  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_111_CHECKER_TYPE,
167339  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_111_WIDTH },
167340  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_112_CHECKER_TYPE,
167341  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_112_WIDTH },
167342  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_113_CHECKER_TYPE,
167343  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_113_WIDTH },
167344  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_114_CHECKER_TYPE,
167345  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_114_WIDTH },
167346  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_115_CHECKER_TYPE,
167347  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_115_WIDTH },
167348  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_116_CHECKER_TYPE,
167349  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_116_WIDTH },
167350  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_117_CHECKER_TYPE,
167351  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_117_WIDTH },
167352  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_118_CHECKER_TYPE,
167353  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_118_WIDTH },
167354  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_119_CHECKER_TYPE,
167355  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_119_WIDTH },
167356  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_120_CHECKER_TYPE,
167357  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_120_WIDTH },
167358  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_121_CHECKER_TYPE,
167359  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_121_WIDTH },
167360  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_122_CHECKER_TYPE,
167361  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_122_WIDTH },
167362  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_123_CHECKER_TYPE,
167363  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_123_WIDTH },
167364  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_124_CHECKER_TYPE,
167365  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_124_WIDTH },
167366  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_125_CHECKER_TYPE,
167367  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_125_WIDTH },
167368  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_126_CHECKER_TYPE,
167369  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_126_WIDTH },
167370  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_127_CHECKER_TYPE,
167371  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_127_WIDTH },
167372  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_128_CHECKER_TYPE,
167373  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_128_WIDTH },
167374  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_129_CHECKER_TYPE,
167375  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_129_WIDTH },
167376  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_130_CHECKER_TYPE,
167377  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_130_WIDTH },
167378  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_131_CHECKER_TYPE,
167379  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_131_WIDTH },
167380  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_132_CHECKER_TYPE,
167381  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_132_WIDTH },
167382  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_133_CHECKER_TYPE,
167383  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_133_WIDTH },
167384  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_134_CHECKER_TYPE,
167385  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_134_WIDTH },
167386  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_135_CHECKER_TYPE,
167387  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_135_WIDTH },
167388  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_136_CHECKER_TYPE,
167389  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_136_WIDTH },
167390  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_137_CHECKER_TYPE,
167391  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_137_WIDTH },
167392  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_138_CHECKER_TYPE,
167393  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_138_WIDTH },
167394  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_139_CHECKER_TYPE,
167395  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_139_WIDTH },
167396  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_140_CHECKER_TYPE,
167397  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_140_WIDTH },
167398  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_141_CHECKER_TYPE,
167399  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_141_WIDTH },
167400  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_142_CHECKER_TYPE,
167401  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_142_WIDTH },
167402  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_143_CHECKER_TYPE,
167403  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_143_WIDTH },
167404  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_144_CHECKER_TYPE,
167405  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_144_WIDTH },
167406  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_145_CHECKER_TYPE,
167407  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_145_WIDTH },
167408  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_146_CHECKER_TYPE,
167409  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_146_WIDTH },
167410  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_147_CHECKER_TYPE,
167411  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_147_WIDTH },
167412  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_148_CHECKER_TYPE,
167413  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_148_WIDTH },
167414  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_149_CHECKER_TYPE,
167415  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_149_WIDTH },
167416  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_150_CHECKER_TYPE,
167417  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_150_WIDTH },
167418  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_151_CHECKER_TYPE,
167419  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_151_WIDTH },
167420  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_152_CHECKER_TYPE,
167421  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_152_WIDTH },
167422  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_153_CHECKER_TYPE,
167423  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_153_WIDTH },
167424  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_154_CHECKER_TYPE,
167425  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_154_WIDTH },
167426  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_155_CHECKER_TYPE,
167427  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_155_WIDTH },
167428  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_156_CHECKER_TYPE,
167429  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_156_WIDTH },
167430  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_157_CHECKER_TYPE,
167431  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_157_WIDTH },
167432  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_158_CHECKER_TYPE,
167433  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_158_WIDTH },
167434  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_159_CHECKER_TYPE,
167435  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_159_WIDTH },
167436  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_160_CHECKER_TYPE,
167437  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_160_WIDTH },
167438  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_161_CHECKER_TYPE,
167439  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_161_WIDTH },
167440  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_162_CHECKER_TYPE,
167441  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_162_WIDTH },
167442  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_163_CHECKER_TYPE,
167443  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_163_WIDTH },
167444  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_164_CHECKER_TYPE,
167445  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_164_WIDTH },
167446  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_165_CHECKER_TYPE,
167447  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_165_WIDTH },
167448  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_166_CHECKER_TYPE,
167449  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_166_WIDTH },
167450  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_167_CHECKER_TYPE,
167451  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_167_WIDTH },
167452  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_168_CHECKER_TYPE,
167453  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_168_WIDTH },
167454  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_169_CHECKER_TYPE,
167455  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_169_WIDTH },
167456  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_170_CHECKER_TYPE,
167457  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_170_WIDTH },
167458  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_171_CHECKER_TYPE,
167459  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_171_WIDTH },
167460  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_172_CHECKER_TYPE,
167461  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_172_WIDTH },
167462  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_173_CHECKER_TYPE,
167463  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_173_WIDTH },
167464  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_174_CHECKER_TYPE,
167465  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_174_WIDTH },
167466  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_175_CHECKER_TYPE,
167467  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_175_WIDTH },
167468  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_176_CHECKER_TYPE,
167469  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_176_WIDTH },
167470  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_177_CHECKER_TYPE,
167471  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_177_WIDTH },
167472  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_178_CHECKER_TYPE,
167473  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_178_WIDTH },
167474  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_179_CHECKER_TYPE,
167475  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_179_WIDTH },
167476  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_180_CHECKER_TYPE,
167477  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_180_WIDTH },
167478  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_181_CHECKER_TYPE,
167479  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_181_WIDTH },
167480  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_182_CHECKER_TYPE,
167481  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_182_WIDTH },
167482  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_183_CHECKER_TYPE,
167483  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_183_WIDTH },
167484  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_184_CHECKER_TYPE,
167485  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_184_WIDTH },
167486  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_185_CHECKER_TYPE,
167487  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_185_WIDTH },
167488  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_186_CHECKER_TYPE,
167489  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_186_WIDTH },
167490  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_187_CHECKER_TYPE,
167491  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_187_WIDTH },
167492  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_188_CHECKER_TYPE,
167493  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_188_WIDTH },
167494  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_189_CHECKER_TYPE,
167495  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_189_WIDTH },
167496  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_190_CHECKER_TYPE,
167497  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_190_WIDTH },
167498  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_191_CHECKER_TYPE,
167499  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_191_WIDTH },
167500  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_192_CHECKER_TYPE,
167501  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_192_WIDTH },
167502  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_193_CHECKER_TYPE,
167503  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_193_WIDTH },
167504  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_194_CHECKER_TYPE,
167505  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_194_WIDTH },
167506  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_195_CHECKER_TYPE,
167507  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_195_WIDTH },
167508  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_196_CHECKER_TYPE,
167509  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_196_WIDTH },
167510  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_197_CHECKER_TYPE,
167511  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_197_WIDTH },
167512  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_198_CHECKER_TYPE,
167513  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_198_WIDTH },
167514  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_199_CHECKER_TYPE,
167515  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_199_WIDTH },
167516  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_200_CHECKER_TYPE,
167517  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_200_WIDTH },
167518  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_201_CHECKER_TYPE,
167519  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_201_WIDTH },
167520  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_202_CHECKER_TYPE,
167521  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_202_WIDTH },
167522  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_203_CHECKER_TYPE,
167523  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_203_WIDTH },
167524  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_204_CHECKER_TYPE,
167525  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_204_WIDTH },
167526  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_205_CHECKER_TYPE,
167527  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_205_WIDTH },
167528  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_206_CHECKER_TYPE,
167529  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_206_WIDTH },
167530  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_207_CHECKER_TYPE,
167531  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_207_WIDTH },
167532  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_208_CHECKER_TYPE,
167533  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_208_WIDTH },
167534  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_209_CHECKER_TYPE,
167535  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_209_WIDTH },
167536  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_210_CHECKER_TYPE,
167537  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_210_WIDTH },
167538  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_211_CHECKER_TYPE,
167539  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_211_WIDTH },
167540  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_212_CHECKER_TYPE,
167541  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_212_WIDTH },
167542  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_213_CHECKER_TYPE,
167543  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_213_WIDTH },
167544  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_214_CHECKER_TYPE,
167545  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_214_WIDTH },
167546  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_215_CHECKER_TYPE,
167547  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_215_WIDTH },
167548  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_216_CHECKER_TYPE,
167549  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_216_WIDTH },
167550  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_217_CHECKER_TYPE,
167551  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_217_WIDTH },
167552  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_218_CHECKER_TYPE,
167553  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_218_WIDTH },
167554  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_219_CHECKER_TYPE,
167555  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_219_WIDTH },
167556  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_220_CHECKER_TYPE,
167557  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_220_WIDTH },
167558  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_221_CHECKER_TYPE,
167559  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_221_WIDTH },
167560  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_222_CHECKER_TYPE,
167561  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_222_WIDTH },
167562  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_223_CHECKER_TYPE,
167563  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_223_WIDTH },
167564  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_224_CHECKER_TYPE,
167565  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_224_WIDTH },
167566  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_225_CHECKER_TYPE,
167567  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_225_WIDTH },
167568  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_226_CHECKER_TYPE,
167569  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_226_WIDTH },
167570  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_227_CHECKER_TYPE,
167571  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_227_WIDTH },
167572  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_228_CHECKER_TYPE,
167573  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_228_WIDTH },
167574  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_229_CHECKER_TYPE,
167575  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_229_WIDTH },
167576  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_230_CHECKER_TYPE,
167577  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_230_WIDTH },
167578  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_231_CHECKER_TYPE,
167579  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_231_WIDTH },
167580  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_232_CHECKER_TYPE,
167581  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_232_WIDTH },
167582  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_233_CHECKER_TYPE,
167583  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_233_WIDTH },
167584  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_234_CHECKER_TYPE,
167585  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_234_WIDTH },
167586  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_235_CHECKER_TYPE,
167587  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_235_WIDTH },
167588  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_236_CHECKER_TYPE,
167589  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_236_WIDTH },
167590  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_237_CHECKER_TYPE,
167591  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_237_WIDTH },
167592  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_238_CHECKER_TYPE,
167593  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_238_WIDTH },
167594  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_239_CHECKER_TYPE,
167595  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_239_WIDTH },
167596  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_240_CHECKER_TYPE,
167597  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_240_WIDTH },
167598  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_241_CHECKER_TYPE,
167599  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_241_WIDTH },
167600  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_242_CHECKER_TYPE,
167601  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_242_WIDTH },
167602  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_243_CHECKER_TYPE,
167603  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_243_WIDTH },
167604  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_244_CHECKER_TYPE,
167605  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_244_WIDTH },
167606  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_245_CHECKER_TYPE,
167607  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_245_WIDTH },
167608  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_246_CHECKER_TYPE,
167609  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_246_WIDTH },
167610  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_247_CHECKER_TYPE,
167611  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_247_WIDTH },
167612  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_248_CHECKER_TYPE,
167613  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_248_WIDTH },
167614  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_249_CHECKER_TYPE,
167615  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_249_WIDTH },
167616  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_250_CHECKER_TYPE,
167617  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_250_WIDTH },
167618  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_251_CHECKER_TYPE,
167619  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_251_WIDTH },
167620  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_252_CHECKER_TYPE,
167621  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_252_WIDTH },
167622  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_253_CHECKER_TYPE,
167623  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_253_WIDTH },
167624  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_254_CHECKER_TYPE,
167625  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_254_WIDTH },
167626  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_255_CHECKER_TYPE,
167627  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_GROUP_255_WIDTH },
167628 };
167629 
167635 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS] =
167636 {
167637  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_0_CHECKER_TYPE,
167638  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_0_WIDTH },
167639  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_1_CHECKER_TYPE,
167640  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_1_WIDTH },
167641  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_2_CHECKER_TYPE,
167642  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_2_WIDTH },
167643  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_3_CHECKER_TYPE,
167644  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_3_WIDTH },
167645  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_4_CHECKER_TYPE,
167646  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_4_WIDTH },
167647  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_5_CHECKER_TYPE,
167648  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_5_WIDTH },
167649  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_6_CHECKER_TYPE,
167650  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_6_WIDTH },
167651  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_7_CHECKER_TYPE,
167652  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_7_WIDTH },
167653  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_8_CHECKER_TYPE,
167654  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_8_WIDTH },
167655  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_9_CHECKER_TYPE,
167656  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_9_WIDTH },
167657  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_10_CHECKER_TYPE,
167658  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_10_WIDTH },
167659  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_11_CHECKER_TYPE,
167660  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_11_WIDTH },
167661  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_12_CHECKER_TYPE,
167662  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_12_WIDTH },
167663  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_13_CHECKER_TYPE,
167664  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_13_WIDTH },
167665  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_14_CHECKER_TYPE,
167666  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_14_WIDTH },
167667  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_15_CHECKER_TYPE,
167668  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_15_WIDTH },
167669  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_16_CHECKER_TYPE,
167670  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_16_WIDTH },
167671  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_17_CHECKER_TYPE,
167672  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_17_WIDTH },
167673  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_18_CHECKER_TYPE,
167674  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_18_WIDTH },
167675  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_19_CHECKER_TYPE,
167676  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_19_WIDTH },
167677  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_20_CHECKER_TYPE,
167678  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_20_WIDTH },
167679  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_21_CHECKER_TYPE,
167680  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_21_WIDTH },
167681  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_22_CHECKER_TYPE,
167682  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_22_WIDTH },
167683  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_23_CHECKER_TYPE,
167684  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_23_WIDTH },
167685  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_24_CHECKER_TYPE,
167686  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_24_WIDTH },
167687  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_25_CHECKER_TYPE,
167688  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_25_WIDTH },
167689  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_26_CHECKER_TYPE,
167690  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_26_WIDTH },
167691  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_27_CHECKER_TYPE,
167692  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_27_WIDTH },
167693  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_28_CHECKER_TYPE,
167694  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_28_WIDTH },
167695  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_29_CHECKER_TYPE,
167696  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_29_WIDTH },
167697  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_30_CHECKER_TYPE,
167698  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_30_WIDTH },
167699  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_31_CHECKER_TYPE,
167700  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_31_WIDTH },
167701  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_32_CHECKER_TYPE,
167702  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_32_WIDTH },
167703  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_33_CHECKER_TYPE,
167704  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_33_WIDTH },
167705  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_34_CHECKER_TYPE,
167706  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_34_WIDTH },
167707  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_35_CHECKER_TYPE,
167708  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_35_WIDTH },
167709  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_36_CHECKER_TYPE,
167710  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_36_WIDTH },
167711  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_37_CHECKER_TYPE,
167712  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_37_WIDTH },
167713  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_38_CHECKER_TYPE,
167714  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_38_WIDTH },
167715  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_39_CHECKER_TYPE,
167716  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_39_WIDTH },
167717  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_40_CHECKER_TYPE,
167718  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_40_WIDTH },
167719  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_41_CHECKER_TYPE,
167720  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_41_WIDTH },
167721  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_42_CHECKER_TYPE,
167722  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_42_WIDTH },
167723  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_43_CHECKER_TYPE,
167724  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_43_WIDTH },
167725  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_44_CHECKER_TYPE,
167726  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_44_WIDTH },
167727  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_45_CHECKER_TYPE,
167728  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_45_WIDTH },
167729  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_46_CHECKER_TYPE,
167730  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_46_WIDTH },
167731  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_47_CHECKER_TYPE,
167732  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_47_WIDTH },
167733  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_48_CHECKER_TYPE,
167734  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_48_WIDTH },
167735  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_49_CHECKER_TYPE,
167736  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_49_WIDTH },
167737  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_50_CHECKER_TYPE,
167738  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_50_WIDTH },
167739  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_51_CHECKER_TYPE,
167740  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_51_WIDTH },
167741  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_52_CHECKER_TYPE,
167742  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_52_WIDTH },
167743  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_53_CHECKER_TYPE,
167744  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_53_WIDTH },
167745  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_54_CHECKER_TYPE,
167746  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_54_WIDTH },
167747  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_55_CHECKER_TYPE,
167748  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_55_WIDTH },
167749  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_56_CHECKER_TYPE,
167750  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_56_WIDTH },
167751  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_57_CHECKER_TYPE,
167752  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_57_WIDTH },
167753  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_58_CHECKER_TYPE,
167754  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_58_WIDTH },
167755  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_59_CHECKER_TYPE,
167756  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_59_WIDTH },
167757  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_60_CHECKER_TYPE,
167758  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_60_WIDTH },
167759  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_61_CHECKER_TYPE,
167760  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_61_WIDTH },
167761  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_62_CHECKER_TYPE,
167762  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_62_WIDTH },
167763  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_63_CHECKER_TYPE,
167764  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_63_WIDTH },
167765  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_64_CHECKER_TYPE,
167766  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_64_WIDTH },
167767  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_65_CHECKER_TYPE,
167768  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_65_WIDTH },
167769  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_66_CHECKER_TYPE,
167770  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_66_WIDTH },
167771  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_67_CHECKER_TYPE,
167772  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_67_WIDTH },
167773  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_68_CHECKER_TYPE,
167774  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_68_WIDTH },
167775  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_69_CHECKER_TYPE,
167776  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_69_WIDTH },
167777  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_70_CHECKER_TYPE,
167778  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_70_WIDTH },
167779  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_71_CHECKER_TYPE,
167780  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_71_WIDTH },
167781  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_72_CHECKER_TYPE,
167782  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_72_WIDTH },
167783  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_73_CHECKER_TYPE,
167784  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_73_WIDTH },
167785  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_74_CHECKER_TYPE,
167786  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_74_WIDTH },
167787  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_75_CHECKER_TYPE,
167788  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_75_WIDTH },
167789  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_76_CHECKER_TYPE,
167790  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_76_WIDTH },
167791  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_77_CHECKER_TYPE,
167792  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_77_WIDTH },
167793  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_78_CHECKER_TYPE,
167794  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_78_WIDTH },
167795  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_79_CHECKER_TYPE,
167796  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_79_WIDTH },
167797  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_80_CHECKER_TYPE,
167798  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_80_WIDTH },
167799  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_81_CHECKER_TYPE,
167800  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_81_WIDTH },
167801  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_82_CHECKER_TYPE,
167802  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_82_WIDTH },
167803  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_83_CHECKER_TYPE,
167804  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_83_WIDTH },
167805  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_84_CHECKER_TYPE,
167806  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_84_WIDTH },
167807  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_85_CHECKER_TYPE,
167808  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_85_WIDTH },
167809  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_86_CHECKER_TYPE,
167810  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_86_WIDTH },
167811  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_87_CHECKER_TYPE,
167812  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_87_WIDTH },
167813  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_88_CHECKER_TYPE,
167814  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_88_WIDTH },
167815  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_89_CHECKER_TYPE,
167816  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_89_WIDTH },
167817  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_90_CHECKER_TYPE,
167818  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_90_WIDTH },
167819  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_91_CHECKER_TYPE,
167820  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_91_WIDTH },
167821  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_92_CHECKER_TYPE,
167822  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_92_WIDTH },
167823  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_93_CHECKER_TYPE,
167824  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_93_WIDTH },
167825  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_94_CHECKER_TYPE,
167826  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_94_WIDTH },
167827  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_95_CHECKER_TYPE,
167828  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_95_WIDTH },
167829  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_96_CHECKER_TYPE,
167830  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_96_WIDTH },
167831  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_97_CHECKER_TYPE,
167832  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_97_WIDTH },
167833  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_98_CHECKER_TYPE,
167834  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_98_WIDTH },
167835  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_99_CHECKER_TYPE,
167836  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_99_WIDTH },
167837  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_100_CHECKER_TYPE,
167838  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_100_WIDTH },
167839  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_101_CHECKER_TYPE,
167840  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_101_WIDTH },
167841  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_102_CHECKER_TYPE,
167842  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_102_WIDTH },
167843  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_103_CHECKER_TYPE,
167844  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_103_WIDTH },
167845  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_104_CHECKER_TYPE,
167846  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_104_WIDTH },
167847  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_105_CHECKER_TYPE,
167848  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_105_WIDTH },
167849  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_106_CHECKER_TYPE,
167850  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_106_WIDTH },
167851  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_107_CHECKER_TYPE,
167852  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_107_WIDTH },
167853  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_108_CHECKER_TYPE,
167854  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_108_WIDTH },
167855  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_109_CHECKER_TYPE,
167856  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_109_WIDTH },
167857  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_110_CHECKER_TYPE,
167858  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_110_WIDTH },
167859  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_111_CHECKER_TYPE,
167860  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_111_WIDTH },
167861  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_112_CHECKER_TYPE,
167862  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_112_WIDTH },
167863  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_113_CHECKER_TYPE,
167864  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_113_WIDTH },
167865  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_114_CHECKER_TYPE,
167866  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_114_WIDTH },
167867  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_115_CHECKER_TYPE,
167868  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_115_WIDTH },
167869  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_116_CHECKER_TYPE,
167870  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_116_WIDTH },
167871  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_117_CHECKER_TYPE,
167872  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_117_WIDTH },
167873  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_118_CHECKER_TYPE,
167874  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_118_WIDTH },
167875  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_119_CHECKER_TYPE,
167876  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_119_WIDTH },
167877  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_120_CHECKER_TYPE,
167878  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_120_WIDTH },
167879  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_121_CHECKER_TYPE,
167880  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_121_WIDTH },
167881  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_122_CHECKER_TYPE,
167882  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_122_WIDTH },
167883  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_123_CHECKER_TYPE,
167884  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_123_WIDTH },
167885  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_124_CHECKER_TYPE,
167886  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_124_WIDTH },
167887  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_125_CHECKER_TYPE,
167888  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_125_WIDTH },
167889  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_126_CHECKER_TYPE,
167890  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_126_WIDTH },
167891  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_127_CHECKER_TYPE,
167892  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_127_WIDTH },
167893  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_128_CHECKER_TYPE,
167894  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_128_WIDTH },
167895  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_129_CHECKER_TYPE,
167896  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_129_WIDTH },
167897  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_130_CHECKER_TYPE,
167898  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_130_WIDTH },
167899  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_131_CHECKER_TYPE,
167900  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_131_WIDTH },
167901  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_132_CHECKER_TYPE,
167902  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_132_WIDTH },
167903  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_133_CHECKER_TYPE,
167904  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_133_WIDTH },
167905  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_134_CHECKER_TYPE,
167906  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_134_WIDTH },
167907  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_135_CHECKER_TYPE,
167908  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_135_WIDTH },
167909  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_136_CHECKER_TYPE,
167910  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_136_WIDTH },
167911  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_137_CHECKER_TYPE,
167912  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_137_WIDTH },
167913  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_138_CHECKER_TYPE,
167914  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_138_WIDTH },
167915  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_139_CHECKER_TYPE,
167916  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_139_WIDTH },
167917  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_140_CHECKER_TYPE,
167918  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_140_WIDTH },
167919  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_141_CHECKER_TYPE,
167920  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_141_WIDTH },
167921  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_142_CHECKER_TYPE,
167922  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_142_WIDTH },
167923  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_143_CHECKER_TYPE,
167924  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_143_WIDTH },
167925  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_144_CHECKER_TYPE,
167926  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_144_WIDTH },
167927  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_145_CHECKER_TYPE,
167928  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_145_WIDTH },
167929  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_146_CHECKER_TYPE,
167930  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_146_WIDTH },
167931  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_147_CHECKER_TYPE,
167932  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_147_WIDTH },
167933  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_148_CHECKER_TYPE,
167934  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_148_WIDTH },
167935  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_149_CHECKER_TYPE,
167936  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_149_WIDTH },
167937  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_150_CHECKER_TYPE,
167938  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_150_WIDTH },
167939  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_151_CHECKER_TYPE,
167940  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_151_WIDTH },
167941  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_152_CHECKER_TYPE,
167942  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_152_WIDTH },
167943  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_153_CHECKER_TYPE,
167944  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_153_WIDTH },
167945  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_154_CHECKER_TYPE,
167946  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_154_WIDTH },
167947  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_155_CHECKER_TYPE,
167948  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_155_WIDTH },
167949  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_156_CHECKER_TYPE,
167950  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_156_WIDTH },
167951  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_157_CHECKER_TYPE,
167952  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_157_WIDTH },
167953  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_158_CHECKER_TYPE,
167954  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_158_WIDTH },
167955  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_159_CHECKER_TYPE,
167956  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_159_WIDTH },
167957  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_160_CHECKER_TYPE,
167958  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_160_WIDTH },
167959  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_161_CHECKER_TYPE,
167960  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_161_WIDTH },
167961  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_162_CHECKER_TYPE,
167962  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_162_WIDTH },
167963  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_163_CHECKER_TYPE,
167964  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_163_WIDTH },
167965  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_164_CHECKER_TYPE,
167966  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_164_WIDTH },
167967  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_165_CHECKER_TYPE,
167968  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_165_WIDTH },
167969  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_166_CHECKER_TYPE,
167970  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_166_WIDTH },
167971  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_167_CHECKER_TYPE,
167972  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_167_WIDTH },
167973  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_168_CHECKER_TYPE,
167974  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_168_WIDTH },
167975  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_169_CHECKER_TYPE,
167976  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_169_WIDTH },
167977  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_170_CHECKER_TYPE,
167978  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_170_WIDTH },
167979  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_171_CHECKER_TYPE,
167980  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_171_WIDTH },
167981  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_172_CHECKER_TYPE,
167982  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_172_WIDTH },
167983  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_173_CHECKER_TYPE,
167984  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_173_WIDTH },
167985  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_174_CHECKER_TYPE,
167986  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_174_WIDTH },
167987  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_175_CHECKER_TYPE,
167988  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_175_WIDTH },
167989  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_176_CHECKER_TYPE,
167990  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_176_WIDTH },
167991  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_177_CHECKER_TYPE,
167992  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_177_WIDTH },
167993  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_178_CHECKER_TYPE,
167994  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_178_WIDTH },
167995  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_179_CHECKER_TYPE,
167996  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_179_WIDTH },
167997  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_180_CHECKER_TYPE,
167998  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_180_WIDTH },
167999  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_181_CHECKER_TYPE,
168000  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_181_WIDTH },
168001  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_182_CHECKER_TYPE,
168002  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_182_WIDTH },
168003  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_183_CHECKER_TYPE,
168004  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_183_WIDTH },
168005  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_184_CHECKER_TYPE,
168006  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_184_WIDTH },
168007  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_185_CHECKER_TYPE,
168008  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_185_WIDTH },
168009  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_186_CHECKER_TYPE,
168010  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_186_WIDTH },
168011  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_187_CHECKER_TYPE,
168012  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_187_WIDTH },
168013  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_188_CHECKER_TYPE,
168014  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_188_WIDTH },
168015  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_189_CHECKER_TYPE,
168016  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_189_WIDTH },
168017  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_190_CHECKER_TYPE,
168018  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_190_WIDTH },
168019  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_191_CHECKER_TYPE,
168020  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_191_WIDTH },
168021  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_192_CHECKER_TYPE,
168022  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_192_WIDTH },
168023  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_193_CHECKER_TYPE,
168024  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_193_WIDTH },
168025  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_194_CHECKER_TYPE,
168026  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_194_WIDTH },
168027  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_195_CHECKER_TYPE,
168028  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_195_WIDTH },
168029  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_196_CHECKER_TYPE,
168030  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_196_WIDTH },
168031  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_197_CHECKER_TYPE,
168032  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_197_WIDTH },
168033  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_198_CHECKER_TYPE,
168034  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_198_WIDTH },
168035  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_199_CHECKER_TYPE,
168036  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_199_WIDTH },
168037  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_200_CHECKER_TYPE,
168038  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_200_WIDTH },
168039  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_201_CHECKER_TYPE,
168040  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_201_WIDTH },
168041  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_202_CHECKER_TYPE,
168042  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_202_WIDTH },
168043  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_203_CHECKER_TYPE,
168044  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_203_WIDTH },
168045  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_204_CHECKER_TYPE,
168046  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_204_WIDTH },
168047  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_205_CHECKER_TYPE,
168048  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_205_WIDTH },
168049  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_206_CHECKER_TYPE,
168050  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_206_WIDTH },
168051  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_207_CHECKER_TYPE,
168052  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_207_WIDTH },
168053  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_208_CHECKER_TYPE,
168054  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_208_WIDTH },
168055  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_209_CHECKER_TYPE,
168056  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_209_WIDTH },
168057  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_210_CHECKER_TYPE,
168058  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_210_WIDTH },
168059  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_211_CHECKER_TYPE,
168060  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_211_WIDTH },
168061  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_212_CHECKER_TYPE,
168062  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_212_WIDTH },
168063  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_213_CHECKER_TYPE,
168064  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_213_WIDTH },
168065  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_214_CHECKER_TYPE,
168066  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_214_WIDTH },
168067  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_215_CHECKER_TYPE,
168068  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_215_WIDTH },
168069  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_216_CHECKER_TYPE,
168070  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_216_WIDTH },
168071  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_217_CHECKER_TYPE,
168072  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_217_WIDTH },
168073  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_218_CHECKER_TYPE,
168074  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_218_WIDTH },
168075  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_219_CHECKER_TYPE,
168076  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_219_WIDTH },
168077  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_220_CHECKER_TYPE,
168078  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_220_WIDTH },
168079  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_221_CHECKER_TYPE,
168080  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_221_WIDTH },
168081  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_222_CHECKER_TYPE,
168082  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_222_WIDTH },
168083  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_223_CHECKER_TYPE,
168084  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_223_WIDTH },
168085  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_224_CHECKER_TYPE,
168086  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_224_WIDTH },
168087  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_225_CHECKER_TYPE,
168088  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_225_WIDTH },
168089  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_226_CHECKER_TYPE,
168090  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_226_WIDTH },
168091  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_227_CHECKER_TYPE,
168092  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_227_WIDTH },
168093  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_228_CHECKER_TYPE,
168094  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_228_WIDTH },
168095  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_229_CHECKER_TYPE,
168096  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_229_WIDTH },
168097  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_230_CHECKER_TYPE,
168098  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_230_WIDTH },
168099  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_231_CHECKER_TYPE,
168100  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_231_WIDTH },
168101  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_232_CHECKER_TYPE,
168102  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_232_WIDTH },
168103  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_233_CHECKER_TYPE,
168104  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_233_WIDTH },
168105  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_234_CHECKER_TYPE,
168106  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_234_WIDTH },
168107  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_235_CHECKER_TYPE,
168108  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_235_WIDTH },
168109  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_236_CHECKER_TYPE,
168110  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_236_WIDTH },
168111  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_237_CHECKER_TYPE,
168112  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_237_WIDTH },
168113  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_238_CHECKER_TYPE,
168114  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_238_WIDTH },
168115  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_239_CHECKER_TYPE,
168116  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_239_WIDTH },
168117  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_240_CHECKER_TYPE,
168118  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_240_WIDTH },
168119  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_241_CHECKER_TYPE,
168120  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_241_WIDTH },
168121  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_242_CHECKER_TYPE,
168122  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_242_WIDTH },
168123  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_243_CHECKER_TYPE,
168124  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_243_WIDTH },
168125  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_244_CHECKER_TYPE,
168126  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_244_WIDTH },
168127  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_245_CHECKER_TYPE,
168128  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_245_WIDTH },
168129  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_246_CHECKER_TYPE,
168130  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_246_WIDTH },
168131  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_247_CHECKER_TYPE,
168132  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_247_WIDTH },
168133  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_248_CHECKER_TYPE,
168134  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_248_WIDTH },
168135  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_249_CHECKER_TYPE,
168136  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_249_WIDTH },
168137  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_250_CHECKER_TYPE,
168138  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_250_WIDTH },
168139  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_251_CHECKER_TYPE,
168140  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_251_WIDTH },
168141  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_252_CHECKER_TYPE,
168142  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_252_WIDTH },
168143  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_253_CHECKER_TYPE,
168144  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_253_WIDTH },
168145  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_254_CHECKER_TYPE,
168146  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_254_WIDTH },
168147  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_255_CHECKER_TYPE,
168148  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_GROUP_255_WIDTH },
168149 };
168150 
168156 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS] =
168157 {
168158  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_0_CHECKER_TYPE,
168159  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_0_WIDTH },
168160  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_1_CHECKER_TYPE,
168161  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_1_WIDTH },
168162  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_2_CHECKER_TYPE,
168163  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_2_WIDTH },
168164  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_3_CHECKER_TYPE,
168165  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_3_WIDTH },
168166  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_4_CHECKER_TYPE,
168167  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_4_WIDTH },
168168  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_5_CHECKER_TYPE,
168169  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_5_WIDTH },
168170  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_6_CHECKER_TYPE,
168171  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_6_WIDTH },
168172  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_7_CHECKER_TYPE,
168173  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_7_WIDTH },
168174  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_8_CHECKER_TYPE,
168175  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_8_WIDTH },
168176  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_9_CHECKER_TYPE,
168177  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_9_WIDTH },
168178  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_10_CHECKER_TYPE,
168179  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_10_WIDTH },
168180  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_11_CHECKER_TYPE,
168181  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_11_WIDTH },
168182  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_12_CHECKER_TYPE,
168183  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_12_WIDTH },
168184  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_13_CHECKER_TYPE,
168185  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_13_WIDTH },
168186  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_14_CHECKER_TYPE,
168187  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_14_WIDTH },
168188  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_15_CHECKER_TYPE,
168189  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_15_WIDTH },
168190  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_16_CHECKER_TYPE,
168191  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_16_WIDTH },
168192  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_17_CHECKER_TYPE,
168193  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_17_WIDTH },
168194  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_18_CHECKER_TYPE,
168195  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_18_WIDTH },
168196  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_19_CHECKER_TYPE,
168197  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_19_WIDTH },
168198  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_20_CHECKER_TYPE,
168199  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_20_WIDTH },
168200  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_21_CHECKER_TYPE,
168201  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_21_WIDTH },
168202  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_22_CHECKER_TYPE,
168203  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_22_WIDTH },
168204  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_23_CHECKER_TYPE,
168205  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_23_WIDTH },
168206  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_24_CHECKER_TYPE,
168207  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_24_WIDTH },
168208  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_25_CHECKER_TYPE,
168209  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_25_WIDTH },
168210  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_26_CHECKER_TYPE,
168211  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_26_WIDTH },
168212  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_27_CHECKER_TYPE,
168213  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_27_WIDTH },
168214  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_28_CHECKER_TYPE,
168215  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_28_WIDTH },
168216  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_29_CHECKER_TYPE,
168217  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_29_WIDTH },
168218  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_30_CHECKER_TYPE,
168219  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_30_WIDTH },
168220  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_31_CHECKER_TYPE,
168221  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_31_WIDTH },
168222  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_32_CHECKER_TYPE,
168223  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_32_WIDTH },
168224  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_33_CHECKER_TYPE,
168225  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_33_WIDTH },
168226  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_34_CHECKER_TYPE,
168227  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_34_WIDTH },
168228  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_35_CHECKER_TYPE,
168229  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_35_WIDTH },
168230  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_36_CHECKER_TYPE,
168231  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_36_WIDTH },
168232  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_37_CHECKER_TYPE,
168233  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_37_WIDTH },
168234  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_38_CHECKER_TYPE,
168235  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_38_WIDTH },
168236  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_39_CHECKER_TYPE,
168237  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_39_WIDTH },
168238  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_40_CHECKER_TYPE,
168239  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_40_WIDTH },
168240  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_41_CHECKER_TYPE,
168241  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_41_WIDTH },
168242  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_42_CHECKER_TYPE,
168243  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_42_WIDTH },
168244  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_43_CHECKER_TYPE,
168245  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_43_WIDTH },
168246  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_44_CHECKER_TYPE,
168247  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_44_WIDTH },
168248  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_45_CHECKER_TYPE,
168249  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_45_WIDTH },
168250  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_46_CHECKER_TYPE,
168251  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_46_WIDTH },
168252  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_47_CHECKER_TYPE,
168253  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_47_WIDTH },
168254  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_48_CHECKER_TYPE,
168255  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_48_WIDTH },
168256  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_49_CHECKER_TYPE,
168257  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_49_WIDTH },
168258  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_50_CHECKER_TYPE,
168259  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_50_WIDTH },
168260  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_51_CHECKER_TYPE,
168261  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_51_WIDTH },
168262  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_52_CHECKER_TYPE,
168263  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_52_WIDTH },
168264  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_53_CHECKER_TYPE,
168265  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_53_WIDTH },
168266  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_54_CHECKER_TYPE,
168267  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_54_WIDTH },
168268  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_55_CHECKER_TYPE,
168269  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_55_WIDTH },
168270  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_56_CHECKER_TYPE,
168271  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_56_WIDTH },
168272  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_57_CHECKER_TYPE,
168273  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_57_WIDTH },
168274  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_58_CHECKER_TYPE,
168275  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_58_WIDTH },
168276  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_59_CHECKER_TYPE,
168277  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_59_WIDTH },
168278  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_60_CHECKER_TYPE,
168279  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_60_WIDTH },
168280  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_61_CHECKER_TYPE,
168281  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_61_WIDTH },
168282  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_62_CHECKER_TYPE,
168283  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_62_WIDTH },
168284  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_63_CHECKER_TYPE,
168285  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_63_WIDTH },
168286  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_64_CHECKER_TYPE,
168287  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_64_WIDTH },
168288  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_65_CHECKER_TYPE,
168289  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_65_WIDTH },
168290  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_66_CHECKER_TYPE,
168291  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_66_WIDTH },
168292  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_67_CHECKER_TYPE,
168293  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_67_WIDTH },
168294  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_68_CHECKER_TYPE,
168295  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_68_WIDTH },
168296  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_69_CHECKER_TYPE,
168297  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_69_WIDTH },
168298  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_70_CHECKER_TYPE,
168299  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_70_WIDTH },
168300  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_71_CHECKER_TYPE,
168301  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_71_WIDTH },
168302  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_72_CHECKER_TYPE,
168303  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_72_WIDTH },
168304  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_73_CHECKER_TYPE,
168305  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_73_WIDTH },
168306  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_74_CHECKER_TYPE,
168307  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_74_WIDTH },
168308  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_75_CHECKER_TYPE,
168309  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_75_WIDTH },
168310  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_76_CHECKER_TYPE,
168311  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_76_WIDTH },
168312  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_77_CHECKER_TYPE,
168313  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_77_WIDTH },
168314  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_78_CHECKER_TYPE,
168315  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_78_WIDTH },
168316  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_79_CHECKER_TYPE,
168317  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_79_WIDTH },
168318  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_80_CHECKER_TYPE,
168319  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_80_WIDTH },
168320  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_81_CHECKER_TYPE,
168321  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_81_WIDTH },
168322  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_82_CHECKER_TYPE,
168323  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_82_WIDTH },
168324  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_83_CHECKER_TYPE,
168325  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_83_WIDTH },
168326  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_84_CHECKER_TYPE,
168327  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_84_WIDTH },
168328  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_85_CHECKER_TYPE,
168329  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_85_WIDTH },
168330  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_86_CHECKER_TYPE,
168331  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_86_WIDTH },
168332  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_87_CHECKER_TYPE,
168333  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_87_WIDTH },
168334  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_88_CHECKER_TYPE,
168335  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_88_WIDTH },
168336  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_89_CHECKER_TYPE,
168337  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_89_WIDTH },
168338  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_90_CHECKER_TYPE,
168339  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_90_WIDTH },
168340  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_91_CHECKER_TYPE,
168341  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_91_WIDTH },
168342  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_92_CHECKER_TYPE,
168343  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_92_WIDTH },
168344  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_93_CHECKER_TYPE,
168345  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_93_WIDTH },
168346  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_94_CHECKER_TYPE,
168347  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_94_WIDTH },
168348  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_95_CHECKER_TYPE,
168349  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_95_WIDTH },
168350  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_96_CHECKER_TYPE,
168351  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_96_WIDTH },
168352  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_97_CHECKER_TYPE,
168353  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_97_WIDTH },
168354  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_98_CHECKER_TYPE,
168355  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_98_WIDTH },
168356  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_99_CHECKER_TYPE,
168357  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_99_WIDTH },
168358  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_100_CHECKER_TYPE,
168359  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_100_WIDTH },
168360  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_101_CHECKER_TYPE,
168361  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_101_WIDTH },
168362  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_102_CHECKER_TYPE,
168363  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_102_WIDTH },
168364  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_103_CHECKER_TYPE,
168365  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_103_WIDTH },
168366  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_104_CHECKER_TYPE,
168367  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_104_WIDTH },
168368  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_105_CHECKER_TYPE,
168369  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_105_WIDTH },
168370  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_106_CHECKER_TYPE,
168371  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_106_WIDTH },
168372  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_107_CHECKER_TYPE,
168373  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_107_WIDTH },
168374  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_108_CHECKER_TYPE,
168375  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_108_WIDTH },
168376  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_109_CHECKER_TYPE,
168377  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_109_WIDTH },
168378  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_110_CHECKER_TYPE,
168379  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_110_WIDTH },
168380  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_111_CHECKER_TYPE,
168381  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_111_WIDTH },
168382  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_112_CHECKER_TYPE,
168383  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_112_WIDTH },
168384  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_113_CHECKER_TYPE,
168385  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_113_WIDTH },
168386  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_114_CHECKER_TYPE,
168387  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_114_WIDTH },
168388  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_115_CHECKER_TYPE,
168389  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_115_WIDTH },
168390  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_116_CHECKER_TYPE,
168391  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_116_WIDTH },
168392  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_117_CHECKER_TYPE,
168393  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_117_WIDTH },
168394  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_118_CHECKER_TYPE,
168395  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_118_WIDTH },
168396  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_119_CHECKER_TYPE,
168397  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_119_WIDTH },
168398  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_120_CHECKER_TYPE,
168399  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_120_WIDTH },
168400  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_121_CHECKER_TYPE,
168401  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_121_WIDTH },
168402  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_122_CHECKER_TYPE,
168403  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_122_WIDTH },
168404  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_123_CHECKER_TYPE,
168405  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_123_WIDTH },
168406  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_124_CHECKER_TYPE,
168407  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_124_WIDTH },
168408  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_125_CHECKER_TYPE,
168409  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_125_WIDTH },
168410  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_126_CHECKER_TYPE,
168411  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_126_WIDTH },
168412  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_127_CHECKER_TYPE,
168413  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_127_WIDTH },
168414  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_128_CHECKER_TYPE,
168415  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_128_WIDTH },
168416  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_129_CHECKER_TYPE,
168417  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_129_WIDTH },
168418  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_130_CHECKER_TYPE,
168419  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_130_WIDTH },
168420  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_131_CHECKER_TYPE,
168421  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_131_WIDTH },
168422  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_132_CHECKER_TYPE,
168423  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_132_WIDTH },
168424  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_133_CHECKER_TYPE,
168425  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_133_WIDTH },
168426  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_134_CHECKER_TYPE,
168427  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_134_WIDTH },
168428  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_135_CHECKER_TYPE,
168429  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_135_WIDTH },
168430  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_136_CHECKER_TYPE,
168431  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_136_WIDTH },
168432  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_137_CHECKER_TYPE,
168433  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_137_WIDTH },
168434  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_138_CHECKER_TYPE,
168435  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_138_WIDTH },
168436  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_139_CHECKER_TYPE,
168437  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_139_WIDTH },
168438  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_140_CHECKER_TYPE,
168439  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_140_WIDTH },
168440  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_141_CHECKER_TYPE,
168441  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_141_WIDTH },
168442  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_142_CHECKER_TYPE,
168443  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_142_WIDTH },
168444  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_143_CHECKER_TYPE,
168445  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_143_WIDTH },
168446  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_144_CHECKER_TYPE,
168447  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_144_WIDTH },
168448  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_145_CHECKER_TYPE,
168449  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_145_WIDTH },
168450  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_146_CHECKER_TYPE,
168451  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_146_WIDTH },
168452  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_147_CHECKER_TYPE,
168453  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_147_WIDTH },
168454  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_148_CHECKER_TYPE,
168455  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_148_WIDTH },
168456  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_149_CHECKER_TYPE,
168457  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_149_WIDTH },
168458  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_150_CHECKER_TYPE,
168459  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_150_WIDTH },
168460  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_151_CHECKER_TYPE,
168461  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_151_WIDTH },
168462  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_152_CHECKER_TYPE,
168463  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_152_WIDTH },
168464  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_153_CHECKER_TYPE,
168465  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_153_WIDTH },
168466  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_154_CHECKER_TYPE,
168467  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_154_WIDTH },
168468  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_155_CHECKER_TYPE,
168469  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_155_WIDTH },
168470  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_156_CHECKER_TYPE,
168471  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_156_WIDTH },
168472  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_157_CHECKER_TYPE,
168473  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_157_WIDTH },
168474  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_158_CHECKER_TYPE,
168475  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_158_WIDTH },
168476  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_159_CHECKER_TYPE,
168477  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_159_WIDTH },
168478  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_160_CHECKER_TYPE,
168479  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_160_WIDTH },
168480  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_161_CHECKER_TYPE,
168481  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_161_WIDTH },
168482  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_162_CHECKER_TYPE,
168483  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_162_WIDTH },
168484  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_163_CHECKER_TYPE,
168485  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_163_WIDTH },
168486  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_164_CHECKER_TYPE,
168487  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_164_WIDTH },
168488  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_165_CHECKER_TYPE,
168489  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_165_WIDTH },
168490  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_166_CHECKER_TYPE,
168491  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_166_WIDTH },
168492  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_167_CHECKER_TYPE,
168493  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_167_WIDTH },
168494  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_168_CHECKER_TYPE,
168495  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_168_WIDTH },
168496  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_169_CHECKER_TYPE,
168497  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_169_WIDTH },
168498  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_170_CHECKER_TYPE,
168499  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_170_WIDTH },
168500  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_171_CHECKER_TYPE,
168501  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_171_WIDTH },
168502  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_172_CHECKER_TYPE,
168503  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_172_WIDTH },
168504  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_173_CHECKER_TYPE,
168505  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_173_WIDTH },
168506  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_174_CHECKER_TYPE,
168507  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_174_WIDTH },
168508  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_175_CHECKER_TYPE,
168509  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_175_WIDTH },
168510  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_176_CHECKER_TYPE,
168511  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_176_WIDTH },
168512  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_177_CHECKER_TYPE,
168513  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_177_WIDTH },
168514  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_178_CHECKER_TYPE,
168515  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_178_WIDTH },
168516  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_179_CHECKER_TYPE,
168517  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_179_WIDTH },
168518  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_180_CHECKER_TYPE,
168519  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_180_WIDTH },
168520  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_181_CHECKER_TYPE,
168521  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_181_WIDTH },
168522  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_182_CHECKER_TYPE,
168523  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_182_WIDTH },
168524  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_183_CHECKER_TYPE,
168525  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_183_WIDTH },
168526  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_184_CHECKER_TYPE,
168527  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_184_WIDTH },
168528  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_185_CHECKER_TYPE,
168529  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_185_WIDTH },
168530  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_186_CHECKER_TYPE,
168531  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_186_WIDTH },
168532  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_187_CHECKER_TYPE,
168533  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_187_WIDTH },
168534  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_188_CHECKER_TYPE,
168535  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_188_WIDTH },
168536  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_189_CHECKER_TYPE,
168537  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_189_WIDTH },
168538  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_190_CHECKER_TYPE,
168539  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_190_WIDTH },
168540  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_191_CHECKER_TYPE,
168541  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_191_WIDTH },
168542  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_192_CHECKER_TYPE,
168543  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_192_WIDTH },
168544  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_193_CHECKER_TYPE,
168545  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_193_WIDTH },
168546  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_194_CHECKER_TYPE,
168547  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_194_WIDTH },
168548  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_195_CHECKER_TYPE,
168549  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_195_WIDTH },
168550  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_196_CHECKER_TYPE,
168551  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_196_WIDTH },
168552  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_197_CHECKER_TYPE,
168553  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_197_WIDTH },
168554  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_198_CHECKER_TYPE,
168555  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_198_WIDTH },
168556  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_199_CHECKER_TYPE,
168557  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_199_WIDTH },
168558  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_200_CHECKER_TYPE,
168559  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_200_WIDTH },
168560  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_201_CHECKER_TYPE,
168561  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_201_WIDTH },
168562  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_202_CHECKER_TYPE,
168563  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_202_WIDTH },
168564  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_203_CHECKER_TYPE,
168565  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_203_WIDTH },
168566  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_204_CHECKER_TYPE,
168567  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_204_WIDTH },
168568  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_205_CHECKER_TYPE,
168569  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_205_WIDTH },
168570  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_206_CHECKER_TYPE,
168571  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_206_WIDTH },
168572  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_207_CHECKER_TYPE,
168573  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_207_WIDTH },
168574  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_208_CHECKER_TYPE,
168575  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_208_WIDTH },
168576  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_209_CHECKER_TYPE,
168577  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_209_WIDTH },
168578  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_210_CHECKER_TYPE,
168579  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_210_WIDTH },
168580  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_211_CHECKER_TYPE,
168581  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_211_WIDTH },
168582  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_212_CHECKER_TYPE,
168583  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_212_WIDTH },
168584  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_213_CHECKER_TYPE,
168585  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_213_WIDTH },
168586  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_214_CHECKER_TYPE,
168587  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_214_WIDTH },
168588  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_215_CHECKER_TYPE,
168589  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_215_WIDTH },
168590  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_216_CHECKER_TYPE,
168591  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_216_WIDTH },
168592  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_217_CHECKER_TYPE,
168593  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_217_WIDTH },
168594  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_218_CHECKER_TYPE,
168595  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_218_WIDTH },
168596  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_219_CHECKER_TYPE,
168597  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_219_WIDTH },
168598  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_220_CHECKER_TYPE,
168599  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_220_WIDTH },
168600  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_221_CHECKER_TYPE,
168601  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_221_WIDTH },
168602  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_222_CHECKER_TYPE,
168603  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_222_WIDTH },
168604  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_223_CHECKER_TYPE,
168605  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_223_WIDTH },
168606  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_224_CHECKER_TYPE,
168607  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_224_WIDTH },
168608  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_225_CHECKER_TYPE,
168609  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_225_WIDTH },
168610  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_226_CHECKER_TYPE,
168611  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_226_WIDTH },
168612  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_227_CHECKER_TYPE,
168613  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_227_WIDTH },
168614  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_228_CHECKER_TYPE,
168615  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_228_WIDTH },
168616  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_229_CHECKER_TYPE,
168617  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_229_WIDTH },
168618  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_230_CHECKER_TYPE,
168619  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_230_WIDTH },
168620  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_231_CHECKER_TYPE,
168621  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_231_WIDTH },
168622  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_232_CHECKER_TYPE,
168623  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_232_WIDTH },
168624  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_233_CHECKER_TYPE,
168625  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_233_WIDTH },
168626  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_234_CHECKER_TYPE,
168627  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_234_WIDTH },
168628  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_235_CHECKER_TYPE,
168629  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_235_WIDTH },
168630  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_236_CHECKER_TYPE,
168631  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_236_WIDTH },
168632  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_237_CHECKER_TYPE,
168633  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_237_WIDTH },
168634  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_238_CHECKER_TYPE,
168635  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_238_WIDTH },
168636  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_239_CHECKER_TYPE,
168637  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_239_WIDTH },
168638  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_240_CHECKER_TYPE,
168639  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_240_WIDTH },
168640  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_241_CHECKER_TYPE,
168641  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_241_WIDTH },
168642  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_242_CHECKER_TYPE,
168643  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_242_WIDTH },
168644  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_243_CHECKER_TYPE,
168645  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_243_WIDTH },
168646  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_244_CHECKER_TYPE,
168647  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_244_WIDTH },
168648  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_245_CHECKER_TYPE,
168649  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_245_WIDTH },
168650  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_246_CHECKER_TYPE,
168651  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_246_WIDTH },
168652  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_247_CHECKER_TYPE,
168653  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_247_WIDTH },
168654  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_248_CHECKER_TYPE,
168655  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_248_WIDTH },
168656  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_249_CHECKER_TYPE,
168657  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_249_WIDTH },
168658  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_250_CHECKER_TYPE,
168659  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_250_WIDTH },
168660  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_251_CHECKER_TYPE,
168661  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_251_WIDTH },
168662  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_252_CHECKER_TYPE,
168663  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_252_WIDTH },
168664  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_253_CHECKER_TYPE,
168665  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_253_WIDTH },
168666  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_254_CHECKER_TYPE,
168667  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_254_WIDTH },
168668  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_255_CHECKER_TYPE,
168669  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_GROUP_255_WIDTH },
168670 };
168671 
168677 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS] =
168678 {
168679  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_0_CHECKER_TYPE,
168680  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_0_WIDTH },
168681  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_1_CHECKER_TYPE,
168682  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_1_WIDTH },
168683  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_2_CHECKER_TYPE,
168684  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_2_WIDTH },
168685  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_3_CHECKER_TYPE,
168686  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_3_WIDTH },
168687  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_4_CHECKER_TYPE,
168688  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_4_WIDTH },
168689  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_5_CHECKER_TYPE,
168690  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_5_WIDTH },
168691  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_6_CHECKER_TYPE,
168692  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_6_WIDTH },
168693  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_7_CHECKER_TYPE,
168694  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_7_WIDTH },
168695  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_8_CHECKER_TYPE,
168696  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_8_WIDTH },
168697  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_9_CHECKER_TYPE,
168698  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_9_WIDTH },
168699  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_10_CHECKER_TYPE,
168700  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_10_WIDTH },
168701  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_11_CHECKER_TYPE,
168702  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_11_WIDTH },
168703  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_12_CHECKER_TYPE,
168704  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_12_WIDTH },
168705  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_13_CHECKER_TYPE,
168706  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_13_WIDTH },
168707  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_14_CHECKER_TYPE,
168708  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_14_WIDTH },
168709  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_15_CHECKER_TYPE,
168710  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_15_WIDTH },
168711  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_16_CHECKER_TYPE,
168712  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_16_WIDTH },
168713  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_17_CHECKER_TYPE,
168714  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_17_WIDTH },
168715  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_18_CHECKER_TYPE,
168716  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_18_WIDTH },
168717  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_19_CHECKER_TYPE,
168718  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_19_WIDTH },
168719  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_20_CHECKER_TYPE,
168720  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_20_WIDTH },
168721  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_21_CHECKER_TYPE,
168722  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_21_WIDTH },
168723  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_22_CHECKER_TYPE,
168724  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_22_WIDTH },
168725  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_23_CHECKER_TYPE,
168726  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_23_WIDTH },
168727  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_24_CHECKER_TYPE,
168728  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_24_WIDTH },
168729  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_25_CHECKER_TYPE,
168730  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_25_WIDTH },
168731  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_26_CHECKER_TYPE,
168732  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_26_WIDTH },
168733  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_27_CHECKER_TYPE,
168734  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_27_WIDTH },
168735  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_28_CHECKER_TYPE,
168736  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_28_WIDTH },
168737  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_29_CHECKER_TYPE,
168738  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_29_WIDTH },
168739  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_30_CHECKER_TYPE,
168740  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_30_WIDTH },
168741  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_31_CHECKER_TYPE,
168742  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_31_WIDTH },
168743  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_32_CHECKER_TYPE,
168744  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_32_WIDTH },
168745  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_33_CHECKER_TYPE,
168746  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_33_WIDTH },
168747  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_34_CHECKER_TYPE,
168748  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_34_WIDTH },
168749  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_35_CHECKER_TYPE,
168750  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_35_WIDTH },
168751  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_36_CHECKER_TYPE,
168752  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_36_WIDTH },
168753  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_37_CHECKER_TYPE,
168754  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_37_WIDTH },
168755  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_38_CHECKER_TYPE,
168756  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_38_WIDTH },
168757  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_39_CHECKER_TYPE,
168758  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_39_WIDTH },
168759  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_40_CHECKER_TYPE,
168760  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_40_WIDTH },
168761  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_41_CHECKER_TYPE,
168762  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_41_WIDTH },
168763  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_42_CHECKER_TYPE,
168764  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_42_WIDTH },
168765  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_43_CHECKER_TYPE,
168766  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_43_WIDTH },
168767  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_44_CHECKER_TYPE,
168768  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_44_WIDTH },
168769  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_45_CHECKER_TYPE,
168770  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_45_WIDTH },
168771  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_46_CHECKER_TYPE,
168772  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_46_WIDTH },
168773  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_47_CHECKER_TYPE,
168774  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_47_WIDTH },
168775  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_48_CHECKER_TYPE,
168776  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_48_WIDTH },
168777  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_49_CHECKER_TYPE,
168778  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_49_WIDTH },
168779  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_50_CHECKER_TYPE,
168780  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_50_WIDTH },
168781  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_51_CHECKER_TYPE,
168782  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_51_WIDTH },
168783  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_52_CHECKER_TYPE,
168784  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_52_WIDTH },
168785  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_53_CHECKER_TYPE,
168786  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_53_WIDTH },
168787  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_54_CHECKER_TYPE,
168788  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_54_WIDTH },
168789  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_55_CHECKER_TYPE,
168790  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_55_WIDTH },
168791  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_56_CHECKER_TYPE,
168792  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_56_WIDTH },
168793  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_57_CHECKER_TYPE,
168794  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_57_WIDTH },
168795  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_58_CHECKER_TYPE,
168796  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_58_WIDTH },
168797  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_59_CHECKER_TYPE,
168798  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_59_WIDTH },
168799  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_60_CHECKER_TYPE,
168800  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_60_WIDTH },
168801  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_61_CHECKER_TYPE,
168802  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_61_WIDTH },
168803  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_62_CHECKER_TYPE,
168804  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_62_WIDTH },
168805  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_63_CHECKER_TYPE,
168806  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_63_WIDTH },
168807  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_64_CHECKER_TYPE,
168808  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_64_WIDTH },
168809  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_65_CHECKER_TYPE,
168810  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_65_WIDTH },
168811  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_66_CHECKER_TYPE,
168812  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_66_WIDTH },
168813  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_67_CHECKER_TYPE,
168814  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_67_WIDTH },
168815  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_68_CHECKER_TYPE,
168816  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_68_WIDTH },
168817  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_69_CHECKER_TYPE,
168818  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_69_WIDTH },
168819  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_70_CHECKER_TYPE,
168820  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_70_WIDTH },
168821  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_71_CHECKER_TYPE,
168822  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_71_WIDTH },
168823  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_72_CHECKER_TYPE,
168824  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_72_WIDTH },
168825  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_73_CHECKER_TYPE,
168826  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_73_WIDTH },
168827  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_74_CHECKER_TYPE,
168828  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_74_WIDTH },
168829  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_75_CHECKER_TYPE,
168830  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_75_WIDTH },
168831  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_76_CHECKER_TYPE,
168832  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_76_WIDTH },
168833  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_77_CHECKER_TYPE,
168834  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_77_WIDTH },
168835  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_78_CHECKER_TYPE,
168836  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_78_WIDTH },
168837  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_79_CHECKER_TYPE,
168838  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_79_WIDTH },
168839  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_80_CHECKER_TYPE,
168840  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_80_WIDTH },
168841  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_81_CHECKER_TYPE,
168842  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_81_WIDTH },
168843  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_82_CHECKER_TYPE,
168844  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_82_WIDTH },
168845  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_83_CHECKER_TYPE,
168846  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_83_WIDTH },
168847  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_84_CHECKER_TYPE,
168848  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_84_WIDTH },
168849  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_85_CHECKER_TYPE,
168850  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_85_WIDTH },
168851  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_86_CHECKER_TYPE,
168852  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_86_WIDTH },
168853  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_87_CHECKER_TYPE,
168854  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_87_WIDTH },
168855  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_88_CHECKER_TYPE,
168856  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_88_WIDTH },
168857  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_89_CHECKER_TYPE,
168858  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_89_WIDTH },
168859  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_90_CHECKER_TYPE,
168860  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_90_WIDTH },
168861  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_91_CHECKER_TYPE,
168862  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_91_WIDTH },
168863  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_92_CHECKER_TYPE,
168864  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_92_WIDTH },
168865  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_93_CHECKER_TYPE,
168866  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_93_WIDTH },
168867  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_94_CHECKER_TYPE,
168868  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_94_WIDTH },
168869  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_95_CHECKER_TYPE,
168870  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_95_WIDTH },
168871  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_96_CHECKER_TYPE,
168872  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_96_WIDTH },
168873  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_97_CHECKER_TYPE,
168874  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_97_WIDTH },
168875  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_98_CHECKER_TYPE,
168876  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_98_WIDTH },
168877  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_99_CHECKER_TYPE,
168878  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_99_WIDTH },
168879  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_100_CHECKER_TYPE,
168880  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_100_WIDTH },
168881  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_101_CHECKER_TYPE,
168882  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_101_WIDTH },
168883  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_102_CHECKER_TYPE,
168884  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_102_WIDTH },
168885  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_103_CHECKER_TYPE,
168886  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_103_WIDTH },
168887  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_104_CHECKER_TYPE,
168888  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_104_WIDTH },
168889  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_105_CHECKER_TYPE,
168890  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_105_WIDTH },
168891  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_106_CHECKER_TYPE,
168892  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_106_WIDTH },
168893  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_107_CHECKER_TYPE,
168894  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_107_WIDTH },
168895  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_108_CHECKER_TYPE,
168896  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_108_WIDTH },
168897  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_109_CHECKER_TYPE,
168898  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_109_WIDTH },
168899  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_110_CHECKER_TYPE,
168900  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_110_WIDTH },
168901  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_111_CHECKER_TYPE,
168902  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_111_WIDTH },
168903  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_112_CHECKER_TYPE,
168904  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_112_WIDTH },
168905  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_113_CHECKER_TYPE,
168906  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_113_WIDTH },
168907  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_114_CHECKER_TYPE,
168908  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_114_WIDTH },
168909  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_115_CHECKER_TYPE,
168910  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_115_WIDTH },
168911  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_116_CHECKER_TYPE,
168912  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_116_WIDTH },
168913  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_117_CHECKER_TYPE,
168914  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_117_WIDTH },
168915  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_118_CHECKER_TYPE,
168916  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_118_WIDTH },
168917  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_119_CHECKER_TYPE,
168918  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_119_WIDTH },
168919  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_120_CHECKER_TYPE,
168920  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_120_WIDTH },
168921  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_121_CHECKER_TYPE,
168922  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_121_WIDTH },
168923  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_122_CHECKER_TYPE,
168924  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_122_WIDTH },
168925  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_123_CHECKER_TYPE,
168926  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_123_WIDTH },
168927  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_124_CHECKER_TYPE,
168928  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_124_WIDTH },
168929  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_125_CHECKER_TYPE,
168930  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_125_WIDTH },
168931  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_126_CHECKER_TYPE,
168932  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_126_WIDTH },
168933  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_127_CHECKER_TYPE,
168934  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_127_WIDTH },
168935  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_128_CHECKER_TYPE,
168936  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_128_WIDTH },
168937  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_129_CHECKER_TYPE,
168938  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_129_WIDTH },
168939  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_130_CHECKER_TYPE,
168940  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_130_WIDTH },
168941  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_131_CHECKER_TYPE,
168942  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_131_WIDTH },
168943  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_132_CHECKER_TYPE,
168944  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_132_WIDTH },
168945  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_133_CHECKER_TYPE,
168946  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_133_WIDTH },
168947  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_134_CHECKER_TYPE,
168948  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_134_WIDTH },
168949  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_135_CHECKER_TYPE,
168950  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_135_WIDTH },
168951  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_136_CHECKER_TYPE,
168952  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_136_WIDTH },
168953  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_137_CHECKER_TYPE,
168954  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_137_WIDTH },
168955  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_138_CHECKER_TYPE,
168956  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_138_WIDTH },
168957  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_139_CHECKER_TYPE,
168958  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_139_WIDTH },
168959  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_140_CHECKER_TYPE,
168960  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_140_WIDTH },
168961  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_141_CHECKER_TYPE,
168962  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_141_WIDTH },
168963  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_142_CHECKER_TYPE,
168964  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_142_WIDTH },
168965  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_143_CHECKER_TYPE,
168966  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_143_WIDTH },
168967  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_144_CHECKER_TYPE,
168968  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_144_WIDTH },
168969  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_145_CHECKER_TYPE,
168970  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_145_WIDTH },
168971  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_146_CHECKER_TYPE,
168972  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_146_WIDTH },
168973  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_147_CHECKER_TYPE,
168974  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_147_WIDTH },
168975  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_148_CHECKER_TYPE,
168976  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_148_WIDTH },
168977  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_149_CHECKER_TYPE,
168978  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_149_WIDTH },
168979  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_150_CHECKER_TYPE,
168980  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_150_WIDTH },
168981  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_151_CHECKER_TYPE,
168982  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_151_WIDTH },
168983  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_152_CHECKER_TYPE,
168984  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_152_WIDTH },
168985  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_153_CHECKER_TYPE,
168986  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_153_WIDTH },
168987  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_154_CHECKER_TYPE,
168988  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_154_WIDTH },
168989  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_155_CHECKER_TYPE,
168990  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_155_WIDTH },
168991  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_156_CHECKER_TYPE,
168992  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_156_WIDTH },
168993  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_157_CHECKER_TYPE,
168994  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_157_WIDTH },
168995  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_158_CHECKER_TYPE,
168996  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_158_WIDTH },
168997  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_159_CHECKER_TYPE,
168998  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_159_WIDTH },
168999  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_160_CHECKER_TYPE,
169000  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_160_WIDTH },
169001  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_161_CHECKER_TYPE,
169002  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_161_WIDTH },
169003  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_162_CHECKER_TYPE,
169004  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_162_WIDTH },
169005  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_163_CHECKER_TYPE,
169006  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_163_WIDTH },
169007  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_164_CHECKER_TYPE,
169008  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_164_WIDTH },
169009  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_165_CHECKER_TYPE,
169010  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_165_WIDTH },
169011  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_166_CHECKER_TYPE,
169012  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_166_WIDTH },
169013  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_167_CHECKER_TYPE,
169014  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_167_WIDTH },
169015  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_168_CHECKER_TYPE,
169016  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_168_WIDTH },
169017  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_169_CHECKER_TYPE,
169018  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_169_WIDTH },
169019  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_170_CHECKER_TYPE,
169020  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_170_WIDTH },
169021  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_171_CHECKER_TYPE,
169022  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_171_WIDTH },
169023  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_172_CHECKER_TYPE,
169024  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_172_WIDTH },
169025  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_173_CHECKER_TYPE,
169026  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_173_WIDTH },
169027  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_174_CHECKER_TYPE,
169028  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_174_WIDTH },
169029  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_175_CHECKER_TYPE,
169030  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_175_WIDTH },
169031  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_176_CHECKER_TYPE,
169032  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_176_WIDTH },
169033  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_177_CHECKER_TYPE,
169034  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_177_WIDTH },
169035  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_178_CHECKER_TYPE,
169036  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_178_WIDTH },
169037  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_179_CHECKER_TYPE,
169038  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_179_WIDTH },
169039  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_180_CHECKER_TYPE,
169040  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_180_WIDTH },
169041  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_181_CHECKER_TYPE,
169042  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_181_WIDTH },
169043  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_182_CHECKER_TYPE,
169044  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_182_WIDTH },
169045  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_183_CHECKER_TYPE,
169046  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_183_WIDTH },
169047  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_184_CHECKER_TYPE,
169048  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_184_WIDTH },
169049  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_185_CHECKER_TYPE,
169050  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_185_WIDTH },
169051  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_186_CHECKER_TYPE,
169052  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_186_WIDTH },
169053  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_187_CHECKER_TYPE,
169054  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_187_WIDTH },
169055  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_188_CHECKER_TYPE,
169056  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_188_WIDTH },
169057  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_189_CHECKER_TYPE,
169058  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_189_WIDTH },
169059  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_190_CHECKER_TYPE,
169060  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_190_WIDTH },
169061  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_191_CHECKER_TYPE,
169062  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_191_WIDTH },
169063  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_192_CHECKER_TYPE,
169064  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_192_WIDTH },
169065  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_193_CHECKER_TYPE,
169066  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_193_WIDTH },
169067  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_194_CHECKER_TYPE,
169068  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_194_WIDTH },
169069  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_195_CHECKER_TYPE,
169070  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_195_WIDTH },
169071  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_196_CHECKER_TYPE,
169072  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_196_WIDTH },
169073  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_197_CHECKER_TYPE,
169074  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_197_WIDTH },
169075  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_198_CHECKER_TYPE,
169076  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_198_WIDTH },
169077  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_199_CHECKER_TYPE,
169078  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_199_WIDTH },
169079  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_200_CHECKER_TYPE,
169080  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_200_WIDTH },
169081  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_201_CHECKER_TYPE,
169082  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_201_WIDTH },
169083  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_202_CHECKER_TYPE,
169084  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_202_WIDTH },
169085  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_203_CHECKER_TYPE,
169086  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_203_WIDTH },
169087  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_204_CHECKER_TYPE,
169088  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_204_WIDTH },
169089  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_205_CHECKER_TYPE,
169090  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_205_WIDTH },
169091  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_206_CHECKER_TYPE,
169092  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_206_WIDTH },
169093  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_207_CHECKER_TYPE,
169094  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_207_WIDTH },
169095  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_208_CHECKER_TYPE,
169096  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_208_WIDTH },
169097  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_209_CHECKER_TYPE,
169098  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_209_WIDTH },
169099  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_210_CHECKER_TYPE,
169100  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_210_WIDTH },
169101  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_211_CHECKER_TYPE,
169102  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_211_WIDTH },
169103  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_212_CHECKER_TYPE,
169104  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_212_WIDTH },
169105  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_213_CHECKER_TYPE,
169106  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_213_WIDTH },
169107  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_214_CHECKER_TYPE,
169108  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_214_WIDTH },
169109  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_215_CHECKER_TYPE,
169110  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_215_WIDTH },
169111  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_216_CHECKER_TYPE,
169112  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_216_WIDTH },
169113  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_217_CHECKER_TYPE,
169114  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_217_WIDTH },
169115  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_218_CHECKER_TYPE,
169116  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_218_WIDTH },
169117  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_219_CHECKER_TYPE,
169118  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_219_WIDTH },
169119  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_220_CHECKER_TYPE,
169120  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_220_WIDTH },
169121  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_221_CHECKER_TYPE,
169122  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_221_WIDTH },
169123  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_222_CHECKER_TYPE,
169124  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_222_WIDTH },
169125  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_223_CHECKER_TYPE,
169126  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_223_WIDTH },
169127  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_224_CHECKER_TYPE,
169128  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_224_WIDTH },
169129  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_225_CHECKER_TYPE,
169130  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_225_WIDTH },
169131  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_226_CHECKER_TYPE,
169132  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_226_WIDTH },
169133  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_227_CHECKER_TYPE,
169134  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_227_WIDTH },
169135  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_228_CHECKER_TYPE,
169136  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_228_WIDTH },
169137  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_229_CHECKER_TYPE,
169138  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_229_WIDTH },
169139  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_230_CHECKER_TYPE,
169140  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_230_WIDTH },
169141  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_231_CHECKER_TYPE,
169142  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_231_WIDTH },
169143  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_232_CHECKER_TYPE,
169144  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_232_WIDTH },
169145  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_233_CHECKER_TYPE,
169146  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_233_WIDTH },
169147  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_234_CHECKER_TYPE,
169148  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_234_WIDTH },
169149  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_235_CHECKER_TYPE,
169150  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_235_WIDTH },
169151  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_236_CHECKER_TYPE,
169152  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_236_WIDTH },
169153  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_237_CHECKER_TYPE,
169154  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_237_WIDTH },
169155  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_238_CHECKER_TYPE,
169156  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_238_WIDTH },
169157  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_239_CHECKER_TYPE,
169158  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_239_WIDTH },
169159  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_240_CHECKER_TYPE,
169160  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_240_WIDTH },
169161  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_241_CHECKER_TYPE,
169162  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_241_WIDTH },
169163  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_242_CHECKER_TYPE,
169164  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_242_WIDTH },
169165  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_243_CHECKER_TYPE,
169166  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_243_WIDTH },
169167  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_244_CHECKER_TYPE,
169168  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_244_WIDTH },
169169  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_245_CHECKER_TYPE,
169170  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_245_WIDTH },
169171  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_246_CHECKER_TYPE,
169172  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_246_WIDTH },
169173  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_247_CHECKER_TYPE,
169174  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_247_WIDTH },
169175  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_248_CHECKER_TYPE,
169176  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_248_WIDTH },
169177  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_249_CHECKER_TYPE,
169178  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_249_WIDTH },
169179  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_250_CHECKER_TYPE,
169180  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_250_WIDTH },
169181  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_251_CHECKER_TYPE,
169182  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_251_WIDTH },
169183  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_252_CHECKER_TYPE,
169184  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_252_WIDTH },
169185  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_253_CHECKER_TYPE,
169186  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_253_WIDTH },
169187  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_254_CHECKER_TYPE,
169188  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_254_WIDTH },
169189  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_255_CHECKER_TYPE,
169190  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_GROUP_255_WIDTH },
169191 };
169192 
169198 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS] =
169199 {
169200  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_0_CHECKER_TYPE,
169201  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_0_WIDTH },
169202  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_1_CHECKER_TYPE,
169203  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_1_WIDTH },
169204  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_2_CHECKER_TYPE,
169205  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_2_WIDTH },
169206  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_3_CHECKER_TYPE,
169207  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_3_WIDTH },
169208  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_4_CHECKER_TYPE,
169209  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_4_WIDTH },
169210  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_5_CHECKER_TYPE,
169211  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_5_WIDTH },
169212  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_6_CHECKER_TYPE,
169213  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_6_WIDTH },
169214  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_7_CHECKER_TYPE,
169215  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_7_WIDTH },
169216  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_8_CHECKER_TYPE,
169217  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_8_WIDTH },
169218  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_9_CHECKER_TYPE,
169219  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_9_WIDTH },
169220  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_10_CHECKER_TYPE,
169221  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_10_WIDTH },
169222  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_11_CHECKER_TYPE,
169223  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_11_WIDTH },
169224  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_12_CHECKER_TYPE,
169225  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_12_WIDTH },
169226  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_13_CHECKER_TYPE,
169227  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_13_WIDTH },
169228  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_14_CHECKER_TYPE,
169229  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_14_WIDTH },
169230  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_15_CHECKER_TYPE,
169231  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_15_WIDTH },
169232  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_16_CHECKER_TYPE,
169233  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_16_WIDTH },
169234  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_17_CHECKER_TYPE,
169235  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_17_WIDTH },
169236  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_18_CHECKER_TYPE,
169237  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_18_WIDTH },
169238  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_19_CHECKER_TYPE,
169239  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_19_WIDTH },
169240  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_20_CHECKER_TYPE,
169241  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_20_WIDTH },
169242  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_21_CHECKER_TYPE,
169243  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_21_WIDTH },
169244  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_22_CHECKER_TYPE,
169245  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_22_WIDTH },
169246  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_23_CHECKER_TYPE,
169247  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_23_WIDTH },
169248  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_24_CHECKER_TYPE,
169249  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_24_WIDTH },
169250  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_25_CHECKER_TYPE,
169251  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_25_WIDTH },
169252  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_26_CHECKER_TYPE,
169253  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_26_WIDTH },
169254  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_27_CHECKER_TYPE,
169255  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_27_WIDTH },
169256  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_28_CHECKER_TYPE,
169257  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_28_WIDTH },
169258  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_29_CHECKER_TYPE,
169259  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_29_WIDTH },
169260  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_30_CHECKER_TYPE,
169261  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_30_WIDTH },
169262  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_31_CHECKER_TYPE,
169263  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_31_WIDTH },
169264  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_32_CHECKER_TYPE,
169265  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_32_WIDTH },
169266  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_33_CHECKER_TYPE,
169267  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_33_WIDTH },
169268  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_34_CHECKER_TYPE,
169269  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_34_WIDTH },
169270  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_35_CHECKER_TYPE,
169271  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_35_WIDTH },
169272  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_36_CHECKER_TYPE,
169273  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_36_WIDTH },
169274  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_37_CHECKER_TYPE,
169275  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_37_WIDTH },
169276  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_38_CHECKER_TYPE,
169277  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_38_WIDTH },
169278  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_39_CHECKER_TYPE,
169279  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_39_WIDTH },
169280  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_40_CHECKER_TYPE,
169281  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_40_WIDTH },
169282  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_41_CHECKER_TYPE,
169283  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_41_WIDTH },
169284  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_42_CHECKER_TYPE,
169285  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_42_WIDTH },
169286  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_43_CHECKER_TYPE,
169287  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_43_WIDTH },
169288  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_44_CHECKER_TYPE,
169289  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_44_WIDTH },
169290  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_45_CHECKER_TYPE,
169291  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_45_WIDTH },
169292  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_46_CHECKER_TYPE,
169293  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_46_WIDTH },
169294  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_47_CHECKER_TYPE,
169295  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_47_WIDTH },
169296  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_48_CHECKER_TYPE,
169297  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_48_WIDTH },
169298  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_49_CHECKER_TYPE,
169299  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_49_WIDTH },
169300  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_50_CHECKER_TYPE,
169301  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_50_WIDTH },
169302  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_51_CHECKER_TYPE,
169303  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_51_WIDTH },
169304  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_52_CHECKER_TYPE,
169305  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_52_WIDTH },
169306  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_53_CHECKER_TYPE,
169307  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_53_WIDTH },
169308  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_54_CHECKER_TYPE,
169309  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_54_WIDTH },
169310  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_55_CHECKER_TYPE,
169311  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_55_WIDTH },
169312  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_56_CHECKER_TYPE,
169313  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_56_WIDTH },
169314  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_57_CHECKER_TYPE,
169315  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_57_WIDTH },
169316  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_58_CHECKER_TYPE,
169317  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_58_WIDTH },
169318  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_59_CHECKER_TYPE,
169319  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_59_WIDTH },
169320  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_60_CHECKER_TYPE,
169321  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_60_WIDTH },
169322  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_61_CHECKER_TYPE,
169323  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_61_WIDTH },
169324  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_62_CHECKER_TYPE,
169325  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_62_WIDTH },
169326  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_63_CHECKER_TYPE,
169327  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_63_WIDTH },
169328  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_64_CHECKER_TYPE,
169329  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_64_WIDTH },
169330  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_65_CHECKER_TYPE,
169331  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_65_WIDTH },
169332  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_66_CHECKER_TYPE,
169333  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_66_WIDTH },
169334  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_67_CHECKER_TYPE,
169335  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_67_WIDTH },
169336  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_68_CHECKER_TYPE,
169337  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_68_WIDTH },
169338  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_69_CHECKER_TYPE,
169339  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_69_WIDTH },
169340  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_70_CHECKER_TYPE,
169341  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_70_WIDTH },
169342  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_71_CHECKER_TYPE,
169343  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_71_WIDTH },
169344  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_72_CHECKER_TYPE,
169345  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_72_WIDTH },
169346  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_73_CHECKER_TYPE,
169347  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_73_WIDTH },
169348  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_74_CHECKER_TYPE,
169349  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_74_WIDTH },
169350  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_75_CHECKER_TYPE,
169351  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_75_WIDTH },
169352  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_76_CHECKER_TYPE,
169353  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_76_WIDTH },
169354  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_77_CHECKER_TYPE,
169355  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_77_WIDTH },
169356  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_78_CHECKER_TYPE,
169357  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_78_WIDTH },
169358  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_79_CHECKER_TYPE,
169359  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_79_WIDTH },
169360  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_80_CHECKER_TYPE,
169361  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_80_WIDTH },
169362  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_81_CHECKER_TYPE,
169363  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_81_WIDTH },
169364  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_82_CHECKER_TYPE,
169365  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_82_WIDTH },
169366  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_83_CHECKER_TYPE,
169367  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_83_WIDTH },
169368  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_84_CHECKER_TYPE,
169369  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_84_WIDTH },
169370  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_85_CHECKER_TYPE,
169371  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_85_WIDTH },
169372  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_86_CHECKER_TYPE,
169373  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_86_WIDTH },
169374  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_87_CHECKER_TYPE,
169375  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_87_WIDTH },
169376  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_88_CHECKER_TYPE,
169377  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_88_WIDTH },
169378  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_89_CHECKER_TYPE,
169379  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_89_WIDTH },
169380  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_90_CHECKER_TYPE,
169381  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_90_WIDTH },
169382  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_91_CHECKER_TYPE,
169383  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_91_WIDTH },
169384  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_92_CHECKER_TYPE,
169385  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_92_WIDTH },
169386  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_93_CHECKER_TYPE,
169387  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_93_WIDTH },
169388  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_94_CHECKER_TYPE,
169389  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_94_WIDTH },
169390  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_95_CHECKER_TYPE,
169391  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_95_WIDTH },
169392  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_96_CHECKER_TYPE,
169393  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_96_WIDTH },
169394  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_97_CHECKER_TYPE,
169395  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_97_WIDTH },
169396  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_98_CHECKER_TYPE,
169397  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_98_WIDTH },
169398  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_99_CHECKER_TYPE,
169399  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_99_WIDTH },
169400  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_100_CHECKER_TYPE,
169401  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_100_WIDTH },
169402  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_101_CHECKER_TYPE,
169403  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_101_WIDTH },
169404  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_102_CHECKER_TYPE,
169405  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_102_WIDTH },
169406  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_103_CHECKER_TYPE,
169407  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_103_WIDTH },
169408  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_104_CHECKER_TYPE,
169409  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_104_WIDTH },
169410  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_105_CHECKER_TYPE,
169411  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_105_WIDTH },
169412  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_106_CHECKER_TYPE,
169413  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_106_WIDTH },
169414  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_107_CHECKER_TYPE,
169415  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_107_WIDTH },
169416  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_108_CHECKER_TYPE,
169417  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_108_WIDTH },
169418  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_109_CHECKER_TYPE,
169419  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_109_WIDTH },
169420  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_110_CHECKER_TYPE,
169421  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_110_WIDTH },
169422  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_111_CHECKER_TYPE,
169423  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_111_WIDTH },
169424  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_112_CHECKER_TYPE,
169425  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_112_WIDTH },
169426  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_113_CHECKER_TYPE,
169427  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_113_WIDTH },
169428  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_114_CHECKER_TYPE,
169429  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_114_WIDTH },
169430  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_115_CHECKER_TYPE,
169431  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_115_WIDTH },
169432  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_116_CHECKER_TYPE,
169433  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_116_WIDTH },
169434  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_117_CHECKER_TYPE,
169435  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_117_WIDTH },
169436  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_118_CHECKER_TYPE,
169437  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_118_WIDTH },
169438  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_119_CHECKER_TYPE,
169439  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_119_WIDTH },
169440  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_120_CHECKER_TYPE,
169441  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_120_WIDTH },
169442  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_121_CHECKER_TYPE,
169443  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_121_WIDTH },
169444  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_122_CHECKER_TYPE,
169445  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_122_WIDTH },
169446  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_123_CHECKER_TYPE,
169447  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_123_WIDTH },
169448  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_124_CHECKER_TYPE,
169449  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_124_WIDTH },
169450  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_125_CHECKER_TYPE,
169451  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_125_WIDTH },
169452  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_126_CHECKER_TYPE,
169453  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_126_WIDTH },
169454  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_127_CHECKER_TYPE,
169455  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_127_WIDTH },
169456  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_128_CHECKER_TYPE,
169457  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_128_WIDTH },
169458  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_129_CHECKER_TYPE,
169459  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_129_WIDTH },
169460  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_130_CHECKER_TYPE,
169461  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_130_WIDTH },
169462  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_131_CHECKER_TYPE,
169463  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_131_WIDTH },
169464  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_132_CHECKER_TYPE,
169465  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_132_WIDTH },
169466  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_133_CHECKER_TYPE,
169467  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_133_WIDTH },
169468  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_134_CHECKER_TYPE,
169469  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_134_WIDTH },
169470  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_135_CHECKER_TYPE,
169471  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_135_WIDTH },
169472  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_136_CHECKER_TYPE,
169473  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_136_WIDTH },
169474  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_137_CHECKER_TYPE,
169475  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_137_WIDTH },
169476  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_138_CHECKER_TYPE,
169477  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_138_WIDTH },
169478  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_139_CHECKER_TYPE,
169479  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_139_WIDTH },
169480  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_140_CHECKER_TYPE,
169481  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_140_WIDTH },
169482  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_141_CHECKER_TYPE,
169483  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_141_WIDTH },
169484  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_142_CHECKER_TYPE,
169485  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_142_WIDTH },
169486  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_143_CHECKER_TYPE,
169487  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_143_WIDTH },
169488  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_144_CHECKER_TYPE,
169489  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_144_WIDTH },
169490  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_145_CHECKER_TYPE,
169491  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_145_WIDTH },
169492  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_146_CHECKER_TYPE,
169493  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_146_WIDTH },
169494  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_147_CHECKER_TYPE,
169495  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_147_WIDTH },
169496  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_148_CHECKER_TYPE,
169497  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_148_WIDTH },
169498  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_149_CHECKER_TYPE,
169499  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_149_WIDTH },
169500  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_150_CHECKER_TYPE,
169501  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_150_WIDTH },
169502  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_151_CHECKER_TYPE,
169503  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_151_WIDTH },
169504  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_152_CHECKER_TYPE,
169505  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_152_WIDTH },
169506  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_153_CHECKER_TYPE,
169507  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_153_WIDTH },
169508  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_154_CHECKER_TYPE,
169509  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_154_WIDTH },
169510  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_155_CHECKER_TYPE,
169511  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_155_WIDTH },
169512  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_156_CHECKER_TYPE,
169513  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_156_WIDTH },
169514  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_157_CHECKER_TYPE,
169515  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_157_WIDTH },
169516  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_158_CHECKER_TYPE,
169517  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_158_WIDTH },
169518  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_159_CHECKER_TYPE,
169519  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_159_WIDTH },
169520  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_160_CHECKER_TYPE,
169521  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_160_WIDTH },
169522  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_161_CHECKER_TYPE,
169523  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_161_WIDTH },
169524  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_162_CHECKER_TYPE,
169525  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_162_WIDTH },
169526  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_163_CHECKER_TYPE,
169527  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_163_WIDTH },
169528  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_164_CHECKER_TYPE,
169529  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_164_WIDTH },
169530  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_165_CHECKER_TYPE,
169531  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_165_WIDTH },
169532  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_166_CHECKER_TYPE,
169533  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_166_WIDTH },
169534  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_167_CHECKER_TYPE,
169535  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_167_WIDTH },
169536  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_168_CHECKER_TYPE,
169537  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_168_WIDTH },
169538  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_169_CHECKER_TYPE,
169539  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_169_WIDTH },
169540  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_170_CHECKER_TYPE,
169541  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_170_WIDTH },
169542  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_171_CHECKER_TYPE,
169543  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_171_WIDTH },
169544  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_172_CHECKER_TYPE,
169545  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_172_WIDTH },
169546  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_173_CHECKER_TYPE,
169547  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_173_WIDTH },
169548  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_174_CHECKER_TYPE,
169549  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_174_WIDTH },
169550  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_175_CHECKER_TYPE,
169551  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_175_WIDTH },
169552  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_176_CHECKER_TYPE,
169553  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_176_WIDTH },
169554  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_177_CHECKER_TYPE,
169555  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_177_WIDTH },
169556  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_178_CHECKER_TYPE,
169557  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_178_WIDTH },
169558  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_179_CHECKER_TYPE,
169559  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_179_WIDTH },
169560  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_180_CHECKER_TYPE,
169561  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_180_WIDTH },
169562  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_181_CHECKER_TYPE,
169563  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_181_WIDTH },
169564  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_182_CHECKER_TYPE,
169565  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_182_WIDTH },
169566  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_183_CHECKER_TYPE,
169567  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_183_WIDTH },
169568  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_184_CHECKER_TYPE,
169569  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_184_WIDTH },
169570  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_185_CHECKER_TYPE,
169571  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_185_WIDTH },
169572  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_186_CHECKER_TYPE,
169573  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_186_WIDTH },
169574  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_187_CHECKER_TYPE,
169575  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_187_WIDTH },
169576  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_188_CHECKER_TYPE,
169577  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_188_WIDTH },
169578  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_189_CHECKER_TYPE,
169579  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_189_WIDTH },
169580  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_190_CHECKER_TYPE,
169581  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_190_WIDTH },
169582  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_191_CHECKER_TYPE,
169583  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_191_WIDTH },
169584  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_192_CHECKER_TYPE,
169585  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_192_WIDTH },
169586  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_193_CHECKER_TYPE,
169587  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_193_WIDTH },
169588  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_194_CHECKER_TYPE,
169589  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_194_WIDTH },
169590  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_195_CHECKER_TYPE,
169591  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_195_WIDTH },
169592  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_196_CHECKER_TYPE,
169593  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_196_WIDTH },
169594  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_197_CHECKER_TYPE,
169595  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_197_WIDTH },
169596  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_198_CHECKER_TYPE,
169597  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_198_WIDTH },
169598  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_199_CHECKER_TYPE,
169599  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_199_WIDTH },
169600  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_200_CHECKER_TYPE,
169601  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_200_WIDTH },
169602  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_201_CHECKER_TYPE,
169603  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_201_WIDTH },
169604  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_202_CHECKER_TYPE,
169605  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_202_WIDTH },
169606  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_203_CHECKER_TYPE,
169607  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_203_WIDTH },
169608  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_204_CHECKER_TYPE,
169609  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_204_WIDTH },
169610  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_205_CHECKER_TYPE,
169611  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_205_WIDTH },
169612  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_206_CHECKER_TYPE,
169613  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_206_WIDTH },
169614  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_207_CHECKER_TYPE,
169615  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_207_WIDTH },
169616  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_208_CHECKER_TYPE,
169617  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_208_WIDTH },
169618  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_209_CHECKER_TYPE,
169619  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_209_WIDTH },
169620  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_210_CHECKER_TYPE,
169621  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_210_WIDTH },
169622  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_211_CHECKER_TYPE,
169623  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_211_WIDTH },
169624  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_212_CHECKER_TYPE,
169625  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_212_WIDTH },
169626  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_213_CHECKER_TYPE,
169627  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_213_WIDTH },
169628  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_214_CHECKER_TYPE,
169629  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_214_WIDTH },
169630  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_215_CHECKER_TYPE,
169631  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_215_WIDTH },
169632  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_216_CHECKER_TYPE,
169633  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_216_WIDTH },
169634  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_217_CHECKER_TYPE,
169635  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_217_WIDTH },
169636  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_218_CHECKER_TYPE,
169637  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_218_WIDTH },
169638  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_219_CHECKER_TYPE,
169639  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_219_WIDTH },
169640  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_220_CHECKER_TYPE,
169641  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_220_WIDTH },
169642  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_221_CHECKER_TYPE,
169643  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_221_WIDTH },
169644  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_222_CHECKER_TYPE,
169645  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_222_WIDTH },
169646  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_223_CHECKER_TYPE,
169647  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_223_WIDTH },
169648  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_224_CHECKER_TYPE,
169649  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_224_WIDTH },
169650  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_225_CHECKER_TYPE,
169651  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_225_WIDTH },
169652  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_226_CHECKER_TYPE,
169653  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_226_WIDTH },
169654  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_227_CHECKER_TYPE,
169655  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_227_WIDTH },
169656  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_228_CHECKER_TYPE,
169657  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_228_WIDTH },
169658  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_229_CHECKER_TYPE,
169659  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_229_WIDTH },
169660  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_230_CHECKER_TYPE,
169661  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_230_WIDTH },
169662  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_231_CHECKER_TYPE,
169663  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_GROUP_231_WIDTH },
169664 };
169665 
169671 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS] =
169672 {
169673  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
169674  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
169675  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
169676  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
169677  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
169678  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
169679  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
169680  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
169681  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
169682  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
169683  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
169684  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
169685  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
169686  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
169687  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
169688  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
169689  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
169690  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
169691  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
169692  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
169693  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
169694  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
169695  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
169696  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
169697  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
169698  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
169699  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
169700  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
169701  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
169702  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
169703  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
169704  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
169705  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
169706  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
169707  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
169708  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
169709  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
169710  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
169711  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
169712  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
169713  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
169714  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
169715  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
169716  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
169717  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
169718  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
169719  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
169720  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
169721  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
169722  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
169723  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
169724  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
169725  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
169726  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
169727  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
169728  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
169729  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
169730  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
169731  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
169732  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
169733  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
169734  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
169735  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
169736  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
169737  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
169738  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
169739  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
169740  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
169741  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
169742  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
169743  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
169744  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
169745  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
169746  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
169747  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
169748  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
169749  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
169750  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
169751  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
169752  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
169753  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
169754  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
169755  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
169756  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
169757  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
169758  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
169759  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
169760  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
169761  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
169762  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
169763  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
169764  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
169765  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
169766  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
169767  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
169768  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
169769  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
169770  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
169771  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
169772  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
169773  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
169774  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
169775  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
169776  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
169777  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
169778  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
169779  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
169780  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
169781  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
169782  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
169783  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
169784  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
169785  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
169786  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
169787  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
169788  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
169789  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
169790  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
169791  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
169792  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
169793  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
169794  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
169795  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
169796  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
169797  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
169798  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
169799  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
169800  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
169801  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
169802  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
169803  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
169804  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
169805  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
169806  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
169807  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
169808  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
169809  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
169810  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
169811  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
169812  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
169813  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
169814  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
169815  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
169816  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
169817  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
169818  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
169819  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
169820  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
169821  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
169822  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
169823  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
169824  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
169825  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
169826  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
169827  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
169828  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
169829  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
169830  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
169831  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
169832  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
169833  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
169834  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
169835  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
169836  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
169837  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
169838  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
169839  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
169840  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
169841  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
169842  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
169843  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
169844  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
169845  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
169846  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
169847  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
169848  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
169849  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
169850  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
169851  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
169852  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
169853  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
169854  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
169855  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
169856  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
169857  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
169858  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
169859  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
169860  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
169861  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
169862  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
169863  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
169864  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
169865  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
169866  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
169867  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
169868  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
169869  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
169870  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
169871  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
169872  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
169873  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
169874  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
169875  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
169876  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
169877  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
169878  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
169879  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
169880  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
169881  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
169882  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
169883  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
169884  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
169885  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
169886  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
169887  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
169888  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
169889  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
169890  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
169891  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
169892  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
169893  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
169894  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
169895  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
169896  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
169897  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
169898  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
169899  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
169900  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
169901  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
169902  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
169903  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
169904  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
169905  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
169906  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
169907  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
169908  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
169909  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
169910  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
169911  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
169912  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
169913  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
169914  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
169915  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
169916  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
169917  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
169918  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
169919  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
169920  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
169921  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
169922  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
169923  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
169924  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
169925  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
169926  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
169927  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
169928  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
169929  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
169930  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
169931  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
169932  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
169933  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
169934  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
169935  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
169936  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
169937  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
169938  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
169939  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
169940  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
169941  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
169942  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
169943  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
169944  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
169945  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
169946  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
169947  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
169948  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
169949  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
169950  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
169951  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
169952  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
169953  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
169954  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
169955  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
169956  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
169957  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
169958  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
169959  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
169960  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
169961  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
169962  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
169963  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
169964  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
169965  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
169966  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
169967  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
169968  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
169969  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
169970  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
169971  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
169972  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
169973  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
169974  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
169975  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
169976  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
169977  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
169978  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
169979  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
169980  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
169981  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
169982  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
169983  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
169984  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
169985  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
169986  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
169987  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
169988  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
169989  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
169990  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
169991  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
169992  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
169993  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
169994  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
169995  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
169996  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
169997  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
169998  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
169999  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
170000  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
170001  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
170002  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
170003  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
170004  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
170005  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
170006  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
170007  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
170008  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
170009  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
170010  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
170011  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
170012  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
170013  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
170014  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
170015  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
170016  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
170017  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
170018  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
170019  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
170020  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
170021  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
170022  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
170023  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
170024  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
170025  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
170026  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
170027  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
170028  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
170029  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
170030  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
170031  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
170032  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
170033  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
170034  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
170035  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
170036  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
170037  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
170038  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
170039  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
170040  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
170041  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
170042  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
170043  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
170044  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
170045  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
170046  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
170047  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
170048  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
170049  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
170050  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
170051  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
170052  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
170053  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
170054  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
170055  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
170056  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
170057  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
170058  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
170059  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
170060  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
170061  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
170062  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
170063  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
170064  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
170065  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
170066  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
170067  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
170068  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
170069  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
170070  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
170071  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
170072  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
170073  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
170074  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
170075  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
170076  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
170077  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
170078  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
170079  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
170080  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
170081  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
170082  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
170083  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
170084  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
170085  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
170086  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
170087  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
170088  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
170089  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
170090  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
170091  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
170092  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
170093  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
170094  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
170095  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
170096  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
170097  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
170098  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
170099  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
170100  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
170101  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
170102  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
170103  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
170104  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
170105  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
170106  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
170107  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
170108  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
170109  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
170110  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
170111  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
170112  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
170113  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
170114  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
170115  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
170116  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
170117  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
170118  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
170119  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
170120  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
170121  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
170122  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
170123  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
170124  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
170125  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
170126  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
170127  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
170128  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
170129  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
170130  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
170131  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
170132  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
170133  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
170134  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
170135  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
170136  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
170137  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
170138  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
170139  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
170140  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
170141  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
170142  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
170143  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
170144  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
170145  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
170146  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
170147  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
170148  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
170149  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
170150  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
170151  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
170152  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
170153  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
170154  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
170155  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
170156  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
170157  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
170158  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
170159  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
170160  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
170161  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
170162  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
170163  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
170164  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
170165  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
170166  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
170167  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
170168  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
170169  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
170170  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
170171  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
170172  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
170173  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
170174  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
170175  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
170176  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
170177  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
170178  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
170179  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
170180  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
170181  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
170182  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
170183  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
170184  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
170185 };
170186 
170192 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS] =
170193 {
170194  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
170195  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
170196  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
170197  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
170198  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
170199  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
170200  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
170201  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
170202  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
170203  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
170204  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
170205  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
170206  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
170207  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
170208  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
170209  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
170210  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
170211  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
170212  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
170213  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
170214  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
170215  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
170216  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
170217  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
170218  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
170219  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
170220  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
170221  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
170222  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
170223  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
170224  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
170225  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
170226  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
170227  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
170228  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
170229  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
170230  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
170231  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
170232  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
170233  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
170234  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
170235  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
170236  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
170237  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
170238  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
170239  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
170240  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
170241  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
170242  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
170243  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
170244  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
170245  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
170246  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
170247  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
170248  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
170249  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
170250  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
170251  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
170252  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
170253  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
170254  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
170255  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
170256  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
170257  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
170258  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
170259  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
170260  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
170261  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
170262  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
170263  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
170264  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
170265  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
170266  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
170267  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
170268  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
170269  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
170270  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
170271  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
170272  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
170273  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
170274  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
170275  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
170276  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
170277  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
170278  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
170279  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
170280  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
170281  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
170282  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
170283  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
170284  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
170285  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
170286  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
170287  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
170288  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
170289  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
170290  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
170291  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
170292  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
170293  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
170294  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
170295  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
170296  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
170297  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
170298  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
170299  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
170300  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
170301  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
170302  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
170303  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
170304  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
170305  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
170306  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
170307  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
170308  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
170309  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
170310  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
170311  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
170312  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
170313  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
170314  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
170315  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
170316  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
170317  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
170318  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
170319  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
170320  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
170321  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
170322  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
170323  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
170324  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
170325  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
170326  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
170327  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
170328  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
170329  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
170330  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
170331  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
170332  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
170333  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
170334  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
170335  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
170336  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
170337  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
170338  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
170339  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
170340  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
170341  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
170342  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
170343  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
170344  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
170345  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
170346  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
170347  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
170348  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
170349  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
170350  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
170351  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
170352  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
170353  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
170354  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
170355  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
170356  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
170357  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
170358  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
170359  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
170360  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
170361  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
170362  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
170363  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
170364  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
170365  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
170366  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
170367  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
170368  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
170369  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
170370  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
170371  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
170372  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
170373  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
170374  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
170375  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
170376  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
170377  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
170378  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
170379  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
170380  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
170381  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
170382  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
170383  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
170384  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
170385  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
170386  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
170387  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
170388  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
170389  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
170390  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
170391  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
170392  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
170393  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
170394  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
170395  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
170396  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
170397  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
170398  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
170399  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
170400  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
170401  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
170402  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
170403  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
170404  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
170405  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
170406  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
170407  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
170408  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
170409  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
170410  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
170411  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
170412  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
170413  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
170414  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
170415  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
170416  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
170417  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
170418  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
170419  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
170420  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
170421  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
170422  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
170423  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
170424  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
170425  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
170426  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
170427  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
170428  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
170429  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
170430  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
170431  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
170432  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
170433  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
170434  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
170435  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
170436  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
170437  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
170438  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
170439  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
170440  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
170441  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
170442  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
170443  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
170444  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
170445  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
170446  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
170447  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
170448  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
170449  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
170450  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
170451  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
170452  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
170453  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
170454  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
170455  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
170456  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
170457  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
170458  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
170459  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
170460  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
170461  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
170462  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
170463  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
170464  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
170465  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
170466  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
170467  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
170468  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
170469  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
170470  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
170471  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
170472  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
170473  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
170474  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
170475  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
170476  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
170477  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
170478  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
170479  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
170480  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
170481  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
170482  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
170483  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
170484  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
170485  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
170486  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
170487  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
170488  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
170489  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
170490  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
170491  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
170492  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
170493  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
170494  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
170495  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
170496  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
170497  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
170498  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
170499  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
170500  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
170501  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
170502  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
170503  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
170504  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
170505  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
170506  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
170507  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
170508  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
170509  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
170510  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
170511  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
170512  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
170513  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
170514  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
170515  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
170516  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
170517  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
170518  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
170519  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
170520  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
170521  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
170522  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
170523  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
170524  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
170525  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
170526  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
170527  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
170528  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
170529  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
170530  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
170531  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
170532  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
170533  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
170534  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
170535  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
170536  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
170537  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
170538  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
170539  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
170540  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
170541  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
170542  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
170543  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
170544  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
170545  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
170546  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
170547  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
170548  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
170549  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
170550  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
170551  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
170552  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
170553  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
170554  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
170555  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
170556  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
170557  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
170558  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
170559  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
170560  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
170561  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
170562  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
170563  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
170564  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
170565  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
170566  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
170567  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
170568  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
170569  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
170570  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
170571  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
170572  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
170573  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
170574  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
170575  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
170576  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
170577  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
170578  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
170579  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
170580  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
170581  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
170582  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
170583  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
170584  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
170585  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
170586  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
170587  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
170588  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
170589  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
170590  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
170591  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
170592  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
170593  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
170594  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
170595  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
170596  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
170597  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
170598  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
170599  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
170600  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
170601  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
170602  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
170603  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
170604  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
170605  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
170606  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
170607  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
170608  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
170609  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
170610  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
170611  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
170612  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
170613  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
170614  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
170615  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
170616  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
170617  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
170618  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
170619  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
170620  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
170621  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
170622  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
170623  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
170624  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
170625  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
170626  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
170627  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
170628  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
170629  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
170630  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
170631  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
170632  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
170633  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
170634  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
170635  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
170636  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
170637  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
170638  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
170639  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
170640  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
170641  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
170642  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
170643  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
170644  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
170645  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
170646  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
170647  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
170648  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
170649  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
170650  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
170651  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
170652  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
170653  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
170654  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
170655  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
170656  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
170657  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
170658  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
170659  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
170660  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
170661  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
170662  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
170663  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
170664  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
170665  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
170666  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
170667  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
170668  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
170669  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
170670  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
170671  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
170672  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
170673  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
170674  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
170675  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
170676  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
170677  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
170678  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
170679  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
170680  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
170681  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
170682  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
170683  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
170684  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
170685  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
170686  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
170687  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
170688  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
170689  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
170690  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
170691  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
170692  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
170693  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
170694  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
170695  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
170696 };
170697 
170703 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
170704 {
170705  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
170706  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
170707  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
170708  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
170709  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
170710  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
170711  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
170712  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
170713  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
170714  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
170715  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
170716  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
170717  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
170718  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
170719  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
170720  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
170721  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
170722  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
170723  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
170724  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
170725  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
170726  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
170727  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
170728  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
170729  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
170730  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
170731  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
170732  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
170733  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
170734  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
170735 };
170736 
170742 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS] =
170743 {
170744  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
170745  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
170746  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
170747  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
170748  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
170749  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
170750  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
170751  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
170752 };
170753 
170759 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
170760 {
170761  { SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
170762  SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
170763 };
170764 
170770 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
170771 {
170772  { SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
170773  SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
170774 };
170775 
170781 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
170782 {
170783  { SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
170784  SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_GROUP_0_WIDTH },
170785 };
170786 
170792 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
170793 {
170794  { SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
170795  SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_GROUP_0_WIDTH },
170796 };
170797 
170803 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
170804 {
170805  { SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
170806  SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_GROUP_0_WIDTH },
170807 };
170808 
170814 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
170815 {
170816  { SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
170817  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
170818  { SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
170819  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
170820  { SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
170821  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
170822  { SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
170823  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
170824 };
170825 
170831 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
170832 {
170833  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
170834  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
170835  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
170836  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
170837  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
170838  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
170839  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
170840  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
170841  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
170842  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
170843  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
170844  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
170845  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
170846  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
170847  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
170848  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
170849  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
170850  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
170851  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
170852  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
170853  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
170854  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
170855  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
170856  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
170857  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
170858  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
170859  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
170860  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
170861  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
170862  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
170863  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
170864  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
170865  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
170866  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
170867  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
170868  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
170869  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
170870  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
170871  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
170872  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
170873  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
170874  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
170875  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
170876  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
170877  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
170878  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
170879  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
170880  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
170881  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
170882  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
170883  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
170884  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
170885  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
170886  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
170887 };
170888 
170894 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
170895 {
170896  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
170897  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
170898  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
170899  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
170900  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
170901  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
170902  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
170903  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
170904  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
170905  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
170906  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
170907  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
170908  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
170909  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
170910  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
170911  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
170912  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
170913  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
170914  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
170915  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
170916 };
170917 
170923 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
170924 {
170925  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
170926  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
170927  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
170928  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
170929  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
170930  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
170931  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
170932  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
170933  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
170934  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
170935  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
170936  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
170937  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
170938  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
170939  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
170940  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
170941  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
170942  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
170943  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
170944  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
170945  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
170946  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
170947  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
170948  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
170949  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
170950  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
170951  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
170952  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
170953  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
170954  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
170955  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
170956  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
170957  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
170958  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
170959  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
170960  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
170961  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
170962  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
170963  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
170964  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
170965  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
170966  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
170967  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
170968  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
170969  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
170970  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
170971  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
170972  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
170973  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
170974  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
170975  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
170976  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
170977  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
170978  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
170979  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
170980  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
170981  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
170982  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
170983  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
170984  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
170985  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
170986  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
170987  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
170988  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
170989  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
170990  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
170991  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
170992  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
170993  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
170994  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
170995  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
170996  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
170997  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
170998  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
170999  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
171000  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
171001  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
171002  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
171003  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
171004  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
171005  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
171006  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
171007  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
171008  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
171009 };
171010 
171016 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171017 {
171018  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171019  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171020  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171021  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171022  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171023  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171024  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171025  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171026  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171027  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171028  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171029  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171030  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171031  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171032  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171033  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171034  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171035  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171036  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171037  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171038  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171039  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171040  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171041  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171042  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
171043  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
171044  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
171045  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
171046  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
171047  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
171048  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
171049  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
171050  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
171051  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
171052  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
171053  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
171054  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
171055  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
171056  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
171057  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
171058  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
171059  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
171060  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
171061  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
171062  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
171063  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
171064  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
171065  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
171066  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
171067  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
171068  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
171069  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
171070  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
171071  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
171072  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
171073  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
171074  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
171075  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
171076  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
171077  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
171078  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
171079  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
171080  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
171081  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
171082  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
171083  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
171084  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
171085  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
171086  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
171087  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
171088  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
171089  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
171090  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
171091  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
171092  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
171093  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
171094  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
171095  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
171096  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
171097  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
171098  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
171099  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
171100  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
171101  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
171102  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
171103  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
171104  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
171105  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
171106  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
171107  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
171108  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
171109  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
171110  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
171111  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
171112  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
171113  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
171114  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
171115  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
171116  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
171117  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
171118  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
171119  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
171120  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
171121  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
171122  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
171123  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
171124  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
171125  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
171126  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
171127  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
171128  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
171129  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
171130  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
171131  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
171132 };
171133 
171139 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS] =
171140 {
171141  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
171142  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
171143  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
171144  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
171145  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
171146  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
171147  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
171148  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
171149  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
171150  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
171151  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
171152  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
171153  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
171154  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
171155  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
171156  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
171157  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
171158  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
171159  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
171160  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
171161  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
171162  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
171163  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
171164  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
171165  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
171166  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
171167  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
171168  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
171169  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
171170  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
171171 };
171172 
171178 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171179 {
171180  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171181  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171182  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171183  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171184  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171185  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171186  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171187  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171188  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171189  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171190  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171191  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171192  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171193  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171194  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171195  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171196  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171197  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171198  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171199  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171200  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171201  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171202  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171203  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171204  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
171205  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
171206  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
171207  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
171208  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
171209  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
171210  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
171211  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
171212  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
171213  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
171214  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
171215  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
171216  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
171217  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
171218  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
171219  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
171220  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
171221  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
171222  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
171223  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
171224  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
171225  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
171226  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
171227  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
171228  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
171229  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
171230  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
171231  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
171232  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
171233  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
171234  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
171235  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
171236  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
171237  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
171238  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
171239  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
171240  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
171241  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
171242  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
171243  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
171244  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
171245  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
171246  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
171247  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
171248  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
171249  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
171250  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
171251  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
171252  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
171253  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
171254  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
171255  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
171256  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
171257  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
171258  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
171259  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
171260  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
171261  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
171262  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
171263  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
171264  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
171265  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
171266  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
171267  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
171268  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
171269  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
171270  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
171271  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
171272  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
171273  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
171274  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
171275  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
171276  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
171277  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
171278  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
171279  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
171280  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
171281  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
171282  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
171283  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
171284  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
171285  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
171286  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
171287  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
171288  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
171289  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
171290  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
171291  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
171292  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
171293  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
171294 };
171295 
171301 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171302 {
171303  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171304  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171305  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171306  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171307  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171308  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171309  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171310  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171311  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171312  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171313  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171314  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171315  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171316  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171317  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171318  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171319  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171320  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171321  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171322  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171323  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171324  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171325  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171326  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171327  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
171328  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
171329  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
171330  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
171331  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
171332  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
171333  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
171334  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
171335  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
171336  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
171337  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
171338  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
171339 };
171340 
171346 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171347 {
171348  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171349  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171350  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171351  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171352  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171353  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171354  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171355  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171356  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171357  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171358  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171359  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171360  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171361  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171362  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171363  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171364  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171365  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171366  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171367  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171368  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171369  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171370  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171371  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171372  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
171373  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
171374  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
171375  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
171376  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
171377  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
171378  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
171379  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
171380  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
171381  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
171382  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
171383  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
171384  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
171385  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
171386  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
171387  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
171388  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
171389  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
171390  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
171391  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
171392  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
171393  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
171394  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
171395  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
171396  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
171397  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
171398  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
171399  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
171400  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
171401  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
171402  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
171403  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
171404  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
171405  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
171406  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
171407  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
171408  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
171409  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
171410  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
171411  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
171412  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
171413  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
171414  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
171415  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
171416  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
171417  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
171418  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
171419  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
171420  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
171421  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
171422  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
171423  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
171424  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
171425  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
171426  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
171427  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
171428  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
171429  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
171430  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
171431  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
171432  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
171433  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
171434  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
171435  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
171436  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
171437  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
171438  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
171439  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
171440  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
171441  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
171442  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
171443  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
171444  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
171445  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
171446  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
171447  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
171448  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
171449  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
171450  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
171451  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
171452  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
171453  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
171454  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
171455  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
171456  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
171457  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
171458  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
171459  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
171460  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
171461  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
171462  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
171463  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
171464  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
171465  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
171466  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
171467  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
171468  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
171469  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
171470  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
171471  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
171472  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
171473  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
171474  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
171475  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
171476  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
171477  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
171478  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
171479  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
171480  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
171481  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
171482  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
171483  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
171484  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
171485  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
171486  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
171487  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
171488  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
171489  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
171490  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
171491  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
171492  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
171493  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
171494  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
171495  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
171496  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
171497  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
171498  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
171499  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
171500  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
171501  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
171502  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
171503  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
171504  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
171505  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
171506  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
171507  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
171508  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
171509  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
171510  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
171511  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
171512  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
171513  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
171514 };
171515 
171521 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171522 {
171523  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171524  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171525  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171526  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171527  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171528  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171529  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171530  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171531  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171532  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171533  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171534  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171535  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171536  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171537  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171538  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171539  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171540  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171541  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171542  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171543  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171544  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171545  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171546  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171547  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
171548  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
171549  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
171550  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
171551  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
171552  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
171553  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
171554  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
171555  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
171556  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
171557  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
171558  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
171559  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
171560  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
171561  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
171562  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
171563  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
171564  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
171565  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
171566  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
171567  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
171568  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
171569  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
171570  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
171571  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
171572  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
171573  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
171574  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
171575  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
171576  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
171577  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
171578  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
171579  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
171580  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
171581  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
171582  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
171583  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
171584  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
171585  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
171586  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
171587  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
171588  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
171589  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
171590  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
171591  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
171592  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
171593  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
171594  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
171595  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
171596  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
171597  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
171598  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
171599  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
171600  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
171601  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
171602  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
171603  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
171604  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
171605  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
171606  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
171607 };
171608 
171614 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171615 {
171616  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171617  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171618  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171619  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171620  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171621  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171622  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171623  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171624  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171625  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171626  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171627  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171628  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171629  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171630  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171631  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171632  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171633  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171634  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171635  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171636  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171637  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171638  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171639  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171640 };
171641 
171647 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS] =
171648 {
171649  { SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
171650  SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
171651 };
171652 
171658 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171659 {
171660  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171661  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171662  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171663  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171664  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171665  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171666  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171667  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171668  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171669  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171670  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171671  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171672  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171673  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171674  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171675  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171676  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171677  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171678  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171679  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171680  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171681  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171682  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171683  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171684  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
171685  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
171686  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
171687  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
171688  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
171689  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
171690  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
171691  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
171692  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
171693  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
171694  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
171695  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
171696  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
171697  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
171698  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
171699  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
171700  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
171701  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
171702  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
171703  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
171704  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
171705  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
171706  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
171707  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
171708  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
171709  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
171710  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
171711  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
171712  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
171713  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
171714  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
171715  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
171716  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
171717  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
171718  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
171719  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
171720  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
171721  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
171722  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
171723  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
171724 };
171725 
171731 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171732 {
171733  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171734  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171735  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171736  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171737  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171738  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171739  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171740  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171741  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
171742  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
171743  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
171744  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
171745  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
171746  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
171747  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
171748  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
171749  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
171750  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
171751  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
171752  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
171753  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
171754  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
171755  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
171756  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
171757  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
171758  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
171759  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
171760  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
171761  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
171762  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
171763  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
171764  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
171765  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
171766  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
171767  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
171768  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
171769  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
171770  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
171771  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
171772  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
171773  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
171774  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
171775  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
171776  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
171777  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
171778  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
171779  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
171780  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
171781  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
171782  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
171783  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
171784  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
171785  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
171786  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
171787  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
171788  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
171789  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
171790  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
171791  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
171792  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
171793  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
171794  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
171795 };
171796 
171802 static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS] =
171803 {
171804  { SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
171805  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
171806  { SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
171807  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
171808  { SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
171809  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
171810  { SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
171811  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
171812 };
171813 
171818 static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_10_MemEntries[SDL_COMPUTE_CLUSTER0_10_RAM_IDS_TOTAL_ENTRIES] =
171819 {
171820  { SDL_COMPUTE_CLUSTER0_ICB_RAMECC_RAM_ID, 0u,
171821  SDL_COMPUTE_CLUSTER0_ICB_RAMECC_RAM_SIZE, 4u,
171822  SDL_COMPUTE_CLUSTER0_ICB_RAMECC_ROW_WIDTH, ((bool)false) },
171823  { SDL_COMPUTE_CLUSTER0_ITE_RAMECC_RAM_ID, 0u,
171824  SDL_COMPUTE_CLUSTER0_ITE_RAMECC_RAM_SIZE, 4u,
171825  SDL_COMPUTE_CLUSTER0_ITE_RAMECC_ROW_WIDTH, ((bool)false) },
171826  { SDL_COMPUTE_CLUSTER0_LPI_RAMECC_RAM_ID, 0u,
171827  SDL_COMPUTE_CLUSTER0_LPI_RAMECC_RAM_SIZE, 4u,
171828  SDL_COMPUTE_CLUSTER0_LPI_RAMECC_ROW_WIDTH, ((bool)false) },
171829  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
171830  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
171831  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
171832 };
171833 
171839 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS] =
171840 {
171841  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
171842  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_0_WIDTH },
171843  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
171844  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_1_WIDTH },
171845  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
171846  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_2_WIDTH },
171847  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
171848  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_3_WIDTH },
171849  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
171850  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_4_WIDTH },
171851  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
171852  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_5_WIDTH },
171853  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
171854  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_6_WIDTH },
171855  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
171856  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_7_WIDTH },
171857  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
171858  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_8_WIDTH },
171859  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
171860  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_9_WIDTH },
171861  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
171862  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_10_WIDTH },
171863  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
171864  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_11_WIDTH },
171865  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
171866  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_12_WIDTH },
171867  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
171868  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_13_WIDTH },
171869  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
171870  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_14_WIDTH },
171871  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
171872  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_15_WIDTH },
171873  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
171874  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_16_WIDTH },
171875  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
171876  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_17_WIDTH },
171877  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
171878  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_18_WIDTH },
171879  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
171880  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_19_WIDTH },
171881  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
171882  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_20_WIDTH },
171883  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
171884  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_21_WIDTH },
171885  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
171886  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_22_WIDTH },
171887  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
171888  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_23_WIDTH },
171889  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
171890  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_24_WIDTH },
171891  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
171892  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_25_WIDTH },
171893  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
171894  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_26_WIDTH },
171895  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
171896  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_27_WIDTH },
171897  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
171898  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_28_WIDTH },
171899  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
171900  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_29_WIDTH },
171901  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
171902  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_GROUP_30_WIDTH },
171903 };
171904 
171910 static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS] =
171911 {
171912  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
171913  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_0_WIDTH },
171914  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
171915  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_1_WIDTH },
171916  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
171917  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_2_WIDTH },
171918  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
171919  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_3_WIDTH },
171920  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
171921  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_4_WIDTH },
171922  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
171923  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_5_WIDTH },
171924  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
171925  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_6_WIDTH },
171926  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
171927  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_7_WIDTH },
171928  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
171929  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_8_WIDTH },
171930  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
171931  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_9_WIDTH },
171932  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
171933  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_10_WIDTH },
171934  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
171935  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_11_WIDTH },
171936  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
171937  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_12_WIDTH },
171938  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
171939  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_13_WIDTH },
171940  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
171941  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_14_WIDTH },
171942  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
171943  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_15_WIDTH },
171944  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
171945  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_16_WIDTH },
171946  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
171947  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_17_WIDTH },
171948  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
171949  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_18_WIDTH },
171950  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
171951  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_19_WIDTH },
171952  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
171953  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_20_WIDTH },
171954  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
171955  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_21_WIDTH },
171956  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
171957  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_22_WIDTH },
171958  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
171959  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_23_WIDTH },
171960  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
171961  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_24_WIDTH },
171962  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
171963  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_25_WIDTH },
171964  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
171965  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_26_WIDTH },
171966  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
171967  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_27_WIDTH },
171968  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
171969  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_28_WIDTH },
171970  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
171971  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_29_WIDTH },
171972  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
171973  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_30_WIDTH },
171974  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
171975  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_31_WIDTH },
171976  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
171977  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_32_WIDTH },
171978  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
171979  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_33_WIDTH },
171980  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
171981  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_34_WIDTH },
171982  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
171983  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_35_WIDTH },
171984  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
171985  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_36_WIDTH },
171986  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
171987  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_37_WIDTH },
171988  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
171989  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_38_WIDTH },
171990  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
171991  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_GROUP_39_WIDTH },
171992 };
171993 
171998 static const SDL_MemConfig_t SDL_CPSW0_0_MemEntries[SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES] =
171999 {
172000  { SDL_CPSW0_ALE_RAM_RAM_ID, 0u,
172001  SDL_CPSW0_ALE_RAM_RAM_SIZE, 4u,
172002  SDL_CPSW0_ALE_RAM_ROW_WIDTH, ((bool)false) },
172003  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL1_RAM_ID, 0u,
172004  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL1_RAM_SIZE, 4u,
172005  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL1_ROW_WIDTH, ((bool)false) },
172006  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL2_RAM_ID, 0u,
172007  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL2_RAM_SIZE, 4u,
172008  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL2_ROW_WIDTH, ((bool)false) },
172009  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
172010  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL3_RAM_SIZE, 4u,
172011  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)false) },
172012  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
172013  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL4_RAM_SIZE, 4u,
172014  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)false) },
172015  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL5_RAM_ID, 0u,
172016  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL5_RAM_SIZE, 4u,
172017  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL5_ROW_WIDTH, ((bool)false) },
172018  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL6_RAM_ID, 0u,
172019  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL6_RAM_SIZE, 4u,
172020  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL6_ROW_WIDTH, ((bool)false) },
172021  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL7_RAM_ID, 0u,
172022  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL7_RAM_SIZE, 4u,
172023  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL7_ROW_WIDTH, ((bool)false) },
172024  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL8_RAM_ID, 0u,
172025  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL8_RAM_SIZE, 4u,
172026  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL8_ROW_WIDTH, ((bool)false) },
172027  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL9_RAM_ID, 0u,
172028  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL9_RAM_SIZE, 4u,
172029  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL9_ROW_WIDTH, ((bool)false) },
172030  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL10_RAM_ID, 0u,
172031  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL10_RAM_SIZE, 4u,
172032  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL10_ROW_WIDTH, ((bool)false) },
172033  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL11_RAM_ID, 0u,
172034  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL11_RAM_SIZE, 4u,
172035  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL11_ROW_WIDTH, ((bool)false) },
172036  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL12_RAM_ID, 0u,
172037  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL12_RAM_SIZE, 4u,
172038  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL12_ROW_WIDTH, ((bool)false) },
172039  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL13_RAM_ID, 0u,
172040  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL13_RAM_SIZE, 4u,
172041  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL13_ROW_WIDTH, ((bool)false) },
172042  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL14_RAM_ID, 0u,
172043  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL14_RAM_SIZE, 4u,
172044  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL14_ROW_WIDTH, ((bool)false) },
172045  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL15_RAM_ID, 0u,
172046  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL15_RAM_SIZE, 4u,
172047  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL15_ROW_WIDTH, ((bool)false) },
172048  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL16_RAM_ID, 0u,
172049  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL16_RAM_SIZE, 4u,
172050  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL16_ROW_WIDTH, ((bool)false) },
172051  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL17_RAM_ID, 0u,
172052  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL17_RAM_SIZE, 4u,
172053  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL17_ROW_WIDTH, ((bool)false) },
172054  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL18_RAM_ID, 0u,
172055  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL18_RAM_SIZE, 4u,
172056  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL18_ROW_WIDTH, ((bool)false) },
172057  { SDL_CPSW0_EST_RAM_RAM_ID, 0u,
172058  SDL_CPSW0_EST_RAM_RAM_SIZE, 4u,
172059  SDL_CPSW0_EST_RAM_ROW_WIDTH, ((bool)false) },
172060 };
172061 
172066 static const SDL_RAMIdEntry_t SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS] =
172067 {
172068  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
172069  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
172070  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
172071  0u,
172072  NULL },
172073  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
172074  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
172075  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
172076  0u,
172077  NULL },
172078  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
172079  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
172080  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
172081  0u,
172082  NULL },
172083  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
172084  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
172085  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
172086  0u,
172087  NULL },
172088  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
172089  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
172090  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
172091  0u,
172092  NULL },
172093  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID,
172094  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_INJECT_TYPE,
172095  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ECC_TYPE,
172096  0u,
172097  NULL },
172098  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID,
172099  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_INJECT_TYPE,
172100  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ECC_TYPE,
172101  0u,
172102  NULL },
172103  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID,
172104  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_INJECT_TYPE,
172105  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ECC_TYPE,
172106  0u,
172107  NULL },
172108  { SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID,
172109  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_INJECT_TYPE,
172110  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ECC_TYPE,
172111  0u,
172112  NULL },
172113 };
172114 
172119 static const SDL_RAMIdEntry_t SDL_MAIN_AC_ECC_AGGR0_RamIdTable[SDL_MAIN_AC_ECC_AGGR0_NUM_RAMS] =
172120 {
172121  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
172122  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
172123  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
172124  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172125  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
172126  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
172127  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
172128  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
172129  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172130  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
172131  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
172132  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
172133  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
172134  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172135  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
172136  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
172137  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
172138  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
172139  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172140  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
172141  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
172142  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
172143  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
172144  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172145  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
172146  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_RAM_ID,
172147  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_INJECT_TYPE,
172148  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_ECC_TYPE,
172149  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS,
172150  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries },
172151  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
172152  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
172153  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
172154  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
172155  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_groupEntries },
172156  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_RAM_ID,
172157  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
172158  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
172159  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
172160  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_groupEntries },
172161  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
172162  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
172163  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
172164  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
172165  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
172166  { SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
172167  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
172168  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
172169  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
172170  SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
172171  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
172172  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
172173  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
172174  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172175  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
172176  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
172177  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
172178  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
172179  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172180  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
172181  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_RAM_ID,
172182  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_INJECT_TYPE,
172183  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_ECC_TYPE,
172184  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
172185  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_groupEntries },
172186  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
172187  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
172188  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
172189  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
172190  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
172191  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
172192  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
172193  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
172194  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
172195  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
172196  { SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
172197  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
172198  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
172199  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172200  SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
172201  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_RAM_ID,
172202  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_INJECT_TYPE,
172203  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ECC_TYPE,
172204  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172205  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries },
172206  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_RAM_ID,
172207  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_INJECT_TYPE,
172208  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ECC_TYPE,
172209  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172210  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries },
172211  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_RAM_ID,
172212  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_INJECT_TYPE,
172213  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ECC_TYPE,
172214  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172215  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries },
172216  { SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_RAM_ID,
172217  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_INJECT_TYPE,
172218  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ECC_TYPE,
172219  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172220  SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries },
172221  { SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_RAM_ID,
172222  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
172223  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_ECC_TYPE,
172224  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
172225  SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_groupEntries },
172226 };
172227 
172232 static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_NUM_RAMS] =
172233 {
172234  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_RAM_ID,
172235  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_INJECT_TYPE,
172236  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_ECC_ECC_TYPE,
172237  0u,
172238  NULL },
172239  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_RAM_ID,
172240  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_INJECT_TYPE,
172241  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_ECC_TYPE,
172242  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
172243  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries },
172244  { SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_RAM_ID,
172245  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_INJECT_TYPE,
172246  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_ECC_TYPE,
172247  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_MAX_NUM_CHECKERS,
172248  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries },
172249 };
172250 
172255 static const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_NUM_RAMS] =
172256 {
172257  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_RAM_ID,
172258  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_INJECT_TYPE,
172259  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_ECC_TYPE,
172260  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS,
172261  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_groupEntries },
172262  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_RAM_ID,
172263  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_INJECT_TYPE,
172264  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_ECC_TYPE,
172265  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS,
172266  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_groupEntries },
172267  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_RAM_ID,
172268  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_INJECT_TYPE,
172269  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_ECC_TYPE,
172270  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS,
172271  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_groupEntries },
172272  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_RAM_ID,
172273  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_INJECT_TYPE,
172274  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_ECC_TYPE,
172275  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_MAX_NUM_CHECKERS,
172276  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_groupEntries },
172277  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_RAM_ID,
172278  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_INJECT_TYPE,
172279  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_ECC_TYPE,
172280  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS,
172281  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries },
172282  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
172283  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
172284  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
172285  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
172286  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
172287 };
172288 
172293 static const SDL_RAMIdEntry_t SDL_PCIE2_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE2_ECC_AGGR_CORE_0_NUM_RAMS] =
172294 {
172295  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
172296  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
172297  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
172298  0u,
172299  NULL },
172300  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID,
172301  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_INJECT_TYPE,
172302  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ECC_TYPE,
172303  0u,
172304  NULL },
172305  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
172306  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
172307  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
172308  0u,
172309  NULL },
172310  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID,
172311  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_INJECT_TYPE,
172312  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ECC_TYPE,
172313  0u,
172314  NULL },
172315  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
172316  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
172317  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
172318  0u,
172319  NULL },
172320  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
172321  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
172322  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
172323  0u,
172324  NULL },
172325  { SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID,
172326  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_INJECT_TYPE,
172327  SDL_PCIE2_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ECC_TYPE,
172328  0u,
172329  NULL },
172330 };
172331 
172336 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_NUM_RAMS] =
172337 {
172338  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
172339  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
172340  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
172341  0u,
172342  NULL },
172343  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
172344  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
172345  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
172346  0u,
172347  NULL },
172348  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
172349  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
172350  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
172351  0u,
172352  NULL },
172353  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
172354  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
172355  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
172356  0u,
172357  NULL },
172358  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
172359  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
172360  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
172361  0u,
172362  NULL },
172363  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
172364  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
172365  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
172366  0u,
172367  NULL },
172368  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
172369  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
172370  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
172371  0u,
172372  NULL },
172373  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
172374  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
172375  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
172376  0u,
172377  NULL },
172378  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
172379  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
172380  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
172381  0u,
172382  NULL },
172383  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
172384  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
172385  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
172386  0u,
172387  NULL },
172388  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
172389  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
172390  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
172391  0u,
172392  NULL },
172393  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
172394  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
172395  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
172396  0u,
172397  NULL },
172398  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
172399  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
172400  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
172401  0u,
172402  NULL },
172403  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
172404  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
172405  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
172406  0u,
172407  NULL },
172408  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
172409  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
172410  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
172411  0u,
172412  NULL },
172413  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
172414  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
172415  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
172416  0u,
172417  NULL },
172418  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
172419  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
172420  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
172421  0u,
172422  NULL },
172423  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
172424  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
172425  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
172426  0u,
172427  NULL },
172428  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
172429  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
172430  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
172431  0u,
172432  NULL },
172433  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
172434  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
172435  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
172436  0u,
172437  NULL },
172438  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK8_ECC_SVBUS_RAM_ID,
172439  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK8_ECC_SVBUS_INJECT_TYPE,
172440  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK8_ECC_SVBUS_ECC_TYPE,
172441  0u,
172442  NULL },
172443  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK9_ECC_SVBUS_RAM_ID,
172444  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK9_ECC_SVBUS_INJECT_TYPE,
172445  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK9_ECC_SVBUS_ECC_TYPE,
172446  0u,
172447  NULL },
172448  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK10_ECC_SVBUS_RAM_ID,
172449  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK10_ECC_SVBUS_INJECT_TYPE,
172450  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK10_ECC_SVBUS_ECC_TYPE,
172451  0u,
172452  NULL },
172453  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK11_ECC_SVBUS_RAM_ID,
172454  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK11_ECC_SVBUS_INJECT_TYPE,
172455  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK11_ECC_SVBUS_ECC_TYPE,
172456  0u,
172457  NULL },
172458  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK12_ECC_SVBUS_RAM_ID,
172459  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK12_ECC_SVBUS_INJECT_TYPE,
172460  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK12_ECC_SVBUS_ECC_TYPE,
172461  0u,
172462  NULL },
172463  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK13_ECC_SVBUS_RAM_ID,
172464  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK13_ECC_SVBUS_INJECT_TYPE,
172465  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK13_ECC_SVBUS_ECC_TYPE,
172466  0u,
172467  NULL },
172468  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK14_ECC_SVBUS_RAM_ID,
172469  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK14_ECC_SVBUS_INJECT_TYPE,
172470  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK14_ECC_SVBUS_ECC_TYPE,
172471  0u,
172472  NULL },
172473  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK15_ECC_SVBUS_RAM_ID,
172474  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK15_ECC_SVBUS_INJECT_TYPE,
172475  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_TAG_SPRAM_BANK15_ECC_SVBUS_ECC_TYPE,
172476  0u,
172477  NULL },
172478  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
172479  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
172480  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
172481  0u,
172482  NULL },
172483  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
172484  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
172485  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
172486  0u,
172487  NULL },
172488  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
172489  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
172490  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
172491  0u,
172492  NULL },
172493  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
172494  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
172495  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
172496  0u,
172497  NULL },
172498  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_RAM_ID,
172499  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_INJECT_TYPE,
172500  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_ECC_TYPE,
172501  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS,
172502  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries },
172503  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_RAM_ID,
172504  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_INJECT_TYPE,
172505  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ECC_TYPE,
172506  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
172507  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_groupEntries },
172508  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_RAM_ID,
172509  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_INJECT_TYPE,
172510  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ECC_TYPE,
172511  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
172512  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_groupEntries },
172513  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_RAM_ID,
172514  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_INJECT_TYPE,
172515  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ECC_TYPE,
172516  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
172517  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_groupEntries },
172518  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_RAM_ID,
172519  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
172520  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
172521  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
172522  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries },
172523  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_RAM_ID,
172524  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_INJECT_TYPE,
172525  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ECC_TYPE,
172526  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_MAX_NUM_CHECKERS,
172527  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_groupEntries },
172528  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_RAM_ID,
172529  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_INJECT_TYPE,
172530  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_ECC_TYPE,
172531  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS,
172532  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries },
172533  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_RAM_ID,
172534  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_INJECT_TYPE,
172535  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_ECC_TYPE,
172536  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS,
172537  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_groupEntries },
172538  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_RAM_ID,
172539  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_INJECT_TYPE,
172540  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_ECC_TYPE,
172541  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS,
172542  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries },
172543  { SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_RAM_ID,
172544  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_INJECT_TYPE,
172545  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_ECC_TYPE,
172546  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS,
172547  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries },
172548 };
172549 
172554 static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_NUM_RAMS] =
172555 {
172556  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_RAM_ID,
172557  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_INJECT_TYPE,
172558  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_ECC_TYPE,
172559  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
172560  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries },
172561  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
172562  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
172563  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
172564  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
172565  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
172566  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
172567  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
172568  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
172569  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
172570  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
172571  { SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
172572  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
172573  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
172574  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
172575  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
172576 };
172577 
172582 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
172583 {
172584  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
172585  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
172586  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
172587  0u,
172588  NULL },
172589 };
172590 
172595 static const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_NUM_RAMS] =
172596 {
172597  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_RAM_ID,
172598  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_INJECT_TYPE,
172599  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_IRAM_SPRAM_ECC_ECC_TYPE,
172600  0u,
172601  NULL },
172602  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_RAM_ID,
172603  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_INJECT_TYPE,
172604  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_DRAM_SPRAM_ECC_ECC_TYPE,
172605  0u,
172606  NULL },
172607  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_RAM_ID,
172608  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_INJECT_TYPE,
172609  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_ECC_TYPE,
172610  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_MAX_NUM_CHECKERS,
172611  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries },
172612 };
172613 
172618 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_NUM_RAMS] =
172619 {
172620  { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID,
172621  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_INJECT_TYPE,
172622  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ECC_TYPE,
172623  0u,
172624  NULL },
172625 };
172626 
172631 static const SDL_RAMIdEntry_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
172632 {
172633  { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
172634  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
172635  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
172636  0u,
172637  NULL },
172638  { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
172639  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
172640  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
172641  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
172642  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
172643 };
172644 
172649 static const SDL_RAMIdEntry_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_NUM_RAMS] =
172650 {
172651  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_RAM_ID,
172652  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_INJECT_TYPE,
172653  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_ECC_TYPE,
172654  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS,
172655  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries },
172656  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
172657  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
172658  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
172659  0u,
172660  NULL },
172661  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
172662  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
172663  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
172664  0u,
172665  NULL },
172666  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
172667  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
172668  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
172669  0u,
172670  NULL },
172671  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID,
172672  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_INJECT_TYPE,
172673  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ECC_TYPE,
172674  0u,
172675  NULL },
172676  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID,
172677  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_INJECT_TYPE,
172678  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ECC_TYPE,
172679  0u,
172680  NULL },
172681  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID,
172682  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_INJECT_TYPE,
172683  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ECC_TYPE,
172684  0u,
172685  NULL },
172686  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
172687  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
172688  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
172689  0u,
172690  NULL },
172691  { SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
172692  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
172693  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
172694  0u,
172695  NULL },
172696 };
172697 
172702 static const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_NUM_RAMS] =
172703 {
172704  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_RAM_ID,
172705  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_INJECT_TYPE,
172706  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_ECC_TYPE,
172707  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_MAX_NUM_CHECKERS,
172708  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries },
172709  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
172710  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
172711  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
172712  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
172713  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
172714  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_RAM_ID,
172715  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
172716  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
172717  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
172718  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_groupEntries },
172719  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_RAM_ID,
172720  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
172721  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_ECC_TYPE,
172722  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
172723  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_groupEntries },
172724  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_RAM_ID,
172725  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_INJECT_TYPE,
172726  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_ECC_TYPE,
172727  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
172728  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries },
172729  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
172730  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
172731  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
172732  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
172733  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
172734  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
172735  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
172736  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
172737  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
172738  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
172739 };
172740 
172745 static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
172746 {
172747  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
172748  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
172749  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
172750  0u,
172751  NULL },
172752  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
172753  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
172754  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
172755  0u,
172756  NULL },
172757  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
172758  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
172759  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
172760  0u,
172761  NULL },
172762  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
172763  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
172764  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
172765  0u,
172766  NULL },
172767  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
172768  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
172769  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
172770  0u,
172771  NULL },
172772  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
172773  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
172774  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
172775  0u,
172776  NULL },
172777  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
172778  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
172779  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
172780  0u,
172781  NULL },
172782  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
172783  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
172784  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
172785  0u,
172786  NULL },
172787  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
172788  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
172789  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
172790  0u,
172791  NULL },
172792  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
172793  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
172794  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
172795  0u,
172796  NULL },
172797  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
172798  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
172799  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
172800  0u,
172801  NULL },
172802  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
172803  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
172804  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
172805  0u,
172806  NULL },
172807  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
172808  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
172809  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
172810  0u,
172811  NULL },
172812  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
172813  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
172814  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
172815  0u,
172816  NULL },
172817  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
172818  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
172819  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
172820  0u,
172821  NULL },
172822  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
172823  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
172824  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
172825  0u,
172826  NULL },
172827  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
172828  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
172829  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
172830  0u,
172831  NULL },
172832  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
172833  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
172834  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
172835  0u,
172836  NULL },
172837  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
172838  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
172839  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
172840  0u,
172841  NULL },
172842  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
172843  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
172844  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
172845  0u,
172846  NULL },
172847  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
172848  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
172849  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
172850  0u,
172851  NULL },
172852  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
172853  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
172854  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
172855  0u,
172856  NULL },
172857  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
172858  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
172859  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
172860  0u,
172861  NULL },
172862  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
172863  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
172864  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
172865  0u,
172866  NULL },
172867  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
172868  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
172869  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
172870  0u,
172871  NULL },
172872  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
172873  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
172874  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
172875  0u,
172876  NULL },
172877  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
172878  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
172879  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
172880  0u,
172881  NULL },
172882  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
172883  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
172884  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
172885  0u,
172886  NULL },
172887  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID,
172888  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_INJECT_TYPE,
172889  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_ECC_TYPE,
172890  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS,
172891  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries },
172892  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
172893  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
172894  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
172895  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
172896  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
172897  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
172898  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
172899  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
172900  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
172901  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
172902  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
172903  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
172904  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
172905  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
172906  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
172907  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
172908  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
172909  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
172910  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
172911  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
172912  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_RAM_ID,
172913  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_INJECT_TYPE,
172914  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_ECC_TYPE,
172915  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS,
172916  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries },
172917  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_RAM_ID,
172918  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
172919  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE,
172920  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS,
172921  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries },
172922  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
172923  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
172924  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
172925  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
172926  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries },
172927 };
172928 
172933 static const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_NUM_RAMS] =
172934 {
172935  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_RAM_ID,
172936  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_INJECT_TYPE,
172937  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_LB_TPRAM_ECC_ECC_TYPE,
172938  0u,
172939  NULL },
172940  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_RAM_ID,
172941  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_INJECT_TYPE,
172942  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_S_TPRAM_ECC_ECC_TYPE,
172943  0u,
172944  NULL },
172945  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_RAM_ID,
172946  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_INJECT_TYPE,
172947  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_SSM_D_TPRAM_ECC_ECC_TYPE,
172948  0u,
172949  NULL },
172950  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_RAM_ID,
172951  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_INJECT_TYPE,
172952  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC0_OB0_TPRAM_ECC_ECC_TYPE,
172953  0u,
172954  NULL },
172955  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_RAM_ID,
172956  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_INJECT_TYPE,
172957  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_LB_TPRAM_ECC_ECC_TYPE,
172958  0u,
172959  NULL },
172960  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_RAM_ID,
172961  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_INJECT_TYPE,
172962  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_S_TPRAM_ECC_ECC_TYPE,
172963  0u,
172964  NULL },
172965  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_RAM_ID,
172966  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_INJECT_TYPE,
172967  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_SSM_D_TPRAM_ECC_ECC_TYPE,
172968  0u,
172969  NULL },
172970  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_RAM_ID,
172971  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_INJECT_TYPE,
172972  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_K3_DSS_EDP_MHDPTX_WRAPPER_ENC1_OB0_TPRAM_ECC_ECC_TYPE,
172973  0u,
172974  NULL },
172975 };
172976 
172981 static const SDL_RAMIdEntry_t SDL_MCU_I3C0_I3C_S_ECC_AGGR_RamIdTable[SDL_MCU_I3C0_I3C_S_ECC_AGGR_NUM_RAMS] =
172982 {
172983  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID,
172984  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_INJECT_TYPE,
172985  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ECC_TYPE,
172986  0u,
172987  NULL },
172988  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID,
172989  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_INJECT_TYPE,
172990  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ECC_TYPE,
172991  0u,
172992  NULL },
172993  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID,
172994  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_INJECT_TYPE,
172995  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ECC_TYPE,
172996  0u,
172997  NULL },
172998  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID,
172999  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_INJECT_TYPE,
173000  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ECC_TYPE,
173001  0u,
173002  NULL },
173003  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID,
173004  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_INJECT_TYPE,
173005  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_IBI_ECC_TYPE,
173006  0u,
173007  NULL },
173008  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID,
173009  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_INJECT_TYPE,
173010  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ECC_TYPE,
173011  0u,
173012  NULL },
173013  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID,
173014  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_INJECT_TYPE,
173015  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_ECC_TYPE,
173016  0u,
173017  NULL },
173018  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID,
173019  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_INJECT_TYPE,
173020  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ECC_TYPE,
173021  0u,
173022  NULL },
173023  { SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID,
173024  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_INJECT_TYPE,
173025  SDL_MCU_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_ECC_TYPE,
173026  0u,
173027  NULL },
173028 };
173029 
173034 static const SDL_RAMIdEntry_t SDL_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS] =
173035 {
173036  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_RAM_ID,
173037  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_INJECT_TYPE,
173038  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_ECC_TYPE,
173039  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS,
173040  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries },
173041  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PSTATE_RAM_ID,
173042  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PSTATE_INJECT_TYPE,
173043  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PSTATE_ECC_TYPE,
173044  0u,
173045  NULL },
173046  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PCONFIG_RAM_ID,
173047  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PCONFIG_INJECT_TYPE,
173048  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFG_PCONFIG_ECC_TYPE,
173049  0u,
173050  NULL },
173051  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_CF_RAM_ID,
173052  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_CF_INJECT_TYPE,
173053  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_CF_ECC_TYPE,
173054  0u,
173055  NULL },
173056  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_DF_RAM_ID,
173057  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_DF_INJECT_TYPE,
173058  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_DF_ECC_TYPE,
173059  0u,
173060  NULL },
173061  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_PF_RAM_ID,
173062  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_PF_INJECT_TYPE,
173063  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPBUF_PF_ECC_TYPE,
173064  0u,
173065  NULL },
173066  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_SB_RAM_ID,
173067  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_SB_INJECT_TYPE,
173068  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_SB_ECC_TYPE,
173069  0u,
173070  NULL },
173071  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_RAM_ID,
173072  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_INJECT_TYPE,
173073  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_ECC_TYPE,
173074  0u,
173075  NULL },
173076  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_SB_RAM_ID,
173077  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_SB_INJECT_TYPE,
173078  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_SB_ECC_TYPE,
173079  0u,
173080  NULL },
173081  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_ARRAYCNT_ARRAYCNT_TPRAM_640X13_SWW_AR_RAM_ID,
173082  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_ARRAYCNT_ARRAYCNT_TPRAM_640X13_SWW_AR_INJECT_TYPE,
173083  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPECU_ARRAYCNT_ARRAYCNT_TPRAM_640X13_SWW_AR_ECC_TYPE,
173084  0u,
173085  NULL },
173086  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PSTATE_RAM_ID,
173087  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PSTATE_INJECT_TYPE,
173088  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PSTATE_ECC_TYPE,
173089  0u,
173090  NULL },
173091  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PCONFIG_RAM_ID,
173092  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PCONFIG_INJECT_TYPE,
173093  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PCONFIG_ECC_TYPE,
173094  0u,
173095  NULL },
173096  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PQINFO_RAM_ID,
173097  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PQINFO_INJECT_TYPE,
173098  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFG_PQINFO_ECC_TYPE,
173099  0u,
173100  NULL },
173101  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_CF_RAM_ID,
173102  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_CF_INJECT_TYPE,
173103  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_CF_ECC_TYPE,
173104  0u,
173105  NULL },
173106  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_DF_RAM_ID,
173107  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_DF_INJECT_TYPE,
173108  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_DF_ECC_TYPE,
173109  0u,
173110  NULL },
173111  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_PF_RAM_ID,
173112  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_PF_INJECT_TYPE,
173113  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPBUF_PF_ECC_TYPE,
173114  0u,
173115  NULL },
173116  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TCF_RAM_ID,
173117  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TCF_INJECT_TYPE,
173118  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TCF_ECC_TYPE,
173119  0u,
173120  NULL },
173121  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TDF_RAM_ID,
173122  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TDF_INJECT_TYPE,
173123  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EPSILIF_TDF_ECC_TYPE,
173124  0u,
173125  NULL },
173126  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB0_RAM_ID,
173127  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB0_INJECT_TYPE,
173128  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB0_ECC_TYPE,
173129  0u,
173130  NULL },
173131  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB1_RAM_ID,
173132  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB1_INJECT_TYPE,
173133  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB1_ECC_TYPE,
173134  0u,
173135  NULL },
173136  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB2_RAM_ID,
173137  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB2_INJECT_TYPE,
173138  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_SB2_ECC_TYPE,
173139  0u,
173140  NULL },
173141  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_RAM_ID,
173142  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_INJECT_TYPE,
173143  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_ECC_TYPE,
173144  0u,
173145  NULL },
173146  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB0_RAM_ID,
173147  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB0_INJECT_TYPE,
173148  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB0_ECC_TYPE,
173149  0u,
173150  NULL },
173151  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB1_RAM_ID,
173152  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB1_INJECT_TYPE,
173153  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB1_ECC_TYPE,
173154  0u,
173155  NULL },
173156  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB2_RAM_ID,
173157  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB2_INJECT_TYPE,
173158  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_SB2_ECC_TYPE,
173159  0u,
173160  NULL },
173161  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_RAM_ID,
173162  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_INJECT_TYPE,
173163  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_ECC_TYPE,
173164  0u,
173165  NULL },
173166  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB0_RAM_ID,
173167  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB0_INJECT_TYPE,
173168  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB0_ECC_TYPE,
173169  0u,
173170  NULL },
173171  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB1_RAM_ID,
173172  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB1_INJECT_TYPE,
173173  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_SB1_ECC_TYPE,
173174  0u,
173175  NULL },
173176  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_RAM_ID,
173177  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_INJECT_TYPE,
173178  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_ECC_TYPE,
173179  0u,
173180  NULL },
173181  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TCFG_STATE_RAM_ID,
173182  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TCFG_STATE_INJECT_TYPE,
173183  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TCFG_STATE_ECC_TYPE,
173184  0u,
173185  NULL },
173186  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F0_RAM_ID,
173187  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F0_INJECT_TYPE,
173188  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F0_ECC_TYPE,
173189  0u,
173190  NULL },
173191  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F1_RAM_ID,
173192  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F1_INJECT_TYPE,
173193  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_F1_ECC_TYPE,
173194  0u,
173195  NULL },
173196  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_C0_RAM_ID,
173197  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_C0_INJECT_TYPE,
173198  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TPCFIFO0_C0_ECC_TYPE,
173199  0u,
173200  NULL },
173201  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RFLOWFW_RFFW_RAM_ID,
173202  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RFLOWFW_RFFW_INJECT_TYPE,
173203  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RFLOWFW_RFFW_ECC_TYPE,
173204  0u,
173205  NULL },
173206  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F0_RAM_ID,
173207  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F0_INJECT_TYPE,
173208  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F0_ECC_TYPE,
173209  0u,
173210  NULL },
173211  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F1_RAM_ID,
173212  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F1_INJECT_TYPE,
173213  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_F1_ECC_TYPE,
173214  0u,
173215  NULL },
173216  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C0_RAM_ID,
173217  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C0_INJECT_TYPE,
173218  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C0_ECC_TYPE,
173219  0u,
173220  NULL },
173221  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_WC0_RAM_ID,
173222  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_WC0_INJECT_TYPE,
173223  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_WC0_ECC_TYPE,
173224  0u,
173225  NULL },
173226  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C1_RAM_ID,
173227  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C1_INJECT_TYPE,
173228  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RPCFIFO_C1_ECC_TYPE,
173229  0u,
173230  NULL },
173231  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW0_RAM_ID,
173232  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW0_INJECT_TYPE,
173233  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW0_ECC_TYPE,
173234  0u,
173235  NULL },
173236  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW1_RAM_ID,
173237  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW1_INJECT_TYPE,
173238  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RFLOW1_ECC_TYPE,
173239  0u,
173240  NULL },
173241  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RSTATE_RAM_ID,
173242  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RSTATE_INJECT_TYPE,
173243  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RCFG_RSTATE_ECC_TYPE,
173244  0u,
173245  NULL },
173246  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PROXY_PCONFIG_RAM_ID,
173247  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PROXY_PCONFIG_INJECT_TYPE,
173248  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PROXY_PCONFIG_ECC_TYPE,
173249  0u,
173250  NULL },
173251  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EHANDLER_ECONFIG_RAM_ID,
173252  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EHANDLER_ECONFIG_INJECT_TYPE,
173253  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EHANDLER_ECONFIG_ECC_TYPE,
173254  0u,
173255  NULL },
173256  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST0_RAM_ID,
173257  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST0_INJECT_TYPE,
173258  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST0_ECC_TYPE,
173259  0u,
173260  NULL },
173261  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST1_RAM_ID,
173262  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST1_INJECT_TYPE,
173263  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STST1_ECC_TYPE,
173264  0u,
173265  NULL },
173266  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR0_RAM_ID,
173267  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR0_INJECT_TYPE,
173268  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR0_ECC_TYPE,
173269  0u,
173270  NULL },
173271  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR1_RAM_ID,
173272  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR1_INJECT_TYPE,
173273  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_STATS_STSR1_ECC_TYPE,
173274  0u,
173275  NULL },
173276  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_RAM_ID,
173277  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_INJECT_TYPE,
173278  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_ECC_TYPE,
173279  0u,
173280  NULL },
173281  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_RAM_ID,
173282  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_INJECT_TYPE,
173283  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_ECC_TYPE,
173284  0u,
173285  NULL },
173286  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC0_SB_RAM_ID,
173287  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC0_SB_INJECT_TYPE,
173288  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC0_SB_ECC_TYPE,
173289  0u,
173290  NULL },
173291  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC1_SB_RAM_ID,
173292  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC1_SB_INJECT_TYPE,
173293  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC1_SB_ECC_TYPE,
173294  0u,
173295  NULL },
173296  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC2_SB_RAM_ID,
173297  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC2_SB_INJECT_TYPE,
173298  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RDEC2_SB_ECC_TYPE,
173299  0u,
173300  NULL },
173301  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC0_SB_RAM_ID,
173302  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC0_SB_INJECT_TYPE,
173303  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC0_SB_ECC_TYPE,
173304  0u,
173305  NULL },
173306  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC3_SB_RAM_ID,
173307  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC3_SB_INJECT_TYPE,
173308  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_SDEC3_SB_ECC_TYPE,
173309  0u,
173310  NULL },
173311  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_RAM_ID,
173312  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_INJECT_TYPE,
173313  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_ECC_TYPE,
173314  0u,
173315  NULL },
173316  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_TRETID_RAM_ID,
173317  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_TRETID_INJECT_TYPE,
173318  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_PSILIF_TRETID_ECC_TYPE,
173319  0u,
173320  NULL },
173321  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_RAM_ID,
173322  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_INJECT_TYPE,
173323  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_ECC_TYPE,
173324  0u,
173325  NULL },
173326  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_RAM_ID,
173327  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_INJECT_TYPE,
173328  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_ECC_TYPE,
173329  0u,
173330  NULL },
173331  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_RAM_ID,
173332  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_INJECT_TYPE,
173333  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_ECC_TYPE,
173334  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS,
173335  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries },
173336  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_RAM_ID,
173337  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_INJECT_TYPE,
173338  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_ECC_TYPE,
173339  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS,
173340  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries },
173341  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_RAM_ID,
173342  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_INJECT_TYPE,
173343  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_ECC_TYPE,
173344  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS,
173345  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries },
173346  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_RAM_ID,
173347  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_INJECT_TYPE,
173348  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_ECC_TYPE,
173349  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS,
173350  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries },
173351  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_RAM_ID,
173352  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_INJECT_TYPE,
173353  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_ECC_TYPE,
173354  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS,
173355  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries },
173356  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_STRAM_RAM_ID,
173357  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_STRAM_INJECT_TYPE,
173358  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_STRAM_ECC_TYPE,
173359  0u,
173360  NULL },
173361  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_RAM_ID,
173362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_INJECT_TYPE,
173363  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_ECC_TYPE,
173364  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS,
173365  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries },
173366  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_4608X15_SWW_SR_RAM_ID,
173367  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_4608X15_SWW_SR_INJECT_TYPE,
173368  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_4608X15_SWW_SR_ECC_TYPE,
173369  0u,
173370  NULL },
173371  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_RAM_ID,
173372  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_INJECT_TYPE,
173373  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_ECC_TYPE,
173374  0u,
173375  NULL },
173376  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_512X32_SWW_SR_RAM_ID,
173377  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_512X32_SWW_SR_INJECT_TYPE,
173378  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_512X32_SWW_SR_ECC_TYPE,
173379  0u,
173380  NULL },
173381  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_512X48_SWW_SR_RAM_ID,
173382  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_512X48_SWW_SR_INJECT_TYPE,
173383  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_512X48_SWW_SR_ECC_TYPE,
173384  0u,
173385  NULL },
173386  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_RAM_ID,
173387  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
173388  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_ECC_TYPE,
173389  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
173390  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries },
173391  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_ECC0_RAM_ID,
173392  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_ECC0_INJECT_TYPE,
173393  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_ECC0_ECC_TYPE,
173394  0u,
173395  NULL },
173396  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_RAM_ID,
173397  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173398  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173399  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173400  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries },
173401  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
173402  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
173403  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
173404  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173405  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
173406  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
173407  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
173408  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
173409  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173410  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries },
173411  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_RAM_ID,
173412  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_INJECT_TYPE,
173413  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_ECC_TYPE,
173414  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
173415  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_groupEntries },
173416  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_RAM_ID,
173417  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_INJECT_TYPE,
173418  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_ECC_TYPE,
173419  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
173420  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries },
173421  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_RAM_ID,
173422  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_INJECT_TYPE,
173423  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_ECC_TYPE,
173424  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
173425  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries },
173426  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_RAM_ID,
173427  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_INJECT_TYPE,
173428  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_ECC_TYPE,
173429  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173430  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_groupEntries },
173431  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
173432  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
173433  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
173434  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173435  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries },
173436  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
173437  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
173438  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
173439  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173440  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries },
173441  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
173442  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
173443  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
173444  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173445  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
173446  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
173447  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
173448  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
173449  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173450  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries },
173451  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_RAM_ID,
173452  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_INJECT_TYPE,
173453  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_ECC_TYPE,
173454  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS,
173455  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries },
173456  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_RAM_ID,
173457  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_INJECT_TYPE,
173458  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_ECC_TYPE,
173459  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS,
173460  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries },
173461  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
173462  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
173463  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
173464  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173465  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
173466  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_RAM_ID,
173467  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173468  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173469  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173470  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries },
173471  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_RAM_ID,
173472  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173473  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173474  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173475  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries },
173476  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_RAM_ID,
173477  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173478  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173479  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173480  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries },
173481  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_RAM_ID,
173482  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173483  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173484  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173485  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries },
173486  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_RAM_ID,
173487  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173488  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173489  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173490  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries },
173491  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
173492  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
173493  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
173494  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173495  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_groupEntries },
173496  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
173497  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
173498  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
173499  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173500  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
173501  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
173502  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
173503  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
173504  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173505  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
173506  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
173507  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173508  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173509  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173510  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
173511  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
173512  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173513  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173514  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173515  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
173516  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
173517  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
173518  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
173519  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173520  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
173521  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_RAM_ID,
173522  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_INJECT_TYPE,
173523  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_ECC_TYPE,
173524  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
173525  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries },
173526  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_RAM_ID,
173527  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_INJECT_TYPE,
173528  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_ECC_TYPE,
173529  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
173530  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_groupEntries },
173531  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_RAM_ID,
173532  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_INJECT_TYPE,
173533  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_ECC_TYPE,
173534  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
173535  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries },
173536  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_RAM_ID,
173537  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_INJECT_TYPE,
173538  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_ECC_TYPE,
173539  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
173540  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_groupEntries },
173541  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_RAM_ID,
173542  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_INJECT_TYPE,
173543  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_ECC_TYPE,
173544  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
173545  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries },
173546  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_RAM_ID,
173547  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_INJECT_TYPE,
173548  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_ECC_TYPE,
173549  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
173550  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_groupEntries },
173551  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_RAM_ID,
173552  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
173553  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
173554  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
173555  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries },
173556  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_RAM_ID,
173557  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
173558  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
173559  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
173560  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries },
173561  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_RAM_ID,
173562  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_INJECT_TYPE,
173563  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_ECC_TYPE,
173564  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
173565  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_groupEntries },
173566  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
173567  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
173568  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
173569  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173570  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries },
173571  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
173572  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
173573  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
173574  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173575  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries },
173576  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
173577  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
173578  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
173579  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173580  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
173581  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
173582  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
173583  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
173584  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173585  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries },
173586  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_RAM_ID,
173587  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_INJECT_TYPE,
173588  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_ECC_TYPE,
173589  0u,
173590  NULL },
173591  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
173592  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
173593  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
173594  0u,
173595  NULL },
173596  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
173597  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
173598  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
173599  0u,
173600  NULL },
173601  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
173602  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
173603  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
173604  0u,
173605  NULL },
173606  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173607  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173608  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173609  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173610  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173611  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173612  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173613  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173614  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173615  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173616  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173617  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173618  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173619  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173620  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173621  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173622  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173623  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173624  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173625  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173626  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173627  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173628  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173629  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173630  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173631  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173632  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173633  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173634  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173635  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173636  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173637  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173638  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173639  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173640  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173641  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
173642  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
173643  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
173644  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173645  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
173646  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173647  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173648  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173649  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173650  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173651  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173652  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173653  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173654  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173655  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173656  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173657  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173658  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173659  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173660  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173661  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_RAM_ID,
173662  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_INJECT_TYPE,
173663  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_ECC_TYPE,
173664  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS,
173665  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries },
173666  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173667  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173668  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173669  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173670  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173671  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173672  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173673  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173674  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173675  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173676  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173677  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173678  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173679  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173680  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173681  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
173682  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
173683  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
173684  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173685  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
173686  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
173687  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
173688  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
173689  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173690  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
173691  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
173692  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
173693  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
173694  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
173695  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
173696  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
173697  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
173698  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
173699  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173700  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
173701  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
173702  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
173703  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
173704  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
173705  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
173706  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
173707  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
173708  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
173709  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173710  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
173711  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
173712  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
173713  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
173714  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173715  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
173716  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
173717  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
173718  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
173719  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
173720  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
173721  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
173722  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
173723  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
173724  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
173725  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
173726  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_RAM_ID,
173727  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_INJECT_TYPE,
173728  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_ECC_TYPE,
173729  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173730  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries },
173731  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_RAM_ID,
173732  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_INJECT_TYPE,
173733  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_ECC_TYPE,
173734  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS,
173735  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries },
173736  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_RAM_ID,
173737  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_INJECT_TYPE,
173738  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_ECC_TYPE,
173739  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173740  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries },
173741  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_RAM_ID,
173742  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_INJECT_TYPE,
173743  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_ECC_TYPE,
173744  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS,
173745  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries },
173746  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
173747  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
173748  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
173749  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173750  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
173751  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
173752  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
173753  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
173754  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
173755  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
173756  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_RAM_ID,
173757  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_INJECT_TYPE,
173758  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_ECC_TYPE,
173759  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
173760  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries },
173761  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
173762  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
173763  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
173764  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173765  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
173766  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
173767  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
173768  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
173769  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
173770  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
173771  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
173772  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
173773  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
173774  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173775  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
173776  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
173777  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
173778  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
173779  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
173780  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
173781  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
173782  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
173783  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
173784  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173785  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
173786  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
173787  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
173788  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
173789  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
173790  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
173791  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
173792  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
173793  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
173794  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
173795  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
173796  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
173797  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
173798  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
173799  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
173800  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
173801  { SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
173802  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
173803  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
173804  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
173805  SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
173806 };
173807 
173812 static const SDL_RAMIdEntry_t SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RamIdTable[SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_NUM_RAMS] =
173813 {
173814  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RX_TC0_RAM_ID,
173815  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RX_TC0_INJECT_TYPE,
173816  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RX_TC0_ECC_TYPE,
173817  0u,
173818  NULL },
173819  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCF_RAM_ID,
173820  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCF_INJECT_TYPE,
173821  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCF_ECC_TYPE,
173822  0u,
173823  NULL },
173824  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU7_RAM_ID,
173825  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU7_INJECT_TYPE,
173826  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU7_ECC_TYPE,
173827  0u,
173828  NULL },
173829  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCM_RAM_ID,
173830  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCM_INJECT_TYPE,
173831  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDCM_ECC_TYPE,
173832  0u,
173833  NULL },
173834  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU6_RAM_ID,
173835  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU6_INJECT_TYPE,
173836  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU6_ECC_TYPE,
173837  0u,
173838  NULL },
173839  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDC_RAM_ID,
173840  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDC_INJECT_TYPE,
173841  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDC_ECC_TYPE,
173842  0u,
173843  NULL },
173844  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CIP_RAM_ID,
173845  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CIP_INJECT_TYPE,
173846  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CIP_ECC_TYPE,
173847  0u,
173848  NULL },
173849  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_ID_RAM_ID,
173850  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_ID_INJECT_TYPE,
173851  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_ID_ECC_TYPE,
173852  0u,
173853  NULL },
173854  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU2_RAM_ID,
173855  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU2_INJECT_TYPE,
173856  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU2_ECC_TYPE,
173857  0u,
173858  NULL },
173859  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU4_RAM_ID,
173860  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU4_INJECT_TYPE,
173861  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU4_ECC_TYPE,
173862  0u,
173863  NULL },
173864  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CCI_RAM_ID,
173865  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CCI_INJECT_TYPE,
173866  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CCI_ECC_TYPE,
173867  0u,
173868  NULL },
173869  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU5_RAM_ID,
173870  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU5_INJECT_TYPE,
173871  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU5_ECC_TYPE,
173872  0u,
173873  NULL },
173874  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDF_RAM_ID,
173875  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDF_INJECT_TYPE,
173876  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDF_ECC_TYPE,
173877  0u,
173878  NULL },
173879  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_TMU_RAM_ID,
173880  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_TMU_INJECT_TYPE,
173881  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_TMU_ECC_TYPE,
173882  0u,
173883  NULL },
173884  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU3_RAM_ID,
173885  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU3_INJECT_TYPE,
173886  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU3_ECC_TYPE,
173887  0u,
173888  NULL },
173889  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDF_RAM_ID,
173890  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDF_INJECT_TYPE,
173891  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RDF_ECC_TYPE,
173892  0u,
173893  NULL },
173894  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDC_RAM_ID,
173895  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDC_INJECT_TYPE,
173896  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_WDC_ECC_TYPE,
173897  0u,
173898  NULL },
173899  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RTT_RAM_ID,
173900  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RTT_INJECT_TYPE,
173901  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_RTT_ECC_TYPE,
173902  0u,
173903  NULL },
173904  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU1_RAM_ID,
173905  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU1_INJECT_TYPE,
173906  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_IPS_RAMS_MEM_CMU1_ECC_TYPE,
173907  0u,
173908  NULL },
173909  { SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
173910  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
173911  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_UFSHCI2P1SS_16FFC_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
173912  0u,
173913  NULL },
173914 };
173915 
173920 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS] =
173921 {
173922  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
173923  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
173924  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
173925  0u,
173926  NULL },
173927  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
173928  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
173929  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
173930  0u,
173931  NULL },
173932  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
173933  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
173934  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
173935  0u,
173936  NULL },
173937  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
173938  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
173939  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
173940  0u,
173941  NULL },
173942  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
173943  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
173944  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
173945  0u,
173946  NULL },
173947  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
173948  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
173949  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
173950  0u,
173951  NULL },
173952  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
173953  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
173954  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
173955  0u,
173956  NULL },
173957  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
173958  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
173959  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
173960  0u,
173961  NULL },
173962  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
173963  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
173964  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
173965  0u,
173966  NULL },
173967  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
173968  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
173969  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
173970  0u,
173971  NULL },
173972  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
173973  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
173974  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
173975  0u,
173976  NULL },
173977  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
173978  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
173979  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
173980  0u,
173981  NULL },
173982  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
173983  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
173984  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
173985  0u,
173986  NULL },
173987  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
173988  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
173989  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
173990  0u,
173991  NULL },
173992  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
173993  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
173994  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
173995  0u,
173996  NULL },
173997  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
173998  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
173999  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
174000  0u,
174001  NULL },
174002  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
174003  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
174004  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
174005  0u,
174006  NULL },
174007  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
174008  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
174009  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
174010  0u,
174011  NULL },
174012  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
174013  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
174014  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
174015  0u,
174016  NULL },
174017  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
174018  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
174019  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
174020  0u,
174021  NULL },
174022  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
174023  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
174024  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
174025  0u,
174026  NULL },
174027  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
174028  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
174029  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
174030  0u,
174031  NULL },
174032  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
174033  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
174034  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
174035  0u,
174036  NULL },
174037  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
174038  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
174039  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
174040  0u,
174041  NULL },
174042  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
174043  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
174044  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
174045  0u,
174046  NULL },
174047  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
174048  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
174049  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
174050  0u,
174051  NULL },
174052  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
174053  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
174054  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
174055  0u,
174056  NULL },
174057  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
174058  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
174059  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
174060  0u,
174061  NULL },
174062  { SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_RAM_ID,
174063  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_INJECT_TYPE,
174064  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_ECC_TYPE,
174065  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS,
174066  SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries },
174067  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
174068  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
174069  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
174070  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
174071  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
174072  { SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
174073  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
174074  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
174075  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
174076  SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
174077  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
174078  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
174079  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
174080  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
174081  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
174082  { SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
174083  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
174084  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
174085  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
174086  SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
174087  { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_RAM_ID,
174088  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_INJECT_TYPE,
174089  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_ECC_TYPE,
174090  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS,
174091  SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries },
174092  { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_RAM_ID,
174093  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
174094  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_ECC_TYPE,
174095  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
174096  SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries },
174097 };
174098 
174103 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
174104 {
174105  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
174106  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
174107  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
174108  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
174109  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries },
174110  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
174111  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
174112  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
174113  0u,
174114  NULL },
174115  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
174116  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
174117  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
174118  0u,
174119  NULL },
174120  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
174121  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
174122  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
174123  0u,
174124  NULL },
174125  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
174126  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
174127  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
174128  0u,
174129  NULL },
174130  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
174131  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
174132  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
174133  0u,
174134  NULL },
174135  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
174136  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
174137  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
174138  0u,
174139  NULL },
174140  { SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
174141  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
174142  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
174143  0u,
174144  NULL },
174145 };
174146 
174151 static const SDL_RAMIdEntry_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS] =
174152 {
174153  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_RAM_ID,
174154  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_INJECT_TYPE,
174155  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_ECC_TYPE,
174156  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
174157  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries },
174158  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_RAM_ID,
174159  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
174160  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
174161  0u,
174162  NULL },
174163  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
174164  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
174165  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
174166  0u,
174167  NULL },
174168  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
174169  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
174170  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
174171  0u,
174172  NULL },
174173  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
174174  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
174175  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
174176  0u,
174177  NULL },
174178  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
174179  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
174180  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
174181  0u,
174182  NULL },
174183  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_RAM_ID,
174184  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_INJECT_TYPE,
174185  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP0_VP_FIFO_ECC_TYPE,
174186  0u,
174187  NULL },
174188  { SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_RAM_ID,
174189  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_INJECT_TYPE,
174190  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_VP1_VP_FIFO_ECC_TYPE,
174191  0u,
174192  NULL },
174193 };
174194 
174199 static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
174200 {
174201  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
174202  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
174203  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
174204  0u,
174205  NULL },
174206  { SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
174207  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
174208  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
174209  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
174210  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
174211 };
174212 
174217 static const SDL_RAMIdEntry_t SDL_NAVSS0_MODSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS] =
174218 {
174219  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_RAM_ID,
174220  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_INJECT_TYPE,
174221  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_ECC_TYPE,
174222  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS,
174223  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries },
174224  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_RAM_ID,
174225  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_INJECT_TYPE,
174226  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_ECC_TYPE,
174227  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_MAX_NUM_CHECKERS,
174228  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries },
174229  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_RAM_ID,
174230  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_INJECT_TYPE,
174231  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_ECC_TYPE,
174232  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_MAX_NUM_CHECKERS,
174233  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries },
174234  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_RAM_ECC_RAM_ID,
174235  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_RAM_ECC_INJECT_TYPE,
174236  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_RAM_ECC_ECC_TYPE,
174237  0u,
174238  NULL },
174239  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_RAM_ID,
174240  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_INJECT_TYPE,
174241  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_ECC_TYPE,
174242  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_MAX_NUM_CHECKERS,
174243  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries },
174244  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_RAM_ID,
174245  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_INJECT_TYPE,
174246  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_ECC_TYPE,
174247  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_MAX_NUM_CHECKERS,
174248  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries },
174249  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_RAM_ID,
174250  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_INJECT_TYPE,
174251  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_ECC_TYPE,
174252  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_MAX_NUM_CHECKERS,
174253  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries },
174254  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_TIMER_FSM_RAM_ECC_RAM_ID,
174255  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_TIMER_FSM_RAM_ECC_INJECT_TYPE,
174256  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_TIMER_FSM_RAM_ECC_ECC_TYPE,
174257  0u,
174258  NULL },
174259  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_REPROG_FSM_RAM_ECC_RAM_ID,
174260  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_REPROG_FSM_RAM_ECC_INJECT_TYPE,
174261  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_REPROG_FSM_RAM_ECC_ECC_TYPE,
174262  0u,
174263  NULL },
174264  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_FIFO_RAM_ECC_RAM_ID,
174265  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_FIFO_RAM_ECC_INJECT_TYPE,
174266  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_FIFO_RAM_ECC_ECC_TYPE,
174267  0u,
174268  NULL },
174269  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_OFFSET_RAM_ECC_RAM_ID,
174270  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_OFFSET_RAM_ECC_INJECT_TYPE,
174271  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EVENT_OFFSET_RAM_ECC_ECC_TYPE,
174272  0u,
174273  NULL },
174274  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_RAM_ID,
174275  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_INJECT_TYPE,
174276  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_ECC_TYPE,
174277  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_MAX_NUM_CHECKERS,
174278  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries },
174279  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_TIMER_FSM_RAM_ECC_RAM_ID,
174280  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_TIMER_FSM_RAM_ECC_INJECT_TYPE,
174281  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_TIMER_FSM_RAM_ECC_ECC_TYPE,
174282  0u,
174283  NULL },
174284  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_REPROG_FSM_RAM_ECC_RAM_ID,
174285  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_REPROG_FSM_RAM_ECC_INJECT_TYPE,
174286  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_REPROG_FSM_RAM_ECC_ECC_TYPE,
174287  0u,
174288  NULL },
174289  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_FIFO_RAM_ECC_RAM_ID,
174290  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_FIFO_RAM_ECC_INJECT_TYPE,
174291  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_FIFO_RAM_ECC_ECC_TYPE,
174292  0u,
174293  NULL },
174294  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_OFFSET_RAM_ECC_RAM_ID,
174295  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_OFFSET_RAM_ECC_INJECT_TYPE,
174296  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EVENT_OFFSET_RAM_ECC_ECC_TYPE,
174297  0u,
174298  NULL },
174299  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_RAM_ID,
174300  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_INJECT_TYPE,
174301  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_ECC_TYPE,
174302  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_MAX_NUM_CHECKERS,
174303  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries },
174304  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_RAM_ID,
174305  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_INJECT_TYPE,
174306  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_ECC_TYPE,
174307  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS,
174308  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries },
174309  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_INTMAP_IM_SPRAM_1024X15_SWW_SR_RAM_ID,
174310  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_INTMAP_IM_SPRAM_1024X15_SWW_SR_INJECT_TYPE,
174311  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_INTMAP_IM_SPRAM_1024X15_SWW_SR_ECC_TYPE,
174312  0u,
174313  NULL },
174314  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_STATREG_SR_SPRAM_64X128_SWW_SR_RAM_ID,
174315  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_STATREG_SR_SPRAM_64X128_SWW_SR_INJECT_TYPE,
174316  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_STATREG_SR_SPRAM_64X128_SWW_SR_ECC_TYPE,
174317  0u,
174318  NULL },
174319  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_RAM_ID,
174320  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_INJECT_TYPE,
174321  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_ECC_TYPE,
174322  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_MAX_NUM_CHECKERS,
174323  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries },
174324  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_INTMAP_IM_SPRAM_1024X15_SWW_SR_RAM_ID,
174325  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_INTMAP_IM_SPRAM_1024X15_SWW_SR_INJECT_TYPE,
174326  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_INTMAP_IM_SPRAM_1024X15_SWW_SR_ECC_TYPE,
174327  0u,
174328  NULL },
174329  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_STATREG_SR_SPRAM_64X128_SWW_SR_RAM_ID,
174330  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_STATREG_SR_SPRAM_64X128_SWW_SR_INJECT_TYPE,
174331  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_STATREG_SR_SPRAM_64X128_SWW_SR_ECC_TYPE,
174332  0u,
174333  NULL },
174334  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_STRAM_RAM_ID,
174335  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_STRAM_INJECT_TYPE,
174336  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_STRAM_ECC_TYPE,
174337  0u,
174338  NULL },
174339  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_BUFRAM_ECC_RAM_ID,
174340  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_BUFRAM_ECC_INJECT_TYPE,
174341  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_BUFRAM_ECC_ECC_TYPE,
174342  0u,
174343  NULL },
174344  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_RAM_ID,
174345  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_INJECT_TYPE,
174346  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_ECC_TYPE,
174347  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174348  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries },
174349  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_RAM_ID,
174350  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_INJECT_TYPE,
174351  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_ECC_TYPE,
174352  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS,
174353  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_groupEntries },
174354  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_STRAM_RAM_ID,
174355  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_STRAM_INJECT_TYPE,
174356  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_STRAM_ECC_TYPE,
174357  0u,
174358  NULL },
174359  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_BUFRAM_RAM_ID,
174360  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_BUFRAM_INJECT_TYPE,
174361  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_BUF_BUFRAM_ECC_TYPE,
174362  0u,
174363  NULL },
174364  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_RAM_ID,
174365  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_INJECT_TYPE,
174366  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_ECC_TYPE,
174367  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS,
174368  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries },
174369  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_RAM_ID,
174370  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_INJECT_TYPE,
174371  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_ECC_TYPE,
174372  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS,
174373  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries },
174374  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_RAM_ID,
174375  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_INJECT_TYPE,
174376  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_ECC_TYPE,
174377  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS,
174378  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries },
174379  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
174380  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
174381  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
174382  0u,
174383  NULL },
174384  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
174385  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
174386  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
174387  0u,
174388  NULL },
174389  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
174390  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
174391  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
174392  0u,
174393  NULL },
174394  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
174395  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
174396  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
174397  0u,
174398  NULL },
174399  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
174400  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
174401  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
174402  0u,
174403  NULL },
174404  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
174405  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
174406  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
174407  0u,
174408  NULL },
174409  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
174410  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
174411  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
174412  0u,
174413  NULL },
174414  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID,
174415  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_INJECT_TYPE,
174416  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_ECC_TYPE,
174417  0u,
174418  NULL },
174419  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID,
174420  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_INJECT_TYPE,
174421  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_ECC_TYPE,
174422  0u,
174423  NULL },
174424  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174425  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174426  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174427  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174428  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174429  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174430  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174431  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174432  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174433  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174434  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174435  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174436  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174437  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174438  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174439  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174440  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174441  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174442  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174443  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174444  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174445  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174446  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174447  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174448  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174449  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174450  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174451  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174452  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174453  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174454  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174455  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174456  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174457  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174458  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174459  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174460  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174461  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174462  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174463  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174464  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174465  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174466  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174467  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174468  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174469  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
174470  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
174471  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
174472  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174473  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
174474  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
174475  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
174476  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
174477  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174478  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
174479  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
174480  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
174481  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
174482  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174483  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
174484  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
174485  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
174486  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
174487  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
174488  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
174489  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
174490  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
174491  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
174492  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174493  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
174494  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
174495  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
174496  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
174497  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174498  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
174499  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
174500  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
174501  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
174502  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
174503  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
174504  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
174505  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
174506  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
174507  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174508  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
174509  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
174510  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
174511  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
174512  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174513  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
174514  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
174515  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
174516  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
174517  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
174518  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
174519  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
174520  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
174521  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
174522  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174523  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
174524  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
174525  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
174526  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
174527  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
174528  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
174529  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
174530  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
174531  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
174532  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174533  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
174534  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
174535  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
174536  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
174537  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
174538  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
174539  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
174540  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
174541  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
174542  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174543  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
174544  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
174545  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
174546  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
174547  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
174548  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
174549  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
174550  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
174551  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
174552  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174553  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
174554  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
174555  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
174556  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
174557  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
174558  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
174559  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
174560  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
174561  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
174562  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174563  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
174564  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
174565  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
174566  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
174567  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174568  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
174569  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
174570  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
174571  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
174572  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
174573  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
174574  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_RAM_ID,
174575  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_INJECT_TYPE,
174576  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_ECC_TYPE,
174577  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS,
174578  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries },
174579  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_RAM_ID,
174580  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_INJECT_TYPE,
174581  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_ECC_TYPE,
174582  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS,
174583  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries },
174584  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174585  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174586  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174587  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174588  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174589  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174590  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174591  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174592  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174593  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174594  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174595  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174596  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174597  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174598  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174599  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174600  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174601  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174602  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174603  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174604  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174605  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174606  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174607  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174608  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174609  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174610  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174611  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174612  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174613  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174614  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
174615  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
174616  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
174617  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174618  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
174619  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_RAM_ID,
174620  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_INJECT_TYPE,
174621  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_ECC_TYPE,
174622  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
174623  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries },
174624  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_RAM_ID,
174625  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_INJECT_TYPE,
174626  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_ECC_TYPE,
174627  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
174628  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries },
174629  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_RAM_ID,
174630  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_INJECT_TYPE,
174631  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_ECC_TYPE,
174632  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS,
174633  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries },
174634  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_RAM_ID,
174635  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_INJECT_TYPE,
174636  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_ECC_TYPE,
174637  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS,
174638  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_groupEntries },
174639  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_RAM_ID,
174640  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_INJECT_TYPE,
174641  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_ECC_TYPE,
174642  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS,
174643  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries },
174644  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174645  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174646  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174647  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174648  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174649  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174650  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174651  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174652  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174653  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174654  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_RAM_ID,
174655  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_INJECT_TYPE,
174656  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_ECC_TYPE,
174657  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
174658  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries },
174659  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174660  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174661  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174662  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174663  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174664  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174665  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174666  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174667  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174668  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174669  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174670  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174671  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174672  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174673  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174674  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174675  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174676  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174677  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174678  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174679  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174680  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174681  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174682  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174683  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174684  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174685  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174686  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174687  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174688  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174689  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174690  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174691  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174692  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174693  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174694  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174695  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174696  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174697  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174698  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174699  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174700  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174701  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174702  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174703  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174704  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174705  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174706  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174707  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174708  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174709  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174710  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174711  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174712  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174713  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174714  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174715  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174716  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174717  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174718  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174719  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174720  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174721  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174722  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174723  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174724  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174725  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174726  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174727  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174728  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174729  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174730  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174731  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174732  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174733  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174734  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174735  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174736  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174737  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174738  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174739  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
174740  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
174741  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
174742  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
174743  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
174744  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
174745  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
174746  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
174747  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
174748  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
174749  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
174750  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
174751  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
174752  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
174753  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
174754  { SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_RAM_ID,
174755  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_INJECT_TYPE,
174756  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_ECC_TYPE,
174757  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS,
174758  SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries },
174759 };
174760 
174765 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
174766 {
174767  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
174768  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
174769  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
174770  0u,
174771  NULL },
174772  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
174773  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
174774  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
174775  0u,
174776  NULL },
174777  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
174778  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
174779  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
174780  0u,
174781  NULL },
174782  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
174783  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
174784  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
174785  0u,
174786  NULL },
174787  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
174788  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
174789  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
174790  0u,
174791  NULL },
174792  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
174793  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
174794  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
174795  0u,
174796  NULL },
174797  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
174798  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
174799  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
174800  0u,
174801  NULL },
174802  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
174803  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
174804  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
174805  0u,
174806  NULL },
174807  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
174808  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
174809  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
174810  0u,
174811  NULL },
174812  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
174813  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
174814  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
174815  0u,
174816  NULL },
174817  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
174818  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
174819  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
174820  0u,
174821  NULL },
174822  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
174823  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
174824  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
174825  0u,
174826  NULL },
174827  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
174828  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
174829  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
174830  0u,
174831  NULL },
174832  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
174833  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
174834  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
174835  0u,
174836  NULL },
174837  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
174838  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
174839  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
174840  0u,
174841  NULL },
174842  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
174843  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
174844  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
174845  0u,
174846  NULL },
174847  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
174848  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
174849  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
174850  0u,
174851  NULL },
174852  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
174853  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
174854  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
174855  0u,
174856  NULL },
174857  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
174858  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
174859  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
174860  0u,
174861  NULL },
174862  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
174863  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
174864  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
174865  0u,
174866  NULL },
174867  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
174868  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
174869  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
174870  0u,
174871  NULL },
174872  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
174873  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
174874  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
174875  0u,
174876  NULL },
174877  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
174878  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
174879  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
174880  0u,
174881  NULL },
174882  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
174883  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
174884  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
174885  0u,
174886  NULL },
174887  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
174888  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
174889  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
174890  0u,
174891  NULL },
174892  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
174893  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
174894  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
174895  0u,
174896  NULL },
174897  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
174898  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
174899  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
174900  0u,
174901  NULL },
174902  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
174903  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
174904  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
174905  0u,
174906  NULL },
174907  { SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID,
174908  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_INJECT_TYPE,
174909  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_ECC_TYPE,
174910  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS,
174911  SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries },
174912  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
174913  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
174914  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
174915  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
174916  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
174917  { SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
174918  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
174919  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
174920  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
174921  SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
174922  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
174923  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
174924  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
174925  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
174926  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
174927  { SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
174928  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
174929  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
174930  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
174931  SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
174932  { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_RAM_ID,
174933  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_INJECT_TYPE,
174934  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_ECC_TYPE,
174935  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS,
174936  SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries },
174937  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_RAM_ID,
174938  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
174939  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE,
174940  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS,
174941  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries },
174942  { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
174943  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
174944  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
174945  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
174946  SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries },
174947 };
174948 
174953 static const SDL_RAMIdEntry_t SDL_PCIE0_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE0_ECC_AGGR_CORE_0_NUM_RAMS] =
174954 {
174955  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
174956  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
174957  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
174958  0u,
174959  NULL },
174960  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID,
174961  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_INJECT_TYPE,
174962  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ECC_TYPE,
174963  0u,
174964  NULL },
174965  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
174966  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
174967  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
174968  0u,
174969  NULL },
174970  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID,
174971  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_INJECT_TYPE,
174972  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ECC_TYPE,
174973  0u,
174974  NULL },
174975  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
174976  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
174977  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
174978  0u,
174979  NULL },
174980  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
174981  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
174982  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
174983  0u,
174984  NULL },
174985  { SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID,
174986  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_INJECT_TYPE,
174987  SDL_PCIE0_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ECC_TYPE,
174988  0u,
174989  NULL },
174990 };
174991 
174996 static const SDL_RAMIdEntry_t SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable[SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS] =
174997 {
174998  { SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
174999  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
175000  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
175001  0u,
175002  NULL },
175003 };
175004 
175009 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS] =
175010 {
175011  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
175012  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
175013  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
175014  0u,
175015  NULL },
175016 };
175017 
175022 static const SDL_RAMIdEntry_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_NUM_RAMS] =
175023 {
175024  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_RAM_ID,
175025  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_INJECT_TYPE,
175026  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_ECC_TYPE,
175027  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS,
175028  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries },
175029  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
175030  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
175031  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
175032  0u,
175033  NULL },
175034  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
175035  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
175036  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
175037  0u,
175038  NULL },
175039  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
175040  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
175041  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
175042  0u,
175043  NULL },
175044  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID,
175045  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_INJECT_TYPE,
175046  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ECC_TYPE,
175047  0u,
175048  NULL },
175049  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID,
175050  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_INJECT_TYPE,
175051  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ECC_TYPE,
175052  0u,
175053  NULL },
175054  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID,
175055  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_INJECT_TYPE,
175056  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ECC_TYPE,
175057  0u,
175058  NULL },
175059  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
175060  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
175061  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
175062  0u,
175063  NULL },
175064  { SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
175065  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
175066  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
175067  0u,
175068  NULL },
175069 };
175070 
175075 static const SDL_RAMIdEntry_t SDL_I3C0_I3C_S_ECC_AGGR_RamIdTable[SDL_I3C0_I3C_S_ECC_AGGR_NUM_RAMS] =
175076 {
175077  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID,
175078  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_INJECT_TYPE,
175079  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ECC_TYPE,
175080  0u,
175081  NULL },
175082  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID,
175083  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_INJECT_TYPE,
175084  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ECC_TYPE,
175085  0u,
175086  NULL },
175087  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID,
175088  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_INJECT_TYPE,
175089  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ECC_TYPE,
175090  0u,
175091  NULL },
175092  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID,
175093  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_INJECT_TYPE,
175094  SDL_I3C0_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ECC_TYPE,
175095  0u,
175096  NULL },
175097  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID,
175098  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_INJECT_TYPE,
175099  SDL_I3C0_I3C_S_ECC_AGGR_I3C_IBI_ECC_TYPE,
175100  0u,
175101  NULL },
175102  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID,
175103  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_INJECT_TYPE,
175104  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ECC_TYPE,
175105  0u,
175106  NULL },
175107  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID,
175108  SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_INJECT_TYPE,
175109  SDL_I3C0_I3C_S_ECC_AGGR_I3C_TX_DATA_ECC_TYPE,
175110  0u,
175111  NULL },
175112  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID,
175113  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_INJECT_TYPE,
175114  SDL_I3C0_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ECC_TYPE,
175115  0u,
175116  NULL },
175117  { SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID,
175118  SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_INJECT_TYPE,
175119  SDL_I3C0_I3C_S_ECC_AGGR_I3C_RX_DATA_ECC_TYPE,
175120  0u,
175121  NULL },
175122 };
175123 
175128 static const SDL_RAMIdEntry_t SDL_VPAC0_ECC_AGGR_RamIdTable[SDL_VPAC0_ECC_AGGR_NUM_RAMS] =
175129 {
175130  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_RAM_ID,
175131  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_INJECT_TYPE,
175132  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_ECC_TYPE,
175133  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
175134  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries },
175135  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_RAM_ID,
175136  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_INJECT_TYPE,
175137  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_ECC_TYPE,
175138  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
175139  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries },
175140  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID,
175141  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_INJECT_TYPE,
175142  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_ECC_TYPE,
175143  0u,
175144  NULL },
175145  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID,
175146  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_INJECT_TYPE,
175147  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_ECC_TYPE,
175148  0u,
175149  NULL },
175150  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID,
175151  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_INJECT_TYPE,
175152  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_ECC_TYPE,
175153  0u,
175154  NULL },
175155  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID,
175156  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_INJECT_TYPE,
175157  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_ECC_TYPE,
175158  0u,
175159  NULL },
175160  { SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_ID,
175161  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_INJECT_TYPE,
175162  SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_ECC_TYPE,
175163  0u,
175164  NULL },
175165  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_RAM_ID,
175166  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_INJECT_TYPE,
175167  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_ECC_TYPE,
175168  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
175169  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_groupEntries },
175170  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_RAM_ID,
175171  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_INJECT_TYPE,
175172  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_ECC_TYPE,
175173  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
175174  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries },
175175  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID,
175176  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_RESPONSE_BUFFER0_INJECT_TYPE,
175177  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_RESPONSE_BUFFER0_ECC_TYPE,
175178  0u,
175179  NULL },
175180  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID,
175181  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER0_INJECT_TYPE,
175182  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER0_ECC_TYPE,
175183  0u,
175184  NULL },
175185  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID,
175186  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER1_INJECT_TYPE,
175187  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER1_ECC_TYPE,
175188  0u,
175189  NULL },
175190  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID,
175191  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER2_INJECT_TYPE,
175192  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_QUEUE_BUFFER2_ECC_TYPE,
175193  0u,
175194  NULL },
175195  { SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_STATE_BUFFER0_RAM_ID,
175196  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_STATE_BUFFER0_INJECT_TYPE,
175197  SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_TPRAM_DRU_STATE_BUFFER0_ECC_TYPE,
175198  0u,
175199  NULL },
175200 };
175201 
175206 static const SDL_RAMIdEntry_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NUM_RAMS] =
175207 {
175208  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_RAM_ID,
175209  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_INJECT_TYPE,
175210  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_ECC_TYPE,
175211  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
175212  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_groupEntries },
175213  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_TABLE_ECC_RAM_ID,
175214  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_TABLE_ECC_INJECT_TYPE,
175215  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_TABLE_ECC_ECC_TYPE,
175216  0u,
175217  NULL },
175218  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_RAM_ID,
175219  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_INJECT_TYPE,
175220  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_ECC_TYPE,
175221  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_MAX_NUM_CHECKERS,
175222  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_groupEntries },
175223  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_TABLE_ECC_RAM_ID,
175224  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_TABLE_ECC_INJECT_TYPE,
175225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_TABLE_ECC_ECC_TYPE,
175226  0u,
175227  NULL },
175228  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_RAM_ID,
175229  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_INJECT_TYPE,
175230  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_ECC_TYPE,
175231  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_MAX_NUM_CHECKERS,
175232  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_groupEntries },
175233  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_TABLE_ECC_RAM_ID,
175234  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_TABLE_ECC_INJECT_TYPE,
175235  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_TABLE_ECC_ECC_TYPE,
175236  0u,
175237  NULL },
175238  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_RAM_ID,
175239  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_INJECT_TYPE,
175240  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_ECC_TYPE,
175241  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_MAX_NUM_CHECKERS,
175242  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_groupEntries },
175243  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_TABLE_ECC_RAM_ID,
175244  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_TABLE_ECC_INJECT_TYPE,
175245  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_TABLE_ECC_ECC_TYPE,
175246  0u,
175247  NULL },
175248  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_RAM_ID,
175249  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_INJECT_TYPE,
175250  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_ECC_TYPE,
175251  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_MAX_NUM_CHECKERS,
175252  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_groupEntries },
175253  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_TABLE_ECC_RAM_ID,
175254  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_TABLE_ECC_INJECT_TYPE,
175255  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_TABLE_ECC_ECC_TYPE,
175256  0u,
175257  NULL },
175258  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_RAM_ID,
175259  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_INJECT_TYPE,
175260  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_ECC_TYPE,
175261  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_MAX_NUM_CHECKERS,
175262  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_groupEntries },
175263  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_RAM_ID,
175264  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_INJECT_TYPE,
175265  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_TLBIF_TLB_BANK_ECC_TYPE,
175266  0u,
175267  NULL },
175268  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_RAM_ID,
175269  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_INJECT_TYPE,
175270  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_ECC_TYPE,
175271  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS,
175272  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries },
175273  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_TLBIF_TLB_BANK_RAM_ID,
175274  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_TLBIF_TLB_BANK_INJECT_TYPE,
175275  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_TLBIF_TLB_BANK_ECC_TYPE,
175276  0u,
175277  NULL },
175278  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_RAM_ID,
175279  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_INJECT_TYPE,
175280  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_ECC_TYPE,
175281  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS,
175282  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_groupEntries },
175283  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_TLBIF_TLB_BANK_RAM_ID,
175284  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_TLBIF_TLB_BANK_INJECT_TYPE,
175285  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_TLBIF_TLB_BANK_ECC_TYPE,
175286  0u,
175287  NULL },
175288  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_RAM_ID,
175289  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_INJECT_TYPE,
175290  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_ECC_TYPE,
175291  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS,
175292  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_groupEntries },
175293  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X594_RAM_ID,
175294  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X594_INJECT_TYPE,
175295  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X594_ECC_TYPE,
175296  0u,
175297  NULL },
175298  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_1_RAM_ID,
175299  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_1_INJECT_TYPE,
175300  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_1_ECC_TYPE,
175301  0u,
175302  NULL },
175303  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_2_RAM_ID,
175304  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_2_INJECT_TYPE,
175305  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_2_ECC_TYPE,
175306  0u,
175307  NULL },
175308  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_3_RAM_ID,
175309  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_3_INJECT_TYPE,
175310  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_3_ECC_TYPE,
175311  0u,
175312  NULL },
175313  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_4_RAM_ID,
175314  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_4_INJECT_TYPE,
175315  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X139_4_ECC_TYPE,
175316  0u,
175317  NULL },
175318  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_1_RAM_ID,
175319  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_1_INJECT_TYPE,
175320  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_1_ECC_TYPE,
175321  0u,
175322  NULL },
175323  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_2_RAM_ID,
175324  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_2_INJECT_TYPE,
175325  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_2_ECC_TYPE,
175326  0u,
175327  NULL },
175328  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_3_RAM_ID,
175329  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_3_INJECT_TYPE,
175330  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_3_ECC_TYPE,
175331  0u,
175332  NULL },
175333  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_4_RAM_ID,
175334  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_4_INJECT_TYPE,
175335  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X72_4_ECC_TYPE,
175336  0u,
175337  NULL },
175338  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_RAM_ID,
175339  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_INJECT_TYPE,
175340  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_ECC_TYPE,
175341  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS,
175342  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_groupEntries },
175343  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_RAM_ID,
175344  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_INJECT_TYPE,
175345  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_ECC_TYPE,
175346  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS,
175347  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries },
175348  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_RAM_ID,
175349  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_INJECT_TYPE,
175350  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_ECC_TYPE,
175351  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS,
175352  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries },
175353  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175354  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175355  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175356  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175357  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175358  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_RAM_ID,
175359  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_INJECT_TYPE,
175360  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_ECC_TYPE,
175361  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_MAX_NUM_CHECKERS,
175362  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_groupEntries },
175363  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X142_RAM_ID,
175364  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X142_INJECT_TYPE,
175365  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_32X142_ECC_TYPE,
175366  0u,
175367  NULL },
175368  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X294_RAM_ID,
175369  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X294_INJECT_TYPE,
175370  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_16X294_ECC_TYPE,
175371  0u,
175372  NULL },
175373  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4608X68_RAM_ID,
175374  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4608X68_INJECT_TYPE,
175375  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4608X68_ECC_TYPE,
175376  0u,
175377  NULL },
175378  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_1_RAM_ID,
175379  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_1_INJECT_TYPE,
175380  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_1_ECC_TYPE,
175381  0u,
175382  NULL },
175383  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_2_RAM_ID,
175384  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_2_INJECT_TYPE,
175385  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_2_ECC_TYPE,
175386  0u,
175387  NULL },
175388  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_3_RAM_ID,
175389  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_3_INJECT_TYPE,
175390  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_3_ECC_TYPE,
175391  0u,
175392  NULL },
175393  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_4_RAM_ID,
175394  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_4_INJECT_TYPE,
175395  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_4X62_4_ECC_TYPE,
175396  0u,
175397  NULL },
175398  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_1_RAM_ID,
175399  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_1_INJECT_TYPE,
175400  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_1_ECC_TYPE,
175401  0u,
175402  NULL },
175403  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_2_RAM_ID,
175404  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_2_INJECT_TYPE,
175405  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_2_ECC_TYPE,
175406  0u,
175407  NULL },
175408  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_3_RAM_ID,
175409  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_3_INJECT_TYPE,
175410  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_3_ECC_TYPE,
175411  0u,
175412  NULL },
175413  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_4_RAM_ID,
175414  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_4_INJECT_TYPE,
175415  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MMU600_SPRAM_ECC_1152X108_4_ECC_TYPE,
175416  0u,
175417  NULL },
175418  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_RAM_ID,
175419  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_INJECT_TYPE,
175420  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_ECC_TYPE,
175421  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS,
175422  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries },
175423  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_RAM_ID,
175424  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_INJECT_TYPE,
175425  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_ECC_TYPE,
175426  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS,
175427  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries },
175428  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_ID,
175429  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_CFIFO_WRAP_CFIFO_IFIFO_BUF_INJECT_TYPE,
175430  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_CFIFO_WRAP_CFIFO_IFIFO_BUF_ECC_TYPE,
175431  0u,
175432  NULL },
175433  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_ID,
175434  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_WFIFO_WRAP_WFIFO_IFIFO_BUF_INJECT_TYPE,
175435  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_WFIFO_WRAP_WFIFO_IFIFO_BUF_ECC_TYPE,
175436  0u,
175437  NULL },
175438  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_RAM_ID,
175439  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_INJECT_TYPE,
175440  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_ECC_TYPE,
175441  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175442  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_groupEntries },
175443  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_ID,
175444  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_CFIFO_WRAP_CFIFO_IFIFO_BUF_INJECT_TYPE,
175445  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_CFIFO_WRAP_CFIFO_IFIFO_BUF_ECC_TYPE,
175446  0u,
175447  NULL },
175448  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_ID,
175449  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_WFIFO_WRAP_WFIFO_IFIFO_BUF_INJECT_TYPE,
175450  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_WFIFO_WRAP_WFIFO_IFIFO_BUF_ECC_TYPE,
175451  0u,
175452  NULL },
175453  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_RAM_ID,
175454  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_INJECT_TYPE,
175455  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_ECC_TYPE,
175456  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175457  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_groupEntries },
175458  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_CFIFO_WRAP_CFIFO_IFIFO_BUF_RAM_ID,
175459  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_CFIFO_WRAP_CFIFO_IFIFO_BUF_INJECT_TYPE,
175460  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_CFIFO_WRAP_CFIFO_IFIFO_BUF_ECC_TYPE,
175461  0u,
175462  NULL },
175463  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_WFIFO_WRAP_WFIFO_IFIFO_BUF_RAM_ID,
175464  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_WFIFO_WRAP_WFIFO_IFIFO_BUF_INJECT_TYPE,
175465  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_WFIFO_WRAP_WFIFO_IFIFO_BUF_ECC_TYPE,
175466  0u,
175467  NULL },
175468  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_RAM_ID,
175469  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_INJECT_TYPE,
175470  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_ECC_TYPE,
175471  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175472  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_groupEntries },
175473  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175474  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175475  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175476  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175477  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175478  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175479  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175480  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175481  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175482  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175483  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175484  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175485  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175486  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175487  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175488  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175489  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175490  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175491  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175492  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175493  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175494  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175495  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175496  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175497  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175498  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175499  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175500  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175501  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175502  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175503  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175504  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175505  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175506  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175507  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175508  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175509  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175510  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175511  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175512  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175513  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175514  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175515  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175516  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175517  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175518  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175519  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175520  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175521  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175522  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175523  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175524  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175525  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175526  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175527  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175528  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175529  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175530  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175531  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175532  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175533  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175534  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175535  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175536  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175537  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175538  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175539  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175540  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175541  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175542  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175543  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175544  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175545  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175546  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175547  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175548  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175549  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175550  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175551  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175552  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175553  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175554  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175555  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175556  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175557  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175558  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175559  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175560  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175561  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175562  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175563  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175564  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175565  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175566  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175567  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175568  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175569  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175570  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175571  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175572  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175573  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175574  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175575  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175576  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175577  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175578  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
175579  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
175580  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
175581  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
175582  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
175583  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175584  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175585  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175586  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175587  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175588  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175589  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175590  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175591  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175592  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175593  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175594  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175595  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175596  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175597  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175598  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175599  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175600  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175601  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175602  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175603  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175604  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175605  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175606  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175607  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175608  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175609  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175610  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175611  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175612  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175613  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175614  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175615  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175616  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175617  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175618  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175619  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175620  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175621  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175622  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175623  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175624  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175625  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175626  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175627  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175628  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175629  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175630  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175631  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175632  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175633  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175634  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175635  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175636  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175637  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175638  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175639  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175640  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175641  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175642  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175643  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175644  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175645  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175646  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175647  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175648  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175649  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175650  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175651  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175652  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175653  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175654  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175655  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175656  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175657  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175658  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175659  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175660  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175661  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175662  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175663  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175664  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175665  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175666  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175667  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175668  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
175669  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
175670  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
175671  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175672  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
175673  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
175674  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
175675  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
175676  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
175677  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
175678  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
175679  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
175680  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
175681  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
175682  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
175683  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_RAM_ID,
175684  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_INJECT_TYPE,
175685  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_ECC_TYPE,
175686  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS,
175687  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries },
175688  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_RAM_ID,
175689  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_INJECT_TYPE,
175690  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_ECC_TYPE,
175691  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS,
175692  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries },
175693  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_RAM_ID,
175694  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_INJECT_TYPE,
175695  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_ECC_TYPE,
175696  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_MAX_NUM_CHECKERS,
175697  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries },
175698  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_RAM_ID,
175699  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_INJECT_TYPE,
175700  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_ECC_TYPE,
175701  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_MAX_NUM_CHECKERS,
175702  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_groupEntries },
175703  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_RAM_ID,
175704  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_INJECT_TYPE,
175705  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_ECC_TYPE,
175706  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_MAX_NUM_CHECKERS,
175707  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_groupEntries },
175708  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_RAM_ID,
175709  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_INJECT_TYPE,
175710  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_ECC_TYPE,
175711  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_MAX_NUM_CHECKERS,
175712  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_groupEntries },
175713  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_RAM_ID,
175714  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_INJECT_TYPE,
175715  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_ECC_TYPE,
175716  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_MAX_NUM_CHECKERS,
175717  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_groupEntries },
175718  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_RAM_ID,
175719  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_INJECT_TYPE,
175720  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_ECC_TYPE,
175721  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_MAX_NUM_CHECKERS,
175722  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_groupEntries },
175723  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_RAM_ID,
175724  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_INJECT_TYPE,
175725  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_ECC_TYPE,
175726  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_MAX_NUM_CHECKERS,
175727  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_groupEntries },
175728  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
175729  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
175730  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
175731  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
175732  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
175733  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_RAM_ID,
175734  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_INJECT_TYPE,
175735  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_ECC_TYPE,
175736  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS,
175737  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_groupEntries },
175738  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_RAM_ID,
175739  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_INJECT_TYPE,
175740  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_ECC_TYPE,
175741  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS,
175742  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries },
175743  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
175744  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
175745  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
175746  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
175747  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
175748  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
175749  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
175750  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
175751  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
175752  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
175753  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_RAM_ID,
175754  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_INJECT_TYPE,
175755  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_ECC_TYPE,
175756  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
175757  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries },
175758  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_RAM_ID,
175759  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_INJECT_TYPE,
175760  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_ECC_TYPE,
175761  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
175762  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries },
175763  { SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_RAM_ID,
175764  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_INJECT_TYPE,
175765  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_ECC_TYPE,
175766  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS,
175767  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_groupEntries },
175768 };
175769 
175774 static const SDL_RAMIdEntry_t SDL_MCU_I3C0_I3C_P_ECC_AGGR_RamIdTable[SDL_MCU_I3C0_I3C_P_ECC_AGGR_NUM_RAMS] =
175775 {
175776  { SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_RAM_ID,
175777  SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_INJECT_TYPE,
175778  SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_ECC_TYPE,
175779  SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
175780  SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries },
175781 };
175782 
175787 static const SDL_RAMIdEntry_t SDL_PCIE1_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE1_ECC_AGGR_CORE_0_NUM_RAMS] =
175788 {
175789  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
175790  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
175791  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
175792  0u,
175793  NULL },
175794  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID,
175795  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_INJECT_TYPE,
175796  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ECC_TYPE,
175797  0u,
175798  NULL },
175799  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
175800  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
175801  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
175802  0u,
175803  NULL },
175804  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID,
175805  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_INJECT_TYPE,
175806  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ECC_TYPE,
175807  0u,
175808  NULL },
175809  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
175810  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
175811  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
175812  0u,
175813  NULL },
175814  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
175815  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
175816  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
175817  0u,
175818  NULL },
175819  { SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID,
175820  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_INJECT_TYPE,
175821  SDL_PCIE1_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ECC_TYPE,
175822  0u,
175823  NULL },
175824 };
175825 
175830 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS] =
175831 {
175832  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
175833  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
175834  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
175835  0u,
175836  NULL },
175837  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
175838  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
175839  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
175840  0u,
175841  NULL },
175842  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
175843  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
175844  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
175845  0u,
175846  NULL },
175847  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
175848  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
175849  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
175850  0u,
175851  NULL },
175852  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
175853  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
175854  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
175855  0u,
175856  NULL },
175857  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
175858  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
175859  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
175860  0u,
175861  NULL },
175862  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
175863  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
175864  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
175865  0u,
175866  NULL },
175867  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
175868  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
175869  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
175870  0u,
175871  NULL },
175872  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
175873  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
175874  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
175875  0u,
175876  NULL },
175877  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
175878  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
175879  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
175880  0u,
175881  NULL },
175882  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
175883  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
175884  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
175885  0u,
175886  NULL },
175887  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
175888  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
175889  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
175890  0u,
175891  NULL },
175892  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
175893  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
175894  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
175895  0u,
175896  NULL },
175897  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
175898  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
175899  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
175900  0u,
175901  NULL },
175902  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
175903  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
175904  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
175905  0u,
175906  NULL },
175907  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
175908  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
175909  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
175910  0u,
175911  NULL },
175912  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
175913  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
175914  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
175915  0u,
175916  NULL },
175917  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
175918  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
175919  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
175920  0u,
175921  NULL },
175922  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
175923  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
175924  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
175925  0u,
175926  NULL },
175927  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
175928  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
175929  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
175930  0u,
175931  NULL },
175932  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
175933  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
175934  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
175935  0u,
175936  NULL },
175937  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
175938  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
175939  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
175940  0u,
175941  NULL },
175942  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
175943  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
175944  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
175945  0u,
175946  NULL },
175947  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
175948  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
175949  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
175950  0u,
175951  NULL },
175952  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
175953  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
175954  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
175955  0u,
175956  NULL },
175957  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
175958  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
175959  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
175960  0u,
175961  NULL },
175962  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
175963  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
175964  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
175965  0u,
175966  NULL },
175967  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
175968  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
175969  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
175970  0u,
175971  NULL },
175972  { SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID,
175973  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_INJECT_TYPE,
175974  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_ECC_TYPE,
175975  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS,
175976  SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries },
175977  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
175978  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
175979  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
175980  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
175981  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
175982  { SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
175983  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
175984  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
175985  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
175986  SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
175987  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
175988  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
175989  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
175990  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
175991  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
175992  { SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
175993  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
175994  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
175995  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
175996  SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
175997  { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_RAM_ID,
175998  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_INJECT_TYPE,
175999  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_ECC_TYPE,
176000  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS,
176001  SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries },
176002  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_RAM_ID,
176003  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
176004  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE,
176005  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS,
176006  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries },
176007  { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
176008  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
176009  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
176010  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
176011  SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries },
176012 };
176013 
176018 static const SDL_RAMIdEntry_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RamIdTable[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_NUM_RAMS] =
176019 {
176020  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_RAM_ID,
176021  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_INJECT_TYPE,
176022  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_ECC_ECC_TYPE,
176023  0u,
176024  NULL },
176025  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_RAM_ID,
176026  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_INJECT_TYPE,
176027  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_ECC_TYPE,
176028  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
176029  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries },
176030  { SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_RAM_ID,
176031  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
176032  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
176033  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
176034  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries },
176035 };
176036 
176041 static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
176042 {
176043  { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
176044  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
176045  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
176046  0u,
176047  NULL },
176048 };
176049 
176054 static const SDL_RAMIdEntry_t SDL_NAVSS0_NBSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_NBSS_ECC_AGGR0_NUM_RAMS] =
176055 {
176056  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_RAM_ID,
176057  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_INJECT_TYPE,
176058  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_ECC_TYPE,
176059  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS,
176060  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_groupEntries },
176061  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_RAM_ID,
176062  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_INJECT_TYPE,
176063  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_ECC_TYPE,
176064  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176065  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries },
176066  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_RAM_ID,
176067  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_INJECT_TYPE,
176068  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_ECC_TYPE,
176069  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176070  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries },
176071  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_RAM_ID,
176072  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_INJECT_TYPE,
176073  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_ECC_TYPE,
176074  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176075  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries },
176076  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_RAM_ID,
176077  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_INJECT_TYPE,
176078  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_ECC_TYPE,
176079  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176080  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries },
176081  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_RAM_ID,
176082  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_INJECT_TYPE,
176083  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_ECC_TYPE,
176084  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176085  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries },
176086  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_RAM_ID,
176087  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_INJECT_TYPE,
176088  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_ECC_TYPE,
176089  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176090  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries },
176091  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_RAM_ID,
176092  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_INJECT_TYPE,
176093  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_ECC_TYPE,
176094  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176095  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries },
176096  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_RAM_ID,
176097  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_INJECT_TYPE,
176098  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_ECC_TYPE,
176099  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176100  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries },
176101  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_RAM_ID,
176102  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_INJECT_TYPE,
176103  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_ECC_TYPE,
176104  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS,
176105  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries },
176106  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
176107  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
176108  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
176109  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
176110  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
176111  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
176112  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
176113  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
176114  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176115  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
176116  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
176117  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
176118  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
176119  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176120  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
176121  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
176122  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
176123  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
176124  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
176125  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
176126  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_RAM_ID,
176127  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_INJECT_TYPE,
176128  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_ECC_TYPE,
176129  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_MAX_NUM_CHECKERS,
176130  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_groupEntries },
176131  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_RAM_ID,
176132  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_INJECT_TYPE,
176133  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_ECC_TYPE,
176134  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176135  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries },
176136  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_RAM_ID,
176137  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_INJECT_TYPE,
176138  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_ECC_TYPE,
176139  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176140  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries },
176141  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_RAM_ID,
176142  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_INJECT_TYPE,
176143  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_ECC_TYPE,
176144  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176145  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries },
176146  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_RAM_ID,
176147  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_INJECT_TYPE,
176148  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_ECC_TYPE,
176149  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176150  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries },
176151  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_RAM_ID,
176152  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_INJECT_TYPE,
176153  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_ECC_TYPE,
176154  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176155  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries },
176156  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_RAM_ID,
176157  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_INJECT_TYPE,
176158  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_ECC_TYPE,
176159  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176160  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries },
176161  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_RAM_ID,
176162  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_INJECT_TYPE,
176163  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_ECC_TYPE,
176164  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176165  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries },
176166  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_RAM_ID,
176167  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_INJECT_TYPE,
176168  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_ECC_TYPE,
176169  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176170  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries },
176171  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_RAM_ID,
176172  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_INJECT_TYPE,
176173  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_ECC_TYPE,
176174  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS,
176175  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries },
176176  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
176177  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
176178  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
176179  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
176180  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
176181  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
176182  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
176183  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
176184  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
176185  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
176186  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
176187  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
176188  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
176189  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
176190  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
176191  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
176192  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
176193  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
176194  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
176195  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
176196  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_RAM_ID,
176197  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_INJECT_TYPE,
176198  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_ECC_TYPE,
176199  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_MAX_NUM_CHECKERS,
176200  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_groupEntries },
176201  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_RAM_ID,
176202  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_INJECT_TYPE,
176203  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_ECC_TYPE,
176204  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS,
176205  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries },
176206  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_RAM_ID,
176207  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_INJECT_TYPE,
176208  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_ECC_TYPE,
176209  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
176210  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries },
176211  { SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
176212  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
176213  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
176214  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
176215  SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
176216 };
176217 
176222 static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
176223 {
176224  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
176225  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
176226  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
176227  0u,
176228  NULL },
176229  { SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
176230  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
176231  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
176232  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
176233  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
176234 };
176235 
176240 static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_NUM_RAMS] =
176241 {
176242  { SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID,
176243  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_INJECT_TYPE,
176244  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ECC_TYPE,
176245  0u,
176246  NULL },
176247 };
176248 
176253 static const SDL_RAMIdEntry_t SDL_IDOM1_ECC_AGGR0_RamIdTable[SDL_IDOM1_ECC_AGGR0_NUM_RAMS] =
176254 {
176255  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
176256  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176257  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176258  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176259  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
176260  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
176261  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176262  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176263  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176264  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries },
176265  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
176266  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176267  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176268  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176269  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries },
176270  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
176271  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176272  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176273  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176274  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
176275  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176276  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176277  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176278  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176279  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176280  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176281  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176282  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176283  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176284  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176285  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176286  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176287  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176288  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176289  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176290  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176291  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176292  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176293  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176294  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176295  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176296  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176297  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176298  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176299  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176300  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176301  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176302  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176303  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176304  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176305  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176306  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176307  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176308  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176309  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176310  { SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176311  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176312  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176313  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176314  SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176315  { SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_RAM_ID,
176316  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
176317  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_ECC_TYPE,
176318  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
176319  SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries },
176320  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
176321  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176322  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176323  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176324  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
176325  { SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
176326  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176327  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176328  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176329  SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries },
176330 };
176331 
176336 static const SDL_RAMIdEntry_t SDL_IDOM1_ECC_AGGR1_RamIdTable[SDL_IDOM1_ECC_AGGR1_NUM_RAMS] =
176337 {
176338  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
176339  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176340  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176341  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176342  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
176343  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
176344  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176345  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176346  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176347  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries },
176348  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
176349  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176350  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176351  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176352  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries },
176353  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
176354  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176355  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176356  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176357  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
176358  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176359  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176360  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176361  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176362  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176363  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176364  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176365  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176366  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176367  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176368  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176369  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176370  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176371  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176372  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176373  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176374  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176375  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176376  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176377  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176378  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176379  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176380  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176381  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176382  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176383  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176384  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176385  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176386  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176387  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176388  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_RAM_ID,
176389  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176390  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176391  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176392  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries },
176393  { SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_RAM_ID,
176394  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176395  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176396  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176397  SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries },
176398  { SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_RAM_ID,
176399  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
176400  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_ECC_TYPE,
176401  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
176402  SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries },
176403  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
176404  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176405  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176406  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176407  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
176408  { SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
176409  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176410  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176411  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176412  SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries },
176413 };
176414 
176419 static const SDL_RAMIdEntry_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RamIdTable[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_NUM_RAMS] =
176420 {
176421  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
176422  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176423  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176424  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176425  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
176426  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
176427  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176428  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176429  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176430  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries },
176431  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
176432  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176433  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176434  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176435  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries },
176436  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
176437  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176438  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176439  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176440  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
176441  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176442  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176443  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176444  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176445  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176446  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176447  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176448  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176449  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176450  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176451  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176452  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176453  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176454  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176455  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176456  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176457  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176458  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176459  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176460  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176461  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176462  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176463  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176464  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176465  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176466  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176467  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176468  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176469  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176470  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176471  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176472  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176473  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176474  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176475  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176476  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176477  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176478  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176479  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176480  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176481  { SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_RAM_ID,
176482  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
176483  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
176484  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
176485  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries },
176486 };
176487 
176492 static const SDL_RAMIdEntry_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
176493 {
176494  { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
176495  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
176496  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
176497  0u,
176498  NULL },
176499  { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
176500  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
176501  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
176502  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
176503  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
176504 };
176505 
176510 static const SDL_RAMIdEntry_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_NUM_RAMS] =
176511 {
176512  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_RAM_ID,
176513  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_INJECT_TYPE,
176514  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_ECC_TYPE,
176515  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS,
176516  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries },
176517  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
176518  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
176519  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
176520  0u,
176521  NULL },
176522  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
176523  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
176524  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
176525  0u,
176526  NULL },
176527  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
176528  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
176529  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
176530  0u,
176531  NULL },
176532  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID,
176533  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_INJECT_TYPE,
176534  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ECC_TYPE,
176535  0u,
176536  NULL },
176537  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID,
176538  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_INJECT_TYPE,
176539  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ECC_TYPE,
176540  0u,
176541  NULL },
176542  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID,
176543  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_INJECT_TYPE,
176544  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ECC_TYPE,
176545  0u,
176546  NULL },
176547  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
176548  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
176549  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
176550  0u,
176551  NULL },
176552  { SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
176553  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
176554  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
176555  0u,
176556  NULL },
176557 };
176558 
176563 static const SDL_RAMIdEntry_t SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable[SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS] =
176564 {
176565  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_ID,
176566  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_INJECT_TYPE,
176567  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_ECC_TYPE,
176568  0u,
176569  NULL },
176570  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_ID,
176571  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_INJECT_TYPE,
176572  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_ECC_TYPE,
176573  0u,
176574  NULL },
176575  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_ID,
176576  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_INJECT_TYPE,
176577  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_ECC_TYPE,
176578  0u,
176579  NULL },
176580  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
176581  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
176582  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
176583  0u,
176584  NULL },
176585  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
176586  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
176587  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
176588  0u,
176589  NULL },
176590  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
176591  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
176592  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
176593  0u,
176594  NULL },
176595  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
176596  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
176597  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
176598  0u,
176599  NULL },
176600  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
176601  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
176602  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
176603  0u,
176604  NULL },
176605  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
176606  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
176607  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
176608  0u,
176609  NULL },
176610  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
176611  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
176612  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
176613  0u,
176614  NULL },
176615  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
176616  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
176617  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
176618  0u,
176619  NULL },
176620  { SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
176621  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
176622  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
176623  0u,
176624  NULL },
176625 };
176626 
176631 static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
176632 {
176633  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
176634  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
176635  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
176636  0u,
176637  NULL },
176638  { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
176639  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
176640  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
176641  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
176642  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
176643 };
176644 
176649 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
176650 {
176651  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
176652  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
176653  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
176654  0u,
176655  NULL },
176656  { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
176657  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
176658  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
176659  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
176660  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
176661 };
176662 
176667 static const SDL_RAMIdEntry_t SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS] =
176668 {
176669  { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
176670  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
176671  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
176672  0u,
176673  NULL },
176674  { SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
176675  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
176676  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
176677  0u,
176678  NULL },
176679 };
176680 
176685 static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_NUM_RAMS] =
176686 {
176687  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_RAM_ID,
176688  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_INJECT_TYPE,
176689  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_ECC_TYPE,
176690  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS,
176691  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries },
176692  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_RAM_ID,
176693  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_INJECT_TYPE,
176694  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_DMA_PSIL_FIFO_ECC_TYPE,
176695  0u,
176696  NULL },
176697  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_RAM_ID,
176698  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_INJECT_TYPE,
176699  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_TX_SHIM_KSDMA_PSIL_ENDPT_IPCFIFO_F0_TPRAM_256X167_SBW_SR_ECC_TYPE,
176700  0u,
176701  NULL },
176702 };
176703 
176708 static const SDL_RAMIdEntry_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RamIdTable[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_NUM_RAMS] =
176709 {
176710  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
176711  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176712  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176713  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176714  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
176715  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
176716  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176717  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176718  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176719  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries },
176720  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
176721  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176722  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176723  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176724  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries },
176725  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
176726  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176727  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176728  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176729  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
176730  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176731  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176732  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176733  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176734  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176735  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176736  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176737  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176738  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176739  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176740  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176741  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176742  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176743  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176744  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176745  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176746  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176747  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176748  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176749  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176750  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176751  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176752  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176753  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176754  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176755  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176756  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176757  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176758  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176759  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176760  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_RAM_ID,
176761  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
176762  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
176763  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176764  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries },
176765  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_RAM_ID,
176766  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
176767  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_ECC_TYPE,
176768  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176769  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries },
176770  { SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_RAM_ID,
176771  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
176772  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
176773  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
176774  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries },
176775 };
176776 
176781 static const SDL_RAMIdEntry_t SDL_MCU_I3C1_I3C_S_ECC_AGGR_RamIdTable[SDL_MCU_I3C1_I3C_S_ECC_AGGR_NUM_RAMS] =
176782 {
176783  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_RAM_ID,
176784  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_INJECT_TYPE,
176785  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBIR_QUEUE_ECC_TYPE,
176786  0u,
176787  NULL },
176788  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_RAM_ID,
176789  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_INJECT_TYPE,
176790  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_RX_ECC_TYPE,
176791  0u,
176792  NULL },
176793  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_RAM_ID,
176794  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_INJECT_TYPE,
176795  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMDR_QUEUE_ECC_TYPE,
176796  0u,
176797  NULL },
176798  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_RAM_ID,
176799  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_INJECT_TYPE,
176800  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_SLV_DDR_TX_ECC_TYPE,
176801  0u,
176802  NULL },
176803  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_RAM_ID,
176804  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_INJECT_TYPE,
176805  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_IBI_ECC_TYPE,
176806  0u,
176807  NULL },
176808  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_RAM_ID,
176809  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_INJECT_TYPE,
176810  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD1_ECC_TYPE,
176811  0u,
176812  NULL },
176813  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_RAM_ID,
176814  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_INJECT_TYPE,
176815  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_TX_DATA_ECC_TYPE,
176816  0u,
176817  NULL },
176818  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_RAM_ID,
176819  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_INJECT_TYPE,
176820  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_CMD_WRD0_ECC_TYPE,
176821  0u,
176822  NULL },
176823  { SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_RAM_ID,
176824  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_INJECT_TYPE,
176825  SDL_MCU_I3C1_I3C_S_ECC_AGGR_I3C_RX_DATA_ECC_TYPE,
176826  0u,
176827  NULL },
176828 };
176829 
176834 static const SDL_RAMIdEntry_t SDL_MCU_I3C1_I3C_P_ECC_AGGR_RamIdTable[SDL_MCU_I3C1_I3C_P_ECC_AGGR_NUM_RAMS] =
176835 {
176836  { SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_RAM_ID,
176837  SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_INJECT_TYPE,
176838  SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_ECC_TYPE,
176839  SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
176840  SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries },
176841 };
176842 
176847 static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_NUM_RAMS] =
176848 {
176849  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_RAM_ID,
176850  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_INJECT_TYPE,
176851  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER0_FIFO_ECC_TYPE,
176852  0u,
176853  NULL },
176854  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_RAM_ID,
176855  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_INJECT_TYPE,
176856  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER1_FIFO_ECC_TYPE,
176857  0u,
176858  NULL },
176859  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_RAM_ID,
176860  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_INJECT_TYPE,
176861  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER2_FIFO_ECC_TYPE,
176862  0u,
176863  NULL },
176864  { SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_RAM_ID,
176865  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_INJECT_TYPE,
176866  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_CSI_TX_IF_RAM_WRAPPER3_FIFO_ECC_TYPE,
176867  0u,
176868  NULL },
176869 };
176870 
176875 static const SDL_RAMIdEntry_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RamIdTable[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_NUM_RAMS] =
176876 {
176877  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_RAM_ID,
176878  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
176879  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
176880  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176881  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries },
176882  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_RAM_ID,
176883  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_INJECT_TYPE,
176884  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ECC_TYPE,
176885  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
176886  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries },
176887  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_RAM_ID,
176888  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
176889  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
176890  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176891  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries },
176892  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_RAM_ID,
176893  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_INJECT_TYPE,
176894  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_ECC_TYPE,
176895  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
176896  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries },
176897  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_RAM_ID,
176898  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_INJECT_TYPE,
176899  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_ECC_TYPE,
176900  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
176901  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries },
176902  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_RAM_ID,
176903  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_INJECT_TYPE,
176904  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_ECC_TYPE,
176905  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
176906  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries },
176907  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_RAM_ID,
176908  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_INJECT_TYPE,
176909  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_ECC_TYPE,
176910  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
176911  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries },
176912  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
176913  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
176914  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
176915  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
176916  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
176917  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
176918  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
176919  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
176920  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
176921  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
176922  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_RAM_ID,
176923  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_INJECT_TYPE,
176924  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_ECC_TYPE,
176925  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
176926  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_groupEntries },
176927  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_RAM_ID,
176928  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_INJECT_TYPE,
176929  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_ECC_TYPE,
176930  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
176931  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_groupEntries },
176932  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_RAM_ID,
176933  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_INJECT_TYPE,
176934  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_ECC_TYPE,
176935  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
176936  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_groupEntries },
176937  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_RAM_ID,
176938  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
176939  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
176940  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
176941  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_groupEntries },
176942  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_RAM_ID,
176943  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_INJECT_TYPE,
176944  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_ECC_TYPE,
176945  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
176946  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_groupEntries },
176947  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
176948  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
176949  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
176950  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
176951  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_groupEntries },
176952  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
176953  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
176954  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
176955  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
176956  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
176957  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
176958  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
176959  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
176960  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
176961  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
176962  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
176963  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
176964  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
176965  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
176966  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_groupEntries },
176967  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
176968  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
176969  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
176970  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
176971  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_groupEntries },
176972  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
176973  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
176974  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
176975  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
176976  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
176977  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
176978  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
176979  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
176980  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
176981  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_groupEntries },
176982  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
176983  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
176984  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
176985  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
176986  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_groupEntries },
176987  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
176988  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
176989  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
176990  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
176991  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
176992  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_RAM_ID,
176993  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
176994  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
176995  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
176996  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_groupEntries },
176997  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_RAM_ID,
176998  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
176999  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
177000  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
177001  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_groupEntries },
177002  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
177003  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
177004  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
177005  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
177006  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
177007  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_RAM_ID,
177008  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
177009  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
177010  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
177011  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries },
177012  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_RAM_ID,
177013  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_INJECT_TYPE,
177014  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_ECC_TYPE,
177015  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
177016  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries },
177017  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_RAM_ID,
177018  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_INJECT_TYPE,
177019  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_ECC_TYPE,
177020  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
177021  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries },
177022  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_RAM_ID,
177023  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_INJECT_TYPE,
177024  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_ECC_TYPE,
177025  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
177026  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries },
177027  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_RAM_ID,
177028  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_INJECT_TYPE,
177029  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_ECC_TYPE,
177030  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS,
177031  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries },
177032  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_RAM_ID,
177033  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
177034  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
177035  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
177036  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries },
177037  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_RAM_ID,
177038  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
177039  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_ECC_TYPE,
177040  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
177041  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_groupEntries },
177042  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_RAM_ID,
177043  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_INJECT_TYPE,
177044  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ECC_TYPE,
177045  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS,
177046  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries },
177047  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_ID,
177048  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_INJECT_TYPE,
177049  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ECC_TYPE,
177050  0u,
177051  NULL },
177052  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_ID,
177053  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_INJECT_TYPE,
177054  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ECC_TYPE,
177055  0u,
177056  NULL },
177057  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_RAM_ID,
177058  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_INJECT_TYPE,
177059  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_ECC_TYPE,
177060  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS,
177061  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries },
177062  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_RAM_ID,
177063  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_INJECT_TYPE,
177064  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_ECC_TYPE,
177065  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS,
177066  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries },
177067  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
177068  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
177069  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
177070  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
177071  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
177072  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_RAM_ID,
177073  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_INJECT_TYPE,
177074  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ECC_TYPE,
177075  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS,
177076  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries },
177077  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_RAM_ID,
177078  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_INJECT_TYPE,
177079  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_ECC_TYPE,
177080  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
177081  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries },
177082  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_RAM_ID,
177083  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_INJECT_TYPE,
177084  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_ECC_TYPE,
177085  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS,
177086  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_groupEntries },
177087  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_RAM_ID,
177088  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_INJECT_TYPE,
177089  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_ECC_TYPE,
177090  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS,
177091  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_groupEntries },
177092  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_RAM_ID,
177093  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_INJECT_TYPE,
177094  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_ECC_TYPE,
177095  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS,
177096  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_groupEntries },
177097  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
177098  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
177099  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
177100  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
177101  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
177102  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
177103  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
177104  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
177105  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
177106  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
177107  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
177108  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
177109  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
177110  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
177111  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries },
177112  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_RAM_ID,
177113  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
177114  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_ECC_TYPE,
177115  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
177116  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries },
177117  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_RAM_ID,
177118  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_INJECT_TYPE,
177119  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_ECC_TYPE,
177120  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
177121  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries },
177122  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_RAM_ID,
177123  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_INJECT_TYPE,
177124  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_ECC_TYPE,
177125  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
177126  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries },
177127  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_RAM_ID,
177128  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_INJECT_TYPE,
177129  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_ECC_TYPE,
177130  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
177131  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries },
177132  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_RAM_ID,
177133  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_INJECT_TYPE,
177134  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_ECC_TYPE,
177135  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS,
177136  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries },
177137  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
177138  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
177139  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
177140  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
177141  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
177142  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
177143  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
177144  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
177145  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
177146  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
177147  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
177148  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
177149  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
177150  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
177151  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
177152  { SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
177153  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
177154  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
177155  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
177156  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
177157 };
177158 
177163 static const SDL_RAMIdEntry_t SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable[SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS] =
177164 {
177165  { SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
177166  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
177167  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_USB3P0SS_16FFC_USB3P0SS_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
177168  0u,
177169  NULL },
177170 };
177171 
177176 static const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RamIdTable[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS] =
177177 {
177178  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_RAM_ID,
177179  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_INJECT_TYPE,
177180  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_ECC_TYPE,
177181  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177182  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries },
177183  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_STRAM_RAM_ID,
177184  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_STRAM_INJECT_TYPE,
177185  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_STRAM_ECC_TYPE,
177186  0u,
177187  NULL },
177188  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_BUFRAM_ECC_RAM_ID,
177189  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_BUFRAM_ECC_INJECT_TYPE,
177190  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_BUFRAM_ECC_ECC_TYPE,
177191  0u,
177192  NULL },
177193  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_RAM_ID,
177194  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_INJECT_TYPE,
177195  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_ECC_TYPE,
177196  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177197  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries },
177198  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_RAM_ID,
177199  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_INJECT_TYPE,
177200  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_ECC_TYPE,
177201  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177202  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries },
177203  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_STRAM_RAM_ID,
177204  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_STRAM_INJECT_TYPE,
177205  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_STRAM_ECC_TYPE,
177206  0u,
177207  NULL },
177208  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_BUFRAM_RAM_ID,
177209  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_BUFRAM_INJECT_TYPE,
177210  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_BUF_BUFRAM_ECC_TYPE,
177211  0u,
177212  NULL },
177213  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_RAM_ID,
177214  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_INJECT_TYPE,
177215  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_ECC_TYPE,
177216  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177217  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries },
177218  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_RAM_ID,
177219  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
177220  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_ECC_TYPE,
177221  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177222  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries },
177223  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_ECC0_RAM_ID,
177224  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_ECC0_INJECT_TYPE,
177225  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_ECC0_ECC_TYPE,
177226  0u,
177227  NULL },
177228  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_RAM_ID,
177229  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_INJECT_TYPE,
177230  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_ECC_TYPE,
177231  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_MAX_NUM_CHECKERS,
177232  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries },
177233  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_ECC0_RAM_ID,
177234  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_ECC0_INJECT_TYPE,
177235  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_ECC0_ECC_TYPE,
177236  0u,
177237  NULL },
177238  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
177239  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
177240  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
177241  0u,
177242  NULL },
177243  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
177244  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
177245  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
177246  0u,
177247  NULL },
177248  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
177249  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
177250  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
177251  0u,
177252  NULL },
177253  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
177254  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
177255  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
177256  0u,
177257  NULL },
177258  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_RAM_ID,
177259  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_INJECT_TYPE,
177260  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_TABLE_ECC_TYPE,
177261  0u,
177262  NULL },
177263  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID,
177264  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_INJECT_TYPE,
177265  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_TABLE_ECC_TYPE,
177266  0u,
177267  NULL },
177268  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_RAM_ID,
177269  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_INJECT_TYPE,
177270  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_TABLE_ECC_TYPE,
177271  0u,
177272  NULL },
177273  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_RAM_ID,
177274  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_INJECT_TYPE,
177275  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_TABLE_ECC_TYPE,
177276  0u,
177277  NULL },
177278  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177279  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177280  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177281  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177282  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177283  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177284  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177285  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177286  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177287  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177288  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
177289  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
177290  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
177291  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177292  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
177293  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
177294  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
177295  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
177296  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177297  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
177298  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
177299  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
177300  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
177301  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177302  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
177303  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
177304  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
177305  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
177306  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177307  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
177308  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
177309  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
177310  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
177311  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177312  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
177313  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
177314  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
177315  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
177316  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177317  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
177318  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
177319  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
177320  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
177321  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177322  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
177323  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
177324  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
177325  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
177326  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
177327  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
177328  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
177329  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
177330  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
177331  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177332  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
177333  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
177334  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
177335  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
177336  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
177337  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
177338  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
177339  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
177340  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
177341  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177342  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
177343  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
177344  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
177345  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
177346  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
177347  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
177348  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
177349  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
177350  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
177351  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177352  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
177353  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
177354  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
177355  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
177356  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
177357  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
177358  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
177359  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
177360  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
177361  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177362  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
177363  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_RAM_ID,
177364  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_INJECT_TYPE,
177365  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_ECC_TYPE,
177366  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177367  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries },
177368  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_RAM_ID,
177369  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_INJECT_TYPE,
177370  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_ECC_TYPE,
177371  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS,
177372  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries },
177373  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
177374  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
177375  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
177376  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177377  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
177378  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
177379  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
177380  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
177381  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
177382  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
177383  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_RAM_ID,
177384  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_INJECT_TYPE,
177385  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_ECC_TYPE,
177386  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS,
177387  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries },
177388  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_RAM_ID,
177389  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_INJECT_TYPE,
177390  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_ECC_TYPE,
177391  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS,
177392  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries },
177393  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_RAM_ID,
177394  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_INJECT_TYPE,
177395  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_ECC_TYPE,
177396  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS,
177397  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries },
177398  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
177399  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
177400  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
177401  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177402  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
177403  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_RAM_ID,
177404  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_INJECT_TYPE,
177405  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_ECC_TYPE,
177406  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
177407  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries },
177408  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_RAM_ID,
177409  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_INJECT_TYPE,
177410  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_ECC_TYPE,
177411  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
177412  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries },
177413  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_RAM_ID,
177414  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_INJECT_TYPE,
177415  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_ECC_TYPE,
177416  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS,
177417  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries },
177418  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_RAM_ID,
177419  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_INJECT_TYPE,
177420  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_ECC_TYPE,
177421  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS,
177422  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries },
177423  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177424  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177425  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177426  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177427  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177428  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177429  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177430  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177431  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177432  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177433  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_RAM_ID,
177434  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_INJECT_TYPE,
177435  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_ECC_TYPE,
177436  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
177437  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries },
177438  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177439  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177440  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177441  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177442  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177443  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177444  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177445  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177446  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177447  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177448  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177449  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177450  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177451  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177452  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177453  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177454  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177455  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177456  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177457  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177458  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177459  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177460  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177461  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177462  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177463  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177464  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177465  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177466  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177467  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177468  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177469  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177470  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177471  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177472  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177473  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177474  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177475  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177476  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177477  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177478  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177479  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177480  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177481  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177482  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177483  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177484  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177485  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177486  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177487  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177488  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177489  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177490  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177491  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177492  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177493  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177494  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177495  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177496  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177497  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177498  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177499  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177500  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177501  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177502  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177503  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177504  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177505  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177506  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177507  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177508  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
177509  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
177510  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
177511  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
177512  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
177513  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
177514  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
177515  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
177516  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
177517  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
177518  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
177519  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
177520  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
177521  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
177522  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries },
177523  { SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_RAM_ID,
177524  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_INJECT_TYPE,
177525  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_ECC_TYPE,
177526  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS,
177527  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries },
177528 };
177529 
177534 static const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_NUM_RAMS] =
177535 {
177536  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_RAM_ID,
177537  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_INJECT_TYPE,
177538  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_0_SPRAM_ECC_ECC_TYPE,
177539  0u,
177540  NULL },
177541  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_RAM_ID,
177542  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_INJECT_TYPE,
177543  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_1_SPRAM_ECC_ECC_TYPE,
177544  0u,
177545  NULL },
177546  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_RAM_ID,
177547  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_INJECT_TYPE,
177548  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_2_SPRAM_ECC_ECC_TYPE,
177549  0u,
177550  NULL },
177551  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_RAM_ID,
177552  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_INJECT_TYPE,
177553  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_PKT_MEM_3_SPRAM_ECC_ECC_TYPE,
177554  0u,
177555  NULL },
177556  { SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_RAM_ID,
177557  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_INJECT_TYPE,
177558  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_K3_DSS_EDP_MHDPTX_WRAPPER_AIF_MEM_TPRAM_ECC_ECC_TYPE,
177559  0u,
177560  NULL },
177561 };
177562 
177567 static const SDL_RAMIdEntry_t SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RamIdTable[SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS] =
177568 {
177569  { SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_RAM_ID,
177570  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_INJECT_TYPE,
177571  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_ECC_TYPE,
177572  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS,
177573  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries },
177574 };
177575 
177580 static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
177581 {
177582  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
177583  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
177584  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
177585  0u,
177586  NULL },
177587  { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
177588  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
177589  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
177590  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
177591  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
177592 };
177593 
177598 static const SDL_RAMIdEntry_t SDL_PCIE3_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE3_ECC_AGGR_CORE_0_NUM_RAMS] =
177599 {
177600  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
177601  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
177602  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
177603  0u,
177604  NULL },
177605  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_RAM_ID,
177606  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_INJECT_TYPE,
177607  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_PNPFIFO_ECC_TYPE,
177608  0u,
177609  NULL },
177610  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
177611  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
177612  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
177613  0u,
177614  NULL },
177615  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_RAM_ID,
177616  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_INJECT_TYPE,
177617  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_RXCPLFIFO_ECC_TYPE,
177618  0u,
177619  NULL },
177620  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
177621  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
177622  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
177623  0u,
177624  NULL },
177625  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
177626  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
177627  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
177628  0u,
177629  NULL },
177630  { SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_RAM_ID,
177631  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_INJECT_TYPE,
177632  SDL_PCIE3_ECC_AGGR_CORE_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISRODR_ECC_TYPE,
177633  0u,
177634  NULL },
177635 };
177636 
177641 static const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS] =
177642 {
177643  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_RAM_ID,
177644  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_INJECT_TYPE,
177645  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_ECC_TYPE,
177646  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177647  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries },
177648  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PSTATE_RAM_ID,
177649  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PSTATE_INJECT_TYPE,
177650  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PSTATE_ECC_TYPE,
177651  0u,
177652  NULL },
177653  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PCONFIG_RAM_ID,
177654  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PCONFIG_INJECT_TYPE,
177655  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFG_PCONFIG_ECC_TYPE,
177656  0u,
177657  NULL },
177658  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_CF_RAM_ID,
177659  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_CF_INJECT_TYPE,
177660  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_CF_ECC_TYPE,
177661  0u,
177662  NULL },
177663  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_DF_RAM_ID,
177664  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_DF_INJECT_TYPE,
177665  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_DF_ECC_TYPE,
177666  0u,
177667  NULL },
177668  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_PF_RAM_ID,
177669  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_PF_INJECT_TYPE,
177670  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPBUF_PF_ECC_TYPE,
177671  0u,
177672  NULL },
177673  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_SB_RAM_ID,
177674  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_SB_INJECT_TYPE,
177675  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_SB_ECC_TYPE,
177676  0u,
177677  NULL },
177678  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_RAM_ID,
177679  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_INJECT_TYPE,
177680  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCU_ARRAYCNT_CNTR_ECC_TYPE,
177681  0u,
177682  NULL },
177683  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PSTATE_RAM_ID,
177684  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PSTATE_INJECT_TYPE,
177685  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PSTATE_ECC_TYPE,
177686  0u,
177687  NULL },
177688  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PCONFIG_RAM_ID,
177689  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PCONFIG_INJECT_TYPE,
177690  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PCONFIG_ECC_TYPE,
177691  0u,
177692  NULL },
177693  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PQINFO_RAM_ID,
177694  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PQINFO_INJECT_TYPE,
177695  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFG_PQINFO_ECC_TYPE,
177696  0u,
177697  NULL },
177698  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_CF_RAM_ID,
177699  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_CF_INJECT_TYPE,
177700  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_CF_ECC_TYPE,
177701  0u,
177702  NULL },
177703  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_DF_RAM_ID,
177704  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_DF_INJECT_TYPE,
177705  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_DF_ECC_TYPE,
177706  0u,
177707  NULL },
177708  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_PF_RAM_ID,
177709  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_PF_INJECT_TYPE,
177710  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPBUF_PF_ECC_TYPE,
177711  0u,
177712  NULL },
177713  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB0_RAM_ID,
177714  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB0_INJECT_TYPE,
177715  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB0_ECC_TYPE,
177716  0u,
177717  NULL },
177718  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB1_RAM_ID,
177719  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB1_INJECT_TYPE,
177720  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB1_ECC_TYPE,
177721  0u,
177722  NULL },
177723  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB2_RAM_ID,
177724  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB2_INJECT_TYPE,
177725  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_SB2_ECC_TYPE,
177726  0u,
177727  NULL },
177728  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_RAM_ID,
177729  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_INJECT_TYPE,
177730  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPTRCU_ARRAYCNT_CNTR_ECC_TYPE,
177731  0u,
177732  NULL },
177733  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB0_RAM_ID,
177734  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB0_INJECT_TYPE,
177735  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB0_ECC_TYPE,
177736  0u,
177737  NULL },
177738  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB1_RAM_ID,
177739  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB1_INJECT_TYPE,
177740  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB1_ECC_TYPE,
177741  0u,
177742  NULL },
177743  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB2_RAM_ID,
177744  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB2_INJECT_TYPE,
177745  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_SB2_ECC_TYPE,
177746  0u,
177747  NULL },
177748  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_RAM_ID,
177749  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_INJECT_TYPE,
177750  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPTRCU_ARRAYCNT_CNTR_ECC_TYPE,
177751  0u,
177752  NULL },
177753  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB0_RAM_ID,
177754  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB0_INJECT_TYPE,
177755  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB0_ECC_TYPE,
177756  0u,
177757  NULL },
177758  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB1_RAM_ID,
177759  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB1_INJECT_TYPE,
177760  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_SB1_ECC_TYPE,
177761  0u,
177762  NULL },
177763  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_RAM_ID,
177764  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_INJECT_TYPE,
177765  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCU_ARRAYCNT_CNTR_ECC_TYPE,
177766  0u,
177767  NULL },
177768  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TCFG_STATE_RAM_ID,
177769  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TCFG_STATE_INJECT_TYPE,
177770  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TCFG_STATE_ECC_TYPE,
177771  0u,
177772  NULL },
177773  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F0_RAM_ID,
177774  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F0_INJECT_TYPE,
177775  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F0_ECC_TYPE,
177776  0u,
177777  NULL },
177778  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F1_RAM_ID,
177779  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F1_INJECT_TYPE,
177780  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_F1_ECC_TYPE,
177781  0u,
177782  NULL },
177783  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_C0_RAM_ID,
177784  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_C0_INJECT_TYPE,
177785  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TPCFIFO0_C0_ECC_TYPE,
177786  0u,
177787  NULL },
177788  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RFLOWFW_RFFW_RAM_ID,
177789  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RFLOWFW_RFFW_INJECT_TYPE,
177790  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RFLOWFW_RFFW_ECC_TYPE,
177791  0u,
177792  NULL },
177793  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F0_RAM_ID,
177794  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F0_INJECT_TYPE,
177795  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F0_ECC_TYPE,
177796  0u,
177797  NULL },
177798  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F1_RAM_ID,
177799  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F1_INJECT_TYPE,
177800  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_F1_ECC_TYPE,
177801  0u,
177802  NULL },
177803  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C0_RAM_ID,
177804  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C0_INJECT_TYPE,
177805  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C0_ECC_TYPE,
177806  0u,
177807  NULL },
177808  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_WC0_RAM_ID,
177809  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_WC0_INJECT_TYPE,
177810  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_WC0_ECC_TYPE,
177811  0u,
177812  NULL },
177813  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C1_RAM_ID,
177814  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C1_INJECT_TYPE,
177815  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RPCFIFO_C1_ECC_TYPE,
177816  0u,
177817  NULL },
177818  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW0_RAM_ID,
177819  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW0_INJECT_TYPE,
177820  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW0_ECC_TYPE,
177821  0u,
177822  NULL },
177823  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW1_RAM_ID,
177824  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW1_INJECT_TYPE,
177825  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RFLOW1_ECC_TYPE,
177826  0u,
177827  NULL },
177828  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RSTATE_RAM_ID,
177829  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RSTATE_INJECT_TYPE,
177830  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RCFG_RSTATE_ECC_TYPE,
177831  0u,
177832  NULL },
177833  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PROXY_PCONFIG_RAM_ID,
177834  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PROXY_PCONFIG_INJECT_TYPE,
177835  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PROXY_PCONFIG_ECC_TYPE,
177836  0u,
177837  NULL },
177838  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EHANDLER_ECONFIG_RAM_ID,
177839  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EHANDLER_ECONFIG_INJECT_TYPE,
177840  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EHANDLER_ECONFIG_ECC_TYPE,
177841  0u,
177842  NULL },
177843  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST0_RAM_ID,
177844  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST0_INJECT_TYPE,
177845  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST0_ECC_TYPE,
177846  0u,
177847  NULL },
177848  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST1_RAM_ID,
177849  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST1_INJECT_TYPE,
177850  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STST1_ECC_TYPE,
177851  0u,
177852  NULL },
177853  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR0_RAM_ID,
177854  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR0_INJECT_TYPE,
177855  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR0_ECC_TYPE,
177856  0u,
177857  NULL },
177858  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR1_RAM_ID,
177859  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR1_INJECT_TYPE,
177860  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_STATS_STSR1_ECC_TYPE,
177861  0u,
177862  NULL },
177863  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_RAM_ID,
177864  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_INJECT_TYPE,
177865  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_TEVTCU_ARRAYCNT_CNTR_ECC_TYPE,
177866  0u,
177867  NULL },
177868  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_RAM_ID,
177869  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_INJECT_TYPE,
177870  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_REVTCU_ARRAYCNT_CNTR_ECC_TYPE,
177871  0u,
177872  NULL },
177873  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC0_SB_RAM_ID,
177874  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC0_SB_INJECT_TYPE,
177875  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC0_SB_ECC_TYPE,
177876  0u,
177877  NULL },
177878  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC1_SB_RAM_ID,
177879  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC1_SB_INJECT_TYPE,
177880  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC1_SB_ECC_TYPE,
177881  0u,
177882  NULL },
177883  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC2_SB_RAM_ID,
177884  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC2_SB_INJECT_TYPE,
177885  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RDEC2_SB_ECC_TYPE,
177886  0u,
177887  NULL },
177888  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC0_SB_RAM_ID,
177889  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC0_SB_INJECT_TYPE,
177890  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC0_SB_ECC_TYPE,
177891  0u,
177892  NULL },
177893  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC3_SB_RAM_ID,
177894  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC3_SB_INJECT_TYPE,
177895  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_SDEC3_SB_ECC_TYPE,
177896  0u,
177897  NULL },
177898  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_RAM_ID,
177899  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_INJECT_TYPE,
177900  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_IPCFIFO_BUF_ECC_TYPE,
177901  0u,
177902  NULL },
177903  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_TRETID_RAM_ID,
177904  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_TRETID_INJECT_TYPE,
177905  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_PSILIF_TRETID_ECC_TYPE,
177906  0u,
177907  NULL },
177908  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_RAM_ID,
177909  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_INJECT_TYPE,
177910  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_TOCC_CNTR_ECC_TYPE,
177911  0u,
177912  NULL },
177913  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_RAM_ID,
177914  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_INJECT_TYPE,
177915  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_RINGPEND_ROCC_CNTR_ECC_TYPE,
177916  0u,
177917  NULL },
177918  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_RAM_ID,
177919  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_INJECT_TYPE,
177920  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_ECC_TYPE,
177921  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177922  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries },
177923  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_RAM_ID,
177924  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_INJECT_TYPE,
177925  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_ECC_TYPE,
177926  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS,
177927  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries },
177928  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_RAM_ID,
177929  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_INJECT_TYPE,
177930  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_ECC_TYPE,
177931  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS,
177932  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries },
177933  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_RAM_ID,
177934  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_INJECT_TYPE,
177935  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_ECC_TYPE,
177936  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177937  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries },
177938  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_RAM_ID,
177939  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_INJECT_TYPE,
177940  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_ECC_TYPE,
177941  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS,
177942  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries },
177943  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_STRAM_RAM_ID,
177944  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_STRAM_INJECT_TYPE,
177945  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_STRAM_ECC_TYPE,
177946  0u,
177947  NULL },
177948  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_RAM_ID,
177949  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_INJECT_TYPE,
177950  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_ECC_TYPE,
177951  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS,
177952  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries },
177953  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_1536X15_SWW_SR_RAM_ID,
177954  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_1536X15_SWW_SR_INJECT_TYPE,
177955  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_INTMAP_IM_SPRAM_1536X15_SWW_SR_ECC_TYPE,
177956  0u,
177957  NULL },
177958  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_RAM_ID,
177959  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_INJECT_TYPE,
177960  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_STATREG_SR_SPRAM_256X128_SWW_SR_ECC_TYPE,
177961  0u,
177962  NULL },
177963  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_128X32_SWW_SR_RAM_ID,
177964  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_128X32_SWW_SR_INJECT_TYPE,
177965  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_MC_MC_SPRAM_128X32_SWW_SR_ECC_TYPE,
177966  0u,
177967  NULL },
177968  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_256X48_SWW_SR_RAM_ID,
177969  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_256X48_SWW_SR_INJECT_TYPE,
177970  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_GEVICNTR_GC_SPRAM_256X48_SWW_SR_ECC_TYPE,
177971  0u,
177972  NULL },
177973  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_RAM_ID,
177974  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_INJECT_TYPE,
177975  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_ECC_TYPE,
177976  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS,
177977  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries },
177978  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_RAM_ID,
177979  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_INJECT_TYPE,
177980  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_ECC_TYPE,
177981  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS,
177982  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries },
177983  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
177984  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
177985  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
177986  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
177987  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
177988  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
177989  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
177990  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
177991  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
177992  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
177993  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
177994  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
177995  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
177996  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
177997  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
177998  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
177999  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
178000  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
178001  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
178002  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
178003  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
178004  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
178005  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
178006  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
178007  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
178008  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
178009  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
178010  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
178011  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
178012  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries },
178013  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
178014  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
178015  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
178016  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
178017  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries },
178018  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
178019  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
178020  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
178021  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
178022  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
178023  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
178024  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
178025  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
178026  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
178027  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries },
178028  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_RAM_ID,
178029  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
178030  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_ECC_TYPE,
178031  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
178032  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries },
178033  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
178034  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
178035  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
178036  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
178037  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
178038  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
178039  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
178040  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
178041  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
178042  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries },
178043  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_RAM_ID,
178044  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_INJECT_TYPE,
178045  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_ECC_TYPE,
178046  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
178047  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries },
178048  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_RAM_ID,
178049  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_INJECT_TYPE,
178050  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_ECC_TYPE,
178051  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
178052  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries },
178053  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_RAM_ID,
178054  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_INJECT_TYPE,
178055  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_ECC_TYPE,
178056  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
178057  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries },
178058  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_RAM_ID,
178059  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_INJECT_TYPE,
178060  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_ECC_TYPE,
178061  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
178062  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries },
178063  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_RAM_ID,
178064  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_INJECT_TYPE,
178065  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_ECC_TYPE,
178066  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
178067  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries },
178068  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_RAM_ID,
178069  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_INJECT_TYPE,
178070  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_ECC_TYPE,
178071  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
178072  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries },
178073  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_RAM_ID,
178074  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_INJECT_TYPE,
178075  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_ECC_TYPE,
178076  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
178077  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries },
178078  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_RAM_ID,
178079  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_INJECT_TYPE,
178080  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_ECC_TYPE,
178081  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
178082  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries },
178083  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_RAM_ID,
178084  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_INJECT_TYPE,
178085  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_ECC_TYPE,
178086  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
178087  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries },
178088  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_RAM_ID,
178089  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_INJECT_TYPE,
178090  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_ECC_TYPE,
178091  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
178092  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries },
178093  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_RAM_ID,
178094  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_INJECT_TYPE,
178095  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_ECC_TYPE,
178096  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
178097  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries },
178098  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_RAM_ID,
178099  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_INJECT_TYPE,
178100  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_ECC_TYPE,
178101  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS,
178102  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries },
178103  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_RAM_ID,
178104  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
178105  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
178106  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
178107  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries },
178108  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_RAM_ID,
178109  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
178110  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
178111  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
178112  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries },
178113  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_RAM_ID,
178114  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_INJECT_TYPE,
178115  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_ECC_TYPE,
178116  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
178117  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries },
178118  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
178119  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
178120  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
178121  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
178122  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries },
178123  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
178124  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
178125  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
178126  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
178127  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries },
178128  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
178129  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
178130  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
178131  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
178132  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
178133  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
178134  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
178135  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
178136  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
178137  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries },
178138  { SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_RAM_ID,
178139  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_INJECT_TYPE,
178140  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_ECC_TYPE,
178141  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS,
178142  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries },
178143 };
178144 
178149 static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_NUM_RAMS] =
178150 {
178151  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_RAM_ID,
178152  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_INJECT_TYPE,
178153  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_ECC0_ECC_TYPE,
178154  0u,
178155  NULL },
178156  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_RAM_ID,
178157  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
178158  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
178159  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
178160  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries },
178161  { SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_RAM_ID,
178162  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
178163  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
178164  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
178165  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries },
178166 };
178167 
178172 static const SDL_RAMIdEntry_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
178173 {
178174  { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
178175  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
178176  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
178177  0u,
178178  NULL },
178179  { SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
178180  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
178181  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
178182  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
178183  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
178184 };
178185 
178190 static const SDL_RAMIdEntry_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
178191 {
178192  { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
178193  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
178194  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
178195  0u,
178196  NULL },
178197  { SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
178198  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
178199  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
178200  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
178201  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
178202 };
178203 
178208 static const SDL_RAMIdEntry_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
178209 {
178210  { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
178211  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
178212  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
178213  0u,
178214  NULL },
178215  { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
178216  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
178217  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
178218  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
178219  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
178220 };
178221 
178226 static const SDL_RAMIdEntry_t SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RamIdTable[SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_NUM_RAMS] =
178227 {
178228  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_RAM_ID,
178229  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_INJECT_TYPE,
178230  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F0_TPRAM_120X128_SBW_SR_ECC_TYPE,
178231  0u,
178232  NULL },
178233  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_RAM_ID,
178234  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_INJECT_TYPE,
178235  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_TF0_F1_TPRAM_120X128_SBW_SR_ECC_TYPE,
178236  0u,
178237  NULL },
178238  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_RAM_ID,
178239  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_INJECT_TYPE,
178240  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F0_TPRAM_120X144_SBW_SR_ECC_TYPE,
178241  0u,
178242  NULL },
178243  { SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_RAM_ID,
178244  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_INJECT_TYPE,
178245  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_PDMA_J7_MAIN_MCAN_PDMA_CORE_RF0_F1_TPRAM_120X144_SBW_SR_ECC_TYPE,
178246  0u,
178247  NULL },
178248 };
178249 
178254 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_NUM_RAMS] =
178255 {
178256  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178257  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178258  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178259  0u,
178260  NULL },
178261  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178262  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178263  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178264  0u,
178265  NULL },
178266  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178267  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178268  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178269  0u,
178270  NULL },
178271  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178272  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178273  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178274  0u,
178275  NULL },
178276  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
178277  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
178278  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
178279  0u,
178280  NULL },
178281  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
178282  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
178283  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
178284  0u,
178285  NULL },
178286  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178287  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178288  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178289  0u,
178290  NULL },
178291  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178292  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178293  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178294  0u,
178295  NULL },
178296  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178297  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178298  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178299  0u,
178300  NULL },
178301  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178302  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178303  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178304  0u,
178305  NULL },
178306  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178307  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178308  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178309  0u,
178310  NULL },
178311  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178312  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178313  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178314  0u,
178315  NULL },
178316  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
178317  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
178318  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
178319  0u,
178320  NULL },
178321  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
178322  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
178323  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
178324  0u,
178325  NULL },
178326  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
178327  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
178328  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
178329  0u,
178330  NULL },
178331  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
178332  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
178333  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
178334  0u,
178335  NULL },
178336  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178337  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178338  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178339  0u,
178340  NULL },
178341  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178342  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178343  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178344  0u,
178345  NULL },
178346  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178347  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178348  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178349  0u,
178350  NULL },
178351  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178352  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178353  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178354  0u,
178355  NULL },
178356  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178357  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178358  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178359  0u,
178360  NULL },
178361  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178362  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178363  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178364  0u,
178365  NULL },
178366  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178367  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178368  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178369  0u,
178370  NULL },
178371  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178372  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178373  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_CPU0_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178374  0u,
178375  NULL },
178376  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_RAM_ID,
178377  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_INJECT_TYPE,
178378  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_ECC_TYPE,
178379  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_MAX_NUM_CHECKERS,
178380  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_groupEntries },
178381 };
178382 
178387 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_NUM_RAMS] =
178388 {
178389  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178390  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178391  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178392  0u,
178393  NULL },
178394  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178395  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178396  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178397  0u,
178398  NULL },
178399  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178400  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178401  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178402  0u,
178403  NULL },
178404  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178405  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178406  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178407  0u,
178408  NULL },
178409  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
178410  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
178411  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
178412  0u,
178413  NULL },
178414  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
178415  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
178416  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_DATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
178417  0u,
178418  NULL },
178419  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178420  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178421  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178422  0u,
178423  NULL },
178424  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178425  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178426  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_IF_TAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178427  0u,
178428  NULL },
178429  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178430  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178431  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178432  0u,
178433  NULL },
178434  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178435  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178436  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178437  0u,
178438  NULL },
178439  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178440  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178441  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178442  0u,
178443  NULL },
178444  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178445  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178446  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178447  0u,
178448  NULL },
178449  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_RAM_ID,
178450  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_INJECT_TYPE,
178451  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK4_ECC_SVBUS_ECC_TYPE,
178452  0u,
178453  NULL },
178454  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_RAM_ID,
178455  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_INJECT_TYPE,
178456  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK5_ECC_SVBUS_ECC_TYPE,
178457  0u,
178458  NULL },
178459  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_RAM_ID,
178460  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_INJECT_TYPE,
178461  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK6_ECC_SVBUS_ECC_TYPE,
178462  0u,
178463  NULL },
178464  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_RAM_ID,
178465  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_INJECT_TYPE,
178466  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_DATA_SPRAM_BANK7_ECC_SVBUS_ECC_TYPE,
178467  0u,
178468  NULL },
178469  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178470  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178471  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178472  0u,
178473  NULL },
178474  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178475  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178476  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178477  0u,
178478  NULL },
178479  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178480  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178481  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178482  0u,
178483  NULL },
178484  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178485  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178486  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_LS_TAG_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178487  0u,
178488  NULL },
178489  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_RAM_ID,
178490  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_INJECT_TYPE,
178491  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK0_ECC_SVBUS_ECC_TYPE,
178492  0u,
178493  NULL },
178494  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_RAM_ID,
178495  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_INJECT_TYPE,
178496  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK1_ECC_SVBUS_ECC_TYPE,
178497  0u,
178498  NULL },
178499  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_RAM_ID,
178500  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_INJECT_TYPE,
178501  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK2_ECC_SVBUS_ECC_TYPE,
178502  0u,
178503  NULL },
178504  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_RAM_ID,
178505  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_INJECT_TYPE,
178506  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_CPU1_L2_TLB_SPRAM_BANK3_ECC_SVBUS_ECC_TYPE,
178507  0u,
178508  NULL },
178509  { SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_RAM_ID,
178510  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_INJECT_TYPE,
178511  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_ECC_TYPE,
178512  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_MAX_NUM_CHECKERS,
178513  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_groupEntries },
178514 };
178515 
178520 static const SDL_RAMIdEntry_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
178521 {
178522  { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
178523  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
178524  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
178525  0u,
178526  NULL },
178527  { SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
178528  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
178529  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
178530  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
178531  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
178532 };
178533 
178538 static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
178539 {
178540  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
178541  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
178542  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
178543  0u,
178544  NULL },
178545  { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
178546  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
178547  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
178548  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
178549  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
178550 };
178551 
178556 static const SDL_RAMIdEntry_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_NUM_RAMS] =
178557 {
178558  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_RAM_ID,
178559  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_INJECT_TYPE,
178560  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_ECC0_ECC_TYPE,
178561  0u,
178562  NULL },
178563  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_RAM_ID,
178564  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_INJECT_TYPE,
178565  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_ECC_TYPE,
178566  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS,
178567  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries },
178568  { SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_RAM_ID,
178569  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
178570  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_ECC_TYPE,
178571  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
178572  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries },
178573 };
178574 
178579 static const SDL_RAMIdEntry_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
178580 {
178581  { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
178582  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
178583  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
178584  0u,
178585  NULL },
178586  { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
178587  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
178588  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
178589  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
178590  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
178591 };
178592 
178597 static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS] =
178598 {
178599  { SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
178600  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
178601  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
178602  0u,
178603  NULL },
178604 };
178605 
178610 static const SDL_RAMIdEntry_t SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS] =
178611 {
178612  { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
178613  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
178614  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
178615  0u,
178616  NULL },
178617  { SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
178618  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
178619  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
178620  0u,
178621  NULL },
178622 };
178623 
178628 static const SDL_RAMIdEntry_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_NUM_RAMS] =
178629 {
178630  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_RAM_ID,
178631  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_INJECT_TYPE,
178632  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_ECC_TYPE,
178633  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS,
178634  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries },
178635  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
178636  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
178637  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
178638  0u,
178639  NULL },
178640  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
178641  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
178642  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
178643  0u,
178644  NULL },
178645  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
178646  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
178647  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
178648  0u,
178649  NULL },
178650  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_RAM_ID,
178651  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_INJECT_TYPE,
178652  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXIMFIFO_ECC_TYPE,
178653  0u,
178654  NULL },
178655  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_RAM_ID,
178656  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_INJECT_TYPE,
178657  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_AXISFIFO_ECC_TYPE,
178658  0u,
178659  NULL },
178660  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_RAM_ID,
178661  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_INJECT_TYPE,
178662  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_RAMS_HP_DIBRAM_ECC_TYPE,
178663  0u,
178664  NULL },
178665  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
178666  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
178667  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_HP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
178668  0u,
178669  NULL },
178670  { SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
178671  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
178672  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_AXI2VBUSM_MST_LP_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
178673  0u,
178674  NULL },
178675 };
178676 
178681 static const SDL_RAMIdEntry_t SDL_I3C0_I3C_P_ECC_AGGR_RamIdTable[SDL_I3C0_I3C_P_ECC_AGGR_NUM_RAMS] =
178682 {
178683  { SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_RAM_ID,
178684  SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_INJECT_TYPE,
178685  SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_ECC_TYPE,
178686  SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS,
178687  SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries },
178688 };
178689 
178694 static const SDL_RAMIdEntry_t SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS] =
178695 {
178696  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
178697  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
178698  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
178699  0u,
178700  NULL },
178701  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
178702  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
178703  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
178704  0u,
178705  NULL },
178706  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
178707  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
178708  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
178709  0u,
178710  NULL },
178711  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
178712  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
178713  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
178714  0u,
178715  NULL },
178716  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
178717  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
178718  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
178719  0u,
178720  NULL },
178721  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID,
178722  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_INJECT_TYPE,
178723  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ECC_TYPE,
178724  0u,
178725  NULL },
178726  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID,
178727  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_INJECT_TYPE,
178728  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ECC_TYPE,
178729  0u,
178730  NULL },
178731  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID,
178732  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_INJECT_TYPE,
178733  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ECC_TYPE,
178734  0u,
178735  NULL },
178736  { SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID,
178737  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_INJECT_TYPE,
178738  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ECC_TYPE,
178739  0u,
178740  NULL },
178741 };
178742 
178747 static const SDL_RAMIdEntry_t SDL_CBASS_ECC_AGGR0_RamIdTable[SDL_CBASS_ECC_AGGR0_NUM_RAMS] =
178748 {
178749  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
178750  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
178751  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
178752  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
178753  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
178754  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
178755  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
178756  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
178757  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
178758  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
178759  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
178760  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
178761  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
178762  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
178763  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_groupEntries },
178764  { SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_RAM_ID,
178765  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
178766  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
178767  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
178768  SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_groupEntries },
178769  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
178770  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
178771  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
178772  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
178773  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries },
178774  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_RAM_ID,
178775  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_INJECT_TYPE,
178776  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_ECC_TYPE,
178777  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS,
178778  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_groupEntries },
178779  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_RAM_ID,
178780  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_INJECT_TYPE,
178781  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_ECC_TYPE,
178782  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS,
178783  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_groupEntries },
178784  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_RAM_ID,
178785  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_INJECT_TYPE,
178786  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_ECC_TYPE,
178787  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS,
178788  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_groupEntries },
178789  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_RAM_ID,
178790  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_INJECT_TYPE,
178791  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_ECC_TYPE,
178792  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS,
178793  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_groupEntries },
178794  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_RAM_ID,
178795  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_INJECT_TYPE,
178796  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_ECC_TYPE,
178797  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS,
178798  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_groupEntries },
178799  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
178800  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
178801  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
178802  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
178803  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries },
178804  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
178805  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
178806  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
178807  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
178808  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries },
178809  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_RAM_ID,
178810  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
178811  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_ECC_TYPE,
178812  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
178813  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries },
178814  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_RAM_ID,
178815  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_INJECT_TYPE,
178816  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_ECC_TYPE,
178817  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
178818  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries },
178819  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_RAM_ID,
178820  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_INJECT_TYPE,
178821  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_ECC_TYPE,
178822  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
178823  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries },
178824  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_RAM_ID,
178825  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_INJECT_TYPE,
178826  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_ECC_TYPE,
178827  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
178828  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries },
178829  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_RAM_ID,
178830  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_INJECT_TYPE,
178831  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_ECC_TYPE,
178832  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS,
178833  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries },
178834  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_RAM_ID,
178835  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_INJECT_TYPE,
178836  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_ECC_TYPE,
178837  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS,
178838  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_groupEntries },
178839  { SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_RAM_ID,
178840  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_INJECT_TYPE,
178841  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_ECC_TYPE,
178842  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS,
178843  SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_groupEntries },
178844  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
178845  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
178846  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
178847  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
178848  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
178849  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
178850  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
178851  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
178852  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
178853  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
178854  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
178855  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
178856  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
178857  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
178858  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
178859  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
178860  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
178861  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
178862  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
178863  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
178864  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
178865  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
178866  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
178867  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
178868  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries },
178869  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_RAM_ID,
178870  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_INJECT_TYPE,
178871  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ECC_TYPE,
178872  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
178873  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries },
178874  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_RAM_ID,
178875  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_INJECT_TYPE,
178876  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_ECC_TYPE,
178877  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
178878  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries },
178879  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_RAM_ID,
178880  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_INJECT_TYPE,
178881  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_ECC_TYPE,
178882  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
178883  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries },
178884  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_RAM_ID,
178885  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_INJECT_TYPE,
178886  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_ECC_TYPE,
178887  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
178888  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries },
178889  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
178890  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
178891  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
178892  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
178893  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_groupEntries },
178894  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
178895  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
178896  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
178897  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
178898  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_groupEntries },
178899  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
178900  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
178901  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
178902  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
178903  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_groupEntries },
178904  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_RAM_ID,
178905  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
178906  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_ECC_TYPE,
178907  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
178908  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_groupEntries },
178909  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_RAM_ID,
178910  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_INJECT_TYPE,
178911  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_ECC_TYPE,
178912  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
178913  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_groupEntries },
178914  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_RAM_ID,
178915  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_INJECT_TYPE,
178916  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_ECC_TYPE,
178917  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
178918  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_groupEntries },
178919  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_RAM_ID,
178920  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_INJECT_TYPE,
178921  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_ECC_TYPE,
178922  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
178923  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_groupEntries },
178924  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_RAM_ID,
178925  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
178926  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
178927  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
178928  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_groupEntries },
178929  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
178930  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
178931  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
178932  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
178933  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
178934  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
178935  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
178936  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
178937  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
178938  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
178939  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
178940  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
178941  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
178942  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
178943  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
178944  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_RAM_ID,
178945  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_INJECT_TYPE,
178946  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_ECC_TYPE,
178947  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
178948  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_groupEntries },
178949  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
178950  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
178951  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
178952  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
178953  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
178954  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_RAM_ID,
178955  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_INJECT_TYPE,
178956  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_ECC_TYPE,
178957  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
178958  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries },
178959  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_RAM_ID,
178960  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_INJECT_TYPE,
178961  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_ECC_TYPE,
178962  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS,
178963  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries },
178964  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_RAM_ID,
178965  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_INJECT_TYPE,
178966  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_ECC_TYPE,
178967  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS,
178968  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries },
178969  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_RAM_ID,
178970  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_INJECT_TYPE,
178971  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_ECC_TYPE,
178972  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS,
178973  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_groupEntries },
178974  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_RAM_ID,
178975  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_INJECT_TYPE,
178976  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_ECC_TYPE,
178977  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS,
178978  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_groupEntries },
178979  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_RAM_ID,
178980  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_INJECT_TYPE,
178981  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_ECC_TYPE,
178982  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS,
178983  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_groupEntries },
178984  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_RAM_ID,
178985  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_INJECT_TYPE,
178986  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_ECC_TYPE,
178987  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS,
178988  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_groupEntries },
178989  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_RAM_ID,
178990  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_INJECT_TYPE,
178991  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_ECC_TYPE,
178992  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS,
178993  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_groupEntries },
178994  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_RAM_ID,
178995  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_INJECT_TYPE,
178996  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_ECC_TYPE,
178997  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS,
178998  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_groupEntries },
178999  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_RAM_ID,
179000  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_INJECT_TYPE,
179001  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_ECC_TYPE,
179002  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS,
179003  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_groupEntries },
179004  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_RAM_ID,
179005  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_INJECT_TYPE,
179006  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_ECC_TYPE,
179007  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS,
179008  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_groupEntries },
179009  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_RAM_ID,
179010  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_INJECT_TYPE,
179011  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_ECC_TYPE,
179012  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS,
179013  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_groupEntries },
179014  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_RAM_ID,
179015  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_INJECT_TYPE,
179016  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_ECC_TYPE,
179017  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
179018  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries },
179019  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_RAM_ID,
179020  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_INJECT_TYPE,
179021  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_ECC_TYPE,
179022  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
179023  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries },
179024  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_RAM_ID,
179025  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_INJECT_TYPE,
179026  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_ECC_TYPE,
179027  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
179028  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries },
179029  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_RAM_ID,
179030  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_INJECT_TYPE,
179031  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_ECC_TYPE,
179032  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
179033  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries },
179034  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_RAM_ID,
179035  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_INJECT_TYPE,
179036  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_ECC_TYPE,
179037  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
179038  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries },
179039  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_RAM_ID,
179040  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_INJECT_TYPE,
179041  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_ECC_TYPE,
179042  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
179043  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries },
179044  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_RAM_ID,
179045  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_INJECT_TYPE,
179046  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_ECC_TYPE,
179047  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS,
179048  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries },
179049  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_RAM_ID,
179050  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_INJECT_TYPE,
179051  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_ECC_TYPE,
179052  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS,
179053  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries },
179054  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_RAM_ID,
179055  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_INJECT_TYPE,
179056  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_ECC_TYPE,
179057  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS,
179058  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries },
179059  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
179060  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
179061  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
179062  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179063  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
179064  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179065  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179066  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179067  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179068  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
179069  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179070  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179071  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179072  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179073  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179074  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_RAM_ID,
179075  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_INJECT_TYPE,
179076  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_ECC_TYPE,
179077  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_MAX_NUM_CHECKERS,
179078  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_groupEntries },
179079  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_RAM_ID,
179080  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_INJECT_TYPE,
179081  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_ECC_TYPE,
179082  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_MAX_NUM_CHECKERS,
179083  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_groupEntries },
179084  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_RAM_ID,
179085  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_INJECT_TYPE,
179086  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_ECC_TYPE,
179087  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_MAX_NUM_CHECKERS,
179088  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_groupEntries },
179089  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_RAM_ID,
179090  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_INJECT_TYPE,
179091  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_ECC_TYPE,
179092  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_MAX_NUM_CHECKERS,
179093  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_groupEntries },
179094  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_RAM_ID,
179095  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_INJECT_TYPE,
179096  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_ECC_TYPE,
179097  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_MAX_NUM_CHECKERS,
179098  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_groupEntries },
179099  { SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_RAM_ID,
179100  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
179101  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_ECC_TYPE,
179102  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
179103  SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_groupEntries },
179104  { SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_RAM_ID,
179105  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
179106  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_ECC_TYPE,
179107  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
179108  SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_groupEntries },
179109 };
179110 
179115 static const SDL_RAMIdEntry_t SDL_MAIN_RC_ECC_AGGR0_RamIdTable[SDL_MAIN_RC_ECC_AGGR0_NUM_RAMS] =
179116 {
179117  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179118  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179119  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179120  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179121  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179122  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179123  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179124  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179125  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179126  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179127  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179128  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179129  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179130  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179131  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179132  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179133  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179134  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179135  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179136  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179137  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179138  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179139  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179140  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179141  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179142  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179143  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179144  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179145  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179146  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179147  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179148  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179149  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179150  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179151  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179152  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179153  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179154  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179155  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179156  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179157  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179158  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179159  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179160  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179161  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179162  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179163  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179164  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179165  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179166  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179167  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179168  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179169  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179170  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179171  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179172  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179173  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179174  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179175  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179176  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179177  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179178  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179179  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179180  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179181  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179182  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179183  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179184  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179185  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179186  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179187  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179188  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179189  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179190  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179191  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179192  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179193  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179194  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179195  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179196  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179197  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179198  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179199  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179200  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179201  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179202  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179203  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179204  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179205  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179206  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179207  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179208  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179209  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179210  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179211  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179212  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179213  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179214  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179215  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179216  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179217  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179218  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179219  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179220  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179221  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179222  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179223  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179224  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179225  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179226  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179227  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179228  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179229  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179230  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179231  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179232  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179233  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179234  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179235  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179236  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179237  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179238  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179239  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179240  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179241  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179242  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179243  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179244  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179245  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179246  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179247  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179248  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179249  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179250  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179251  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179252  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179253  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179254  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179255  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179256  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179257  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179258  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179259  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179260  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179261  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179262  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179263  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179264  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179265  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179266  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179267  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179268  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179269  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179270  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179271  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179272  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179273  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179274  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179275  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179276  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179277  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179278  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179279  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179280  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179281  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179282  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179283  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179284  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179285  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179286  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179287  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179288  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179289  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179290  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179291  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179292  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179293  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179294  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179295  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179296  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179297  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179298  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179299  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179300  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179301  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179302  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179303  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179304  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179305  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179306  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179307  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179308  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179309  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179310  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179311  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179312  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179313  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179314  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179315  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179316  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179317  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179318  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179319  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179320  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179321  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179322  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179323  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179324  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179325  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179326  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179327  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
179328  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
179329  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
179330  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179331  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
179332  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179333  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179334  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179335  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179336  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179337  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179338  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179339  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179340  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179341  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179342  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179343  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179344  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179345  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179346  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries },
179347  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179348  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179349  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179350  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179351  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179352  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179353  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179354  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179355  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179356  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179357  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179358  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179359  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179360  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179361  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179362  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179363  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179364  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179365  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179366  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179367  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
179368  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
179369  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
179370  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
179371  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_groupEntries },
179372  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
179373  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
179374  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
179375  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
179376  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_groupEntries },
179377  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
179378  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
179379  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
179380  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
179381  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_groupEntries },
179382  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_RAM_ID,
179383  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
179384  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_ECC_TYPE,
179385  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
179386  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_groupEntries },
179387  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
179388  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
179389  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
179390  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
179391  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_groupEntries },
179392  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
179393  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
179394  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
179395  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
179396  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_groupEntries },
179397  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
179398  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
179399  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
179400  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
179401  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_groupEntries },
179402  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_RAM_ID,
179403  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
179404  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_ECC_TYPE,
179405  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
179406  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_groupEntries },
179407  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
179408  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
179409  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
179410  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
179411  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_groupEntries },
179412  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
179413  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
179414  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
179415  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
179416  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_groupEntries },
179417  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
179418  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
179419  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
179420  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179421  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
179422  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179423  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179424  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179425  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179426  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179427  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179428  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179429  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179430  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179431  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
179432  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
179433  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
179434  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
179435  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179436  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
179437  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
179438  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
179439  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
179440  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179441  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
179442  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_RAM_ID,
179443  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_INJECT_TYPE,
179444  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_ECC_TYPE,
179445  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_MAX_NUM_CHECKERS,
179446  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_groupEntries },
179447  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_RAM_ID,
179448  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_INJECT_TYPE,
179449  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_ECC_TYPE,
179450  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_MAX_NUM_CHECKERS,
179451  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_groupEntries },
179452  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_RAM_ID,
179453  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_INJECT_TYPE,
179454  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_ECC_TYPE,
179455  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_MAX_NUM_CHECKERS,
179456  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_groupEntries },
179457  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_RAM_ID,
179458  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_INJECT_TYPE,
179459  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_ECC_TYPE,
179460  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_MAX_NUM_CHECKERS,
179461  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_groupEntries },
179462  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_RAM_ID,
179463  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179464  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_ECC_TYPE,
179465  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179466  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries },
179467  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_RAM_ID,
179468  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_INJECT_TYPE,
179469  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_ECC_TYPE,
179470  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179471  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries },
179472  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_RAM_ID,
179473  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179474  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_ECC_TYPE,
179475  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179476  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries },
179477  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_RAM_ID,
179478  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_INJECT_TYPE,
179479  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_ECC_TYPE,
179480  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179481  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries },
179482  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_RAM_ID,
179483  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179484  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_ECC_TYPE,
179485  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179486  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries },
179487  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_RAM_ID,
179488  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_INJECT_TYPE,
179489  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_ECC_TYPE,
179490  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179491  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries },
179492  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_RAM_ID,
179493  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179494  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_ECC_TYPE,
179495  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179496  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries },
179497  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_RAM_ID,
179498  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_INJECT_TYPE,
179499  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_ECC_TYPE,
179500  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179501  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries },
179502  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179503  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179504  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179505  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179506  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179507  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179508  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179509  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179510  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179511  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries },
179512  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179513  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179514  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179515  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179516  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179517  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179518  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179519  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179520  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179521  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries },
179522  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_RAM_ID,
179523  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_INJECT_TYPE,
179524  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_ECC_TYPE,
179525  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179526  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries },
179527  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_RAM_ID,
179528  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
179529  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
179530  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179531  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries },
179532  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_RAM_ID,
179533  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_INJECT_TYPE,
179534  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_ECC_TYPE,
179535  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179536  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries },
179537  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_RAM_ID,
179538  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_INJECT_TYPE,
179539  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_ECC_TYPE,
179540  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179541  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_groupEntries },
179542  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_RAM_ID,
179543  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_INJECT_TYPE,
179544  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_ECC_TYPE,
179545  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179546  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_groupEntries },
179547  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
179548  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179549  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
179550  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179551  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries },
179552  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_RAM_ID,
179553  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
179554  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
179555  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179556  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries },
179557  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179558  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179559  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179560  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179561  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179562  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179563  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179564  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179565  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179566  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
179567  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
179568  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
179569  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
179570  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
179571  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
179572  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179573  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179574  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179575  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179576  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179577  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179578  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179579  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179580  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179581  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
179582  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
179583  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
179584  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
179585  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
179586  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
179587  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
179588  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
179589  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
179590  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179591  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
179592  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
179593  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
179594  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
179595  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179596  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
179597  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
179598  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179599  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
179600  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179601  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
179602  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_RAM_ID,
179603  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_INJECT_TYPE,
179604  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_ECC_TYPE,
179605  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS,
179606  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries },
179607  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_RAM_ID,
179608  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_INJECT_TYPE,
179609  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_ECC_TYPE,
179610  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS,
179611  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries },
179612  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_RAM_ID,
179613  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_INJECT_TYPE,
179614  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_ECC_TYPE,
179615  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS,
179616  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries },
179617  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_RAM_ID,
179618  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_INJECT_TYPE,
179619  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_ECC_TYPE,
179620  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS,
179621  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries },
179622  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_RAM_ID,
179623  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_INJECT_TYPE,
179624  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_ECC_TYPE,
179625  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS,
179626  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries },
179627  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_RAM_ID,
179628  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_INJECT_TYPE,
179629  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_ECC_TYPE,
179630  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS,
179631  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries },
179632  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_RAM_ID,
179633  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_INJECT_TYPE,
179634  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_ECC_TYPE,
179635  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS,
179636  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries },
179637  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_RAM_ID,
179638  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_INJECT_TYPE,
179639  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_ECC_TYPE,
179640  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS,
179641  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries },
179642  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_RAM_ID,
179643  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_INJECT_TYPE,
179644  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_ECC_TYPE,
179645  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS,
179646  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries },
179647  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_RAM_ID,
179648  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_INJECT_TYPE,
179649  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_ECC_TYPE,
179650  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS,
179651  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries },
179652  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_RAM_ID,
179653  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_INJECT_TYPE,
179654  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_ECC_TYPE,
179655  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS,
179656  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries },
179657  { SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_RAM_ID,
179658  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_INJECT_TYPE,
179659  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_ECC_TYPE,
179660  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS,
179661  SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries },
179662  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
179663  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
179664  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
179665  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
179666  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
179667  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
179668  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
179669  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
179670  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
179671  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
179672  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_RAM_ID,
179673  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179674  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_ECC_TYPE,
179675  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179676  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries },
179677  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_RAM_ID,
179678  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_INJECT_TYPE,
179679  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_ECC_TYPE,
179680  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179681  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries },
179682  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
179683  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
179684  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
179685  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179686  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
179687  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_RAM_ID,
179688  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_INJECT_TYPE,
179689  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_ECC_TYPE,
179690  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179691  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries },
179692  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
179693  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
179694  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
179695  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
179696  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
179697  { SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_RAM_ID,
179698  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_INJECT_TYPE,
179699  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_ECC_TYPE,
179700  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS,
179701  SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries },
179702  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_RAM_ID,
179703  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_INJECT_TYPE,
179704  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_ECC_TYPE,
179705  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS,
179706  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries },
179707  { SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_RAM_ID,
179708  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_INJECT_TYPE,
179709  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_ECC_TYPE,
179710  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS,
179711  SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries },
179712  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
179713  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179714  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
179715  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179716  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries },
179717  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_RAM_ID,
179718  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
179719  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
179720  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179721  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries },
179722  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
179723  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179724  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
179725  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179726  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries },
179727  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
179728  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
179729  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
179730  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179731  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
179732  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
179733  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
179734  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
179735  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
179736  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries },
179737  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_RAM_ID,
179738  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
179739  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
179740  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
179741  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries },
179742  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_RAM_ID,
179743  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_INJECT_TYPE,
179744  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_ECC_TYPE,
179745  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179746  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_groupEntries },
179747  { SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
179748  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
179749  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
179750  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179751  SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
179752  { SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_RAM_ID,
179753  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_INJECT_TYPE,
179754  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_ECC_TYPE,
179755  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179756  SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries },
179757  { SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_RAM_ID,
179758  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_INJECT_TYPE,
179759  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_ECC_TYPE,
179760  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179761  SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_groupEntries },
179762  { SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_RAM_ID,
179763  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_INJECT_TYPE,
179764  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_ECC_TYPE,
179765  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179766  SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries },
179767  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
179768  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
179769  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
179770  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
179771  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
179772  { SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_RAM_ID,
179773  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_INJECT_TYPE,
179774  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_ECC_TYPE,
179775  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
179776  SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries },
179777  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_RAM_ID,
179778  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_INJECT_TYPE,
179779  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_ECC_TYPE,
179780  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
179781  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries },
179782  { SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_RAM_ID,
179783  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
179784  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_ECC_TYPE,
179785  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
179786  SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries },
179787 };
179788 
179793 static const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_NUM_RAMS] =
179794 {
179795  { SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_RAM_ID,
179796  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_INJECT_TYPE,
179797  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_ECC_TYPE,
179798  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS,
179799  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries },
179800 };
179801 
179806 static const SDL_RAMIdEntry_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RamIdTable[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_NUM_RAMS] =
179807 {
179808  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_RAM_ID,
179809  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_INJECT_TYPE,
179810  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_ECC_TYPE,
179811  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_MAX_NUM_CHECKERS,
179812  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries },
179813  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_RAM_ID,
179814  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_INJECT_TYPE,
179815  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_ECC_TYPE,
179816  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS,
179817  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries },
179818  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_RAM_ID,
179819  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_INJECT_TYPE,
179820  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_ECC_TYPE,
179821  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_MAX_NUM_CHECKERS,
179822  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries },
179823  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_RAM_ID,
179824  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_INJECT_TYPE,
179825  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_ECC_TYPE,
179826  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS,
179827  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries },
179828  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_RAM_ID,
179829  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_INJECT_TYPE,
179830  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_ECC_TYPE,
179831  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS,
179832  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries },
179833  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_RAM_ID,
179834  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_INJECT_TYPE,
179835  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_ECC_TYPE,
179836  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_MAX_NUM_CHECKERS,
179837  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries },
179838  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_RAM_ID,
179839  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_INJECT_TYPE,
179840  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_ECC_TYPE,
179841  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_MAX_NUM_CHECKERS,
179842  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries },
179843  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_RAM_ID,
179844  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_INJECT_TYPE,
179845  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_ECC_TYPE,
179846  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS,
179847  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_groupEntries },
179848  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_RAM_ID,
179849  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_INJECT_TYPE,
179850  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_ECC_TYPE,
179851  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_MAX_NUM_CHECKERS,
179852  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries },
179853  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_RAM_ID,
179854  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_INJECT_TYPE,
179855  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_ECC_TYPE,
179856  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS,
179857  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_groupEntries },
179858  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_RAM_ID,
179859  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_INJECT_TYPE,
179860  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_ECC_TYPE,
179861  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS,
179862  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries },
179863  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_RAM_ID,
179864  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_INJECT_TYPE,
179865  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_ECC_TYPE,
179866  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_MAX_NUM_CHECKERS,
179867  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries },
179868  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_RAM_ID,
179869  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_INJECT_TYPE,
179870  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_ECC_TYPE,
179871  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_MAX_NUM_CHECKERS,
179872  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries },
179873  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_RAM_ID,
179874  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_INJECT_TYPE,
179875  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_ECC_TYPE,
179876  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_MAX_NUM_CHECKERS,
179877  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries },
179878  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_RAM_ID,
179879  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_INJECT_TYPE,
179880  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_ECC_TYPE,
179881  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_MAX_NUM_CHECKERS,
179882  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries },
179883  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_RAM_ID,
179884  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_INJECT_TYPE,
179885  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_ECC_TYPE,
179886  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_MAX_NUM_CHECKERS,
179887  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries },
179888  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_RAM_ID,
179889  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_INJECT_TYPE,
179890  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_ECC_TYPE,
179891  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_MAX_NUM_CHECKERS,
179892  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries },
179893  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_RAM_ID,
179894  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_INJECT_TYPE,
179895  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_ECC_TYPE,
179896  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS,
179897  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries },
179898  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_RAM_ID,
179899  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_INJECT_TYPE,
179900  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_ECC_TYPE,
179901  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_MAX_NUM_CHECKERS,
179902  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries },
179903  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_RAM_ID,
179904  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_INJECT_TYPE,
179905  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_ECC_TYPE,
179906  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_MAX_NUM_CHECKERS,
179907  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries },
179908  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_RAM_ID,
179909  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_INJECT_TYPE,
179910  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_ECC_TYPE,
179911  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS,
179912  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries },
179913  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_RAM_ID,
179914  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_INJECT_TYPE,
179915  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_ECC_TYPE,
179916  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS,
179917  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries },
179918  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_RAM_ID,
179919  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_INJECT_TYPE,
179920  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_ECC_TYPE,
179921  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS,
179922  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries },
179923  { SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_RAM_ID,
179924  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
179925  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_ECC_TYPE,
179926  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
179927  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries },
179928 };
179929 
179934 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_NUM_RAMS] =
179935 {
179936  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_RAM_ID,
179937  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_INJECT_TYPE,
179938  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_ECC_TYPE,
179939  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS,
179940  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries },
179941  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
179942  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
179943  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
179944  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
179945  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
179946  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
179947  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
179948  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
179949  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
179950  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
179951  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_RAM_ID,
179952  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_INJECT_TYPE,
179953  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_ECC_TYPE,
179954  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
179955  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_groupEntries },
179956  { SDL_ECC_RAMID_INVALID,
179957  0u,
179958  0u,
179959  0u,
179960  NULL },
179961  { SDL_ECC_RAMID_INVALID,
179962  0u,
179963  0u,
179964  0u,
179965  NULL },
179966  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_RAM_ID,
179967  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_INJECT_TYPE,
179968  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_ECC_TYPE,
179969  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_MAX_NUM_CHECKERS,
179970  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_groupEntries },
179971  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_RAM_ID,
179972  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_INJECT_TYPE,
179973  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_ECC_TYPE,
179974  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_MAX_NUM_CHECKERS,
179975  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_groupEntries },
179976  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_RAM_ID,
179977  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_INJECT_TYPE,
179978  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_ECC_TYPE,
179979  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_MAX_NUM_CHECKERS,
179980  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_groupEntries },
179981  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_RAM_ID,
179982  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_INJECT_TYPE,
179983  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_ECC_TYPE,
179984  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_MAX_NUM_CHECKERS,
179985  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_groupEntries },
179986  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_RAM_ID,
179987  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_INJECT_TYPE,
179988  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_ECC_TYPE,
179989  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_MAX_NUM_CHECKERS,
179990  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_groupEntries },
179991  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_RAM_ID,
179992  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_INJECT_TYPE,
179993  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_ECC_TYPE,
179994  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_MAX_NUM_CHECKERS,
179995  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_groupEntries },
179996  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_RAM_ID,
179997  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_INJECT_TYPE,
179998  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_ECC_TYPE,
179999  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_MAX_NUM_CHECKERS,
180000  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_groupEntries },
180001  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_RAM_ID,
180002  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_INJECT_TYPE,
180003  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_ECC_TYPE,
180004  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_MAX_NUM_CHECKERS,
180005  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_groupEntries },
180006  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_RAM_ID,
180007  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_INJECT_TYPE,
180008  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_ECC_TYPE,
180009  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_MAX_NUM_CHECKERS,
180010  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_groupEntries },
180011  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_RAM_ID,
180012  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_INJECT_TYPE,
180013  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_ECC_TYPE,
180014  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_MAX_NUM_CHECKERS,
180015  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_groupEntries },
180016  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_RAM_ID,
180017  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_INJECT_TYPE,
180018  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_ECC_TYPE,
180019  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_MAX_NUM_CHECKERS,
180020  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_groupEntries },
180021  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_RAM_ID,
180022  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_INJECT_TYPE,
180023  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_ECC_TYPE,
180024  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_MAX_NUM_CHECKERS,
180025  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_groupEntries },
180026  { SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_RAM_ID,
180027  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_INJECT_TYPE,
180028  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_ECC_TYPE,
180029  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_MAX_NUM_CHECKERS,
180030  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_groupEntries },
180031 };
180032 
180037 static const SDL_RAMIdEntry_t SDL_DMPAC0_ECC_AGGR_RamIdTable[SDL_DMPAC0_ECC_AGGR_NUM_RAMS] =
180038 {
180039  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_RAM_ID,
180040  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_INJECT_TYPE,
180041  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_RESPONSE_BUFFER0_ECC_TYPE,
180042  0u,
180043  NULL },
180044  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_RAM_ID,
180045  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_INJECT_TYPE,
180046  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER0_ECC_TYPE,
180047  0u,
180048  NULL },
180049  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_RAM_ID,
180050  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_INJECT_TYPE,
180051  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_STATE_BUFFER0_ECC_TYPE,
180052  0u,
180053  NULL },
180054  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_RAM_ID,
180055  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_INJECT_TYPE,
180056  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER1_ECC_TYPE,
180057  0u,
180058  NULL },
180059  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_RAM_ID,
180060  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_INJECT_TYPE,
180061  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_TPRAM_DRU_QUEUE_BUFFER2_ECC_TYPE,
180062  0u,
180063  NULL },
180064  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_RAM_ID,
180065  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_INJECT_TYPE,
180066  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_ECC_TYPE,
180067  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
180068  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries },
180069  { SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_RAM_ID,
180070  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_INJECT_TYPE,
180071  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_ECC_TYPE,
180072  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
180073  SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries },
180074 };
180075 
180080 static const SDL_RAMIdEntry_t SDL_MAIN_HC_ECC_AGGR0_RamIdTable[SDL_MAIN_HC_ECC_AGGR0_NUM_RAMS] =
180081 {
180082  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180083  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180084  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180085  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180086  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180087  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180088  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180089  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180090  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180091  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180092  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180093  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180094  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180095  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180096  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180097  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
180098  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
180099  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
180100  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180101  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
180102  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180103  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180104  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180105  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180106  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180107  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
180108  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
180109  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
180110  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180111  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
180112  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180113  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180114  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180115  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180116  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180117  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180118  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180119  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180120  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180121  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180122  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
180123  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
180124  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
180125  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
180126  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_groupEntries },
180127  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
180128  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
180129  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
180130  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
180131  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_groupEntries },
180132  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
180133  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
180134  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
180135  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
180136  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_groupEntries },
180137  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_RAM_ID,
180138  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
180139  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_ECC_TYPE,
180140  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
180141  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_groupEntries },
180142  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
180143  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
180144  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
180145  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180146  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
180147  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180148  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180149  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180150  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180151  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180152  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180153  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180154  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180155  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180156  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
180157  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
180158  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
180159  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
180160  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180161  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
180162  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
180163  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
180164  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
180165  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180166  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
180167  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_RAM_ID,
180168  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_INJECT_TYPE,
180169  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_ECC_TYPE,
180170  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_MAX_NUM_CHECKERS,
180171  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_groupEntries },
180172  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_RAM_ID,
180173  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_INJECT_TYPE,
180174  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_ECC_TYPE,
180175  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_MAX_NUM_CHECKERS,
180176  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_groupEntries },
180177  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_RAM_ID,
180178  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_INJECT_TYPE,
180179  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_ECC_TYPE,
180180  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_MAX_NUM_CHECKERS,
180181  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_groupEntries },
180182  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180183  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180184  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180185  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180186  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180187  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
180188  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
180189  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
180190  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180191  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
180192  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
180193  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
180194  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
180195  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
180196  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_groupEntries },
180197  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
180198  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
180199  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
180200  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
180201  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_groupEntries },
180202  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
180203  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
180204  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
180205  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180206  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
180207  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180208  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180209  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180210  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180211  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180212  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180213  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180214  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180215  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180216  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
180217  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
180218  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
180219  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
180220  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180221  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
180222  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
180223  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
180224  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
180225  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180226  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries },
180227  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_RAM_ID,
180228  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_INJECT_TYPE,
180229  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ECC_TYPE,
180230  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS,
180231  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries },
180232  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
180233  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180234  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
180235  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180236  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries },
180237  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_RAM_ID,
180238  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
180239  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
180240  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180241  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries },
180242  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
180243  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
180244  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
180245  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
180246  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
180247  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180248  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180249  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180250  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180251  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180252  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180253  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180254  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180255  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180256  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
180257  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180258  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180259  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180260  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180261  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180262  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180263  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180264  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180265  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180266  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
180267  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180268  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180269  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180270  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180271  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
180272  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
180273  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
180274  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
180275  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180276  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
180277  { SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
180278  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
180279  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
180280  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
180281  SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
180282  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
180283  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
180284  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
180285  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
180286  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
180287  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180288  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180289  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180290  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180291  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
180292  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180293  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180294  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180295  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180296  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180297  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_RAM_ID,
180298  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_INJECT_TYPE,
180299  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_ECC_TYPE,
180300  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
180301  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_groupEntries },
180302  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_RAM_ID,
180303  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_INJECT_TYPE,
180304  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_ECC_TYPE,
180305  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
180306  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_groupEntries },
180307  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_RAM_ID,
180308  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_INJECT_TYPE,
180309  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_ECC_TYPE,
180310  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
180311  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_groupEntries },
180312  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_RAM_ID,
180313  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_INJECT_TYPE,
180314  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_ECC_TYPE,
180315  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS,
180316  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_groupEntries },
180317  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_RAM_ID,
180318  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_INJECT_TYPE,
180319  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_ECC_TYPE,
180320  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS,
180321  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_groupEntries },
180322  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_RAM_ID,
180323  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_INJECT_TYPE,
180324  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_ECC_TYPE,
180325  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS,
180326  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_groupEntries },
180327  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180328  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180329  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180330  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180331  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180332  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180333  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180334  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180335  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180336  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
180337  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180338  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180339  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180340  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180341  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180342  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
180343  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
180344  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
180345  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
180346  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
180347  { SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
180348  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
180349  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
180350  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
180351  SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
180352  { SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_RAM_ID,
180353  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_INJECT_TYPE,
180354  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_ECC_TYPE,
180355  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
180356  SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_groupEntries },
180357  { SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_RAM_ID,
180358  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
180359  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_ECC_TYPE,
180360  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
180361  SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries },
180362 };
180363 
180368 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_NUM_RAMS] =
180369 {
180370  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_RAM_ID,
180371  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_INJECT_TYPE,
180372  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_ECC_TYPE,
180373  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_MAX_NUM_CHECKERS,
180374  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries },
180375  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_RAM_ID,
180376  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_INJECT_TYPE,
180377  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_ECC_TYPE,
180378  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS,
180379  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries },
180380  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
180381  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
180382  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
180383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
180384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
180385 };
180386 
180391 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_NUM_RAMS] =
180392 {
180393  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_RAM_ID,
180394  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_INJECT_TYPE,
180395  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_ECC_TYPE,
180396  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_MAX_NUM_CHECKERS,
180397  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_groupEntries },
180398  { SDL_ECC_RAMID_INVALID,
180399  0u,
180400  0u,
180401  0u,
180402  NULL },
180403  { SDL_ECC_RAMID_INVALID,
180404  0u,
180405  0u,
180406  0u,
180407  NULL },
180408  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
180409  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
180410  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
180411  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
180412  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
180413  { SDL_ECC_RAMID_INVALID,
180414  0u,
180415  0u,
180416  0u,
180417  NULL },
180418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
180419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
180420  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
180421  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
180422  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries },
180423  { SDL_ECC_RAMID_INVALID,
180424  0u,
180425  0u,
180426  0u,
180427  NULL },
180428  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_RAM_ID,
180429  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_INJECT_TYPE,
180430  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_ECC_TYPE,
180431  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_MAX_NUM_CHECKERS,
180432  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries },
180433  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_RAM_ID,
180434  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_INJECT_TYPE,
180435  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_ECC_TYPE,
180436  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_MAX_NUM_CHECKERS,
180437  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries },
180438  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_RAM_ID,
180439  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_INJECT_TYPE,
180440  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_ECC_TYPE,
180441  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_MAX_NUM_CHECKERS,
180442  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries },
180443  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_RAM_ID,
180444  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_INJECT_TYPE,
180445  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_ECC_TYPE,
180446  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
180447  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries },
180448  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_RAM_ID,
180449  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
180450  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
180451  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
180452  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries },
180453  { SDL_ECC_RAMID_INVALID,
180454  0u,
180455  0u,
180456  0u,
180457  NULL },
180458  { SDL_ECC_RAMID_INVALID,
180459  0u,
180460  0u,
180461  0u,
180462  NULL },
180463  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
180464  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
180465  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
180466  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
180467  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
180468  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
180469  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
180470  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
180471  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
180472  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
180473  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_RAM_ID,
180474  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_INJECT_TYPE,
180475  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_ECC_TYPE,
180476  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
180477  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries },
180478  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_RAM_ID,
180479  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_INJECT_TYPE,
180480  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_ECC_TYPE,
180481  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS,
180482  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries },
180483  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_RAM_ID,
180484  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_INJECT_TYPE,
180485  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ECC_TYPE,
180486  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS,
180487  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries },
180488  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_RAM_ID,
180489  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_INJECT_TYPE,
180490  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_ECC_TYPE,
180491  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_MAX_NUM_CHECKERS,
180492  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries },
180493  { SDL_ECC_RAMID_INVALID,
180494  0u,
180495  0u,
180496  0u,
180497  NULL },
180498  { SDL_ECC_RAMID_INVALID,
180499  0u,
180500  0u,
180501  0u,
180502  NULL },
180503  { SDL_ECC_RAMID_INVALID,
180504  0u,
180505  0u,
180506  0u,
180507  NULL },
180508  { SDL_ECC_RAMID_INVALID,
180509  0u,
180510  0u,
180511  0u,
180512  NULL },
180513  { SDL_ECC_RAMID_INVALID,
180514  0u,
180515  0u,
180516  0u,
180517  NULL },
180518  { SDL_ECC_RAMID_INVALID,
180519  0u,
180520  0u,
180521  0u,
180522  NULL },
180523  { SDL_ECC_RAMID_INVALID,
180524  0u,
180525  0u,
180526  0u,
180527  NULL },
180528  { SDL_ECC_RAMID_INVALID,
180529  0u,
180530  0u,
180531  0u,
180532  NULL },
180533  { SDL_ECC_RAMID_INVALID,
180534  0u,
180535  0u,
180536  0u,
180537  NULL },
180538  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_RAM_ID,
180539  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_INJECT_TYPE,
180540  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_ECC_TYPE,
180541  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
180542  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries },
180543  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
180544  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
180545  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
180546  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
180547  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
180548  { SDL_ECC_RAMID_INVALID,
180549  0u,
180550  0u,
180551  0u,
180552  NULL },
180553  { SDL_ECC_RAMID_INVALID,
180554  0u,
180555  0u,
180556  0u,
180557  NULL },
180558  { SDL_ECC_RAMID_INVALID,
180559  0u,
180560  0u,
180561  0u,
180562  NULL },
180563  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
180564  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
180565  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
180566  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
180567  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
180568  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_RAM_ID,
180569  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_INJECT_TYPE,
180570  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_ECC_TYPE,
180571  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_MAX_NUM_CHECKERS,
180572  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries },
180573  { SDL_ECC_RAMID_INVALID,
180574  0u,
180575  0u,
180576  0u,
180577  NULL },
180578  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
180579  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
180580  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
180581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
180582  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
180583  { SDL_ECC_RAMID_INVALID,
180584  0u,
180585  0u,
180586  0u,
180587  NULL },
180588  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_RAM_ID,
180589  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_INJECT_TYPE,
180590  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_ECC_TYPE,
180591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_MAX_NUM_CHECKERS,
180592  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_groupEntries },
180593  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_RAM_ID,
180594  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_INJECT_TYPE,
180595  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_ECC_TYPE,
180596  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_MAX_NUM_CHECKERS,
180597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_groupEntries },
180598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
180599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
180600  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
180601  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
180602  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
180603  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
180604  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
180605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
180606  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
180607  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries },
180608  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_RAM_ID,
180609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_INJECT_TYPE,
180610  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_ECC_TYPE,
180611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
180612  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_groupEntries },
180613  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_RAM_ID,
180614  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_INJECT_TYPE,
180615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_ECC_TYPE,
180616  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_MAX_NUM_CHECKERS,
180617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_groupEntries },
180618  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_RAM_ID,
180619  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_INJECT_TYPE,
180620  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_ECC_TYPE,
180621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_MAX_NUM_CHECKERS,
180622  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries },
180623  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_RAM_ID,
180624  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_INJECT_TYPE,
180625  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_ECC_TYPE,
180626  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS,
180627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries },
180628 };
180629 
180634 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_NUM_RAMS] =
180635 {
180636  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_RAM_ID,
180637  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_INJECT_TYPE,
180638  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_ECC_TYPE,
180639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_MAX_NUM_CHECKERS,
180640  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_groupEntries },
180641  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_RAM_ID,
180642  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_INJECT_TYPE,
180643  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_ECC_TYPE,
180644  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_MAX_NUM_CHECKERS,
180645  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_groupEntries },
180646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_RAM_ID,
180647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_INJECT_TYPE,
180648  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_ECC_TYPE,
180649  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_MAX_NUM_CHECKERS,
180650  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_groupEntries },
180651  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_RAM_ID,
180652  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_INJECT_TYPE,
180653  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_ECC_TYPE,
180654  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_MAX_NUM_CHECKERS,
180655  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_groupEntries },
180656  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_RAM_ID,
180657  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_INJECT_TYPE,
180658  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_ECC_TYPE,
180659  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_MAX_NUM_CHECKERS,
180660  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_groupEntries },
180661  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_RAM_ID,
180662  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_INJECT_TYPE,
180663  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_ECC_TYPE,
180664  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_MAX_NUM_CHECKERS,
180665  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_groupEntries },
180666  { SDL_ECC_RAMID_INVALID,
180667  0u,
180668  0u,
180669  0u,
180670  NULL },
180671  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_ID,
180672  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_INJECT_TYPE,
180673  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ECC_TYPE,
180674  0u,
180675  NULL },
180676  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_RAM_ID,
180677  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_INJECT_TYPE,
180678  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_ECC_TYPE,
180679  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_MAX_NUM_CHECKERS,
180680  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_groupEntries },
180681  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_RAM_ID,
180682  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_INJECT_TYPE,
180683  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_ECC_TYPE,
180684  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_MAX_NUM_CHECKERS,
180685  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_groupEntries },
180686  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_RAM_ID,
180687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_INJECT_TYPE,
180688  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_ECC_TYPE,
180689  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_MAX_NUM_CHECKERS,
180690  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_groupEntries },
180691  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_RAM_ID,
180692  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_INJECT_TYPE,
180693  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_ECC_TYPE,
180694  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_MAX_NUM_CHECKERS,
180695  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_groupEntries },
180696  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_RAM_ID,
180697  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_INJECT_TYPE,
180698  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_ECC_TYPE,
180699  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_MAX_NUM_CHECKERS,
180700  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_groupEntries },
180701  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_RAM_ID,
180702  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_INJECT_TYPE,
180703  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_ECC_TYPE,
180704  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
180705  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries },
180706  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_RAM_ID,
180707  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_INJECT_TYPE,
180708  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_ECC_TYPE,
180709  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_MAX_NUM_CHECKERS,
180710  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_groupEntries },
180711  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_RAM_ID,
180712  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_INJECT_TYPE,
180713  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_ECC_TYPE,
180714  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_MAX_NUM_CHECKERS,
180715  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_groupEntries },
180716  { SDL_ECC_RAMID_INVALID,
180717  0u,
180718  0u,
180719  0u,
180720  NULL },
180721  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_RAM_ID,
180722  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_INJECT_TYPE,
180723  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_ECC_TYPE,
180724  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_MAX_NUM_CHECKERS,
180725  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_groupEntries },
180726  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_RAM_ID,
180727  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_INJECT_TYPE,
180728  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_ECC_TYPE,
180729  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_MAX_NUM_CHECKERS,
180730  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_groupEntries },
180731  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_RAM_ID,
180732  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_INJECT_TYPE,
180733  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_ECC_TYPE,
180734  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_MAX_NUM_CHECKERS,
180735  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_groupEntries },
180736  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID,
180737  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_INJECT_TYPE,
180738  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_ECC_TYPE,
180739  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS,
180740  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_groupEntries },
180741  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_RAM_ID,
180742  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_INJECT_TYPE,
180743  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_ECC_TYPE,
180744  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_MAX_NUM_CHECKERS,
180745  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_groupEntries },
180746  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_RAM_ID,
180747  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
180748  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE,
180749  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180750  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_groupEntries },
180751  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_RAM_ID,
180752  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
180753  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_ECC_TYPE,
180754  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180755  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_groupEntries },
180756  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
180757  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
180758  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE,
180759  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180760  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_groupEntries },
180761  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_RAM_ID,
180762  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
180763  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_ECC_TYPE,
180764  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180765  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_groupEntries },
180766  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_RAM_ID,
180767  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_INJECT_TYPE,
180768  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_ECC_TYPE,
180769  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_MAX_NUM_CHECKERS,
180770  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_groupEntries },
180771  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_RAM_ID,
180772  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_INJECT_TYPE,
180773  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_ECC_TYPE,
180774  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_MAX_NUM_CHECKERS,
180775  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_groupEntries },
180776  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_RAM_ID,
180777  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
180778  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE,
180779  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180780  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries },
180781  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
180782  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
180783  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE,
180784  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180785  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries },
180786  { SDL_ECC_RAMID_INVALID,
180787  0u,
180788  0u,
180789  0u,
180790  NULL },
180791  { SDL_ECC_RAMID_INVALID,
180792  0u,
180793  0u,
180794  0u,
180795  NULL },
180796  { SDL_ECC_RAMID_INVALID,
180797  0u,
180798  0u,
180799  0u,
180800  NULL },
180801  { SDL_ECC_RAMID_INVALID,
180802  0u,
180803  0u,
180804  0u,
180805  NULL },
180806  { SDL_ECC_RAMID_INVALID,
180807  0u,
180808  0u,
180809  0u,
180810  NULL },
180811  { SDL_ECC_RAMID_INVALID,
180812  0u,
180813  0u,
180814  0u,
180815  NULL },
180816  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_RAM_ID,
180817  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
180818  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_ECC_TYPE,
180819  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180820  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_groupEntries },
180821  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_RAM_ID,
180822  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
180823  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_ECC_TYPE,
180824  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180825  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_groupEntries },
180826  { SDL_ECC_RAMID_INVALID,
180827  0u,
180828  0u,
180829  0u,
180830  NULL },
180831  { SDL_ECC_RAMID_INVALID,
180832  0u,
180833  0u,
180834  0u,
180835  NULL },
180836  { SDL_ECC_RAMID_INVALID,
180837  0u,
180838  0u,
180839  0u,
180840  NULL },
180841  { SDL_ECC_RAMID_INVALID,
180842  0u,
180843  0u,
180844  0u,
180845  NULL },
180846  { SDL_ECC_RAMID_INVALID,
180847  0u,
180848  0u,
180849  0u,
180850  NULL },
180851  { SDL_ECC_RAMID_INVALID,
180852  0u,
180853  0u,
180854  0u,
180855  NULL },
180856  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_RAM_ID,
180857  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
180858  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_ECC_TYPE,
180859  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180860  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries },
180861  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_RAM_ID,
180862  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
180863  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_ECC_TYPE,
180864  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180865  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries },
180866  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_RAM_ID,
180867  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
180868  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_ECC_TYPE,
180869  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180870  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries },
180871  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_RAM_ID,
180872  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
180873  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_ECC_TYPE,
180874  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS,
180875  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries },
180876  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_RAM_ID,
180877  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_INJECT_TYPE,
180878  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_ECC_TYPE,
180879  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_MAX_NUM_CHECKERS,
180880  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_groupEntries },
180881  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_RAM_ID,
180882  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_INJECT_TYPE,
180883  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_ECC_TYPE,
180884  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_MAX_NUM_CHECKERS,
180885  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_groupEntries },
180886  { SDL_ECC_RAMID_INVALID,
180887  0u,
180888  0u,
180889  0u,
180890  NULL },
180891  { SDL_ECC_RAMID_INVALID,
180892  0u,
180893  0u,
180894  0u,
180895  NULL },
180896  { SDL_ECC_RAMID_INVALID,
180897  0u,
180898  0u,
180899  0u,
180900  NULL },
180901  { SDL_ECC_RAMID_INVALID,
180902  0u,
180903  0u,
180904  0u,
180905  NULL },
180906  { SDL_ECC_RAMID_INVALID,
180907  0u,
180908  0u,
180909  0u,
180910  NULL },
180911  { SDL_ECC_RAMID_INVALID,
180912  0u,
180913  0u,
180914  0u,
180915  NULL },
180916  { SDL_ECC_RAMID_INVALID,
180917  0u,
180918  0u,
180919  0u,
180920  NULL },
180921  { SDL_ECC_RAMID_INVALID,
180922  0u,
180923  0u,
180924  0u,
180925  NULL },
180926  { SDL_ECC_RAMID_INVALID,
180927  0u,
180928  0u,
180929  0u,
180930  NULL },
180931  { SDL_ECC_RAMID_INVALID,
180932  0u,
180933  0u,
180934  0u,
180935  NULL },
180936  { SDL_ECC_RAMID_INVALID,
180937  0u,
180938  0u,
180939  0u,
180940  NULL },
180941  { SDL_ECC_RAMID_INVALID,
180942  0u,
180943  0u,
180944  0u,
180945  NULL },
180946  { SDL_ECC_RAMID_INVALID,
180947  0u,
180948  0u,
180949  0u,
180950  NULL },
180951  { SDL_ECC_RAMID_INVALID,
180952  0u,
180953  0u,
180954  0u,
180955  NULL },
180956  { SDL_ECC_RAMID_INVALID,
180957  0u,
180958  0u,
180959  0u,
180960  NULL },
180961  { SDL_ECC_RAMID_INVALID,
180962  0u,
180963  0u,
180964  0u,
180965  NULL },
180966  { SDL_ECC_RAMID_INVALID,
180967  0u,
180968  0u,
180969  0u,
180970  NULL },
180971  { SDL_ECC_RAMID_INVALID,
180972  0u,
180973  0u,
180974  0u,
180975  NULL },
180976  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_RAM_ID,
180977  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_INJECT_TYPE,
180978  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_ECC_TYPE,
180979  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_MAX_NUM_CHECKERS,
180980  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_groupEntries },
180981  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_RAM_ID,
180982  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
180983  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_ECC_TYPE,
180984  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS,
180985  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries },
180986  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_RAM_ID,
180987  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_INJECT_TYPE,
180988  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ECC_TYPE,
180989  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_MAX_NUM_CHECKERS,
180990  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_groupEntries },
180991  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_RAM_ID,
180992  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_INJECT_TYPE,
180993  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_ECC_TYPE,
180994  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_MAX_NUM_CHECKERS,
180995  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_groupEntries },
180996  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_RAM_ID,
180997  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
180998  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_ECC_TYPE,
180999  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS,
181000  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries },
181001  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_RAM_ID,
181002  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
181003  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_ECC_TYPE,
181004  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS,
181005  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries },
181006  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_RAM_ID,
181007  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_INJECT_TYPE,
181008  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_ECC_TYPE,
181009  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_MAX_NUM_CHECKERS,
181010  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_groupEntries },
181011  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_RAM_ID,
181012  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_INJECT_TYPE,
181013  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_ECC_TYPE,
181014  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_MAX_NUM_CHECKERS,
181015  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_groupEntries },
181016  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_RAM_ID,
181017  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_INJECT_TYPE,
181018  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_ECC_TYPE,
181019  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_MAX_NUM_CHECKERS,
181020  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_groupEntries },
181021  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_RAM_ID,
181022  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
181023  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_ECC_TYPE,
181024  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS,
181025  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries },
181026  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_RAM_ID,
181027  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_INJECT_TYPE,
181028  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_ECC_TYPE,
181029  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_MAX_NUM_CHECKERS,
181030  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_groupEntries },
181031  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_RAM_ID,
181032  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_INJECT_TYPE,
181033  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_ECC_TYPE,
181034  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_MAX_NUM_CHECKERS,
181035  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_groupEntries },
181036  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_RAM_ID,
181037  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
181038  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_ECC_TYPE,
181039  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS,
181040  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries },
181041  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_RAM_ID,
181042  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
181043  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_ECC_TYPE,
181044  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS,
181045  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries },
181046  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_RAM_ID,
181047  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_INJECT_TYPE,
181048  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_ECC_TYPE,
181049  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_MAX_NUM_CHECKERS,
181050  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_groupEntries },
181051  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_RAM_ID,
181052  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_INJECT_TYPE,
181053  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_ECC_TYPE,
181054  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_MAX_NUM_CHECKERS,
181055  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_groupEntries },
181056  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_RAM_ID,
181057  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_INJECT_TYPE,
181058  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_ECC_TYPE,
181059  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_MAX_NUM_CHECKERS,
181060  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_groupEntries },
181061  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_RAM_ID,
181062  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
181063  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_ECC_TYPE,
181064  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS,
181065  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_groupEntries },
181066  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_RAM_ID,
181067  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_INJECT_TYPE,
181068  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_ECC_TYPE,
181069  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_MAX_NUM_CHECKERS,
181070  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_groupEntries },
181071  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_RAM_ID,
181072  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_INJECT_TYPE,
181073  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_ECC_TYPE,
181074  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_MAX_NUM_CHECKERS,
181075  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_groupEntries },
181076  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_RAM_ID,
181077  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
181078  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_ECC_TYPE,
181079  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS,
181080  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_groupEntries },
181081  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_RAM_ID,
181082  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
181083  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_ECC_TYPE,
181084  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS,
181085  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_groupEntries },
181086  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_RAM_ID,
181087  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_INJECT_TYPE,
181088  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_ECC_TYPE,
181089  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_MAX_NUM_CHECKERS,
181090  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_groupEntries },
181091  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_RAM_ID,
181092  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_INJECT_TYPE,
181093  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_ECC_TYPE,
181094  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_MAX_NUM_CHECKERS,
181095  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_groupEntries },
181096  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_RAM_ID,
181097  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_INJECT_TYPE,
181098  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_ECC_TYPE,
181099  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_MAX_NUM_CHECKERS,
181100  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_groupEntries },
181101  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_RAM_ID,
181102  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
181103  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_ECC_TYPE,
181104  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS,
181105  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_groupEntries },
181106  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_RAM_ID,
181107  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_INJECT_TYPE,
181108  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_ECC_TYPE,
181109  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_MAX_NUM_CHECKERS,
181110  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_groupEntries },
181111  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_RAM_ID,
181112  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_INJECT_TYPE,
181113  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_ECC_TYPE,
181114  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_MAX_NUM_CHECKERS,
181115  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_groupEntries },
181116  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_RAM_ID,
181117  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
181118  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_ECC_TYPE,
181119  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS,
181120  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_groupEntries },
181121  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_RAM_ID,
181122  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
181123  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_ECC_TYPE,
181124  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS,
181125  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_groupEntries },
181126  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_RAM_ID,
181127  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_INJECT_TYPE,
181128  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_ECC_TYPE,
181129  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_MAX_NUM_CHECKERS,
181130  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_groupEntries },
181131  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_RAM_ID,
181132  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_INJECT_TYPE,
181133  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_ECC_TYPE,
181134  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_MAX_NUM_CHECKERS,
181135  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_groupEntries },
181136  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID,
181137  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_INJECT_TYPE,
181138  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ECC_TYPE,
181139  0u,
181140  NULL },
181141  { SDL_ECC_RAMID_INVALID,
181142  0u,
181143  0u,
181144  0u,
181145  NULL },
181146  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
181147  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
181148  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE,
181149  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS,
181150  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries },
181151  { SDL_ECC_RAMID_INVALID,
181152  0u,
181153  0u,
181154  0u,
181155  NULL },
181156  { SDL_ECC_RAMID_INVALID,
181157  0u,
181158  0u,
181159  0u,
181160  NULL },
181161  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_RAM_ID,
181162  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_INJECT_TYPE,
181163  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_ECC_TYPE,
181164  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_MAX_NUM_CHECKERS,
181165  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_groupEntries },
181166  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_RAM_ID,
181167  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_INJECT_TYPE,
181168  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_ECC_TYPE,
181169  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_MAX_NUM_CHECKERS,
181170  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_groupEntries },
181171  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID,
181172  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_INJECT_TYPE,
181173  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ECC_TYPE,
181174  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
181175  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_groupEntries },
181176 };
181177 
181182 static const SDL_RAMIdEntry_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
181183 {
181184  { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
181185  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
181186  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
181187  0u,
181188  NULL },
181189  { SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
181190  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
181191  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
181192  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
181193  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
181194 };
181195 
181200 static const SDL_RAMIdEntry_t SDL_VPAC0_LDC_ECC_AGGR_RamIdTable[SDL_VPAC0_LDC_ECC_AGGR_NUM_RAMS] =
181201 {
181202  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_RAM_ID,
181203  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_INJECT_TYPE,
181204  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B0_MEMECC_ECC_TYPE,
181205  0u,
181206  NULL },
181207  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_RAM_ID,
181208  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_INJECT_TYPE,
181209  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALY_LUT_B1_MEMECC_ECC_TYPE,
181210  0u,
181211  NULL },
181212  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_RAM_ID,
181213  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_INJECT_TYPE,
181214  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B0_MEMECC_ECC_TYPE,
181215  0u,
181216  NULL },
181217  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_RAM_ID,
181218  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_INJECT_TYPE,
181219  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_DUALC_LUT_B1_MEMECC_ECC_TYPE,
181220  0u,
181221  NULL },
181222  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_RAM_ID,
181223  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_INJECT_TYPE,
181224  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P0_MEMECC_ECC_TYPE,
181225  0u,
181226  NULL },
181227  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_RAM_ID,
181228  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_INJECT_TYPE,
181229  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P0_MEMECC_ECC_TYPE,
181230  0u,
181231  NULL },
181232  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_RAM_ID,
181233  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_INJECT_TYPE,
181234  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P0_MEMECC_ECC_TYPE,
181235  0u,
181236  NULL },
181237  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_RAM_ID,
181238  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_INJECT_TYPE,
181239  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P0_MEMECC_ECC_TYPE,
181240  0u,
181241  NULL },
181242  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_RAM_ID,
181243  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_INJECT_TYPE,
181244  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B0_P1_MEMECC_ECC_TYPE,
181245  0u,
181246  NULL },
181247  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_RAM_ID,
181248  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_INJECT_TYPE,
181249  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B1_P1_MEMECC_ECC_TYPE,
181250  0u,
181251  NULL },
181252  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_RAM_ID,
181253  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_INJECT_TYPE,
181254  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B2_P1_MEMECC_ECC_TYPE,
181255  0u,
181256  NULL },
181257  { SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_RAM_ID,
181258  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_INJECT_TYPE,
181259  SDL_VPAC0_LDC_ECC_AGGR_VPAC_LDC_MEMWRAP_MESHMEM_B3_P1_MEMECC_ECC_TYPE,
181260  0u,
181261  NULL },
181262 };
181263 
181268 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
181269 {
181270  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
181271  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
181272  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
181273  0u,
181274  NULL },
181275  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
181276  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
181277  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
181278  0u,
181279  NULL },
181280  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
181281  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
181282  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
181283  0u,
181284  NULL },
181285  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
181286  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
181287  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
181288  0u,
181289  NULL },
181290  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
181291  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
181292  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
181293  0u,
181294  NULL },
181295  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
181296  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
181297  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
181298  0u,
181299  NULL },
181300  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
181301  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
181302  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
181303  0u,
181304  NULL },
181305  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
181306  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
181307  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
181308  0u,
181309  NULL },
181310  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
181311  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
181312  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
181313  0u,
181314  NULL },
181315  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
181316  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
181317  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
181318  0u,
181319  NULL },
181320  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
181321  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
181322  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
181323  0u,
181324  NULL },
181325  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
181326  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
181327  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
181328  0u,
181329  NULL },
181330  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
181331  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
181332  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
181333  0u,
181334  NULL },
181335  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
181336  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
181337  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
181338  0u,
181339  NULL },
181340  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
181341  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
181342  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
181343  0u,
181344  NULL },
181345  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
181346  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
181347  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
181348  0u,
181349  NULL },
181350  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
181351  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
181352  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
181353  0u,
181354  NULL },
181355  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
181356  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
181357  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
181358  0u,
181359  NULL },
181360  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
181361  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
181362  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
181363  0u,
181364  NULL },
181365  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
181366  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
181367  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
181368  0u,
181369  NULL },
181370  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
181371  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
181372  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
181373  0u,
181374  NULL },
181375  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
181376  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
181377  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
181378  0u,
181379  NULL },
181380  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
181381  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
181382  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
181383  0u,
181384  NULL },
181385  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
181386  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
181387  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
181388  0u,
181389  NULL },
181390  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
181391  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
181392  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
181393  0u,
181394  NULL },
181395  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
181396  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
181397  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
181398  0u,
181399  NULL },
181400  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
181401  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
181402  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
181403  0u,
181404  NULL },
181405  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
181406  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
181407  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
181408  0u,
181409  NULL },
181410  { SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_RAM_ID,
181411  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_INJECT_TYPE,
181412  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_ECC_TYPE,
181413  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS,
181414  SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries },
181415  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
181416  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
181417  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
181418  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
181419  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
181420  { SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
181421  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
181422  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
181423  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
181424  SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
181425  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
181426  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
181427  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
181428  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
181429  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
181430  { SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
181431  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
181432  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
181433  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
181434  SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
181435  { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_RAM_ID,
181436  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_INJECT_TYPE,
181437  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_ECC_TYPE,
181438  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS,
181439  SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries },
181440  { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_RAM_ID,
181441  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
181442  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_ECC_TYPE,
181443  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
181444  SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries },
181445 };
181446 
181451 static const SDL_RAMIdEntry_t SDL_NAVSS_VIRTSS_ECC_AGGR0_RamIdTable[SDL_NAVSS_VIRTSS_ECC_AGGR0_NUM_RAMS] =
181452 {
181453  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
181454  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
181455  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
181456  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
181457  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries },
181458  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
181459  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
181460  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
181461  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181462  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
181463  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
181464  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181465  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
181466  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181467  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
181468  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
181469  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
181470  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
181471  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181472  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
181473  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
181474  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181475  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
181476  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181477  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
181478  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
181479  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
181480  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
181481  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181482  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
181483  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
181484  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181485  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
181486  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181487  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
181488  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_RAM_ID,
181489  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_INJECT_TYPE,
181490  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_ECC_TYPE,
181491  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS,
181492  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries },
181493  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_RAM_ID,
181494  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_INJECT_TYPE,
181495  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_ECC_TYPE,
181496  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS,
181497  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries },
181498  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
181499  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
181500  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
181501  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
181502  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
181503  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_RAM_ID,
181504  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_INJECT_TYPE,
181505  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_ECC_TYPE,
181506  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS,
181507  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries },
181508  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_RAM_ID,
181509  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_INJECT_TYPE,
181510  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_ECC_TYPE,
181511  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_MAX_NUM_CHECKERS,
181512  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries },
181513  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_RAM_ID,
181514  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_INJECT_TYPE,
181515  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_ECC_TYPE,
181516  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS,
181517  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_groupEntries },
181518  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
181519  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
181520  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
181521  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
181522  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
181523  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_RAM_ID,
181524  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_INJECT_TYPE,
181525  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_ECC_TYPE,
181526  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS,
181527  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries },
181528  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_RAM_ID,
181529  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_INJECT_TYPE,
181530  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_ECC_TYPE,
181531  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_MAX_NUM_CHECKERS,
181532  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries },
181533  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_RAM_ID,
181534  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_INJECT_TYPE,
181535  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_ECC_TYPE,
181536  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_MAX_NUM_CHECKERS,
181537  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries },
181538  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_RAM_ID,
181539  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_INJECT_TYPE,
181540  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_ECC_TYPE,
181541  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_MAX_NUM_CHECKERS,
181542  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries },
181543  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_RAM_ID,
181544  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_INJECT_TYPE,
181545  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_ECC_TYPE,
181546  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_MAX_NUM_CHECKERS,
181547  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries },
181548  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_RAM_ID,
181549  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_INJECT_TYPE,
181550  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_ECC_TYPE,
181551  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_MAX_NUM_CHECKERS,
181552  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries },
181553  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_RAM_ID,
181554  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_INJECT_TYPE,
181555  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_ECC_TYPE,
181556  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_MAX_NUM_CHECKERS,
181557  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries },
181558  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_RAM_ID,
181559  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_INJECT_TYPE,
181560  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_ECC_TYPE,
181561  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_MAX_NUM_CHECKERS,
181562  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries },
181563  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_RAM_ID,
181564  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_INJECT_TYPE,
181565  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_ECC_TYPE,
181566  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_MAX_NUM_CHECKERS,
181567  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries },
181568  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_RAM_ID,
181569  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_INJECT_TYPE,
181570  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_ECC_TYPE,
181571  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_MAX_NUM_CHECKERS,
181572  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries },
181573  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_RAM_ID,
181574  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_INJECT_TYPE,
181575  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_ECC_TYPE,
181576  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_MAX_NUM_CHECKERS,
181577  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries },
181578  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_RAM_ID,
181579  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_INJECT_TYPE,
181580  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_ECC_TYPE,
181581  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS,
181582  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries },
181583  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
181584  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
181585  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
181586  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
181587  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
181588  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_RAM_ID,
181589  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_INJECT_TYPE,
181590  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_ECC_TYPE,
181591  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS,
181592  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_groupEntries },
181593  { SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_RAM_ID,
181594  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_INJECT_TYPE,
181595  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_ECC_TYPE,
181596  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS,
181597  SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries },
181598  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_RAM_ID,
181599  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_INJECT_TYPE,
181600  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_ECC_TYPE,
181601  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181602  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries },
181603  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_RAM_ID,
181604  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_INJECT_TYPE,
181605  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_ECC_TYPE,
181606  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181607  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_groupEntries },
181608  { SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_RAM_ID,
181609  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
181610  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_ECC_TYPE,
181611  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
181612  SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries },
181613 };
181614 
181619 static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
181620 {
181621  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
181622  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
181623  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
181624  0u,
181625  NULL },
181626  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
181627  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
181628  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
181629  0u,
181630  NULL },
181631  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
181632  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
181633  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
181634  0u,
181635  NULL },
181636  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
181637  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
181638  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
181639  0u,
181640  NULL },
181641  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
181642  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
181643  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
181644  0u,
181645  NULL },
181646  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
181647  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
181648  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
181649  0u,
181650  NULL },
181651  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
181652  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
181653  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
181654  0u,
181655  NULL },
181656  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
181657  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
181658  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
181659  0u,
181660  NULL },
181661  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
181662  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
181663  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
181664  0u,
181665  NULL },
181666  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
181667  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
181668  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
181669  0u,
181670  NULL },
181671  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
181672  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
181673  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
181674  0u,
181675  NULL },
181676  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
181677  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
181678  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
181679  0u,
181680  NULL },
181681  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
181682  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
181683  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
181684  0u,
181685  NULL },
181686  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
181687  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
181688  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
181689  0u,
181690  NULL },
181691  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
181692  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
181693  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
181694  0u,
181695  NULL },
181696  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
181697  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
181698  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
181699  0u,
181700  NULL },
181701  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
181702  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
181703  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
181704  0u,
181705  NULL },
181706  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
181707  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
181708  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
181709  0u,
181710  NULL },
181711  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
181712  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
181713  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
181714  0u,
181715  NULL },
181716  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
181717  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
181718  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
181719  0u,
181720  NULL },
181721  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
181722  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
181723  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
181724  0u,
181725  NULL },
181726  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
181727  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
181728  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
181729  0u,
181730  NULL },
181731  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
181732  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
181733  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
181734  0u,
181735  NULL },
181736  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
181737  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
181738  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
181739  0u,
181740  NULL },
181741  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
181742  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
181743  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
181744  0u,
181745  NULL },
181746  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
181747  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
181748  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
181749  0u,
181750  NULL },
181751  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
181752  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
181753  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
181754  0u,
181755  NULL },
181756  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
181757  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
181758  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
181759  0u,
181760  NULL },
181761  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_RAM_ID,
181762  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_INJECT_TYPE,
181763  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_ECC_TYPE,
181764  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS,
181765  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries },
181766  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
181767  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
181768  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
181769  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
181770  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
181771  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
181772  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
181773  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
181774  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
181775  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
181776  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
181777  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
181778  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE,
181779  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS,
181780  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries },
181781  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
181782  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
181783  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE,
181784  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS,
181785  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries },
181786  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_RAM_ID,
181787  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_INJECT_TYPE,
181788  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_ECC_TYPE,
181789  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS,
181790  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries },
181791  { SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_RAM_ID,
181792  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
181793  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_ECC_TYPE,
181794  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
181795  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries },
181796 };
181797 
181802 static const SDL_RAMIdEntry_t SDL_MCU_CBASS_ECC_AGGR0_RamIdTable[SDL_MCU_CBASS_ECC_AGGR0_NUM_RAMS] =
181803 {
181804  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_ID,
181805  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_INJECT_TYPE,
181806  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ECC_TYPE,
181807  0u,
181808  NULL },
181809  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_ID,
181810  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_INJECT_TYPE,
181811  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ECC_TYPE,
181812  0u,
181813  NULL },
181814  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID,
181815  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_INJECT_TYPE,
181816  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ECC_TYPE,
181817  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS,
181818  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries },
181819  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_RAM_ID,
181820  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_INJECT_TYPE,
181821  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_ECC_TYPE,
181822  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS,
181823  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries },
181824  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_RAM_ID,
181825  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_INJECT_TYPE,
181826  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_ECC_TYPE,
181827  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS,
181828  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries },
181829  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
181830  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
181831  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
181832  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
181833  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
181834  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_RAM_ID,
181835  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_INJECT_TYPE,
181836  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_ECC_TYPE,
181837  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS,
181838  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries },
181839  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_RAM_ID,
181840  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_INJECT_TYPE,
181841  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_ECC_TYPE,
181842  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS,
181843  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries },
181844  { SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_RAM_ID,
181845  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_INJECT_TYPE,
181846  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_ECC_TYPE,
181847  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS,
181848  SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries },
181849  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_RAM_ID,
181850  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_INJECT_TYPE,
181851  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_ECC_TYPE,
181852  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS,
181853  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries },
181854  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_RAM_ID,
181855  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_INJECT_TYPE,
181856  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_WR_RAMECC_ECC_TYPE,
181857  0u,
181858  NULL },
181859  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_RAM_ID,
181860  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_INJECT_TYPE,
181861  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_RD_RAMECC_ECC_TYPE,
181862  0u,
181863  NULL },
181864  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_RAM_ID,
181865  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_INJECT_TYPE,
181866  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_ECC_TYPE,
181867  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS,
181868  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries },
181869  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_RAM_ID,
181870  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_INJECT_TYPE,
181871  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_ECC_TYPE,
181872  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS,
181873  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries },
181874  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_RAM_ID,
181875  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_INJECT_TYPE,
181876  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_ECC_TYPE,
181877  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS,
181878  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries },
181879  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_RAM_ID,
181880  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_INJECT_TYPE,
181881  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_ECC_TYPE,
181882  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS,
181883  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries },
181884  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_RAM_ID,
181885  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_INJECT_TYPE,
181886  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_ECC_TYPE,
181887  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS,
181888  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries },
181889  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_RAM_ID,
181890  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181891  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
181892  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181893  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries },
181894  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_RAM_ID,
181895  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
181896  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
181897  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181898  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries },
181899  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_RAM_ID,
181900  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181901  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
181902  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181903  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries },
181904  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_RAM_ID,
181905  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
181906  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
181907  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181908  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries },
181909  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
181910  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
181911  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
181912  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
181913  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
181914  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_RAM_ID,
181915  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181916  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_ECC_TYPE,
181917  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181918  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries },
181919  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_RAM_ID,
181920  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_INJECT_TYPE,
181921  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_ECC_TYPE,
181922  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181923  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries },
181924  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
181925  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
181926  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
181927  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181928  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
181929  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_RAM_ID,
181930  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
181931  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
181932  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181933  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries },
181934  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_RAM_ID,
181935  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_INJECT_TYPE,
181936  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_ECC_TYPE,
181937  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181938  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries },
181939  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
181940  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
181941  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
181942  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181943  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries },
181944  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
181945  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181946  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
181947  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181948  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
181949  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
181950  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
181951  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
181952  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181953  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
181954  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_RAM_ID,
181955  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_INJECT_TYPE,
181956  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_ECC_TYPE,
181957  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181958  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries },
181959  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_RAM_ID,
181960  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_INJECT_TYPE,
181961  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_ECC_TYPE,
181962  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
181963  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries },
181964  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
181965  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
181966  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
181967  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
181968  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_groupEntries },
181969  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_RAM_ID,
181970  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
181971  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
181972  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
181973  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_groupEntries },
181974  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
181975  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
181976  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
181977  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
181978  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries },
181979  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
181980  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
181981  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
181982  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
181983  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries },
181984  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
181985  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
181986  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
181987  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
181988  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries },
181989  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
181990  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
181991  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
181992  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
181993  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries },
181994  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_RAM_ID,
181995  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
181996  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_ECC_TYPE,
181997  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
181998  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries },
181999  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_RAM_ID,
182000  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_INJECT_TYPE,
182001  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_ECC_TYPE,
182002  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
182003  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries },
182004  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_RAM_ID,
182005  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_INJECT_TYPE,
182006  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_ECC_TYPE,
182007  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
182008  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_groupEntries },
182009  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
182010  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
182011  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
182012  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
182013  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries },
182014  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
182015  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
182016  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
182017  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
182018  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries },
182019  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
182020  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
182021  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
182022  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
182023  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries },
182024  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
182025  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
182026  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
182027  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
182028  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries },
182029  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
182030  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
182031  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
182032  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
182033  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries },
182034  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_RAM_ID,
182035  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
182036  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_ECC_TYPE,
182037  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
182038  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries },
182039  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_RAM_ID,
182040  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_INJECT_TYPE,
182041  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_ECC_TYPE,
182042  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
182043  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_groupEntries },
182044  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_RAM_ID,
182045  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_INJECT_TYPE,
182046  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_ECC_TYPE,
182047  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
182048  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_groupEntries },
182049  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_RAM_ID,
182050  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
182051  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
182052  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182053  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries },
182054  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_RAM_ID,
182055  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_INJECT_TYPE,
182056  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_ECC_TYPE,
182057  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
182058  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries },
182059  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_RAM_ID,
182060  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_INJECT_TYPE,
182061  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_ECC_TYPE,
182062  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
182063  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries },
182064  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_RAM_ID,
182065  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_INJECT_TYPE,
182066  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_ECC_TYPE,
182067  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
182068  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries },
182069  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_RAM_ID,
182070  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_INJECT_TYPE,
182071  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_ECC_TYPE,
182072  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
182073  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries },
182074  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_RAM_ID,
182075  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_INJECT_TYPE,
182076  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_ECC_TYPE,
182077  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
182078  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries },
182079  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_RAM_ID,
182080  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_INJECT_TYPE,
182081  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_ECC_TYPE,
182082  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
182083  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries },
182084  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_RAM_ID,
182085  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_INJECT_TYPE,
182086  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_ECC_TYPE,
182087  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
182088  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries },
182089  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_RAM_ID,
182090  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_INJECT_TYPE,
182091  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_ECC_TYPE,
182092  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS,
182093  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries },
182094  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_RAM_ID,
182095  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_INJECT_TYPE,
182096  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_ECC_TYPE,
182097  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS,
182098  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_groupEntries },
182099  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_RAM_ID,
182100  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_INJECT_TYPE,
182101  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_ECC_TYPE,
182102  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS,
182103  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_groupEntries },
182104  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_RAM_ID,
182105  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_INJECT_TYPE,
182106  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_ECC_TYPE,
182107  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS,
182108  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_groupEntries },
182109  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_RAM_ID,
182110  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_INJECT_TYPE,
182111  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_ECC_TYPE,
182112  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS,
182113  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_groupEntries },
182114  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_RAM_ID,
182115  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_INJECT_TYPE,
182116  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_ECC_TYPE,
182117  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS,
182118  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_groupEntries },
182119  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_RAM_ID,
182120  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_INJECT_TYPE,
182121  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_ECC_TYPE,
182122  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS,
182123  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_groupEntries },
182124  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_RAM_ID,
182125  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_INJECT_TYPE,
182126  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_ECC_TYPE,
182127  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS,
182128  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_groupEntries },
182129  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_RAM_ID,
182130  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_INJECT_TYPE,
182131  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_ECC_TYPE,
182132  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS,
182133  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_groupEntries },
182134  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_RAM_ID,
182135  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_INJECT_TYPE,
182136  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_ECC_TYPE,
182137  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS,
182138  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_groupEntries },
182139  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_RAM_ID,
182140  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_INJECT_TYPE,
182141  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_ECC_TYPE,
182142  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS,
182143  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_groupEntries },
182144  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_RAM_ID,
182145  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_INJECT_TYPE,
182146  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_ECC_TYPE,
182147  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS,
182148  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_groupEntries },
182149  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_RAM_ID,
182150  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_INJECT_TYPE,
182151  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_ECC_TYPE,
182152  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS,
182153  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_groupEntries },
182154  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_RAM_ID,
182155  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_INJECT_TYPE,
182156  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_ECC_TYPE,
182157  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS,
182158  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_groupEntries },
182159  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_RAM_ID,
182160  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_INJECT_TYPE,
182161  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_ECC_TYPE,
182162  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_MAX_NUM_CHECKERS,
182163  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_groupEntries },
182164  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_RAM_ID,
182165  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_INJECT_TYPE,
182166  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_ECC_TYPE,
182167  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_MAX_NUM_CHECKERS,
182168  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_groupEntries },
182169  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_RAM_ID,
182170  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_INJECT_TYPE,
182171  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_ECC_TYPE,
182172  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_MAX_NUM_CHECKERS,
182173  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_groupEntries },
182174  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_RAM_ID,
182175  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_INJECT_TYPE,
182176  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_ECC_TYPE,
182177  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_MAX_NUM_CHECKERS,
182178  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_groupEntries },
182179  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_RAM_ID,
182180  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_INJECT_TYPE,
182181  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_ECC_TYPE,
182182  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_MAX_NUM_CHECKERS,
182183  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_groupEntries },
182184  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_RAM_ID,
182185  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_INJECT_TYPE,
182186  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_ECC_TYPE,
182187  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_MAX_NUM_CHECKERS,
182188  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_groupEntries },
182189  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_RAM_ID,
182190  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_INJECT_TYPE,
182191  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_ECC_TYPE,
182192  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_MAX_NUM_CHECKERS,
182193  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_groupEntries },
182194  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_RAM_ID,
182195  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_INJECT_TYPE,
182196  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_ECC_TYPE,
182197  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_MAX_NUM_CHECKERS,
182198  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_groupEntries },
182199  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_RAM_ID,
182200  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_INJECT_TYPE,
182201  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_ECC_TYPE,
182202  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_MAX_NUM_CHECKERS,
182203  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_groupEntries },
182204  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_RAM_ID,
182205  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_INJECT_TYPE,
182206  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_ECC_TYPE,
182207  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_MAX_NUM_CHECKERS,
182208  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_groupEntries },
182209  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_RAM_ID,
182210  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_INJECT_TYPE,
182211  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_ECC_TYPE,
182212  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_MAX_NUM_CHECKERS,
182213  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_groupEntries },
182214  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
182215  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
182216  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
182217  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
182218  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
182219  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_RAM_ID,
182220  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
182221  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
182222  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
182223  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries },
182224  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
182225  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
182226  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
182227  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182228  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
182229  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_RAM_ID,
182230  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
182231  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
182232  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182233  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries },
182234  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
182235  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
182236  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
182237  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
182238  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
182239  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
182240  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
182241  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
182242  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
182243  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
182244  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
182245  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
182246  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
182247  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182248  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
182249  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_RAM_ID,
182250  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_INJECT_TYPE,
182251  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_ECC_TYPE,
182252  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_MAX_NUM_CHECKERS,
182253  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries },
182254  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_RAM_ID,
182255  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_INJECT_TYPE,
182256  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_ECC_TYPE,
182257  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_MAX_NUM_CHECKERS,
182258  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries },
182259  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_RAM_ID,
182260  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_INJECT_TYPE,
182261  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_ECC_TYPE,
182262  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_MAX_NUM_CHECKERS,
182263  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries },
182264  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_RAM_ID,
182265  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_INJECT_TYPE,
182266  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_ECC_TYPE,
182267  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_MAX_NUM_CHECKERS,
182268  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries },
182269  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_RAM_ID,
182270  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_INJECT_TYPE,
182271  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_ECC_TYPE,
182272  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS,
182273  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries },
182274  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_RAM_ID,
182275  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_INJECT_TYPE,
182276  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_ECC_TYPE,
182277  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS,
182278  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries },
182279  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_RAM_ID,
182280  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_INJECT_TYPE,
182281  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_ECC_TYPE,
182282  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_MAX_NUM_CHECKERS,
182283  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries },
182284  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_RAM_ID,
182285  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_INJECT_TYPE,
182286  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_ECC_TYPE,
182287  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_MAX_NUM_CHECKERS,
182288  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries },
182289  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
182290  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
182291  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
182292  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
182293  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
182294  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_RAM_ID,
182295  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
182296  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
182297  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182298  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries },
182299  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_RAM_ID,
182300  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_INJECT_TYPE,
182301  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_ECC_TYPE,
182302  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS,
182303  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries },
182304  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_RAM_ID,
182305  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_INJECT_TYPE,
182306  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_WR_RAMECC_ECC_TYPE,
182307  0u,
182308  NULL },
182309  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_RAM_ID,
182310  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_INJECT_TYPE,
182311  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_RD_RAMECC_ECC_TYPE,
182312  0u,
182313  NULL },
182314  { SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_RAM_ID,
182315  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_INJECT_TYPE,
182316  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_ECC_TYPE,
182317  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_MAX_NUM_CHECKERS,
182318  SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries },
182319  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_RAM_ID,
182320  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
182321  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
182322  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182323  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries },
182324  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID,
182325  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
182326  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
182327  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182328  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries },
182329  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_RAM_ID,
182330  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
182331  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
182332  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182333  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries },
182334  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_RAM_ID,
182335  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_INJECT_TYPE,
182336  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_ECC_TYPE,
182337  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
182338  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries },
182339  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
182340  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
182341  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
182342  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
182343  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries },
182344  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_RAM_ID,
182345  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
182346  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
182347  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182348  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries },
182349  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
182350  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
182351  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
182352  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
182353  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries },
182354  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_RAM_ID,
182355  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_INJECT_TYPE,
182356  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_ECC_TYPE,
182357  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
182358  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries },
182359  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_RAM_ID,
182360  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_INJECT_TYPE,
182361  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_ECC_TYPE,
182362  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
182363  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries },
182364  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
182365  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
182366  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
182367  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
182368  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries },
182369  { SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_RAM_ID,
182370  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_INJECT_TYPE,
182371  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_ECC_TYPE,
182372  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
182373  SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries },
182374  { SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_RAM_ID,
182375  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_INJECT_TYPE,
182376  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_ECC_TYPE,
182377  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_MAX_NUM_CHECKERS,
182378  SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_groupEntries },
182379 };
182380 
182385 static const SDL_RAMIdEntry_t SDL_VPAC0_VISS_ECC_AGGR_RamIdTable[SDL_VPAC0_VISS_ECC_AGGR_NUM_RAMS] =
182386 {
182387  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_RAM_ID,
182388  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_INJECT_TYPE,
182389  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM0_ECC_TYPE,
182390  0u,
182391  NULL },
182392  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_RAM_ID,
182393  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_INJECT_TYPE,
182394  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT1_RAM_INTF_RAM1_ECC_TYPE,
182395  0u,
182396  NULL },
182397  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_RAM_ID,
182398  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_INJECT_TYPE,
182399  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM0_ECC_TYPE,
182400  0u,
182401  NULL },
182402  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_RAM_ID,
182403  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_INJECT_TYPE,
182404  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT2_RAM_INTF_RAM1_ECC_TYPE,
182405  0u,
182406  NULL },
182407  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_RAM_ID,
182408  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_INJECT_TYPE,
182409  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM0_ECC_TYPE,
182410  0u,
182411  NULL },
182412  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_RAM_ID,
182413  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_INJECT_TYPE,
182414  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LUT3_RAM_INTF_RAM1_ECC_TYPE,
182415  0u,
182416  NULL },
182417  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_RAM_ID,
182418  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_INJECT_TYPE,
182419  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM0_ECC_TYPE,
182420  0u,
182421  NULL },
182422  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_RAM_ID,
182423  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_INJECT_TYPE,
182424  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_WDR_LUT_RAM_INTF_RAM1_ECC_TYPE,
182425  0u,
182426  NULL },
182427  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_RAM_ID,
182428  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_INJECT_TYPE,
182429  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_DPC_DPC_LUT_RAM_INTF_RAM0_ECC_TYPE,
182430  0u,
182431  NULL },
182432  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_RAM_ID,
182433  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_INJECT_TYPE,
182434  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_LSC_RAM_INTF_RAM0_ECC_TYPE,
182435  0u,
182436  NULL },
182437  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_RAM_ID,
182438  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_INJECT_TYPE,
182439  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM0_ECC_TYPE,
182440  0u,
182441  NULL },
182442  { SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_RAM_ID,
182443  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_INJECT_TYPE,
182444  SDL_VPAC0_VISS_ECC_AGGR_VISS_RAWFE_H3A_LUT_RAM_INTF_RAM1_ECC_TYPE,
182445  0u,
182446  NULL },
182447  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_RAM_ID,
182448  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_INJECT_TYPE,
182449  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM0_RAMECC_ECC_TYPE,
182450  0u,
182451  NULL },
182452  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_RAM_ID,
182453  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_INJECT_TYPE,
182454  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM1_RAMECC_ECC_TYPE,
182455  0u,
182456  NULL },
182457  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_RAM_ID,
182458  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_INJECT_TYPE,
182459  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM2_RAMECC_ECC_TYPE,
182460  0u,
182461  NULL },
182462  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_RAM_ID,
182463  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_INJECT_TYPE,
182464  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM3_RAMECC_ECC_TYPE,
182465  0u,
182466  NULL },
182467  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_RAM_ID,
182468  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_INJECT_TYPE,
182469  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM4_RAMECC_ECC_TYPE,
182470  0u,
182471  NULL },
182472  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_RAM_ID,
182473  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_INJECT_TYPE,
182474  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM5_RAMECC_ECC_TYPE,
182475  0u,
182476  NULL },
182477  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_RAM_ID,
182478  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_INJECT_TYPE,
182479  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM6_RAMECC_ECC_TYPE,
182480  0u,
182481  NULL },
182482  { SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_RAM_ID,
182483  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_INJECT_TYPE,
182484  SDL_VPAC0_VISS_ECC_AGGR_VPAC_VISS_K3_GLBCE_TOP_STAT_MEM7_RAMECC_ECC_TYPE,
182485  0u,
182486  NULL },
182487  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_RAM_ID,
182488  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_INJECT_TYPE,
182489  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK0_MEMECC_ECC_TYPE,
182490  0u,
182491  NULL },
182492  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_RAM_ID,
182493  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_INJECT_TYPE,
182494  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_HIST_BANK1_MEMECC_ECC_TYPE,
182495  0u,
182496  NULL },
182497  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_RAM_ID,
182498  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_INJECT_TYPE,
182499  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK0_MEMECC_ECC_TYPE,
182500  0u,
182501  NULL },
182502  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_RAM_ID,
182503  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_INJECT_TYPE,
182504  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX0_BANK1_MEMECC_ECC_TYPE,
182505  0u,
182506  NULL },
182507  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_RAM_ID,
182508  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_INJECT_TYPE,
182509  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK0_MEMECC_ECC_TYPE,
182510  0u,
182511  NULL },
182512  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_RAM_ID,
182513  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_INJECT_TYPE,
182514  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX1_BANK1_MEMECC_ECC_TYPE,
182515  0u,
182516  NULL },
182517  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_RAM_ID,
182518  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_INJECT_TYPE,
182519  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK0_MEMECC_ECC_TYPE,
182520  0u,
182521  NULL },
182522  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_RAM_ID,
182523  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_INJECT_TYPE,
182524  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_CONTRAST_PIX2_BANK1_MEMECC_ECC_TYPE,
182525  0u,
182526  NULL },
182527  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_RAM_ID,
182528  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_INJECT_TYPE,
182529  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK0_MEMECC_ECC_TYPE,
182530  0u,
182531  NULL },
182532  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_RAM_ID,
182533  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_INJECT_TYPE,
182534  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_Y8R8_BANK1_MEMECC_ECC_TYPE,
182535  0u,
182536  NULL },
182537  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_RAM_ID,
182538  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_INJECT_TYPE,
182539  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK0_MEMECC_ECC_TYPE,
182540  0u,
182541  NULL },
182542  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_RAM_ID,
182543  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_INJECT_TYPE,
182544  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_UV8G8_BANK1_MEMECC_ECC_TYPE,
182545  0u,
182546  NULL },
182547  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_RAM_ID,
182548  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_INJECT_TYPE,
182549  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK0_MEMECC_ECC_TYPE,
182550  0u,
182551  NULL },
182552  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_RAM_ID,
182553  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_INJECT_TYPE,
182554  SDL_VPAC0_VISS_ECC_AGGR_VISS_FLEXCC_MEMWRAP_S8B8_BANK1_MEMECC_ECC_TYPE,
182555  0u,
182556  NULL },
182557  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_RAM_ID,
182558  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_INJECT_TYPE,
182559  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_0_RAMECC_ECC_TYPE,
182560  0u,
182561  NULL },
182562  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_RAM_ID,
182563  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_INJECT_TYPE,
182564  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_LUT_1_RAMECC_ECC_TYPE,
182565  0u,
182566  NULL },
182567  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_RAM_ID,
182568  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_INJECT_TYPE,
182569  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_0_RAMECC_ECC_TYPE,
182570  0u,
182571  NULL },
182572  { SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_RAM_ID,
182573  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_INJECT_TYPE,
182574  SDL_VPAC0_VISS_ECC_AGGR_VISS_FCP_EELUT_1_RAMECC_ECC_TYPE,
182575  0u,
182576  NULL },
182577 };
182578 
182583 static const SDL_RAMIdEntry_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
182584 {
182585  { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
182586  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
182587  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
182588  0u,
182589  NULL },
182590  { SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
182591  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
182592  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
182593  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
182594  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
182595 };
182596 
182601 static const SDL_RAMIdEntry_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS] =
182602 {
182603  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_RAM_ID,
182604  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_INJECT_TYPE,
182605  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM0_ECC_ECC_TYPE,
182606  0u,
182607  NULL },
182608  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_RAM_ID,
182609  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_INJECT_TYPE,
182610  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKTRAM1_ECC_ECC_TYPE,
182611  0u,
182612  NULL },
182613  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_RAM_ID,
182614  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_INJECT_TYPE,
182615  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_PKA_PROG_RAM_ECC_ECC_TYPE,
182616  0u,
182617  NULL },
182618  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
182619  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
182620  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
182621  0u,
182622  NULL },
182623  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
182624  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
182625  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
182626  0u,
182627  NULL },
182628  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
182629  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
182630  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
182631  0u,
182632  NULL },
182633  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
182634  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
182635  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
182636  0u,
182637  NULL },
182638  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
182639  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
182640  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
182641  0u,
182642  NULL },
182643  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
182644  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
182645  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
182646  0u,
182647  NULL },
182648  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
182649  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
182650  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
182651  0u,
182652  NULL },
182653  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
182654  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
182655  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
182656  0u,
182657  NULL },
182658  { SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
182659  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
182660  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_SA2_UL_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
182661  0u,
182662  NULL },
182663 };
182664 
182669 static const SDL_RAMIdEntry_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
182670 {
182671  { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
182672  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
182673  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
182674  0u,
182675  NULL },
182676  { SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
182677  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
182678  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
182679  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
182680  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
182681 };
182682 
182687 static const SDL_RAMIdEntry_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS] =
182688 {
182689  { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID,
182690  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_INJECT_TYPE,
182691  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ECC_TYPE,
182692  0u,
182693  NULL },
182694 };
182695 
182700 static const SDL_RAMIdEntry_t SDL_MCU_FSS0_0_RamIdTable[SDL_MCU_FSS0_0_NUM_RAMS] =
182701 {
182702  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_RAM_ID,
182703  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_INJECT_TYPE,
182704  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_ECC_TYPE,
182705  0u,
182706  NULL },
182707  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_RAM_ID,
182708  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_INJECT_TYPE,
182709  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_ECC_TYPE,
182710  0u,
182711  NULL },
182712  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_RAM_ID,
182713  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_INJECT_TYPE,
182714  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_ECC_TYPE,
182715  0u,
182716  NULL },
182717  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_RAM_ID,
182718  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_INJECT_TYPE,
182719  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_ECC_TYPE,
182720  0u,
182721  NULL },
182722  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_RAM_ID,
182723  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_INJECT_TYPE,
182724  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_ECC_TYPE,
182725  0u,
182726  NULL },
182727  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_RAM_ID,
182728  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_INJECT_TYPE,
182729  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_ECC_TYPE,
182730  0u,
182731  NULL },
182732  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RX_FIFO_RAM_ID,
182733  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RX_FIFO_INJECT_TYPE,
182734  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_RX_FIFO_ECC_TYPE,
182735  0u,
182736  NULL },
182737  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_RAM_ID,
182738  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_INJECT_TYPE,
182739  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_ECC_TYPE,
182740  0u,
182741  NULL },
182742  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_RAM_ID,
182743  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_INJECT_TYPE,
182744  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_ECC_TYPE,
182745  0u,
182746  NULL },
182747  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_RAM_ID,
182748  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_INJECT_TYPE,
182749  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_ECC_TYPE,
182750  0u,
182751  NULL },
182752  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_RAM_ID,
182753  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_INJECT_TYPE,
182754  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_ECC_TYPE,
182755  0u,
182756  NULL },
182757  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_RAM_ID,
182758  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_INJECT_TYPE,
182759  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_ECC_TYPE,
182760  0u,
182761  NULL },
182762  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_RAM_ID,
182763  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_INJECT_TYPE,
182764  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_ECC_TYPE,
182765  0u,
182766  NULL },
182767  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AR_FIFO_RAM_ID,
182768  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AR_FIFO_INJECT_TYPE,
182769  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_AR_FIFO_ECC_TYPE,
182770  0u,
182771  NULL },
182772  { SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_RAM_ID,
182773  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_INJECT_TYPE,
182774  SDL_MCU_FSS0_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_ECC_TYPE,
182775  0u,
182776  NULL },
182777 };
182778 
182783 static const SDL_RAMIdEntry_t SDL_MCU_FSS0_1_RamIdTable[SDL_MCU_FSS0_1_NUM_RAMS] =
182784 {
182785  { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
182786  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
182787  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
182788  0u,
182789  NULL },
182790 };
182791 
182796 static const SDL_RAMIdEntry_t SDL_MCU_FSS0_2_RamIdTable[SDL_MCU_FSS0_2_NUM_RAMS] =
182797 {
182798  { SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_RAM_ID,
182799  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
182800  SDL_MCU_FSS0_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
182801  0u,
182802  NULL },
182803 };
182804 
182809 static const SDL_RAMIdEntry_t SDL_MCU_CPSW0_0_RamIdTable[SDL_MCU_CPSW0_0_NUM_RAMS + 17] =
182810 {
182811  { SDL_ECC_RAMID_INVALID,
182812  0u,
182813  0u,
182814  0u,
182815  NULL },
182816  { SDL_ECC_RAMID_INVALID,
182817  0u,
182818  0u,
182819  0u,
182820  NULL },
182821  { SDL_ECC_RAMID_INVALID,
182822  0u,
182823  0u,
182824  0u,
182825  NULL },
182826  { SDL_MCU_CPSW0_P1_RX_FIFO_RAM_ID,
182827  SDL_MCU_CPSW0_P1_RX_FIFO_INJECT_TYPE,
182828  SDL_MCU_CPSW0_P1_RX_FIFO_ECC_TYPE,
182829  0u,
182830  NULL },
182831  { SDL_MCU_CPSW0_P1_TX_FIFO_RAM_ID,
182832  SDL_MCU_CPSW0_P1_TX_FIFO_INJECT_TYPE,
182833  SDL_MCU_CPSW0_P1_TX_FIFO_ECC_TYPE,
182834  0u,
182835  NULL },
182836  { SDL_ECC_RAMID_INVALID,
182837  0u,
182838  0u,
182839  0u,
182840  NULL },
182841  { SDL_ECC_RAMID_INVALID,
182842  0u,
182843  0u,
182844  0u,
182845  NULL },
182846  { SDL_ECC_RAMID_INVALID,
182847  0u,
182848  0u,
182849  0u,
182850  NULL },
182851  { SDL_ECC_RAMID_INVALID,
182852  0u,
182853  0u,
182854  0u,
182855  NULL },
182856  { SDL_ECC_RAMID_INVALID,
182857  0u,
182858  0u,
182859  0u,
182860  NULL },
182861  { SDL_ECC_RAMID_INVALID,
182862  0u,
182863  0u,
182864  0u,
182865  NULL },
182866  { SDL_ECC_RAMID_INVALID,
182867  0u,
182868  0u,
182869  0u,
182870  NULL },
182871  { SDL_ECC_RAMID_INVALID,
182872  0u,
182873  0u,
182874  0u,
182875  NULL },
182876  { SDL_ECC_RAMID_INVALID,
182877  0u,
182878  0u,
182879  0u,
182880  NULL },
182881  { SDL_ECC_RAMID_INVALID,
182882  0u,
182883  0u,
182884  0u,
182885  NULL },
182886  { SDL_ECC_RAMID_INVALID,
182887  0u,
182888  0u,
182889  0u,
182890  NULL },
182891  { SDL_ECC_RAMID_INVALID,
182892  0u,
182893  0u,
182894  0u,
182895  NULL },
182896  { SDL_ECC_RAMID_INVALID,
182897  0u,
182898  0u,
182899  0u,
182900  NULL },
182901  { SDL_ECC_RAMID_INVALID,
182902  0u,
182903  0u,
182904  0u,
182905  NULL },
182906  { SDL_MCU_CPSW0_EST_RAM_RAM_ID,
182907  SDL_MCU_CPSW0_EST_RAM_INJECT_TYPE,
182908  SDL_MCU_CPSW0_EST_RAM_ECC_TYPE,
182909  0u,
182910  NULL },
182911 };
182916 static const SDL_RAMIdEntry_t SDL_WKUP_DMSC0_0_RamIdTable[SDL_WKUP_DMSC0_0_NUM_RAMS] =
182917 {
182918  { SDL_WKUP_DMSC0_IRAM_RAMECC_RAM_ID,
182919  SDL_WKUP_DMSC0_IRAM_RAMECC_INJECT_TYPE,
182920  SDL_WKUP_DMSC0_IRAM_RAMECC_ECC_TYPE,
182921  0u,
182922  NULL },
182923  { SDL_WKUP_DMSC0_IDRAM0_RAMECC_RAM_ID,
182924  SDL_WKUP_DMSC0_IDRAM0_RAMECC_INJECT_TYPE,
182925  SDL_WKUP_DMSC0_IDRAM0_RAMECC_ECC_TYPE,
182926  0u,
182927  NULL },
182928  { SDL_WKUP_DMSC0_IDRAM1_RAMECC_RAM_ID,
182929  SDL_WKUP_DMSC0_IDRAM1_RAMECC_INJECT_TYPE,
182930  SDL_WKUP_DMSC0_IDRAM1_RAMECC_ECC_TYPE,
182931  0u,
182932  NULL },
182933  { SDL_WKUP_DMSC0_IRAM_BUSECC_RAM_ID,
182934  SDL_WKUP_DMSC0_IRAM_BUSECC_INJECT_TYPE,
182935  SDL_WKUP_DMSC0_IRAM_BUSECC_ECC_TYPE,
182936  SDL_WKUP_DMSC0_IRAM_BUSECC_MAX_NUM_CHECKERS,
182937  SDL_WKUP_DMSC0_IRAM_BUSECC_groupEntries },
182938  { SDL_WKUP_DMSC0_IDRAM0_BUSECC_RAM_ID,
182939  SDL_WKUP_DMSC0_IDRAM0_BUSECC_INJECT_TYPE,
182940  SDL_WKUP_DMSC0_IDRAM0_BUSECC_ECC_TYPE,
182941  SDL_WKUP_DMSC0_IDRAM0_BUSECC_MAX_NUM_CHECKERS,
182942  SDL_WKUP_DMSC0_IDRAM0_BUSECC_groupEntries },
182943  { SDL_WKUP_DMSC0_IDRAM1_BUSECC_RAM_ID,
182944  SDL_WKUP_DMSC0_IDRAM1_BUSECC_INJECT_TYPE,
182945  SDL_WKUP_DMSC0_IDRAM1_BUSECC_ECC_TYPE,
182946  SDL_WKUP_DMSC0_IDRAM1_BUSECC_MAX_NUM_CHECKERS,
182947  SDL_WKUP_DMSC0_IDRAM1_BUSECC_groupEntries },
182948  { SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_RAM_ID,
182949  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_INJECT_TYPE,
182950  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_ECC_TYPE,
182951  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
182952  SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_groupEntries },
182953  { SDL_WKUP_DMSC0_IM_RAMECC_RAM_ID,
182954  SDL_WKUP_DMSC0_IM_RAMECC_INJECT_TYPE,
182955  SDL_WKUP_DMSC0_IM_RAMECC_ECC_TYPE,
182956  0u,
182957  NULL },
182958  { SDL_WKUP_DMSC0_SR_RAMECC_RAM_ID,
182959  SDL_WKUP_DMSC0_SR_RAMECC_INJECT_TYPE,
182960  SDL_WKUP_DMSC0_SR_RAMECC_ECC_TYPE,
182961  0u,
182962  NULL },
182963  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_RAM_ID,
182964  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_INJECT_TYPE,
182965  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_ECC_TYPE,
182966  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
182967  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_groupEntries },
182968  { SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_RAM_ID,
182969  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_INJECT_TYPE,
182970  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_ECC_TYPE,
182971  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
182972  SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_groupEntries },
182973  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_RAM_ID,
182974  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_INJECT_TYPE,
182975  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_ECC_TYPE,
182976  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
182977  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries },
182978  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_RAM_ID,
182979  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_INJECT_TYPE,
182980  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_ECC_TYPE,
182981  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
182982  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries },
182983  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_RAM_ID,
182984  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_INJECT_TYPE,
182985  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_ECC_TYPE,
182986  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
182987  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries },
182988  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_RAM_ID,
182989  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_INJECT_TYPE,
182990  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_ECC_TYPE,
182991  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS,
182992  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries },
182993  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_RAM_ID,
182994  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_INJECT_TYPE,
182995  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_ECC_TYPE,
182996  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS,
182997  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries },
182998  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_RAM_ID,
182999  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_INJECT_TYPE,
183000  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_ECC_TYPE,
183001  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS,
183002  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries },
183003  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_RAM_ID,
183004  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_INJECT_TYPE,
183005  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_ECC_TYPE,
183006  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS,
183007  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries },
183008  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_RAM_ID,
183009  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_INJECT_TYPE,
183010  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_ECC_TYPE,
183011  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS,
183012  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries },
183013  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_RAM_ID,
183014  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_INJECT_TYPE,
183015  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_ECC_TYPE,
183016  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS,
183017  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries },
183018  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_RAM_ID,
183019  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_INJECT_TYPE,
183020  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_ECC_TYPE,
183021  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS,
183022  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries },
183023  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_RAM_ID,
183024  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_INJECT_TYPE,
183025  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_ECC_TYPE,
183026  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS,
183027  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries },
183028  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_RAM_ID,
183029  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_INJECT_TYPE,
183030  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_ECC_TYPE,
183031  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS,
183032  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries },
183033  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
183034  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
183035  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
183036  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
183037  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries },
183038  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
183039  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
183040  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
183041  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
183042  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries },
183043  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
183044  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
183045  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
183046  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
183047  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_groupEntries },
183048  { SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_RAM_ID,
183049  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
183050  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
183051  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
183052  SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_groupEntries },
183053  { SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_RAM_ID,
183054  SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_INJECT_TYPE,
183055  SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_ECC_TYPE,
183056  SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
183057  SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_groupEntries },
183058  { SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_RAM_ID,
183059  SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_INJECT_TYPE,
183060  SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_ECC_TYPE,
183061  SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
183062  SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries },
183063  { SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_RAM_ID,
183064  SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_INJECT_TYPE,
183065  SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_ECC_TYPE,
183066  SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
183067  SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_groupEntries },
183068  { SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_RAM_ID,
183069  SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_INJECT_TYPE,
183070  SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_ECC_TYPE,
183071  SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
183072  SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_groupEntries },
183073  { SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_RAM_ID,
183074  SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_INJECT_TYPE,
183075  SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_ECC_TYPE,
183076  SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
183077  SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_groupEntries },
183078  { SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
183079  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
183080  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
183081  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183082  SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
183083  { SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
183084  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
183085  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
183086  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183087  SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries },
183088  { SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_RAM_ID,
183089  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_INJECT_TYPE,
183090  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_ECC_TYPE,
183091  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183092  SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_groupEntries },
183093  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
183094  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
183095  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
183096  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183097  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
183098  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
183099  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
183100  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
183101  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183102  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
183103  { SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_RAM_ID,
183104  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_INJECT_TYPE,
183105  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_ECC_TYPE,
183106  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
183107  SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries },
183108  { SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
183109  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
183110  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
183111  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183112  SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_groupEntries },
183113  { SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_RAM_ID,
183114  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_INJECT_TYPE,
183115  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_ECC_TYPE,
183116  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183117  SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_groupEntries },
183118  { SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_RAM_ID,
183119  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
183120  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
183121  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183122  SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_groupEntries },
183123  { SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
183124  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
183125  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
183126  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183127  SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries },
183128  { SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_RAM_ID,
183129  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_INJECT_TYPE,
183130  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_ECC_TYPE,
183131  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183132  SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_groupEntries },
183133  { SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_RAM_ID,
183134  SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_INJECT_TYPE,
183135  SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_ECC_TYPE,
183136  SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
183137  SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_groupEntries },
183138  { SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_RAM_ID,
183139  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
183140  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_ECC_TYPE,
183141  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183142  SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_groupEntries },
183143  { SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_RAM_ID,
183144  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
183145  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_ECC_TYPE,
183146  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183147  SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_groupEntries },
183148  { SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
183149  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
183150  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
183151  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
183152  SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries },
183153 };
183154 
183159 static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_10_RamIdTable[SDL_COMPUTE_CLUSTER0_10_NUM_RAMS] =
183160 {
183161  { SDL_COMPUTE_CLUSTER0_ICB_RAMECC_RAM_ID,
183162  SDL_COMPUTE_CLUSTER0_ICB_RAMECC_INJECT_TYPE,
183163  SDL_COMPUTE_CLUSTER0_ICB_RAMECC_ECC_TYPE,
183164  0u,
183165  NULL },
183166  { SDL_COMPUTE_CLUSTER0_ITE_RAMECC_RAM_ID,
183167  SDL_COMPUTE_CLUSTER0_ITE_RAMECC_INJECT_TYPE,
183168  SDL_COMPUTE_CLUSTER0_ITE_RAMECC_ECC_TYPE,
183169  0u,
183170  NULL },
183171  { SDL_COMPUTE_CLUSTER0_LPI_RAMECC_RAM_ID,
183172  SDL_COMPUTE_CLUSTER0_LPI_RAMECC_INJECT_TYPE,
183173  SDL_COMPUTE_CLUSTER0_LPI_RAMECC_ECC_TYPE,
183174  0u,
183175  NULL },
183176  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_RAM_ID,
183177  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_INJECT_TYPE,
183178  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_ECC_TYPE,
183179  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS,
183180  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_groupEntries },
183181  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
183182  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
183183  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
183184  0u,
183185  NULL },
183186  { SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_RAM_ID,
183187  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_INJECT_TYPE,
183188  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_ECC_TYPE,
183189  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS,
183190  SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_groupEntries },
183191 };
183192 
183197 static const SDL_RAMIdEntry_t SDL_CPSW0_0_RamIdTable[SDL_CPSW0_0_NUM_RAMS] =
183198 {
183199  { SDL_CPSW0_ALE_RAM_RAM_ID,
183200  SDL_CPSW0_ALE_RAM_INJECT_TYPE,
183201  SDL_CPSW0_ALE_RAM_ECC_TYPE,
183202  0u,
183203  NULL },
183204  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL1_RAM_ID,
183205  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL1_INJECT_TYPE,
183206  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL1_ECC_TYPE,
183207  0u,
183208  NULL },
183209  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL2_RAM_ID,
183210  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL2_INJECT_TYPE,
183211  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL2_ECC_TYPE,
183212  0u,
183213  NULL },
183214  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL3_RAM_ID,
183215  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL3_INJECT_TYPE,
183216  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL3_ECC_TYPE,
183217  0u,
183218  NULL },
183219  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL4_RAM_ID,
183220  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL4_INJECT_TYPE,
183221  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL4_ECC_TYPE,
183222  0u,
183223  NULL },
183224  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL5_RAM_ID,
183225  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL5_INJECT_TYPE,
183226  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL5_ECC_TYPE,
183227  0u,
183228  NULL },
183229  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL6_RAM_ID,
183230  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL6_INJECT_TYPE,
183231  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL6_ECC_TYPE,
183232  0u,
183233  NULL },
183234  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL7_RAM_ID,
183235  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL7_INJECT_TYPE,
183236  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL7_ECC_TYPE,
183237  0u,
183238  NULL },
183239  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL8_RAM_ID,
183240  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL8_INJECT_TYPE,
183241  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL8_ECC_TYPE,
183242  0u,
183243  NULL },
183244  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL9_RAM_ID,
183245  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL9_INJECT_TYPE,
183246  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL9_ECC_TYPE,
183247  0u,
183248  NULL },
183249  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL10_RAM_ID,
183250  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL10_INJECT_TYPE,
183251  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL10_ECC_TYPE,
183252  0u,
183253  NULL },
183254  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL11_RAM_ID,
183255  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL11_INJECT_TYPE,
183256  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL11_ECC_TYPE,
183257  0u,
183258  NULL },
183259  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL12_RAM_ID,
183260  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL12_INJECT_TYPE,
183261  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL12_ECC_TYPE,
183262  0u,
183263  NULL },
183264  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL13_RAM_ID,
183265  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL13_INJECT_TYPE,
183266  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL13_ECC_TYPE,
183267  0u,
183268  NULL },
183269  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL14_RAM_ID,
183270  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL14_INJECT_TYPE,
183271  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL14_ECC_TYPE,
183272  0u,
183273  NULL },
183274  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL15_RAM_ID,
183275  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL15_INJECT_TYPE,
183276  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL15_ECC_TYPE,
183277  0u,
183278  NULL },
183279  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL16_RAM_ID,
183280  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL16_INJECT_TYPE,
183281  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL16_ECC_TYPE,
183282  0u,
183283  NULL },
183284  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL17_RAM_ID,
183285  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL17_INJECT_TYPE,
183286  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL17_ECC_TYPE,
183287  0u,
183288  NULL },
183289  { SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL18_RAM_ID,
183290  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL18_INJECT_TYPE,
183291  SDL_CPSW0_CPSW_9XU_CORE_ECC_ECC_CTRL18_ECC_TYPE,
183292  0u,
183293  NULL },
183294  { SDL_CPSW0_EST_RAM_RAM_ID,
183295  SDL_CPSW0_EST_RAM_INJECT_TYPE,
183296  SDL_CPSW0_EST_RAM_ECC_TYPE,
183297  0u,
183298  NULL },
183299 };
183300 
183301 
183302 /* Max entries based on max mem type */
183303 #define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES (SDL_NAVSS0_UDMASS_ECC_AGGR0+1u)
183304 
183305 #define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR - \
183306  SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)
183307 
183308 /* Max entries based on max mem type */
183309 #define SDL_ECC_AGGREGATOR_MAX_ENTRIES (SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES + \
183310  SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES)
183311 
183316 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES] =
183317 {
183318  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
183319  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE1_ECC_AGGR_BASE)),
183320  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ADC0_ECC_REGS_BASE)),
183321  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ADC1_ECC_REGS_BASE)),
183322  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_CPSW0_ECC_BASE)),
183323  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_HPB_ECC_AGGR_BASE)),
183324  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_OSPI0_ECC_AGGR_BASE)),
183325  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_OSPI1_ECC_AGGR_BASE)),
183326  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE)),
183327  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE)),
183328  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_1MB0_ECC_AGGR_REGS_BASE)),
183329  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_NAVSS0_ECCAGGR0_BASE)),
183330  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAM2KECC0_ECC_AGGR_BASE)),
183331  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_CBASS_ECC_AGGR0_REGS_BASE)),
183332  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_AGGR_BASE)),
183333  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_AGGR_BASE)),
183334  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN2_ECC_AGGR_BASE)),
183335  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN3_ECC_AGGR_BASE)),
183336  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN4_ECC_AGGR_BASE)),
183337  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN5_ECC_AGGR_BASE)),
183338  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN6_ECC_AGGR_BASE)),
183339  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN7_ECC_AGGR_BASE)),
183340  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN8_ECC_AGGR_BASE)),
183341  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN9_ECC_AGGR_BASE)),
183342  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN10_ECC_AGGR_BASE)),
183343  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN11_ECC_AGGR_BASE)),
183344  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN12_ECC_AGGR_BASE)),
183345  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN13_ECC_AGGR_BASE)),
183346  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MSRAM_512K0_ECC_AGGR_REGS_BASE)),
183347  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE0_CORE_ECC_AGGR0_BASE)),
183348  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE0_CORE_ECC_AGGR1_BASE)),
183349  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE1_CORE_ECC_AGGR0_BASE)),
183350  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE1_CORE_ECC_AGGR1_BASE)),
183351  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE2_CORE_ECC_AGGR0_BASE)),
183352  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE2_CORE_ECC_AGGR1_BASE)),
183353  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE3_CORE_ECC_AGGR0_BASE)),
183354  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PCIE3_CORE_ECC_AGGR1_BASE)),
183355  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_I3C0_S_ECC_AGGR_CFG_BASE)),
183356  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_I3C0_P_ECC_AGGR_CFG_BASE)),
183357  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_I3C0_P_ECC_AGGR_CFG_BASE)),
183358  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_I3C0_S_ECC_AGGR_CFG_BASE)),
183359  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_I3C1_P_ECC_AGGR_CFG_BASE)),
183360  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_I3C1_S_ECC_AGGR_CFG_BASE)),
183361  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PRU_ICSSG0_ECC_AGGR_BASE)),
183362  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PRU_ICSSG1_ECC_AGGR_BASE)),
183363  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CBASS_ECC_AGGR0_REGS_BASE)),
183364  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MAIN_RC_ECC_AGGR0_REGS_BASE)),
183365  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_NAVSS_NBSS_ECC_AGGR0_REGS_BASE)),
183366  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DMPAC0_ECC_AGGR_BASE)),
183367  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MAIN_HC_ECC_AGGR0_REGS_BASE)),
183368  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_ECC_AGGR_BASE)),
183369  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_VISS_ECC_AGGR_BASE)),
183370  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_VPAC0_LDC_ECC_AGGR_BASE)),
183371  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_R5FSS0_CORE0_ECC_AGGR_BASE)),
183372  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_R5FSS1_CORE0_ECC_AGGR_BASE)),
183373  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_R5FSS0_CORE1_ECC_AGGR_BASE)),
183374  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_R5FSS1_CORE1_ECC_AGGR_BASE)),
183375  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_NAVSS_VIRTSS_ECC_AGGR0_REGS_BASE)),
183376  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_SA2_UL0_ECC_AGGR_BASE)),
183377  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_SA2_UL0_ECC_AGGR_BASE)),
183378  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MLB0_MLBDIM_WRAP_ECC_AGGR_VBP_BASE)),
183379  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MAIN_AC_ECC_AGGR0_REGS_BASE)),
183380  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_VTM0_ECCAGGR_CFG_BASE)),
183381  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_RXMEM_BASE)),
183382  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD0_ECC_AGGR_TXMEM_BASE)),
183383  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_RXMEM_BASE)),
183384  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD1_ECC_AGGR_TXMEM_BASE)),
183385  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_RXMEM_BASE)),
183386  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MMCSD2_ECC_AGGR_TXMEM_BASE)),
183387  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG_BASE)),
183388  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG_BASE)),
183389  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_EDP0_MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG_BASE)),
183390  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_UFS0_HCLK_ECC_AGGR_CFG_BASE)),
183391  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF0_ECC_AGGR_CFG_BASE)),
183392  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_RX_IF1_ECC_AGGR_CFG_BASE)),
183393  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_NAVSS0_ECCAGGR0_REGS_BASE)),
183394  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB0_ECC_AGGR_BASE)),
183395  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_USB1_ECC_AGGR_BASE)),
183396  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_NAVSS0_VIRTSS_ECCAGGR_CFG_BASE)),
183397  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_NAVSS0_NBSS_CFG_ECCAGGR0_REGS_BASE)),
183398  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM1_ECC_AGGR0_REGS_BASE)),
183399  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM1_ECC_AGGR1_REGS_BASE)),
183400  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM0_ECC_AGGR0_REGS_BASE)),
183401  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM0_ECC_AGGR1_REGS_BASE)),
183402  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_TX_IF0_ECC_AGGR_CFG_BASE)),
183403  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CSI_TX_IF0_ECC_AGGR_BYTE_CFG_BASE)),
183404  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_WKUP_CBASS_ECC_AGGR0_REGS_BASE)),
183405  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_DSS_DSI0_DSI_TOP_ECC_AGGR_SYS_CFG_BASE)),
183406  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_NAVSS0_UDMASS_ECCAGGR0_BASE)),
183407  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PDMA5_REGS_BASE)),
183408  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)),
183409  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_NAVSS0_UDMASS_ECCAGGR0_CFG_REGS_BASE)),
183410 
183411 };
183412 
183413 /* Addresses will be cast to SDL_ecc_aggrRegs after RAT translation */
183414 uint64_t static const SDL_ECC_aggrHighBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES] =
183415 {
183416  (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_BASE,
183417  (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_BASE,
183418  (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_BASE,
183419  (uint64_t)SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_BASE,
183420  (uint64_t)SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_BASE,
183421  (uint64_t)SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_BASE,
183422  (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_VBUS_BASE,
183423  (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_CTL_BASE,
183424  (uint64_t)SDL_COMPUTE_CLUSTER0_ECC_AGGR_CFG_BASE,
183425  (uint64_t)SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BASE,
183426 };
183427 
183428 SDL_ecc_aggrRegs * SDL_ECC_aggrHighBaseAddressTableTrans[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES];
183429 
183432 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
183433 {
183434  // Index: SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0)
183435  {
183436  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
183437  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
183438  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183439  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MemEntries,
183440  SDL_ESM_INST_MCU_ESM0,
183441  SDL_ESM_MCU_R5_CORE0_SEC_INT, // ESM event Id - SEC
183442  SDL_ESM_MCU_R5_CORE0_DED_INT, // ESM event Id - DED
183443  },
183444  // Index: SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1)
183445  {
183446  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
183447  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
183448  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183449  SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MemEntries,
183450  SDL_ESM_INST_MCU_ESM0,
183451  SDL_ESM_MCU_R5_CORE1_SEC_INT,
183452  SDL_ESM_MCU_R5_CORE1_DED_INT,
183453  },
183454  // Index: SDL_ECC_MEMTYPE_MCU_ADC0 (SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR) (2)
183455  {
183456  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS,
183457  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable,
183458  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183459  SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries,
183460  SDL_ESM_INST_MCU_ESM0,
183461  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ADC0_ECC_CORRECTED_ERR_LEVEL_0,
183462  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ADC0_ECC_UNCORRECTED_ERR_LEVEL_0,
183463  },
183464  // Index: SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR (3)
183465  {
183466  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS,
183467  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable,
183468  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183469  SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries,
183470  SDL_ESM_INST_MCU_ESM0,
183471  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ADC1_ECC_CORRECTED_ERR_LEVEL_0,
183472  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ADC1_ECC_UNCORRECTED_ERR_LEVEL_0
183473  },
183474  // Index: SDL_ECC_MEMTYPE_MCU_CPSW0 (4)
183475  {
183476  0,
183477  NULL,
183478  0,
183479  NULL,
183480  0,
183481  0,
183482  0
183483  },
183484  // Index: SDL_ECC_MEMTYPE_MCU_FSS0_HPB0 (5)
183485  {
183486  0,
183487  NULL,
183488  0,
183489  NULL,
183490  0,
183491  0,
183492  0
183493  },
183494  // Index: SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0 (6)
183495  {
183496  0,
183497  NULL,
183498  0,
183499  NULL,
183500  0,
183501  0,
183502  0
183503  },
183504  // Index: SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1 (7)
183505  {
183506  0,
183507  NULL,
183508  0,
183509  NULL,
183510  0,
183511  0,
183512  0
183513  },
183514  // SDL_ECC_MEMTYPE_MCU_MCAN0 (8)
183515  {
183516  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183517  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183518  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183519  SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183520  SDL_ESM_INST_MCU_ESM0,
183521  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
183522  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
183523  },
183524  // Index: SDL_ECC_MEMTYPE_MCU_MCAN1 (9)
183525  {
183526  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183527  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183528  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183529  SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183530  SDL_ESM_INST_MCU_ESM0,
183531  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
183532  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
183533  },
183534  // Index: SDL_ECC_MEMTYPE_MCU_MSRAM0 (10)
183535  {
183536  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_NUM_RAMS,
183537  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RamIdTable,
183538  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183539  SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MemEntries,
183540  SDL_ESM_INST_MCU_ESM0,
183541  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_MSRAM_1MB0_ECC_CORR_LEVEL_0,
183542  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_MSRAM_1MB0_ECC_UNCORR_LEVEL_0
183543  },
183544  // Index: SDL_ECC_MEMTYPE_MCU_NAVSS0 (11u)
183545  {
183546  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS,
183547  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RamIdTable,
183548  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
183549  SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_MemEntries,
183550  SDL_ESM_INST_MCU_ESM0,
183551  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_NAVSS0_MODSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
183552  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_NAVSS0_MODSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
183553  },
183554  // Index: SDL_ECC_MEMTYPE_MCU_PSRAM0 (12u)
183555  {
183556  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_NUM_RAMS,
183557  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RamIdTable,
183558  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183559  SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_MemEntries,
183560  SDL_ESM_INST_MAIN_ESM0,
183561  SDLR_ESM0_ESM_LVL_EVENT_PSRAM2KECC0_ECC_CORR_LEVEL_0,
183562  SDLR_ESM0_ESM_LVL_EVENT_PSRAM2KECC0_ECC_UNCORR_LEVEL_0
183563  },
183564 
183565  // Index: SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0 (13u)
183566  {
183567  SDL_MCU_CBASS_ECC_AGGR0_NUM_RAMS,
183568  SDL_MCU_CBASS_ECC_AGGR0_RamIdTable,
183569  SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
183570  SDL_MCU_CBASS_ECC_AGGR0_MemEntries,
183571  SDL_ESM_INST_MCU_ESM0,
183572  SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT,
183573  SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT
183574  },
183575 
183576  // Index: SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (14u)
183577  {
183578  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183579  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183580  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183581  SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183582  SDL_ESM_INST_MAIN_ESM0,
183583  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
183584  SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
183585  },
183586  // Index: SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (15u)
183587  {
183588  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183589  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183590  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183591  SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183592  SDL_ESM_INST_MAIN_ESM0,
183593  SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
183594  SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
183595  },
183596  // Index: SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (16u)
183597  {
183598  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183599  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183600  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183601  SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183602  SDL_ESM_INST_MAIN_ESM0,
183603  SDLR_ESM0_ESM_LVL_EVENT_MCAN2_MCANSS_ECC_CORR_LVL_INT_0,
183604  SDLR_ESM0_ESM_LVL_EVENT_MCAN2_MCANSS_ECC_UNCORR_LVL_INT_0
183605  },
183606  // Index: SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (17u)
183607  {
183608  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183609  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183610  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183611  SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183612  SDL_ESM_INST_MAIN_ESM0,
183613  SDLR_ESM0_ESM_LVL_EVENT_MCAN3_MCANSS_ECC_CORR_LVL_INT_0,
183614  SDLR_ESM0_ESM_LVL_EVENT_MCAN3_MCANSS_ECC_UNCORR_LVL_INT_0
183615  },
183616  // Index: SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (18u)
183617  {
183618  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183619  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183620  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183621  SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183622  SDL_ESM_INST_MAIN_ESM0,
183623  SDLR_ESM0_ESM_LVL_EVENT_MCAN4_MCANSS_ECC_CORR_LVL_INT_0,
183624  SDLR_ESM0_ESM_LVL_EVENT_MCAN4_MCANSS_ECC_UNCORR_LVL_INT_0
183625  },
183626  // Index: SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (19u)
183627  {
183628  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183629  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183630  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183631  SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183632  SDL_ESM_INST_MAIN_ESM0,
183633  SDLR_ESM0_ESM_LVL_EVENT_MCAN5_MCANSS_ECC_CORR_LVL_INT_0,
183634  SDLR_ESM0_ESM_LVL_EVENT_MCAN5_MCANSS_ECC_UNCORR_LVL_INT_0
183635  },
183636  // Index: SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (20u)
183637  {
183638  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183639  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183640  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183641  SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183642  SDL_ESM_INST_MAIN_ESM0,
183643  SDLR_ESM0_ESM_LVL_EVENT_MCAN6_MCANSS_ECC_CORR_LVL_INT_0,
183644  SDLR_ESM0_ESM_LVL_EVENT_MCAN6_MCANSS_ECC_UNCORR_LVL_INT_0
183645  },
183646  // Index: SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (21u)
183647  {
183648  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183649  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183650  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183651  SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183652  SDL_ESM_INST_MAIN_ESM0,
183653  SDLR_ESM0_ESM_LVL_EVENT_MCAN7_MCANSS_ECC_CORR_LVL_INT_0,
183654  SDLR_ESM0_ESM_LVL_EVENT_MCAN7_MCANSS_ECC_UNCORR_LVL_INT_0
183655  },
183656  // Index: SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR (22u)
183657  {
183658  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183659  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183660  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183661  SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183662  SDL_ESM_INST_MAIN_ESM0,
183663  SDLR_ESM0_ESM_LVL_EVENT_MCAN8_MCANSS_ECC_CORR_LVL_INT_0,
183664  SDLR_ESM0_ESM_LVL_EVENT_MCAN8_MCANSS_ECC_UNCORR_LVL_INT_0
183665  },
183666  // Index: SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR (23u)
183667  {
183668  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183669  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183670  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183671  SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183672  SDL_ESM_INST_MAIN_ESM0,
183673  SDLR_ESM0_ESM_LVL_EVENT_MCAN9_MCANSS_ECC_CORR_LVL_INT_0,
183674  SDLR_ESM0_ESM_LVL_EVENT_MCAN9_MCANSS_ECC_UNCORR_LVL_INT_0
183675  },
183676  // Index: SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR (24u)
183677  {
183678  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183679  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183680  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183681  SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183682  SDL_ESM_INST_MAIN_ESM0,
183683  SDLR_ESM0_ESM_LVL_EVENT_MCAN10_MCANSS_ECC_CORR_LVL_INT_0,
183684  SDLR_ESM0_ESM_LVL_EVENT_MCAN10_MCANSS_ECC_UNCORR_LVL_INT_0
183685  },
183686  // Index: SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR (25u)
183687  {
183688  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183689  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183690  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183691  SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183692  SDL_ESM_INST_MAIN_ESM0,
183693  SDLR_ESM0_ESM_LVL_EVENT_MCAN11_MCANSS_ECC_CORR_LVL_INT_0,
183694  SDLR_ESM0_ESM_LVL_EVENT_MCAN11_MCANSS_ECC_UNCORR_LVL_INT_0
183695  },
183696  // Index: SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR (26u)
183697  {
183698  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183699  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183700  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183701  SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183702  SDL_ESM_INST_MAIN_ESM0,
183703  SDLR_ESM0_ESM_LVL_EVENT_MCAN12_MCANSS_ECC_CORR_LVL_INT_0,
183704  SDLR_ESM0_ESM_LVL_EVENT_MCAN12_MCANSS_ECC_UNCORR_LVL_INT_0
183705  },
183706  // Index: SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR (27u)
183707  {
183708  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
183709  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
183710  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183711  SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
183712  SDL_ESM_INST_MAIN_ESM0,
183713  SDLR_ESM0_ESM_LVL_EVENT_MCAN13_MCANSS_ECC_CORR_LVL_INT_0,
183714  SDLR_ESM0_ESM_LVL_EVENT_MCAN13_MCANSS_ECC_UNCORR_LVL_INT_0
183715  },
183716  // Index: SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR (28u)
183717  {
183718  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_NUM_RAMS,
183719  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RamIdTable,
183720  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183721  SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MemEntries,
183722  SDL_ESM_INST_MAIN_ESM0,
183723  SDLR_ESM0_ESM_LVL_EVENT_MSRAM16KX256E0_ECC_CORR_LEVEL_0,
183724  SDLR_ESM0_ESM_LVL_EVENT_MSRAM16KX256E0_ECC_UNCORR_LEVEL_0
183725  },
183726  // Index: SDL_PCIE0_ECC_AGGR_CORE_AXI_0 (29u)
183727  {
183728  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_NUM_RAMS,
183729  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RamIdTable,
183730  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES,
183731  SDL_PCIE0_ECC_AGGR_CORE_AXI_0_MemEntries,
183732  SDL_ESM_INST_MAIN_ESM0,
183733  SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_CORR_LEVEL_0,
183734  SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC0_UNCORR_LEVEL_0
183735  },
183736  // Index: SDL_PCIE0_ECC_AGGR_CORE_0 (30u)
183737  {
183738  SDL_PCIE0_ECC_AGGR_CORE_0_NUM_RAMS,
183739  SDL_PCIE0_ECC_AGGR_CORE_0_RamIdTable,
183740  SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES,
183741  SDL_PCIE0_ECC_AGGR_CORE_0_MemEntries,
183742  SDL_ESM_INST_MAIN_ESM0,
183743  0,
183744  SDLR_ESM0_ESM_LVL_EVENT_PCIE0_PCIE_ECC1_UNCORR_LEVEL_0
183745  },
183746  // Index: SDL_PCIE1_ECC_AGGR_CORE_AXI_0 (31u)
183747  {
183748  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_NUM_RAMS,
183749  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RamIdTable,
183750  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES,
183751  SDL_PCIE1_ECC_AGGR_CORE_AXI_0_MemEntries,
183752  SDL_ESM_INST_MAIN_ESM0,
183753  SDLR_ESM0_ESM_LVL_EVENT_PCIE1_PCIE_ECC0_CORR_LEVEL_0,
183754  SDLR_ESM0_ESM_LVL_EVENT_PCIE1_PCIE_ECC0_UNCORR_LEVEL_0
183755  },
183756  // Index: SDL_PCIE1_ECC_AGGR_CORE_0 (32u)
183757  {
183758  SDL_PCIE1_ECC_AGGR_CORE_0_NUM_RAMS,
183759  SDL_PCIE1_ECC_AGGR_CORE_0_RamIdTable,
183760  SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES,
183761  SDL_PCIE1_ECC_AGGR_CORE_0_MemEntries,
183762  SDL_ESM_INST_MAIN_ESM0,
183763  0,
183764  SDLR_ESM0_ESM_LVL_EVENT_PCIE1_PCIE_ECC1_UNCORR_LEVEL_0
183765  },
183766  // Index: SDL_PCIE2_ECC_AGGR_CORE_AXI_0 (33)
183767  {
183768  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_NUM_RAMS,
183769  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RamIdTable,
183770  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES,
183771  SDL_PCIE2_ECC_AGGR_CORE_AXI_0_MemEntries,
183772  SDL_ESM_INST_MAIN_ESM0,
183773  SDLR_ESM0_ESM_LVL_EVENT_PCIE2_PCIE_ECC0_CORR_LEVEL_0,
183774  SDLR_ESM0_ESM_LVL_EVENT_PCIE2_PCIE_ECC0_UNCORR_LEVEL_0
183775  },
183776  // Index: SDL_PCIE2_ECC_AGGR_CORE_0 (34)
183777  {
183778  SDL_PCIE2_ECC_AGGR_CORE_0_NUM_RAMS,
183779  SDL_PCIE2_ECC_AGGR_CORE_0_RamIdTable,
183780  SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES,
183781  SDL_PCIE2_ECC_AGGR_CORE_0_MemEntries,
183782  SDL_ESM_INST_MAIN_ESM0,
183783  0,
183784  SDLR_ESM0_ESM_LVL_EVENT_PCIE2_PCIE_ECC1_UNCORR_LEVEL_0
183785  },
183786  // Index: SDL_PCIE3_ECC_AGGR_CORE_AXI_0 (35)
183787  {
183788  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_NUM_RAMS,
183789  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RamIdTable,
183790  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES,
183791  SDL_PCIE3_ECC_AGGR_CORE_AXI_0_MemEntries,
183792  SDL_ESM_INST_MAIN_ESM0,
183793  SDLR_ESM0_ESM_LVL_EVENT_PCIE3_PCIE_ECC0_CORR_LEVEL_0,
183794  SDLR_ESM0_ESM_LVL_EVENT_PCIE3_PCIE_ECC0_UNCORR_LEVEL_0
183795  },
183796  // Index: SDL_PCIE3_ECC_AGGR_CORE_0 (36)
183797  {
183798  SDL_PCIE3_ECC_AGGR_CORE_0_NUM_RAMS,
183799  SDL_PCIE3_ECC_AGGR_CORE_0_RamIdTable,
183800  SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES,
183801  SDL_PCIE3_ECC_AGGR_CORE_0_MemEntries,
183802  SDL_ESM_INST_MAIN_ESM0,
183803  0,
183804  SDLR_ESM0_ESM_LVL_EVENT_PCIE3_PCIE_ECC1_UNCORR_LEVEL_0
183805  },
183806  // Index: SDL_I3C0_I3C_S_ECC_AGGR (37)
183807  {
183808  SDL_I3C0_I3C_S_ECC_AGGR_NUM_RAMS,
183809  SDL_I3C0_I3C_S_ECC_AGGR_RamIdTable,
183810  SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183811  SDL_I3C0_I3C_S_ECC_AGGR_MemEntries,
183812  SDL_ESM_INST_MAIN_ESM0,
183813  0,
183814  SDLR_ESM0_ESM_LVL_EVENT_I3C0_SCLK_ECC_UNCORR_LVL_0
183815  },
183816  // Index: SDL_I3C0_I3C_P_ECC_AGGR (38)
183817  {
183818  SDL_I3C0_I3C_P_ECC_AGGR_NUM_RAMS,
183819  SDL_I3C0_I3C_P_ECC_AGGR_RamIdTable,
183820  SDL_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183821  NULL,
183822  SDL_ESM_INST_MAIN_ESM0,
183823  0,
183824  SDLR_ESM0_ESM_LVL_EVENT_I3C0_PCLK_ECC_UNCORR_LVL_0
183825  },
183826  // Index: SDL_MCU_I3C0_I3C_P_ECC_AGGR (39)
183827  {
183828  SDL_MCU_I3C0_I3C_P_ECC_AGGR_NUM_RAMS,
183829  SDL_MCU_I3C0_I3C_P_ECC_AGGR_RamIdTable,
183830  SDL_MCU_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183831  NULL,
183832  SDL_ESM_INST_MCU_ESM0,
183833  0,
183834  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_I3C0_PCLK_ECC_UNCORR_LVL_0
183835  },
183836  // Index: SDL_MCU_I3C0_I3C_S_ECC_AGGR (40)
183837  {
183838  SDL_MCU_I3C0_I3C_S_ECC_AGGR_NUM_RAMS,
183839  SDL_MCU_I3C0_I3C_S_ECC_AGGR_RamIdTable,
183840  SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183841  SDL_MCU_I3C0_I3C_S_ECC_AGGR_MemEntries,
183842  SDL_ESM_INST_MCU_ESM0,
183843  0,
183844  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_I3C0_SCLK_ECC_UNCORR_LVL_0
183845  },
183846  // Index: SDL_MCU_I3C1_I3C_P_ECC_AGGR (41)
183847  {
183848  SDL_MCU_I3C1_I3C_P_ECC_AGGR_NUM_RAMS,
183849  SDL_MCU_I3C1_I3C_P_ECC_AGGR_RamIdTable,
183850  SDL_MCU_I3C1_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183851  NULL,
183852  SDL_ESM_INST_MCU_ESM0,
183853  0,
183854  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_I3C1_PCLK_ECC_UNCORR_LVL_0
183855  },
183856  // Index: SDL_MCU_I3C1_I3C_S_ECC_AGGR (42)
183857  {
183858  SDL_MCU_I3C1_I3C_S_ECC_AGGR_NUM_RAMS,
183859  SDL_MCU_I3C1_I3C_S_ECC_AGGR_RamIdTable,
183860  SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183861  SDL_MCU_I3C1_I3C_S_ECC_AGGR_MemEntries,
183862  SDL_ESM_INST_MCU_ESM0,
183863  0,
183864  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_I3C1_SCLK_ECC_UNCORR_LVL_0
183865  },
183866  // Index: SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR (43)
183867  {
183868  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS,
183869  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable,
183870  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183871  SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries,
183872  SDL_ESM_INST_MAIN_ESM0,
183873  SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG0_PR1_ECC_SEC_ERR_PEND_0,
183874  SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG0_PR1_ECC_DED_ERR_PEND_0
183875  },
183876  // Index: SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR (44)
183877  {
183878  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS,
183879  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable,
183880  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183881  SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries,
183882  SDL_ESM_INST_MAIN_ESM0,
183883  SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG1_PR1_ECC_SEC_ERR_PEND_0,
183884  SDLR_ESM0_ESM_LVL_EVENT_PRU_ICSSG1_PR1_ECC_DED_ERR_PEND_0
183885  },
183886  // Index: SDL_CBASS_ECC_AGGR0 (45)
183887  {
183888  SDL_CBASS_ECC_AGGR0_NUM_RAMS,
183889  SDL_CBASS_ECC_AGGR0_RamIdTable,
183890  SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
183891  NULL,
183892  SDL_ESM_INST_MAIN_ESM0,
183893  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
183894  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0
183895 
183896  },
183897  // Index: SDL_MAIN_RC_ECC_AGGR0 (46)
183898  {
183899  SDL_MAIN_RC_ECC_AGGR0_NUM_RAMS,
183900  SDL_MAIN_RC_ECC_AGGR0_RamIdTable,
183901  SDL_MAIN_RC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
183902  NULL,
183903  SDL_ESM_INST_MAIN_ESM0,
183904  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR4_CORR_LEVEL_0,
183905  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR4_UNCORR_LEVEL_0
183906 
183907  },
183908  // Index: SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR (47)
183909  {
183910  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_NUM_RAMS,
183911  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RamIdTable,
183912  SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183913  NULL,
183914  SDL_ESM_INST_MAIN_ESM0,
183915  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR11_CORR_LEVEL_0,
183916  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR11_UNCORR_LEVEL_0
183917  },
183918  // Index: SDL_DMPAC0_ECC_AGGR (48)
183919  {
183920  SDL_DMPAC0_ECC_AGGR_NUM_RAMS,
183921  SDL_DMPAC0_ECC_AGGR_RamIdTable,
183922  SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183923  SDL_DMPAC0_ECC_AGGR_MemEntries,
183924  SDL_ESM_INST_MAIN_ESM0,
183925  SDLR_ESM0_ESM_LVL_EVENT_DMPAC0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
183926  SDLR_ESM0_ESM_LVL_EVENT_DMPAC0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
183927  },
183928  // Index: SDL_MAIN_HC_ECC_AGGR0 (49)
183929  {
183930  SDL_MAIN_HC_ECC_AGGR0_NUM_RAMS,
183931  SDL_MAIN_HC_ECC_AGGR0_RamIdTable,
183932  SDL_MAIN_HC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
183933  NULL,
183934  SDL_ESM_INST_MAIN_ESM0,
183935  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR5_CORR_LEVEL_0,
183936  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR5_UNCORR_LEVEL_0
183937 
183938  },
183939  // Index: SDL_VPAC0_ECC_AGGR (50)
183940  {
183941  SDL_VPAC0_ECC_AGGR_NUM_RAMS,
183942  SDL_VPAC0_ECC_AGGR_RamIdTable,
183943  SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183944  SDL_VPAC0_ECC_AGGR_MemEntries,
183945  SDL_ESM_INST_MAIN_ESM0,
183946  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
183947  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
183948  },
183949  // Index: SDL_VPAC0_VISS_ECC_AGGR (51)
183950  {
183951  SDL_VPAC0_VISS_ECC_AGGR_NUM_RAMS,
183952  SDL_VPAC0_VISS_ECC_AGGR_RamIdTable,
183953  SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183954  SDL_VPAC0_VISS_ECC_AGGR_MemEntries,
183955  SDL_ESM_INST_MAIN_ESM0,
183956  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_VISS_0_CORR_LEVEL_INTR_0,
183957  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_VISS_0_UNCORR_LEVEL_INTR_0
183958  },
183959  // Index: SDL_VPAC0_LDC_ECC_AGGR (52)
183960  {
183961  SDL_VPAC0_LDC_ECC_AGGR_NUM_RAMS,
183962  SDL_VPAC0_LDC_ECC_AGGR_RamIdTable,
183963  SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183964  SDL_VPAC0_LDC_ECC_AGGR_MemEntries,
183965  SDL_ESM_INST_MAIN_ESM0,
183966  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_LDC_0_CORR_LEVEL_INTR_0,
183967  SDLR_ESM0_ESM_LVL_EVENT_VPAC0_LDC_0_UNCORR_LEVEL_INTR_0
183968  },
183969  // Index: SDL_R5FSS0_CORE0_ECC_AGGR (53)
183970  {
183971  SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
183972  SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
183973  SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183974  SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
183975  SDL_ESM_INST_MAIN_ESM0,
183976  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS0_CORE0_ECC_CORRECTED_PULSE_0,
183977  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS0_CORE0_ECC_UNCORRECTED_PULSE_0
183978  },
183979  // Index: SDL_R5FSS1_CORE0_ECC_AGGR (54)
183980  {
183981  SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS,
183982  SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable,
183983  SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183984  SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries,
183985  SDL_ESM_INST_MAIN_ESM0,
183986  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS1_CORE0_ECC_CORRECTED_PULSE_0,
183987  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS1_CORE0_ECC_UNCORRECTED_PULSE_0
183988  },
183989  // Index: SDL_R5FSS0_CORE1_ECC_AGGR (55)
183990  {
183991  SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
183992  SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
183993  SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
183994  SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
183995  SDL_ESM_INST_MAIN_ESM0,
183996  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS0_CORE1_ECC_CORRECTED_PULSE_0,
183997  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS0_CORE1_ECC_UNCORRECTED_PULSE_0
183998  },
183999  // Index: SDL_R5FSS1_CORE1_ECC_AGGR (56)
184000  {
184001  SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS,
184002  SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable,
184003  SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184004  SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries,
184005  SDL_ESM_INST_MAIN_ESM0,
184006  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS1_CORE1_ECC_CORRECTED_PULSE_0,
184007  SDLR_ESM0_ESM_PLS_EVENT0_R5FSS1_CORE1_ECC_UNCORRECTED_PULSE_0
184008  },
184009  // Index: SDL_NAVSS_VIRTSS_ECC_AGGR0 (57)
184010  {
184011  SDL_NAVSS_VIRTSS_ECC_AGGR0_NUM_RAMS,
184012  SDL_NAVSS_VIRTSS_ECC_AGGR0_RamIdTable,
184013  SDL_NAVSS_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184014  NULL,
184015  SDL_ESM_INST_MAIN_ESM0,
184016  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR10_CORR_LEVEL_0,
184017  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR10_UNCORR_LEVEL_0
184018  },
184019  // Index: SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (58)
184020  {
184021  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS,
184022  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable,
184023  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184024  SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries,
184025  SDL_ESM_INST_MCU_ESM0,
184026  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_SA2_UL0_SA_UL_ECC_CORR_LEVEL_0,
184027  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_SA2_UL0_SA_UL_ECC_UNCORR_LEVEL_0
184028  },
184029  // Index: SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (59)
184030  {
184031  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS,
184032  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable,
184033  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184034  SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries,
184035  SDL_ESM_INST_MAIN_ESM0,
184036  SDLR_ESM0_ESM_LVL_EVENT_SA2_UL0_SA_UL_ECC_CORR_LEVEL_0,
184037  SDLR_ESM0_ESM_LVL_EVENT_SA2_UL0_SA_UL_ECC_UNCORR_LEVEL_0
184038  },
184039  // Index: SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR (60)
184040  {
184041  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS,
184042  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable,
184043  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184044  SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries,
184045  SDL_ESM_INST_MAIN_ESM0,
184046  SDLR_ESM0_ESM_LVL_EVENT_MLB0_MLBSS_ECC_CORR_LVL_0,
184047  SDLR_ESM0_ESM_LVL_EVENT_MLB0_MLBSS_ECC_UNCORR_LVL_0
184048  },
184049  // Index: SDL_MAIN_AC_ECC_AGGR0 (61)
184050  {
184051  SDL_MAIN_AC_ECC_AGGR0_NUM_RAMS,
184052  SDL_MAIN_AC_ECC_AGGR0_RamIdTable,
184053  SDL_MAIN_AC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184054  NULL,
184055  SDL_ESM_INST_MAIN_ESM0,
184056  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR6_CORR_LEVEL_0,
184057  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR6_UNCORR_LEVEL_0
184058 
184059  },
184060  // Index: SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR (62)
184061  {
184062  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_NUM_RAMS,
184063  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RamIdTable,
184064  SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
184065  NULL,
184066  SDL_ESM_INST_WKUP_ESM0,
184067  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_VTM0_CORR_LEVEL_0,
184068  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_VTM0_UNCORR_LEVEL_0
184069  },
184070  // Index: SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM (63)
184071  {
184072  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_NUM_RAMS,
184073  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RamIdTable,
184074  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
184075  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_MemEntries,
184076  SDL_ESM_INST_MAIN_ESM0,
184077  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0,
184078  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0
184079  },
184080  // Index: SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM (64)
184081  {
184082  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_NUM_RAMS,
184083  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RamIdTable,
184084  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
184085  SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_MemEntries,
184086  SDL_ESM_INST_MAIN_ESM0,
184087  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0,
184088  SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0
184089  },
184090  // Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (65)
184091  {
184092  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
184093  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
184094  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
184095  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
184096  SDL_ESM_INST_MAIN_ESM0,
184097  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
184098  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
184099  },
184100  // Index: SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (66)
184101  {
184102  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
184103  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
184104  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
184105  SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
184106  SDL_ESM_INST_MAIN_ESM0,
184107  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
184108  SDLR_ESM0_ESM_LVL_EVENT_MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
184109  },
184110  // Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (67)
184111  {
184112  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS,
184113  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable,
184114  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES,
184115  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries,
184116  SDL_ESM_INST_MAIN_ESM0,
184117  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
184118  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
184119  },
184120  // Index: SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (68)
184121  {
184122  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS,
184123  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable,
184124  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES,
184125  SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries,
184126  SDL_ESM_INST_MAIN_ESM0,
184127  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
184128  SDLR_ESM0_ESM_LVL_EVENT_MMCSD2_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
184129  },
184130  // Index: SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE (69)
184131  {
184132  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_NUM_RAMS,
184133  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RamIdTable,
184134  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES,
184135  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_MemEntries,
184136  SDL_ESM_INST_MAIN_ESM0,
184137  0,
184138  SDLR_ESM0_ESM_LVL_EVENT_DSS_EDP0_INTR_ASF_4
184139 
184140  },
184141  // Index: SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY (70)
184142  {
184143  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_NUM_RAMS,
184144  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RamIdTable,
184145  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES,
184146  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_MemEntries,
184147  SDL_ESM_INST_MAIN_ESM0,
184148  0,
184149  SDLR_ESM0_ESM_LVL_EVENT_DSS_EDP0_INTR_ASF_5
184150 
184151  },
184152  // Index: SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC (71)
184153  {
184154  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_NUM_RAMS,
184155  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RamIdTable,
184156  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES,
184157  SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_MemEntries,
184158  SDL_ESM_INST_MAIN_ESM0,
184159  0,
184160  SDLR_ESM0_ESM_LVL_EVENT_DSS_EDP0_INTR_ASF_6
184161 
184162  },
184163  // Index: SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR (72)
184164  {
184165  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_NUM_RAMS,
184166  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RamIdTable,
184167  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184168  SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_MemEntries,
184169  SDL_ESM_INST_MAIN_ESM0,
184170  SDLR_ESM0_ESM_LVL_EVENT_UFS0_HCLK_ECC_CORR_LVL_0,
184171  SDLR_ESM0_ESM_LVL_EVENT_UFS0_HCLK_ECC_UNCORR_LVL_0
184172  },
184173  // Index: SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR (73)
184174  {
184175  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
184176  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable,
184177  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184178  SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries,
184179  SDL_ESM_INST_MAIN_ESM0,
184180  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_CORR_LEVEL_0,
184181  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF0_UNCORR_LEVEL_0
184182  },
184183  // Index: SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR (74)
184184  {
184185  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS,
184186  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable,
184187  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184188  SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries,
184189  SDL_ESM_INST_MAIN_ESM0,
184190  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF1_CORR_LEVEL_0,
184191  SDLR_ESM0_ESM_LVL_EVENT_CSI_RX_IF1_UNCORR_LEVEL_0
184192  },
184193  // Index: SDL_NAVSS0_MODSS_ECC_AGGR0 (75)
184194  {
184195  SDL_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS,
184196  SDL_NAVSS0_MODSS_ECC_AGGR0_RamIdTable,
184197  SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184198  SDL_NAVSS0_MODSS_ECC_AGGR0_MemEntries,
184199  SDL_ESM_INST_MAIN_ESM0,
184200  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_MODSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
184201  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_MODSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
184202  },
184203  // Index: SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (76)
184204  {
184205  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS,
184206  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable,
184207  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184208  SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries,
184209  SDL_ESM_INST_MAIN_ESM0,
184210  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
184211  SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
184212  },
184213  // Index: SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (77)
184214  {
184215  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS,
184216  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable,
184217  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184218  SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries,
184219  SDL_ESM_INST_MAIN_ESM0,
184220  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
184221  SDLR_ESM0_ESM_LVL_EVENT_USB1_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
184222  },
184223  // Index: SDL_NAVSS0_VIRTSS_ECC_AGGR0 (78)
184224  {
184225  SDL_NAVSS0_VIRTSS_ECC_AGGR0_NUM_RAMS,
184226  SDL_NAVSS0_VIRTSS_ECC_AGGR0_RamIdTable,
184227  SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184228  SDL_NAVSS0_VIRTSS_ECC_AGGR0_MemEntries,
184229  SDL_ESM_INST_MAIN_ESM0,
184230  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_VIRTSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
184231  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_VIRTSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
184232  },
184233  // Index: SDL_NAVSS0_NBSS_ECC_AGGR0 (79)
184234  {
184235  SDL_NAVSS0_NBSS_ECC_AGGR0_NUM_RAMS,
184236  SDL_NAVSS0_NBSS_ECC_AGGR0_RamIdTable,
184237  SDL_NAVSS0_NBSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184238  NULL,
184239  SDL_ESM_INST_MAIN_ESM0,
184240  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_NBSS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
184241  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_NBSS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
184242  },
184243  // Index: SDL_IDOM1_ECC_AGGR0 (80)
184244  {
184245  SDL_IDOM1_ECC_AGGR0_NUM_RAMS,
184246  SDL_IDOM1_ECC_AGGR0_RamIdTable,
184247  SDL_IDOM1_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184248  NULL,
184249  SDL_ESM_INST_MAIN_ESM0,
184250  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR17_CORR_LEVEL_0,
184251  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR17_UNCORR_LEVEL_0
184252 
184253  },
184254  // Index: SDL_IDOM1_ECC_AGGR1 (81)
184255  {
184256  SDL_IDOM1_ECC_AGGR1_NUM_RAMS,
184257  SDL_IDOM1_ECC_AGGR1_RamIdTable,
184258  SDL_IDOM1_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES,
184259  NULL,
184260  SDL_ESM_INST_MAIN_ESM0,
184261  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR19_CORR_LEVEL_0,
184262  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR19_UNCORR_LEVEL_0
184263 
184264  },
184265  // Index: SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR (82)
184266  {
184267  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_NUM_RAMS,
184268  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RamIdTable,
184269  SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184270  NULL,
184271  SDL_ESM_INST_MAIN_ESM0,
184272  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR16_CORR_LEVEL_0,
184273  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR16_UNCORR_LEVEL_0
184274 
184275  },
184276  // Index: SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR (83)
184277  {
184278  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_NUM_RAMS,
184279  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RamIdTable,
184280  SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184281  NULL,
184282  SDL_ESM_INST_MAIN_ESM0,
184283  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR18_CORR_LEVEL_0,
184284  SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR18_UNCORR_LEVEL_0
184285 
184286  },
184287  // Index: SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR (84)
184288  {
184289  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_NUM_RAMS,
184290  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RamIdTable,
184291  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184292  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_MemEntries,
184293  SDL_ESM_INST_MAIN_ESM0,
184294  SDLR_ESM0_ESM_LVL_EVENT_CSI_TX_IF0_CORR_LEVEL_0,
184295  SDLR_ESM0_ESM_LVL_EVENT_CSI_TX_IF0_UNCORR_LEVEL_0
184296  },
184297  // Index: SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE (85)
184298  {
184299  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_NUM_RAMS,
184300  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RamIdTable,
184301  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES,
184302  SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_MemEntries,
184303  SDL_ESM_INST_MAIN_ESM0,
184304  0,
184305  0
184306  },
184307  // Index: SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR (86)
184308  {
184309  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_NUM_RAMS,
184310  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RamIdTable,
184311  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184312  SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_MemEntries,
184313  SDL_ESM_INST_WKUP_ESM0,
184314  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_CORR_LEVEL_0,
184315  SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_UNCORR_LEVEL_0
184316 
184317  },
184318  // Index: SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS (87)
184319  {
184320  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS,
184321  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RamIdTable,
184322  SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES,
184323  NULL,
184324  SDL_ESM_INST_MAIN_ESM0,
184325  0,
184326  SDLR_ESM0_ESM_LVL_EVENT_DSS_DSI0_ECC_INTR_UNCORR_LEVEL_SYS_0
184327 
184328  },
184329  // Index: SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0 (88)
184330  {
184331  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS,
184332  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable,
184333  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184334  SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_MemEntries,
184335  SDL_ESM_INST_MCU_ESM0,
184336  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_NAVSS0_UDMASS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
184337  SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_NAVSS0_UDMASS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
184338  },
184339  // Index: SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR (89)
184340  {
184341  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_NUM_RAMS,
184342  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RamIdTable,
184343  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES,
184344  SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_MemEntries,
184345  SDL_ESM_INST_MAIN_ESM0,
184346  SDLR_ESM0_ESM_LVL_EVENT_PDMA5_ECC_SEC_PEND_0,
184347  SDLR_ESM0_ESM_LVL_EVENT_PDMA5_ECC_DED_PEND_0
184348  },
184349 
184350  // Index: SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR (90)
184351  {
184352  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_NUM_RAMS,
184353  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RamIdTable,
184354  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184355  SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_MemEntries,
184356  SDL_ESM_INST_MAIN_ESM0,
184357  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
184358  SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0
184359  },
184360  // Index: SDL_NAVSS0_UDMASS_ECC_AGGR0 (91)
184361  {
184362  SDL_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS,
184363  SDL_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable,
184364  SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184365  SDL_NAVSS0_UDMASS_ECC_AGGR0_MemEntries,
184366  SDL_ESM_INST_MAIN_ESM0,
184367  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_UDMASS_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
184368  SDLR_ESM0_ESM_LVL_EVENT_NAVSS0_UDMASS_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
184369  },
184370 
184371  // Index: SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (92)
184372  {
184373  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_NUM_RAMS,
184374  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RamIdTable,
184375  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES,
184376  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MemEntries,
184377  SDL_ESM_INST_MAIN_ESM0,
184378  SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT,
184379  SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT
184380  },
184381  // Index: SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (93)
184382  {
184383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_NUM_RAMS,
184384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RamIdTable,
184385  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES,
184386  NULL,
184387  SDL_ESM_INST_MAIN_ESM0,
184388  SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT,
184389  SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT
184390  },
184391  // Index: SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (94)
184392  {
184393  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_NUM_RAMS,
184394  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RamIdTable,
184395  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES,
184396  NULL,
184397  SDL_ESM_INST_MAIN_ESM0,
184398  SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT,
184399  SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT
184400  },
184401  //Index: SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR (SDL_ECC_MEMTYPE_MAIN_A72_AGGR0) (95)
184402  {
184403  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_NUM_RAMS,
184404  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RamIdTable,
184405  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184406  SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MemEntries,
184407  SDL_ESM_INST_MAIN_ESM0,
184408  SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT,
184409  SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT
184410  },
184411  //Index: SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR (96)
184412  {
184413  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_NUM_RAMS,
184414  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RamIdTable,
184415  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184416  SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MemEntries,
184417  SDL_ESM_INST_MAIN_ESM0,
184418  SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT,
184419  SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT
184420  },
184421  // Index: SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR (97)
184422  {
184423  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_NUM_RAMS,
184424  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RamIdTable,
184425  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184426  SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MemEntries,
184427  SDL_ESM_INST_MAIN_ESM0,
184428  SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT,
184429  SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT
184430 
184431  },
184432  // Index: SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS (98)
184433  {
184434  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_NUM_RAMS,
184435  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RamIdTable,
184436  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RAM_IDS_TOTAL_ENTRIES,
184437  NULL,
184438  SDL_ESM_INST_MAIN_ESM0,
184439  SDLR_ESM0_ESM_LVL_EVENT_DDR0_DDRSS_VBUS_ECC_AGGR_CORR_ERR_LVL_0,
184440  SDLR_ESM0_ESM_LVL_EVENT_DDR0_DDRSS_VBUS_ECC_AGGR_UNCORR_ERR_LVL_0
184441 
184442  },
184443  // Index: SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL (99)
184444  {
184445  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_NUM_RAMS,
184446  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RamIdTable,
184447  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RAM_IDS_TOTAL_ENTRIES,
184448  NULL,
184449  SDL_ESM_INST_MAIN_ESM0,
184450  SDLR_ESM0_ESM_LVL_EVENT_DDR0_DDRSS_CTL_ECC_AGGR_CORR_ERR_LVL_0,
184451  SDLR_ESM0_ESM_LVL_EVENT_DDR0_DDRSS_CTL_ECC_AGGR_UNCORR_ERR_LVL_0
184452 
184453  },
184454  // Index: SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG (100)
184455  {
184456  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_NUM_RAMS,
184457  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RamIdTable,
184458  SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RAM_IDS_TOTAL_ENTRIES,
184459  NULL,
184460  SDL_ESM_INST_MAIN_ESM0,
184461  SDLR_ESM0_ESM_LVL_EVENT_DDR0_DDRSS_CFG_ECC_AGGR_CORR_ERR_LVL_0,
184462  SDLR_ESM0_ESM_LVL_EVENT_DDR0_DDRSS_CFG_ECC_AGGR_UNCORR_ERR_LVL_0
184463 
184464  },
184465  // Index: SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR (101)
184466  {
184467  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_NUM_RAMS,
184468  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RamIdTable,
184469  SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
184470  NULL,
184471  SDL_ESM_INST_MAIN_ESM0,
184472  SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_40,
184473  SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_39
184474 
184475  },
184476 };
184477 
184478 #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV0_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132072
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_NAVSS_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:66836
SDL_PCIE1_ECC_AGGR_CORE_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE1_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE1_ECC_AGGR_CORE_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:175787
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100708
SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5093
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:143411
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_29_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:155915
SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69968
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21512
SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170192
SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:69
SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_IRAM_P2P_BRIDGE_IRAM_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170803
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46140
SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_J7_MAIN_INFRA_FW_TO_FW_P2P_BRIDGE_J7_MAIN_INFRA_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109126
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133965
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123950
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:120354
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107718
SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41076
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124402
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:141327
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EDC_CTRL_ECCAGGR1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121374
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58643
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132578
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU2_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67182
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:127940
SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:43914
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:128018
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123851
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61721
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30500
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43926
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:172745
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131664
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45593
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_J7_AC_CBASS_MAIN_FW_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1603
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR1_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20099
SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178208
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109415
SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97002
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SPINLOCK0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21482
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79571
SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable[SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:174996
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24033
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:94477
SDL_WKUP_DMSC0_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_DMSC0_0_RamIdTable[SDL_WKUP_DMSC0_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:182916
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:51302
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_2_2_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107576
SDL_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:126
SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171139
SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable[SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176563
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17859
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43971
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19050
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER2_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:34163
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:28831
SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178254
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46502
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:114490
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107662
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_MemEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:58104
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46101
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8032
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:166593
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:112197
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4909
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:113421
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:562
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131597
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_DMPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11047
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123256
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22991
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_J7_HC2_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117092
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20186
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79487
SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131128
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:125578
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:149142
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:109
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_DMSC_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67528
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:151226
SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_DSP4_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122872
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:85709
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17817
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107290
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:59
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:57200
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14255
SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:163418
SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:151
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41578
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130600
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58155
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:148100
SDL_PCIE1_ECC_AGGR_CORE_AXI_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:45790
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133004
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:60616
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14164
SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:128
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:125358
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46157
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43541
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IJ7_MAIN_INFRACLK2_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79470
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124377
SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries[SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:45863
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17847
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RamIdTable
static const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_NUM_RAMS]
Definition: sdl_ecc_soc.h:172255
SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RamIdTable[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176018
SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5692
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65887
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:111
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33162
SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:181182
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42885
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:39935
SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_FWMGR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171301
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21853
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133713
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21603
SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:70537
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33799
SDL_IDOM1_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
#define SDL_IDOM1_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:91
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_OTHERS_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:60095
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53248
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:51170
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_J7_MCU_CBASS_SCRP_32_PCLK12_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:140459
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:25965
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107346
SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108858
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:95519
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:72209
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:653
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:165030
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:103776
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107251
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45548
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:71688
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21497
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:25110
SDL_MAIN_RC_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MAIN_RC_ECC_AGGR0_RamIdTable[SDL_MAIN_RC_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:179115
SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:152
SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69470
SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170814
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59663
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:50649
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132902
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:91202
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49161
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:93286
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_MemEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:62721
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER2_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30591
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:36874
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21618
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15031
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132168
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:50089
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:107
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:128238
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IJ7_MCU_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162247
SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131169
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176222
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:134486
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30955
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14940
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133814
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:145495
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:34269
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43846
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100268
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_M2P_BRIDGE_IEXPORT_VBUSM_32B_MST_WKUP_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49124
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:132266
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_BOOT_DMSC_MMR_BOOT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121695
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99914
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22374
SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5476
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65818
SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_SMMU_BUFFER0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30409
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:96
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65014
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59562
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61329
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132185
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124352
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99462
SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_IA_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171614
SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171802
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_28_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:155394
SDL_ESM_MCU_R5_CORE0_DED_INT
#define SDL_ESM_MCU_R5_CORE0_DED_INT
Definition: sdl_esm_core.h:81
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_23_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:152789
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110953
SDL_MCU_FSS0_1_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_FSS0_1_RamIdTable[SDL_MCU_FSS0_1_NUM_RAMS]
Definition: sdl_ecc_soc.h:182783
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42732
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:161709
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130695
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:139024
SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5114
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:175009
SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121158
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:198
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45192
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122979
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_PMC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111605
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:115700
SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_J7_TO_J7_RC_FW_CBAS_P2P_BRIDGE_J7_TO_J7_RC_FW_CBAS_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109633
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:64881
SDL_DMPAC0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_DMPAC0_ECC_AGGR_MemEntries[SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:111621
SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44026
SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:155
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22556
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100122
SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RamIdTable[SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178226
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SCR_J7_HC2_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117963
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC1_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10942
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:34790
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_RD_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110647
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_WR_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98548
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110664
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108490
SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178579
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69724
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:176041
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126492
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11221
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43904
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:56158
SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:172232
SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:148
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44760
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131765
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_PRIVID_DMSC_MMR_PRIVID_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121935
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110823
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:74293
SDL_PCIE0_ECC_AGGR_CORE_AXI_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:26508
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_FW_TO_J7_FW_P2P_BRIDGE_FW_TO_J7_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132235
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:104297
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]
This structure holds the base addresses for each memory subtype in MCU domain
Definition: sdl_ecc_soc.h:183316
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:125132
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT3_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:28149
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123454
SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RamIdTable[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178149
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:27126
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49228
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:63449
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13709
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32320
SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26165
SDL_MAIN_AC_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MAIN_AC_ECC_AGGR0_RamIdTable[SDL_MAIN_AC_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:172119
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109471
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15046
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43001
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67541
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_31_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:156957
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15160
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_ECCAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:27105
SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_MemEntries[SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17230
SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26655
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61368
SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41268
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR1_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20752
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MAIN_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100307
SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:61
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:116652
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:94438
SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69702
SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries[SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:26486
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109359
SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:130791
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_SBUS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170831
SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178520
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_SLV_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100177
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9431
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:34254
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:106
SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178387
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59395
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:142890
SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18510
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126099
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RamIdTable
static const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_NUM_RAMS]
Definition: sdl_ecc_soc.h:172702
SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176667
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132688
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31046
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:140066
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32980
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:45907
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130089
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:70
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33344
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_TAGRAM_DMC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111558
SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:66
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59615
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43558
SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:60
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:174199
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14346
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97729
SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162656
SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_DMSC_SBUS_CBASS_DMSC_SBUS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171016
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121214
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123109
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:181268
SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:182583
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4640
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46557
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2823
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SCR_VD2VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:23512
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49217
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132359
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_0_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107546
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44960
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3865
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131964
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:136049
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:25037
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11359
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:3344
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:158403
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59509
SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69436
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:87793
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67567
SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:94
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24645
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_20_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:89356
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SCR_J7_WKUP_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:57984
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:159570
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU1_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65340
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49297
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59547
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41471
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU1_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67093
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_SPARE_9_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1622
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97344
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:54074
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:57928
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111906
SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_groupEntries[SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_K3_DSS_DSI_DSI_TOP_DSI_EDC_CTRL_SYS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:62658
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44815
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20936
SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178172
SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:73
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_LOC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9346
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124947
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124512
SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108765
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4589
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131485
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99371
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_MemEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17775
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126688
SDL_ESM_MCU_R5_CORE1_DED_INT
#define SDL_ESM_MCU_R5_CORE1_DED_INT
Definition: sdl_esm_core.h:83
SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69880
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123747
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6969
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_WKUP2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46679
SDL_NAVSS0_UDMASS_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_MemEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6756
SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69746
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:81149
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21808
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_INT_DMSC_SCR_J7_HC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:114546
SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IVDC_DATA_SAFEG_VBUSM_64B_REF_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:161034
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:123
SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69458
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER1_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:34072
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_MMRS_J7_RC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105280
SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:45951
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CPSW0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65180
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:57967
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:115949
SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109002
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:471
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_VBUSP_ECCAGGR_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111012
SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RamIdTable[SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:173812
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16341
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_MCLK4_TEST_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:83095
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_J7_RC_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_GIC_MEM_RD_VBUSM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98457
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44427
SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:68
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162301
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR2_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122950
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59486
SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:113
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:35311
SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171346
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42387
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61609
SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_DMSC_SBUS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170923
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108657
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12611
SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69337
SDL_NAVSS0_MODSS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_NAVSS0_MODSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:174217
SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162568
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:177641
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_MST_MCU_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133521
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33071
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16324
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_J7_RC_CBASS_IEXPORT_VBUSM_64B_MST_MAIN_0_MST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98639
SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_groupEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2281
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13891
SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:175830
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157882
SDL_PCIE3_ECC_AGGR_CORE_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE3_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:62692
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110244
SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69714
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:84146
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_NUM_RAMS]
Definition: sdl_ecc_soc.h:180391
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:83606
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45493
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1676
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124666
SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION
#define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION
Definition: sdl_ecc_soc.h:6191
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61592
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46302
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_TRSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11152
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:48011
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124820
SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_MemEntries
static const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5595
SDL_PCIE1_ECC_AGGR_CORE_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE1_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:40735
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:90160
SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_VBUSM2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171839
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:63970
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20845
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4625
SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:172554
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:82191
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_J7_RC_CBASS_IMSRAM32KX256E_MAIN_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109542
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45648
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:83481
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_NAVSS_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65097
SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DSMC_CBASS_ECC_S_P2P_BRIDGE_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170759
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_J7_MCU_FW_CBASS_MCU_FW_SCRP_32B_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:161748
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130641
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:88314
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61091
SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES
#define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES
Definition: sdl_ecc_soc.h:183303
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132537
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22465
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:102734
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178538
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132770
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24352
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108674
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:40045
SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_LOCAL_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162426
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_WKUP_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53332
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61480
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21391
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12596
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131524
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99969
SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:172066
SDL_PCIE2_ECC_AGGR_CORE_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE2_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4455
SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:45965
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CTRL_MMR_MCU_0_J7_MCU_CTRL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:161467
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131580
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:51321
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49070
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126610
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41906
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131335
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_ERR_J7_HC2_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117185
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111571
SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17298
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24981
SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15107
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:160612
SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C0_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:40723
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31592
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MAILBOX0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21527
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_PLL_MMR_MCU_0_J7_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:161242
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:104
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67738
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SCR_CFG_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59820
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59600
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:129463
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1014
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:81670
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122729
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108581
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110448
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SMMU_BUFFER0_IN_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33981
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16285
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43689
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_21_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:151747
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49267
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SCR_J7_MCU_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157610
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45748
SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES
#define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES
Definition: sdl_ecc_soc.h:183305
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117720
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:56
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6669
SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17391
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131873
SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109655
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6509
SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26541
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6468
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21656
SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_DMPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:133
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:97
SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26348
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21785
SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE0_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE0_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:175022
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5917
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110698
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123431
SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69682
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4965
SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CBASS_ISYS_M_P2P_BRIDGE_ISYS_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171647
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33435
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:172582
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110409
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109268
SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMAIN_J7_IPPHY_CBASS_MAIN_FW_CBASS_0_J7_IPPHY_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108949
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131625
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:118270
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22283
SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RamIdTable
static const SDL_RAMIdEntry_t SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RamIdTable[SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_NUM_RAMS]
Definition: sdl_ecc_soc.h:177567
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MemEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:122964
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10161
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13399
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_NUM_RAMS]
Definition: sdl_ecc_soc.h:180368
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:140
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111997
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:68246
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:129207
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_P2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111278
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46969
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_CLK1_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111202
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108618
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24998
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46202
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMASS_INTA0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9047
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67439
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:137
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97911
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:137757
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:129152
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:62682
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121410
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44227
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MODSS_INTA1_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20219
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:129348
SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178694
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_DP_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111237
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:64117
SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170742
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133767
SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE1_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1996
SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26277
SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_AASRC_CBASS_MAIN_FW_CBASS_FW_TO_AASRC_FW_P2P_BRIDGE_FW_TO_AASRC_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109644
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR1_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21209
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:88835
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45060
SDL_VPAC0_LDC_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_LDC_ECC_AGGR_MemEntries[SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:130813
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15069
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_ECCAGGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21838
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_DDRSS0_ASAFE_SI_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121310
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32889
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59114
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58833
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_VBUSMC2AXI_V512D32E_D_VEDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109856
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBM_MST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21919
SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17681
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67360
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_J7_NAVSS512L_NBSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110970
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:102271
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107402
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58757
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20769
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_UMEMR_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59209
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97089
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59433
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RamIdTable[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176419
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WAKEUP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53112
SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69601
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:54595
SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_EDC_CTRL_ECCAGGR_CPU0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69581
SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22101
SDL_ESM_INST_MAIN_ESM0
Definition: ip/sdl_esm.h:172
SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5649
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:78878
SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171731
SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:114
SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:150
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98002
SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:172649
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41731
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:140806
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_CFG_VBUSP_32B_SRC_MSMC_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131614
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30289
SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:138
SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_MemEntries
static const SDL_MemConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_MemEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:46625
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6149
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:142369
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_25_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:153831
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6580
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122448
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122772
SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84
SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:115
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4874
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_P2P_BRIDGE_CBASS_LPSC_MCU_COMMON_ERR_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162262
SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_groupEntries[SDL_WKUP_DMSC0_DMSC_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162876
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21565
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9241
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IJ7_WKUP_CLK4_ECC_AGGR_WKUP_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53097
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:96561
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41343
SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69827
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24869
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9180
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44282
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_WMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44860
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59524
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RamIdTable
static const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_NUM_RAMS]
Definition: sdl_ecc_soc.h:172933
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16258
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:25631
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97820
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_RC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107701
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133300
SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45823
SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41221
SDL_PCIE2_ECC_AGGR_CORE_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE2_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE2_ECC_AGGR_CORE_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:172293
SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_INFRA_CBASS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109111
SDL_NAVSS_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_NAVSS_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:141
SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176492
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133339
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:127877
SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_VPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_VPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2101
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_1_1_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107561
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE1_DP_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111265
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:118231
SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:169671
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_WKUP_FW_CBASS_WKUP_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49282
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98730
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:125103
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_DP_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111321
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_MSRAM1_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58700
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99865
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131709
SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:99
SDL_CPSW0_0_MemEntries
static const SDL_MemConfig_t SDL_CPSW0_0_MemEntries[SDL_CPSW0_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:171998
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:127429
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31683
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130537
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:100
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107195
SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109666
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79526
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:25054
SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131314
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_DMPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12270
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:73251
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:112042
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8275
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124008
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46257
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK4_DMSC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49818
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99761
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:143932
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:181619
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_P2P_BRIDGE_ICOMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0_VBUSP_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107531
SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DRAM0_P2P_BRIDGE_DRAM0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170792
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_26_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:154352
SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_MemEntries[SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:58093
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MCU_FW_CBASS_MCU_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133728
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_MMR_EMULATION_DMSC_MMR_EMULATION_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121830
SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26825
SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_HC2_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117946
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_NB_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31774
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123295
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107458
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_J7_RC_CBASS_BR_TO_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97535
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV0_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110281
SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5637
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98093
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21633
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_DP_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111293
SDL_VPAC0_VISS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_VISS_ECC_AGGR_RamIdTable[SDL_VPAC0_VISS_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:182385
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30682
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42337
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33617
SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109835
SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69500
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_VPAC_TC0_CC_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10837
SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:173920
SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44503
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:136570
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49053
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21671
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_UDMASS_CBASS_DMSC_SLV_P2P_BRIDGE_UDMASS_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131468
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:90681
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_32M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97638
SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE1_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE1_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:176510
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97244
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:137236
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16593
SDL_MCU_CBASS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_CBASS_ECC_AGGR0_RamIdTable[SDL_MCU_CBASS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:181802
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_HC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111815
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24369
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44604
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_MCU0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67004
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:66374
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV3_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132123
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24662
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107038
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33526
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53265
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_GSKT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122703
SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171658
SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_VPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26924
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130712
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4439
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_14_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:86230
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_16_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:87272
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33890
SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_0__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1786
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_SE_1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111588
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_P2P_BRIDGE_BR_SCRP_32B_CLK4_INFRA_TO_SCRP_32B_MCLK4_TEST_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:83591
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123676
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CTL_WRAP_VBUSP2AHB_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4386
SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_groupEntries[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_PCIE_G4X2_CORE_DBN_WRAP_AXI_PARITY_INV_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69927
SDL_MCU_I3C0_I3C_S_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_I3C0_I3C_S_ECC_AGGR_MemEntries[SDL_MCU_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6721
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_DATA_VBUSM_64B_SRC_MSMC_GIC_MEM_WR_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109935
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:138503
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44327
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST3_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31319
SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_VPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26754
SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61536
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107419
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105346
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44127
SDL_MCU_FSS0_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_FSS0_0_RamIdTable[SDL_MCU_FSS0_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:182700
SDL_ECC_aggrHighBaseAddressTableTrans
SDL_ecc_aggrRegs * SDL_ECC_aggrHighBaseAddressTableTrans[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
Definition: sdl_ecc_soc.h:183428
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:43892
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:129311
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSP_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16037
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1693
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107475
SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170770
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105307
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_INFRA_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79455
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122746
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_P2P_BRIDGE_INAVSS_MCU_J7_MCU_0_MODSS_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:160929
SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41147
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126803
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_J7_MCU_CBASS_SCRP_32B_PCLK3_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:136715
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45331
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133151
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:78357
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_MST0_SRC_NB_MST0_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110630
SDL_PCIE3_ECC_AGGR_CORE_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE3_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE3_ECC_AGGR_CORE_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:177598
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:112379
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133612
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108341
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107514
SDL_PCIE3_ECC_AGGR_CORE_AXI_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69894
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53347
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:52363
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11290
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117075
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31137
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126908
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:118791
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_P2P_BRIDGE_IPSRAM512X32E_MAIN_0_ECCAGGR_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79556
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99007
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46046
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_MemEntries
static const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:62634
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16554
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:45929
SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17498
SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108802
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:141848
SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45115
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_24_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:153310
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_P2P_BRIDGE_IPULSAR_SL_MCU_0_CPU1_CFG_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133698
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13982
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67580
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:106517
SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:103
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21300
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4948
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133389
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_M2AXI_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:29656
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12438
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53460
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10542
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24925
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24701
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RamIdTable[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:180634
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_RD_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131748
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:132
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:127822
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79416
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44182
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:74710
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117929
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99098
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99280
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:77836
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IMSRAM128KX64E_MCU_0_CFG_P2P_BRIDGE_IMSRAM128KX64E_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133668
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:136
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_INT_DMSC_SCR_J7_RC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105363
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_NAV_DDR0_VIRT_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21118
SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_PSRAM512X32E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41311
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:75752
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RamIdTable[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:179806
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124481
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24886
SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69859
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45348
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21694
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK3_TO_SCRP_32_PCLK6_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133428
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:177580
SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:176240
SDL_MCU_I3C1_I3C_P_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_I3C1_I3C_P_ECC_AGGR_RamIdTable[SDL_MCU_I3C1_I3C_P_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176834
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:77315
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58077
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69869
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124639
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32502
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SCR_J7_MCU_FW_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162318
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100526
SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17569
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_MSMC0_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10732
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124085
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IDMSC_WKUP_0_VBUSP_S_P2P_BRIDGE_IDMSC_WKUP_0_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49109
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123967
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_SCLK_CLK_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10459
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45919
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:62298
SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178190
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124225
SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:182669
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU0_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107307
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RamIdTable
static const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY_NUM_RAMS]
Definition: sdl_ecc_soc.h:177534
SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:45768
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_5_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117681
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97289
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:118214
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_0_CPU0_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_0_CPU0_PMST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107234
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_DMC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111349
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_CLK4_CLK_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122478
SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:89
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5584
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61385
SDL_VPAC0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_ECC_AGGR_RamIdTable[SDL_VPAC0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:175128
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_AC_6_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1053
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:62670
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24813
SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:172618
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_8_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:38437
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_J7_MCU_CBASS_IEXPORT_VBUSM_32B_SLV_MCU_0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133870
SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109094
SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:118
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:139545
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:146016
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_P2P_BRIDGE_IJ7_MCUCLK8_ECC_AGGR_MCU_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133683
SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_groupEntries[SDL_WKUP_DMSC0_DRAM1_P2P_BRIDGE_DRAM1_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170781
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:73772
SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:125
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU0_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100344
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:89639
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157554
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:76273
SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41236
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99706
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11914
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:82712
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:289
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_MSMC0_SLV_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43672
SDL_PCIE0_ECC_AGGR_CORE_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE0_ECC_AGGR_CORE_0_RamIdTable[SDL_PCIE0_ECC_AGGR_CORE_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:174953
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:114529
SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133043
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110539
SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:53
SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130803
SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:182687
SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_RC_NAVMCU_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109730
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:80107
SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44659
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_R_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:29773
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67753
SDL_PCIE2_ECC_AGGR_CORE_AXI_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE2_ECC_AGGR_CORE_AXI_0_MemEntries[SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5659
SDL_CPSW0_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW0_0_RamIdTable[SDL_CPSW0_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:183197
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_M2M_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109952
SDL_MCU_FSS0_2_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_FSS0_2_RamIdTable[SDL_MCU_FSS0_2_NUM_RAMS]
Definition: sdl_ecc_soc.h:182796
SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_MAIN_AC_DMPAC_PSIL_RETIME_BR_MAIN_1__J7_MAIN_AC_DMPAC_PSIL_RETIME_BR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1891
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_VIRTSS_DMSC_SLV_P2P_BRIDGE_VIRTSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131541
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:130857
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6290
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9798
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:93807
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IPULSAR_SL_MAIN_1_CPU1_PMST_P2P_BRIDGE_IPULSAR_SL_MAIN_1_CPU1_PMST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107363
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132993
SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:108
SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ADC12C0_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:98
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_J7_MAIN_INFRA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:94328
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_LOC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9516
SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109234
SDL_COMPUTE_CLUSTER0_10_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_10_MemEntries[SDL_COMPUTE_CLUSTER0_10_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:171818
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24757
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61704
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:144974
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108358
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_M2M_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132140
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21747
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46001
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_9_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:38958
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV1_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132089
SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162580
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_CSI_RX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17805
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107645
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13410
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69245
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:92765
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RAM_IDS_TOTAL_ENTRIES
#define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:130
SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121268
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:163467
SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_groupEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_PSRAM256X32E_16FFC_PSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2238
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMASS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:62907
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58267
SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26387
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_VBUSP_CFG_ECC_AGGR2_P2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122911
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:160963
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130482
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:174151
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_P2P_BRIDGE_IVDC_INFRA_SAFEG_VBUSP_32B_REF_MCU2MAIN_INFRA_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133784
sdl_esm_core.h
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61553
SDL_WKUP_DMSC0_IRAM_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IRAM_BUSECC_groupEntries[SDL_WKUP_DMSC0_IRAM_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162783
SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17755
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:148621
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:165551
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_TCU_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30342
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5750
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT4_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32229
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20808
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_J7_AC_CBASS_MAIN_FW_CBASS_DMSC_FW_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1332
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_ECCAGGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17968
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_MST1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97389
SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:40964
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42840
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14758
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_ERR_SCR_J7_HC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:118121
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32608
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61760
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15696
SDL_MAIN_AC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MAIN_AC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:52
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:8796
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RamIdTable
static const SDL_RAMIdEntry_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_RamIdTable[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_VBUS_NUM_RAMS]
Definition: sdl_ecc_soc.h:179793
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117204
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_15_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:86751
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2M_VOLTAGE_DOMAIN1_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5733
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11683
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42948
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42497
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46357
SDL_MCU_CPSW0_0_MemEntries
static const SDL_MemConfig_t SDL_MCU_CPSW0_0_MemEntries[SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162742
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105081
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24830
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:129270
SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_MemEntries[SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:41256
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:125145
SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_groupEntries[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_MSRAM16KX256E_MSRAM0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69758
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_DDRSS0_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122714
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14361
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE2_P2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111306
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100435
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:55116
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117834
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RAM_IDS_TOTAL_ENTRIES
#define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:54
SDL_ESM_INST_MCU_ESM0
Definition: ip/sdl_esm.h:170
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:7511
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30773
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:146537
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_MMRS_J7_HC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:114463
SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:146
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC2_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:116040
SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:95
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:159049
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_P2M_BRIDGE_IEXPORT_VBUSM_32B_SLV_WKUP_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:49200
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:135528
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67659
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97023
SDL_IDOM1_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_IDOM1_ECC_AGGR0_RamIdTable[SDL_IDOM1_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:176253
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_UMEMW_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14073
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98916
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:41331
SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_RamIdTable[SDL_CSI_RX_IF0_CSI_RX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:174103
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT4_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:28490
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_DATA_VBUSM_64B_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109251
SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MSRAM128KX64E_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69394
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22010
SDL_MCU_CPSW0_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_CPSW0_0_RamIdTable[SDL_MCU_CPSW0_0_NUM_RAMS+17]
Definition: sdl_ecc_soc.h:182809
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_UDMASS_VBP_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21823
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:101229
SDL_DMPAC0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_DMPAC0_ECC_AGGR_RamIdTable[SDL_DMPAC0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:180037
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131429
SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE2_ECC_AGGR_CORE_AXI_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:62
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21770
SDL_MAIN_HC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MAIN_HC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:134
SDL_MCU_CBASS_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_MCU_CBASS_ECC_AGGR0_MemEntries[SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:132743
SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17720
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4610
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122621
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_27_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:154873
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58472
SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44542
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M256_SCR_J7_RC_CBASS_RC_M256_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:101750
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_J7_RC_CBASS_BR_FROM_64M_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97444
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:169198
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_HC2_SCR_J7_HC2_CBASS_HC2_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:116131
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_RINGACC0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61441
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46457
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:52884
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45941
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69736
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_MSMC_ECC_AGGR1_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122463
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_ECC_AGGR_DST_NB_ECC_AGGR_CFG_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110171
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17871
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:144453
SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:127
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59630
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_SEC_PROXY0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21886
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_22_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:152268
SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44065
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_ECC_AGGR_SRC_NB_ECC_AGGR_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132157
SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:88
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_HC_SPARE_8_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121253
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122638
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:112288
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:119312
SDL_ECC_aggrHighBaseAddressTable
static uint64_t const SDL_ECC_aggrHighBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
Definition: sdl_ecc_soc.h:183414
SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176685
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98366
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_DATA_VBUSM_64B_DST_MSMC_GIC_MEM_WR_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131856
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_13_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:147579
SDL_MCU_I3C0_I3C_P_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_I3C0_I3C_P_ECC_AGGR_RamIdTable[SDL_MCU_I3C0_I3C_P_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:175774
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132466
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6193
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT3_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32138
SDL_WKUP_DMSC0_IDRAM0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IDRAM0_BUSECC_groupEntries[SDL_WKUP_DMSC0_IDRAM0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162814
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_MAIN_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1637
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_CFG_VBUSP_32B_DST_MSMC_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110134
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_10_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109398
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176631
SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44698
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44559
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_INTA0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15084
SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_CBASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:143
SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_MAIN_AC_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2206
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45292
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108397
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61052
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65749
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44715
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_EDC_CTRL_ECCAGGR2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121289
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_8_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:167635
SDL_NAVSS0_NBSS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_NAVSS0_NBSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_NBSS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:176054
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_UDMAP0_TRSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12359
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157535
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_MEMBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44082
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV3_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110681
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:120875
SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_AHB2VBUSP_CPU1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131279
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:164509
SDL_MAIN_HC_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MAIN_HC_ECC_AGGR0_RamIdTable[SDL_MAIN_HC_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:180080
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:19571
SDL_IDOM1_ECC_AGGR1_RamIdTable
static const SDL_RAMIdEntry_t SDL_IDOM1_ECC_AGGR1_RamIdTable[SDL_IDOM1_ECC_AGGR1_NUM_RAMS]
Definition: sdl_ecc_soc.h:176336
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59410
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:80628
SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109141
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:172336
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:39846
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_CPU1_SLV_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100617
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_NAV_DDR0_VIRTID_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20735
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:83442
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123000
SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121102
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130781
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45393
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124098
SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_DMSC0_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162897
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_groupEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_K3_DSS_EDP_MHDPTX_WRAPPER_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5610
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable
static const SDL_RAMIdEntry_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
Definition: sdl_ecc_soc.h:178597
SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:101
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:85188
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M64_SCR_J7_RC_CBASS_RC_M64_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:103255
SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:40857
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99657
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6654
SDL_MCU_FSS0_2_MemEntries
static const SDL_MemConfig_t SDL_MCU_FSS0_2_MemEntries[SDL_MCU_FSS0_2_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162731
SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69847
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43060
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123416
SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PSRAM2KECC0_PSRAM512X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:85
soc.h
This file contains SOC specific defintions.
SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_MemEntries
static const SDL_MemConfig_t SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_MemEntries[SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69480
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:112142
SDL_ecc_aggrRegs
Definition: sdlr_ecc.h:53
SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RamIdTable[SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:177163
SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17610
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_MemEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:4484
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC1_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12181
SDL_ESM_INST_WKUP_ESM0
Definition: ip/sdl_esm.h:168
SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_MemEntries[SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69325
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131698
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:25093
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97189
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:35832
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:4655
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6990
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16666
SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:71058
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_MSMC0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12003
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124976
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:58
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97044
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:94421
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117036
SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26422
SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_PLL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:70016
SDL_I3C0_I3C_S_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_I3C0_I3C_S_ECC_AGGR_MemEntries[SDL_I3C0_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:26581
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:112900
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122097
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_J7_HC_CBASS_J7_HC2_TO_HC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:112097
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133484
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RCNAVSS_11_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109510
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:56679
SDL_NAVSS0_VIRTSS_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_MemEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:26994
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:83625
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110043
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_DDRSS0_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122761
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122565
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_SRC0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59729
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:68713
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_EDC_CTRL_ECCAGGR_COREPAC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110991
SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR_VBUSP_CFG_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5056
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:39896
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RAM_IDS_TOTAL_ENTRIES
#define SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:63
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_19_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:150705
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_RMST1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98275
SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RamIdTable
static const SDL_RAMIdEntry_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_RamIdTable[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE_NUM_RAMS]
Definition: sdl_ecc_soc.h:176847
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PSILCFG0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:66605
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117737
SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE2_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:55
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32794
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:135
SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_NAVSS0_UDMASS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:67
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_NAVSS_TR_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9605
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_DDR0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99810
SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:145
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42404
SDL_MCU_I3C1_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_I3C1_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:102
SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_DEBUG_CBASS_MAIN_FW_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109719
SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:116
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_RamIdTable[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176708
SDL_IDOM1_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_IDOM1_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:90
SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MSRAM_1MB0_MSRAM128KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:112
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59019
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE0_P2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111250
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59471
SDL_NAVSS0_MODSS_ECC_AGGR0_MemEntries
static const SDL_MemConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_MemEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:17881
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132723
SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108172
SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_CPSW0_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:149
SDL_I3C0_I3C_S_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_I3C0_I3C_S_ECC_AGGR_RamIdTable[SDL_I3C0_I3C_S_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:175075
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:68724
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_WMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45693
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_SCR_VBUSM_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15175
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMAP0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16705
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_DMSC_SLV_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24313
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16722
SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:119
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130678
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43491
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61648
SDL_VPAC0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_ECC_AGGR_MemEntries[SDL_VPAC0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:26616
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122582
SDL_MCU_I3C1_I3C_S_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCU_I3C1_I3C_S_ECC_AGGR_MemEntries[SDL_MCU_I3C1_I3C_S_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:46577
SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:86
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_PROXY0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21732
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC2_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117890
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157425
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_ADC_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65510
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_MemEntries
static const SDL_MemConfig_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_MemEntries[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:6689
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:48532
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20343
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:72730
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99602
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133168
SDL_NAVSS_VIRTSS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_NAVSS_VIRTSS_ECC_AGGR0_RamIdTable[SDL_NAVSS_VIRTSS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:181451
SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26058
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133350
SDL_CBASS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_CBASS_ECC_AGGR0_RamIdTable[SDL_CBASS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:178747
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41794
SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:117
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES
#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:65
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31956
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110914
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:37395
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_RINGACC0_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:64638
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_ERR_SCR_J7_RC_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108248
SDL_COMPUTE_CLUSTER0_10_RAM_IDS_TOTAL_ENTRIES
#define SDL_COMPUTE_CLUSTER0_10_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:154
SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5465
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_C711_COREPAC_CFG_CBASS_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111027
SDL_VPAC0_LDC_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_VPAC0_LDC_ECC_AGGR_RamIdTable[SDL_VPAC0_LDC_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:181200
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61777
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_UDMAP0_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:11452
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CTL_VBUSMC2AXI_V512D32E_D_HEDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:2302
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DMA_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:29381
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_SPARE_7_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109527
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58176
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59696
SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:57
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_RC_M32_SCR_J7_RC_CBASS_RC_M32_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:104560
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6619
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33253
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21580
SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45175
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:167114
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41623
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61497
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_CC_SOC_DMSC_VBUSP_32B_SRC_MSMC_VBUSP_DMSC_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131681
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_P2P_BRIDGE_IPSRAM256X32E_16FFC_MAIN_0_RAM_VB_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79541
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_MSMC_J7ES_ECC_AGGR2_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121357
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:47490
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42348
SDL_NAVSS0_NBSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_NAVSS0_NBSS_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:87
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_TIMERMGR1_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24718
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_SLV_SRC_NB_SLV2_SRC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132106
SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_PCIE3_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:110
SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_IJ7_MAIN_HC_FW_CBASS_0_J7_MAIN_HC_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:118056
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:115179
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_10_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:168677
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_6_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:92244
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:94998
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_11_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:84667
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31410
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:26497
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:163988
SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69414
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:128759
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_DMA_MST1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31501
SDL_VPAC0_VISS_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_VPAC0_VISS_ECC_AGGR_MemEntries[SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162446
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45237
SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44482
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:55637
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176649
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_P2P_BRIDGE_IJ7_MCU_VBUSM_SAFETY_GASKET_MCU2MAIN_0_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162411
SDL_NAVSS0_VIRTSS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:175206
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_GICSS_M2M_BRIDGE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122817
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:39952
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_PDMA_ADC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67271
SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:71579
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_UDMAP0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:62928
SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:40764
SDL_ESM_MCU_R5_CORE1_SEC_INT
#define SDL_ESM_MCU_R5_CORE1_SEC_INT
Definition: sdl_esm_core.h:82
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123659
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5880
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13800
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:22192
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99189
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_CBASS_DEFAULT_ERR_J7_RC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105456
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108473
SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:93
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_0_PBDG_RMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98825
SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_RC_CBASS_DMSC_SLV_P2P_BRIDGE_RC_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108133
SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_groupEntries[SDL_MCU_I3C1_I3C_P_ECC_AGGR_I3C_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46613
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_DDR32SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5990
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_PSILCFG0_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12517
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110732
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:125473
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_GLOBAL_NAVSS_MCU_PSIL_AS_BRIDGE_EDC_CTRL_MCLK_CLK_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10376
SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_VDC_J7_NAV_NB_MST0_DST_NB_MST0_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131981
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14667
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:13016
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MAILBOX0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24606
SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_groupEntries[SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_PSIL_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111744
SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_IJ7_AC_CBASS_MAIN_FW_CBASS_0_J7_AC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1123
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:92
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU2_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65425
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CFG_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:1070
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9977
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_J7_MAIN_INFRA_CBASS_SCRP_32B_CLK4_INFRA_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79586
SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_AC_ECC_AGGR0_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_J7_AC_CBASS_INAVSS512L_MAIN_0_AC_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:380
SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IRC_FW_CBASS_J7_RC_CBASS_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108189
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65595
SDL_MCU_FSS0_0_MemEntries
static const SDL_MemConfig_t SDL_MCU_FSS0_0_MemEntries[SDL_MCU_FSS0_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162667
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9783
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123806
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_INFRA_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133283
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_PDMA_MCU0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65255
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_4_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:36353
SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_DDR0_DDR32SSC_EW_DV_WRAP_DDRSS_BRCTL_SC_ECC_AGGR_CFG_VDC_DDR_CFG_VBUSP_32B_REF_IM2P_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:5841
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:166072
SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162590
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_18_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:150184
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_UDMASS_INTA0_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:67554
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_MS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43651
SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:182601
SDL_MAIN_RC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
#define SDL_MAIN_RC_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:129
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_12_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:147058
SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_groupEntries[SDL_DMPAC0_ECC_AGGR_DRU_UTC_DMPAC_CORE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111645
SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_FW_CBASS_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_P2P_BRIDGE_IEXPORT_VBUSP_32B_MST_FWMAIN_0_MST_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109055
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_12_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_12_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157703
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_PROXY0_BUF_DST_BR_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20252
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_NAVSS512L_VIRTSS_PHYS_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132246
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:33708
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_MAILBOX0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:18529
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16537
SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178556
SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RamIdTable
static const SDL_RAMIdEntry_t SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_RamIdTable[SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE_NUM_RAMS]
Definition: sdl_ecc_soc.h:172595
SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:124
SDL_WKUP_DMSC0_0_RAM_IDS_TOTAL_ENTRIES
#define SDL_WKUP_DMSC0_0_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:153
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53293
SDL_MCU_I3C1_I3C_S_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_I3C1_I3C_S_ECC_AGGR_RamIdTable[SDL_MCU_I3C1_I3C_S_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176781
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_J7_HC2_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117011
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_MEM0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58924
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:96040
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:6397
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_J7_WKUP_CBASS_SCRP_32B_PCLK8_WAKEUP_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:50128
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_CBASS_DEFAULT_ERR_J7_HC_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:114639
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_MAIN_FW_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:79399
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24286
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_MAIN_SYSCLK0_1_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_1_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:114658
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_MODSS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24774
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126547
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_J7_MAIN_INFRA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:91723
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_AC_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:30864
SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_MAIN_HC_FW_CBASS_HC_CBASS_DMSC_SLV_P2P_BRIDGE_HC_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121141
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_UDMAP0_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:65664
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_P2P_BRIDGE_BR_SCRP_32_PCLK6_TO_SCRP_32_PCLK12_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133651
SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_MemEntries
static const SDL_MemConfig_t SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:5626
SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131240
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_FW_CH_VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14634
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122677
SDL_MCU_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_I3C0_I3C_P_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45136
SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:2226
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_AXI2M_KSBUS_AXI2VBUSM_W_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:29826
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110210
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157593
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_30_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:156436
SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_MEM_MST1_KSBUS_AXI2VBUSM_W_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131057
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_TIMERMGR0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20012
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SPINLOCK0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:17989
SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:147
SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IWKU_COR_DATA_VBUSP_32B_M2M_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108841
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45015
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_SRC_P2M_REASSEMBLY_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53282
SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0_NAVSS_MCU_J7_UDMASS_PSILSS0_L2P_CPSW0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:66925
SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:51
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16649
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_J7_MCU_CBASS_SCRM_64B_PCLK3_R5_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:137982
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:129568
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV2_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110715
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_L2P_UDMAP0_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:9694
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT2_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:27808
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_J7_MCU_CBASS_SCRP_32_PCLK6_SCR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:135007
SDL_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_NAVSS0_UDMASS_ECC_AGGR0_RamIdTable[SDL_NAVSS0_UDMASS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:173034
SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CBASS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170894
SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26236
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_J7_MCU_CBASS_CBASS_LPSC_MCU_COMMON_MMRS_EDC_CTRL_BUSECC_17_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:149663
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_J7_RC_CBASS_IPULSAR_SL_MAIN_1_MEMBDG_WMST0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:98184
SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_DMSC0_INTAGGR_CFG_P2P_BRIDGE_INTAGGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:170703
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:29897
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_GCLK_EDC_CTRL_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:40566
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_R5_3_3_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107591
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_LOCAL_CBASS_ETL_D_DEF_EVT_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10150
SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_INFRA_CBASS_MAIN_0_J7_MAIN_INFRA_CBASS_ERR_SCR_J7_MAIN_INFRA_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:83498
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_VD2_TO_VBUSP_M2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:58796
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_RINGACC0_SRC_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14543
SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_SCR_SCR_DMSC_FWMGR_CBASS_DMSC_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171178
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_CC_SOC_DMSC_VBUSP_32B_DST_MSMC_VBUSP_DMSC_DST_M2P_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110372
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_NAVSS_TR_PSIL_RT_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:10627
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:127981
SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69426
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_SEC_PROXY0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:20556
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61424
SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123148
SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41035
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:124793
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_5_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:76794
SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CSI_RX_IF1_CSI_RX_IF_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:71
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_TBU0_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:29988
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCS_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41847
SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_VISS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:144
SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC2_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121197
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CTRL_MMR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:57721
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_TIMERMGR0_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21550
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_J7_RC_CBASS_J7_RC_TO_HC_VBUSM0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:99553
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_3_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_3_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:158924
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_BR_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15122
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_WKUP_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_WKUP_MCU_SYSCLK0_6_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53981
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_IWKU_COR_DATA_VBUSP_32B_INFRA_SAFEG_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:53133
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21027
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:183432
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_IO_PVU1_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:29106
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61025
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RamIdTable[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:176875
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_P2P_BRIDGE_IJ7_MAINCLK2_ECC_AGGR_MAIN_RC_4_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:107606
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCM1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41686
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:161692
SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:64
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100018
SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_DMSC0_DMSC_CBASS_CBASS_INT_DMSC_SCR_DMSC_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171521
SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_DST_M2P_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:108434
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:131
SDL_COMPUTE_CLUSTER0_10_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_10_RamIdTable[SDL_COMPUTE_CLUSTER0_10_NUM_RAMS]
Definition: sdl_ecc_soc.h:183159
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMASS_VBM_SLV1_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14452
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_CLK4_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122008
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_M2P_BRIDGE_BR_SCRM_64B_PCLK3_R5_TO_SCRP_32B_PCLK3_L0_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133445
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:174765
SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45780
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_SEC_MMR_MCU_0_J7_MCU_SEC_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:161189
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_NAV_MCU_DST0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59304
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT0_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31865
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_3_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:113942
SDL_PCIE0_ECC_AGGR_CORE_0_MemEntries
static const SDL_MemConfig_t SDL_PCIE0_ECC_AGGR_CORE_0_MemEntries[SDL_PCIE0_ECC_AGGR_CORE_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:26457
SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_groupEntries[SDL_WKUP_DMSC0_CBASS_DEFAULT_MMRS_DMSC_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_9_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:168156
SDL_MCU_FSS0_1_MemEntries
static const SDL_MemConfig_t SDL_MCU_FSS0_1_MemEntries[SDL_MCU_FSS0_1_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162720
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_groupEntries[SDL_MCU_R5FSS0_CORE1_ECC_AGGR_PERIPH_M_MST1_KSBUS_AXI2VBUSM_R_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132649
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_P2P_BRIDGE_BR_SCRP_32B_PCLK4_DMSC_TO_SCRP_32B_PCLK8_WAKEUP_L0_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:51153
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CFG_CBASS_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_P2P_BRIDGE_IJ7_HC_CBASS_MAIN_0_CBASS_ERR_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:117873
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:31228
SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_VPAC0_LDC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:139
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157386
SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:69980
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_J7_WKUP_FW_CBASS_CBASS_LPSC_WKUP_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46660
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_J7_MCU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:157442
SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:122
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_FW_CBASS_WKUP_0_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_J7_WKUP_FW_CBASS_SCRP_WKUP_FW_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46694
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:39325
SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR_IDOM0_M2M_PBDG_RMST0_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:46402
SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_groupEntries[SDL_MAIN_HC_ECC_AGGR0_J7_HC_CBASS_HC_SCR_J7_HC_CBASS_HC_SCR_EDC_CTRL_BUSECC_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:119833
SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:142
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_ERR_SCR_J7_WKUP_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:51060
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:15137
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_SCR_SCR_EDC_CTRL_7_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:37916
SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:172631
SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_MCU_ADC12C1_ADC12C_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178610
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61108
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_UDMAP0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59577
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_CBASS_MMR_CFG_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:43502
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_J7_FW_TO_FW_P2P_BRIDGE_J7_FW_TO_FW_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132224
SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_GIC500SS_4_2_AXI2VBUSM_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:171910
SDL_ESM_MCU_R5_CORE0_SEC_INT
#define SDL_ESM_MCU_R5_CORE0_SEC_INT
Definition: sdl_esm_core.h:80
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_MemEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:46645
SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RamIdTable
static const SDL_RAMIdEntry_t SDL_PCIE3_ECC_AGGR_CORE_AXI_0_RamIdTable[SDL_PCIE3_ECC_AGGR_CORE_AXI_0_NUM_RAMS]
Definition: sdl_ecc_soc.h:178628
SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:105
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42518
SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE1_ECC_AGGR_KSBUS_VBUSM2AXI1_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:130950
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_M2P_BRIDGE_IEXPORT_VBUSP_32B_SLV_MCU_0_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133853
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:128133
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_MOD_SLV0_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32699
SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_groupEntries[SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR_VDC_J7_NAV_NB_SLV_DST_NB_SLV1_DST_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:110227
SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR0_IDOM1_M2M_PBDG_WMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44382
SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR_IDOM0_M2M_MEMBDG_WMST0_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45448
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105996
SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:121
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:123239
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_CFG_WRAP_CBASS_VBUSP_GICSS_P2M_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:122688
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SRC_P2M_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:132885
SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_NAVSS_VIRTSS_ECC_AGGR0_J7_FW_UDMASS_VDD_CC_CBASS_MODSS_DMSC_SLV_P2P_BRIDGE_MODSS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:131412
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_UDMASS_INTA0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16610
SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_ECC_AGGR1_IDOM1_M2M_PBDG_RMST1_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:44915
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_PAT2_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32047
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_J7_RC_CBASS_J7_HC_TO_RC_VBUSM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:97144
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_IO_PVU1_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32411
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:105475
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_groupEntries[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_BUSECC_PIPE3_P2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:111334
SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162646
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:126651
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_J7_RC_CBASS_INAVSS512L_MAIN_0_NAV_SRAM1_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:100073
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_P2P_BRIDGE_IVDC_SOC_FW_SAFEG_VBUSP_32B_REF_FWMCU2MAIN_SAFEG_CFG_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133799
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_CBASS_CH_SEC_PROXY0_CFG_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:24942
SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_RamIdTable[SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:179934
SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_ICOR_MCU_DATA_VBUSM_64B_M2M_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:133060
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_J7_WKUP_CBASS_CBASS_LPSC_WKUP_COMMON_MMRS_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:51842
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_PAT1_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:27467
SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries
static const SDL_GrpChkConfig_t SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:69448
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCM0_DST_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42777
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:120
SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_NAVSS0_MODSS_ECC_AGGR0_NAVSS512L_MODSS_CBASS_MODSS_INTA1_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:21709
SDL_MCU_I3C0_I3C_S_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_I3C0_I3C_S_ECC_AGGR_RamIdTable[SDL_MCU_I3C0_I3C_S_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:172981
SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:26437
SDL_WKUP_DMSC0_0_MemEntries
static const SDL_MemConfig_t SDL_WKUP_DMSC0_0_MemEntries[SDL_WKUP_DMSC0_0_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162759
SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_groupEntries[SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_CSI_TX_IF_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:45980
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_CBASS_CH_RINGACC0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:16498
SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_MAIN_RC_ECC_AGGR0_J7_RC_CFG_CBASS_IMSRAM32KX256E_MAIN_0_CFG_P2P_BRIDGE_IMSRAM32KX256E_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:109454
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB1_BR_SOCMF1_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:42625
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_FW_CBASS_MCU_0_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_J7_MCU_FW_CBASS_CBASS_LPSC_MCU_COMMON_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:160944
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_VIRTSS_CFG_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:32593
SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR_J7_WKUP_CBASS_WKUP_0_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_J7_WKUP_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:51209
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_PSILSS_TR_L2P_VPAC_TC0_CC_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:12092
SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_NBSS_ECC_AGGR0_NAVSS512L_NBSS_NB0_BR_SOCMF0_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41364
SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_CBASS_ECC_AGGR0_J7_MAIN_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:75231
SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_groupEntries[SDL_NAVSS0_VIRTSS_ECC_AGGR0_NAVSS512L_VIRTSS_DATA_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:39869
SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_groupEntries[SDL_MCU_CBASS_ECC_AGGR0_J7_MCU_CBASS_MCU_0_J7_MCU_CBASS_MCU_SYSCLK0_6_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_6_BUSECC_2_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:160091
SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:72
SDL_I3C0_I3C_P_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_I3C0_I3C_P_ECC_AGGR_RamIdTable[SDL_I3C0_I3C_P_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:178681
SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_groupEntries[SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_MSMC_J7ES_DMSC_WRAP_CBASS_CBASS_VBUSP_DRU_MMR_FW_P2P_BRIDGE_CORE_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:121395
SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_NAVSS0_UDMASS_ECC_AGGR0_NAVSS512L_UDMASS_CBASS_DMA_MST2_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:14849
SDL_WKUP_DMSC0_IDRAM1_BUSECC_groupEntries
static const SDL_GrpChkConfig_t SDL_WKUP_DMSC0_IDRAM1_BUSECC_groupEntries[SDL_WKUP_DMSC0_IDRAM1_BUSECC_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:162845
SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:162634
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_SEC_PROXY0_CFG_FW_CH_VBUSP_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:59448
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries
static const SDL_GrpChkConfig_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_groupEntries[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NAVSS_MCU_J7_MODSS_CBASS_CBASS_CH_SEC_PROXY0_SRC_MMRS_P2P_BRIDGE_CORE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:61665
SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries
static const SDL_GrpChkConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_groupEntries[SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_MAX_NUM_CHECKERS]
Definition: sdl_ecc_soc.h:41186
SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_RamIdTable[SDL_MCU_NAVSS0_MODSS_ECC_AGGR0_NUM_RAMS]
Definition: sdl_ecc_soc.h:177176